xf86-video-intel 2.2.0

5 files changed, 1250 insertions, 0 deletions

diff --git a/driver/xf86-video-intel/src/ivch/Makefile.am b/driver/xf86-video-intel/src/ivch/Makefile.am
new file mode 100644
index 000000000..1dc9cb352
--- /dev/null
+++ b/driver/xf86-video-intel/src/ivch/Makefile.am
@@ -0,0 +1,15 @@
+# this is obnoxious:
+# -module lets us name the module exactly how we want
+# -avoid-version prevents gratuitous .0.0.0 version numbers on the end
+# _ladir passes a dummy rpath to libtool so the thing will actually link
+# TODO: -nostdlib/-Bstatic/-lgcc platform magic, not installing the .a, etc.
+AM_CFLAGS = @WARN_CFLAGS@ @XMODES_CFLAGS@ @XORG_CFLAGS@ @DRI_CFLAGS@
+
+ivch_la_LTLIBRARIES = ivch.la
+ivch_la_LDFLAGS = -module -avoid-version
+ivch_ladir = @moduledir@/drivers
+
+ivch_la_SOURCES = \
+	ivch.c \
+	ivch_module.c \
+	ivch_reg.h
diff --git a/driver/xf86-video-intel/src/ivch/Makefile.in b/driver/xf86-video-intel/src/ivch/Makefile.in
new file mode 100644
index 000000000..231d3d2c3
--- /dev/null
+++ b/driver/xf86-video-intel/src/ivch/Makefile.in
@@ -0,0 +1,511 @@
+# Makefile.in generated by automake 1.10 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+# 2003, 2004, 2005, 2006  Free Software Foundation, Inc.
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
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+	install-html-am install-info install-info-am \
+	install-ivch_laLTLIBRARIES install-man install-pdf \
+	install-pdf-am install-ps install-ps-am install-strip \
+	installcheck installcheck-am installdirs maintainer-clean \
+	maintainer-clean-generic mostlyclean mostlyclean-compile \
+	mostlyclean-generic mostlyclean-libtool pdf pdf-am ps ps-am \
+	tags uninstall uninstall-am uninstall-ivch_laLTLIBRARIES
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/driver/xf86-video-intel/src/ivch/ivch.c b/driver/xf86-video-intel/src/ivch/ivch.c
new file mode 100644
index 000000000..ac57ff3af
--- /dev/null
+++ b/driver/xf86-video-intel/src/ivch/ivch.c
@@ -0,0 +1,369 @@
+/*
+ * Copyright © 2006 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Eric Anholt <eric@anholt.net>
+ *
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "xf86.h"
+#include "xf86_OSproc.h"
+#include "xf86Resources.h"
+#include "compiler.h"
+#include "miscstruct.h"
+#include "xf86i2c.h"
+#include "xf86Crtc.h"
+#define DPMS_SERVER
+#include <X11/extensions/dpms.h>
+#include <unistd.h>
+
+#include "../i2c_vid.h"
+#include "../i830_bios.h"
+#include "ivch_reg.h"
+
+struct ivch_priv {
+    I2CDevRec	    d;
+
+    xf86OutputPtr   output;
+    Bool quiet;
+
+    CARD16    	    width;
+    CARD16    	    height;
+
+    CARD16	    save_VR01;
+    CARD16	    save_VR40;
+};
+
+struct vch_capabilities {
+    struct aimdb_block	aimdb_block;
+    CARD8		panel_type;
+    CARD8		set_panel_type;
+    CARD8		slave_address;
+    CARD8		capabilities;
+#define VCH_PANEL_FITTING_SUPPORT	(0x3 << 0)
+#define VCH_PANEL_FITTING_TEXT		(1 << 2)
+#define VCH_PANEL_FITTING_GRAPHICS	(1 << 3)
+#define VCH_PANEL_FITTING_RATIO		(1 << 4)
+#define VCH_DITHERING			(1 << 5)
+    CARD8		backlight_gpio;
+    CARD8		set_panel_type_us_gpios;
+} __attribute__ ((packed));
+
+static void
+ivch_dump_regs(I2CDevPtr d);
+
+/**
+ * Reads a register on the ivch.
+ *
+ * Each of the 256 registers are 16 bits long.
+ */
+static Bool
+ivch_read(struct ivch_priv *priv, int addr, CARD16 *data)
+{
+    I2CBusPtr b = priv->d.pI2CBus;
+    I2CByte *p = (I2CByte *) data;
+
+    if (!b->I2CStart(b, priv->d.StartTimeout))
+	goto fail;
+
+    if (!b->I2CPutByte(&priv->d, priv->d.SlaveAddr | 1))
+	goto fail;
+
+    if (!b->I2CPutByte(&priv->d, addr))
+	goto fail;
+
+    if (!b->I2CGetByte(&priv->d, p++, FALSE))
+	goto fail;
+
+    if (!b->I2CGetByte(&priv->d, p++, TRUE))
+	goto fail;
+
+    b->I2CStop(&priv->d);
+
+    return TRUE;
+
+ fail:
+    if (!priv->quiet) {
+	xf86DrvMsg(priv->d.pI2CBus->scrnIndex, X_ERROR,
+		   "ivch: Unable to read register 0x%02x from %s:%02x.\n",
+		   addr, priv->d.pI2CBus->BusName, priv->d.SlaveAddr);
+    }
+    b->I2CStop(&priv->d);
+
+    return FALSE;
+}
+ 
+/** Writes a 16-bit register on the ivch */
+static Bool
+ivch_write(struct ivch_priv *priv, int addr, CARD16 data)
+{
+    I2CBusPtr b = priv->d.pI2CBus;
+
+    if (!b->I2CStart(b, priv->d.StartTimeout))
+	goto fail;
+
+    if (!b->I2CPutByte(&priv->d, priv->d.SlaveAddr))
+	goto fail;
+
+    if (!b->I2CPutByte(&priv->d, addr))
+	goto fail;
+
+    if (!b->I2CPutByte(&priv->d, data & 0xff))
+	goto fail;
+
+    if (!b->I2CPutByte(&priv->d, data >> 8))
+	goto fail;
+
+    b->I2CStop(&priv->d);
+
+    return TRUE;
+
+ fail:
+    b->I2CStop(&priv->d);
+
+    if (!priv->quiet) {
+	xf86DrvMsg(priv->d.pI2CBus->scrnIndex, X_ERROR,
+		   "Unable to write register 0x%02x to %s:%d.\n",
+		   addr, priv->d.pI2CBus->BusName, priv->d.SlaveAddr);
+    }
+
+    return FALSE;
+}
+
+/** Probes the given bus and slave address for an ivch */
+static void *
+ivch_init(I2CBusPtr b, I2CSlaveAddr addr)
+{
+    struct	ivch_priv *priv;
+    CARD16	temp;
+
+    priv = xcalloc(1, sizeof(struct ivch_priv));
+    if (priv == NULL)
+	return NULL;
+
+    priv->output = NULL;
+    priv->d.DevName = "i82807aa \"ivch\" LVDS/CMOS panel controller";
+    priv->d.SlaveAddr = addr;
+    priv->d.pI2CBus = b;
+    priv->d.StartTimeout = b->StartTimeout;
+    priv->d.BitTimeout = b->BitTimeout;
+    priv->d.AcknTimeout = b->AcknTimeout;
+    priv->d.ByteTimeout = b->ByteTimeout;
+    priv->d.DriverPrivate.ptr = priv;
+    priv->quiet = TRUE;
+
+    if (!ivch_read(priv, VR00, &temp))
+	goto out;
+    priv->quiet = FALSE;
+
+    /* Since the identification bits are probably zeroes, which doesn't seem
+     * very unique, check that the value in the base address field matches
+     * the address it's responding on.
+     */
+    if ((temp & VR00_BASE_ADDRESS_MASK) != (priv->d.SlaveAddr >> 1)) {
+	xf86DrvMsg(priv->d.pI2CBus->scrnIndex, X_ERROR,
+		   "ivch detect failed due to address mismatch "
+		   "(%d vs %d)\n",
+		   (temp & VR00_BASE_ADDRESS_MASK), priv->d.SlaveAddr >> 1);
+    }
+
+    if (!xf86I2CDevInit(&priv->d)) {
+	goto out;
+    }
+
+    ivch_read(priv, VR20, &priv->width);
+    ivch_read(priv, VR21, &priv->height);
+
+    return priv;
+
+out:
+    xfree(priv);
+    return NULL;
+}
+
+static xf86OutputStatus
+ivch_detect(I2CDevPtr d)
+{
+    return XF86OutputStatusConnected;
+}
+
+static ModeStatus
+ivch_mode_valid(I2CDevPtr d, DisplayModePtr mode)
+{
+    if (mode->Clock > 112000)
+	return MODE_CLOCK_HIGH;
+
+    return MODE_OK;
+}
+
+/** Sets the power state of the panel connected to the ivch */
+static void
+ivch_dpms(I2CDevPtr d, int mode)
+{
+    struct ivch_priv *priv = d->DriverPrivate.ptr;
+    int i;
+    CARD16 vr01, vr30, backlight;
+
+    /* Set the new power state of the panel. */
+    if (!ivch_read(priv, VR01, &vr01))
+	return;
+
+    if (mode == DPMSModeOn)
+	backlight = 1;
+    else
+	backlight = 0;
+    ivch_write(priv, VR80, backlight);
+    
+    if (mode == DPMSModeOn)
+	vr01 |= VR01_LCD_ENABLE | VR01_DVO_ENABLE;
+    else
+	vr01 &= ~(VR01_LCD_ENABLE | VR01_DVO_ENABLE);
+
+    ivch_write(priv, VR01, vr01);
+
+    /* Wait for the panel to make its state transition */
+    for (i = 0; i < 100; i++) {
+	if (!ivch_read(priv, VR30, &vr30))
+	    break;
+
+	if (((vr30 & VR30_PANEL_ON) != 0) == (mode == DPMSModeOn))
+	    break;
+	usleep (1000);
+    }
+    /* And wait some more; without this, the vch fails to resync sometimes */
+    usleep (16 * 1000);
+}
+
+static void
+ivch_mode_set(I2CDevPtr d, DisplayModePtr mode, DisplayModePtr adjusted_mode)
+{
+    struct ivch_priv	*priv = d->DriverPrivate.ptr;
+    CARD16		vr40 = 0;
+    CARD16		vr01;
+
+    vr01 = 0;
+    vr40 = (VR40_STALL_ENABLE |
+	    VR40_VERTICAL_INTERP_ENABLE |
+	    VR40_HORIZONTAL_INTERP_ENABLE);
+    
+    if (mode->HDisplay != adjusted_mode->HDisplay || 
+	mode->VDisplay != adjusted_mode->VDisplay)
+    {
+	CARD16	x_ratio, y_ratio;
+	
+	vr01 |= VR01_PANEL_FIT_ENABLE;
+	vr40 |= VR40_CLOCK_GATING_ENABLE;
+	x_ratio = (((mode->HDisplay - 1) << 16) / (adjusted_mode->HDisplay - 1)) >> 2;
+	y_ratio = (((mode->VDisplay - 1) << 16) / (adjusted_mode->VDisplay - 1)) >> 2;
+	ivch_write (priv, VR42, x_ratio);
+	ivch_write (priv, VR41, y_ratio);
+    }
+    else
+    {
+	vr01 &= ~VR01_PANEL_FIT_ENABLE;
+	vr40 &= ~VR40_CLOCK_GATING_ENABLE;
+    }
+    vr40 &= ~VR40_AUTO_RATIO_ENABLE;
+
+    ivch_write(priv, VR01, vr01);
+    ivch_write(priv, VR40, vr40);
+
+    ivch_dump_regs(d);
+}
+
+static void
+ivch_dump_regs(I2CDevPtr d)
+{
+    struct ivch_priv *priv = d->DriverPrivate.ptr;
+    CARD16 val;
+
+    ivch_read(priv, VR00, &val);
+    xf86DrvMsg(priv->d.pI2CBus->scrnIndex, X_INFO, "VR00: 0x%04x\n", val);
+    ivch_read(priv, VR01, &val);
+    xf86DrvMsg(priv->d.pI2CBus->scrnIndex, X_INFO, "VR01: 0x%04x\n", val);
+    ivch_read(priv, VR30, &val);
+    xf86DrvMsg(priv->d.pI2CBus->scrnIndex, X_INFO, "VR30: 0x%04x\n", val);
+    ivch_read(priv, VR40, &val);
+    xf86DrvMsg(priv->d.pI2CBus->scrnIndex, X_INFO, "VR40: 0x%04x\n", val);
+
+    /* GPIO registers */
+    ivch_read(priv, VR80, &val);
+    xf86DrvMsg(priv->d.pI2CBus->scrnIndex, X_INFO, "VR80: 0x%04x\n", val);
+    ivch_read(priv, VR81, &val);
+    xf86DrvMsg(priv->d.pI2CBus->scrnIndex, X_INFO, "VR81: 0x%04x\n", val);
+    ivch_read(priv, VR82, &val);
+    xf86DrvMsg(priv->d.pI2CBus->scrnIndex, X_INFO, "VR82: 0x%04x\n", val);
+    ivch_read(priv, VR83, &val);
+    xf86DrvMsg(priv->d.pI2CBus->scrnIndex, X_INFO, "VR83: 0x%04x\n", val);
+    ivch_read(priv, VR84, &val);
+    xf86DrvMsg(priv->d.pI2CBus->scrnIndex, X_INFO, "VR84: 0x%04x\n", val);
+    ivch_read(priv, VR85, &val);
+    xf86DrvMsg(priv->d.pI2CBus->scrnIndex, X_INFO, "VR85: 0x%04x\n", val);
+    ivch_read(priv, VR86, &val);
+    xf86DrvMsg(priv->d.pI2CBus->scrnIndex, X_INFO, "VR86: 0x%04x\n", val);
+    ivch_read(priv, VR87, &val);
+    xf86DrvMsg(priv->d.pI2CBus->scrnIndex, X_INFO, "VR87: 0x%04x\n", val);
+    ivch_read(priv, VR88, &val);
+    xf86DrvMsg(priv->d.pI2CBus->scrnIndex, X_INFO, "VR88: 0x%04x\n", val);
+
+    /* Scratch register 0 - AIM Panel type */
+    ivch_read(priv, VR8E, &val);
+    xf86DrvMsg(priv->d.pI2CBus->scrnIndex, X_INFO, "VR8E: 0x%04x\n", val);
+
+    /* Scratch register 1 - Status register */
+    ivch_read(priv, VR8F, &val);
+    xf86DrvMsg(priv->d.pI2CBus->scrnIndex, X_INFO, "VR8F: 0x%04x\n", val);
+}
+
+static void
+ivch_save(I2CDevPtr d)
+{
+    struct ivch_priv *priv = d->DriverPrivate.ptr;
+
+    ivch_read(priv, VR01, &priv->save_VR01);
+    ivch_read(priv, VR40, &priv->save_VR40);
+}
+
+static void
+ivch_restore(I2CDevPtr d)
+{
+    struct ivch_priv *priv = d->DriverPrivate.ptr;
+
+    ivch_write(priv, VR01, priv->save_VR01);
+    ivch_write(priv, VR40, priv->save_VR40);
+}
+
+
+I830I2CVidOutputRec ivch_methods = {
+    .init = ivch_init,
+    .dpms = ivch_dpms,
+    .save = ivch_save,
+    .restore = ivch_restore,
+    .mode_valid = ivch_mode_valid,
+    .mode_set = ivch_mode_set,
+    .detect = ivch_detect,
+    .dump_regs = ivch_dump_regs,
+};
diff --git a/driver/xf86-video-intel/src/ivch/ivch_module.c b/driver/xf86-video-intel/src/ivch/ivch_module.c
new file mode 100644
index 000000000..1ed483b12
--- /dev/null
+++ b/driver/xf86-video-intel/src/ivch/ivch_module.c
@@ -0,0 +1,64 @@
+/* -*- c-basic-offset: 4 -*- */
+/*
+ * Copyright © 2006 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Eric Anholt <eric@anholt.net>
+ *
+ */
+
+#ifdef HAVE_XORG_CONFIG_H
+#include <xorg-config.h>
+#endif
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "xf86Module.h"
+
+static MODULESETUPPROTO(ivch_setup);
+
+static XF86ModuleVersionInfo ivch_version = {
+    "ivch",
+    MODULEVENDORSTRING,
+    MODINFOSTRING1,
+    MODINFOSTRING2,
+    XORG_VERSION_CURRENT,
+    1, 0, 0,
+    ABI_CLASS_VIDEODRV,
+    ABI_VIDEODRV_VERSION,
+    MOD_CLASS_NONE,
+    { 0,0,0,0 }
+};
+
+_X_EXPORT XF86ModuleData ivchModuleData = {
+    &ivch_version,
+    ivch_setup,
+    NULL
+};
+
+static pointer
+ivch_setup(pointer module, pointer opts, int *errmaj, int *errmin)
+{
+    return (pointer)1;
+}
diff --git a/driver/xf86-video-intel/src/ivch/ivch_reg.h b/driver/xf86-video-intel/src/ivch/ivch_reg.h
new file mode 100644
index 000000000..bcd8c56a3
--- /dev/null
+++ b/driver/xf86-video-intel/src/ivch/ivch_reg.h
@@ -0,0 +1,291 @@
+/* -*- c-basic-offset: 4 -*- */
+/*
+ * Copyright © 2006 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Eric Anholt <eric@anholt.net>
+ *
+ */
+
+/** @file
+ * This file contains the register definitions for the i82807aa.
+ *
+ * Documentation on this chipset can be found in datasheet #29069001 at
+ * intel.com.
+ */
+#ifndef I82807AA_REG_H
+#define I82807AA_REG_H
+
+/** @defgroup VR00 VCH Revision & GMBus Base Addr
+ * @{
+ */
+#define VR00		0x00
+# define VR00_BASE_ADDRESS_MASK		0x007f
+/** @} */
+
+/** @defgroup VR01 VCH Functionality Enable
+ * @{
+ */
+#define VR01		0x01
+/**
+ * Enable the panel fitter
+ */
+# define VR01_PANEL_FIT_ENABLE		(1 << 3)
+/**
+ * Enables the LCD display.
+ *
+ * This must not be set while VR01_DVO_BYPASS_ENABLE is set.
+ */
+# define VR01_LCD_ENABLE		(1 << 2)
+/** Enables the DVO repeater. */
+# define VR01_DVO_BYPASS_ENABLE		(1 << 1)
+/** Enables the DVO clock */
+# define VR01_DVO_ENABLE		(1 << 0)
+/** @} */
+
+/** @defgroup VR10 LCD Interface Format
+ * @{
+ */
+#define VR10		0x10
+/** Enables LVDS output instead of CMOS */
+# define VR10_LVDS_ENABLE		(1 << 4)
+/** Enables 18-bit LVDS output. */
+# define VR10_INTERFACE_1X18		(0 << 2)
+/** Enables 24-bit LVDS or CMOS output */
+# define VR10_INTERFACE_1X24		(1 << 2)
+/** Enables 2x18-bit LVDS or CMOS output. */
+# define VR10_INTERFACE_2X18		(2 << 2)
+/** Enables 2x24-bit LVDS output */
+# define VR10_INTERFACE_2X24		(3 << 2)
+/** @} */
+
+/** @defgroup VR11 CMOS Output Control
+ * @{
+ */
+/** @} */
+
+/** @defgroup VR12 LVDS Output Control
+ * @{
+ */
+/** @} */
+
+/** @defgroup VR18 PLL clock select
+ * @{
+ */
+/** @} */
+
+/** @defgroup VR19 PLL clock divisor M
+ * @{
+ */
+/** @} */
+
+/** @defgroup VR1A PLL clock divisor N
+ * @{
+ */
+/** @} */
+
+/** @defgroup VR1F FIFO Pre-load
+ * @{
+ */
+/** @} */
+
+/** @defgroup VR20 LCD Horizontal Display Size
+ * @{
+ */
+#define VR20	0x20
+/** @} */
+
+/** @defgroup VR21 LCD Vertical Display Size
+ * @{
+ */
+#define VR21	0x20
+/** @} */
+
+/** @defgroup VR22 Horizontal TRP to DE Start Delay
+ * @{
+ */
+/** @} */
+
+/** @defgroup VR23 Horizontal TRP to DE End Delay
+ * @{
+ */
+/** @} */
+
+/** @defgroup VR24 Horizontal TRP To LP Start Delay
+ * @{
+ */
+/** @} */
+
+/** @defgroup VR25 Horizontal TRP To LP End Delay
+ * @{
+ */
+/** @} */
+
+/** @defgroup VR26 Vertical TRP To FLM Start Delay
+ * @{
+ */
+/** @} */
+
+/** @defgroup VR27 Vertical TRP To FLM End Delay
+ * @{
+ */
+/** @} */
+
+/** @defgroup VR30 Panel power down status
+ * @{
+ */
+#define VR30		0x30
+/** Read only bit indicating that the panel is not in a safe poweroff state. */
+# define VR30_PANEL_ON			(1 << 15)
+/** @} */
+
+/** @defgroup VR31 Tpon Panel power on sequencing delay
+ * @{
+ */
+/** @} */
+
+/** @defgroup VR32 Tpon Panel power off sequencing delay
+ * @{
+ */
+/** @} */
+
+/** @defgroup VR33 Tstay Panel power off stay down delay
+ * @{
+ */
+/** @} */
+
+/** @defgroup VR34 Maximal FLM Pulse Interval
+ * @{
+ */
+/** @} */
+
+/** @defgroup VR35 Maximal LP Pulse Interval
+ * @{
+ */
+/** @} */
+
+/** @defgroup VR40
+ * @{
+ */
+#define VR40		0x40
+# define VR40_STALL_ENABLE		(1 << 13)
+# define VR40_VERTICAL_INTERP_ENABLE	(1 << 12)
+# define VR40_ENHANCED_PANEL_FITTING	(1 << 11)
+# define VR40_HORIZONTAL_INTERP_ENABLE	(1 << 10)
+# define VR40_AUTO_RATIO_ENABLE		(1 << 9)
+# define VR40_CLOCK_GATING_ENABLE	(1 << 8)
+/** @} */
+
+/** @defgroup VR41 Panel Fitting Vertical Ratio
+ * @{
+ *
+ * (((image_height - 1) << 16) / ((panel_height - 1))) >> 2
+ */
+/** @} */
+#define VR41		0x41
+
+/** @defgroup VR42 Panel Fitting Horizontal Ratio
+ * @{
+ * (((image_width - 1) << 16) / ((panel_width - 1))) >> 2
+ */
+/** @} */
+#define VR42		0x42
+
+/** @defgroup VR43 Horizontal Image Size
+ * @{
+ */
+/** @} */
+#define VR43		0x43
+
+/** @defgroup VR44 Panel Fitting Coefficient 0
+ * @{
+ */
+/** @} */
+
+/** @defgroup VR45 Panel Fitting Coefficient 1
+ * @{
+ */
+/** @} */
+
+/** @defgroup VR46 Panel Fitting Coefficient 2
+ * @{
+ */
+/** @} */
+
+/** @defgroup VR47 Panel Fitting Coefficient 3
+ * @{
+ */
+/** @} */
+
+/** @defgroup VR48 Panel Fitting Coefficient 4
+ * @{
+ */
+/** @} */
+
+/** @defgroup VR49 Panel Fitting Coefficient 5
+ * @{
+ */
+/** @} */
+
+/** @defgroup VR80 GPIO 0
+ * @{
+ */
+/** @} */
+
+#define VR80	    0x80
+#define VR81	    0x81
+#define VR82	    0x82
+#define VR83	    0x83
+#define VR84	    0x84
+#define VR85	    0x85
+#define VR86	    0x86
+#define VR87	    0x87
+    
+/** @defgroup VR88 GPIO 8
+ * @{
+ */
+/** @} */
+
+#define VR88	    0x88
+
+/** @defgroup VR8E Graphics BIOS scratch 0
+ * @{
+ */
+#define VR8E	    0x8E
+# define VR8E_PANEL_TYPE_MASK		(0xf << 0)
+# define VR8E_PANEL_INTERFACE_CMOS	(0 << 4)
+# define VR8E_PANEL_INTERFACE_LVDS	(1 << 4)
+# define VR8E_FORCE_DEFAULT_PANEL	(1 << 5)
+/** @} */
+
+/** @defgroup VR8F Graphics BIOS scratch 1
+ * @{
+ */
+#define VR8F	    0x8F
+# define VR8F_VCH_PRESENT		(1 << 0)
+# define VR8F_DISPLAY_CONN		(1 << 1)
+# define VR8F_POWER_MASK		(0x3c)
+# define VR8F_POWER_POS			(2)
+/** @} */
+
+
+#endif /* I82807AA_REG_H */