diff options
| author | Owain Ainsworth <oga@cvs.openbsd.org> | 2011-11-29 12:39:04 +0000 |
|---|---|---|
| committer | Owain Ainsworth <oga@cvs.openbsd.org> | 2011-11-29 12:39:04 +0000 |
| commit | c2c12b91aa8ce17ebc41929142803a0c4ccac20d (patch) | |
| tree | e53e5be67ebf6695aed2b89659c4eb36db02de30 /driver | |
| parent | 40e8fc6d789367334ea8d8eeaf00f5f749b81f95 (diff) | |
Update the intel driver to a more recent version based on more recent
upsteam code.
Backporting keeping UMS changes by me, some bugfixes from kettenis@.
Has been in snapshots for a while, committed on request so we can be
sure what people are running. This is a prerequesite for sandybridge
support but has those chipsets disabled for now until the correct code
has been added.
Diffstat (limited to 'driver')
168 files changed, 14525 insertions, 7557 deletions
diff --git a/driver/xf86-video-intel/Makefile.in b/driver/xf86-video-intel/Makefile.in index 0e5cfce5a..e39107871 100644 --- a/driver/xf86-video-intel/Makefile.in +++ b/driver/xf86-video-intel/Makefile.in @@ -106,10 +106,6 @@ AUTOCONF = @AUTOCONF@ AUTOHEADER = @AUTOHEADER@ AUTOMAKE = @AUTOMAKE@ AWK = @AWK@ -BUILD_LINUXDOC_FALSE = @BUILD_LINUXDOC_FALSE@ -BUILD_LINUXDOC_TRUE = @BUILD_LINUXDOC_TRUE@ -BUILD_PDFDOC_FALSE = @BUILD_PDFDOC_FALSE@ -BUILD_PDFDOC_TRUE = @BUILD_PDFDOC_TRUE@ CC = @CC@ CCDEPMODE = @CCDEPMODE@ CFLAGS = @CFLAGS@ @@ -149,8 +145,6 @@ GEN4ASM_LIBS = @GEN4ASM_LIBS@ GREP = @GREP@ HAVE_GEN4ASM_FALSE = @HAVE_GEN4ASM_FALSE@ HAVE_GEN4ASM_TRUE = @HAVE_GEN4ASM_TRUE@ -HAVE_XEXTPROTO_71_FALSE = @HAVE_XEXTPROTO_71_FALSE@ -HAVE_XEXTPROTO_71_TRUE = @HAVE_XEXTPROTO_71_TRUE@ INSTALL_CMD = @INSTALL_CMD@ INSTALL_DATA = @INSTALL_DATA@ INSTALL_PROGRAM = @INSTALL_PROGRAM@ @@ -164,17 +158,13 @@ LIBS = @LIBS@ LIBTOOL = @LIBTOOL@ LIB_MAN_DIR = @LIB_MAN_DIR@ LIB_MAN_SUFFIX = @LIB_MAN_SUFFIX@ -LINUXDOC = @LINUXDOC@ LN_S = @LN_S@ LTLIBOBJS = @LTLIBOBJS@ MAINT = @MAINT@ MAINTAINER_MODE_FALSE = @MAINTAINER_MODE_FALSE@ MAINTAINER_MODE_TRUE = @MAINTAINER_MODE_TRUE@ MAKEINFO = @MAKEINFO@ -MAKE_HTML = @MAKE_HTML@ -MAKE_PDF = @MAKE_PDF@ -MAKE_PS = @MAKE_PS@ -MAKE_TEXT = @MAKE_TEXT@ +MAN_SUBSTS = @MAN_SUBSTS@ MISC_MAN_DIR = @MISC_MAN_DIR@ MISC_MAN_SUFFIX = @MISC_MAN_SUFFIX@ NMEDIT = @NMEDIT@ @@ -189,19 +179,15 @@ PATH_SEPARATOR = @PATH_SEPARATOR@ PCIACCESS_CFLAGS = @PCIACCESS_CFLAGS@ PCIACCESS_LIBS = @PCIACCESS_LIBS@ PKG_CONFIG = @PKG_CONFIG@ -PS2PDF = @PS2PDF@ RANLIB = @RANLIB@ SED = @SED@ SET_MAKE = @SET_MAKE@ SHELL = @SHELL@ STRIP = @STRIP@ VERSION = @VERSION@ -VIDEO_DEBUG_FALSE = @VIDEO_DEBUG_FALSE@ -VIDEO_DEBUG_TRUE = @VIDEO_DEBUG_TRUE@ -XEXT_CFLAGS = @XEXT_CFLAGS@ -XEXT_LIBS = @XEXT_LIBS@ XORG_CFLAGS = @XORG_CFLAGS@ XORG_LIBS = @XORG_LIBS@ +XORG_MAN_PAGE = @XORG_MAN_PAGE@ XVMCLIB_CFLAGS = @XVMCLIB_CFLAGS@ XVMCLIB_LIBS = @XVMCLIB_LIBS@ XVMC_FALSE = @XVMC_FALSE@ diff --git a/driver/xf86-video-intel/aclocal.m4 b/driver/xf86-video-intel/aclocal.m4 index 4d51d7e87..a67713050 100644 --- a/driver/xf86-video-intel/aclocal.m4 +++ b/driver/xf86-video-intel/aclocal.m4 @@ -7698,7 +7698,7 @@ dnl DEALINGS IN THE SOFTWARE. # See the "minimum version" comment for each macro you use to see what # version you require. m4_defun([XORG_MACROS_VERSION],[ -m4_define([vers_have], [1.6.1]) +m4_define([vers_have], [1.10.0]) m4_define([maj_have], m4_substr(vers_have, 0, m4_index(vers_have, [.]))) m4_define([maj_needed], m4_substr([$1], 0, m4_index([$1], [.]))) m4_if(m4_cmp(maj_have, maj_needed), 0,, @@ -7766,9 +7766,12 @@ AC_SUBST(RAWCPPFLAGS) # on this OS - replaces *ManSuffix settings in old Imake *.cf per-os files. # Not sure if there's any better way than just hardcoding by OS name. # Override default settings by setting environment variables +# Added MAN_SUBSTS in version 1.8 +# Added AC_PROG_SED in version 1.8 AC_DEFUN([XORG_MANPAGE_SECTIONS],[ AC_REQUIRE([AC_CANONICAL_HOST]) +AC_REQUIRE([AC_PROG_SED]) if test x$APP_MAN_SUFFIX = x ; then APP_MAN_SUFFIX=1 @@ -7837,8 +7840,59 @@ AC_SUBST([FILE_MAN_DIR]) AC_SUBST([MISC_MAN_DIR]) AC_SUBST([DRIVER_MAN_DIR]) AC_SUBST([ADMIN_MAN_DIR]) + +XORG_MAN_PAGE="X Version 11" +AC_SUBST([XORG_MAN_PAGE]) +MAN_SUBSTS="\ + -e 's|__vendorversion__|\"\$(PACKAGE_STRING)\" \"\$(XORG_MAN_PAGE)\"|' \ + -e 's|__xorgversion__|\"\$(PACKAGE_STRING)\" \"\$(XORG_MAN_PAGE)\"|' \ + -e 's|__xservername__|Xorg|g' \ + -e 's|__xconfigfile__|xorg.conf|g' \ + -e 's|__projectroot__|\$(prefix)|g' \ + -e 's|__appmansuffix__|\$(APP_MAN_SUFFIX)|g' \ + -e 's|__drivermansuffix__|\$(DRIVER_MAN_SUFFIX)|g' \ + -e 's|__adminmansuffix__|\$(ADMIN_MAN_SUFFIX)|g' \ + -e 's|__libmansuffix__|\$(LIB_MAN_SUFFIX)|g' \ + -e 's|__miscmansuffix__|\$(MISC_MAN_SUFFIX)|g' \ + -e 's|__filemansuffix__|\$(FILE_MAN_SUFFIX)|g'" +AC_SUBST([MAN_SUBSTS]) + ]) # XORG_MANPAGE_SECTIONS +# XORG_CHECK_SGML_DOCTOOLS([MIN-VERSION]) +# ------------------------ +# Minimum version: 1.7.0 +# +# Defines the variable XORG_SGML_PATH containing the location of X11/defs.ent +# provided by xorg-sgml-doctools, if installed. +AC_DEFUN([XORG_CHECK_SGML_DOCTOOLS],[ +AC_MSG_CHECKING([for X.Org SGML entities m4_ifval([$1],[>= $1])]) +XORG_SGML_PATH= +PKG_CHECK_EXISTS([xorg-sgml-doctools m4_ifval([$1],[>= $1])], + [XORG_SGML_PATH=`$PKG_CONFIG --variable=sgmlrootdir xorg-sgml-doctools`], + [m4_ifval([$1],[:], + [if test x"$cross_compiling" != x"yes" ; then + AC_CHECK_FILE([$prefix/share/sgml/X11/defs.ent], + [XORG_SGML_PATH=$prefix/share/sgml]) + fi]) + ]) + +# Define variables STYLESHEET_SRCDIR and XSL_STYLESHEET containing +# the path and the name of the doc stylesheet +if test "x$XORG_SGML_PATH" != "x" ; then + AC_MSG_RESULT([$XORG_SGML_PATH]) + STYLESHEET_SRCDIR=$XORG_SGML_PATH/X11 + XSL_STYLESHEET=$STYLESHEET_SRCDIR/xorg.xsl +else + AC_MSG_RESULT([no]) +fi + +AC_SUBST(XORG_SGML_PATH) +AC_SUBST(STYLESHEET_SRCDIR) +AC_SUBST(XSL_STYLESHEET) +AM_CONDITIONAL([HAVE_STYLESHEETS], [test "x$XSL_STYLESHEET" != "x"]) +]) # XORG_CHECK_SGML_DOCTOOLS + # XORG_CHECK_LINUXDOC # ------------------- # Minimum version: 1.0.0 @@ -7848,23 +7902,14 @@ AC_SUBST([ADMIN_MAN_DIR]) # Whether or not the necessary tools and files are found can be checked # with the AM_CONDITIONAL "BUILD_LINUXDOC" AC_DEFUN([XORG_CHECK_LINUXDOC],[ -if test x$XORG_SGML_PATH = x ; then - XORG_SGML_PATH=$prefix/share/sgml -fi -HAVE_DEFS_ENT= - -if test x"$cross_compiling" = x"yes" ; then - HAVE_DEFS_ENT=no -else - AC_CHECK_FILE([$XORG_SGML_PATH/X11/defs.ent], [HAVE_DEFS_ENT=yes]) -fi +AC_REQUIRE([XORG_CHECK_SGML_DOCTOOLS]) +AC_REQUIRE([XORG_WITH_PS2PDF]) AC_PATH_PROG(LINUXDOC, linuxdoc) -AC_PATH_PROG(PS2PDF, ps2pdf) AC_MSG_CHECKING([whether to build documentation]) -if test x$HAVE_DEFS_ENT != x && test x$LINUXDOC != x ; then +if test x$XORG_SGML_PATH != x && test x$LINUXDOC != x ; then BUILDDOC=yes else BUILDDOC=no @@ -7876,7 +7921,7 @@ AC_MSG_RESULT([$BUILDDOC]) AC_MSG_CHECKING([whether to build pdf documentation]) -if test x$PS2PDF != x && test x$BUILD_PDFDOC != xno; then +if test x$have_ps2pdf != xno && test x$BUILD_PDFDOC != xno; then BUILDPDFDOC=yes else BUILDPDFDOC=no @@ -7886,7 +7931,7 @@ AM_CONDITIONAL(BUILD_PDFDOC, [test x$BUILDPDFDOC = xyes]) AC_MSG_RESULT([$BUILDPDFDOC]) -MAKE_TEXT="SGML_SEARCH_PATH=$XORG_SGML_PATH GROFF_NO_SGR=y $LINUXDOC -B txt" +MAKE_TEXT="SGML_SEARCH_PATH=$XORG_SGML_PATH GROFF_NO_SGR=y $LINUXDOC -B txt -f" MAKE_PS="SGML_SEARCH_PATH=$XORG_SGML_PATH $LINUXDOC -B latex --papersize=letter --output=ps" MAKE_PDF="$PS2PDF" MAKE_HTML="SGML_SEARCH_PATH=$XORG_SGML_PATH $LINUXDOC -B html --split=0" @@ -7906,24 +7951,20 @@ AC_SUBST(MAKE_HTML) # indicates whether the necessary tools and files are found and, if set, # $(MAKE_XXX) blah.sgml will produce blah.xxx. AC_DEFUN([XORG_CHECK_DOCBOOK],[ -if test x$XORG_SGML_PATH = x ; then - XORG_SGML_PATH=$prefix/share/sgml -fi -HAVE_DEFS_ENT= +AC_REQUIRE([XORG_CHECK_SGML_DOCTOOLS]) + BUILDTXTDOC=no BUILDPDFDOC=no BUILDPSDOC=no BUILDHTMLDOC=no -AC_CHECK_FILE([$XORG_SGML_PATH/X11/defs.ent], [HAVE_DEFS_ENT=yes]) - AC_PATH_PROG(DOCBOOKPS, docbook2ps) AC_PATH_PROG(DOCBOOKPDF, docbook2pdf) AC_PATH_PROG(DOCBOOKHTML, docbook2html) AC_PATH_PROG(DOCBOOKTXT, docbook2txt) AC_MSG_CHECKING([whether to build text documentation]) -if test x$HAVE_DEFS_ENT != x && test x$DOCBOOKTXT != x && +if test x$XORG_SGML_PATH != x && test x$DOCBOOKTXT != x && test x$BUILD_TXTDOC != xno; then BUILDTXTDOC=yes fi @@ -7931,7 +7972,7 @@ AM_CONDITIONAL(BUILD_TXTDOC, [test x$BUILDTXTDOC = xyes]) AC_MSG_RESULT([$BUILDTXTDOC]) AC_MSG_CHECKING([whether to build PDF documentation]) -if test x$HAVE_DEFS_ENT != x && test x$DOCBOOKPDF != x && +if test x$XORG_SGML_PATH != x && test x$DOCBOOKPDF != x && test x$BUILD_PDFDOC != xno; then BUILDPDFDOC=yes fi @@ -7939,7 +7980,7 @@ AM_CONDITIONAL(BUILD_PDFDOC, [test x$BUILDPDFDOC = xyes]) AC_MSG_RESULT([$BUILDPDFDOC]) AC_MSG_CHECKING([whether to build PostScript documentation]) -if test x$HAVE_DEFS_ENT != x && test x$DOCBOOKPS != x && +if test x$XORG_SGML_PATH != x && test x$DOCBOOKPS != x && test x$BUILD_PSDOC != xno; then BUILDPSDOC=yes fi @@ -7947,7 +7988,7 @@ AM_CONDITIONAL(BUILD_PSDOC, [test x$BUILDPSDOC = xyes]) AC_MSG_RESULT([$BUILDPSDOC]) AC_MSG_CHECKING([whether to build HTML documentation]) -if test x$HAVE_DEFS_ENT != x && test x$DOCBOOKHTML != x && +if test x$XORG_SGML_PATH != x && test x$DOCBOOKHTML != x && test x$BUILD_HTMLDOC != xno; then BUILDHTMLDOC=yes fi @@ -7982,6 +8023,10 @@ AC_SUBST(MAKE_HTML) # --with-xmlto: 'yes' user instructs the module to use xmlto # 'no' user instructs the module not to use xmlto # +# Added in version 1.10.0 +# HAVE_XMLTO_TEXT: used in makefiles to conditionally generate text documentation +# xmlto for text output requires either lynx, links, or w3m browsers +# # If the user sets the value of XMLTO, AC_PATH_PROG skips testing the path. # AC_DEFUN([XORG_WITH_XMLTO],[ @@ -8013,6 +8058,8 @@ elif test "x$use_xmlto" = x"no" ; then else AC_MSG_ERROR([--with-xmlto expects 'yes' or 'no']) fi + +# Test for a minimum version of xmlto, if provided. m4_ifval([$1], [if test "$have_xmlto" = yes; then # scrape the xmlto version @@ -8027,6 +8074,17 @@ m4_ifval([$1], AC_MSG_ERROR([xmlto version $xmlto_version found, but $1 needed]) fi]) fi]) + +# Test for the ability of xmlto to generate a text target +have_xmlto_text=no +cat > conftest.xml << "EOF" +EOF +AS_IF([test "$have_xmlto" = yes], + [AS_IF([$XMLTO --skip-validation txt conftest.xml >/dev/null 2>&1], + [have_xmlto_text=yes], + [AC_MSG_WARN([xmlto cannot generate text format, this format skipped])])]) +rm -f conftest.xml +AM_CONDITIONAL([HAVE_XMLTO_TEXT], [test $have_xmlto_text = yes]) AM_CONDITIONAL([HAVE_XMLTO], [test "$have_xmlto" = yes]) ]) # XORG_WITH_XMLTO @@ -8179,6 +8237,12 @@ AM_CONDITIONAL([HAVE_DOXYGEN], [test "$have_doxygen" = yes]) # --with-groff: 'yes' user instructs the module to use groff # 'no' user instructs the module not to use groff # +# Added in version 1.9.0: +# HAVE_GROFF_HTML: groff has dependencies to output HTML format: +# pnmcut pnmcrop pnmtopng pnmtops from the netpbm package. +# psselect from the psutils package. +# the ghostcript package. Refer to the grohtml man pages +# # If the user sets the value of GROFF, AC_PATH_PROG skips testing the path. # # OS and distros often splits groff in a basic and full package, the former @@ -8218,6 +8282,7 @@ elif test "x$use_groff" = x"no" ; then else AC_MSG_ERROR([--with-groff expects 'yes' or 'no']) fi + # We have groff, test for the presence of the macro packages if test "x$have_groff" = x"yes"; then AC_MSG_CHECKING([for ${GROFF} -ms macros]) @@ -8235,9 +8300,25 @@ if test "x$have_groff" = x"yes"; then fi AC_MSG_RESULT([$groff_mm_works]) fi + +# We have groff, test for HTML dependencies, one command per package +if test "x$have_groff" = x"yes"; then + AC_PATH_PROGS(GS_PATH, [gs gswin32c]) + AC_PATH_PROG(PNMTOPNG_PATH, [pnmtopng]) + AC_PATH_PROG(PSSELECT_PATH, [psselect]) + if test "x$GS_PATH" != "x" -a "x$PNMTOPNG_PATH" != "x" -a "x$PSSELECT_PATH" != "x"; then + have_groff_html=yes + else + have_groff_html=no + AC_MSG_WARN([grohtml dependencies not found - HTML Documentation skipped. Refer to grohtml man pages]) + fi +fi + +# Set Automake conditionals for Makefiles AM_CONDITIONAL([HAVE_GROFF], [test "$have_groff" = yes]) AM_CONDITIONAL([HAVE_GROFF_MS], [test "$groff_ms_works" = yes]) AM_CONDITIONAL([HAVE_GROFF_MM], [test "$groff_mm_works" = yes]) +AM_CONDITIONAL([HAVE_GROFF_HTML], [test "$have_groff_html" = yes]) ]) # XORG_WITH_GROFF # XORG_WITH_FOP @@ -8502,38 +8583,69 @@ AC_SUBST([XTMALLOC_ZERO_CFLAGS]) # ---------------- # Minimum version: 1.1.0 # -# Sets up flags for source checkers such as lint and sparse if --with-lint -# is specified. (Use --with-lint=sparse for sparse.) -# Sets $LINT to name of source checker passed with --with-lint (default: lint) -# Sets $LINT_FLAGS to flags to pass to source checker -# Sets LINT automake conditional if enabled (default: disabled) +# This macro enables the use of a tool that flags some suspicious and +# non-portable constructs (likely to be bugs) in C language source code. +# It will attempt to locate the tool and use appropriate options. +# There are various lint type tools on different platforms. +# +# Interface to module: +# LINT: returns the path to the tool found on the platform +# or the value set to LINT on the configure cmd line +# also an Automake conditional +# LINT_FLAGS: an Automake variable with appropriate flags +# +# --with-lint: 'yes' user instructs the module to use lint +# 'no' user instructs the module not to use lint (default) +# +# If the user sets the value of LINT, AC_PATH_PROG skips testing the path. +# If the user sets the value of LINT_FLAGS, they are used verbatim. # AC_DEFUN([XORG_WITH_LINT],[ -# Allow checking code with lint, sparse, etc. +AC_ARG_VAR([LINT], [Path to a lint-style command]) +AC_ARG_VAR([LINT_FLAGS], [Flags for the lint-style command]) AC_ARG_WITH(lint, [AS_HELP_STRING([--with-lint], [Use a lint-style source code checker (default: disabled)])], [use_lint=$withval], [use_lint=no]) -if test "x$use_lint" = "xyes" ; then - LINT="lint" + +# Obtain platform specific info like program name and options +# The lint program on FreeBSD and NetBSD is different from the one on Solaris +case $host_os in + *linux* | *openbsd* | kfreebsd*-gnu | darwin* | cygwin*) + lint_name=splint + lint_options="-badflag" + ;; + *freebsd* | *netbsd*) + lint_name=lint + lint_options="-u -b" + ;; + *solaris*) + lint_name=lint + lint_options="-u -b -h -erroff=E_INDISTING_FROM_TRUNC2" + ;; +esac + +# Test for the presence of the program (either guessed by the code or spelled out by the user) +if test "x$use_lint" = x"yes" ; then + AC_PATH_PROG([LINT], [$lint_name]) + if test "x$LINT" = "x"; then + AC_MSG_ERROR([--with-lint=yes specified but lint-style tool not found in PATH]) + fi +elif test "x$use_lint" = x"no" ; then + if test "x$LINT" != "x"; then + AC_MSG_WARN([ignoring LINT environment variable since --with-lint=no was specified]) + fi else - LINT="$use_lint" + AC_MSG_ERROR([--with-lint expects 'yes' or 'no'. Use LINT variable to specify path.]) fi -if test "x$LINT_FLAGS" = "x" -a "x$LINT" != "xno" ; then - case $LINT in - lint|*/lint) - case $host_os in - solaris*) - LINT_FLAGS="-u -b -h -erroff=E_INDISTING_FROM_TRUNC2" - ;; - esac - ;; - esac + +# User supplied flags override default flags +if test "x$LINT_FLAGS" != "x"; then + lint_options=$LINT_FLAGS fi -AC_SUBST(LINT) -AC_SUBST(LINT_FLAGS) -AM_CONDITIONAL(LINT, [test x$LINT != xno]) +AC_SUBST([LINT_FLAGS],[$lint_options]) +AM_CONDITIONAL(LINT, [test "x$LINT" != x]) ]) # XORG_WITH_LINT @@ -8543,28 +8655,29 @@ AM_CONDITIONAL(LINT, [test x$LINT != xno]) # # Sets up flags for building lint libraries for checking programs that call # functions in the library. -# Disabled by default, enable with --enable-lint-library -# Sets: -# @LINTLIB@ - name of lint library file to make -# MAKE_LINT_LIB - automake conditional # +# Interface to module: +# LINTLIB - Automake variable with the name of lint library file to make +# MAKE_LINT_LIB - Automake conditional +# +# --enable-lint-library: - 'yes' user instructs the module to created a lint library +# - 'no' user instructs the module not to create a lint library (default) AC_DEFUN([XORG_LINT_LIBRARY],[ AC_REQUIRE([XORG_WITH_LINT]) -# Build lint "library" for more indepth checks of programs calling this library AC_ARG_ENABLE(lint-library, [AS_HELP_STRING([--enable-lint-library], [Create lint library (default: disabled)])], [make_lint_lib=$enableval], [make_lint_lib=no]) -if test "x$make_lint_lib" != "xno" ; then - if test "x$LINT" = "xno" ; then - AC_MSG_ERROR([Cannot make lint library without --with-lint]) - fi - if test "x$make_lint_lib" = "xyes" ; then - LINTLIB=llib-l$1.ln - else - LINTLIB=$make_lint_lib - fi + +if test "x$make_lint_lib" = x"yes" ; then + LINTLIB=llib-l$1.ln + if test "x$LINT" = "x"; then + AC_MSG_ERROR([Cannot make lint library without --with-lint]) + fi +elif test "x$make_lint_lib" != x"no" ; then + AC_MSG_ERROR([--enable-lint-library expects 'yes' or 'no'.]) fi + AC_SUBST(LINTLIB) AM_CONDITIONAL(MAKE_LINT_LIB, [test x$make_lint_lib != xno]) @@ -8577,7 +8690,7 @@ AM_CONDITIONAL(MAKE_LINT_LIB, [test x$make_lint_lib != xno]) # Defines CWARNFLAGS to enable C compiler warnings. # AC_DEFUN([XORG_CWARNFLAGS], [ -AC_REQUIRE([AC_PROG_CC]) +AC_REQUIRE([AC_PROG_CC_C99]) if test "x$GCC" = xyes ; then CWARNFLAGS="-Wall -Wpointer-arith -Wstrict-prototypes -Wmissing-prototypes \ -Wmissing-declarations -Wnested-externs -fno-strict-aliasing \ @@ -8602,7 +8715,7 @@ AC_SUBST(CWARNFLAGS) # # Add configure option to enable strict compilation AC_DEFUN([XORG_STRICT_OPTION], [ -AC_REQUIRE([AC_PROG_CC]) +# If the module's configure.ac calls AC_PROG_CC later on, CC gets set to C89 AC_REQUIRE([AC_PROG_CC_C99]) AC_REQUIRE([XORG_CWARNFLAGS]) @@ -8632,6 +8745,7 @@ AC_SUBST([CWARNFLAGS]) # Defines default options for X.Org modules. # AC_DEFUN([XORG_DEFAULT_OPTIONS], [ +AC_REQUIRE([AC_PROG_INSTALL]) XORG_CWARNFLAGS XORG_STRICT_OPTION XORG_RELEASE_VERSION @@ -8685,22 +8799,9 @@ dnl # XORG_RELEASE_VERSION # -------------------- -# Adds --with/without-release-string and changes the PACKAGE and -# PACKAGE_TARNAME to use "$PACKAGE{_TARNAME}-$RELEASE_VERSION". If -# no option is given, PACKAGE and PACKAGE_TARNAME are unchanged. Also -# defines PACKAGE_VERSION_{MAJOR,MINOR,PATCHLEVEL} for modules to use. +# Defines PACKAGE_VERSION_{MAJOR,MINOR,PATCHLEVEL} for modules to use. AC_DEFUN([XORG_RELEASE_VERSION],[ - AC_ARG_WITH(release-version, - AS_HELP_STRING([--with-release-version=STRING], - [Use release version string in package name]), - [RELEASE_VERSION="$withval"], - [RELEASE_VERSION=""]) - if test "x$RELEASE_VERSION" != "x"; then - PACKAGE="$PACKAGE-$RELEASE_VERSION" - PACKAGE_TARNAME="$PACKAGE_TARNAME-$RELEASE_VERSION" - AC_MSG_NOTICE([Building with package name set to $PACKAGE]) - fi AC_DEFINE_UNQUOTED([PACKAGE_VERSION_MAJOR], [`echo $PACKAGE_VERSION | cut -d . -f 1`], [Major version of this package]) @@ -8767,8 +8868,9 @@ dnl # is defined, then add $1 to $REQUIRED_MODULES. AC_DEFUN([XORG_DRIVER_CHECK_EXT],[ + AC_REQUIRE([PKG_PROG_PKG_CONFIG]) SAVE_CFLAGS="$CFLAGS" - CFLAGS="$CFLAGS -I`pkg-config --variable=sdkdir xorg-server`" + CFLAGS="$CFLAGS -I`$PKG_CONFIG --variable=sdkdir xorg-server`" AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[ #include "xorg-server.h" #if !defined $1 diff --git a/driver/xf86-video-intel/config.h.in b/driver/xf86-video-intel/config.h.in index bc7b00d7a..c35938b25 100644 --- a/driver/xf86-video-intel/config.h.in +++ b/driver/xf86-video-intel/config.h.in @@ -14,9 +14,6 @@ /* Define to 1 if you have the <memory.h> header file. */ #undef HAVE_MEMORY_H -/* Define to 1 if you have the `mprotect' function. */ -#undef HAVE_MPROTECT - /* Define to 1 if you have the <stdint.h> header file. */ #undef HAVE_STDINT_H @@ -29,9 +26,6 @@ /* Define to 1 if you have the <string.h> header file. */ #undef HAVE_STRING_H -/* Define to 1 if you have the <sys/mman.h> header file. */ -#undef HAVE_SYS_MMAN_H - /* Define to 1 if you have the <sys/stat.h> header file. */ #undef HAVE_SYS_STAT_H @@ -41,15 +35,9 @@ /* Define to 1 if you have the <unistd.h> header file. */ #undef HAVE_UNISTD_H -/* xextproto 7.1 available */ -#undef HAVE_XEXTPROTO_71 - /* Assume KMS support */ #undef KMS_ONLY -/* Define to 1 if your C compiler doesn't accept -c and -o together. */ -#undef NO_MINUS_C_MINUS_O - /* Name of package */ #undef PACKAGE @@ -83,9 +71,6 @@ /* Version number of package */ #undef VERSION -/* Enable debug support */ -#undef VIDEO_DEBUG - /* Enable DRI driver support */ #undef XF86DRI diff --git a/driver/xf86-video-intel/configure b/driver/xf86-video-intel/configure index 61176dc4c..e96bd39aa 100644 --- a/driver/xf86-video-intel/configure +++ b/driver/xf86-video-intel/configure @@ -1,6 +1,6 @@ #! /bin/sh # Guess values for system-dependent variables and create Makefiles. -# Generated by GNU Autoconf 2.62 for xf86-video-intel 2.9.1. +# Generated by GNU Autoconf 2.62 for xf86-video-intel 2.12.0. # # Report bugs to <https://bugs.freedesktop.org/enter_bug.cgi?product=xorg>. # @@ -750,8 +750,8 @@ SHELL=${CONFIG_SHELL-/bin/sh} # Identity of this package. PACKAGE_NAME='xf86-video-intel' PACKAGE_TARNAME='xf86-video-intel' -PACKAGE_VERSION='2.9.1' -PACKAGE_STRING='xf86-video-intel 2.9.1' +PACKAGE_VERSION='2.12.0' +PACKAGE_STRING='xf86-video-intel 2.12.0' PACKAGE_BUGREPORT='https://bugs.freedesktop.org/enter_bug.cgi?product=xorg' ac_unique_file="Makefile.am" @@ -883,6 +883,7 @@ host host_cpu host_vendor host_os +SED APP_MAN_SUFFIX LIB_MAN_SUFFIX FILE_MAN_SUFFIX @@ -895,8 +896,9 @@ FILE_MAN_DIR MISC_MAN_DIR DRIVER_MAN_DIR ADMIN_MAN_DIR +XORG_MAN_PAGE +MAN_SUBSTS AM_DEFAULT_VERBOSITY -SED LN_S ECHO AR @@ -924,16 +926,10 @@ DRM_CFLAGS DRM_LIBS PCIACCESS_CFLAGS PCIACCESS_LIBS -XEXT_CFLAGS -XEXT_LIBS -HAVE_XEXTPROTO_71_TRUE -HAVE_XEXTPROTO_71_FALSE DRI_TRUE DRI_FALSE DRI_CFLAGS DRI_LIBS -VIDEO_DEBUG_TRUE -VIDEO_DEBUG_FALSE XVMCLIB_CFLAGS XVMCLIB_LIBS XVMC_TRUE @@ -942,16 +938,6 @@ KMS_ONLY_TRUE KMS_ONLY_FALSE DRIVER_NAME moduledir -LINUXDOC -PS2PDF -BUILD_LINUXDOC_TRUE -BUILD_LINUXDOC_FALSE -BUILD_PDFDOC_TRUE -BUILD_PDFDOC_FALSE -MAKE_TEXT -MAKE_PS -MAKE_PDF -MAKE_HTML LIBOBJS LTLIBOBJS' ac_subst_files='' @@ -960,7 +946,6 @@ enable_option_checking enable_maintainer_mode enable_dependency_tracking enable_strict_compilation -with_release_version enable_static enable_shared enable_fast_install @@ -970,7 +955,6 @@ with_pic with_tags with_xorg_module_dir enable_dri -enable_video_debug enable_xvmc enable_kms_only ' @@ -998,8 +982,6 @@ DRM_CFLAGS DRM_LIBS PCIACCESS_CFLAGS PCIACCESS_LIBS -XEXT_CFLAGS -XEXT_LIBS DRI_CFLAGS DRI_LIBS XVMCLIB_CFLAGS @@ -1556,7 +1538,7 @@ if test "$ac_init_help" = "long"; then # Omit some internal or obsolete options to make the list less imposing. # This message is too long to be a string in the A/UX 3.1 sh. cat <<_ACEOF -\`configure' configures xf86-video-intel 2.9.1 to adapt to many kinds of systems. +\`configure' configures xf86-video-intel 2.12.0 to adapt to many kinds of systems. Usage: $0 [OPTION]... [VAR=VALUE]... @@ -1627,7 +1609,7 @@ fi if test -n "$ac_init_help"; then case $ac_init_help in - short | recursive ) echo "Configuration of xf86-video-intel 2.9.1:";; + short | recursive ) echo "Configuration of xf86-video-intel 2.12.0:";; esac cat <<\_ACEOF @@ -1648,15 +1630,12 @@ Optional Features: optimize for fast installation [default=yes] --disable-libtool-lock avoid locking (might break parallel builds) --disable-dri Disable DRI support [default=auto] - --enable-video-debug Enable video debugging support [default=no] --disable-xvmc Disable XvMC support [default=yes] --enable-kms-only Assume KMS support [default=no] Optional Packages: --with-PACKAGE[=ARG] use PACKAGE [ARG=yes] --without-PACKAGE do not use PACKAGE (same as --with-PACKAGE=no) - --with-release-version=STRING - Use release version string in package name --with-gnu-ld assume the C compiler uses GNU ld [default=no] --with-pic try to use only PIC/non-PIC objects [default=use both] @@ -1692,8 +1671,6 @@ Some influential environment variables: C compiler flags for PCIACCESS, overriding pkg-config PCIACCESS_LIBS linker flags for PCIACCESS, overriding pkg-config - XEXT_CFLAGS C compiler flags for XEXT, overriding pkg-config - XEXT_LIBS linker flags for XEXT, overriding pkg-config DRI_CFLAGS C compiler flags for DRI, overriding pkg-config DRI_LIBS linker flags for DRI, overriding pkg-config XVMCLIB_CFLAGS @@ -1767,7 +1744,7 @@ fi test -n "$ac_init_help" && exit $ac_status if $ac_init_version; then cat <<\_ACEOF -xf86-video-intel configure 2.9.1 +xf86-video-intel configure 2.12.0 generated by GNU Autoconf 2.62 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001, @@ -1781,7 +1758,7 @@ cat >config.log <<_ACEOF This file contains any messages produced by compilers while running configure, to aid debugging if configure makes a mistake. -It was created by xf86-video-intel $as_me 2.9.1, which was +It was created by xf86-video-intel $as_me 2.12.0, which was generated by GNU Autoconf 2.62. Invocation command line was $ $0 $@ @@ -2148,7 +2125,6 @@ ac_compiler_gnu=$ac_cv_c_compiler_gnu - ac_config_headers="$ac_config_headers config.h" ac_aux_dir= @@ -2183,6 +2159,7 @@ ac_configure="$SHELL $ac_aux_dir/configure" # Please don't use this var. +# Initialize Automake am__api_version="1.9" # Find a good install program. We prefer a C program (faster), # so one script is as good as another. But avoid the broken or @@ -2435,7 +2412,7 @@ fi # Define the identity of the package. PACKAGE='xf86-video-intel' - VERSION='2.9.1' + VERSION='2.12.0' cat >>confdefs.h <<_ACEOF @@ -2581,7 +2558,6 @@ am__tar='${AMTAR} chof - "$$tardir"'; am__untar='${AMTAR} xf -' - { $as_echo "$as_me:$LINENO: checking whether to enable maintainer-specific portions of Makefiles" >&5 $as_echo_n "checking whether to enable maintainer-specific portions of Makefiles... " >&6; } # Check whether --enable-maintainer-mode was given. @@ -2607,7 +2583,7 @@ fi -# Require xorg-macros: XORG_DEFAULT_OPTIONS +# Require X.Org macros 1.8 or later for MAN_SUBSTS set by XORG_MANPAGE_SECTIONS @@ -3724,6 +3700,208 @@ else fi + { $as_echo "$as_me:$LINENO: checking for $CC option to accept ISO C99" >&5 +$as_echo_n "checking for $CC option to accept ISO C99... " >&6; } +if test "${ac_cv_prog_cc_c99+set}" = set; then + $as_echo_n "(cached) " >&6 +else + ac_cv_prog_cc_c99=no +ac_save_CC=$CC +cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +#include <stdarg.h> +#include <stdbool.h> +#include <stdlib.h> +#include <wchar.h> +#include <stdio.h> + +// Check varargs macros. These examples are taken from C99 6.10.3.5. +#define debug(...) fprintf (stderr, __VA_ARGS__) +#define showlist(...) puts (#__VA_ARGS__) +#define report(test,...) ((test) ? puts (#test) : printf (__VA_ARGS__)) +static void +test_varargs_macros (void) +{ + int x = 1234; + int y = 5678; + debug ("Flag"); + debug ("X = %d\n", x); + showlist (The first, second, and third items.); + report (x>y, "x is %d but y is %d", x, y); +} + +// Check long long types. +#define BIG64 18446744073709551615ull +#define BIG32 4294967295ul +#define BIG_OK (BIG64 / BIG32 == 4294967297ull && BIG64 % BIG32 == 0) +#if !BIG_OK + your preprocessor is broken; +#endif +#if BIG_OK +#else + your preprocessor is broken; +#endif +static long long int bignum = -9223372036854775807LL; +static unsigned long long int ubignum = BIG64; + +struct incomplete_array +{ + int datasize; + double data[]; +}; + +struct named_init { + int number; + const wchar_t *name; + double average; +}; + +typedef const char *ccp; + +static inline int +test_restrict (ccp restrict text) +{ + // See if C++-style comments work. + // Iterate through items via the restricted pointer. + // Also check for declarations in for loops. + for (unsigned int i = 0; *(text+i) != '\0'; ++i) + continue; + return 0; +} + +// Check varargs and va_copy. +static void +test_varargs (const char *format, ...) +{ + va_list args; + va_start (args, format); + va_list args_copy; + va_copy (args_copy, args); + + const char *str; + int number; + float fnumber; + + while (*format) + { + switch (*format++) + { + case 's': // string + str = va_arg (args_copy, const char *); + break; + case 'd': // int + number = va_arg (args_copy, int); + break; + case 'f': // float + fnumber = va_arg (args_copy, double); + break; + default: + break; + } + } + va_end (args_copy); + va_end (args); +} + +int +main () +{ + + // Check bool. + _Bool success = false; + + // Check restrict. + if (test_restrict ("String literal") == 0) + success = true; + char *restrict newvar = "Another string"; + + // Check varargs. + test_varargs ("s, d' f .", "string", 65, 34.234); + test_varargs_macros (); + + // Check flexible array members. + struct incomplete_array *ia = + malloc (sizeof (struct incomplete_array) + (sizeof (double) * 10)); + ia->datasize = 10; + for (int i = 0; i < ia->datasize; ++i) + ia->data[i] = i * 1.234; + + // Check named initializers. + struct named_init ni = { + .number = 34, + .name = L"Test wide string", + .average = 543.34343, + }; + + ni.number = 58; + + int dynamic_array[ni.number]; + dynamic_array[ni.number - 1] = 543; + + // work around unused variable warnings + return (!success || bignum == 0LL || ubignum == 0uLL || newvar[0] == 'x' + || dynamic_array[ni.number - 1] != 543); + + ; + return 0; +} +_ACEOF +for ac_arg in '' -std=gnu99 -std=c99 -c99 -AC99 -xc99=all -qlanglvl=extc99 +do + CC="$ac_save_CC $ac_arg" + rm -f conftest.$ac_objext +if { (ac_try="$ac_compile" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_compile") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest.$ac_objext; then + ac_cv_prog_cc_c99=$ac_arg +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + +fi + +rm -f core conftest.err conftest.$ac_objext + test "x$ac_cv_prog_cc_c99" != "xno" && break +done +rm -f conftest.$ac_ext +CC=$ac_save_CC + +fi +# AC_CACHE_VAL +case "x$ac_cv_prog_cc_c99" in + x) + { $as_echo "$as_me:$LINENO: result: none needed" >&5 +$as_echo "none needed" >&6; } ;; + xno) + { $as_echo "$as_me:$LINENO: result: unsupported" >&5 +$as_echo "unsupported" >&6; } ;; + *) + CC="$CC $ac_cv_prog_cc_c99" + { $as_echo "$as_me:$LINENO: result: $ac_cv_prog_cc_c99" >&5 +$as_echo "$ac_cv_prog_cc_c99" >&6; } ;; +esac + + + ac_ext=c ac_cpp='$CPP $CPPFLAGS' @@ -4344,208 +4522,6 @@ fi done - { $as_echo "$as_me:$LINENO: checking for $CC option to accept ISO C99" >&5 -$as_echo_n "checking for $CC option to accept ISO C99... " >&6; } -if test "${ac_cv_prog_cc_c99+set}" = set; then - $as_echo_n "(cached) " >&6 -else - ac_cv_prog_cc_c99=no -ac_save_CC=$CC -cat >conftest.$ac_ext <<_ACEOF -/* confdefs.h. */ -_ACEOF -cat confdefs.h >>conftest.$ac_ext -cat >>conftest.$ac_ext <<_ACEOF -/* end confdefs.h. */ -#include <stdarg.h> -#include <stdbool.h> -#include <stdlib.h> -#include <wchar.h> -#include <stdio.h> - -// Check varargs macros. These examples are taken from C99 6.10.3.5. -#define debug(...) fprintf (stderr, __VA_ARGS__) -#define showlist(...) puts (#__VA_ARGS__) -#define report(test,...) ((test) ? puts (#test) : printf (__VA_ARGS__)) -static void -test_varargs_macros (void) -{ - int x = 1234; - int y = 5678; - debug ("Flag"); - debug ("X = %d\n", x); - showlist (The first, second, and third items.); - report (x>y, "x is %d but y is %d", x, y); -} - -// Check long long types. -#define BIG64 18446744073709551615ull -#define BIG32 4294967295ul -#define BIG_OK (BIG64 / BIG32 == 4294967297ull && BIG64 % BIG32 == 0) -#if !BIG_OK - your preprocessor is broken; -#endif -#if BIG_OK -#else - your preprocessor is broken; -#endif -static long long int bignum = -9223372036854775807LL; -static unsigned long long int ubignum = BIG64; - -struct incomplete_array -{ - int datasize; - double data[]; -}; - -struct named_init { - int number; - const wchar_t *name; - double average; -}; - -typedef const char *ccp; - -static inline int -test_restrict (ccp restrict text) -{ - // See if C++-style comments work. - // Iterate through items via the restricted pointer. - // Also check for declarations in for loops. - for (unsigned int i = 0; *(text+i) != '\0'; ++i) - continue; - return 0; -} - -// Check varargs and va_copy. -static void -test_varargs (const char *format, ...) -{ - va_list args; - va_start (args, format); - va_list args_copy; - va_copy (args_copy, args); - - const char *str; - int number; - float fnumber; - - while (*format) - { - switch (*format++) - { - case 's': // string - str = va_arg (args_copy, const char *); - break; - case 'd': // int - number = va_arg (args_copy, int); - break; - case 'f': // float - fnumber = va_arg (args_copy, double); - break; - default: - break; - } - } - va_end (args_copy); - va_end (args); -} - -int -main () -{ - - // Check bool. - _Bool success = false; - - // Check restrict. - if (test_restrict ("String literal") == 0) - success = true; - char *restrict newvar = "Another string"; - - // Check varargs. - test_varargs ("s, d' f .", "string", 65, 34.234); - test_varargs_macros (); - - // Check flexible array members. - struct incomplete_array *ia = - malloc (sizeof (struct incomplete_array) + (sizeof (double) * 10)); - ia->datasize = 10; - for (int i = 0; i < ia->datasize; ++i) - ia->data[i] = i * 1.234; - - // Check named initializers. - struct named_init ni = { - .number = 34, - .name = L"Test wide string", - .average = 543.34343, - }; - - ni.number = 58; - - int dynamic_array[ni.number]; - dynamic_array[ni.number - 1] = 543; - - // work around unused variable warnings - return (!success || bignum == 0LL || ubignum == 0uLL || newvar[0] == 'x' - || dynamic_array[ni.number - 1] != 543); - - ; - return 0; -} -_ACEOF -for ac_arg in '' -std=gnu99 -std=c99 -c99 -AC99 -xc99=all -qlanglvl=extc99 -do - CC="$ac_save_CC $ac_arg" - rm -f conftest.$ac_objext -if { (ac_try="$ac_compile" -case "(($ac_try" in - *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; - *) ac_try_echo=$ac_try;; -esac -eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" -$as_echo "$ac_try_echo") >&5 - (eval "$ac_compile") 2>conftest.er1 - ac_status=$? - grep -v '^ *+' conftest.er1 >conftest.err - rm -f conftest.er1 - cat conftest.err >&5 - $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); } && { - test -z "$ac_c_werror_flag" || - test ! -s conftest.err - } && test -s conftest.$ac_objext; then - ac_cv_prog_cc_c99=$ac_arg -else - $as_echo "$as_me: failed program was:" >&5 -sed 's/^/| /' conftest.$ac_ext >&5 - - -fi - -rm -f core conftest.err conftest.$ac_objext - test "x$ac_cv_prog_cc_c99" != "xno" && break -done -rm -f conftest.$ac_ext -CC=$ac_save_CC - -fi -# AC_CACHE_VAL -case "x$ac_cv_prog_cc_c99" in - x) - { $as_echo "$as_me:$LINENO: result: none needed" >&5 -$as_echo "none needed" >&6; } ;; - xno) - { $as_echo "$as_me:$LINENO: result: unsupported" >&5 -$as_echo "unsupported" >&6; } ;; - *) - CC="$CC $ac_cv_prog_cc_c99" - { $as_echo "$as_me:$LINENO: result: $ac_cv_prog_cc_c99" >&5 -$as_echo "$ac_cv_prog_cc_c99" >&6; } ;; -esac - - - if test "x$ac_cv_env_PKG_CONFIG_set" != "xset"; then @@ -4749,6 +4725,78 @@ IFS=$ac_save_IFS case $host_os in *\ *) host_os=`echo "$host_os" | sed 's/ /-/g'`;; esac +{ $as_echo "$as_me:$LINENO: checking for a sed that does not truncate output" >&5 +$as_echo_n "checking for a sed that does not truncate output... " >&6; } +if test "${ac_cv_path_SED+set}" = set; then + $as_echo_n "(cached) " >&6 +else + ac_script=s/aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa/bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb/ + for ac_i in 1 2 3 4 5 6 7; do + ac_script="$ac_script$as_nl$ac_script" + done + echo "$ac_script" 2>/dev/null | sed 99q >conftest.sed + $as_unset ac_script || ac_script= + if test -z "$SED"; then + ac_path_SED_found=false + # Loop through the user's path and test for each of PROGNAME-LIST + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_prog in sed gsed; do + for ac_exec_ext in '' $ac_executable_extensions; do + ac_path_SED="$as_dir/$ac_prog$ac_exec_ext" + { test -f "$ac_path_SED" && $as_test_x "$ac_path_SED"; } || continue +# Check for GNU ac_path_SED and select it if it is found. + # Check for GNU $ac_path_SED +case `"$ac_path_SED" --version 2>&1` in +*GNU*) + ac_cv_path_SED="$ac_path_SED" ac_path_SED_found=:;; +*) + ac_count=0 + $as_echo_n 0123456789 >"conftest.in" + while : + do + cat "conftest.in" "conftest.in" >"conftest.tmp" + mv "conftest.tmp" "conftest.in" + cp "conftest.in" "conftest.nl" + $as_echo '' >> "conftest.nl" + "$ac_path_SED" -f conftest.sed < "conftest.nl" >"conftest.out" 2>/dev/null || break + diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break + ac_count=`expr $ac_count + 1` + if test $ac_count -gt ${ac_path_SED_max-0}; then + # Best one so far, save it but keep looking for a better one + ac_cv_path_SED="$ac_path_SED" + ac_path_SED_max=$ac_count + fi + # 10*(2^10) chars as input seems more than enough + test $ac_count -gt 10 && break + done + rm -f conftest.in conftest.tmp conftest.nl conftest.out;; +esac + + $ac_path_SED_found && break 3 + done + done +done +IFS=$as_save_IFS + if test -z "$ac_cv_path_SED"; then + { { $as_echo "$as_me:$LINENO: error: no acceptable sed could be found in \$PATH" >&5 +$as_echo "$as_me: error: no acceptable sed could be found in \$PATH" >&2;} + { (exit 1); exit 1; }; } + fi +else + ac_cv_path_SED=$SED +fi + +fi +{ $as_echo "$as_me:$LINENO: result: $ac_cv_path_SED" >&5 +$as_echo "$ac_cv_path_SED" >&6; } + SED="$ac_cv_path_SED" + rm -f conftest.sed + + @@ -4828,7 +4876,7 @@ fi - +# If the module's configure.ac calls AC_PROG_CC later on, CC gets set to C89 @@ -4971,20 +5019,6 @@ CWARNFLAGS="$CWARNFLAGS $STRICT_CFLAGS" -# Check whether --with-release-version was given. -if test "${with_release_version+set}" = set; then - withval=$with_release_version; RELEASE_VERSION="$withval" -else - RELEASE_VERSION="" -fi - - if test "x$RELEASE_VERSION" != "x"; then - PACKAGE="$PACKAGE-$RELEASE_VERSION" - PACKAGE_TARNAME="$PACKAGE_TARNAME-$RELEASE_VERSION" - { $as_echo "$as_me:$LINENO: Building with package name set to $PACKAGE" >&5 -$as_echo "$as_me: Building with package name set to $PACKAGE" >&6;} - fi - cat >>confdefs.h <<_ACEOF #define PACKAGE_VERSION_MAJOR `echo $PACKAGE_VERSION | cut -d . -f 1` _ACEOF @@ -5027,6 +5061,7 @@ echo 'util-macros \"pkgdatadir\" from xorg-macros.pc not found: installing possi + if test x$APP_MAN_SUFFIX = x ; then APP_MAN_SUFFIX=1 fi @@ -5095,11 +5130,28 @@ fi +XORG_MAN_PAGE="X Version 11" + +MAN_SUBSTS="\ + -e 's|__vendorversion__|\"\$(PACKAGE_STRING)\" \"\$(XORG_MAN_PAGE)\"|' \ + -e 's|__xorgversion__|\"\$(PACKAGE_STRING)\" \"\$(XORG_MAN_PAGE)\"|' \ + -e 's|__xservername__|Xorg|g' \ + -e 's|__xconfigfile__|xorg.conf|g' \ + -e 's|__projectroot__|\$(prefix)|g' \ + -e 's|__appmansuffix__|\$(APP_MAN_SUFFIX)|g' \ + -e 's|__drivermansuffix__|\$(DRIVER_MAN_SUFFIX)|g' \ + -e 's|__adminmansuffix__|\$(ADMIN_MAN_SUFFIX)|g' \ + -e 's|__libmansuffix__|\$(LIB_MAN_SUFFIX)|g' \ + -e 's|__miscmansuffix__|\$(MISC_MAN_SUFFIX)|g' \ + -e 's|__filemansuffix__|\$(FILE_MAN_SUFFIX)|g'" + + + AM_DEFAULT_VERBOSITY=1 -# Checks for programs. +# Initialize libtool # Check whether --enable-static was given. if test "${enable_static+set}" = set; then enableval=$enable_static; p=${PACKAGE-default} @@ -5663,7 +5715,7 @@ ia64-*-hpux*) ;; *-*-irix6*) # Find out which ABI we are using. - echo '#line 5666 "configure"' > conftest.$ac_ext + echo '#line 5718 "configure"' > conftest.$ac_ext if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 (eval $ac_compile) 2>&5 ac_status=$? @@ -8286,11 +8338,11 @@ else -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:8289: $lt_compile\"" >&5) + (eval echo "\"\$as_me:8341: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:8293: \$? = $ac_status" >&5 + echo "$as_me:8345: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings other than the usual output. @@ -8576,11 +8628,11 @@ else -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:8579: $lt_compile\"" >&5) + (eval echo "\"\$as_me:8631: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:8583: \$? = $ac_status" >&5 + echo "$as_me:8635: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings other than the usual output. @@ -8680,11 +8732,11 @@ else -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:8683: $lt_compile\"" >&5) + (eval echo "\"\$as_me:8735: $lt_compile\"" >&5) (eval "$lt_compile" 2>out/conftest.err) ac_status=$? cat out/conftest.err >&5 - echo "$as_me:8687: \$? = $ac_status" >&5 + echo "$as_me:8739: \$? = $ac_status" >&5 if (exit $ac_status) && test -s out/conftest2.$ac_objext then # The compiler can only warn and ignore the option if not recognized @@ -11080,7 +11132,7 @@ else lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext <<EOF -#line 11083 "configure" +#line 11135 "configure" #include "confdefs.h" #if HAVE_DLFCN_H @@ -11180,7 +11232,7 @@ else lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext <<EOF -#line 11183 "configure" +#line 11235 "configure" #include "confdefs.h" #if HAVE_DLFCN_H @@ -13589,11 +13641,11 @@ else -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:13592: $lt_compile\"" >&5) + (eval echo "\"\$as_me:13644: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:13596: \$? = $ac_status" >&5 + echo "$as_me:13648: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings other than the usual output. @@ -13693,11 +13745,11 @@ else -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:13696: $lt_compile\"" >&5) + (eval echo "\"\$as_me:13748: $lt_compile\"" >&5) (eval "$lt_compile" 2>out/conftest.err) ac_status=$? cat out/conftest.err >&5 - echo "$as_me:13700: \$? = $ac_status" >&5 + echo "$as_me:13752: \$? = $ac_status" >&5 if (exit $ac_status) && test -s out/conftest2.$ac_objext then # The compiler can only warn and ignore the option if not recognized @@ -15276,11 +15328,11 @@ else -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:15279: $lt_compile\"" >&5) + (eval echo "\"\$as_me:15331: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:15283: \$? = $ac_status" >&5 + echo "$as_me:15335: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings other than the usual output. @@ -15380,11 +15432,11 @@ else -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:15383: $lt_compile\"" >&5) + (eval echo "\"\$as_me:15435: $lt_compile\"" >&5) (eval "$lt_compile" 2>out/conftest.err) ac_status=$? cat out/conftest.err >&5 - echo "$as_me:15387: \$? = $ac_status" >&5 + echo "$as_me:15439: \$? = $ac_status" >&5 if (exit $ac_status) && test -s out/conftest2.$ac_objext then # The compiler can only warn and ignore the option if not recognized @@ -17595,11 +17647,11 @@ else -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:17598: $lt_compile\"" >&5) + (eval echo "\"\$as_me:17650: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:17602: \$? = $ac_status" >&5 + echo "$as_me:17654: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings other than the usual output. @@ -17885,11 +17937,11 @@ else -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:17888: $lt_compile\"" >&5) + (eval echo "\"\$as_me:17940: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:17892: \$? = $ac_status" >&5 + echo "$as_me:17944: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings other than the usual output. @@ -17989,11 +18041,11 @@ else -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:17992: $lt_compile\"" >&5) + (eval echo "\"\$as_me:18044: $lt_compile\"" >&5) (eval "$lt_compile" 2>out/conftest.err) ac_status=$? cat out/conftest.err >&5 - echo "$as_me:17996: \$? = $ac_status" >&5 + echo "$as_me:18048: \$? = $ac_status" >&5 if (exit $ac_status) && test -s out/conftest2.$ac_objext then # The compiler can only warn and ignore the option if not recognized @@ -20674,804 +20726,6 @@ LIBTOOL='$(SHELL) $(top_builddir)/libtool' -ac_ext=c -ac_cpp='$CPP $CPPFLAGS' -ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' -ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' -ac_compiler_gnu=$ac_cv_c_compiler_gnu -if test -n "$ac_tool_prefix"; then - # Extract the first word of "${ac_tool_prefix}gcc", so it can be a program name with args. -set dummy ${ac_tool_prefix}gcc; ac_word=$2 -{ $as_echo "$as_me:$LINENO: checking for $ac_word" >&5 -$as_echo_n "checking for $ac_word... " >&6; } -if test "${ac_cv_prog_CC+set}" = set; then - $as_echo_n "(cached) " >&6 -else - if test -n "$CC"; then - ac_cv_prog_CC="$CC" # Let the user override the test. -else -as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -for as_dir in $PATH -do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do - if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then - ac_cv_prog_CC="${ac_tool_prefix}gcc" - $as_echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 - fi -done -done -IFS=$as_save_IFS - -fi -fi -CC=$ac_cv_prog_CC -if test -n "$CC"; then - { $as_echo "$as_me:$LINENO: result: $CC" >&5 -$as_echo "$CC" >&6; } -else - { $as_echo "$as_me:$LINENO: result: no" >&5 -$as_echo "no" >&6; } -fi - - -fi -if test -z "$ac_cv_prog_CC"; then - ac_ct_CC=$CC - # Extract the first word of "gcc", so it can be a program name with args. -set dummy gcc; ac_word=$2 -{ $as_echo "$as_me:$LINENO: checking for $ac_word" >&5 -$as_echo_n "checking for $ac_word... " >&6; } -if test "${ac_cv_prog_ac_ct_CC+set}" = set; then - $as_echo_n "(cached) " >&6 -else - if test -n "$ac_ct_CC"; then - ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test. -else -as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -for as_dir in $PATH -do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do - if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then - ac_cv_prog_ac_ct_CC="gcc" - $as_echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 - fi -done -done -IFS=$as_save_IFS - -fi -fi -ac_ct_CC=$ac_cv_prog_ac_ct_CC -if test -n "$ac_ct_CC"; then - { $as_echo "$as_me:$LINENO: result: $ac_ct_CC" >&5 -$as_echo "$ac_ct_CC" >&6; } -else - { $as_echo "$as_me:$LINENO: result: no" >&5 -$as_echo "no" >&6; } -fi - - if test "x$ac_ct_CC" = x; then - CC="" - else - case $cross_compiling:$ac_tool_warned in -yes:) -{ $as_echo "$as_me:$LINENO: WARNING: In the future, Autoconf will not detect cross-tools -whose name does not start with the host triplet. If you think this -configuration is useful to you, please write to autoconf@gnu.org." >&5 -$as_echo "$as_me: WARNING: In the future, Autoconf will not detect cross-tools -whose name does not start with the host triplet. If you think this -configuration is useful to you, please write to autoconf@gnu.org." >&2;} -ac_tool_warned=yes ;; -esac - CC=$ac_ct_CC - fi -else - CC="$ac_cv_prog_CC" -fi - -if test -z "$CC"; then - if test -n "$ac_tool_prefix"; then - # Extract the first word of "${ac_tool_prefix}cc", so it can be a program name with args. -set dummy ${ac_tool_prefix}cc; ac_word=$2 -{ $as_echo "$as_me:$LINENO: checking for $ac_word" >&5 -$as_echo_n "checking for $ac_word... " >&6; } -if test "${ac_cv_prog_CC+set}" = set; then - $as_echo_n "(cached) " >&6 -else - if test -n "$CC"; then - ac_cv_prog_CC="$CC" # Let the user override the test. -else -as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -for as_dir in $PATH -do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do - if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then - ac_cv_prog_CC="${ac_tool_prefix}cc" - $as_echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 - fi -done -done -IFS=$as_save_IFS - -fi -fi -CC=$ac_cv_prog_CC -if test -n "$CC"; then - { $as_echo "$as_me:$LINENO: result: $CC" >&5 -$as_echo "$CC" >&6; } -else - { $as_echo "$as_me:$LINENO: result: no" >&5 -$as_echo "no" >&6; } -fi - - - fi -fi -if test -z "$CC"; then - # Extract the first word of "cc", so it can be a program name with args. -set dummy cc; ac_word=$2 -{ $as_echo "$as_me:$LINENO: checking for $ac_word" >&5 -$as_echo_n "checking for $ac_word... " >&6; } -if test "${ac_cv_prog_CC+set}" = set; then - $as_echo_n "(cached) " >&6 -else - if test -n "$CC"; then - ac_cv_prog_CC="$CC" # Let the user override the test. -else - ac_prog_rejected=no -as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -for as_dir in $PATH -do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do - if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then - if test "$as_dir/$ac_word$ac_exec_ext" = "/usr/ucb/cc"; then - ac_prog_rejected=yes - continue - fi - ac_cv_prog_CC="cc" - $as_echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 - fi -done -done -IFS=$as_save_IFS - -if test $ac_prog_rejected = yes; then - # We found a bogon in the path, so make sure we never use it. - set dummy $ac_cv_prog_CC - shift - if test $# != 0; then - # We chose a different compiler from the bogus one. - # However, it has the same basename, so the bogon will be chosen - # first if we set CC to just the basename; use the full file name. - shift - ac_cv_prog_CC="$as_dir/$ac_word${1+' '}$@" - fi -fi -fi -fi -CC=$ac_cv_prog_CC -if test -n "$CC"; then - { $as_echo "$as_me:$LINENO: result: $CC" >&5 -$as_echo "$CC" >&6; } -else - { $as_echo "$as_me:$LINENO: result: no" >&5 -$as_echo "no" >&6; } -fi - - -fi -if test -z "$CC"; then - if test -n "$ac_tool_prefix"; then - for ac_prog in cl.exe - do - # Extract the first word of "$ac_tool_prefix$ac_prog", so it can be a program name with args. -set dummy $ac_tool_prefix$ac_prog; ac_word=$2 -{ $as_echo "$as_me:$LINENO: checking for $ac_word" >&5 -$as_echo_n "checking for $ac_word... " >&6; } -if test "${ac_cv_prog_CC+set}" = set; then - $as_echo_n "(cached) " >&6 -else - if test -n "$CC"; then - ac_cv_prog_CC="$CC" # Let the user override the test. -else -as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -for as_dir in $PATH -do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do - if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then - ac_cv_prog_CC="$ac_tool_prefix$ac_prog" - $as_echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 - fi -done -done -IFS=$as_save_IFS - -fi -fi -CC=$ac_cv_prog_CC -if test -n "$CC"; then - { $as_echo "$as_me:$LINENO: result: $CC" >&5 -$as_echo "$CC" >&6; } -else - { $as_echo "$as_me:$LINENO: result: no" >&5 -$as_echo "no" >&6; } -fi - - - test -n "$CC" && break - done -fi -if test -z "$CC"; then - ac_ct_CC=$CC - for ac_prog in cl.exe -do - # Extract the first word of "$ac_prog", so it can be a program name with args. -set dummy $ac_prog; ac_word=$2 -{ $as_echo "$as_me:$LINENO: checking for $ac_word" >&5 -$as_echo_n "checking for $ac_word... " >&6; } -if test "${ac_cv_prog_ac_ct_CC+set}" = set; then - $as_echo_n "(cached) " >&6 -else - if test -n "$ac_ct_CC"; then - ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test. -else -as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -for as_dir in $PATH -do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do - if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then - ac_cv_prog_ac_ct_CC="$ac_prog" - $as_echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 - fi -done -done -IFS=$as_save_IFS - -fi -fi -ac_ct_CC=$ac_cv_prog_ac_ct_CC -if test -n "$ac_ct_CC"; then - { $as_echo "$as_me:$LINENO: result: $ac_ct_CC" >&5 -$as_echo "$ac_ct_CC" >&6; } -else - { $as_echo "$as_me:$LINENO: result: no" >&5 -$as_echo "no" >&6; } -fi - - - test -n "$ac_ct_CC" && break -done - - if test "x$ac_ct_CC" = x; then - CC="" - else - case $cross_compiling:$ac_tool_warned in -yes:) -{ $as_echo "$as_me:$LINENO: WARNING: In the future, Autoconf will not detect cross-tools -whose name does not start with the host triplet. If you think this -configuration is useful to you, please write to autoconf@gnu.org." >&5 -$as_echo "$as_me: WARNING: In the future, Autoconf will not detect cross-tools -whose name does not start with the host triplet. If you think this -configuration is useful to you, please write to autoconf@gnu.org." >&2;} -ac_tool_warned=yes ;; -esac - CC=$ac_ct_CC - fi -fi - -fi - - -test -z "$CC" && { { $as_echo "$as_me:$LINENO: error: no acceptable C compiler found in \$PATH -See \`config.log' for more details." >&5 -$as_echo "$as_me: error: no acceptable C compiler found in \$PATH -See \`config.log' for more details." >&2;} - { (exit 1); exit 1; }; } - -# Provide some information about the compiler. -$as_echo "$as_me:$LINENO: checking for C compiler version" >&5 -set X $ac_compile -ac_compiler=$2 -{ (ac_try="$ac_compiler --version >&5" -case "(($ac_try" in - *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; - *) ac_try_echo=$ac_try;; -esac -eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" -$as_echo "$ac_try_echo") >&5 - (eval "$ac_compiler --version >&5") 2>&5 - ac_status=$? - $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); } -{ (ac_try="$ac_compiler -v >&5" -case "(($ac_try" in - *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; - *) ac_try_echo=$ac_try;; -esac -eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" -$as_echo "$ac_try_echo") >&5 - (eval "$ac_compiler -v >&5") 2>&5 - ac_status=$? - $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); } -{ (ac_try="$ac_compiler -V >&5" -case "(($ac_try" in - *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; - *) ac_try_echo=$ac_try;; -esac -eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" -$as_echo "$ac_try_echo") >&5 - (eval "$ac_compiler -V >&5") 2>&5 - ac_status=$? - $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); } - -{ $as_echo "$as_me:$LINENO: checking whether we are using the GNU C compiler" >&5 -$as_echo_n "checking whether we are using the GNU C compiler... " >&6; } -if test "${ac_cv_c_compiler_gnu+set}" = set; then - $as_echo_n "(cached) " >&6 -else - cat >conftest.$ac_ext <<_ACEOF -/* confdefs.h. */ -_ACEOF -cat confdefs.h >>conftest.$ac_ext -cat >>conftest.$ac_ext <<_ACEOF -/* end confdefs.h. */ - -int -main () -{ -#ifndef __GNUC__ - choke me -#endif - - ; - return 0; -} -_ACEOF -rm -f conftest.$ac_objext -if { (ac_try="$ac_compile" -case "(($ac_try" in - *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; - *) ac_try_echo=$ac_try;; -esac -eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" -$as_echo "$ac_try_echo") >&5 - (eval "$ac_compile") 2>conftest.er1 - ac_status=$? - grep -v '^ *+' conftest.er1 >conftest.err - rm -f conftest.er1 - cat conftest.err >&5 - $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); } && { - test -z "$ac_c_werror_flag" || - test ! -s conftest.err - } && test -s conftest.$ac_objext; then - ac_compiler_gnu=yes -else - $as_echo "$as_me: failed program was:" >&5 -sed 's/^/| /' conftest.$ac_ext >&5 - - ac_compiler_gnu=no -fi - -rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext -ac_cv_c_compiler_gnu=$ac_compiler_gnu - -fi -{ $as_echo "$as_me:$LINENO: result: $ac_cv_c_compiler_gnu" >&5 -$as_echo "$ac_cv_c_compiler_gnu" >&6; } -if test $ac_compiler_gnu = yes; then - GCC=yes -else - GCC= -fi -ac_test_CFLAGS=${CFLAGS+set} -ac_save_CFLAGS=$CFLAGS -{ $as_echo "$as_me:$LINENO: checking whether $CC accepts -g" >&5 -$as_echo_n "checking whether $CC accepts -g... " >&6; } -if test "${ac_cv_prog_cc_g+set}" = set; then - $as_echo_n "(cached) " >&6 -else - ac_save_c_werror_flag=$ac_c_werror_flag - ac_c_werror_flag=yes - ac_cv_prog_cc_g=no - CFLAGS="-g" - cat >conftest.$ac_ext <<_ACEOF -/* confdefs.h. */ -_ACEOF -cat confdefs.h >>conftest.$ac_ext -cat >>conftest.$ac_ext <<_ACEOF -/* end confdefs.h. */ - -int -main () -{ - - ; - return 0; -} -_ACEOF -rm -f conftest.$ac_objext -if { (ac_try="$ac_compile" -case "(($ac_try" in - *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; - *) ac_try_echo=$ac_try;; -esac -eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" -$as_echo "$ac_try_echo") >&5 - (eval "$ac_compile") 2>conftest.er1 - ac_status=$? - grep -v '^ *+' conftest.er1 >conftest.err - rm -f conftest.er1 - cat conftest.err >&5 - $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); } && { - test -z "$ac_c_werror_flag" || - test ! -s conftest.err - } && test -s conftest.$ac_objext; then - ac_cv_prog_cc_g=yes -else - $as_echo "$as_me: failed program was:" >&5 -sed 's/^/| /' conftest.$ac_ext >&5 - - CFLAGS="" - cat >conftest.$ac_ext <<_ACEOF -/* confdefs.h. */ -_ACEOF -cat confdefs.h >>conftest.$ac_ext -cat >>conftest.$ac_ext <<_ACEOF -/* end confdefs.h. */ - -int -main () -{ - - ; - return 0; -} -_ACEOF -rm -f conftest.$ac_objext -if { (ac_try="$ac_compile" -case "(($ac_try" in - *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; - *) ac_try_echo=$ac_try;; -esac -eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" -$as_echo "$ac_try_echo") >&5 - (eval "$ac_compile") 2>conftest.er1 - ac_status=$? - grep -v '^ *+' conftest.er1 >conftest.err - rm -f conftest.er1 - cat conftest.err >&5 - $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); } && { - test -z "$ac_c_werror_flag" || - test ! -s conftest.err - } && test -s conftest.$ac_objext; then - : -else - $as_echo "$as_me: failed program was:" >&5 -sed 's/^/| /' conftest.$ac_ext >&5 - - ac_c_werror_flag=$ac_save_c_werror_flag - CFLAGS="-g" - cat >conftest.$ac_ext <<_ACEOF -/* confdefs.h. */ -_ACEOF -cat confdefs.h >>conftest.$ac_ext -cat >>conftest.$ac_ext <<_ACEOF -/* end confdefs.h. */ - -int -main () -{ - - ; - return 0; -} -_ACEOF -rm -f conftest.$ac_objext -if { (ac_try="$ac_compile" -case "(($ac_try" in - *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; - *) ac_try_echo=$ac_try;; -esac -eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" -$as_echo "$ac_try_echo") >&5 - (eval "$ac_compile") 2>conftest.er1 - ac_status=$? - grep -v '^ *+' conftest.er1 >conftest.err - rm -f conftest.er1 - cat conftest.err >&5 - $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); } && { - test -z "$ac_c_werror_flag" || - test ! -s conftest.err - } && test -s conftest.$ac_objext; then - ac_cv_prog_cc_g=yes -else - $as_echo "$as_me: failed program was:" >&5 -sed 's/^/| /' conftest.$ac_ext >&5 - - -fi - -rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext -fi - -rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext -fi - -rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext - ac_c_werror_flag=$ac_save_c_werror_flag -fi -{ $as_echo "$as_me:$LINENO: result: $ac_cv_prog_cc_g" >&5 -$as_echo "$ac_cv_prog_cc_g" >&6; } -if test "$ac_test_CFLAGS" = set; then - CFLAGS=$ac_save_CFLAGS -elif test $ac_cv_prog_cc_g = yes; then - if test "$GCC" = yes; then - CFLAGS="-g -O2" - else - CFLAGS="-g" - fi -else - if test "$GCC" = yes; then - CFLAGS="-O2" - else - CFLAGS= - fi -fi -{ $as_echo "$as_me:$LINENO: checking for $CC option to accept ISO C89" >&5 -$as_echo_n "checking for $CC option to accept ISO C89... " >&6; } -if test "${ac_cv_prog_cc_c89+set}" = set; then - $as_echo_n "(cached) " >&6 -else - ac_cv_prog_cc_c89=no -ac_save_CC=$CC -cat >conftest.$ac_ext <<_ACEOF -/* confdefs.h. */ -_ACEOF -cat confdefs.h >>conftest.$ac_ext -cat >>conftest.$ac_ext <<_ACEOF -/* end confdefs.h. */ -#include <stdarg.h> -#include <stdio.h> -#include <sys/types.h> -#include <sys/stat.h> -/* Most of the following tests are stolen from RCS 5.7's src/conf.sh. */ -struct buf { int x; }; -FILE * (*rcsopen) (struct buf *, struct stat *, int); -static char *e (p, i) - char **p; - int i; -{ - return p[i]; -} -static char *f (char * (*g) (char **, int), char **p, ...) -{ - char *s; - va_list v; - va_start (v,p); - s = g (p, va_arg (v,int)); - va_end (v); - return s; -} - -/* OSF 4.0 Compaq cc is some sort of almost-ANSI by default. It has - function prototypes and stuff, but not '\xHH' hex character constants. - These don't provoke an error unfortunately, instead are silently treated - as 'x'. The following induces an error, until -std is added to get - proper ANSI mode. Curiously '\x00'!='x' always comes out true, for an - array size at least. It's necessary to write '\x00'==0 to get something - that's true only with -std. */ -int osf4_cc_array ['\x00' == 0 ? 1 : -1]; - -/* IBM C 6 for AIX is almost-ANSI by default, but it replaces macro parameters - inside strings and character constants. */ -#define FOO(x) 'x' -int xlc6_cc_array[FOO(a) == 'x' ? 1 : -1]; - -int test (int i, double x); -struct s1 {int (*f) (int a);}; -struct s2 {int (*f) (double a);}; -int pairnames (int, char **, FILE *(*)(struct buf *, struct stat *, int), int, int); -int argc; -char **argv; -int -main () -{ -return f (e, argv, 0) != argv[0] || f (e, argv, 1) != argv[1]; - ; - return 0; -} -_ACEOF -for ac_arg in '' -qlanglvl=extc89 -qlanglvl=ansi -std \ - -Ae "-Aa -D_HPUX_SOURCE" "-Xc -D__EXTENSIONS__" -do - CC="$ac_save_CC $ac_arg" - rm -f conftest.$ac_objext -if { (ac_try="$ac_compile" -case "(($ac_try" in - *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; - *) ac_try_echo=$ac_try;; -esac -eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" -$as_echo "$ac_try_echo") >&5 - (eval "$ac_compile") 2>conftest.er1 - ac_status=$? - grep -v '^ *+' conftest.er1 >conftest.err - rm -f conftest.er1 - cat conftest.err >&5 - $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); } && { - test -z "$ac_c_werror_flag" || - test ! -s conftest.err - } && test -s conftest.$ac_objext; then - ac_cv_prog_cc_c89=$ac_arg -else - $as_echo "$as_me: failed program was:" >&5 -sed 's/^/| /' conftest.$ac_ext >&5 - - -fi - -rm -f core conftest.err conftest.$ac_objext - test "x$ac_cv_prog_cc_c89" != "xno" && break -done -rm -f conftest.$ac_ext -CC=$ac_save_CC - -fi -# AC_CACHE_VAL -case "x$ac_cv_prog_cc_c89" in - x) - { $as_echo "$as_me:$LINENO: result: none needed" >&5 -$as_echo "none needed" >&6; } ;; - xno) - { $as_echo "$as_me:$LINENO: result: unsupported" >&5 -$as_echo "unsupported" >&6; } ;; - *) - CC="$CC $ac_cv_prog_cc_c89" - { $as_echo "$as_me:$LINENO: result: $ac_cv_prog_cc_c89" >&5 -$as_echo "$ac_cv_prog_cc_c89" >&6; } ;; -esac - - -ac_ext=c -ac_cpp='$CPP $CPPFLAGS' -ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' -ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' -ac_compiler_gnu=$ac_cv_c_compiler_gnu - -depcc="$CC" am_compiler_list= - -{ $as_echo "$as_me:$LINENO: checking dependency style of $depcc" >&5 -$as_echo_n "checking dependency style of $depcc... " >&6; } -if test "${am_cv_CC_dependencies_compiler_type+set}" = set; then - $as_echo_n "(cached) " >&6 -else - if test -z "$AMDEP_TRUE" && test -f "$am_depcomp"; then - # We make a subdir and do the tests there. Otherwise we can end up - # making bogus files that we don't know about and never remove. For - # instance it was reported that on HP-UX the gcc test will end up - # making a dummy file named `D' -- because `-MD' means `put the output - # in D'. - mkdir conftest.dir - # Copy depcomp to subdir because otherwise we won't find it if we're - # using a relative directory. - cp "$am_depcomp" conftest.dir - cd conftest.dir - # We will build objects and dependencies in a subdirectory because - # it helps to detect inapplicable dependency modes. For instance - # both Tru64's cc and ICC support -MD to output dependencies as a - # side effect of compilation, but ICC will put the dependencies in - # the current directory while Tru64 will put them in the object - # directory. - mkdir sub - - am_cv_CC_dependencies_compiler_type=none - if test "$am_compiler_list" = ""; then - am_compiler_list=`sed -n 's/^#*\([a-zA-Z0-9]*\))$/\1/p' < ./depcomp` - fi - for depmode in $am_compiler_list; do - # Setup a source with many dependencies, because some compilers - # like to wrap large dependency lists on column 80 (with \), and - # we should not choose a depcomp mode which is confused by this. - # - # We need to recreate these files for each test, as the compiler may - # overwrite some of them when testing with obscure command lines. - # This happens at least with the AIX C compiler. - : > sub/conftest.c - for i in 1 2 3 4 5 6; do - echo '#include "conftst'$i'.h"' >> sub/conftest.c - # Using `: > sub/conftst$i.h' creates only sub/conftst1.h with - # Solaris 8's {/usr,}/bin/sh. - touch sub/conftst$i.h - done - echo "${am__include} ${am__quote}sub/conftest.Po${am__quote}" > confmf - - case $depmode in - nosideeffect) - # after this tag, mechanisms are not by side-effect, so they'll - # only be used when explicitly requested - if test "x$enable_dependency_tracking" = xyes; then - continue - else - break - fi - ;; - none) break ;; - esac - # We check with `-c' and `-o' for the sake of the "dashmstdout" - # mode. It turns out that the SunPro C++ compiler does not properly - # handle `-M -o', and we need to detect this. - if depmode=$depmode \ - source=sub/conftest.c object=sub/conftest.${OBJEXT-o} \ - depfile=sub/conftest.Po tmpdepfile=sub/conftest.TPo \ - $SHELL ./depcomp $depcc -c -o sub/conftest.${OBJEXT-o} sub/conftest.c \ - >/dev/null 2>conftest.err && - grep sub/conftst6.h sub/conftest.Po > /dev/null 2>&1 && - grep sub/conftest.${OBJEXT-o} sub/conftest.Po > /dev/null 2>&1 && - ${MAKE-make} -s -f confmf > /dev/null 2>&1; then - # icc doesn't choke on unknown options, it will just issue warnings - # or remarks (even with -Werror). So we grep stderr for any message - # that says an option was ignored or not supported. - # When given -MP, icc 7.0 and 7.1 complain thusly: - # icc: Command line warning: ignoring option '-M'; no argument required - # The diagnosis changed in icc 8.0: - # icc: Command line remark: option '-MP' not supported - if (grep 'ignoring option' conftest.err || - grep 'not supported' conftest.err) >/dev/null 2>&1; then :; else - am_cv_CC_dependencies_compiler_type=$depmode - break - fi - fi - done - - cd .. - rm -rf conftest.dir -else - am_cv_CC_dependencies_compiler_type=none -fi - -fi -{ $as_echo "$as_me:$LINENO: result: $am_cv_CC_dependencies_compiler_type" >&5 -$as_echo "$am_cv_CC_dependencies_compiler_type" >&6; } -CCDEPMODE=depmode=$am_cv_CC_dependencies_compiler_type - - - -if - test "x$enable_dependency_tracking" != xno \ - && test "$am_cv_CC_dependencies_compiler_type" = gcc3; then - am__fastdepCC_TRUE= - am__fastdepCC_FALSE='#' -else - am__fastdepCC_TRUE='#' - am__fastdepCC_FALSE= -fi - - if test "x$CC" != xcc; then { $as_echo "$as_me:$LINENO: checking whether $CC and cc understand -c and -o together" >&5 $as_echo_n "checking whether $CC and cc understand -c and -o together... " >&6; } @@ -21685,438 +20939,10 @@ else fi -{ $as_echo "$as_me:$LINENO: checking for ANSI C header files" >&5 -$as_echo_n "checking for ANSI C header files... " >&6; } -if test "${ac_cv_header_stdc+set}" = set; then - $as_echo_n "(cached) " >&6 -else - cat >conftest.$ac_ext <<_ACEOF -/* confdefs.h. */ -_ACEOF -cat confdefs.h >>conftest.$ac_ext -cat >>conftest.$ac_ext <<_ACEOF -/* end confdefs.h. */ -#include <stdlib.h> -#include <stdarg.h> -#include <string.h> -#include <float.h> - -int -main () -{ - - ; - return 0; -} -_ACEOF -rm -f conftest.$ac_objext -if { (ac_try="$ac_compile" -case "(($ac_try" in - *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; - *) ac_try_echo=$ac_try;; -esac -eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" -$as_echo "$ac_try_echo") >&5 - (eval "$ac_compile") 2>conftest.er1 - ac_status=$? - grep -v '^ *+' conftest.er1 >conftest.err - rm -f conftest.er1 - cat conftest.err >&5 - $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); } && { - test -z "$ac_c_werror_flag" || - test ! -s conftest.err - } && test -s conftest.$ac_objext; then - ac_cv_header_stdc=yes -else - $as_echo "$as_me: failed program was:" >&5 -sed 's/^/| /' conftest.$ac_ext >&5 - - ac_cv_header_stdc=no -fi - -rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext - -if test $ac_cv_header_stdc = yes; then - # SunOS 4.x string.h does not declare mem*, contrary to ANSI. - cat >conftest.$ac_ext <<_ACEOF -/* confdefs.h. */ -_ACEOF -cat confdefs.h >>conftest.$ac_ext -cat >>conftest.$ac_ext <<_ACEOF -/* end confdefs.h. */ -#include <string.h> - -_ACEOF -if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | - $EGREP "memchr" >/dev/null 2>&1; then - : -else - ac_cv_header_stdc=no -fi -rm -f conftest* - -fi - -if test $ac_cv_header_stdc = yes; then - # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI. - cat >conftest.$ac_ext <<_ACEOF -/* confdefs.h. */ -_ACEOF -cat confdefs.h >>conftest.$ac_ext -cat >>conftest.$ac_ext <<_ACEOF -/* end confdefs.h. */ -#include <stdlib.h> - -_ACEOF -if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | - $EGREP "free" >/dev/null 2>&1; then - : -else - ac_cv_header_stdc=no -fi -rm -f conftest* - -fi - -if test $ac_cv_header_stdc = yes; then - # /bin/cc in Irix-4.0.5 gets non-ANSI ctype macros unless using -ansi. - if test "$cross_compiling" = yes; then - : -else - cat >conftest.$ac_ext <<_ACEOF -/* confdefs.h. */ -_ACEOF -cat confdefs.h >>conftest.$ac_ext -cat >>conftest.$ac_ext <<_ACEOF -/* end confdefs.h. */ -#include <ctype.h> -#include <stdlib.h> -#if ((' ' & 0x0FF) == 0x020) -# define ISLOWER(c) ('a' <= (c) && (c) <= 'z') -# define TOUPPER(c) (ISLOWER(c) ? 'A' + ((c) - 'a') : (c)) -#else -# define ISLOWER(c) \ - (('a' <= (c) && (c) <= 'i') \ - || ('j' <= (c) && (c) <= 'r') \ - || ('s' <= (c) && (c) <= 'z')) -# define TOUPPER(c) (ISLOWER(c) ? ((c) | 0x40) : (c)) -#endif - -#define XOR(e, f) (((e) && !(f)) || (!(e) && (f))) -int -main () -{ - int i; - for (i = 0; i < 256; i++) - if (XOR (islower (i), ISLOWER (i)) - || toupper (i) != TOUPPER (i)) - return 2; - return 0; -} -_ACEOF -rm -f conftest$ac_exeext -if { (ac_try="$ac_link" -case "(($ac_try" in - *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; - *) ac_try_echo=$ac_try;; -esac -eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" -$as_echo "$ac_try_echo") >&5 - (eval "$ac_link") 2>&5 - ac_status=$? - $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); } && { ac_try='./conftest$ac_exeext' - { (case "(($ac_try" in - *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; - *) ac_try_echo=$ac_try;; -esac -eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" -$as_echo "$ac_try_echo") >&5 - (eval "$ac_try") 2>&5 - ac_status=$? - $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); }; }; then - : -else - $as_echo "$as_me: program exited with status $ac_status" >&5 -$as_echo "$as_me: failed program was:" >&5 -sed 's/^/| /' conftest.$ac_ext >&5 - -( exit $ac_status ) -ac_cv_header_stdc=no -fi -rm -rf conftest.dSYM -rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext -fi - - -fi -fi -{ $as_echo "$as_me:$LINENO: result: $ac_cv_header_stdc" >&5 -$as_echo "$ac_cv_header_stdc" >&6; } -if test $ac_cv_header_stdc = yes; then - -cat >>confdefs.h <<\_ACEOF -#define STDC_HEADERS 1 -_ACEOF - -fi - - -for ac_header in sys/mman.h -do -as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh` -if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then - { $as_echo "$as_me:$LINENO: checking for $ac_header" >&5 -$as_echo_n "checking for $ac_header... " >&6; } -if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then - $as_echo_n "(cached) " >&6 -fi -ac_res=`eval 'as_val=${'$as_ac_Header'} - $as_echo "$as_val"'` - { $as_echo "$as_me:$LINENO: result: $ac_res" >&5 -$as_echo "$ac_res" >&6; } -else - # Is the header compilable? -{ $as_echo "$as_me:$LINENO: checking $ac_header usability" >&5 -$as_echo_n "checking $ac_header usability... " >&6; } -cat >conftest.$ac_ext <<_ACEOF -/* confdefs.h. */ -_ACEOF -cat confdefs.h >>conftest.$ac_ext -cat >>conftest.$ac_ext <<_ACEOF -/* end confdefs.h. */ -$ac_includes_default -#include <$ac_header> -_ACEOF -rm -f conftest.$ac_objext -if { (ac_try="$ac_compile" -case "(($ac_try" in - *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; - *) ac_try_echo=$ac_try;; -esac -eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" -$as_echo "$ac_try_echo") >&5 - (eval "$ac_compile") 2>conftest.er1 - ac_status=$? - grep -v '^ *+' conftest.er1 >conftest.err - rm -f conftest.er1 - cat conftest.err >&5 - $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); } && { - test -z "$ac_c_werror_flag" || - test ! -s conftest.err - } && test -s conftest.$ac_objext; then - ac_header_compiler=yes -else - $as_echo "$as_me: failed program was:" >&5 -sed 's/^/| /' conftest.$ac_ext >&5 - - ac_header_compiler=no -fi - -rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext -{ $as_echo "$as_me:$LINENO: result: $ac_header_compiler" >&5 -$as_echo "$ac_header_compiler" >&6; } - -# Is the header present? -{ $as_echo "$as_me:$LINENO: checking $ac_header presence" >&5 -$as_echo_n "checking $ac_header presence... " >&6; } -cat >conftest.$ac_ext <<_ACEOF -/* confdefs.h. */ -_ACEOF -cat confdefs.h >>conftest.$ac_ext -cat >>conftest.$ac_ext <<_ACEOF -/* end confdefs.h. */ -#include <$ac_header> -_ACEOF -if { (ac_try="$ac_cpp conftest.$ac_ext" -case "(($ac_try" in - *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; - *) ac_try_echo=$ac_try;; -esac -eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" -$as_echo "$ac_try_echo") >&5 - (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1 - ac_status=$? - grep -v '^ *+' conftest.er1 >conftest.err - rm -f conftest.er1 - cat conftest.err >&5 - $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); } >/dev/null && { - test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" || - test ! -s conftest.err - }; then - ac_header_preproc=yes -else - $as_echo "$as_me: failed program was:" >&5 -sed 's/^/| /' conftest.$ac_ext >&5 - - ac_header_preproc=no -fi - -rm -f conftest.err conftest.$ac_ext -{ $as_echo "$as_me:$LINENO: result: $ac_header_preproc" >&5 -$as_echo "$ac_header_preproc" >&6; } - -# So? What about this header? -case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in - yes:no: ) - { $as_echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5 -$as_echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;} - { $as_echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5 -$as_echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;} - ac_header_preproc=yes - ;; - no:yes:* ) - { $as_echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5 -$as_echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;} - { $as_echo "$as_me:$LINENO: WARNING: $ac_header: check for missing prerequisite headers?" >&5 -$as_echo "$as_me: WARNING: $ac_header: check for missing prerequisite headers?" >&2;} - { $as_echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5 -$as_echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;} - { $as_echo "$as_me:$LINENO: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&5 -$as_echo "$as_me: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&2;} - { $as_echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5 -$as_echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;} - { $as_echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 -$as_echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} - ( cat <<\_ASBOX -## ---------------------------------------------------------------------- ## -## Report this to https://bugs.freedesktop.org/enter_bug.cgi?product=xorg ## -## ---------------------------------------------------------------------- ## -_ASBOX - ) | sed "s/^/$as_me: WARNING: /" >&2 - ;; -esac -{ $as_echo "$as_me:$LINENO: checking for $ac_header" >&5 -$as_echo_n "checking for $ac_header... " >&6; } -if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then - $as_echo_n "(cached) " >&6 -else - eval "$as_ac_Header=\$ac_header_preproc" -fi -ac_res=`eval 'as_val=${'$as_ac_Header'} - $as_echo "$as_val"'` - { $as_echo "$as_me:$LINENO: result: $ac_res" >&5 -$as_echo "$ac_res" >&6; } - -fi -if test `eval 'as_val=${'$as_ac_Header'} - $as_echo "$as_val"'` = yes; then - cat >>confdefs.h <<_ACEOF -#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1 -_ACEOF - -fi - -done - - -for ac_func in mprotect -do -as_ac_var=`$as_echo "ac_cv_func_$ac_func" | $as_tr_sh` -{ $as_echo "$as_me:$LINENO: checking for $ac_func" >&5 -$as_echo_n "checking for $ac_func... " >&6; } -if { as_var=$as_ac_var; eval "test \"\${$as_var+set}\" = set"; }; then - $as_echo_n "(cached) " >&6 -else - cat >conftest.$ac_ext <<_ACEOF -/* confdefs.h. */ -_ACEOF -cat confdefs.h >>conftest.$ac_ext -cat >>conftest.$ac_ext <<_ACEOF -/* end confdefs.h. */ -/* Define $ac_func to an innocuous variant, in case <limits.h> declares $ac_func. - For example, HP-UX 11i <limits.h> declares gettimeofday. */ -#define $ac_func innocuous_$ac_func - -/* System header to define __stub macros and hopefully few prototypes, - which can conflict with char $ac_func (); below. - Prefer <limits.h> to <assert.h> if __STDC__ is defined, since - <limits.h> exists even on freestanding compilers. */ - -#ifdef __STDC__ -# include <limits.h> -#else -# include <assert.h> -#endif - -#undef $ac_func - -/* Override any GCC internal prototype to avoid an error. - Use char because int might match the return type of a GCC - builtin and then its argument prototype would still apply. */ -#ifdef __cplusplus -extern "C" -#endif -char $ac_func (); -/* The GNU C library defines this for functions which it implements - to always fail with ENOSYS. Some functions are actually named - something starting with __ and the normal name is an alias. */ -#if defined __stub_$ac_func || defined __stub___$ac_func -choke me -#endif - -int -main () -{ -return $ac_func (); - ; - return 0; -} -_ACEOF -rm -f conftest.$ac_objext conftest$ac_exeext -if { (ac_try="$ac_link" -case "(($ac_try" in - *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; - *) ac_try_echo=$ac_try;; -esac -eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" -$as_echo "$ac_try_echo") >&5 - (eval "$ac_link") 2>conftest.er1 - ac_status=$? - grep -v '^ *+' conftest.er1 >conftest.err - rm -f conftest.er1 - cat conftest.err >&5 - $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); } && { - test -z "$ac_c_werror_flag" || - test ! -s conftest.err - } && test -s conftest$ac_exeext && { - test "$cross_compiling" = yes || - $as_test_x conftest$ac_exeext - }; then - eval "$as_ac_var=yes" -else - $as_echo "$as_me: failed program was:" >&5 -sed 's/^/| /' conftest.$ac_ext >&5 - - eval "$as_ac_var=no" -fi - -rm -rf conftest.dSYM -rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ - conftest$ac_exeext conftest.$ac_ext -fi -ac_res=`eval 'as_val=${'$as_ac_var'} - $as_echo "$as_val"'` - { $as_echo "$as_me:$LINENO: result: $ac_res" >&5 -$as_echo "$ac_res" >&6; } -if test `eval 'as_val=${'$as_ac_var'} - $as_echo "$as_val"'` = yes; then - cat >>confdefs.h <<_ACEOF -#define `$as_echo "HAVE_$ac_func" | $as_tr_cpp` 1 -_ACEOF - -fi -done - - +# Define a configure option for an alternate module directory # Check whether --with-xorg-module-dir was given. if test "${with_xorg_module_dir+set}" = set; then @@ -22134,14 +20960,6 @@ else fi -# Check whether --enable-video-debug was given. -if test "${enable_video_debug+set}" = set; then - enableval=$enable_video_debug; VIDEO_DEBUG="$enableval" -else - VIDEO_DEBUG=no -fi - - # Check whether --enable-xvmc was given. if test "${enable_xvmc+set}" = set; then enableval=$enable_xvmc; XVMC="$enableval" @@ -22158,10 +20976,11 @@ else fi -# Checks for extensions +# Store the list of server defined optional extensions in REQUIRED_MODULES + SAVE_CFLAGS="$CFLAGS" - CFLAGS="$CFLAGS -I`pkg-config --variable=sdkdir xorg-server`" + CFLAGS="$CFLAGS -I`$PKG_CONFIG --variable=sdkdir xorg-server`" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF @@ -22219,8 +21038,9 @@ $as_echo "$_EXT_CHECK" >&6; } fi + SAVE_CFLAGS="$CFLAGS" - CFLAGS="$CFLAGS -I`pkg-config --variable=sdkdir xorg-server`" + CFLAGS="$CFLAGS -I`$PKG_CONFIG --variable=sdkdir xorg-server`" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF @@ -22278,8 +21098,9 @@ $as_echo "$_EXT_CHECK" >&6; } fi + SAVE_CFLAGS="$CFLAGS" - CFLAGS="$CFLAGS -I`pkg-config --variable=sdkdir xorg-server`" + CFLAGS="$CFLAGS -I`$PKG_CONFIG --variable=sdkdir xorg-server`" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF @@ -22337,8 +21158,9 @@ $as_echo "$_EXT_CHECK" >&6; } fi + SAVE_CFLAGS="$CFLAGS" - CFLAGS="$CFLAGS -I`pkg-config --variable=sdkdir xorg-server`" + CFLAGS="$CFLAGS -I`$PKG_CONFIG --variable=sdkdir xorg-server`" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF @@ -22396,7 +21218,7 @@ $as_echo "$_EXT_CHECK" >&6; } fi -# Checks for pkg-config packages +# Obtain compiler/linker options for the driver dependencies pkg_failed=no { $as_echo "$as_me:$LINENO: checking for XORG" >&5 @@ -22731,91 +21553,6 @@ $as_echo "yes" >&6; } : fi -pkg_failed=no -{ $as_echo "$as_me:$LINENO: checking for XEXT" >&5 -$as_echo_n "checking for XEXT... " >&6; } - -if test -n "$PKG_CONFIG"; then - if test -n "$XEXT_CFLAGS"; then - pkg_cv_XEXT_CFLAGS="$XEXT_CFLAGS" - else - if test -n "$PKG_CONFIG" && \ - { ($as_echo "$as_me:$LINENO: \$PKG_CONFIG --exists --print-errors \"xextproto >= 7.0.99.1\"") >&5 - ($PKG_CONFIG --exists --print-errors "xextproto >= 7.0.99.1") 2>&5 - ac_status=$? - $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); }; then - pkg_cv_XEXT_CFLAGS=`$PKG_CONFIG --cflags "xextproto >= 7.0.99.1" 2>/dev/null` -else - pkg_failed=yes -fi - fi -else - pkg_failed=untried -fi -if test -n "$PKG_CONFIG"; then - if test -n "$XEXT_LIBS"; then - pkg_cv_XEXT_LIBS="$XEXT_LIBS" - else - if test -n "$PKG_CONFIG" && \ - { ($as_echo "$as_me:$LINENO: \$PKG_CONFIG --exists --print-errors \"xextproto >= 7.0.99.1\"") >&5 - ($PKG_CONFIG --exists --print-errors "xextproto >= 7.0.99.1") 2>&5 - ac_status=$? - $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); }; then - pkg_cv_XEXT_LIBS=`$PKG_CONFIG --libs "xextproto >= 7.0.99.1" 2>/dev/null` -else - pkg_failed=yes -fi - fi -else - pkg_failed=untried -fi - - - -if test $pkg_failed = yes; then - -if $PKG_CONFIG --atleast-pkgconfig-version 0.20; then - _pkg_short_errors_supported=yes -else - _pkg_short_errors_supported=no -fi - if test $_pkg_short_errors_supported = yes; then - XEXT_PKG_ERRORS=`$PKG_CONFIG --short-errors --errors-to-stdout --print-errors "xextproto >= 7.0.99.1"` - else - XEXT_PKG_ERRORS=`$PKG_CONFIG --errors-to-stdout --print-errors "xextproto >= 7.0.99.1"` - fi - # Put the nasty error message in config.log where it belongs - echo "$XEXT_PKG_ERRORS" >&5 - - { $as_echo "$as_me:$LINENO: result: no" >&5 -$as_echo "no" >&6; } - HAVE_XEXTPROTO_71="no" -elif test $pkg_failed = untried; then - HAVE_XEXTPROTO_71="no" -else - XEXT_CFLAGS=$pkg_cv_XEXT_CFLAGS - XEXT_LIBS=$pkg_cv_XEXT_LIBS - { $as_echo "$as_me:$LINENO: result: yes" >&5 -$as_echo "yes" >&6; } - HAVE_XEXTPROTO_71="yes"; -cat >>confdefs.h <<\_ACEOF -#define HAVE_XEXTPROTO_71 1 -_ACEOF - -fi - - -if test "$HAVE_XEXTPROTO_71" = "yes" ; then - HAVE_XEXTPROTO_71_TRUE= - HAVE_XEXTPROTO_71_FALSE='#' -else - HAVE_XEXTPROTO_71_TRUE='#' - HAVE_XEXTPROTO_71_FALSE= -fi - - sdkdir=$(pkg-config --variable=sdkdir xorg-server) save_CFLAGS="$CFLAGS" @@ -22942,12 +21679,12 @@ if test -n "$PKG_CONFIG"; then pkg_cv_DRI_CFLAGS="$DRI_CFLAGS" else if test -n "$PKG_CONFIG" && \ - { ($as_echo "$as_me:$LINENO: \$PKG_CONFIG --exists --print-errors \"xf86driproto glproto\"") >&5 - ($PKG_CONFIG --exists --print-errors "xf86driproto glproto") 2>&5 + { ($as_echo "$as_me:$LINENO: \$PKG_CONFIG --exists --print-errors \"xf86driproto\"") >&5 + ($PKG_CONFIG --exists --print-errors "xf86driproto") 2>&5 ac_status=$? $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; then - pkg_cv_DRI_CFLAGS=`$PKG_CONFIG --cflags "xf86driproto glproto" 2>/dev/null` + pkg_cv_DRI_CFLAGS=`$PKG_CONFIG --cflags "xf86driproto" 2>/dev/null` else pkg_failed=yes fi @@ -22960,12 +21697,12 @@ if test -n "$PKG_CONFIG"; then pkg_cv_DRI_LIBS="$DRI_LIBS" else if test -n "$PKG_CONFIG" && \ - { ($as_echo "$as_me:$LINENO: \$PKG_CONFIG --exists --print-errors \"xf86driproto glproto\"") >&5 - ($PKG_CONFIG --exists --print-errors "xf86driproto glproto") 2>&5 + { ($as_echo "$as_me:$LINENO: \$PKG_CONFIG --exists --print-errors \"xf86driproto\"") >&5 + ($PKG_CONFIG --exists --print-errors "xf86driproto") 2>&5 ac_status=$? $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; then - pkg_cv_DRI_LIBS=`$PKG_CONFIG --libs "xf86driproto glproto" 2>/dev/null` + pkg_cv_DRI_LIBS=`$PKG_CONFIG --libs "xf86driproto" 2>/dev/null` else pkg_failed=yes fi @@ -22984,14 +21721,14 @@ else _pkg_short_errors_supported=no fi if test $_pkg_short_errors_supported = yes; then - DRI_PKG_ERRORS=`$PKG_CONFIG --short-errors --errors-to-stdout --print-errors "xf86driproto glproto"` + DRI_PKG_ERRORS=`$PKG_CONFIG --short-errors --errors-to-stdout --print-errors "xf86driproto"` else - DRI_PKG_ERRORS=`$PKG_CONFIG --errors-to-stdout --print-errors "xf86driproto glproto"` + DRI_PKG_ERRORS=`$PKG_CONFIG --errors-to-stdout --print-errors "xf86driproto"` fi # Put the nasty error message in config.log where it belongs echo "$DRI_PKG_ERRORS" >&5 - { { $as_echo "$as_me:$LINENO: error: Package requirements (xf86driproto glproto) were not met: + { { $as_echo "$as_me:$LINENO: error: Package requirements (xf86driproto) were not met: $DRI_PKG_ERRORS @@ -23002,7 +21739,7 @@ Alternatively, you may set the environment variables DRI_CFLAGS and DRI_LIBS to avoid the need to call pkg-config. See the pkg-config man page for more details. " >&5 -$as_echo "$as_me: error: Package requirements (xf86driproto glproto) were not met: +$as_echo "$as_me: error: Package requirements (xf86driproto) were not met: $DRI_PKG_ERRORS @@ -23055,24 +21792,6 @@ _ACEOF fi - - -if test x$VIDEO_DEBUG = xyes; then - VIDEO_DEBUG_TRUE= - VIDEO_DEBUG_FALSE='#' -else - VIDEO_DEBUG_TRUE='#' - VIDEO_DEBUG_FALSE= -fi - -if test "$VIDEO_DEBUG" = yes; then - -cat >>confdefs.h <<\_ACEOF -#define VIDEO_DEBUG 1 -_ACEOF - -fi - if test "$XVMC" = yes; then pkg_failed=no @@ -23186,187 +21905,11 @@ _ACEOF fi - - DRIVER_NAME=intel - -if test x$XORG_SGML_PATH = x ; then - XORG_SGML_PATH=$prefix/share/sgml -fi -HAVE_DEFS_ENT= - -if test x"$cross_compiling" = x"yes" ; then - HAVE_DEFS_ENT=no -else - as_ac_File=`$as_echo "ac_cv_file_$XORG_SGML_PATH/X11/defs.ent" | $as_tr_sh` -{ $as_echo "$as_me:$LINENO: checking for $XORG_SGML_PATH/X11/defs.ent" >&5 -$as_echo_n "checking for $XORG_SGML_PATH/X11/defs.ent... " >&6; } -if { as_var=$as_ac_File; eval "test \"\${$as_var+set}\" = set"; }; then - $as_echo_n "(cached) " >&6 -else - test "$cross_compiling" = yes && - { { $as_echo "$as_me:$LINENO: error: cannot check for file existence when cross compiling" >&5 -$as_echo "$as_me: error: cannot check for file existence when cross compiling" >&2;} - { (exit 1); exit 1; }; } -if test -r "$XORG_SGML_PATH/X11/defs.ent"; then - eval "$as_ac_File=yes" -else - eval "$as_ac_File=no" -fi -fi -ac_res=`eval 'as_val=${'$as_ac_File'} - $as_echo "$as_val"'` - { $as_echo "$as_me:$LINENO: result: $ac_res" >&5 -$as_echo "$ac_res" >&6; } -if test `eval 'as_val=${'$as_ac_File'} - $as_echo "$as_val"'` = yes; then - HAVE_DEFS_ENT=yes -fi - -fi - -# Extract the first word of "linuxdoc", so it can be a program name with args. -set dummy linuxdoc; ac_word=$2 -{ $as_echo "$as_me:$LINENO: checking for $ac_word" >&5 -$as_echo_n "checking for $ac_word... " >&6; } -if test "${ac_cv_path_LINUXDOC+set}" = set; then - $as_echo_n "(cached) " >&6 -else - case $LINUXDOC in - [\\/]* | ?:[\\/]*) - ac_cv_path_LINUXDOC="$LINUXDOC" # Let the user override the test with a path. - ;; - *) - as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -for as_dir in $PATH -do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do - if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then - ac_cv_path_LINUXDOC="$as_dir/$ac_word$ac_exec_ext" - $as_echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 - fi -done -done -IFS=$as_save_IFS - - ;; -esac -fi -LINUXDOC=$ac_cv_path_LINUXDOC -if test -n "$LINUXDOC"; then - { $as_echo "$as_me:$LINENO: result: $LINUXDOC" >&5 -$as_echo "$LINUXDOC" >&6; } -else - { $as_echo "$as_me:$LINENO: result: no" >&5 -$as_echo "no" >&6; } -fi - - -# Extract the first word of "ps2pdf", so it can be a program name with args. -set dummy ps2pdf; ac_word=$2 -{ $as_echo "$as_me:$LINENO: checking for $ac_word" >&5 -$as_echo_n "checking for $ac_word... " >&6; } -if test "${ac_cv_path_PS2PDF+set}" = set; then - $as_echo_n "(cached) " >&6 -else - case $PS2PDF in - [\\/]* | ?:[\\/]*) - ac_cv_path_PS2PDF="$PS2PDF" # Let the user override the test with a path. - ;; - *) - as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -for as_dir in $PATH -do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do - if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then - ac_cv_path_PS2PDF="$as_dir/$ac_word$ac_exec_ext" - $as_echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 - fi -done -done -IFS=$as_save_IFS - - ;; -esac -fi -PS2PDF=$ac_cv_path_PS2PDF -if test -n "$PS2PDF"; then - { $as_echo "$as_me:$LINENO: result: $PS2PDF" >&5 -$as_echo "$PS2PDF" >&6; } -else - { $as_echo "$as_me:$LINENO: result: no" >&5 -$as_echo "no" >&6; } -fi - - - -{ $as_echo "$as_me:$LINENO: checking whether to build documentation" >&5 -$as_echo_n "checking whether to build documentation... " >&6; } - -if test x$HAVE_DEFS_ENT != x && test x$LINUXDOC != x ; then - BUILDDOC=yes -else - BUILDDOC=no -fi - - - -if test x$BUILDDOC = xyes; then - BUILD_LINUXDOC_TRUE= - BUILD_LINUXDOC_FALSE='#' -else - BUILD_LINUXDOC_TRUE='#' - BUILD_LINUXDOC_FALSE= -fi - - -{ $as_echo "$as_me:$LINENO: result: $BUILDDOC" >&5 -$as_echo "$BUILDDOC" >&6; } - -{ $as_echo "$as_me:$LINENO: checking whether to build pdf documentation" >&5 -$as_echo_n "checking whether to build pdf documentation... " >&6; } - -if test x$PS2PDF != x && test x$BUILD_PDFDOC != xno; then - BUILDPDFDOC=yes -else - BUILDPDFDOC=no -fi - - - -if test x$BUILDPDFDOC = xyes; then - BUILD_PDFDOC_TRUE= - BUILD_PDFDOC_FALSE='#' -else - BUILD_PDFDOC_TRUE='#' - BUILD_PDFDOC_FALSE= -fi - - -{ $as_echo "$as_me:$LINENO: result: $BUILDPDFDOC" >&5 -$as_echo "$BUILDPDFDOC" >&6; } - -MAKE_TEXT="SGML_SEARCH_PATH=$XORG_SGML_PATH GROFF_NO_SGR=y $LINUXDOC -B txt" -MAKE_PS="SGML_SEARCH_PATH=$XORG_SGML_PATH $LINUXDOC -B latex --papersize=letter --output=ps" -MAKE_PDF="$PS2PDF" -MAKE_HTML="SGML_SEARCH_PATH=$XORG_SGML_PATH $LINUXDOC -B html --split=0" - - - - - - - -ac_config_files="$ac_config_files Makefile uxa/Makefile src/Makefile src/xvmc/Makefile src/xvmc/shader/Makefile src/xvmc/shader/mc/Makefile src/xvmc/shader/vld/Makefile src/bios_reader/Makefile src/ch7017/Makefile src/ch7xxx/Makefile src/ivch/Makefile src/reg_dumper/Makefile src/sil164/Makefile src/tfp410/Makefile man/Makefile src/render_program/Makefile" +ac_config_files="$ac_config_files Makefile uxa/Makefile src/Makefile src/xvmc/Makefile src/xvmc/shader/Makefile src/xvmc/shader/mc/Makefile src/xvmc/shader/vld/Makefile src/bios_reader/Makefile src/ch7017/Makefile src/ch7xxx/Makefile src/ivch/Makefile src/reg_dumper/Makefile src/sil164/Makefile src/tfp410/Makefile src/legacy/Makefile src/legacy/i810/Makefile src/legacy/i810/xvmc/Makefile man/Makefile src/render_program/Makefile" cat >confcache <<\_ACEOF # This file is a shell script that caches the results of configure @@ -23493,13 +22036,6 @@ $as_echo "$as_me: error: conditional \"am__fastdepCXX\" was never defined. Usually this means the macro was only invoked conditionally." >&2;} { (exit 1); exit 1; }; } fi -if test -z "${am__fastdepCC_TRUE}" && test -z "${am__fastdepCC_FALSE}"; then - { { $as_echo "$as_me:$LINENO: error: conditional \"am__fastdepCC\" was never defined. -Usually this means the macro was only invoked conditionally." >&5 -$as_echo "$as_me: error: conditional \"am__fastdepCC\" was never defined. -Usually this means the macro was only invoked conditionally." >&2;} - { (exit 1); exit 1; }; } -fi if test -z "${HAVE_GEN4ASM_TRUE}" && test -z "${HAVE_GEN4ASM_FALSE}"; then { { $as_echo "$as_me:$LINENO: error: conditional \"HAVE_GEN4ASM\" was never defined. Usually this means the macro was only invoked conditionally." >&5 @@ -23507,13 +22043,6 @@ $as_echo "$as_me: error: conditional \"HAVE_GEN4ASM\" was never defined. Usually this means the macro was only invoked conditionally." >&2;} { (exit 1); exit 1; }; } fi -if test -z "${HAVE_XEXTPROTO_71_TRUE}" && test -z "${HAVE_XEXTPROTO_71_FALSE}"; then - { { $as_echo "$as_me:$LINENO: error: conditional \"HAVE_XEXTPROTO_71\" was never defined. -Usually this means the macro was only invoked conditionally." >&5 -$as_echo "$as_me: error: conditional \"HAVE_XEXTPROTO_71\" was never defined. -Usually this means the macro was only invoked conditionally." >&2;} - { (exit 1); exit 1; }; } -fi if test -z "${DRI_TRUE}" && test -z "${DRI_FALSE}"; then { { $as_echo "$as_me:$LINENO: error: conditional \"DRI\" was never defined. Usually this means the macro was only invoked conditionally." >&5 @@ -23521,13 +22050,6 @@ $as_echo "$as_me: error: conditional \"DRI\" was never defined. Usually this means the macro was only invoked conditionally." >&2;} { (exit 1); exit 1; }; } fi -if test -z "${VIDEO_DEBUG_TRUE}" && test -z "${VIDEO_DEBUG_FALSE}"; then - { { $as_echo "$as_me:$LINENO: error: conditional \"VIDEO_DEBUG\" was never defined. -Usually this means the macro was only invoked conditionally." >&5 -$as_echo "$as_me: error: conditional \"VIDEO_DEBUG\" was never defined. -Usually this means the macro was only invoked conditionally." >&2;} - { (exit 1); exit 1; }; } -fi if test -z "${XVMC_TRUE}" && test -z "${XVMC_FALSE}"; then { { $as_echo "$as_me:$LINENO: error: conditional \"XVMC\" was never defined. Usually this means the macro was only invoked conditionally." >&5 @@ -23542,20 +22064,6 @@ $as_echo "$as_me: error: conditional \"KMS_ONLY\" was never defined. Usually this means the macro was only invoked conditionally." >&2;} { (exit 1); exit 1; }; } fi -if test -z "${BUILD_LINUXDOC_TRUE}" && test -z "${BUILD_LINUXDOC_FALSE}"; then - { { $as_echo "$as_me:$LINENO: error: conditional \"BUILD_LINUXDOC\" was never defined. -Usually this means the macro was only invoked conditionally." >&5 -$as_echo "$as_me: error: conditional \"BUILD_LINUXDOC\" was never defined. -Usually this means the macro was only invoked conditionally." >&2;} - { (exit 1); exit 1; }; } -fi -if test -z "${BUILD_PDFDOC_TRUE}" && test -z "${BUILD_PDFDOC_FALSE}"; then - { { $as_echo "$as_me:$LINENO: error: conditional \"BUILD_PDFDOC\" was never defined. -Usually this means the macro was only invoked conditionally." >&5 -$as_echo "$as_me: error: conditional \"BUILD_PDFDOC\" was never defined. -Usually this means the macro was only invoked conditionally." >&2;} - { (exit 1); exit 1; }; } -fi : ${CONFIG_STATUS=./config.status} ac_write_fail=0 @@ -23878,7 +22386,7 @@ exec 6>&1 # report actual input values of CONFIG_FILES etc. instead of their # values after options handling. ac_log=" -This file was extended by xf86-video-intel $as_me 2.9.1, which was +This file was extended by xf86-video-intel $as_me 2.12.0, which was generated by GNU Autoconf 2.62. Invocation command line was CONFIG_FILES = $CONFIG_FILES @@ -23931,7 +22439,7 @@ Report bugs to <bug-autoconf@gnu.org>." _ACEOF cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 ac_cs_version="\\ -xf86-video-intel config.status 2.9.1 +xf86-video-intel config.status 2.12.0 configured by $0, generated by GNU Autoconf 2.62, with options \\"`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`\\" @@ -24069,6 +22577,9 @@ do "src/reg_dumper/Makefile") CONFIG_FILES="$CONFIG_FILES src/reg_dumper/Makefile" ;; "src/sil164/Makefile") CONFIG_FILES="$CONFIG_FILES src/sil164/Makefile" ;; "src/tfp410/Makefile") CONFIG_FILES="$CONFIG_FILES src/tfp410/Makefile" ;; + "src/legacy/Makefile") CONFIG_FILES="$CONFIG_FILES src/legacy/Makefile" ;; + "src/legacy/i810/Makefile") CONFIG_FILES="$CONFIG_FILES src/legacy/i810/Makefile" ;; + "src/legacy/i810/xvmc/Makefile") CONFIG_FILES="$CONFIG_FILES src/legacy/i810/xvmc/Makefile" ;; "man/Makefile") CONFIG_FILES="$CONFIG_FILES man/Makefile" ;; "src/render_program/Makefile") CONFIG_FILES="$CONFIG_FILES src/render_program/Makefile" ;; diff --git a/driver/xf86-video-intel/configure.ac b/driver/xf86-video-intel/configure.ac index 58c9430db..be664cdb6 100644 --- a/driver/xf86-video-intel/configure.ac +++ b/driver/xf86-video-intel/configure.ac @@ -20,81 +20,73 @@ # # Process this file with autoconf to produce a configure script -AC_PREREQ(2.57) +# Initialize Autoconf +AC_PREREQ([2.60]) AC_INIT([xf86-video-intel], - 2.9.1, + [2.12.0], [https://bugs.freedesktop.org/enter_bug.cgi?product=xorg], - xf86-video-intel) - + [xf86-video-intel]) AC_CONFIG_SRCDIR([Makefile.am]) AM_CONFIG_HEADER([config.h]) AC_CONFIG_AUX_DIR(.) +# Initialize Automake AM_INIT_AUTOMAKE([foreign dist-bzip2]) - AM_MAINTAINER_MODE -# Require xorg-macros: XORG_DEFAULT_OPTIONS -m4_ifndef([XORG_MACROS_VERSION], - [m4_fatal([must install xorg-macros 1.3 or later before running autoconf/autogen])]) -XORG_MACROS_VERSION(1.3) +# Require X.Org macros 1.8 or later for MAN_SUBSTS set by XORG_MANPAGE_SECTIONS +m4_ifndef([XORG_MACROS_VERSION], + [m4_fatal([must install xorg-macros 1.8 or later before running autoconf/autogen])]) +XORG_MACROS_VERSION(1.8) XORG_DEFAULT_OPTIONS -# Checks for programs. +# Initialize libtool AC_DISABLE_STATIC AC_PROG_LIBTOOL -AC_PROG_CC -AM_PROG_CC_C_O -PKG_CHECK_MODULES(GEN4ASM, [intel-gen4asm >= 1.0], [gen4asm=yes], [gen4asm=no]) +PKG_CHECK_MODULES(GEN4ASM, [intel-gen4asm >= 1.2], [gen4asm=yes], [gen4asm=no]) AM_CONDITIONAL(HAVE_GEN4ASM, test x$gen4asm = xyes) -AC_HEADER_STDC -AC_CHECK_HEADERS(sys/mman.h) -AC_CHECK_FUNCS(mprotect) - AH_TOP([#include "xorg-server.h"]) +# Define a configure option for an alternate module directory AC_ARG_WITH(xorg-module-dir, - AC_HELP_STRING([--with-xorg-module-dir=DIR], + AS_HELP_STRING([--with-xorg-module-dir=DIR], [Default xorg module directory [[default=$libdir/xorg/modules]]]), [moduledir="$withval"], [moduledir="$libdir/xorg/modules"]) -AC_ARG_ENABLE(dri, AC_HELP_STRING([--disable-dri], +AC_ARG_ENABLE(dri, AS_HELP_STRING([--disable-dri], [Disable DRI support [[default=auto]]]), [DRI="$enableval"], [DRI=auto]) -AC_ARG_ENABLE(video-debug, AC_HELP_STRING([--enable-video-debug], - [Enable video debugging support [[default=no]]]), - [VIDEO_DEBUG="$enableval"], - [VIDEO_DEBUG=no]) - -AC_ARG_ENABLE(xvmc, AC_HELP_STRING([--disable-xvmc], +AC_ARG_ENABLE(xvmc, AS_HELP_STRING([--disable-xvmc], [Disable XvMC support [[default=yes]]]), [XVMC="$enableval"], [XVMC=yes]) -AC_ARG_ENABLE(kms-only, AC_HELP_STRING([--enable-kms-only], +AC_ARG_ENABLE(kms-only, AS_HELP_STRING([--enable-kms-only], [Assume KMS support [[default=no]]]), [KMS_ONLY="$enableval"], [KMS_ONLY=no]) -# Checks for extensions +AC_ARG_ENABLE(debug, + AS_HELP_STRING([--enable-debug], + [Enables internal debugging [[default=yes]]]), + [DEBUG="$enableval"], + [DEBUG=yes]) + +# Store the list of server defined optional extensions in REQUIRED_MODULES XORG_DRIVER_CHECK_EXT(RANDR, randrproto) XORG_DRIVER_CHECK_EXT(RENDER, renderproto) XORG_DRIVER_CHECK_EXT(XF86DRI, xextproto x11) XORG_DRIVER_CHECK_EXT(DPMSExtension, xextproto) -# Checks for pkg-config packages +# Obtain compiler/linker options for the driver dependencies PKG_CHECK_MODULES(XORG, [xorg-server >= 1.6 xproto fontsproto $REQUIRED_MODULES]) PKG_CHECK_MODULES(DRM, [libdrm >= 2.4.11]) PKG_CHECK_MODULES(PCIACCESS, [pciaccess >= 0.10]) -PKG_CHECK_MODULES(XEXT, [xextproto >= 7.0.99.1], - HAVE_XEXTPROTO_71="yes"; AC_DEFINE(HAVE_XEXTPROTO_71, 1, [xextproto 7.1 available]), - HAVE_XEXTPROTO_71="no") -AM_CONDITIONAL(HAVE_XEXTPROTO_71, [ test "$HAVE_XEXTPROTO_71" = "yes" ]) sdkdir=$(pkg-config --variable=sdkdir xorg-server) @@ -125,16 +117,11 @@ CFLAGS="$save_CFLAGS $DEBUGFLAGS" AM_CONDITIONAL(DRI, test x$DRI = xyes) if test "$DRI" = yes; then - PKG_CHECK_MODULES(DRI, [xf86driproto glproto]) + PKG_CHECK_MODULES(DRI, [xf86driproto]) AC_DEFINE(XF86DRI,1,[Enable DRI driver support]) AC_DEFINE(XF86DRI_DEVEL,1,[Enable developmental DRI driver support]) fi -AM_CONDITIONAL(VIDEO_DEBUG, test x$VIDEO_DEBUG = xyes) -if test "$VIDEO_DEBUG" = yes; then - AC_DEFINE(VIDEO_DEBUG,1,[Enable debug support]) -fi - if test "$XVMC" = yes; then PKG_CHECK_MODULES(XVMCLIB, [xvmc xext xfixes dri2proto x11-xcb xcb-dri2 xcb-aux], @@ -143,38 +130,42 @@ fi AC_MSG_CHECKING([whether to include XvMC support]) AC_MSG_RESULT([$XVMC]) AM_CONDITIONAL(XVMC, test x$XVMC = xyes) -if test "$XVMC" = yes; then +if test "x$XVMC" = xyes; then AC_DEFINE(ENABLE_XVMC,1,[Enable XvMC support]) fi AM_CONDITIONAL(KMS_ONLY, test x$KMS_ONLY = xyes) -if test "$KMS_ONLY" = yes; then +if test "x$KMS_ONLY" = xyes; then AC_DEFINE(KMS_ONLY,1,[Assume KMS support]) fi -AC_SUBST([DRI_CFLAGS]) +if test "x$DEBUG" = xno; then + AC_DEFINE(NDEBUG,1,[Disable internal debugging]) +fi DRIVER_NAME=intel AC_SUBST([DRIVER_NAME]) AC_SUBST([moduledir]) -XORG_CHECK_LINUXDOC - -AC_OUTPUT([ - Makefile - uxa/Makefile - src/Makefile - src/xvmc/Makefile - src/xvmc/shader/Makefile - src/xvmc/shader/mc/Makefile - src/xvmc/shader/vld/Makefile - src/bios_reader/Makefile - src/ch7017/Makefile - src/ch7xxx/Makefile - src/ivch/Makefile - src/reg_dumper/Makefile - src/sil164/Makefile - src/tfp410/Makefile - man/Makefile - src/render_program/Makefile +AC_CONFIG_FILES([ + Makefile + uxa/Makefile + src/Makefile + src/xvmc/Makefile + src/xvmc/shader/Makefile + src/xvmc/shader/mc/Makefile + src/xvmc/shader/vld/Makefile + src/bios_reader/Makefile + src/ch7017/Makefile + src/ch7xxx/Makefile + src/ivch/Makefile + src/reg_dumper/Makefile + src/sil164/Makefile + src/tfp410/Makefile + src/legacy/Makefile + src/legacy/i810/Makefile + src/legacy/i810/xvmc/Makefile + man/Makefile + src/render_program/Makefile ]) +AC_OUTPUT diff --git a/driver/xf86-video-intel/man/Makefile.am b/driver/xf86-video-intel/man/Makefile.am index 7b687e472..9ca5ff6e2 100644 --- a/driver/xf86-video-intel/man/Makefile.am +++ b/driver/xf86-video-intel/man/Makefile.am @@ -28,23 +28,10 @@ EXTRA_DIST = $(DRIVER_NAME).man CLEANFILES = $(driverman_DATA) -# Strings to replace in man pages -XORGRELSTRING = @PACKAGE_STRING@ - XORGMANNAME = X Version 11 +# String replacements in MAN_SUBSTS now come from xorg-macros.m4 via configure -MAN_SUBSTS = \ - -e 's|__vendorversion__|"$(XORGRELSTRING)" "$(XORGMANNAME)"|' \ - -e 's|__xorgversion__|"$(XORGRELSTRING)" "$(XORGMANNAME)"|' \ - -e 's|__xservername__|Xorg|g' \ - -e 's|__xconfigfile__|xorg.conf|g' \ - -e 's|__projectroot__|$(prefix)|g' \ - -e 's|__appmansuffix__|$(APP_MAN_SUFFIX)|g' \ - -e 's|__drivermansuffix__|$(DRIVER_MAN_SUFFIX)|g' \ - -e 's|__adminmansuffix__|$(ADMIN_MAN_SUFFIX)|g' \ - -e 's|__miscmansuffix__|$(MISC_MAN_SUFFIX)|g' \ - -e 's|__filemansuffix__|$(FILE_MAN_SUFFIX)|g' SUFFIXES = .$(DRIVER_MAN_SUFFIX) .man .man.$(DRIVER_MAN_SUFFIX): - sed $(MAN_SUBSTS) < $< > $@ + $(AM_V_GEN)$(SED) $(MAN_SUBSTS) < $< > $@ diff --git a/driver/xf86-video-intel/man/Makefile.in b/driver/xf86-video-intel/man/Makefile.in index 64b843cdc..f21aada01 100644 --- a/driver/xf86-video-intel/man/Makefile.in +++ b/driver/xf86-video-intel/man/Makefile.in @@ -94,10 +94,6 @@ AUTOCONF = @AUTOCONF@ AUTOHEADER = @AUTOHEADER@ AUTOMAKE = @AUTOMAKE@ AWK = @AWK@ -BUILD_LINUXDOC_FALSE = @BUILD_LINUXDOC_FALSE@ -BUILD_LINUXDOC_TRUE = @BUILD_LINUXDOC_TRUE@ -BUILD_PDFDOC_FALSE = @BUILD_PDFDOC_FALSE@ -BUILD_PDFDOC_TRUE = @BUILD_PDFDOC_TRUE@ CC = @CC@ CCDEPMODE = @CCDEPMODE@ CFLAGS = @CFLAGS@ @@ -137,8 +133,6 @@ GEN4ASM_LIBS = @GEN4ASM_LIBS@ GREP = @GREP@ HAVE_GEN4ASM_FALSE = @HAVE_GEN4ASM_FALSE@ HAVE_GEN4ASM_TRUE = @HAVE_GEN4ASM_TRUE@ -HAVE_XEXTPROTO_71_FALSE = @HAVE_XEXTPROTO_71_FALSE@ -HAVE_XEXTPROTO_71_TRUE = @HAVE_XEXTPROTO_71_TRUE@ INSTALL_CMD = @INSTALL_CMD@ INSTALL_DATA = @INSTALL_DATA@ INSTALL_PROGRAM = @INSTALL_PROGRAM@ @@ -152,17 +146,13 @@ LIBS = @LIBS@ LIBTOOL = @LIBTOOL@ LIB_MAN_DIR = @LIB_MAN_DIR@ LIB_MAN_SUFFIX = @LIB_MAN_SUFFIX@ -LINUXDOC = @LINUXDOC@ LN_S = @LN_S@ LTLIBOBJS = @LTLIBOBJS@ MAINT = @MAINT@ MAINTAINER_MODE_FALSE = @MAINTAINER_MODE_FALSE@ MAINTAINER_MODE_TRUE = @MAINTAINER_MODE_TRUE@ MAKEINFO = @MAKEINFO@ -MAKE_HTML = @MAKE_HTML@ -MAKE_PDF = @MAKE_PDF@ -MAKE_PS = @MAKE_PS@ -MAKE_TEXT = @MAKE_TEXT@ +MAN_SUBSTS = @MAN_SUBSTS@ MISC_MAN_DIR = @MISC_MAN_DIR@ MISC_MAN_SUFFIX = @MISC_MAN_SUFFIX@ NMEDIT = @NMEDIT@ @@ -177,19 +167,15 @@ PATH_SEPARATOR = @PATH_SEPARATOR@ PCIACCESS_CFLAGS = @PCIACCESS_CFLAGS@ PCIACCESS_LIBS = @PCIACCESS_LIBS@ PKG_CONFIG = @PKG_CONFIG@ -PS2PDF = @PS2PDF@ RANLIB = @RANLIB@ SED = @SED@ SET_MAKE = @SET_MAKE@ SHELL = @SHELL@ STRIP = @STRIP@ VERSION = @VERSION@ -VIDEO_DEBUG_FALSE = @VIDEO_DEBUG_FALSE@ -VIDEO_DEBUG_TRUE = @VIDEO_DEBUG_TRUE@ -XEXT_CFLAGS = @XEXT_CFLAGS@ -XEXT_LIBS = @XEXT_LIBS@ XORG_CFLAGS = @XORG_CFLAGS@ XORG_LIBS = @XORG_LIBS@ +XORG_MAN_PAGE = @XORG_MAN_PAGE@ XVMCLIB_CFLAGS = @XVMCLIB_CFLAGS@ XVMCLIB_LIBS = @XVMCLIB_LIBS@ XVMC_FALSE = @XVMC_FALSE@ @@ -247,21 +233,7 @@ driverman_DATA = $(DRIVER_NAME).$(DRIVER_MAN_SUFFIX) EXTRA_DIST = $(DRIVER_NAME).man CLEANFILES = $(driverman_DATA) -# Strings to replace in man pages -XORGRELSTRING = @PACKAGE_STRING@ -XORGMANNAME = X Version 11 -MAN_SUBSTS = \ - -e 's|__vendorversion__|"$(XORGRELSTRING)" "$(XORGMANNAME)"|' \ - -e 's|__xorgversion__|"$(XORGRELSTRING)" "$(XORGMANNAME)"|' \ - -e 's|__xservername__|Xorg|g' \ - -e 's|__xconfigfile__|xorg.conf|g' \ - -e 's|__projectroot__|$(prefix)|g' \ - -e 's|__appmansuffix__|$(APP_MAN_SUFFIX)|g' \ - -e 's|__drivermansuffix__|$(DRIVER_MAN_SUFFIX)|g' \ - -e 's|__adminmansuffix__|$(ADMIN_MAN_SUFFIX)|g' \ - -e 's|__miscmansuffix__|$(MISC_MAN_SUFFIX)|g' \ - -e 's|__filemansuffix__|$(FILE_MAN_SUFFIX)|g' - +# String replacements in MAN_SUBSTS now come from xorg-macros.m4 via configure SUFFIXES = .$(DRIVER_MAN_SUFFIX) .man all: all-am @@ -448,7 +420,7 @@ uninstall-am: uninstall-drivermanDATA uninstall-info-am .man.$(DRIVER_MAN_SUFFIX): - sed $(MAN_SUBSTS) < $< > $@ + $(AM_V_GEN)$(SED) $(MAN_SUBSTS) < $< > $@ # Tell versions [3.59,3.63) of GNU make to not export all variables. # Otherwise a system limit (for SysV at least) may be exceeded. .NOEXPORT: diff --git a/driver/xf86-video-intel/man/intel.man b/driver/xf86-video-intel/man/intel.man index 1e8b3605e..4923c89b5 100644 --- a/driver/xf86-video-intel/man/intel.man +++ b/driver/xf86-video-intel/man/intel.man @@ -204,6 +204,20 @@ i.e. perform synchronous rendering. .IP Default: Disabled .TP +.BI "Option \*qShadow\*q \*q" boolean \*q +This option controls the use of GPU acceleration and placement of auxiliary +buffers in memory. Enabling the Shadow will disable all use of the GPU for +RENDER acceleration and force software-fallbacks for all but updating the +scan-out buffer. Hardware overlay is still supported so Xv will continue to +playback videos using the GPU, but GL will be forced to use software +rasterisation as well. This is a last resort measure for systems with +crippling bugs, such as early 8xx chipsets. It is still hoped that we will +find a workaround to enable as much hardware acceleration on those +architectures as is possible, but until then, using a shadow buffer should +maintain system stability. +.IP +Default: Disabled +.TP .BI "Option \*qSwapbuffersWait\*q \*q" boolean \*q This option controls the behavior of glXSwapBuffers and glXCopySubBufferMESA calls by GL applications. If enabled, the calls will avoid tearing by making @@ -229,6 +243,18 @@ allows the driver to automatically figure out the correct fixed panel timings. See further in the section about LVDS fixed timing for more information. .TP +.BI "Option \*qTiling\*q \*q" boolean \*q +This option controls whether memory buffers for Pixmaps are allocated in tiled mode. In +most cases (especially for complex rendering), tiling dramatically improves +performance. +.BI "Option \*qLinearFramebuffer\*q \*q" boolean \*q +This option controls whether the memory for the scanout (also known as the +front or frame buffer) is allocated in linear memory. A tiled framebuffer is +required for power conservation features, but for certain system configurations +you may wish to override this and force a linear layout. +.IP +Default: disabled +.TP .BI "Option \*qXvMC\*q \*q" boolean \*q Enable XvMC driver. Current support MPEG2 MC on 915/945 and G33 series. User should provide absolute path to libIntelXvMC.so in XvMCConfig file. diff --git a/driver/xf86-video-intel/src/Makefile.am b/driver/xf86-video-intel/src/Makefile.am index 0ae81cd79..2d20c24f6 100644 --- a/driver/xf86-video-intel/src/Makefile.am +++ b/driver/xf86-video-intel/src/Makefile.am @@ -18,7 +18,7 @@ # IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN # CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -SUBDIRS = xvmc bios_reader ch7017 ch7xxx ivch sil164 tfp410 reg_dumper render_program +SUBDIRS = xvmc ch7017 ch7xxx ivch sil164 tfp410 render_program legacy # this is obnoxious: # -module lets us name the module exactly how we want @@ -32,63 +32,43 @@ AM_CFLAGS = @CWARNFLAGS@ @XORG_CFLAGS@ @DRM_CFLAGS@ @DRI_CFLAGS@ \ intel_drv_la_LTLIBRARIES = intel_drv.la intel_drv_la_LDFLAGS = -module -avoid-version intel_drv_ladir = @moduledir@/drivers -intel_drv_la_LIBADD = -lm @DRM_LIBS@ -ldrm_intel ../uxa/libuxa.la +intel_drv_la_LIBADD = -lm @DRM_LIBS@ -ldrm_intel ../uxa/libuxa.la legacy/liblegacy.la intel_drv_la_LIBADD += @PCIACCESS_LIBS@ -INTEL_DRI_SRCS = \ - i810_dri.c \ - i810_dri.h \ - i830_dri.c \ - i810_hwmc.c \ - i830_dri.h - -INTEL_XVMC_SRCS = \ - i830_hwmc.h \ - i830_hwmc.c \ - i915_hwmc.h \ - i965_hwmc.h - +NULL:=# intel_drv_la_SOURCES = \ brw_defines.h \ brw_structs.h \ common.h \ i2c_vid.h \ - i810_accel.c \ - i810_common.h \ - i810_cursor.c \ - i810_dga.c \ - i810_driver.c \ - i810.h \ - i810_io.c \ - i810_memory.c \ - i810_reg.h \ - i810_ring.h \ - i810_video.c \ - i810_wmark.c \ + intel.h \ + intel_module.c \ + intel_driver.c \ + intel_batchbuffer.c \ + intel_batchbuffer.h \ + intel_memory.c \ + intel_shadow.c \ + intel_uxa.c \ + intel_video.c \ + intel_video.h \ i830_3d.c \ - i830_accel.c \ i830_bios.c \ i830_bios.h \ - i830_batchbuffer.c \ - i830_batchbuffer.h \ i830_common.h \ i830_crt.c \ i830_cursor.c \ i830_display.c \ i830_display.h \ i830_quirks.c \ - i830_driver.c \ i830_dvo.c \ i830.h \ i830_hdmi.c \ i830_i2c.c \ i830_io.c \ i830_lvds.c \ - i830_memory.c \ i830_modes.c \ - i830_video.c \ - i830_video.h \ + i830_render.c \ i830_reg.h \ i830_ring.h \ i830_sdvo.c \ @@ -98,27 +78,27 @@ intel_drv_la_SOURCES = \ i915_3d.c \ i915_3d.h \ i915_reg.h \ + i915_render.c \ i915_video.c \ + i965_reg.h \ + i965_3d.c \ i965_video.c \ - i830_uxa.c \ - i830_render.c \ - i915_render.c \ i965_render.c \ - drmmode_display.c - -EXTRA_DIST = \ - $(XMODE_SRCS) \ - $(INTEL_DRI_SRCS) \ - $(INTEL_XVMC_SRCS) + drmmode_display.c \ + $(NULL) if DRI intel_drv_la_SOURCES += \ - $(INTEL_DRI_SRCS) + intel_dri.c \ + $(NULL) intel_drv_la_LIBADD += \ - $(DRI_LIBS) + $(DRI_LIBS) \ + $(NULL) endif if XVMC intel_drv_la_SOURCES += \ - $(INTEL_XVMC_SRCS) + intel_hwmc.h \ + intel_hwmc.c \ + $(NULL) endif diff --git a/driver/xf86-video-intel/src/Makefile.in b/driver/xf86-video-intel/src/Makefile.in index 44ca1d3a0..f9e641aec 100644 --- a/driver/xf86-video-intel/src/Makefile.in +++ b/driver/xf86-video-intel/src/Makefile.in @@ -57,13 +57,17 @@ POST_UNINSTALL = : build_triplet = @build@ host_triplet = @host@ @DRI_TRUE@am__append_1 = \ -@DRI_TRUE@ $(INTEL_DRI_SRCS) +@DRI_TRUE@ intel_dri.c \ +@DRI_TRUE@ $(NULL) @DRI_TRUE@am__append_2 = \ -@DRI_TRUE@ $(DRI_LIBS) +@DRI_TRUE@ $(DRI_LIBS) \ +@DRI_TRUE@ $(NULL) @XVMC_TRUE@am__append_3 = \ -@XVMC_TRUE@ $(INTEL_XVMC_SRCS) +@XVMC_TRUE@ intel_hwmc.h \ +@XVMC_TRUE@ intel_hwmc.c \ +@XVMC_TRUE@ $(NULL) subdir = src DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in @@ -84,36 +88,34 @@ am__installdirs = "$(DESTDIR)$(intel_drv_ladir)" intel_drv_laLTLIBRARIES_INSTALL = $(INSTALL) LTLIBRARIES = $(intel_drv_la_LTLIBRARIES) am__DEPENDENCIES_1 = -@DRI_TRUE@am__DEPENDENCIES_2 = $(am__DEPENDENCIES_1) -intel_drv_la_DEPENDENCIES = ../uxa/libuxa.la $(am__DEPENDENCIES_2) +@DRI_TRUE@am__DEPENDENCIES_2 = $(am__DEPENDENCIES_1) \ +@DRI_TRUE@ $(am__DEPENDENCIES_1) +intel_drv_la_DEPENDENCIES = ../uxa/libuxa.la legacy/liblegacy.la \ + $(am__DEPENDENCIES_2) am__intel_drv_la_SOURCES_DIST = brw_defines.h brw_structs.h common.h \ - i2c_vid.h i810_accel.c i810_common.h i810_cursor.c i810_dga.c \ - i810_driver.c i810.h i810_io.c i810_memory.c i810_reg.h \ - i810_ring.h i810_video.c i810_wmark.c i830_3d.c i830_accel.c \ - i830_bios.c i830_bios.h i830_batchbuffer.c i830_batchbuffer.h \ - i830_common.h i830_crt.c i830_cursor.c i830_display.c \ - i830_display.h i830_quirks.c i830_driver.c i830_dvo.c i830.h \ - i830_hdmi.c i830_i2c.c i830_io.c i830_lvds.c i830_memory.c \ - i830_modes.c i830_video.c i830_video.h i830_reg.h i830_ring.h \ - i830_sdvo.c i830_sdvo.h i830_sdvo_regs.h i830_tv.c i915_3d.c \ - i915_3d.h i915_reg.h i915_video.c i965_video.c i830_uxa.c \ - i830_render.c i915_render.c i965_render.c drmmode_display.c \ - i810_dri.c i810_dri.h i830_dri.c i810_hwmc.c i830_dri.h \ - i830_hwmc.h i830_hwmc.c i915_hwmc.h i965_hwmc.h -am__objects_1 = i810_dri.lo i830_dri.lo i810_hwmc.lo -@DRI_TRUE@am__objects_2 = $(am__objects_1) -am__objects_3 = i830_hwmc.lo -@XVMC_TRUE@am__objects_4 = $(am__objects_3) -am_intel_drv_la_OBJECTS = i810_accel.lo i810_cursor.lo i810_dga.lo \ - i810_driver.lo i810_io.lo i810_memory.lo i810_video.lo \ - i810_wmark.lo i830_3d.lo i830_accel.lo i830_bios.lo \ - i830_batchbuffer.lo i830_crt.lo i830_cursor.lo i830_display.lo \ - i830_quirks.lo i830_driver.lo i830_dvo.lo i830_hdmi.lo \ - i830_i2c.lo i830_io.lo i830_lvds.lo i830_memory.lo \ - i830_modes.lo i830_video.lo i830_sdvo.lo i830_tv.lo i915_3d.lo \ - i915_video.lo i965_video.lo i830_uxa.lo i830_render.lo \ - i915_render.lo i965_render.lo drmmode_display.lo \ - $(am__objects_2) $(am__objects_4) + i2c_vid.h intel.h intel_module.c intel_driver.c \ + intel_batchbuffer.c intel_batchbuffer.h intel_memory.c \ + intel_uxa.c intel_video.c intel_video.h i830_3d.c i830_bios.c \ + i830_bios.h i830_common.h i830_crt.c i830_cursor.c \ + i830_display.c i830_display.h i830_quirks.c i830_dvo.c i830.h \ + i830_hdmi.c i830_i2c.c i830_io.c i830_lvds.c i830_modes.c \ + i830_render.c i830_reg.h i830_ring.h i830_sdvo.c i830_sdvo.h \ + i830_sdvo_regs.h i830_tv.c i915_3d.c i915_3d.h i915_reg.h \ + i915_render.c i915_video.c i965_reg.h i965_video.c \ + i965_render.c drmmode_display.c intel_dri.c intel_hwmc.h \ + intel_hwmc.c +am__objects_1 = +@DRI_TRUE@am__objects_2 = intel_dri.lo $(am__objects_1) +@XVMC_TRUE@am__objects_3 = intel_hwmc.lo $(am__objects_1) +am_intel_drv_la_OBJECTS = intel_module.lo intel_driver.lo \ + intel_batchbuffer.lo intel_memory.lo intel_uxa.lo \ + intel_video.lo i830_3d.lo i830_bios.lo i830_crt.lo \ + i830_cursor.lo i830_display.lo i830_quirks.lo i830_dvo.lo \ + i830_hdmi.lo i830_i2c.lo i830_io.lo i830_lvds.lo i830_modes.lo \ + i830_render.lo i830_sdvo.lo i830_tv.lo i915_3d.lo \ + i915_render.lo i915_video.lo i965_video.lo i965_render.lo \ + drmmode_display.lo $(am__objects_1) $(am__objects_2) \ + $(am__objects_3) intel_drv_la_OBJECTS = $(am_intel_drv_la_OBJECTS) DEFAULT_INCLUDES = -I. -I$(srcdir) -I$(top_builddir) depcomp = $(SHELL) $(top_srcdir)/depcomp @@ -152,10 +154,6 @@ AUTOCONF = @AUTOCONF@ AUTOHEADER = @AUTOHEADER@ AUTOMAKE = @AUTOMAKE@ AWK = @AWK@ -BUILD_LINUXDOC_FALSE = @BUILD_LINUXDOC_FALSE@ -BUILD_LINUXDOC_TRUE = @BUILD_LINUXDOC_TRUE@ -BUILD_PDFDOC_FALSE = @BUILD_PDFDOC_FALSE@ -BUILD_PDFDOC_TRUE = @BUILD_PDFDOC_TRUE@ CC = @CC@ CCDEPMODE = @CCDEPMODE@ CFLAGS = @CFLAGS@ @@ -195,8 +193,6 @@ GEN4ASM_LIBS = @GEN4ASM_LIBS@ GREP = @GREP@ HAVE_GEN4ASM_FALSE = @HAVE_GEN4ASM_FALSE@ HAVE_GEN4ASM_TRUE = @HAVE_GEN4ASM_TRUE@ -HAVE_XEXTPROTO_71_FALSE = @HAVE_XEXTPROTO_71_FALSE@ -HAVE_XEXTPROTO_71_TRUE = @HAVE_XEXTPROTO_71_TRUE@ INSTALL_CMD = @INSTALL_CMD@ INSTALL_DATA = @INSTALL_DATA@ INSTALL_PROGRAM = @INSTALL_PROGRAM@ @@ -210,17 +206,13 @@ LIBS = @LIBS@ LIBTOOL = @LIBTOOL@ LIB_MAN_DIR = @LIB_MAN_DIR@ LIB_MAN_SUFFIX = @LIB_MAN_SUFFIX@ -LINUXDOC = @LINUXDOC@ LN_S = @LN_S@ LTLIBOBJS = @LTLIBOBJS@ MAINT = @MAINT@ MAINTAINER_MODE_FALSE = @MAINTAINER_MODE_FALSE@ MAINTAINER_MODE_TRUE = @MAINTAINER_MODE_TRUE@ MAKEINFO = @MAKEINFO@ -MAKE_HTML = @MAKE_HTML@ -MAKE_PDF = @MAKE_PDF@ -MAKE_PS = @MAKE_PS@ -MAKE_TEXT = @MAKE_TEXT@ +MAN_SUBSTS = @MAN_SUBSTS@ MISC_MAN_DIR = @MISC_MAN_DIR@ MISC_MAN_SUFFIX = @MISC_MAN_SUFFIX@ NMEDIT = @NMEDIT@ @@ -235,19 +227,15 @@ PATH_SEPARATOR = @PATH_SEPARATOR@ PCIACCESS_CFLAGS = @PCIACCESS_CFLAGS@ PCIACCESS_LIBS = @PCIACCESS_LIBS@ PKG_CONFIG = @PKG_CONFIG@ -PS2PDF = @PS2PDF@ RANLIB = @RANLIB@ SED = @SED@ SET_MAKE = @SET_MAKE@ SHELL = @SHELL@ STRIP = @STRIP@ VERSION = @VERSION@ -VIDEO_DEBUG_FALSE = @VIDEO_DEBUG_FALSE@ -VIDEO_DEBUG_TRUE = @VIDEO_DEBUG_TRUE@ -XEXT_CFLAGS = @XEXT_CFLAGS@ -XEXT_LIBS = @XEXT_LIBS@ XORG_CFLAGS = @XORG_CFLAGS@ XORG_LIBS = @XORG_LIBS@ +XORG_MAN_PAGE = @XORG_MAN_PAGE@ XVMCLIB_CFLAGS = @XVMCLIB_CFLAGS@ XVMCLIB_LIBS = @XVMCLIB_LIBS@ XVMC_FALSE = @XVMC_FALSE@ @@ -300,7 +288,7 @@ sbindir = @sbindir@ sharedstatedir = @sharedstatedir@ sysconfdir = @sysconfdir@ target_alias = @target_alias@ -SUBDIRS = xvmc bios_reader ch7017 ch7xxx ivch sil164 tfp410 reg_dumper render_program +SUBDIRS = xvmc ch7017 ch7xxx ivch sil164 tfp410 render_program legacy # this is obnoxious: # -module lets us name the module exactly how we want @@ -314,38 +302,19 @@ intel_drv_la_LTLIBRARIES = intel_drv.la intel_drv_la_LDFLAGS = -module -avoid-version intel_drv_ladir = @moduledir@/drivers intel_drv_la_LIBADD = -lm @DRM_LIBS@ -ldrm_intel ../uxa/libuxa.la \ - @PCIACCESS_LIBS@ $(am__append_2) -INTEL_DRI_SRCS = \ - i810_dri.c \ - i810_dri.h \ - i830_dri.c \ - i810_hwmc.c \ - i830_dri.h - -INTEL_XVMC_SRCS = \ - i830_hwmc.h \ - i830_hwmc.c \ - i915_hwmc.h \ - i965_hwmc.h - + legacy/liblegacy.la @PCIACCESS_LIBS@ $(am__append_2) +NULL := # intel_drv_la_SOURCES = brw_defines.h brw_structs.h common.h i2c_vid.h \ - i810_accel.c i810_common.h i810_cursor.c i810_dga.c \ - i810_driver.c i810.h i810_io.c i810_memory.c i810_reg.h \ - i810_ring.h i810_video.c i810_wmark.c i830_3d.c i830_accel.c \ - i830_bios.c i830_bios.h i830_batchbuffer.c i830_batchbuffer.h \ - i830_common.h i830_crt.c i830_cursor.c i830_display.c \ - i830_display.h i830_quirks.c i830_driver.c i830_dvo.c i830.h \ - i830_hdmi.c i830_i2c.c i830_io.c i830_lvds.c i830_memory.c \ - i830_modes.c i830_video.c i830_video.h i830_reg.h i830_ring.h \ - i830_sdvo.c i830_sdvo.h i830_sdvo_regs.h i830_tv.c i915_3d.c \ - i915_3d.h i915_reg.h i915_video.c i965_video.c i830_uxa.c \ - i830_render.c i915_render.c i965_render.c drmmode_display.c \ - $(am__append_1) $(am__append_3) -EXTRA_DIST = \ - $(XMODE_SRCS) \ - $(INTEL_DRI_SRCS) \ - $(INTEL_XVMC_SRCS) - + intel.h intel_module.c intel_driver.c intel_batchbuffer.c \ + intel_batchbuffer.h intel_memory.c intel_uxa.c intel_video.c \ + intel_video.h i830_3d.c i830_bios.c i830_bios.h i830_common.h \ + i830_crt.c i830_cursor.c i830_display.c i830_display.h \ + i830_quirks.c i830_dvo.c i830.h i830_hdmi.c i830_i2c.c \ + i830_io.c i830_lvds.c i830_modes.c i830_render.c i830_reg.h \ + i830_ring.h i830_sdvo.c i830_sdvo.h i830_sdvo_regs.h i830_tv.c \ + i915_3d.c i915_3d.h i915_reg.h i915_render.c i915_video.c \ + i965_reg.h i965_video.c i965_render.c drmmode_display.c \ + $(NULL) $(am__append_1) $(am__append_3) all: all-recursive .SUFFIXES: @@ -416,44 +385,34 @@ distclean-compile: -rm -f *.tab.c @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drmmode_display.Plo@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i810_accel.Plo@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i810_cursor.Plo@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i810_dga.Plo@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i810_dri.Plo@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i810_driver.Plo@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i810_hwmc.Plo@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i810_io.Plo@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i810_memory.Plo@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i810_video.Plo@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i810_wmark.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i830_3d.Plo@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i830_accel.Plo@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i830_batchbuffer.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i830_bios.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i830_crt.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i830_cursor.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i830_display.Plo@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i830_dri.Plo@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i830_driver.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i830_dvo.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i830_hdmi.Plo@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i830_hwmc.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i830_i2c.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i830_io.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i830_lvds.Plo@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i830_memory.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i830_modes.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i830_quirks.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i830_render.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i830_sdvo.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i830_tv.Plo@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i830_uxa.Plo@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i830_video.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i915_3d.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i915_render.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i915_video.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i965_render.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i965_video.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/intel_batchbuffer.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/intel_dri.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/intel_driver.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/intel_hwmc.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/intel_memory.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/intel_module.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/intel_uxa.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/intel_video.Plo@am__quote@ .c.o: @am__fastdepCC_TRUE@ if $(COMPILE) -MT $@ -MD -MP -MF "$(DEPDIR)/$*.Tpo" -c -o $@ $<; \ diff --git a/driver/xf86-video-intel/src/bios_reader/Makefile.in b/driver/xf86-video-intel/src/bios_reader/Makefile.in index 6206b47fc..2a5ca2857 100644 --- a/driver/xf86-video-intel/src/bios_reader/Makefile.in +++ b/driver/xf86-video-intel/src/bios_reader/Makefile.in @@ -90,10 +90,6 @@ AUTOCONF = @AUTOCONF@ AUTOHEADER = @AUTOHEADER@ AUTOMAKE = @AUTOMAKE@ AWK = @AWK@ -BUILD_LINUXDOC_FALSE = @BUILD_LINUXDOC_FALSE@ -BUILD_LINUXDOC_TRUE = @BUILD_LINUXDOC_TRUE@ -BUILD_PDFDOC_FALSE = @BUILD_PDFDOC_FALSE@ -BUILD_PDFDOC_TRUE = @BUILD_PDFDOC_TRUE@ CC = @CC@ CCDEPMODE = @CCDEPMODE@ CFLAGS = @CFLAGS@ @@ -133,8 +129,6 @@ GEN4ASM_LIBS = @GEN4ASM_LIBS@ GREP = @GREP@ HAVE_GEN4ASM_FALSE = @HAVE_GEN4ASM_FALSE@ HAVE_GEN4ASM_TRUE = @HAVE_GEN4ASM_TRUE@ -HAVE_XEXTPROTO_71_FALSE = @HAVE_XEXTPROTO_71_FALSE@ -HAVE_XEXTPROTO_71_TRUE = @HAVE_XEXTPROTO_71_TRUE@ INSTALL_CMD = @INSTALL_CMD@ INSTALL_DATA = @INSTALL_DATA@ INSTALL_PROGRAM = @INSTALL_PROGRAM@ @@ -148,17 +142,13 @@ LIBS = @LIBS@ LIBTOOL = @LIBTOOL@ LIB_MAN_DIR = @LIB_MAN_DIR@ LIB_MAN_SUFFIX = @LIB_MAN_SUFFIX@ -LINUXDOC = @LINUXDOC@ LN_S = @LN_S@ LTLIBOBJS = @LTLIBOBJS@ MAINT = @MAINT@ MAINTAINER_MODE_FALSE = @MAINTAINER_MODE_FALSE@ MAINTAINER_MODE_TRUE = @MAINTAINER_MODE_TRUE@ MAKEINFO = @MAKEINFO@ -MAKE_HTML = @MAKE_HTML@ -MAKE_PDF = @MAKE_PDF@ -MAKE_PS = @MAKE_PS@ -MAKE_TEXT = @MAKE_TEXT@ +MAN_SUBSTS = @MAN_SUBSTS@ MISC_MAN_DIR = @MISC_MAN_DIR@ MISC_MAN_SUFFIX = @MISC_MAN_SUFFIX@ NMEDIT = @NMEDIT@ @@ -173,19 +163,15 @@ PATH_SEPARATOR = @PATH_SEPARATOR@ PCIACCESS_CFLAGS = @PCIACCESS_CFLAGS@ PCIACCESS_LIBS = @PCIACCESS_LIBS@ PKG_CONFIG = @PKG_CONFIG@ -PS2PDF = @PS2PDF@ RANLIB = @RANLIB@ SED = @SED@ SET_MAKE = @SET_MAKE@ SHELL = @SHELL@ STRIP = @STRIP@ VERSION = @VERSION@ -VIDEO_DEBUG_FALSE = @VIDEO_DEBUG_FALSE@ -VIDEO_DEBUG_TRUE = @VIDEO_DEBUG_TRUE@ -XEXT_CFLAGS = @XEXT_CFLAGS@ -XEXT_LIBS = @XEXT_LIBS@ XORG_CFLAGS = @XORG_CFLAGS@ XORG_LIBS = @XORG_LIBS@ +XORG_MAN_PAGE = @XORG_MAN_PAGE@ XVMCLIB_CFLAGS = @XVMCLIB_CFLAGS@ XVMCLIB_LIBS = @XVMCLIB_LIBS@ XVMC_FALSE = @XVMC_FALSE@ diff --git a/driver/xf86-video-intel/src/brw_structs.h b/driver/xf86-video-intel/src/brw_structs.h index 1cee5bdf5..f4dc927db 100644 --- a/driver/xf86-video-intel/src/brw_structs.h +++ b/driver/xf86-video-intel/src/brw_structs.h @@ -861,6 +861,11 @@ struct brw_wm_unit_state } wm10; }; +struct brw_wm_unit_state_padded { + struct brw_wm_unit_state state; + char pad[64 - sizeof(struct brw_wm_unit_state)]; +}; + /* The hardware supports two different modes for border color. The * default (OpenGL) mode uses floating-point color channels, while the * legacy mode uses 4 bytes. @@ -1487,4 +1492,228 @@ struct brw_interface_descriptor { } desc3; }; +struct gen6_blend_state +{ + struct { + unsigned int dest_blend_factor:5; + unsigned int source_blend_factor:5; + unsigned int pad3:1; + unsigned int blend_func:3; + unsigned int pad2:1; + unsigned int ia_dest_blend_factor:5; + unsigned int ia_source_blend_factor:5; + unsigned int pad1:1; + unsigned int ia_blend_func:3; + unsigned int pad0:1; + unsigned int ia_blend_enable:1; + unsigned int blend_enable:1; + } blend0; + + struct { + unsigned int post_blend_clamp_enable:1; + unsigned int pre_blend_clamp_enable:1; + unsigned int clamp_range:2; + unsigned int pad0:4; + unsigned int x_dither_offset:2; + unsigned int y_dither_offset:2; + unsigned int dither_enable:1; + unsigned int alpha_test_func:3; + unsigned int alpha_test_enable:1; + unsigned int pad1:1; + unsigned int logic_op_func:4; + unsigned int logic_op_enable:1; + unsigned int pad2:1; + unsigned int write_disable_b:1; + unsigned int write_disable_g:1; + unsigned int write_disable_r:1; + unsigned int write_disable_a:1; + unsigned int pad3:1; + unsigned int alpha_to_coverage_dither:1; + unsigned int alpha_to_one:1; + unsigned int alpha_to_coverage:1; + } blend1; +}; + +struct gen6_color_calc_state +{ + struct { + unsigned int alpha_test_format:1; + unsigned int pad0:14; + unsigned int round_disable:1; + unsigned int bf_stencil_ref:8; + unsigned int stencil_ref:8; + } cc0; + + union { + float alpha_ref_f; + struct { + unsigned int ui:8; + unsigned int pad0:24; + } alpha_ref_fi; + } cc1; + + float constant_r; + float constant_g; + float constant_b; + float constant_a; +}; + +struct gen6_depth_stencil_state +{ + struct { + unsigned int pad0:3; + unsigned int bf_stencil_pass_depth_pass_op:3; + unsigned int bf_stencil_pass_depth_fail_op:3; + unsigned int bf_stencil_fail_op:3; + unsigned int bf_stencil_func:3; + unsigned int bf_stencil_enable:1; + unsigned int pad1:2; + unsigned int stencil_write_enable:1; + unsigned int stencil_pass_depth_pass_op:3; + unsigned int stencil_pass_depth_fail_op:3; + unsigned int stencil_fail_op:3; + unsigned int stencil_func:3; + unsigned int stencil_enable:1; + } ds0; + + struct { + unsigned int bf_stencil_write_mask:8; + unsigned int bf_stencil_test_mask:8; + unsigned int stencil_write_mask:8; + unsigned int stencil_test_mask:8; + } ds1; + + struct { + unsigned int pad0:26; + unsigned int depth_write_enable:1; + unsigned int depth_test_func:3; + unsigned int pad1:1; + unsigned int depth_test_enable:1; + } ds2; +}; + +struct gen7_surface_state +{ + struct { + unsigned int cube_pos_z:1; + unsigned int cube_neg_z:1; + unsigned int cube_pos_y:1; + unsigned int cube_neg_y:1; + unsigned int cube_pos_x:1; + unsigned int cube_neg_x:1; + unsigned int pad2:2; + unsigned int render_cache_read_write:1; + unsigned int pad1:1; + unsigned int surface_array_spacing:1; + unsigned int vert_line_stride_ofs:1; + unsigned int vert_line_stride:1; + unsigned int tile_walk:1; + unsigned int tiled_surface:1; + unsigned int horizontal_alignment:1; + unsigned int vertical_alignment:2; + unsigned int surface_format:9; /**< BRW_SURFACEFORMAT_x */ + unsigned int pad0:1; + unsigned int is_array:1; + unsigned int surface_type:3; /**< BRW_SURFACE_1D/2D/3D/CUBE */ + } ss0; + + struct { + unsigned int base_addr; + } ss1; + + struct { + unsigned int width:14; + unsigned int pad1:2; + unsigned int height:14; + unsigned int pad0:2; + } ss2; + + struct { + unsigned int pitch:18; + unsigned int pad:3; + unsigned int depth:11; + } ss3; + + struct { + unsigned int multisample_position_palette_index:3; + unsigned int num_multisamples:3; + unsigned int multisampled_surface_storage_format:1; + unsigned int render_target_view_extent:11; + unsigned int min_array_elt:11; + unsigned int rotation:2; + unsigned int pad0:1; + } ss4; + + struct { + unsigned int mip_count:4; + unsigned int min_lod:4; + unsigned int pad1:12; + unsigned int y_offset:4; + unsigned int pad0:1; + unsigned int x_offset:7; + } ss5; + + struct { + unsigned int pad; /* Multisample Control Surface stuff */ + } ss6; + + struct { + unsigned int resource_min_lod:12; + unsigned int pad0:16; + unsigned int alpha_clear_color:1; + unsigned int blue_clear_color:1; + unsigned int green_clear_color:1; + unsigned int red_clear_color:1; + } ss7; +}; + +struct gen7_sampler_state +{ + struct + { + unsigned int aniso_algorithm:1; + unsigned int lod_bias:13; + unsigned int min_filter:3; + unsigned int mag_filter:3; + unsigned int mip_filter:2; + unsigned int base_level:5; + unsigned int pad1:1; + unsigned int lod_preclamp:1; + unsigned int default_color_mode:1; + unsigned int pad0:1; + unsigned int disable:1; + } ss0; + + struct + { + unsigned int cube_control_mode:1; + unsigned int shadow_function:3; + unsigned int pad:4; + unsigned int max_lod:12; + unsigned int min_lod:12; + } ss1; + + struct + { + unsigned int pad:5; + unsigned int default_color_pointer:27; + } ss2; + + struct + { + unsigned int r_wrap_mode:3; + unsigned int t_wrap_mode:3; + unsigned int s_wrap_mode:3; + unsigned int pad:1; + unsigned int non_normalized_coord:1; + unsigned int trilinear_quality:2; + unsigned int address_round:6; + unsigned int max_aniso:3; + unsigned int chroma_key_mode:1; + unsigned int chroma_key_index:2; + unsigned int chroma_key_enable:1; + unsigned int pad0:6; + } ss3; +}; + #endif diff --git a/driver/xf86-video-intel/src/ch7017/Makefile.in b/driver/xf86-video-intel/src/ch7017/Makefile.in index 875871386..5933240b2 100644 --- a/driver/xf86-video-intel/src/ch7017/Makefile.in +++ b/driver/xf86-video-intel/src/ch7017/Makefile.in @@ -87,10 +87,6 @@ AUTOCONF = @AUTOCONF@ AUTOHEADER = @AUTOHEADER@ AUTOMAKE = @AUTOMAKE@ AWK = @AWK@ -BUILD_LINUXDOC_FALSE = @BUILD_LINUXDOC_FALSE@ -BUILD_LINUXDOC_TRUE = @BUILD_LINUXDOC_TRUE@ -BUILD_PDFDOC_FALSE = @BUILD_PDFDOC_FALSE@ -BUILD_PDFDOC_TRUE = @BUILD_PDFDOC_TRUE@ CC = @CC@ CCDEPMODE = @CCDEPMODE@ CFLAGS = @CFLAGS@ @@ -130,8 +126,6 @@ GEN4ASM_LIBS = @GEN4ASM_LIBS@ GREP = @GREP@ HAVE_GEN4ASM_FALSE = @HAVE_GEN4ASM_FALSE@ HAVE_GEN4ASM_TRUE = @HAVE_GEN4ASM_TRUE@ -HAVE_XEXTPROTO_71_FALSE = @HAVE_XEXTPROTO_71_FALSE@ -HAVE_XEXTPROTO_71_TRUE = @HAVE_XEXTPROTO_71_TRUE@ INSTALL_CMD = @INSTALL_CMD@ INSTALL_DATA = @INSTALL_DATA@ INSTALL_PROGRAM = @INSTALL_PROGRAM@ @@ -145,17 +139,13 @@ LIBS = @LIBS@ LIBTOOL = @LIBTOOL@ LIB_MAN_DIR = @LIB_MAN_DIR@ LIB_MAN_SUFFIX = @LIB_MAN_SUFFIX@ -LINUXDOC = @LINUXDOC@ LN_S = @LN_S@ LTLIBOBJS = @LTLIBOBJS@ MAINT = @MAINT@ MAINTAINER_MODE_FALSE = @MAINTAINER_MODE_FALSE@ MAINTAINER_MODE_TRUE = @MAINTAINER_MODE_TRUE@ MAKEINFO = @MAKEINFO@ -MAKE_HTML = @MAKE_HTML@ -MAKE_PDF = @MAKE_PDF@ -MAKE_PS = @MAKE_PS@ -MAKE_TEXT = @MAKE_TEXT@ +MAN_SUBSTS = @MAN_SUBSTS@ MISC_MAN_DIR = @MISC_MAN_DIR@ MISC_MAN_SUFFIX = @MISC_MAN_SUFFIX@ NMEDIT = @NMEDIT@ @@ -170,19 +160,15 @@ PATH_SEPARATOR = @PATH_SEPARATOR@ PCIACCESS_CFLAGS = @PCIACCESS_CFLAGS@ PCIACCESS_LIBS = @PCIACCESS_LIBS@ PKG_CONFIG = @PKG_CONFIG@ -PS2PDF = @PS2PDF@ RANLIB = @RANLIB@ SED = @SED@ SET_MAKE = @SET_MAKE@ SHELL = @SHELL@ STRIP = @STRIP@ VERSION = @VERSION@ -VIDEO_DEBUG_FALSE = @VIDEO_DEBUG_FALSE@ -VIDEO_DEBUG_TRUE = @VIDEO_DEBUG_TRUE@ -XEXT_CFLAGS = @XEXT_CFLAGS@ -XEXT_LIBS = @XEXT_LIBS@ XORG_CFLAGS = @XORG_CFLAGS@ XORG_LIBS = @XORG_LIBS@ +XORG_MAN_PAGE = @XORG_MAN_PAGE@ XVMCLIB_CFLAGS = @XVMCLIB_CFLAGS@ XVMCLIB_LIBS = @XVMCLIB_LIBS@ XVMC_FALSE = @XVMC_FALSE@ diff --git a/driver/xf86-video-intel/src/ch7xxx/Makefile.in b/driver/xf86-video-intel/src/ch7xxx/Makefile.in index 2e98ecbd7..404e2715d 100644 --- a/driver/xf86-video-intel/src/ch7xxx/Makefile.in +++ b/driver/xf86-video-intel/src/ch7xxx/Makefile.in @@ -87,10 +87,6 @@ AUTOCONF = @AUTOCONF@ AUTOHEADER = @AUTOHEADER@ AUTOMAKE = @AUTOMAKE@ AWK = @AWK@ -BUILD_LINUXDOC_FALSE = @BUILD_LINUXDOC_FALSE@ -BUILD_LINUXDOC_TRUE = @BUILD_LINUXDOC_TRUE@ -BUILD_PDFDOC_FALSE = @BUILD_PDFDOC_FALSE@ -BUILD_PDFDOC_TRUE = @BUILD_PDFDOC_TRUE@ CC = @CC@ CCDEPMODE = @CCDEPMODE@ CFLAGS = @CFLAGS@ @@ -130,8 +126,6 @@ GEN4ASM_LIBS = @GEN4ASM_LIBS@ GREP = @GREP@ HAVE_GEN4ASM_FALSE = @HAVE_GEN4ASM_FALSE@ HAVE_GEN4ASM_TRUE = @HAVE_GEN4ASM_TRUE@ -HAVE_XEXTPROTO_71_FALSE = @HAVE_XEXTPROTO_71_FALSE@ -HAVE_XEXTPROTO_71_TRUE = @HAVE_XEXTPROTO_71_TRUE@ INSTALL_CMD = @INSTALL_CMD@ INSTALL_DATA = @INSTALL_DATA@ INSTALL_PROGRAM = @INSTALL_PROGRAM@ @@ -145,17 +139,13 @@ LIBS = @LIBS@ LIBTOOL = @LIBTOOL@ LIB_MAN_DIR = @LIB_MAN_DIR@ LIB_MAN_SUFFIX = @LIB_MAN_SUFFIX@ -LINUXDOC = @LINUXDOC@ LN_S = @LN_S@ LTLIBOBJS = @LTLIBOBJS@ MAINT = @MAINT@ MAINTAINER_MODE_FALSE = @MAINTAINER_MODE_FALSE@ MAINTAINER_MODE_TRUE = @MAINTAINER_MODE_TRUE@ MAKEINFO = @MAKEINFO@ -MAKE_HTML = @MAKE_HTML@ -MAKE_PDF = @MAKE_PDF@ -MAKE_PS = @MAKE_PS@ -MAKE_TEXT = @MAKE_TEXT@ +MAN_SUBSTS = @MAN_SUBSTS@ MISC_MAN_DIR = @MISC_MAN_DIR@ MISC_MAN_SUFFIX = @MISC_MAN_SUFFIX@ NMEDIT = @NMEDIT@ @@ -170,19 +160,15 @@ PATH_SEPARATOR = @PATH_SEPARATOR@ PCIACCESS_CFLAGS = @PCIACCESS_CFLAGS@ PCIACCESS_LIBS = @PCIACCESS_LIBS@ PKG_CONFIG = @PKG_CONFIG@ -PS2PDF = @PS2PDF@ RANLIB = @RANLIB@ SED = @SED@ SET_MAKE = @SET_MAKE@ SHELL = @SHELL@ STRIP = @STRIP@ VERSION = @VERSION@ -VIDEO_DEBUG_FALSE = @VIDEO_DEBUG_FALSE@ -VIDEO_DEBUG_TRUE = @VIDEO_DEBUG_TRUE@ -XEXT_CFLAGS = @XEXT_CFLAGS@ -XEXT_LIBS = @XEXT_LIBS@ XORG_CFLAGS = @XORG_CFLAGS@ XORG_LIBS = @XORG_LIBS@ +XORG_MAN_PAGE = @XORG_MAN_PAGE@ XVMCLIB_CFLAGS = @XVMCLIB_CFLAGS@ XVMCLIB_LIBS = @XVMCLIB_LIBS@ XVMC_FALSE = @XVMC_FALSE@ diff --git a/driver/xf86-video-intel/src/common.h b/driver/xf86-video-intel/src/common.h index 6f35d56db..56c97b687 100644 --- a/driver/xf86-video-intel/src/common.h +++ b/driver/xf86-video-intel/src/common.h @@ -122,38 +122,16 @@ static inline void memcpy_volatile(volatile void *dst, const void *src, #define OUTREG8(addr, val) do { \ *(volatile uint8_t *)(RecPtr->MMIOBase + (addr)) = (val); \ - if (I810_DEBUG&DEBUG_VERBOSE_OUTREG) { \ - ErrorF("OUTREG8(0x%lx, 0x%lx) in %s\n", (unsigned long)(addr), \ - (unsigned long)(val), FUNCTION_NAME); \ - } \ } while (0) #define OUTREG16(addr, val) do { \ *(volatile uint16_t *)(RecPtr->MMIOBase + (addr)) = (val); \ - if (I810_DEBUG&DEBUG_VERBOSE_OUTREG) { \ - ErrorF("OUTREG16(0x%lx, 0x%lx) in %s\n", (unsigned long)(addr), \ - (unsigned long)(val), FUNCTION_NAME); \ - } \ } while (0) #define OUTREG(addr, val) do { \ *(volatile uint32_t *)(RecPtr->MMIOBase + (addr)) = (val); \ - if (I810_DEBUG&DEBUG_VERBOSE_OUTREG) { \ - ErrorF("OUTREG(0x%lx, 0x%lx) in %s\n", (unsigned long)(addr), \ - (unsigned long)(val), FUNCTION_NAME); \ - } \ } while (0) -/* To remove all debugging, make sure I810_DEBUG is defined as a - * preprocessor symbol, and equal to zero. - */ -#if 1 -#define I810_DEBUG 0 -#endif -#ifndef I810_DEBUG -#warning "Debugging enabled - expect reduced performance" -extern int I810_DEBUG; -#endif #define DEBUG_VERBOSE_ACCEL 0x1 #define DEBUG_VERBOSE_SYNC 0x2 @@ -171,222 +149,7 @@ extern int I810_DEBUG; */ #define I810_REG_SIZE 0x80000 -#ifndef PCI_CHIP_I810 -#define PCI_CHIP_I810 0x7121 -#define PCI_CHIP_I810_DC100 0x7123 -#define PCI_CHIP_I810_E 0x7125 -#define PCI_CHIP_I815 0x1132 -#define PCI_CHIP_I810_BRIDGE 0x7120 -#define PCI_CHIP_I810_DC100_BRIDGE 0x7122 -#define PCI_CHIP_I810_E_BRIDGE 0x7124 -#define PCI_CHIP_I815_BRIDGE 0x1130 -#endif - -#ifndef PCI_CHIP_I830_M -#define PCI_CHIP_I830_M 0x3577 -#define PCI_CHIP_I830_M_BRIDGE 0x3575 -#endif - -#ifndef PCI_CHIP_845_G -#define PCI_CHIP_845_G 0x2562 -#define PCI_CHIP_845_G_BRIDGE 0x2560 -#endif - -#ifndef PCI_CHIP_I855_GM -#define PCI_CHIP_I855_GM 0x3582 -#define PCI_CHIP_I855_GM_BRIDGE 0x3580 -#endif - -#ifndef PCI_CHIP_I865_G -#define PCI_CHIP_I865_G 0x2572 -#define PCI_CHIP_I865_G_BRIDGE 0x2570 -#endif - -#ifndef PCI_CHIP_I915_G -#define PCI_CHIP_I915_G 0x2582 -#define PCI_CHIP_I915_G_BRIDGE 0x2580 -#endif - -#ifndef PCI_CHIP_I915_GM -#define PCI_CHIP_I915_GM 0x2592 -#define PCI_CHIP_I915_GM_BRIDGE 0x2590 -#endif - -#ifndef PCI_CHIP_E7221_G -#define PCI_CHIP_E7221_G 0x258A -/* Same as I915_G_BRIDGE */ -#define PCI_CHIP_E7221_G_BRIDGE 0x2580 -#endif - -#ifndef PCI_CHIP_I945_G -#define PCI_CHIP_I945_G 0x2772 -#define PCI_CHIP_I945_G_BRIDGE 0x2770 -#endif - -#ifndef PCI_CHIP_I945_GM -#define PCI_CHIP_I945_GM 0x27A2 -#define PCI_CHIP_I945_GM_BRIDGE 0x27A0 -#endif - -#ifndef PCI_CHIP_I945_GME -#define PCI_CHIP_I945_GME 0x27AE -#define PCI_CHIP_I945_GME_BRIDGE 0x27AC -#endif - -#ifndef PCI_CHIP_IGD_GM -#define PCI_CHIP_IGD_GM 0xA011 -#define PCI_CHIP_IGD_GM_BRIDGE 0xA010 -#define PCI_CHIP_IGD_G 0xA001 -#define PCI_CHIP_IGD_G_BRIDGE 0xA000 -#endif - -#ifndef PCI_CHIP_G35_G -#define PCI_CHIP_G35_G 0x2982 -#define PCI_CHIP_G35_G_BRIDGE 0x2980 -#endif - -#ifndef PCI_CHIP_I965_Q -#define PCI_CHIP_I965_Q 0x2992 -#define PCI_CHIP_I965_Q_BRIDGE 0x2990 -#endif - -#ifndef PCI_CHIP_I965_G -#define PCI_CHIP_I965_G 0x29A2 -#define PCI_CHIP_I965_G_BRIDGE 0x29A0 -#endif - -#ifndef PCI_CHIP_I946_GZ -#define PCI_CHIP_I946_GZ 0x2972 -#define PCI_CHIP_I946_GZ_BRIDGE 0x2970 -#endif - -#ifndef PCI_CHIP_I965_GM -#define PCI_CHIP_I965_GM 0x2A02 -#define PCI_CHIP_I965_GM_BRIDGE 0x2A00 -#endif - -#ifndef PCI_CHIP_I965_GME -#define PCI_CHIP_I965_GME 0x2A12 -#define PCI_CHIP_I965_GME_BRIDGE 0x2A10 -#endif - -#ifndef PCI_CHIP_G33_G -#define PCI_CHIP_G33_G 0x29C2 -#define PCI_CHIP_G33_G_BRIDGE 0x29C0 -#endif - -#ifndef PCI_CHIP_Q35_G -#define PCI_CHIP_Q35_G 0x29B2 -#define PCI_CHIP_Q35_G_BRIDGE 0x29B0 -#endif - -#ifndef PCI_CHIP_Q33_G -#define PCI_CHIP_Q33_G 0x29D2 -#define PCI_CHIP_Q33_G_BRIDGE 0x29D0 -#endif - -#ifndef PCI_CHIP_GM45_GM -#define PCI_CHIP_GM45_GM 0x2A42 -#define PCI_CHIP_GM45_BRIDGE 0x2A40 -#endif - -#ifndef PCI_CHIP_IGD_E_G -#define PCI_CHIP_IGD_E_G 0x2E02 -#define PCI_CHIP_IGD_E_G_BRIDGE 0x2E00 -#endif - -#ifndef PCI_CHIP_G45_G -#define PCI_CHIP_G45_G 0x2E22 -#define PCI_CHIP_G45_G_BRIDGE 0x2E20 -#endif - -#ifndef PCI_CHIP_Q45_G -#define PCI_CHIP_Q45_G 0x2E12 -#define PCI_CHIP_Q45_G_BRIDGE 0x2E10 -#endif - -#ifndef PCI_CHIP_G41_G -#define PCI_CHIP_G41_G 0x2E32 -#define PCI_CHIP_G41_G_BRIDGE 0x2E30 -#endif - -#ifndef PCI_CHIP_B43_G -#define PCI_CHIP_B43_G 0x2E42 -#define PCI_CHIP_B43_G_BRIDGE 0x2E40 -#endif - -#ifndef PCI_CHIP_IGDNG_D_G -#define PCI_CHIP_IGDNG_D_G 0x0042 -#define PCI_CHIP_IGDNG_D_G_BRIDGE 0x0040 -#endif - -#ifndef PCI_CHIP_IGDNG_M_G -#define PCI_CHIP_IGDNG_M_G 0x0046 -#define PCI_CHIP_IGDNG_M_G_BRIDGE 0x0044 -#endif - -#define I810_MEMBASE(p,n) (p)->regions[(n)].base_addr -#define VENDOR_ID(p) (p)->vendor_id -#define DEVICE_ID(p) (p)->device_id -#define SUBVENDOR_ID(p) (p)->subvendor_id -#define SUBSYS_ID(p) (p)->subdevice_id -#define CHIP_REVISION(p) (p)->revision - -#define IS_I810(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I810 || \ - DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I810_DC100 || \ - DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I810_E) -#define IS_I815(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I815) -#define IS_I830(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I830_M) -#define IS_845G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_845_G) -#define IS_I85X(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I855_GM) -#define IS_I852(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I855_GM && (pI810->variant == I852_GM || pI810->variant == I852_GME)) -#define IS_I855(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I855_GM && (pI810->variant == I855_GM || pI810->variant == I855_GME)) -#define IS_I865G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I865_G) - -#define IS_I915G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I915_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_E7221_G) -#define IS_I915GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I915_GM) -#define IS_I945G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_G) -#define IS_I945GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GME) -#define IS_IGDGM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_GM) -#define IS_IGDG(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_G) -#define IS_IGD(pI810) (IS_IGDG(pI810) || IS_IGDGM(pI810)) -#define IS_GM45(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_GM45_GM) -#define IS_G4X(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_E_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G45_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q45_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G41_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_B43_G || IS_GM45(pI810)) -#define IS_I965GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME) -#define IS_965_Q(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q) -#define IS_IGDNG_D(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGDNG_D_G) -#define IS_IGDNG_M(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGDNG_M_G) -#define IS_IGDNG(pI810) (IS_IGDNG_D(pI810) || IS_IGDNG_M(pI810)) -#define IS_I965G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G35_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I946_GZ || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME || IS_G4X(pI810) || IS_IGDNG(pI810)) -#define IS_G33CLASS(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G33_G ||\ - DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q35_G ||\ - DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q33_G || \ - IS_IGD(pI810)) -#define IS_I9XX(pI810) (IS_I915G(pI810) || IS_I915GM(pI810) || IS_I945G(pI810) || IS_I945GM(pI810) || IS_I965G(pI810) || IS_G33CLASS(pI810)) -#define IS_I915(pI810) (IS_I915G(pI810) || IS_I915GM(pI810) || IS_I945G(pI810) || IS_I945GM(pI810) || IS_G33CLASS(pI810)) - -#define IS_MOBILE(pI810) (IS_I830(pI810) || IS_I85X(pI810) || IS_I915GM(pI810) || IS_I945GM(pI810) || IS_I965GM(pI810) || IS_GM45(pI810) || IS_IGD(pI810) || IS_IGDNG_M(pI810)) -/* mark chipsets for using gfx VM offset for overlay */ -#define OVERLAY_NOPHYSICAL(pI810) (IS_G33CLASS(pI810) || IS_I965G(pI810)) -/* mark chipsets without overlay hw */ -#define OVERLAY_NOEXIST(pI810) (IS_G4X(pI810) || IS_IGDNG(pI810)) -/* chipsets require graphics mem for hardware status page */ -#define HWS_NEED_GFX(pI810) (!pI810->use_drm_mode && \ - (IS_G33CLASS(pI810) ||\ - IS_G4X(pI810) || IS_IGDNG(pI810))) -/* chipsets require status page in non stolen memory */ -#define HWS_NEED_NONSTOLEN(pI810) (IS_G4X(pI810) || IS_IGDNG(pI810)) -#define SUPPORTS_INTEGRATED_HDMI(pI810) (IS_G4X(pI810) || IS_IGDNG(pI810)) -/* dsparb controlled by hw only */ -#define DSPARB_HWCONTROL(pI810) (IS_G4X(pI810) || IS_IGDNG(pI810)) -/* supports Y tiled surfaces (pre-965 Mesa isn't ready yet) */ -#define SUPPORTS_YTILING(pI810) (IS_I965G(intel)) - #define GTT_PAGE_SIZE KB(4) -#define ROUND_TO(x, y) (((x) + (y) - 1) / (y) * (y)) -#define ROUND_DOWN_TO(x, y) ((x) / (y) * (y)) -#define ROUND_TO_PAGE(x) ROUND_TO((x), GTT_PAGE_SIZE) -#define ROUND_TO_MB(x) ROUND_TO((x), MB(1)) #define PRIMARY_RINGBUFFER_SIZE KB(128) #define MIN_SCRATCH_BUFFER_SIZE KB(16) #define MAX_SCRATCH_BUFFER_SIZE KB(64) @@ -410,9 +173,10 @@ intel_host_bridge (void); * Compare to CREATE_PIXMAP_USAGE_* in the server. */ enum { - INTEL_CREATE_PIXMAP_TILING_X = 0x10000000, - INTEL_CREATE_PIXMAP_TILING_Y, - INTEL_CREATE_PIXMAP_TILING_NONE, + INTEL_CREATE_PIXMAP_TILING_X = 0x10000000, + INTEL_CREATE_PIXMAP_TILING_Y = 0x20000000, + INTEL_CREATE_PIXMAP_TILING_NONE = 0x40000000, + INTEL_CREATE_PIXMAP_DRI2 = 0x80000000, }; #endif /* _INTEL_COMMON_H_ */ diff --git a/driver/xf86-video-intel/src/drmmode_display.c b/driver/xf86-video-intel/src/drmmode_display.c index de40fe9b5..bfe961df4 100644 --- a/driver/xf86-video-intel/src/drmmode_display.c +++ b/driver/xf86-video-intel/src/drmmode_display.c @@ -37,7 +37,7 @@ #include "xorgVersion.h" -#include "i830.h" +#include "intel.h" #include "intel_bufmgr.h" #include "xf86drmMode.h" #include "X11/Xatom.h" @@ -54,6 +54,7 @@ typedef struct { drmModeCrtcPtr mode_crtc; dri_bo *cursor; dri_bo *rotate_bo; + uint32_t rotate_pitch; uint32_t rotate_fb_id; } drmmode_crtc_private_rec, *drmmode_crtc_private_ptr; @@ -318,7 +319,7 @@ drmmode_set_mode_major(xf86CrtcPtr crtc, DisplayModePtr mode, ret = drmModeAddFB(drmmode->fd, scrn->virtualX, scrn->virtualY, scrn->depth, scrn->bitsPerPixel, - pitch, intel->front_buffer->bo->handle, + pitch, intel->front_buffer->handle, &drmmode->fb_id); if (ret < 0) { ErrorF("failed to add fb\n"); @@ -395,7 +396,7 @@ drmmode_set_mode_major(xf86CrtcPtr crtc, DisplayModePtr mode, drmmode_output_dpms(output, DPMSModeOn); } - i830_set_gem_max_sizes(scrn); + intel_set_gem_max_sizes(scrn); if (scrn->pScreen) xf86_reload_cursors(scrn->pScreen); @@ -464,18 +465,17 @@ static void * drmmode_crtc_shadow_allocate(xf86CrtcPtr crtc, int width, int height) { ScrnInfoPtr scrn = crtc->scrn; - intel_screen_private *intel = intel_get_screen_private(scrn); drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; drmmode_ptr drmmode = drmmode_crtc->drmmode; - int size, ret; unsigned long rotate_pitch; + uint32_t tiling; + int ret; - width = i830_pad_drawable_width(width); - rotate_pitch = width * drmmode->cpp; - size = rotate_pitch * height; - - drmmode_crtc->rotate_bo = - drm_intel_bo_alloc(intel->bufmgr, "rotate", size, 4096); + drmmode_crtc->rotate_bo = intel_allocate_framebuffer(scrn, + width, height, + drmmode->cpp, + &rotate_pitch, + &tiling); if (!drmmode_crtc->rotate_bo) { xf86DrvMsg(crtc->scrn->scrnIndex, X_ERROR, @@ -483,8 +483,6 @@ drmmode_crtc_shadow_allocate(xf86CrtcPtr crtc, int width, int height) return NULL; } - drm_intel_bo_disable_reuse(drmmode_crtc->rotate_bo); - ret = drmModeAddFB(drmmode->fd, width, height, crtc->scrn->depth, crtc->scrn->bitsPerPixel, rotate_pitch, drmmode_crtc->rotate_bo->handle, @@ -495,6 +493,7 @@ drmmode_crtc_shadow_allocate(xf86CrtcPtr crtc, int width, int height) return NULL; } + drmmode_crtc->rotate_pitch = rotate_pitch; return drmmode_crtc->rotate_bo; } @@ -502,9 +501,8 @@ static PixmapPtr drmmode_crtc_shadow_create(xf86CrtcPtr crtc, void *data, int width, int height) { ScrnInfoPtr scrn = crtc->scrn; + intel_screen_private *intel = intel_get_screen_private(scrn); drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; - drmmode_ptr drmmode = drmmode_crtc->drmmode; - unsigned long rotate_pitch; PixmapPtr rotate_pixmap; if (!data) { @@ -515,13 +513,17 @@ drmmode_crtc_shadow_create(xf86CrtcPtr crtc, void *data, int width, int height) return NULL; } } + if (drmmode_crtc->rotate_bo == NULL) { + xf86DrvMsg(scrn->scrnIndex, X_ERROR, + "Couldn't allocate shadow pixmap for rotated CRTC\n"); + return NULL; + } - rotate_pitch = i830_pad_drawable_width(width) * drmmode->cpp; rotate_pixmap = GetScratchPixmapHeader(scrn->pScreen, width, height, scrn->depth, scrn->bitsPerPixel, - rotate_pitch, + drmmode_crtc->rotate_pitch, NULL); if (rotate_pixmap == NULL) { @@ -530,8 +532,9 @@ drmmode_crtc_shadow_create(xf86CrtcPtr crtc, void *data, int width, int height) return NULL; } - if (drmmode_crtc->rotate_bo) - i830_set_pixmap_bo(rotate_pixmap, drmmode_crtc->rotate_bo); + intel_set_pixmap_bo(rotate_pixmap, drmmode_crtc->rotate_bo); + + intel->shadow_present = TRUE; return rotate_pixmap; } @@ -539,11 +542,13 @@ drmmode_crtc_shadow_create(xf86CrtcPtr crtc, void *data, int width, int height) static void drmmode_crtc_shadow_destroy(xf86CrtcPtr crtc, PixmapPtr rotate_pixmap, void *data) { + ScrnInfoPtr scrn = crtc->scrn; + intel_screen_private *intel = intel_get_screen_private(scrn); drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; drmmode_ptr drmmode = drmmode_crtc->drmmode; if (rotate_pixmap) { - i830_set_pixmap_bo(rotate_pixmap, NULL); + intel_set_pixmap_bo(rotate_pixmap, NULL); FreeScratchPixmapHeader(rotate_pixmap); } @@ -556,6 +561,8 @@ drmmode_crtc_shadow_destroy(xf86CrtcPtr crtc, PixmapPtr rotate_pixmap, void *dat dri_bo_unreference(drmmode_crtc->rotate_bo); drmmode_crtc->rotate_bo = NULL; } + + intel->shadow_present = intel->use_shadow; } static void @@ -1308,46 +1315,42 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int height) drmmode_crtc = xf86_config->crtc[0]->driver_private; drmmode_ptr drmmode = drmmode_crtc->drmmode; intel_screen_private *intel = intel_get_screen_private(scrn); - i830_memory *old_front = NULL; - Bool tiled, ret; - ScreenPtr screen = screenInfo.screens[scrn->scrnIndex]; + drm_intel_bo *old_front = NULL; + Bool ret; uint32_t old_fb_id; - int i, w, pitch, old_width, old_height, old_pitch; + int i, old_width, old_height, old_pitch; + unsigned long pitch; + uint32_t tiling; if (scrn->virtualX == width && scrn->virtualY == height) return TRUE; - w = i830_pad_drawable_width(width); - i830_tiled_width(intel, &w, intel->cpp); - pitch = w * intel->cpp; - xf86DrvMsg(scrn->scrnIndex, X_INFO, - "Allocate new frame buffer %dx%d stride %d\n", - width, height, pitch); - old_width = scrn->virtualX; old_height = scrn->virtualY; old_pitch = scrn->displayWidth; old_fb_id = drmmode->fb_id; old_front = intel->front_buffer; - scrn->virtualX = width; - scrn->virtualY = height; - scrn->displayWidth = w; - intel->front_buffer = i830_allocate_framebuffer(scrn); + intel->front_buffer = intel_allocate_framebuffer(scrn, + width, height, + intel->cpp, + &pitch, + &tiling); if (!intel->front_buffer) goto fail; ret = drmModeAddFB(drmmode->fd, width, height, scrn->depth, scrn->bitsPerPixel, pitch, - intel->front_buffer->bo->handle, + intel->front_buffer->handle, &drmmode->fb_id); if (ret) goto fail; - i830_set_pixmap_bo(screen->GetScreenPixmap(screen), intel->front_buffer->bo); + intel->front_pitch = pitch; + intel->front_tiling = tiling; - screen->ModifyPixmapHeader(screen->GetScreenPixmap(screen), - width, height, -1, -1, pitch, NULL); + scrn->virtualX = width; + scrn->virtualY = height; for (i = 0; i < xf86_config->num_crtc; i++) { xf86CrtcPtr crtc = xf86_config->crtc[i]; @@ -1359,16 +1362,18 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int height) crtc->rotation, crtc->x, crtc->y); } + intel_uxa_create_screen_resources(scrn->pScreen); + if (old_fb_id) drmModeRmFB(drmmode->fd, old_fb_id); if (old_front) - i830_free_memory(scrn, old_front); + drm_intel_bo_unreference(old_front); return TRUE; fail: if (intel->front_buffer) - i830_free_memory(scrn, intel->front_buffer); + drm_intel_bo_unreference(intel->front_buffer); intel->front_buffer = old_front; scrn->virtualX = old_width; scrn->virtualY = old_height; diff --git a/driver/xf86-video-intel/src/i830_3d.c b/driver/xf86-video-intel/src/i830_3d.c index a92da055d..10432011d 100644 --- a/driver/xf86-video-intel/src/i830_3d.c +++ b/driver/xf86-video-intel/src/i830_3d.c @@ -30,7 +30,7 @@ #endif #include "xf86.h" -#include "i830.h" +#include "intel.h" #include "i830_reg.h" diff --git a/driver/xf86-video-intel/src/i830_accel.c b/driver/xf86-video-intel/src/i830_accel.c deleted file mode 100644 index df4f58db9..000000000 --- a/driver/xf86-video-intel/src/i830_accel.c +++ /dev/null @@ -1,125 +0,0 @@ -/************************************************************************** - -Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas. -All Rights Reserved. - -Permission is hereby granted, free of charge, to any person obtaining a -copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sub license, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial portions -of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS -OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. -IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR -ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE -SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/* - * Authors: - * Keith Whitwell <keith@tungstengraphics.com> - * - */ - -/* - * XXX So far, for GXxor this is about 40% of the speed of SW, but CPU - * utilisation falls from 95% to < 5%. - */ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include "xf86.h" -#include "i830.h" -#include "i810_reg.h" -#include "i830_ring.h" -#include "i915_drm.h" - -unsigned long intel_get_pixmap_pitch(PixmapPtr pixmap) -{ - return (unsigned long)pixmap->devKind; -} - -void i830_debug_flush(ScrnInfoPtr scrn) -{ - intel_screen_private *intel = intel_get_screen_private(scrn); - - if (intel->debug_flush & DEBUG_FLUSH_CACHES) - intel_batch_emit_flush(scrn); - - if (intel->debug_flush & DEBUG_FLUSH_BATCHES) - intel_batch_submit(scrn, FALSE); -} - -/* The following function sets up the supported acceleration. Call it - * from the FbInit() function in the SVGA driver, or before ScreenInit - * in a monolithic server. - */ -Bool I830AccelInit(ScreenPtr screen) -{ - ScrnInfoPtr scrn = xf86Screens[screen->myNum]; - intel_screen_private *intel = intel_get_screen_private(scrn); - - /* Limits are described in the BLT engine chapter under Graphics Data Size - * Limitations, and the descriptions of SURFACE_STATE, 3DSTATE_BUFFER_INFO, - * 3DSTATE_DRAWING_RECTANGLE, 3DSTATE_MAP_INFO, and 3DSTATE_MAP_INFO. - * - * i845 through i965 limits 2D rendering to 65536 lines and pitch of 32768. - * - * i965 limits 3D surface to (2*element size)-aligned offset if un-tiled. - * i965 limits 3D surface to 4kB-aligned offset if tiled. - * i965 limits 3D surfaces to w,h of ?,8192. - * i965 limits 3D surface to pitch of 1B - 128kB. - * i965 limits 3D surface pitch alignment to 1 or 2 times the element size. - * i965 limits 3D surface pitch alignment to 512B if tiled. - * i965 limits 3D destination drawing rect to w,h of 8192,8192. - * - * i915 limits 3D textures to 4B-aligned offset if un-tiled. - * i915 limits 3D textures to ~4kB-aligned offset if tiled. - * i915 limits 3D textures to width,height of 2048,2048. - * i915 limits 3D textures to pitch of 16B - 8kB, in dwords. - * i915 limits 3D destination to ~4kB-aligned offset if tiled. - * i915 limits 3D destination to pitch of 16B - 8kB, in dwords, if un-tiled. - * i915 limits 3D destination to pitch 64B-aligned if used with depth. - * i915 limits 3D destination to pitch of 512B - 8kB, in tiles, if tiled. - * i915 limits 3D destination to POT aligned pitch if tiled. - * i915 limits 3D destination drawing rect to w,h of 2048,2048. - * - * i845 limits 3D textures to 4B-aligned offset if un-tiled. - * i845 limits 3D textures to ~4kB-aligned offset if tiled. - * i845 limits 3D textures to width,height of 2048,2048. - * i845 limits 3D textures to pitch of 4B - 8kB, in dwords. - * i845 limits 3D destination to 4B-aligned offset if un-tiled. - * i845 limits 3D destination to ~4kB-aligned offset if tiled. - * i845 limits 3D destination to pitch of 8B - 8kB, in dwords. - * i845 limits 3D destination drawing rect to w,h of 2048,2048. - * - * For the tiled issues, the only tiled buffer we draw to should be - * the front, which will have an appropriate pitch/offset already set up, - * so UXA doesn't need to worry. - */ - if (IS_I965G(intel)) { - intel->accel_pixmap_offset_alignment = 4 * 2; - intel->accel_pixmap_pitch_alignment = 64; - intel->accel_max_x = 8192; - intel->accel_max_y = 8192; - } else { - intel->accel_pixmap_offset_alignment = 4; - intel->accel_pixmap_pitch_alignment = 64; - intel->accel_max_x = 2048; - intel->accel_max_y = 2048; - } - - return i830_uxa_init(screen); -} diff --git a/driver/xf86-video-intel/src/i830_bios.c b/driver/xf86-video-intel/src/i830_bios.c index da77cd432..c366ecb0c 100644 --- a/driver/xf86-video-intel/src/i830_bios.c +++ b/driver/xf86-video-intel/src/i830_bios.c @@ -35,7 +35,7 @@ #define _PARSE_EDID_ #include "xf86.h" -#include "i830.h" +#include "intel.h" #include "i830_bios.h" #include "edid.h" diff --git a/driver/xf86-video-intel/src/i830_crt.c b/driver/xf86-video-intel/src/i830_crt.c index b18834e74..8cc061a21 100644 --- a/driver/xf86-video-intel/src/i830_crt.c +++ b/driver/xf86-video-intel/src/i830_crt.c @@ -32,8 +32,9 @@ #include <unistd.h> #include "xf86.h" -#include "i830.h" +#include "intel.h" #include "xf86Modes.h" +#include "i830_reg.h" #include "i830_display.h" static void @@ -511,7 +512,7 @@ i830_crt_get_crtc(xf86OutputPtr output) intel_screen_private *intel = intel_get_screen_private(scrn); int pipe = !!(INREG(ADPA) & ADPA_PIPE_SELECT_MASK); - return i830_pipe_to_crtc(scrn, pipe); + return intel_pipe_to_crtc(scrn, pipe); } #endif diff --git a/driver/xf86-video-intel/src/i830_cursor.c b/driver/xf86-video-intel/src/i830_cursor.c index 675ba0587..d4dd1eadf 100644 --- a/driver/xf86-video-intel/src/i830_cursor.c +++ b/driver/xf86-video-intel/src/i830_cursor.c @@ -52,7 +52,8 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "xf86fbman.h" -#include "i830.h" +#include "intel.h" +#include "i830_reg.h" static void I830SetPipeCursorBase (xf86CrtcPtr crtc) diff --git a/driver/xf86-video-intel/src/i830_display.c b/driver/xf86-video-intel/src/i830_display.c index 243b7a6ae..f83357758 100644 --- a/driver/xf86-video-intel/src/i830_display.c +++ b/driver/xf86-video-intel/src/i830_display.c @@ -38,11 +38,11 @@ #include <sys/ioctl.h> #include "xf86.h" -#include "i830.h" +#include "intel.h" #include "i830_bios.h" #include "i830_display.h" #include "xf86Modes.h" -#include "i810_reg.h" +#include "i830_reg.h" typedef struct { /* given values */ @@ -946,8 +946,8 @@ i830PipeSetBase(xf86CrtcPtr crtc, int x, int y) int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF); int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE; - Offset = ((y * scrn->displayWidth + x) * intel->cpp); - Stride = scrn->displayWidth * intel->cpp; + Offset = y * intel->front_pitch + x * intel->cpp; + Stride = intel->front_pitch; if (intel->front_buffer == NULL) { /* During startup we may be called as part of monitor detection while * there is no memory allocation done, so just supply a dummy base @@ -958,7 +958,7 @@ i830PipeSetBase(xf86CrtcPtr crtc, int x, int y) /* offset is done by shadow painting code, not here */ Start = (char *)crtc->rotatedData - (char *)intel->FbBase; Offset = 0; - Stride = intel_crtc->rotate_mem->pitch; + Stride = intel_crtc->rotate_pitch; } else { Start = intel->front_buffer->offset; } @@ -1063,223 +1063,14 @@ i830_display_tiled(xf86CrtcPtr crtc) if (crtc->rotatedData) return FALSE; - if (intel->front_buffer && intel->front_buffer->tiling != TILE_NONE) - return TRUE; - - return FALSE; -} - -/* - * Several restrictions: - * - DSP[AB]CNTR - no line duplication && no pixel multiplier - * - pixel format == 15 bit, 16 bit, or 32 bit xRGB_8888 - * - no alpha buffer discard - * - no dual wide display - * - progressive mode only (DSP[AB]CNTR) - * - uncompressed fb is <= 2048 in width, 0 mod 8 - * - uncompressed fb is <= 1536 in height, 0 mod 2 - * - SR display watermarks must be equal between 16bpp and 32bpp? - * - * FIXME: verify above conditions are true - * - * Enable 8xx style FB compression - */ -static void -i830_enable_fb_compression_8xx(xf86CrtcPtr crtc) -{ - ScrnInfoPtr scrn = crtc->scrn; - intel_screen_private *intel = intel_get_screen_private(scrn); - I830CrtcPrivatePtr intel_crtc = crtc->driver_private; - uint32_t fbc_ctl = 0; - unsigned long compressed_stride; - int plane = (intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB); - unsigned long uncompressed_stride = scrn->displayWidth * intel->cpp; - unsigned long interval = 1000; - - if (INREG(FBC_CONTROL) & FBC_CTL_EN) - return; - - compressed_stride = intel->compressed_front_buffer->size / - FBC_LL_SIZE; - - if (uncompressed_stride < compressed_stride) - compressed_stride = uncompressed_stride; - - /* FBC_CTL wants 64B units */ - compressed_stride = (compressed_stride / 64) - 1; - - /* Set it up... */ - /* Wait for compressing bit to clear */ - while (INREG(FBC_STATUS) & FBC_STAT_COMPRESSING) - ; /* nothing */ - i830WaitForVblank(scrn); - OUTREG(FBC_CFB_BASE, intel->compressed_front_buffer->bus_addr); - OUTREG(FBC_LL_BASE, intel->compressed_ll_buffer->bus_addr + 6); - OUTREG(FBC_CONTROL2, FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | - FBC_CTL_CPU_FENCE | plane); - OUTREG(FBC_FENCE_OFF, crtc->y); - - /* Zero buffers */ - memset(intel->FbBase + intel->compressed_front_buffer->offset, 0, - intel->compressed_front_buffer->size); - memset(intel->FbBase + intel->compressed_ll_buffer->offset, 0, - intel->compressed_ll_buffer->size); - - /* enable it... */ - fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC; - fbc_ctl |= (compressed_stride & 0xff) << FBC_CTL_STRIDE_SHIFT; - fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT; - fbc_ctl |= FBC_CTL_UNCOMPRESSIBLE; - fbc_ctl |= intel->front_buffer->fence_nr; - OUTREG(FBC_CONTROL, fbc_ctl); -} - -/* - * Disable 8xx style FB compression - */ -static void -i830_disable_fb_compression_8xx(xf86CrtcPtr crtc) -{ - ScrnInfoPtr scrn = crtc->scrn; - intel_screen_private *intel = intel_get_screen_private(scrn); - uint32_t fbc_ctl; - - /* Disable compression */ - fbc_ctl = INREG(FBC_CONTROL); - fbc_ctl &= ~FBC_CTL_EN; - OUTREG(FBC_CONTROL, fbc_ctl); - - /* Wait for compressing bit to clear */ - while (INREG(FBC_STATUS) & FBC_STAT_COMPRESSING) - ; /* nothing */ -} - -static void -i830_disable_fb_compression2(xf86CrtcPtr crtc) -{ - ScrnInfoPtr scrn = crtc->scrn; - intel_screen_private *intel = intel_get_screen_private(scrn); - uint32_t dpfc_ctl; - - /* Disable compression */ - dpfc_ctl = INREG(DPFC_CONTROL); - dpfc_ctl &= ~DPFC_CTL_EN; - OUTREG(DPFC_CONTROL, dpfc_ctl); - i830WaitForVblank(scrn); -} - -static void -i830_enable_fb_compression2(xf86CrtcPtr crtc) -{ - ScrnInfoPtr scrn = crtc->scrn; - intel_screen_private *intel = intel_get_screen_private(scrn); - I830CrtcPrivatePtr intel_crtc = crtc->driver_private; - int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB); - unsigned long stall_watermark = 200, frames = 50; - - if (INREG(DPFC_CONTROL) & DPFC_CTL_EN) - return; - - /* Set it up... */ - i830_disable_fb_compression2(crtc); - OUTREG(DPFC_CB_BASE, intel->compressed_front_buffer->offset); - /* Update i830_memory.c too if compression ratio changes */ - OUTREG(DPFC_CONTROL, plane | DPFC_CTL_FENCE_EN | DPFC_CTL_LIMIT_4X | - intel->front_buffer->fence_nr); - OUTREG(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | - (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | - (frames << DPFC_RECOMP_TIMER_COUNT_SHIFT)); - OUTREG(DPFC_FENCE_YOFF, crtc->y); - - /* Zero buffers */ - memset(intel->FbBase + intel->compressed_front_buffer->offset, 0, - intel->compressed_front_buffer->size); - - /* enable it... */ - OUTREG(DPFC_CONTROL, INREG(DPFC_CONTROL) | DPFC_CTL_EN); -} - -static void -i830_enable_fb_compression(xf86CrtcPtr crtc) -{ - ScrnInfoPtr scrn = crtc->scrn; - intel_screen_private *intel = intel_get_screen_private(scrn); - - if (IS_GM45(intel)) - return i830_enable_fb_compression2(crtc); - - i830_enable_fb_compression_8xx(crtc); -} - -static void -i830_disable_fb_compression(xf86CrtcPtr crtc) -{ - ScrnInfoPtr scrn = crtc->scrn; - intel_screen_private *intel = intel_get_screen_private(scrn); - - if (IS_GM45(intel)) - return i830_disable_fb_compression2(crtc); - - i830_disable_fb_compression_8xx(crtc); -} - -static Bool -i830_use_fb_compression(xf86CrtcPtr crtc) -{ - ScrnInfoPtr scrn = crtc->scrn; - xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(scrn); - intel_screen_private *intel = intel_get_screen_private(scrn); - I830CrtcPrivatePtr intel_crtc = crtc->driver_private; - unsigned long uncompressed_size; - int plane = (intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB); - int i, count = 0; - - /* Only available on one pipe at a time */ - for (i = 0; i < xf86_config->num_crtc; i++) { - if (xf86_config->crtc[i]->enabled) - count++; - } - - /* Here we disable it to catch one->two pipe enabled configs */ - if (count > 1) { - if (i830_fb_compression_supported(intel)) - i830_disable_fb_compression(crtc); - return FALSE; + if (intel->front_buffer) { + uint32_t tiling_mode, swizzle; + if (drm_intel_bo_get_tiling(intel->front_buffer, + &tiling_mode, &swizzle) == 0 && tiling_mode != I915_TILING_NONE) + return TRUE; } - if (!intel->fb_compression) - return FALSE; - - if (!i830_display_tiled(crtc)) - return FALSE; - - /* Pre-965 only supports plane A */ - if (!IS_I965GM(intel) && plane != FBC_CTL_PLANEA) - return FALSE; - - /* Need 15, 16, or 32 (w/alpha) pixel format */ - if (!(scrn->bitsPerPixel == 16 || /* covers 15 bit mode as well */ - scrn->bitsPerPixel == 32)) /* mode_set dtrt if fbc is in use */ - return FALSE; - - /* Can't cache more lines than we can track */ - if (crtc->mode.VDisplay > FBC_LL_SIZE) - return FALSE; - - /* - * Make sure the compressor doesn't go past the end of our compressed - * buffer if the uncompressed size is large. - */ - uncompressed_size = crtc->mode.HDisplay * crtc->mode.VDisplay * - intel->cpp; - if (intel->compressed_front_buffer->size < uncompressed_size) - return FALSE; - - /* - * No checks for pixel multiply, incl. horizontal, or interlaced modes - * since they're currently unused. - */ - return TRUE; + return FALSE; } #if defined(DRM_IOCTL_MODESET_CTL) @@ -1321,7 +1112,7 @@ i830_disable_vga_plane (xf86CrtcPtr crtc) { ScrnInfoPtr scrn = crtc->scrn; intel_screen_private *intel = intel_get_screen_private(scrn); - uint8_t sr01; + uint8_t sr01 = 0; uint32_t vga_reg, vgacntrl; if (IS_IGDNG(intel)) @@ -1412,9 +1203,6 @@ i830_crtc_enable(xf86CrtcPtr crtc) /* Give the overlay scaler a chance to enable if it's on this pipe */ i830_crtc_dpms_video(crtc, TRUE); - /* Reenable compression if needed */ - if (i830_use_fb_compression(crtc)) - i830_enable_fb_compression(crtc); i830_modeset_ctl(crtc, 0); } @@ -1433,9 +1221,6 @@ i830_crtc_disable(xf86CrtcPtr crtc, Bool disable_pipe) uint32_t temp; i830_modeset_ctl(crtc, 1); - /* Shut off compression if in use */ - if (i830_use_fb_compression(crtc)) - i830_disable_fb_compression(crtc); /* Give the overlay scaler a chance to disable if it's on this pipe */ i830_crtc_dpms_video(crtc, FALSE); @@ -1997,9 +1782,6 @@ static void i830_crtc_prepare (xf86CrtcPtr crtc) { I830CrtcPrivatePtr intel_crtc = crtc->driver_private; - /* Temporarily turn off FB compression during modeset */ - if (i830_use_fb_compression(crtc)) - i830_disable_fb_compression(crtc); if (intel_crtc->enabled) crtc->funcs->hide_cursor (crtc); crtc->funcs->dpms (crtc, DPMSModeOff); @@ -2021,10 +1803,6 @@ i830_crtc_commit (xf86CrtcPtr crtc) xf86_reload_cursors (crtc->scrn->pScreen); if (deactivate) i830_pipe_a_require_deactivate (crtc->scrn); - - /* Reenable FB compression if possible */ - if (i830_use_fb_compression(crtc)) - i830_enable_fb_compression(crtc); } void @@ -2309,6 +2087,7 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, switch (intel_output->type) { case I830_OUTPUT_LVDS: + ErrorF("is lvds\n"); is_lvds = TRUE; lvds_bits = intel_output->lvds_bits; break; @@ -2327,6 +2106,7 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, is_tv = TRUE; break; case I830_OUTPUT_ANALOG: + ErrorF("is crt\n"); is_crt = TRUE; break; } @@ -2554,7 +2334,7 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, * will be run after the mode is set. On 9xx, it helps. * On 855, it can lock up the chip (and the entire machine) */ - if (!IS_I85X (intel)) + if (!IS_I85X (intel) && !IS_IGDNG(intel)) { dspcntr |= DISPLAY_PLANE_ENABLE; pipeconf |= PIPEACONF_ENABLE; @@ -2797,24 +2577,19 @@ i830_crtc_shadow_allocate (xf86CrtcPtr crtc, int width, int height) intel_screen_private *intel = intel_get_screen_private(scrn); I830CrtcPrivatePtr intel_crtc = crtc->driver_private; unsigned long rotate_pitch; - int align = KB(4), size; - - width = i830_pad_drawable_width(width); - rotate_pitch = width * intel->cpp; - size = rotate_pitch * height; + uint32_t tiling; - assert(intel_crtc->rotate_mem == NULL); - intel_crtc->rotate_mem = i830_allocate_memory(scrn, "rotated crtc", - size, rotate_pitch, align, - 0, TILE_NONE); - if (intel_crtc->rotate_mem == NULL) { + assert(intel_crtc->rotate_bo == NULL); + intel_crtc->rotate_bo = intel_allocate_framebuffer(scrn, width, height, + intel->cpp, &rotate_pitch, &tiling); + if (intel_crtc->rotate_bo == NULL) { xf86DrvMsg(scrn->scrnIndex, X_ERROR, "Couldn't allocate shadow memory for rotated CRTC\n"); return NULL; } - memset(intel->FbBase + intel_crtc->rotate_mem->offset, 0, size); - return intel->FbBase + intel_crtc->rotate_mem->offset; + intel_crtc->rotate_pitch = rotate_pitch; + return intel->FbBase + intel_crtc->rotate_bo->offset; } /** @@ -2824,29 +2599,33 @@ static PixmapPtr i830_crtc_shadow_create(xf86CrtcPtr crtc, void *data, int width, int height) { ScrnInfoPtr scrn = crtc->scrn; - I830CrtcPrivatePtr intel_crtc = crtc->driver_private; intel_screen_private *intel = intel_get_screen_private(scrn); - int rotate_pitch; + I830CrtcPrivatePtr intel_crtc = crtc->driver_private; PixmapPtr rotate_pixmap; if (!data) data = i830_crtc_shadow_allocate (crtc, width, height); - - rotate_pitch = i830_pad_drawable_width(width) * intel->cpp; + if (intel_crtc->rotate_bo == NULL) { + xf86DrvMsg(scrn->scrnIndex, X_ERROR, + "Couldn't allocate shadow pixmap for rotated CRTC\n"); + } + rotate_pixmap = GetScratchPixmapHeader(scrn->pScreen, width, height, scrn->depth, scrn->bitsPerPixel, - rotate_pitch, + intel_crtc->rotate_pitch, data); if (rotate_pixmap == NULL) { xf86DrvMsg(scrn->scrnIndex, X_ERROR, "Couldn't allocate shadow pixmap for rotated CRTC\n"); } - if (intel_crtc->rotate_mem && intel_crtc->rotate_mem->bo) - i830_set_pixmap_bo(rotate_pixmap, intel_crtc->rotate_mem->bo); + intel_set_pixmap_bo(rotate_pixmap, intel_crtc->rotate_bo); + + intel->shadow_present = TRUE; + return rotate_pixmap; } @@ -2854,19 +2633,24 @@ static void i830_crtc_shadow_destroy(xf86CrtcPtr crtc, PixmapPtr rotate_pixmap, void *data) { ScrnInfoPtr scrn = crtc->scrn; + intel_screen_private *intel = intel_get_screen_private(scrn); I830CrtcPrivatePtr intel_crtc = crtc->driver_private; if (rotate_pixmap) { - i830_set_pixmap_bo(rotate_pixmap, NULL); + intel_set_pixmap_bo(rotate_pixmap, NULL); FreeScratchPixmapHeader(rotate_pixmap); } if (data) { /* Be sure to sync acceleration before the memory gets unbound. */ intel_sync(scrn); - i830_free_memory(scrn, intel_crtc->rotate_mem); - intel_crtc->rotate_mem = NULL; + if (scrn->vtSema) + (void)dri_bo_unpin(intel_crtc->rotate_bo); + drm_intel_bo_unreference(intel_crtc->rotate_bo); + intel_crtc->rotate_bo = NULL; } + + intel->shadow_present = intel->use_shadow; } #if RANDR_13_INTERFACE diff --git a/driver/xf86-video-intel/src/i830_dvo.c b/driver/xf86-video-intel/src/i830_dvo.c index bccbe7b02..5efb97676 100644 --- a/driver/xf86-video-intel/src/i830_dvo.c +++ b/driver/xf86-video-intel/src/i830_dvo.c @@ -30,9 +30,9 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #endif #include "xf86.h" -#include "i830.h" +#include "intel.h" #include "i830_display.h" -#include "i810_reg.h" +#include "i830_reg.h" #include "sil164/sil164.h" #include "ch7xxx/ch7xxx.h" @@ -316,7 +316,7 @@ i830_dvo_get_crtc(xf86OutputPtr output) struct _I830DVODriver *drv = intel_output->i2c_drv; int pipe = !!(INREG(drv->dvo_reg) & SDVO_PIPE_B_SELECT); - return i830_pipe_to_crtc(scrn, pipe); + return intel_pipe_to_crtc(scrn, pipe); } #endif diff --git a/driver/xf86-video-intel/src/i830_hdmi.c b/driver/xf86-video-intel/src/i830_hdmi.c index 41b264ec7..980fea85c 100644 --- a/driver/xf86-video-intel/src/i830_hdmi.c +++ b/driver/xf86-video-intel/src/i830_hdmi.c @@ -30,9 +30,10 @@ #endif #include "xf86.h" -#include "i830.h" +#include "intel.h" #include "xf86Modes.h" #include "i830_display.h" +#include "i830_reg.h" #include "X11/Xatom.h" struct i830_hdmi_priv { diff --git a/driver/xf86-video-intel/src/i830_i2c.c b/driver/xf86-video-intel/src/i830_i2c.c index 038513df6..925aef74a 100644 --- a/driver/xf86-video-intel/src/i830_i2c.c +++ b/driver/xf86-video-intel/src/i830_i2c.c @@ -44,7 +44,8 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #include "xf86xv.h" #include <X11/extensions/Xv.h> #include "shadow.h" -#include "i830.h" +#include "intel.h" +#include "i830_reg.h" #define AIRLIED_I2C 0 diff --git a/driver/xf86-video-intel/src/i830_io.c b/driver/xf86-video-intel/src/i830_io.c index 8006789d2..60fe2611f 100644 --- a/driver/xf86-video-intel/src/i830_io.c +++ b/driver/xf86-video-intel/src/i830_io.c @@ -1,6 +1,6 @@ /************************************************************************** -Copyright 2005 Red Hat, Inc. +Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas. All Rights Reserved. Permission is hereby granted, free of charge, to any person obtaining a @@ -18,18 +18,112 @@ of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. -IN NO EVENT SHALL RED HAT, INC AND/OR ITS SUPPLIERS BE LIABLE FOR +IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. **************************************************************************/ +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + /* * Authors: - * Kristian Høgsberg <krh@redhat.com> + * Daryll Strauss <daryll@precisioninsight.com> * */ -#define BUILD_FOR_I830 1 -#include "i810_io.c" +#include "xf86.h" +#include "xf86_OSproc.h" +#include "compiler.h" + +#include "intel.h" +#define pI810 intel +#define I810Ptr intel_screen_private * +#define I810WriteControlPIO I830WriteControlPIO +#define I810ReadControlPIO I830ReadControlPIO +#define I810WriteStandardPIO I830WriteStandardPIO +#define I810ReadStandardPIO I830ReadStandardPIO +#define I810SetPIOAccess I830SetPIOAccess +#define I810WriteControlMMIO I830WriteControlMMIO +#define I810ReadControlMMIO I830ReadControlMMIO +#define I810WriteStandardMMIO I830WriteStandardMMIO +#define I810ReadStandardMMIO I830ReadStandardMMIO +#define I810SetMMIOAccess I830SetMMIOAccess + +#define minb(p) *(volatile uint8_t *)(pI810->MMIOBase + (p)) +#define moutb(p,v) *(volatile uint8_t *)(pI810->MMIOBase + (p)) = (v) + +static void +I810WriteControlPIO(I810Ptr pI810, IOADDRESS addr, uint8_t index, uint8_t val) +{ + addr += pI810->ioBase; + outb(addr, index); + outb(addr + 1, val); +} + +static uint8_t +I810ReadControlPIO(I810Ptr pI810, IOADDRESS addr, uint8_t index) +{ + addr += pI810->ioBase; + outb(addr, index); + return inb(addr + 1); +} + +static void +I810WriteStandardPIO(I810Ptr pI810, IOADDRESS addr, uint8_t val) +{ + outb(pI810->ioBase + addr, val); +} + +static uint8_t +I810ReadStandardPIO(I810Ptr pI810, IOADDRESS addr) +{ + return inb(pI810->ioBase + addr); +} + +void +I810SetPIOAccess(I810Ptr pI810) +{ + pI810->writeControl = I810WriteControlPIO; + pI810->readControl = I810ReadControlPIO; + pI810->writeStandard = I810WriteStandardPIO; + pI810->readStandard = I810ReadStandardPIO; +} + +static void +I810WriteControlMMIO(I810Ptr pI810, IOADDRESS addr, uint8_t index, uint8_t val) +{ + moutb(addr, index); + moutb(addr + 1, val); +} + +static uint8_t +I810ReadControlMMIO(I810Ptr pI810, IOADDRESS addr, uint8_t index) +{ + moutb(addr, index); + return minb(addr + 1); +} + +static void +I810WriteStandardMMIO(I810Ptr pI810, IOADDRESS addr, uint8_t val) +{ + moutb(addr, val); +} + +static uint8_t +I810ReadStandardMMIO(I810Ptr pI810, IOADDRESS addr) +{ + return minb(addr); +} + +void +I810SetMMIOAccess(I810Ptr pI810) +{ + pI810->writeControl = I810WriteControlMMIO; + pI810->readControl = I810ReadControlMMIO; + pI810->writeStandard = I810WriteStandardMMIO; + pI810->readStandard = I810ReadStandardMMIO; +} diff --git a/driver/xf86-video-intel/src/i830_lvds.c b/driver/xf86-video-intel/src/i830_lvds.c index 651916cf5..03f8a321e 100644 --- a/driver/xf86-video-intel/src/i830_lvds.c +++ b/driver/xf86-video-intel/src/i830_lvds.c @@ -40,7 +40,8 @@ #include <sys/types.h> #include "xf86.h" -#include "i830.h" +#include "intel.h" +#include "i830_reg.h" #include "i830_bios.h" #include "i830_display.h" #include "X11/Xatom.h" @@ -182,9 +183,14 @@ i830_lvds_get_backlight_native(xf86OutputPtr output) { ScrnInfoPtr scrn = output->scrn; intel_screen_private *intel = intel_get_screen_private(scrn); - uint32_t blc_pwm_ctl; + uint32_t blc_pwm_ctl, reg; - blc_pwm_ctl = INREG(BLC_PWM_CTL); + if (IS_IGDNG(intel)) + reg = BLC_PWM_CPU_CTL; + else + reg = BLC_PWM_CTL; + + blc_pwm_ctl = INREG(reg); blc_pwm_ctl &= BACKLIGHT_DUTY_CYCLE_MASK; return blc_pwm_ctl; } @@ -1494,7 +1500,7 @@ i830_lvds_get_crtc(xf86OutputPtr output) intel_screen_private *intel = intel_get_screen_private(scrn); int pipe = !!(INREG(LVDS) & LVDS_PIPEB_SELECT); - return i830_pipe_to_crtc(scrn, pipe); + return intel_pipe_to_crtc(scrn, pipe); } #endif diff --git a/driver/xf86-video-intel/src/i830_modes.c b/driver/xf86-video-intel/src/i830_modes.c index 4aa493ea7..af7fad093 100644 --- a/driver/xf86-video-intel/src/i830_modes.c +++ b/driver/xf86-video-intel/src/i830_modes.c @@ -49,7 +49,7 @@ #include "xf86.h" #include "xf86DDC.h" #include "X11/Xatom.h" -#include "i830.h" +#include "intel.h" #include "i830_display.h" #include "xf86Modes.h" #include <randrstr.h> diff --git a/driver/xf86-video-intel/src/i830_quirks.c b/driver/xf86-video-intel/src/i830_quirks.c index 285856933..01295a56b 100644 --- a/driver/xf86-video-intel/src/i830_quirks.c +++ b/driver/xf86-video-intel/src/i830_quirks.c @@ -28,7 +28,7 @@ #include "config.h" #endif -#include "i830.h" +#include "intel.h" #define SUBSYS_ANY (~0) diff --git a/driver/xf86-video-intel/src/i830_reg.h b/driver/xf86-video-intel/src/i830_reg.h index 3bba44dab..fa4d288c5 100644 --- a/driver/xf86-video-intel/src/i830_reg.h +++ b/driver/xf86-video-intel/src/i830_reg.h @@ -30,6 +30,75 @@ #define I830_SET_FIELD( var, mask, value ) (var &= ~(mask), var |= value) +/* Flush */ +#define MI_FLUSH (0x04<<23) +#define MI_FLUSH_DW (0x26<<23) + +#define MI_WRITE_DIRTY_STATE (1<<4) +#define MI_END_SCENE (1<<3) +#define MI_GLOBAL_SNAPSHOT_COUNT_RESET (1<<3) +#define MI_INHIBIT_RENDER_CACHE_FLUSH (1<<2) +#define MI_STATE_INSTRUCTION_CACHE_FLUSH (1<<1) +#define MI_INVALIDATE_MAP_CACHE (1<<0) +/* broadwater flush bits */ +#define BRW_MI_GLOBAL_SNAPSHOT_RESET (1 << 3) + +#define MI_BATCH_BUFFER_END (0xA << 23) + +/* Noop */ +#define MI_NOOP 0x00 +#define MI_NOOP_WRITE_ID (1<<22) +#define MI_NOOP_ID_MASK (1<<22 - 1) + +/* Wait for Events */ +#define MI_WAIT_FOR_EVENT (0x03<<23) +#define MI_WAIT_FOR_PIPEB_SVBLANK (1<<18) +#define MI_WAIT_FOR_PIPEA_SVBLANK (1<<17) +#define MI_WAIT_FOR_OVERLAY_FLIP (1<<16) +#define MI_WAIT_FOR_PIPEB_VBLANK (1<<7) +#define MI_WAIT_FOR_PIPEB_SCAN_LINE_WINDOW (1<<5) +#define MI_WAIT_FOR_PIPEA_VBLANK (1<<3) +#define MI_WAIT_FOR_PIPEA_SCAN_LINE_WINDOW (1<<1) + +/* Set the scan line for MI_WAIT_FOR_PIPE?_SCAN_LINE_WINDOW */ +#define MI_LOAD_SCAN_LINES_INCL (0x12<<23) +#define MI_LOAD_SCAN_LINES_DISPLAY_PIPEA (0) +#define MI_LOAD_SCAN_LINES_DISPLAY_PIPEB (0x1<<20) + +/* BLT commands */ +#define COLOR_BLT_CMD ((2<<29)|(0x40<<22)|(0x3)) +#define COLOR_BLT_WRITE_ALPHA (1<<21) +#define COLOR_BLT_WRITE_RGB (1<<20) + +#define XY_COLOR_BLT_CMD ((2<<29)|(0x50<<22)|(0x4)) +#define XY_COLOR_BLT_WRITE_ALPHA (1<<21) +#define XY_COLOR_BLT_WRITE_RGB (1<<20) +#define XY_COLOR_BLT_TILED (1<<11) + +#define XY_SETUP_CLIP_BLT_CMD ((2<<29)|(3<<22)|1) + +#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) +#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) +#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) +#define XY_SRC_COPY_BLT_SRC_TILED (1<<15) +#define XY_SRC_COPY_BLT_DST_TILED (1<<11) + +#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|0x4) +#define SRC_COPY_BLT_WRITE_ALPHA (1<<21) +#define SRC_COPY_BLT_WRITE_RGB (1<<20) + +#define XY_PAT_BLT_IMMEDIATE ((2<<29)|(0x72<<22)) + +#define XY_MONO_PAT_BLT_CMD ((0x2<<29)|(0x52<<22)|0x7) +#define XY_MONO_PAT_VERT_SEED ((1<<10)|(1<<9)|(1<<8)) +#define XY_MONO_PAT_HORT_SEED ((1<<14)|(1<<13)|(1<<12)) +#define XY_MONO_PAT_BLT_WRITE_ALPHA (1<<21) +#define XY_MONO_PAT_BLT_WRITE_RGB (1<<20) + +#define XY_MONO_SRC_BLT_CMD ((0x2<<29)|(0x54<<22)|(0x6)) +#define XY_MONO_SRC_BLT_WRITE_ALPHA (1<<21) +#define XY_MONO_SRC_BLT_WRITE_RGB (1<<20) + #define CMD_3D (0x3<<29) #define PRIM3D_INLINE (CMD_3D | (0x1f<<24)) @@ -733,4 +802,3463 @@ #define MIPFILTER_NEAREST 1 #define MIPFILTER_LINEAR 3 +/* I/O register offsets + */ +#define SRX 0x3C4 /* p208 */ +#define GRX 0x3CE /* p213 */ +#define ARX 0x3C0 /* p224 */ + +/* VGA Color Palette Registers */ +#define DACMASK 0x3C6 /* p232 */ +#define DACSTATE 0x3C7 /* p232 */ +#define DACRX 0x3C7 /* p233 */ +#define DACWX 0x3C8 /* p233 */ +#define DACDATA 0x3C9 /* p233 */ + +/* CRT Controller Registers (CRX) */ +#define START_ADDR_HI 0x0C /* p246 */ +#define START_ADDR_LO 0x0D /* p247 */ +#define VERT_SYNC_END 0x11 /* p249 */ +#define EXT_VERT_TOTAL 0x30 /* p257 */ +#define EXT_VERT_DISPLAY 0x31 /* p258 */ +#define EXT_VERT_SYNC_START 0x32 /* p259 */ +#define EXT_VERT_BLANK_START 0x33 /* p260 */ +#define EXT_HORIZ_TOTAL 0x35 /* p261 */ +#define EXT_HORIZ_BLANK 0x39 /* p261 */ +#define EXT_START_ADDR 0x40 /* p262 */ +#define EXT_START_ADDR_ENABLE 0x80 +#define EXT_OFFSET 0x41 /* p263 */ +#define EXT_START_ADDR_HI 0x42 /* p263 */ +#define INTERLACE_CNTL 0x70 /* p264 */ +#define INTERLACE_ENABLE 0x80 +#define INTERLACE_DISABLE 0x00 + +/* Miscellaneous Output Register + */ +#define MSR_R 0x3CC /* p207 */ +#define MSR_W 0x3C2 /* p207 */ +#define IO_ADDR_SELECT 0x01 + +#define MDA_BASE 0x3B0 /* p207 */ +#define CGA_BASE 0x3D0 /* p207 */ + +/* CR80 - IO Control, p264 + */ +#define IO_CTNL 0x80 +#define EXTENDED_ATTR_CNTL 0x02 +#define EXTENDED_CRTC_CNTL 0x01 + +/* GR10 - Address mapping, p221 + */ +#define ADDRESS_MAPPING 0x10 +#define PAGE_TO_LOCAL_MEM_ENABLE 0x10 +#define GTT_MEM_MAP_ENABLE 0x08 +#define PACKED_MODE_ENABLE 0x04 +#define LINEAR_MODE_ENABLE 0x02 +#define PAGE_MAPPING_ENABLE 0x01 + +#define HOTKEY_VBIOS_SWITCH_BLOCK 0x80 +#define HOTKEY_SWITCH 0x20 +#define HOTKEY_TOGGLE 0x10 + +/* Blitter control, p378 + */ +#define BITBLT_CNTL 0x7000c +#define COLEXP_MODE 0x30 +#define COLEXP_8BPP 0x00 +#define COLEXP_16BPP 0x10 +#define COLEXP_24BPP 0x20 +#define COLEXP_RESERVED 0x30 +#define BITBLT_STATUS 0x01 + +#define CHDECMISC 0x10111 +#define DCC 0x10200 +#define C0DRB0 0x10200 +#define C0DRB1 0x10202 +#define C0DRB2 0x10204 +#define C0DRB3 0x10206 +#define C0DRA01 0x10208 +#define C0DRA23 0x1020a +#define C1DRB0 0x10600 +#define C1DRB1 0x10602 +#define C1DRB2 0x10604 +#define C1DRB3 0x10606 +#define C1DRA01 0x10608 +#define C1DRA23 0x1060a + +/* p375. + */ +#define DISPLAY_CNTL 0x70008 +#define VGA_WRAP_MODE 0x02 +#define VGA_WRAP_AT_256KB 0x00 +#define VGA_NO_WRAP 0x02 +#define GUI_MODE 0x01 +#define STANDARD_VGA_MODE 0x00 +#define HIRES_MODE 0x01 + +/* p375 + */ +#define PIXPIPE_CONFIG_0 0x70009 +#define DAC_8_BIT 0x80 +#define DAC_6_BIT 0x00 +#define HW_CURSOR_ENABLE 0x10 +#define EXTENDED_PALETTE 0x01 + +/* p375 + */ +#define PIXPIPE_CONFIG_1 0x7000a +#define DISPLAY_COLOR_MODE 0x0F +#define DISPLAY_VGA_MODE 0x00 +#define DISPLAY_8BPP_MODE 0x02 +#define DISPLAY_15BPP_MODE 0x04 +#define DISPLAY_16BPP_MODE 0x05 +#define DISPLAY_24BPP_MODE 0x06 +#define DISPLAY_32BPP_MODE 0x07 + +/* p375 + */ +#define PIXPIPE_CONFIG_2 0x7000b +#define DISPLAY_GAMMA_ENABLE 0x08 +#define DISPLAY_GAMMA_DISABLE 0x00 +#define OVERLAY_GAMMA_ENABLE 0x04 +#define OVERLAY_GAMMA_DISABLE 0x00 + + +/* p380 + */ +#define DISPLAY_BASE 0x70020 +#define DISPLAY_BASE_MASK 0x03fffffc + + +/* Cursor control registers, pp383-384 + */ +/* Desktop (845G, 865G) */ +#define CURSOR_CONTROL 0x70080 +#define CURSOR_ENABLE 0x80000000 +#define CURSOR_GAMMA_ENABLE 0x40000000 +#define CURSOR_STRIDE_MASK 0x30000000 +#define CURSOR_FORMAT_SHIFT 24 +#define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT) +#define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT) +#define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT) +#define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT) +#define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT) +#define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT) + +/* Mobile and i810 */ +#define CURSOR_A_CONTROL CURSOR_CONTROL +#define CURSOR_ORIGIN_SCREEN 0x00 /* i810 only */ +#define CURSOR_ORIGIN_DISPLAY 0x1 /* i810 only */ +#define CURSOR_MODE 0x27 +#define CURSOR_MODE_DISABLE 0x00 +#define CURSOR_MODE_32_4C_AX 0x01 /* i810 only */ +#define CURSOR_MODE_64_3C 0x04 +#define CURSOR_MODE_64_4C_AX 0x05 +#define CURSOR_MODE_64_4C 0x06 +#define CURSOR_MODE_64_32B_AX 0x07 +#define CURSOR_MODE_64_ARGB_AX (0x20 | CURSOR_MODE_64_32B_AX) +#define MCURSOR_PIPE_SELECT (1 << 28) +#define MCURSOR_PIPE_A 0x00 +#define MCURSOR_PIPE_B (1 << 28) +#define MCURSOR_GAMMA_ENABLE (1 << 26) +#define MCURSOR_MEM_TYPE_LOCAL (1 << 25) + + +#define CURSOR_BASEADDR 0x70084 +#define CURSOR_A_BASE CURSOR_BASEADDR +#define CURSOR_BASEADDR_MASK 0x1FFFFF00 +#define CURSOR_A_POSITION 0x70088 +#define CURSOR_POS_SIGN 0x8000 +#define CURSOR_POS_MASK 0x007FF +#define CURSOR_X_SHIFT 0 +#define CURSOR_Y_SHIFT 16 +#define CURSOR_X_LO 0x70088 +#define CURSOR_X_HI 0x70089 +#define CURSOR_X_POS 0x00 +#define CURSOR_X_NEG 0x80 +#define CURSOR_Y_LO 0x7008A +#define CURSOR_Y_HI 0x7008B +#define CURSOR_Y_POS 0x00 +#define CURSOR_Y_NEG 0x80 + +#define CURSOR_A_PALETTE0 0x70090 +#define CURSOR_A_PALETTE1 0x70094 +#define CURSOR_A_PALETTE2 0x70098 +#define CURSOR_A_PALETTE3 0x7009C + +#define CURSOR_SIZE 0x700A0 +#define CURSOR_SIZE_MASK 0x3FF +#define CURSOR_SIZE_HSHIFT 0 +#define CURSOR_SIZE_VSHIFT 12 + +#define CURSOR_B_CONTROL 0x700C0 +#define CURSOR_B_BASE 0x700C4 +#define CURSOR_B_POSITION 0x700C8 +#define CURSOR_B_PALETTE0 0x700D0 +#define CURSOR_B_PALETTE1 0x700D4 +#define CURSOR_B_PALETTE2 0x700D8 +#define CURSOR_B_PALETTE3 0x700DC + + +/* Similar registers exist in Device 0 on the i810 (pp55-65), but I'm + * not sure they refer to local (graphics) memory. + * + * These details are for the local memory control registers, + * (pp301-310). The test machines are not equiped with local memory, + * so nothing is tested. Only a single row seems to be supported. + */ +#define DRAM_ROW_TYPE 0x3000 +#define DRAM_ROW_0 0x01 +#define DRAM_ROW_0_SDRAM 0x01 +#define DRAM_ROW_0_EMPTY 0x00 +#define DRAM_ROW_CNTL_LO 0x3001 +#define DRAM_PAGE_MODE_CTRL 0x10 +#define DRAM_RAS_TO_CAS_OVRIDE 0x08 +#define DRAM_CAS_LATENCY 0x04 +#define DRAM_RAS_TIMING 0x02 +#define DRAM_RAS_PRECHARGE 0x01 +#define DRAM_ROW_CNTL_HI 0x3002 +#define DRAM_REFRESH_RATE 0x18 +#define DRAM_REFRESH_DISABLE 0x00 +#define DRAM_REFRESH_60HZ 0x08 +#define DRAM_REFRESH_FAST_TEST 0x10 +#define DRAM_REFRESH_RESERVED 0x18 +#define DRAM_SMS 0x07 +#define DRAM_SMS_NORMAL 0x00 +#define DRAM_SMS_NOP_ENABLE 0x01 +#define DRAM_SMS_ABPCE 0x02 +#define DRAM_SMS_MRCE 0x03 +#define DRAM_SMS_CBRCE 0x04 + +/* p307 + */ +#define DPMS_SYNC_SELECT 0x5002 +#define VSYNC_CNTL 0x08 +#define VSYNC_ON 0x00 +#define VSYNC_OFF 0x08 +#define HSYNC_CNTL 0x02 +#define HSYNC_ON 0x00 +#define HSYNC_OFF 0x02 + +#define GPIOA 0x5010 +#define GPIOB 0x5014 +#define GPIOC 0x5018 +#define GPIOD 0x501c +#define GPIOE 0x5020 +#define GPIOF 0x5024 +#define GPIOG 0x5028 +#define GPIOH 0x502c +# define GPIO_CLOCK_DIR_MASK (1 << 0) +# define GPIO_CLOCK_DIR_IN (0 << 1) +# define GPIO_CLOCK_DIR_OUT (1 << 1) +# define GPIO_CLOCK_VAL_MASK (1 << 2) +# define GPIO_CLOCK_VAL_OUT (1 << 3) +# define GPIO_CLOCK_VAL_IN (1 << 4) +# define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) +# define GPIO_DATA_DIR_MASK (1 << 8) +# define GPIO_DATA_DIR_IN (0 << 9) +# define GPIO_DATA_DIR_OUT (1 << 9) +# define GPIO_DATA_VAL_MASK (1 << 10) +# define GPIO_DATA_VAL_OUT (1 << 11) +# define GPIO_DATA_VAL_IN (1 << 12) +# define GPIO_DATA_PULLUP_DISABLE (1 << 13) + +/* GMBus registers for hardware-assisted (non-bitbanging) I2C access */ +#define GMBUS0 0x5100 +#define GMBUS1 0x5104 +#define GMBUS2 0x5108 +#define GMBUS3 0x510c +#define GMBUS4 0x5110 +#define GMBUS5 0x5120 + +/* p317, 319 + */ +#define VCLK2_VCO_M 0x6008 /* treat as 16 bit? (includes msbs) */ +#define VCLK2_VCO_N 0x600a +#define VCLK2_VCO_DIV_SEL 0x6012 + +#define VCLK_DIVISOR_VGA0 0x6000 +#define VCLK_DIVISOR_VGA1 0x6004 +#define VCLK_POST_DIV 0x6010 +/** Selects a post divisor of 4 instead of 2. */ +# define VGA1_PD_P2_DIV_4 (1 << 15) +/** Overrides the p2 post divisor field */ +# define VGA1_PD_P1_DIV_2 (1 << 13) +# define VGA1_PD_P1_SHIFT 8 +/** P1 value is 2 greater than this field */ +# define VGA1_PD_P1_MASK (0x1f << 8) +/** Selects a post divisor of 4 instead of 2. */ +# define VGA0_PD_P2_DIV_4 (1 << 7) +/** Overrides the p2 post divisor field */ +# define VGA0_PD_P1_DIV_2 (1 << 5) +# define VGA0_PD_P1_SHIFT 0 +/** P1 value is 2 greater than this field */ +# define VGA0_PD_P1_MASK (0x1f << 0) + +#define POST_DIV_SELECT 0x70 +#define POST_DIV_1 0x00 +#define POST_DIV_2 0x10 +#define POST_DIV_4 0x20 +#define POST_DIV_8 0x30 +#define POST_DIV_16 0x40 +#define POST_DIV_32 0x50 +#define VCO_LOOP_DIV_BY_4M 0x00 +#define VCO_LOOP_DIV_BY_16M 0x04 + + +/* Instruction Parser Mode Register + * - p281 + * - 2 new bits. + */ +#define INST_PM 0x20c0 +#define AGP_SYNC_PACKET_FLUSH_ENABLE 0x20 /* reserved */ +#define SYNC_PACKET_FLUSH_ENABLE 0x10 +#define TWO_D_INST_DISABLE 0x08 +#define THREE_D_INST_DISABLE 0x04 +#define STATE_VAR_UPDATE_DISABLE 0x02 +#define PAL_STIP_DISABLE 0x01 + + +#define MEMMODE 0x20dc + + +/* Instruction parser error register. p279 + */ +#define IPEIR 0x2088 +#define IPEHR 0x208C + +#define INST_DONE 0x2090 +# define IDCT_DONE (1 << 30) +# define IQ_DONE (1 << 29) +# define PR_DONE (1 << 28) +# define VLD_DONE (1 << 27) +# define IP_DONE (1 << 26) +# define FBC_DONE (1 << 25) +# define BINNER_DONE (1 << 24) +# define SF_DONE (1 << 23) +# define SE_DONE (1 << 22) +# define WM_DONE (1 << 21) +# define IZ_DONE (1 << 20) +# define PERSPECTIVE_INTERP_DONE (1 << 19) +# define DISPATCHER_DONE (1 << 18) +# define PROJECTION_DONE (1 << 17) +# define DEPENDENT_ADDRESS_DONE (1 << 16) +# define QUAD_CACHE_DONE (1 << 15) +# define TEXTURE_FETCH_DONE (1 << 14) +# define TEXTURE_DECOMPRESS_DONE (1 << 13) +# define SAMPLER_CACHE_DONE (1 << 12) +# define FILTER_DONE (1 << 11) +# define BYPASS_FIFO_DONE (1 << 10) +# define PS_DONE (1 << 9) +# define CC_DONE (1 << 8) +# define MAP_FILTER_DONE (1 << 7) +# define MAP_L2_IDLE (1 << 6) +# define RING_2_ENABLE (1 << 2) +# define RING_1_ENABLE (1 << 1) +# define RING_0_ENABLE (1 << 0) + +#define SCPD0 0x209c /* debug */ +#define INST_PS 0x20c4 +#define IPEIR_I965 0x2064 /* i965 */ +#define IPEHR_I965 0x2068 /* i965 */ +#define INST_DONE_I965 0x206c +# define I965_SF_DONE (1 << 23) +# define I965_SE_DONE (1 << 22) +# define I965_WM_DONE (1 << 21) +# define I965_TEXTURE_FETCH_DONE (1 << 14) +# define I965_SAMPLER_CACHE_DONE (1 << 12) +# define I965_FILTER_DONE (1 << 11) +# define I965_PS_DONE (1 << 9) +# define I965_CC_DONE (1 << 8) +# define I965_MAP_FILTER_DONE (1 << 7) +# define I965_MAP_L2_IDLE (1 << 6) +# define I965_CP_DONE (1 << 1) +# define I965_RING_0_ENABLE (1 << 0) +#define INST_PS_I965 0x2070 + +/* Current active ring head address: + */ +#define ACTHD_I965 0x2074 +#define ACTHD 0x20C8 + +/* Current primary/secondary DMA fetch addresses: + */ +#define DMA_FADD_P 0x2078 +#define DMA_FADD_S 0x20d4 +#define INST_DONE_1 0x207c + +#define CACHE_MODE_0 0x2120 +#define CACHE_MODE_1 0x2124 +#define MI_MODE 0x209c +#define MI_DISPLAY_POWER_DOWN 0x20e0 +#define MI_ARB_STATE 0x20e4 +#define MI_RDRET_STATE 0x20fc + +/* Start addresses for each of the primary rings: + */ +#define PR0_STR 0x20f0 +#define PR1_STR 0x20f4 +#define PR2_STR 0x20f8 + +#define WIZ_CTL 0x7c00 +#define WIZ_CTL_SINGLE_SUBSPAN (1<<6) +#define WIZ_CTL_IGNORE_STALLS (1<<5) + +#define SVG_WORK_CTL 0x7408 + +#define TS_CTL 0x7e00 +#define TS_MUX_ERR_CODE (0<<8) +#define TS_MUX_URB_0 (1<<8) +#define TS_MUX_DISPATCH_ID_0 (10<<8) +#define TS_MUX_ERR_CODE_VALID (15<<8) +#define TS_MUX_TID_0 (16<<8) +#define TS_MUX_EUID_0 (18<<8) +#define TS_MUX_FFID_0 (22<<8) +#define TS_MUX_EOT (26<<8) +#define TS_MUX_SIDEBAND_0 (27<<8) +#define TS_SNAP_ALL_CHILD (1<<2) +#define TS_SNAP_ALL_ROOT (1<<1) +#define TS_SNAP_ENABLE (1<<0) + +#define TS_DEBUG_DATA 0x7e0c + +#define TD_CTL 0x8000 +#define TD_CTL2 0x8004 + + +#define ECOSKPD 0x21d0 +#define EXCC 0x2028 + +/* I965 debug regs: + */ +#define IA_VERTICES_COUNT_QW 0x2310 +#define IA_PRIMITIVES_COUNT_QW 0x2318 +#define VS_INVOCATION_COUNT_QW 0x2320 +#define GS_INVOCATION_COUNT_QW 0x2328 +#define GS_PRIMITIVES_COUNT_QW 0x2330 +#define CL_INVOCATION_COUNT_QW 0x2338 +#define CL_PRIMITIVES_COUNT_QW 0x2340 +#define PS_INVOCATION_COUNT_QW 0x2348 +#define PS_DEPTH_COUNT_QW 0x2350 +#define TIMESTAMP_QW 0x2358 +#define CLKCMP_QW 0x2360 + + + + + + +/* General error reporting regs, p296 + */ +#define EIR 0x20B0 +#define EMR 0x20B4 +#define ESR 0x20B8 +# define ERR_VERTEX_MAX (1 << 5) /* lpt/cst */ +# define ERR_PGTBL_ERROR (1 << 4) +# define ERR_DISPLAY_OVERLAY_UNDERRUN (1 << 3) +# define ERR_MAIN_MEMORY_REFRESH (1 << 1) +# define ERR_INSTRUCTION_ERROR (1 << 0) + + +/* Interrupt Control Registers + * - new bits for i810 + * - new register hwstam (mask) + */ +#define HWS_PGA 0x2080 +#define PWRCTXA 0x2088 /* 965GM+ only */ +#define PWRCTX_EN (1<<0) +#define HWSTAM 0x2098 /* p290 */ +#define IER 0x20a0 /* p291 */ +#define IIR 0x20a4 /* p292 */ +#define IMR 0x20a8 /* p293 */ +#define ISR 0x20ac /* p294 */ +#define HW_ERROR 0x8000 +#define SYNC_STATUS_TOGGLE 0x1000 +#define DPY_0_FLIP_PENDING 0x0800 +#define DPY_1_FLIP_PENDING 0x0400 /* not implemented on i810 */ +#define OVL_0_FLIP_PENDING 0x0200 +#define OVL_1_FLIP_PENDING 0x0100 /* not implemented on i810 */ +#define DPY_0_VBLANK 0x0080 +#define DPY_0_EVENT 0x0040 +#define DPY_1_VBLANK 0x0020 /* not implemented on i810 */ +#define DPY_1_EVENT 0x0010 /* not implemented on i810 */ +#define HOST_PORT_EVENT 0x0008 /* */ +#define CAPTURE_EVENT 0x0004 /* */ +#define USER_DEFINED 0x0002 +#define BREAKPOINT 0x0001 + + +#define INTR_RESERVED (0x6000 | \ + DPY_1_FLIP_PENDING | \ + OVL_1_FLIP_PENDING | \ + DPY_1_VBLANK | \ + DPY_1_EVENT | \ + HOST_PORT_EVENT | \ + CAPTURE_EVENT ) + +/* FIFO Watermark and Burst Length Control Register + * + * - different offset and contents on i810 (p299) (fewer bits per field) + * - some overlay fields added + * - what does it all mean? + */ +#define FWATER_BLC 0x20d8 +#define FWATER_BLC2 0x20dc +#define MM_BURST_LENGTH 0x00700000 +#define MM_FIFO_WATERMARK 0x0001F000 +#define LM_BURST_LENGTH 0x00000700 +#define LM_FIFO_WATERMARK 0x0000001F + + +/* Fence/Tiling ranges [0..7] + */ +#define FENCE 0x2000 +#define FENCE_NR 8 + +#define FENCE_NEW 0x3000 +#define FENCE_NEW_NR 16 + +#define FENCE_LINEAR 0 +#define FENCE_XMAJOR 1 +#define FENCE_YMAJOR 2 + +#define I915G_FENCE_START_MASK 0x0ff00000 + +#define I830_FENCE_START_MASK 0x07f80000 + +#define FENCE_START_MASK 0x03F80000 +#define FENCE_X_MAJOR 0x00000000 +#define FENCE_Y_MAJOR 0x00001000 +#define FENCE_SIZE_MASK 0x00000700 +#define FENCE_SIZE_512K 0x00000000 +#define FENCE_SIZE_1M 0x00000100 +#define FENCE_SIZE_2M 0x00000200 +#define FENCE_SIZE_4M 0x00000300 +#define FENCE_SIZE_8M 0x00000400 +#define FENCE_SIZE_16M 0x00000500 +#define FENCE_SIZE_32M 0x00000600 +#define FENCE_SIZE_64M 0x00000700 +#define I915G_FENCE_SIZE_1M 0x00000000 +#define I915G_FENCE_SIZE_2M 0x00000100 +#define I915G_FENCE_SIZE_4M 0x00000200 +#define I915G_FENCE_SIZE_8M 0x00000300 +#define I915G_FENCE_SIZE_16M 0x00000400 +#define I915G_FENCE_SIZE_32M 0x00000500 +#define I915G_FENCE_SIZE_64M 0x00000600 +#define I915G_FENCE_SIZE_128M 0x00000700 +#define I965_FENCE_X_MAJOR 0x00000000 +#define I965_FENCE_Y_MAJOR 0x00000002 +#define FENCE_PITCH_1 0x00000000 +#define FENCE_PITCH_2 0x00000010 +#define FENCE_PITCH_4 0x00000020 +#define FENCE_PITCH_8 0x00000030 +#define FENCE_PITCH_16 0x00000040 +#define FENCE_PITCH_32 0x00000050 +#define FENCE_PITCH_64 0x00000060 +#define FENCE_VALID 0x00000001 + + +/* Registers to control page table, p274 + */ +#define PGETBL_CTL 0x2020 +#define PGETBL_ADDR_MASK 0xFFFFF000 +#define PGETBL_ENABLE_MASK 0x00000001 +#define PGETBL_ENABLED 0x00000001 +/** Added in 965G, this field has the actual size of the global GTT */ +#define PGETBL_SIZE_MASK 0x0000000e +#define PGETBL_SIZE_512KB (0 << 1) +#define PGETBL_SIZE_256KB (1 << 1) +#define PGETBL_SIZE_128KB (2 << 1) +#define PGETBL_SIZE_1MB (3 << 1) +#define PGETBL_SIZE_2MB (4 << 1) +#define PGETBL_SIZE_1_5MB (5 << 1) +#define G33_PGETBL_SIZE_MASK (3 << 8) +#define G33_PGETBL_SIZE_1M (1 << 8) +#define G33_PGETBL_SIZE_2M (2 << 8) + +#define I830_PTE_BASE 0x10000 +#define PTE_ADDRESS_MASK 0xfffff000 +#define PTE_ADDRESS_MASK_HIGH 0x000000f0 /* i915+ */ +#define PTE_MAPPING_TYPE_UNCACHED (0 << 1) +#define PTE_MAPPING_TYPE_DCACHE (1 << 1) /* i830 only */ +#define PTE_MAPPING_TYPE_CACHED (3 << 1) +#define PTE_MAPPING_TYPE_MASK (3 << 1) +#define PTE_VALID (1 << 0) + +/** @defgroup PGE_ERR + * @{ + */ +/** Page table debug register for i845 */ +#define PGE_ERR 0x2024 +#define PGE_ERR_ADDR_MASK 0xFFFFF000 +#define PGE_ERR_ID_MASK 0x00000038 +#define PGE_ERR_CAPTURE 0x00000000 +#define PGE_ERR_OVERLAY 0x00000008 +#define PGE_ERR_DISPLAY 0x00000010 +#define PGE_ERR_HOST 0x00000018 +#define PGE_ERR_RENDER 0x00000020 +#define PGE_ERR_BLITTER 0x00000028 +#define PGE_ERR_MAPPING 0x00000030 +#define PGE_ERR_CMD_PARSER 0x00000038 +#define PGE_ERR_TYPE_MASK 0x00000007 +#define PGE_ERR_INV_TABLE 0x00000000 +#define PGE_ERR_INV_PTE 0x00000001 +#define PGE_ERR_MIXED_TYPES 0x00000002 +#define PGE_ERR_PAGE_MISS 0x00000003 +#define PGE_ERR_ILLEGAL_TRX 0x00000004 +#define PGE_ERR_LOCAL_MEM 0x00000005 +#define PGE_ERR_TILED 0x00000006 +/** @} */ + +/** @defgroup PGTBL_ER + * @{ + */ +/** Page table debug register for i945 */ +# define PGTBL_ER 0x2024 +# define PGTBL_ERR_MT_TILING (1 << 27) +# define PGTBL_ERR_MT_GTT_PTE (1 << 26) +# define PGTBL_ERR_LC_TILING (1 << 25) +# define PGTBL_ERR_LC_GTT_PTE (1 << 24) +# define PGTBL_ERR_BIN_VERTEXDATA_GTT_PTE (1 << 23) +# define PGTBL_ERR_BIN_INSTRUCTION_GTT_PTE (1 << 22) +# define PGTBL_ERR_CS_VERTEXDATA_GTT_PTE (1 << 21) +# define PGTBL_ERR_CS_INSTRUCTION_GTT_PTE (1 << 20) +# define PGTBL_ERR_CS_GTT (1 << 19) +# define PGTBL_ERR_OVERLAY_TILING (1 << 18) +# define PGTBL_ERR_OVERLAY_GTT_PTE (1 << 16) +# define PGTBL_ERR_DISPC_TILING (1 << 14) +# define PGTBL_ERR_DISPC_GTT_PTE (1 << 12) +# define PGTBL_ERR_DISPB_TILING (1 << 10) +# define PGTBL_ERR_DISPB_GTT_PTE (1 << 8) +# define PGTBL_ERR_DISPA_TILING (1 << 6) +# define PGTBL_ERR_DISPA_GTT_PTE (1 << 4) +# define PGTBL_ERR_HOST_PTE_DATA (1 << 1) +# define PGTBL_ERR_HOST_GTT_PTE (1 << 0) +/** @} */ + +/* Ring buffer registers, p277, overview p19 + */ +#define LP_RING 0x2030 +#define HP_RING 0x2040 + +#define RING_TAIL 0x00 +#define TAIL_ADDR 0x000FFFF8 +#define I830_TAIL_MASK 0x001FFFF8 + +#define RING_HEAD 0x04 +#define HEAD_WRAP_COUNT 0xFFE00000 +#define HEAD_WRAP_ONE 0x00200000 +#define HEAD_ADDR 0x001FFFFC +#define I830_HEAD_MASK 0x001FFFFC + +#define RING_START 0x08 +#define START_ADDR 0x03FFFFF8 +#define I830_RING_START_MASK 0xFFFFF000 + +#define RING_LEN 0x0C +#define RING_NR_PAGES 0x001FF000 +#define I830_RING_NR_PAGES 0x001FF000 +#define RING_REPORT_MASK 0x00000006 +#define RING_REPORT_64K 0x00000002 +#define RING_REPORT_128K 0x00000004 +#define RING_NO_REPORT 0x00000000 +#define RING_VALID_MASK 0x00000001 +#define RING_VALID 0x00000001 +#define RING_INVALID 0x00000000 + + + +/* BitBlt Instructions + * + * There are many more masks & ranges yet to add. + */ +#define BR00_BITBLT_CLIENT 0x40000000 +#define BR00_OP_COLOR_BLT 0x10000000 +#define BR00_OP_SRC_COPY_BLT 0x10C00000 +#define BR00_OP_FULL_BLT 0x11400000 +#define BR00_OP_MONO_SRC_BLT 0x11800000 +#define BR00_OP_MONO_SRC_COPY_BLT 0x11000000 +#define BR00_OP_MONO_PAT_BLT 0x11C00000 +#define BR00_OP_MONO_SRC_COPY_IMMEDIATE_BLT (0x61 << 22) +#define BR00_OP_TEXT_IMMEDIATE_BLT 0xc000000 + + +#define BR00_TPCY_DISABLE 0x00000000 +#define BR00_TPCY_ENABLE 0x00000010 + +#define BR00_TPCY_ROP 0x00000000 +#define BR00_TPCY_NO_ROP 0x00000020 +#define BR00_TPCY_EQ 0x00000000 +#define BR00_TPCY_NOT_EQ 0x00000040 + +#define BR00_PAT_MSB_FIRST 0x00000000 /* ? */ + +#define BR00_PAT_VERT_ALIGN 0x000000e0 + +#define BR00_LENGTH 0x0000000F + +#define BR09_DEST_ADDR 0x03FFFFFF + +#define BR11_SOURCE_PITCH 0x00003FFF + +#define BR12_SOURCE_ADDR 0x03FFFFFF + +#define BR13_SOLID_PATTERN 0x80000000 +#define BR13_RIGHT_TO_LEFT 0x40000000 +#define BR13_LEFT_TO_RIGHT 0x00000000 +#define BR13_MONO_TRANSPCY 0x20000000 +#define BR13_MONO_PATN_TRANS 0x10000000 +#define BR13_USE_DYN_DEPTH 0x04000000 +#define BR13_DYN_8BPP 0x00000000 +#define BR13_DYN_16BPP 0x01000000 +#define BR13_DYN_24BPP 0x02000000 +#define BR13_ROP_MASK 0x00FF0000 +#define BR13_DEST_PITCH 0x0000FFFF +#define BR13_PITCH_SIGN_BIT 0x00008000 + +#define BR14_DEST_HEIGHT 0xFFFF0000 +#define BR14_DEST_WIDTH 0x0000FFFF + +#define BR15_PATTERN_ADDR 0x03FFFFFF + +#define BR16_SOLID_PAT_COLOR 0x00FFFFFF +#define BR16_BACKGND_PAT_CLR 0x00FFFFFF + +#define BR17_FGND_PAT_CLR 0x00FFFFFF + +#define BR18_SRC_BGND_CLR 0x00FFFFFF +#define BR19_SRC_FGND_CLR 0x00FFFFFF + + +/* Instruction parser instructions + */ + +#define INST_PARSER_CLIENT 0x00000000 +#define INST_OP_FLUSH 0x02000000 +#define INST_FLUSH_MAP_CACHE 0x00000001 + + +#define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23)) + + +/* Registers in the i810 host-pci bridge pci config space which affect + * the i810 graphics operations. + */ +#define SMRAM_MISCC 0x70 +#define GMS 0x000000c0 +#define GMS_DISABLE 0x00000000 +#define GMS_ENABLE_BARE 0x00000040 +#define GMS_ENABLE_512K 0x00000080 +#define GMS_ENABLE_1M 0x000000c0 +#define USMM 0x00000030 +#define USMM_DISABLE 0x00000000 +#define USMM_TSEG_ZERO 0x00000010 +#define USMM_TSEG_512K 0x00000020 +#define USMM_TSEG_1M 0x00000030 +#define GFX_MEM_WIN_SIZE 0x00010000 +#define GFX_MEM_WIN_32M 0x00010000 +#define GFX_MEM_WIN_64M 0x00000000 + +/* Overkill? I don't know. Need to figure out top of mem to make the + * SMRAM calculations come out. Linux seems to have problems + * detecting it all on its own, so this seems a reasonable double + * check to any user supplied 'mem=...' boot param. + * + * ... unfortunately this reg doesn't work according to spec on the + * test hardware. + */ +#define WHTCFG_PAMR_DRP 0x50 +#define SYS_DRAM_ROW_0_SHIFT 16 +#define SYS_DRAM_ROW_1_SHIFT 20 +#define DRAM_MASK 0x0f +#define DRAM_VALUE_0 0 +#define DRAM_VALUE_1 8 +/* No 2 value defined */ +#define DRAM_VALUE_3 16 +#define DRAM_VALUE_4 16 +#define DRAM_VALUE_5 24 +#define DRAM_VALUE_6 32 +#define DRAM_VALUE_7 32 +#define DRAM_VALUE_8 48 +#define DRAM_VALUE_9 64 +#define DRAM_VALUE_A 64 +#define DRAM_VALUE_B 96 +#define DRAM_VALUE_C 128 +#define DRAM_VALUE_D 128 +#define DRAM_VALUE_E 192 +#define DRAM_VALUE_F 256 /* nice one, geezer */ +#define LM_FREQ_MASK 0x10 +#define LM_FREQ_133 0x10 +#define LM_FREQ_100 0x00 + + + + +/* These are 3d state registers, but the state is invarient, so we let + * the X server handle it: + */ + + + +/* GFXRENDERSTATE_COLOR_CHROMA_KEY, p135 + */ +#define GFX_OP_COLOR_CHROMA_KEY ((0x3<<29)|(0x1d<<24)|(0x2<<16)|0x1) +#define CC1_UPDATE_KILL_WRITE (1<<28) +#define CC1_ENABLE_KILL_WRITE (1<<27) +#define CC1_DISABLE_KILL_WRITE 0 +#define CC1_UPDATE_COLOR_IDX (1<<26) +#define CC1_UPDATE_CHROMA_LOW (1<<25) +#define CC1_UPDATE_CHROMA_HI (1<<24) +#define CC1_CHROMA_LOW_MASK ((1<<24)-1) +#define CC2_COLOR_IDX_SHIFT 24 +#define CC2_COLOR_IDX_MASK (0xff<<24) +#define CC2_CHROMA_HI_MASK ((1<<24)-1) + + +#define GFX_CMD_CONTEXT_SEL ((0<<29)|(0x5<<23)) +#define CS_UPDATE_LOAD (1<<17) +#define CS_UPDATE_USE (1<<16) +#define CS_UPDATE_LOAD (1<<17) +#define CS_LOAD_CTX0 0 +#define CS_LOAD_CTX1 (1<<8) +#define CS_USE_CTX0 0 +#define CS_USE_CTX1 (1<<0) + +/* I810 LCD/TV registers */ +#define LCD_TV_HTOTAL 0x60000 +#define LCD_TV_C 0x60018 +#define LCD_TV_OVRACT 0x6001C + +#define LCD_TV_ENABLE (1 << 31) +#define LCD_TV_VGAMOD (1 << 28) + +/* I830 CRTC registers */ +#define HTOTAL_A 0x60000 +#define HBLANK_A 0x60004 +#define HSYNC_A 0x60008 +#define VTOTAL_A 0x6000c +#define VBLANK_A 0x60010 +#define VSYNC_A 0x60014 +#define PIPEASRC 0x6001c +#define BCLRPAT_A 0x60020 +#define VSYNCSHIFT_A 0x60028 + +#define HTOTAL_B 0x61000 +#define HBLANK_B 0x61004 +#define HSYNC_B 0x61008 +#define VTOTAL_B 0x6100c +#define VBLANK_B 0x61010 +#define VSYNC_B 0x61014 +#define PIPEBSRC 0x6101c +#define BCLRPAT_B 0x61020 +#define VSYNCSHIFT_B 0x61028 + +#define PP_STATUS 0x61200 +# define PP_ON (1 << 31) +/** + * Indicates that all dependencies of the panel are on: + * + * - PLL enabled + * - pipe enabled + * - LVDS/DVOB/DVOC on + */ +# define PP_READY (1 << 30) +# define PP_SEQUENCE_NONE (0 << 28) +# define PP_SEQUENCE_ON (1 << 28) +# define PP_SEQUENCE_OFF (2 << 28) +# define PP_SEQUENCE_MASK 0x30000000 + +#define PP_CONTROL 0x61204 +# define POWER_DOWN_ON_RESET (1 << 1) +# define POWER_TARGET_ON (1 << 0) + +#define PP_ON_DELAYS 0x61208 +#define PP_OFF_DELAYS 0x6120c +#define PP_DIVISOR 0x61210 + +#define PFIT_CONTROL 0x61230 +# define PFIT_ENABLE (1 << 31) +/* Pre-965 */ +# define VERT_INTERP_DISABLE (0 << 10) +# define VERT_INTERP_BILINEAR (1 << 10) +# define VERT_INTERP_MASK (3 << 10) +# define VERT_AUTO_SCALE (1 << 9) +# define HORIZ_INTERP_DISABLE (0 << 6) +# define HORIZ_INTERP_BILINEAR (1 << 6) +# define HORIZ_INTERP_MASK (3 << 6) +# define HORIZ_AUTO_SCALE (1 << 5) +# define PANEL_8TO6_DITHER_ENABLE (1 << 3) +/* 965+ */ +# define PFIT_PIPE_MASK (3 << 29) +# define PFIT_PIPE_SHIFT 29 +# define PFIT_SCALING_MODE_MASK (7 << 26) +# define PFIT_SCALING_AUTO (0 << 26) +# define PFIT_SCALING_PROGRAMMED (1 << 26) +# define PFIT_SCALING_PILLAR (2 << 26) +# define PFIT_SCALING_LETTER (3 << 26) +# define PFIT_FILTER_SELECT_MASK (3 << 24) +# define PFIT_FILTER_FUZZY (0 << 24) +# define PFIT_FILTER_CRISP (1 << 24) +# define PFIT_FILTER_MEDIAN (2 << 24) + +#define PFIT_PGM_RATIOS 0x61234 +/* Pre-965 */ +# define PFIT_VERT_SCALE_SHIFT 20 +# define PFIT_VERT_SCALE_MASK 0xfff00000 +# define PFIT_HORIZ_SCALE_SHIFT 4 +# define PFIT_HORIZ_SCALE_MASK 0x0000fff0 +/* 965+ */ +# define PFIT_VERT_SCALE_SHIFT_965 16 +# define PFIT_VERT_SCALE_MASK_965 0x1fff0000 +# define PFIT_HORIZ_SCALE_SHIFT_965 0 +# define PFIT_HORIZ_SCALE_MASK_965 0x00001fff + +#define DPLL_A 0x06014 +#define DPLL_B 0x06018 +# define DPLL_VCO_ENABLE (1 << 31) +# define DPLL_DVO_HIGH_SPEED (1 << 30) +# define DPLL_SYNCLOCK_ENABLE (1 << 29) +# define DPLL_VGA_MODE_DIS (1 << 28) +# define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ +# define DPLLB_MODE_LVDS (2 << 26) /* i915 */ +# define DPLL_MODE_MASK (3 << 26) +# define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ +# define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ +# define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ +# define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ +# define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ +# define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ +# define DPLL_FPA01_P1_POST_DIV_MASK_IGD 0x00ff8000 /* IGD */ +/** + * The i830 generation, in DAC/serial mode, defines p1 as two plus this + * bitfield, or just 2 if PLL_P1_DIVIDE_BY_TWO is set. + */ +# define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 +/** + * The i830 generation, in LVDS mode, defines P1 as the bit number set within + * this field (only one bit may be set). + */ +# define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 +# define DPLL_FPA01_P1_POST_DIV_SHIFT 16 +# define DPLL_FPA01_P1_POST_DIV_SHIFT_IGD 15 +/* IGDNG */ +# define DPLL_FPA0_P1_POST_DIV_SHIFT 16 + +# define PLL_P2_DIVIDE_BY_4 (1 << 23) /* i830, required in DVO non-gang */ +# define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ +# define PLL_REF_INPUT_DREFCLK (0 << 13) +# define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ +# define PLL_REF_INPUT_SUPER_SSC (1 << 13) /* IGDNG: 120M SSC */ +# define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ +# define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) +# define PLL_REF_INPUT_MASK (3 << 13) +# define PLL_REF_INPUT_DMICLK (5 << 13) /* IGDNG: DMI refclk */ +# define PLL_LOAD_PULSE_PHASE_SHIFT 9 +/* + * Parallel to Serial Load Pulse phase selection. + * Selects the phase for the 10X DPLL clock for the PCIe + * digital display port. The range is 4 to 13; 10 or more + * is just a flip delay. The default is 6 + */ +# define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) +# define DISPLAY_RATE_SELECT_FPA1 (1 << 8) +/* IGDNG */ +# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 +# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) +# define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1)<< PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) +# define DPLL_FPA1_P1_POST_DIV_SHIFT 0 +# define DPLL_FPA1_P1_POST_DIV_MASK 0xff + +/** + * SDVO multiplier for 945G/GM. Not used on 965. + * + * \sa DPLL_MD_UDI_MULTIPLIER_MASK + */ +# define SDVO_MULTIPLIER_MASK 0x000000ff +# define SDVO_MULTIPLIER_SHIFT_HIRES 4 +# define SDVO_MULTIPLIER_SHIFT_VGA 0 + +/** @defgroup DPLL_MD + * @{ + */ +/** Pipe A SDVO/UDI clock multiplier/divider register for G965. */ +#define DPLL_A_MD 0x0601c +/** Pipe B SDVO/UDI clock multiplier/divider register for G965. */ +#define DPLL_B_MD 0x06020 +/** + * UDI pixel divider, controlling how many pixels are stuffed into a packet. + * + * Value is pixels minus 1. Must be set to 1 pixel for SDVO. + */ +# define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 +# define DPLL_MD_UDI_DIVIDER_SHIFT 24 +/** UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ +# define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 +# define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 +/** + * SDVO/UDI pixel multiplier. + * + * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus + * clock rate is 10 times the DPLL clock. At low resolution/refresh rate + * modes, the bus rate would be below the limits, so SDVO allows for stuffing + * dummy bytes in the datastream at an increased clock rate, with both sides of + * the link knowing how many bytes are fill. + * + * So, for a mode with a dotclock of 65Mhz, we would want to double the clock + * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be + * set to 130Mhz, and the SDVO multiplier set to 2x in this register and + * through an SDVO command. + * + * This register field has values of multiplication factor minus 1, with + * a maximum multiplier of 5 for SDVO. + */ +# define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 +# define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 +/** SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. + * This best be set to the default value (3) or the CRT won't work. No, + * I don't entirely understand what this does... + */ +# define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f +# define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 +/** @} */ + +#define DPLL_TEST 0x606c +# define DPLLB_TEST_SDVO_DIV_1 (0 << 22) +# define DPLLB_TEST_SDVO_DIV_2 (1 << 22) +# define DPLLB_TEST_SDVO_DIV_4 (2 << 22) +# define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) +# define DPLLB_TEST_N_BYPASS (1 << 19) +# define DPLLB_TEST_M_BYPASS (1 << 18) +# define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) +# define DPLLA_TEST_N_BYPASS (1 << 3) +# define DPLLA_TEST_M_BYPASS (1 << 2) +# define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) + +#define D_STATE 0x6104 +#define DSPCLK_GATE_D 0x6200 +# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ +# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ +# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ +# define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ +# define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ +# define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ +# define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ +# define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ +# define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ +# define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ +# define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ +# define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ +# define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ +# define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ +# define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ +# define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ +# define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ +# define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ +# define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ +# define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) +# define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) +# define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) +# define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) +# define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ +# define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ +# define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ +# define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) +# define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) +/** + * This bit must be set on the 830 to prevent hangs when turning off the + * overlay scaler. + */ +# define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) +# define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) +# define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) +# define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ +# define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ + +#define RENCLK_GATE_D1 0x6204 +# define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ +# define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ +# define PC_FE_CLOCK_GATE_DISABLE (1 << 11) +# define PC_BE_CLOCK_GATE_DISABLE (1 << 10) +# define WINDOWER_CLOCK_GATE_DISABLE (1 << 9) +# define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) +# define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) +# define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) +# define MAG_CLOCK_GATE_DISABLE (1 << 5) +/** This bit must be unset on 855,865 */ +# define MECI_CLOCK_GATE_DISABLE (1 << 4) +# define DCMP_CLOCK_GATE_DISABLE (1 << 3) +# define MEC_CLOCK_GATE_DISABLE (1 << 2) +# define MECO_CLOCK_GATE_DISABLE (1 << 1) +/** This bit must be set on 855,865. */ +# define SV_CLOCK_GATE_DISABLE (1 << 0) +# define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) +# define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) +# define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) +# define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) +# define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) +# define I915_WM_CLOCK_GATE_DISABLE (1 << 11) +# define I915_IZ_CLOCK_GATE_DISABLE (1 << 10) +# define I915_PI_CLOCK_GATE_DISABLE (1 << 9) +# define I915_DI_CLOCK_GATE_DISABLE (1 << 8) +# define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) +# define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) +# define I915_SC_CLOCK_GATE_DISABLE (1 << 5) +# define I915_FL_CLOCK_GATE_DISABLE (1 << 4) +# define I915_DM_CLOCK_GATE_DISABLE (1 << 3) +# define I915_PS_CLOCK_GATE_DISABLE (1 << 2) +# define I915_CC_CLOCK_GATE_DISABLE (1 << 1) +# define I915_BY_CLOCK_GATE_DISABLE (1 << 0) + +# define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) +/** This bit must always be set on 965G/965GM */ +# define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) +# define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) +# define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) +# define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) +# define I965_GW_CLOCK_GATE_DISABLE (1 << 25) +# define I965_TD_CLOCK_GATE_DISABLE (1 << 24) +/** This bit must always be set on 965G */ +# define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) +# define I965_IC_CLOCK_GATE_DISABLE (1 << 22) +# define I965_EU_CLOCK_GATE_DISABLE (1 << 21) +# define I965_IF_CLOCK_GATE_DISABLE (1 << 20) +# define I965_TC_CLOCK_GATE_DISABLE (1 << 19) +# define I965_SO_CLOCK_GATE_DISABLE (1 << 17) +# define I965_FBC_CLOCK_GATE_DISABLE (1 << 16) +# define I965_MARI_CLOCK_GATE_DISABLE (1 << 15) +# define I965_MASF_CLOCK_GATE_DISABLE (1 << 14) +# define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) +# define I965_EM_CLOCK_GATE_DISABLE (1 << 12) +# define I965_UC_CLOCK_GATE_DISABLE (1 << 11) +# define I965_SI_CLOCK_GATE_DISABLE (1 << 6) +# define I965_MT_CLOCK_GATE_DISABLE (1 << 5) +# define I965_PL_CLOCK_GATE_DISABLE (1 << 4) +# define I965_DG_CLOCK_GATE_DISABLE (1 << 3) +# define I965_QC_CLOCK_GATE_DISABLE (1 << 2) +# define I965_FT_CLOCK_GATE_DISABLE (1 << 1) +# define I965_DM_CLOCK_GATE_DISABLE (1 << 0) + +#define RENCLK_GATE_D2 0x6208 +#define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) +#define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) +#define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) +#define RAMCLK_GATE_D 0x6210 /* CRL only */ +#define DEUC 0x6214 /* CRL only */ + +/* + * This is a PCI config space register to manipulate backlight brightness + * It is used when the BLM_LEGACY_MODE is turned on. When enabled, the first + * byte of this config register sets brightness within the range from + * 0 to 0xff + */ +#define LEGACY_BACKLIGHT_BRIGHTNESS 0xf4 + +#define BLC_PWM_CTL 0x61254 +#define BACKLIGHT_MODULATION_FREQ_SHIFT (17) +#define BACKLIGHT_MODULATION_FREQ_SHIFT2 (16) +/** + * This is the most significant 15 bits of the number of backlight cycles in a + * complete cycle of the modulated backlight control. + * + * The actual value is this field multiplied by two. + */ +#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) +#define BACKLIGHT_MODULATION_FREQ_MASK2 (0xffff << 16) +#define BLM_LEGACY_MODE (1 << 16) + +/** + * This is the number of cycles out of the backlight modulation cycle for which + * the backlight is on. + * + * This field must be no greater than the number of cycles in the complete + * backlight modulation cycle. + */ +#define BACKLIGHT_DUTY_CYCLE_SHIFT (0) +#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) + +/* On 965+ backlight control is in another register */ +#define BLC_PWM_CTL2 0x61250 +#define BLM_LEGACY_MODE2 (1 << 30) + +#define BLM_CTL 0x61260 +#define BLM_THRESHOLD_0 0x61270 +#define BLM_THRESHOLD_1 0x61274 +#define BLM_THRESHOLD_2 0x61278 +#define BLM_THRESHOLD_3 0x6127c +#define BLM_THRESHOLD_4 0x61280 +#define BLM_THRESHOLD_5 0x61284 + +#define BLM_ACCUMULATOR_0 0x61290 +#define BLM_ACCUMULATOR_1 0x61294 +#define BLM_ACCUMULATOR_2 0x61298 +#define BLM_ACCUMULATOR_3 0x6129c +#define BLM_ACCUMULATOR_4 0x612a0 +#define BLM_ACCUMULATOR_5 0x612a4 + +#define FPA0 0x06040 +#define FPA1 0x06044 +#define FPB0 0x06048 +#define FPB1 0x0604c +# define FP_N_DIV_MASK 0x003f0000 +# define FP_N_IGD_DIV_MASK 0x00ff0000 +# define FP_N_DIV_SHIFT 16 +# define FP_M1_DIV_MASK 0x00003f00 +# define FP_M1_DIV_SHIFT 8 +# define FP_M2_DIV_MASK 0x0000003f +# define FP_M2_IGD_DIV_MASK 0x000000ff +# define FP_M2_DIV_SHIFT 0 + +#define PORT_HOTPLUG_EN 0x61110 +# define HDMIB_HOTPLUG_INT_EN (1 << 29) +# define HDMIC_HOTPLUG_INT_EN (1 << 28) +# define HDMID_HOTPLUG_INT_EN (1 << 27) +# define SDVOB_HOTPLUG_INT_EN (1 << 26) +# define SDVOC_HOTPLUG_INT_EN (1 << 25) +# define TV_HOTPLUG_INT_EN (1 << 18) +# define CRT_HOTPLUG_INT_EN (1 << 9) +# define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) +/* must use period 64 on GM45 according to docs */ +# define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) +# define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) +# define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) +# define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) +# define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) +# define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) +# define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) +# define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) +# define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) +# define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) +# define CRT_HOTPLUG_FORCE_DETECT (1 << 3) +# define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) +# define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) +# define CRT_HOTPLUG_MASK (0x3fc) /* Bits 9-2 */ +# define CRT_FORCE_HOTPLUG_MASK 0xfffffe1f + +#define PORT_HOTPLUG_STAT 0x61114 +# define HDMIB_HOTPLUG_INT_STATUS (1 << 29) +# define HDMIC_HOTPLUG_INT_STATUS (1 << 28) +# define HDMID_HOTPLUG_INT_STATUS (1 << 27) +# define CRT_HOTPLUG_INT_STATUS (1 << 11) +# define TV_HOTPLUG_INT_STATUS (1 << 10) +# define CRT_HOTPLUG_MONITOR_MASK (3 << 8) +# define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) +# define CRT_HOTPLUG_MONITOR_MONO (2 << 8) +# define CRT_HOTPLUG_MONITOR_NONE (0 << 8) +# define SDVOC_HOTPLUG_INT_STATUS (1 << 7) +# define SDVOB_HOTPLUG_INT_STATUS (1 << 6) + +#define SDVOB 0x61140 +#define SDVOC 0x61160 +#define SDVO_ENABLE (1 << 31) +#define SDVO_PIPE_B_SELECT (1 << 30) +#define SDVO_STALL_SELECT (1 << 29) +#define SDVO_INTERRUPT_ENABLE (1 << 26) +/** + * 915G/GM SDVO pixel multiplier. + * + * Programmed value is multiplier - 1, up to 5x. + * + * \sa DPLL_MD_UDI_MULTIPLIER_MASK + */ +#define SDVO_PORT_MULTIPLY_MASK (7 << 23) +#define SDVO_PORT_MULTIPLY_SHIFT 23 +#define SDVO_PHASE_SELECT_MASK (15 << 19) +#define SDVO_PHASE_SELECT_DEFAULT (6 << 19) +#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) +#define SDVOC_GANG_MODE (1 << 16) +#define SDVO_ENCODING_SDVO (0x0 << 10) +#define SDVO_ENCODING_HDMI (0x2 << 10) +/** Requird for HDMI operation */ +#define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9) +#define SDVO_COLOR_NOT_FULL_RANGE (1 << 8) +#define SDVO_BORDER_ENABLE (1 << 7) +#define SDVO_AUDIO_ENABLE (1 << 6) +/** New with 965, default is to be set */ +#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) +/** New with 965, default is to be set */ +#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) +/** 915/945 only, read-only bit */ +#define SDVOB_PCIE_CONCURRENCY (1 << 3) +#define SDVO_DETECTED (1 << 2) +/* Bits to be preserved when writing */ +#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14)) +#define SDVOC_PRESERVE_MASK (1 << 17) + +#define UDIB_SVB_SHB_CODES 0x61144 +#define UDIB_SHA_BLANK_CODES 0x61148 +#define UDIB_START_END_FILL_CODES 0x6114c + + +#define SDVOUDI 0x61150 + +#define I830_HTOTAL_MASK 0xfff0000 +#define I830_HACTIVE_MASK 0x7ff + +#define I830_HBLANKEND_MASK 0xfff0000 +#define I830_HBLANKSTART_MASK 0xfff + +#define I830_HSYNCEND_MASK 0xfff0000 +#define I830_HSYNCSTART_MASK 0xfff + +#define I830_VTOTAL_MASK 0xfff0000 +#define I830_VACTIVE_MASK 0x7ff + +#define I830_VBLANKEND_MASK 0xfff0000 +#define I830_VBLANKSTART_MASK 0xfff + +#define I830_VSYNCEND_MASK 0xfff0000 +#define I830_VSYNCSTART_MASK 0xfff + +#define I830_PIPEA_HORZ_MASK 0x7ff0000 +#define I830_PIPEA_VERT_MASK 0x7ff + +#define ADPA 0x61100 +#define ADPA_DAC_ENABLE (1<<31) +#define ADPA_DAC_DISABLE 0 +#define ADPA_PIPE_SELECT_MASK (1<<30) +#define ADPA_PIPE_A_SELECT 0 +#define ADPA_PIPE_B_SELECT (1<<30) +#define ADPA_USE_VGA_HVPOLARITY (1<<15) +#define ADPA_SETS_HVPOLARITY 0 +#define ADPA_VSYNC_CNTL_DISABLE (1<<11) +#define ADPA_VSYNC_CNTL_ENABLE 0 +#define ADPA_HSYNC_CNTL_DISABLE (1<<10) +#define ADPA_HSYNC_CNTL_ENABLE 0 +#define ADPA_VSYNC_ACTIVE_HIGH (1<<4) +#define ADPA_VSYNC_ACTIVE_LOW 0 +#define ADPA_HSYNC_ACTIVE_HIGH (1<<3) +#define ADPA_HSYNC_ACTIVE_LOW 0 + + +#define DVOA 0x61120 +#define DVOB 0x61140 +#define DVOC 0x61160 +#define DVO_ENABLE (1 << 31) +#define DVO_PIPE_B_SELECT (1 << 30) +#define DVO_PIPE_STALL_UNUSED (0 << 28) +#define DVO_PIPE_STALL (1 << 28) +#define DVO_PIPE_STALL_TV (2 << 28) +#define DVO_PIPE_STALL_MASK (3 << 28) +#define DVO_USE_VGA_SYNC (1 << 15) +#define DVO_DATA_ORDER_I740 (0 << 14) +#define DVO_DATA_ORDER_FP (1 << 14) +#define DVO_VSYNC_DISABLE (1 << 11) +#define DVO_HSYNC_DISABLE (1 << 10) +#define DVO_VSYNC_TRISTATE (1 << 9) +#define DVO_HSYNC_TRISTATE (1 << 8) +#define DVO_BORDER_ENABLE (1 << 7) +#define DVO_DATA_ORDER_GBRG (1 << 6) +#define DVO_DATA_ORDER_RGGB (0 << 6) +#define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) +#define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) +#define DVO_VSYNC_ACTIVE_HIGH (1 << 4) +#define DVO_HSYNC_ACTIVE_HIGH (1 << 3) +#define DVO_BLANK_ACTIVE_HIGH (1 << 2) +#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ +#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ +#define DVO_PRESERVE_MASK (0x7<<24) + +#define DVOA_SRCDIM 0x61124 +#define DVOB_SRCDIM 0x61144 +#define DVOC_SRCDIM 0x61164 +#define DVO_SRCDIM_HORIZONTAL_SHIFT 12 +#define DVO_SRCDIM_VERTICAL_SHIFT 0 + +/** @defgroup LVDS + * @{ + */ +/** + * This register controls the LVDS output enable, pipe selection, and data + * format selection. + * + * All of the clock/data pairs are force powered down by power sequencing. + */ +#define LVDS 0x61180 +/** + * Enables the LVDS port. This bit must be set before DPLLs are enabled, as + * the DPLL semantics change when the LVDS is assigned to that pipe. + */ +# define LVDS_PORT_EN (1 << 31) +/** Selects pipe B for LVDS data. Must be set on pre-965. */ +# define LVDS_PIPEB_SELECT (1 << 30) + +/* on 965, dithering is enabled in this register, not PFIT_CONTROL */ +# define LVDS_DITHER_ENABLE (1 << 25) + +/* + * Selects between .0 and .1 formats: + * + * 0 = 1x18.0, 2x18.0, 1x24.0 or 2x24.0 + * 1 = 1x24.1 or 2x24.1 + */ +# define LVDS_DATA_FORMAT_DOT_ONE (1 << 24) + +/* Using LE instead of HS on second channel control signal */ +# define LVDS_LE_CONTROL_ENABLE (1 << 23) + +/* Using LF instead of VS on second channel control signal */ +# define LVDS_LF_CONTROL_ENABLE (1 << 22) + +/* invert vsync signal polarity */ +# define LVDS_VSYNC_POLARITY_INVERT (1 << 21) + +/* invert hsync signal polarity */ +# define LVDS_HSYNC_POLARITY_INVERT (1 << 20) + +/* invert display enable signal polarity */ +# define LVDS_DE_POLARITY_INVERT (1 << 19) + +/* + * Control signals for second channel, ignored in single channel modes + */ + +/* send DE, HS, VS on second channel */ +# define LVDS_SECOND_CHANNEL_DE_HS_VS (0 << 17) + +# define LVDS_SECOND_CHANNEL_RESERVED (1 << 17) + +/* Send zeros instead of DE, HS, VS on second channel */ +# define LVDS_SECOND_CHANNEL_ZEROS (2 << 17) + +/* Set DE=0, HS=LE, VS=LF on second channel */ +# define LVDS_SECOND_CHANNEL_HS_VS (3 << 17) + +/* + * Send duplicate data for channel reserved bits, otherwise send zeros + */ +# define LVDS_CHANNEL_DUP_RESERVED (1 << 16) + +/* + * Enable border for unscaled (or aspect-scaled) display + */ +# define LVDS_BORDER_ENABLE (1 << 15) + +/* + * Tri-state the LVDS buffers when powered down, otherwise + * they are set to 0V + */ +# define LVDS_POWER_DOWN_TRI_STATE (1 << 10) + +/** + * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per + * pixel. + */ +# define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) +# define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) +# define LVDS_A0A2_CLKA_POWER_UP (3 << 8) +/** + * Controls the A3 data pair, which contains the additional LSBs for 24 bit + * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be + * on. + */ +# define LVDS_A3_POWER_MASK (3 << 6) +# define LVDS_A3_POWER_DOWN (0 << 6) +# define LVDS_A3_POWER_UP (3 << 6) +/** + * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP + * is set. + */ +# define LVDS_CLKB_POWER_MASK (3 << 4) +# define LVDS_CLKB_POWER_DOWN (0 << 4) +# define LVDS_CLKB_POWER_UP (3 << 4) + +/** + * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 + * setting for whether we are in dual-channel mode. The B3 pair will + * additionally only be powered up when LVDS_A3_POWER_UP is set. + */ +# define LVDS_B0B3_POWER_MASK (3 << 2) +# define LVDS_B0B3_POWER_DOWN (0 << 2) +# define LVDS_B0B3_POWER_UP (3 << 2) + +/** @} */ + +#define DP_B 0x64100 +#define DPB_AUX_CH_CTL 0x64110 +#define DPB_AUX_CH_DATA1 0x64114 +#define DPB_AUX_CH_DATA2 0x64118 +#define DPB_AUX_CH_DATA3 0x6411c +#define DPB_AUX_CH_DATA4 0x64120 +#define DPB_AUX_CH_DATA5 0x64124 + +#define DP_C 0x64200 +#define DPC_AUX_CH_CTL 0x64210 +#define DPC_AUX_CH_DATA1 0x64214 +#define DPC_AUX_CH_DATA2 0x64218 +#define DPC_AUX_CH_DATA3 0x6421c +#define DPC_AUX_CH_DATA4 0x64220 +#define DPC_AUX_CH_DATA5 0x64224 + +#define DP_D 0x64300 +#define DPD_AUX_CH_CTL 0x64310 +#define DPD_AUX_CH_DATA1 0x64314 +#define DPD_AUX_CH_DATA2 0x64318 +#define DPD_AUX_CH_DATA3 0x6431c +#define DPD_AUX_CH_DATA4 0x64320 +#define DPD_AUX_CH_DATA5 0x64324 + +/* + * Two channel clock control. Turn this on if you need clkb for two channel mode + * Overridden by global LVDS power sequencing + */ + +/* clkb off */ +# define LVDS_CLKB_POWER_DOWN (0 << 4) + +/* powered up, but clkb forced to 0 */ +# define LVDS_CLKB_POWER_PARTIAL (1 << 4) + +/* clock B running */ +# define LVDS_CLKB_POWER_UP (3 << 4) + +/* + * Two channel mode B0-B2 control. Sets state when power is on. + * Set to POWER_DOWN in single channel mode, other settings enable + * two channel mode. The CLKB power control controls whether that clock + * is enabled during two channel mode. + * + */ +/* Everything is off, including B3 and CLKB */ +# define LVDS_B_POWER_DOWN (0 << 2) + +/* B0, B1, B2 and data lines forced to 0. timing is active */ +# define LVDS_B_POWER_PARTIAL (1 << 2) + +/* data lines active (both timing and colour) */ +# define LVDS_B_POWER_UP (3 << 2) + +/** @defgroup TV_CTL + * @{ + */ +#define TV_CTL 0x68000 +/** Enables the TV encoder */ +# define TV_ENC_ENABLE (1 << 31) +/** Sources the TV encoder input from pipe B instead of A. */ +# define TV_ENC_PIPEB_SELECT (1 << 30) +/** Outputs composite video (DAC A only) */ +# define TV_ENC_OUTPUT_COMPOSITE (0 << 28) +/** Outputs SVideo video (DAC B/C) */ +# define TV_ENC_OUTPUT_SVIDEO (1 << 28) +/** Outputs Component video (DAC A/B/C) */ +# define TV_ENC_OUTPUT_COMPONENT (2 << 28) +/** Outputs Composite and SVideo (DAC A/B/C) */ +# define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) +# define TV_TRILEVEL_SYNC (1 << 21) +/** Enables slow sync generation (945GM only) */ +# define TV_SLOW_SYNC (1 << 20) +/** Selects 4x oversampling for 480i and 576p */ +# define TV_OVERSAMPLE_4X (0 << 18) +/** Selects 2x oversampling for 720p and 1080i */ +# define TV_OVERSAMPLE_2X (1 << 18) +/** Selects no oversampling for 1080p */ +# define TV_OVERSAMPLE_NONE (2 << 18) +/** Selects 8x oversampling */ +# define TV_OVERSAMPLE_8X (3 << 18) +/** Selects progressive mode rather than interlaced */ +# define TV_PROGRESSIVE (1 << 17) +/** Sets the colorburst to PAL mode. Required for non-M PAL modes. */ +# define TV_PAL_BURST (1 << 16) +/** Field for setting delay of Y compared to C */ +# define TV_YC_SKEW_MASK (7 << 12) +/** Enables a fix for 480p/576p standard definition modes on the 915GM only */ +# define TV_ENC_SDP_FIX (1 << 11) +/** + * Enables a fix for the 915GM only. + * + * Not sure what it does. + */ +# define TV_ENC_C0_FIX (1 << 10) +/** Bits that must be preserved by software */ +# define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf) +# define TV_FUSE_STATE_MASK (3 << 4) +/** Read-only state that reports all features enabled */ +# define TV_FUSE_STATE_ENABLED (0 << 4) +/** Read-only state that reports that Macrovision is disabled in hardware*/ +# define TV_FUSE_STATE_NO_MACROVISION (1 << 4) +/** Read-only state that reports that TV-out is disabled in hardware. */ +# define TV_FUSE_STATE_DISABLED (2 << 4) +/** Normal operation */ +# define TV_TEST_MODE_NORMAL (0 << 0) +/** Encoder test pattern 1 - combo pattern */ +# define TV_TEST_MODE_PATTERN_1 (1 << 0) +/** Encoder test pattern 2 - full screen vertical 75% color bars */ +# define TV_TEST_MODE_PATTERN_2 (2 << 0) +/** Encoder test pattern 3 - full screen horizontal 75% color bars */ +# define TV_TEST_MODE_PATTERN_3 (3 << 0) +/** Encoder test pattern 4 - random noise */ +# define TV_TEST_MODE_PATTERN_4 (4 << 0) +/** Encoder test pattern 5 - linear color ramps */ +# define TV_TEST_MODE_PATTERN_5 (5 << 0) +/** + * This test mode forces the DACs to 50% of full output. + * + * This is used for load detection in combination with TVDAC_SENSE_MASK + */ +# define TV_TEST_MODE_MONITOR_DETECT (7 << 0) +# define TV_TEST_MODE_MASK (7 << 0) +/** @} */ + +/** @defgroup TV_DAC + * @{ + */ +#define TV_DAC 0x68004 +/** + * Reports that DAC state change logic has reported change (RO). + * + * This gets cleared when TV_DAC_STATE_EN is cleared +*/ +# define TVDAC_STATE_CHG (1 << 31) +# define TVDAC_SENSE_MASK (7 << 28) +/** Reports that DAC A voltage is above the detect threshold */ +# define TVDAC_A_SENSE (1 << 30) +/** Reports that DAC B voltage is above the detect threshold */ +# define TVDAC_B_SENSE (1 << 29) +/** Reports that DAC C voltage is above the detect threshold */ +# define TVDAC_C_SENSE (1 << 28) +/** + * Enables DAC state detection logic, for load-based TV detection. + * + * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set + * to off, for load detection to work. + */ +# define TVDAC_STATE_CHG_EN (1 << 27) +/** Sets the DAC A sense value to high */ +# define TVDAC_A_SENSE_CTL (1 << 26) +/** Sets the DAC B sense value to high */ +# define TVDAC_B_SENSE_CTL (1 << 25) +/** Sets the DAC C sense value to high */ +# define TVDAC_C_SENSE_CTL (1 << 24) +/** Overrides the ENC_ENABLE and DAC voltage levels */ +# define DAC_CTL_OVERRIDE (1 << 7) +/** Sets the slew rate. Must be preserved in software */ +# define ENC_TVDAC_SLEW_FAST (1 << 6) +# define DAC_A_1_3_V (0 << 4) +# define DAC_A_1_1_V (1 << 4) +# define DAC_A_0_7_V (2 << 4) +# define DAC_A_MASK (3 << 4) +# define DAC_B_1_3_V (0 << 2) +# define DAC_B_1_1_V (1 << 2) +# define DAC_B_0_7_V (2 << 2) +# define DAC_B_MASK (3 << 2) +# define DAC_C_1_3_V (0 << 0) +# define DAC_C_1_1_V (1 << 0) +# define DAC_C_0_7_V (2 << 0) +# define DAC_C_MASK (3 << 0) +/** @} */ + +/** + * CSC coefficients are stored in a floating point format with 9 bits of + * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n, + * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with + * -1 (0x3) being the only legal negative value. + */ +#define TV_CSC_Y 0x68010 +# define TV_RY_MASK 0x07ff0000 +# define TV_RY_SHIFT 16 +# define TV_GY_MASK 0x00000fff +# define TV_GY_SHIFT 0 + +#define TV_CSC_Y2 0x68014 +# define TV_BY_MASK 0x07ff0000 +# define TV_BY_SHIFT 16 +/** + * Y attenuation for component video. + * + * Stored in 1.9 fixed point. + */ +# define TV_AY_MASK 0x000003ff +# define TV_AY_SHIFT 0 + +#define TV_CSC_U 0x68018 +# define TV_RU_MASK 0x07ff0000 +# define TV_RU_SHIFT 16 +# define TV_GU_MASK 0x000007ff +# define TV_GU_SHIFT 0 + +#define TV_CSC_U2 0x6801c +# define TV_BU_MASK 0x07ff0000 +# define TV_BU_SHIFT 16 +/** + * U attenuation for component video. + * + * Stored in 1.9 fixed point. + */ +# define TV_AU_MASK 0x000003ff +# define TV_AU_SHIFT 0 + +#define TV_CSC_V 0x68020 +# define TV_RV_MASK 0x0fff0000 +# define TV_RV_SHIFT 16 +# define TV_GV_MASK 0x000007ff +# define TV_GV_SHIFT 0 + +#define TV_CSC_V2 0x68024 +# define TV_BV_MASK 0x07ff0000 +# define TV_BV_SHIFT 16 +/** + * V attenuation for component video. + * + * Stored in 1.9 fixed point. + */ +# define TV_AV_MASK 0x000007ff +# define TV_AV_SHIFT 0 + +/** @defgroup TV_CSC_KNOBS + * @{ + */ +#define TV_CLR_KNOBS 0x68028 +/** 2s-complement brightness adjustment */ +# define TV_BRIGHTNESS_MASK 0xff000000 +# define TV_BRIGHTNESS_SHIFT 24 +/** Contrast adjustment, as a 2.6 unsigned floating point number */ +# define TV_CONTRAST_MASK 0x00ff0000 +# define TV_CONTRAST_SHIFT 16 +/** Saturation adjustment, as a 2.6 unsigned floating point number */ +# define TV_SATURATION_MASK 0x0000ff00 +# define TV_SATURATION_SHIFT 8 +/** Hue adjustment, as an integer phase angle in degrees */ +# define TV_HUE_MASK 0x000000ff +# define TV_HUE_SHIFT 0 +/** @} */ + +/** @defgroup TV_CLR_LEVEL + * @{ + */ +#define TV_CLR_LEVEL 0x6802c +/** Controls the DAC level for black */ +# define TV_BLACK_LEVEL_MASK 0x01ff0000 +# define TV_BLACK_LEVEL_SHIFT 16 +/** Controls the DAC level for blanking */ +# define TV_BLANK_LEVEL_MASK 0x000001ff +# define TV_BLANK_LEVEL_SHIFT 0 +/* @} */ + +/** @defgroup TV_H_CTL_1 + * @{ + */ +#define TV_H_CTL_1 0x68030 +/** Number of pixels in the hsync. */ +# define TV_HSYNC_END_MASK 0x1fff0000 +# define TV_HSYNC_END_SHIFT 16 +/** Total number of pixels minus one in the line (display and blanking). */ +# define TV_HTOTAL_MASK 0x00001fff +# define TV_HTOTAL_SHIFT 0 +/** @} */ + +/** @defgroup TV_H_CTL_2 + * @{ + */ +#define TV_H_CTL_2 0x68034 +/** Enables the colorburst (needed for non-component color) */ +# define TV_BURST_ENA (1 << 31) +/** Offset of the colorburst from the start of hsync, in pixels minus one. */ +# define TV_HBURST_START_SHIFT 16 +# define TV_HBURST_START_MASK 0x1fff0000 +/** Length of the colorburst */ +# define TV_HBURST_LEN_SHIFT 0 +# define TV_HBURST_LEN_MASK 0x0001fff +/** @} */ + +/** @defgroup TV_H_CTL_3 + * @{ + */ +#define TV_H_CTL_3 0x68038 +/** End of hblank, measured in pixels minus one from start of hsync */ +# define TV_HBLANK_END_SHIFT 16 +# define TV_HBLANK_END_MASK 0x1fff0000 +/** Start of hblank, measured in pixels minus one from start of hsync */ +# define TV_HBLANK_START_SHIFT 0 +# define TV_HBLANK_START_MASK 0x0001fff +/** @} */ + +/** @defgroup TV_V_CTL_1 + * @{ + */ +#define TV_V_CTL_1 0x6803c +/** XXX */ +# define TV_NBR_END_SHIFT 16 +# define TV_NBR_END_MASK 0x07ff0000 +/** XXX */ +# define TV_VI_END_F1_SHIFT 8 +# define TV_VI_END_F1_MASK 0x00003f00 +/** XXX */ +# define TV_VI_END_F2_SHIFT 0 +# define TV_VI_END_F2_MASK 0x0000003f +/** @} */ + +/** @defgroup TV_V_CTL_2 + * @{ + */ +#define TV_V_CTL_2 0x68040 +/** Length of vsync, in half lines */ +# define TV_VSYNC_LEN_MASK 0x07ff0000 +# define TV_VSYNC_LEN_SHIFT 16 +/** Offset of the start of vsync in field 1, measured in one less than the + * number of half lines. + */ +# define TV_VSYNC_START_F1_MASK 0x00007f00 +# define TV_VSYNC_START_F1_SHIFT 8 +/** + * Offset of the start of vsync in field 2, measured in one less than the + * number of half lines. + */ +# define TV_VSYNC_START_F2_MASK 0x0000007f +# define TV_VSYNC_START_F2_SHIFT 0 +/** @} */ + +/** @defgroup TV_V_CTL_3 + * @{ + */ +#define TV_V_CTL_3 0x68044 +/** Enables generation of the equalization signal */ +# define TV_EQUAL_ENA (1 << 31) +/** Length of vsync, in half lines */ +# define TV_VEQ_LEN_MASK 0x007f0000 +# define TV_VEQ_LEN_SHIFT 16 +/** Offset of the start of equalization in field 1, measured in one less than + * the number of half lines. + */ +# define TV_VEQ_START_F1_MASK 0x0007f00 +# define TV_VEQ_START_F1_SHIFT 8 +/** + * Offset of the start of equalization in field 2, measured in one less than + * the number of half lines. + */ +# define TV_VEQ_START_F2_MASK 0x000007f +# define TV_VEQ_START_F2_SHIFT 0 +/** @} */ + +/** @defgroup TV_V_CTL_4 + * @{ + */ +#define TV_V_CTL_4 0x68048 +/** + * Offset to start of vertical colorburst, measured in one less than the + * number of lines from vertical start. + */ +# define TV_VBURST_START_F1_MASK 0x003f0000 +# define TV_VBURST_START_F1_SHIFT 16 +/** + * Offset to the end of vertical colorburst, measured in one less than the + * number of lines from the start of NBR. + */ +# define TV_VBURST_END_F1_MASK 0x000000ff +# define TV_VBURST_END_F1_SHIFT 0 +/** @} */ + +/** @defgroup TV_V_CTL_5 + * @{ + */ +#define TV_V_CTL_5 0x6804c +/** + * Offset to start of vertical colorburst, measured in one less than the + * number of lines from vertical start. + */ +# define TV_VBURST_START_F2_MASK 0x003f0000 +# define TV_VBURST_START_F2_SHIFT 16 +/** + * Offset to the end of vertical colorburst, measured in one less than the + * number of lines from the start of NBR. + */ +# define TV_VBURST_END_F2_MASK 0x000000ff +# define TV_VBURST_END_F2_SHIFT 0 +/** @} */ + +/** @defgroup TV_V_CTL_6 + * @{ + */ +#define TV_V_CTL_6 0x68050 +/** + * Offset to start of vertical colorburst, measured in one less than the + * number of lines from vertical start. + */ +# define TV_VBURST_START_F3_MASK 0x003f0000 +# define TV_VBURST_START_F3_SHIFT 16 +/** + * Offset to the end of vertical colorburst, measured in one less than the + * number of lines from the start of NBR. + */ +# define TV_VBURST_END_F3_MASK 0x000000ff +# define TV_VBURST_END_F3_SHIFT 0 +/** @} */ + +/** @defgroup TV_V_CTL_7 + * @{ + */ +#define TV_V_CTL_7 0x68054 +/** + * Offset to start of vertical colorburst, measured in one less than the + * number of lines from vertical start. + */ +# define TV_VBURST_START_F4_MASK 0x003f0000 +# define TV_VBURST_START_F4_SHIFT 16 +/** + * Offset to the end of vertical colorburst, measured in one less than the + * number of lines from the start of NBR. + */ +# define TV_VBURST_END_F4_MASK 0x000000ff +# define TV_VBURST_END_F4_SHIFT 0 +/** @} */ + +/** @defgroup TV_SC_CTL_1 + * @{ + */ +#define TV_SC_CTL_1 0x68060 +/** Turns on the first subcarrier phase generation DDA */ +# define TV_SC_DDA1_EN (1 << 31) +/** Turns on the first subcarrier phase generation DDA */ +# define TV_SC_DDA2_EN (1 << 30) +/** Turns on the first subcarrier phase generation DDA */ +# define TV_SC_DDA3_EN (1 << 29) +/** Sets the subcarrier DDA to reset frequency every other field */ +# define TV_SC_RESET_EVERY_2 (0 << 24) +/** Sets the subcarrier DDA to reset frequency every fourth field */ +# define TV_SC_RESET_EVERY_4 (1 << 24) +/** Sets the subcarrier DDA to reset frequency every eighth field */ +# define TV_SC_RESET_EVERY_8 (2 << 24) +/** Sets the subcarrier DDA to never reset the frequency */ +# define TV_SC_RESET_NEVER (3 << 24) +/** Sets the peak amplitude of the colorburst.*/ +# define TV_BURST_LEVEL_MASK 0x00ff0000 +# define TV_BURST_LEVEL_SHIFT 16 +/** Sets the increment of the first subcarrier phase generation DDA */ +# define TV_SCDDA1_INC_MASK 0x00000fff +# define TV_SCDDA1_INC_SHIFT 0 +/** @} */ + +/** @defgroup TV_SC_CTL_2 + * @{ + */ +#define TV_SC_CTL_2 0x68064 +/** Sets the rollover for the second subcarrier phase generation DDA */ +# define TV_SCDDA2_SIZE_MASK 0x7fff0000 +# define TV_SCDDA2_SIZE_SHIFT 16 +/** Sets the increent of the second subcarrier phase generation DDA */ +# define TV_SCDDA2_INC_MASK 0x00007fff +# define TV_SCDDA2_INC_SHIFT 0 +/** @} */ + +/** @defgroup TV_SC_CTL_3 + * @{ + */ +#define TV_SC_CTL_3 0x68068 +/** Sets the rollover for the third subcarrier phase generation DDA */ +# define TV_SCDDA3_SIZE_MASK 0x7fff0000 +# define TV_SCDDA3_SIZE_SHIFT 16 +/** Sets the increent of the third subcarrier phase generation DDA */ +# define TV_SCDDA3_INC_MASK 0x00007fff +# define TV_SCDDA3_INC_SHIFT 0 +/** @} */ + +/** @defgroup TV_WIN_POS + * @{ + */ +#define TV_WIN_POS 0x68070 +/** X coordinate of the display from the start of horizontal active */ +# define TV_XPOS_MASK 0x1fff0000 +# define TV_XPOS_SHIFT 16 +/** Y coordinate of the display from the start of vertical active (NBR) */ +# define TV_YPOS_MASK 0x00000fff +# define TV_YPOS_SHIFT 0 +/** @} */ + +/** @defgroup TV_WIN_SIZE + * @{ + */ +#define TV_WIN_SIZE 0x68074 +/** Horizontal size of the display window, measured in pixels*/ +# define TV_XSIZE_MASK 0x1fff0000 +# define TV_XSIZE_SHIFT 16 +/** + * Vertical size of the display window, measured in pixels. + * + * Must be even for interlaced modes. + */ +# define TV_YSIZE_MASK 0x00000fff +# define TV_YSIZE_SHIFT 0 +/** @} */ + +/** @defgroup TV_FILTER_CTL_1 + * @{ + */ +#define TV_FILTER_CTL_1 0x68080 +/** + * Enables automatic scaling calculation. + * + * If set, the rest of the registers are ignored, and the calculated values can + * be read back from the register. + */ +# define TV_AUTO_SCALE (1 << 31) +/** + * Disables the vertical filter. + * + * This is required on modes more than 1024 pixels wide */ +# define TV_V_FILTER_BYPASS (1 << 29) +/** Enables adaptive vertical filtering */ +# define TV_VADAPT (1 << 28) +# define TV_VADAPT_MODE_MASK (3 << 26) +/** Selects the least adaptive vertical filtering mode */ +# define TV_VADAPT_MODE_LEAST (0 << 26) +/** Selects the moderately adaptive vertical filtering mode */ +# define TV_VADAPT_MODE_MODERATE (1 << 26) +/** Selects the most adaptive vertical filtering mode */ +# define TV_VADAPT_MODE_MOST (3 << 26) +/** + * Sets the horizontal scaling factor. + * + * This should be the fractional part of the horizontal scaling factor divided + * by the oversampling rate. TV_HSCALE should be less than 1, and set to: + * + * (src width - 1) / ((oversample * dest width) - 1) + */ +# define TV_HSCALE_FRAC_MASK 0x00003fff +# define TV_HSCALE_FRAC_SHIFT 0 +/** @} */ + +/** @defgroup TV_FILTER_CTL_2 + * @{ + */ +#define TV_FILTER_CTL_2 0x68084 +/** + * Sets the integer part of the 3.15 fixed-point vertical scaling factor. + * + * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) + */ +# define TV_VSCALE_INT_MASK 0x00038000 +# define TV_VSCALE_INT_SHIFT 15 +/** + * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. + * + * \sa TV_VSCALE_INT_MASK + */ +# define TV_VSCALE_FRAC_MASK 0x00007fff +# define TV_VSCALE_FRAC_SHIFT 0 +/** @} */ + +/** @defgroup TV_FILTER_CTL_3 + * @{ + */ +#define TV_FILTER_CTL_3 0x68088 +/** + * Sets the integer part of the 3.15 fixed-point vertical scaling factor. + * + * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) + * + * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. + */ +# define TV_VSCALE_IP_INT_MASK 0x00038000 +# define TV_VSCALE_IP_INT_SHIFT 15 +/** + * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. + * + * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. + * + * \sa TV_VSCALE_IP_INT_MASK + */ +# define TV_VSCALE_IP_FRAC_MASK 0x00007fff +# define TV_VSCALE_IP_FRAC_SHIFT 0 +/** @} */ + +/** @defgroup TV_CC_CONTROL + * @{ + */ +#define TV_CC_CONTROL 0x68090 +# define TV_CC_ENABLE (1 << 31) +/** + * Specifies which field to send the CC data in. + * + * CC data is usually sent in field 0. + */ +# define TV_CC_FID_MASK (1 << 27) +# define TV_CC_FID_SHIFT 27 +/** Sets the horizontal position of the CC data. Usually 135. */ +# define TV_CC_HOFF_MASK 0x03ff0000 +# define TV_CC_HOFF_SHIFT 16 +/** Sets the vertical position of the CC data. Usually 21 */ +# define TV_CC_LINE_MASK 0x0000003f +# define TV_CC_LINE_SHIFT 0 +/** @} */ + +/** @defgroup TV_CC_DATA + * @{ + */ +#define TV_CC_DATA 0x68094 +# define TV_CC_RDY (1 << 31) +/** Second word of CC data to be transmitted. */ +# define TV_CC_DATA_2_MASK 0x007f0000 +# define TV_CC_DATA_2_SHIFT 16 +/** First word of CC data to be transmitted. */ +# define TV_CC_DATA_1_MASK 0x0000007f +# define TV_CC_DATA_1_SHIFT 0 +/** @} + */ + +/** @{ */ +#define TV_H_LUMA_0 0x68100 +#define TV_H_LUMA_59 0x681ec +#define TV_H_CHROMA_0 0x68200 +#define TV_H_CHROMA_59 0x682ec +#define TV_V_LUMA_0 0x68300 +#define TV_V_LUMA_42 0x683a8 +#define TV_V_CHROMA_0 0x68400 +#define TV_V_CHROMA_42 0x684a8 +/** @} */ + +#define PIPEA_DSL 0x70000 + +#define PIPEACONF 0x70008 +#define PIPEACONF_ENABLE (1<<31) +#define PIPEACONF_DISABLE 0 +#define PIPEACONF_DOUBLE_WIDE (1<<30) +#define I965_PIPECONF_ACTIVE (1<<30) +#define PIPEACONF_SINGLE_WIDE 0 +#define PIPEACONF_PIPE_UNLOCKED 0 +#define PIPEACONF_PIPE_LOCKED (1<<25) +#define PIPEACONF_PALETTE 0 +#define PIPEACONF_GAMMA (1<<24) +/* IGDNG: gamma */ +#define PIPECONF_PALETTE_8BIT (0<<24) +#define PIPECONF_PALETTE_10BIT (1<<24) +#define PIPECONF_PALETTE_12BIT (2<<24) +#define PIPECONF_FORCE_BORDER (1<<25) +#define PIPECONF_PROGRESSIVE (0 << 21) +#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) +#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) +/* IGDNG */ +#define PIPECONF_MSA_TIMING_DELAY (0<<18) /* for eDP */ +#define PIPECONF_NO_DYNAMIC_RATE_CHANGE (0 << 16) +#define PIPECONF_NO_ROTATION (0<<14) +#define PIPECONF_FULL_COLOR_RANGE (0<<13) +#define PIPECONF_CE_COLOR_RANGE (1<<13) +#define PIPECONF_COLOR_SPACE_RGB (0<<11) +#define PIPECONF_COLOR_SPACE_YUV601 (1<<11) +#define PIPECONF_COLOR_SPACE_YUV709 (2<<11) +#define PIPECONF_CONNECT_DEFAULT (0<<9) +#define PIPECONF_8BPP (0<<5) +#define PIPECONF_10BPP (1<<5) +#define PIPECONF_6BPP (2<<5) +#define PIPECONF_12BPP (3<<5) +#define PIPECONF_ENABLE_DITHER (1<<4) +#define PIPECONF_DITHER_SPATIAL (0<<2) +#define PIPECONF_DITHER_ST1 (1<<2) +#define PIPECONF_DITHER_ST2 (2<<2) +#define PIPECONF_DITHER_TEMPORAL (3<<2) + +#define PIPEAGCMAXRED 0x70010 +#define PIPEAGCMAXGREEN 0x70014 +#define PIPEAGCMAXBLUE 0x70018 +#define PIPEASTAT 0x70024 +# define FIFO_UNDERRUN (1 << 31) +# define CRC_ERROR_ENABLE (1 << 29) +# define CRC_DONE_ENABLE (1 << 28) +# define GMBUS_EVENT_ENABLE (1 << 27) +# define VSYNC_INT_ENABLE (1 << 25) +# define DLINE_COMPARE_ENABLE (1 << 24) +# define DPST_EVENT_ENABLE (1 << 23) +# define LBLC_EVENT_ENABLE (1 << 22) +# define OFIELD_INT_ENABLE (1 << 21) +# define EFIELD_INT_ENABLE (1 << 20) +# define SVBLANK_INT_ENABLE (1 << 18) +# define VBLANK_INT_ENABLE (1 << 17) +# define OREG_UPDATE_ENABLE (1 << 16) +# define CRC_ERROR_INT_STATUS (1 << 13) +# define CRC_DONE_INT_STATUS (1 << 12) +# define GMBUS_INT_STATUS (1 << 11) +# define VSYNC_INT_STATUS (1 << 9) +# define DLINE_COMPARE_STATUS (1 << 8) +# define DPST_EVENT_STATUS (1 << 7) +# define LBLC_EVENT_STATUS (1 << 6) +# define OFIELD_INT_STATUS (1 << 5) +# define EFIELD_INT_STATUS (1 << 4) +# define SVBLANK_INT_STATUS (1 << 2) +# define VBLANK_INT_STATUS (1 << 1) +# define OREG_UPDATE_STATUS (1 << 0) +#define PIPE_BPC_MASK (7 << 5) /* Ironlake */ +#define PIPE_8BPC (0 << 5) +#define PIPE_10BPC (1 << 5) +#define PIPE_6BPC (2 << 5) +#define PIPE_12BPC (3 << 5) + + + +#define DSPARB 0x70030 +#define DSPARB_CSTART_SHIFT 7 +#define DSPARB_BSTART_SHIFT 0 +#define DSPARB_BEND_SHIFT 9 /* on 855 */ +#define DSPARB_AEND_SHIFT 0 +#define DSPFW1 0x70034 +#define DSPFW2 0x70038 +#define DSPFW3 0x7003c +/* + * The two pipe frame counter registers are not synchronized, so + * reading a stable value is somewhat tricky. The following code + * should work: + * + * do { + * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> PIPE_FRAME_HIGH_SHIFT; + * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> PIPE_FRAME_LOW_SHIFT); + * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> PIPE_FRAME_HIGH_SHIFT); + * } while (high1 != high2); + * frame = (high1 << 8) | low1; + */ +#define PIPEAFRAMEHIGH 0x70040 +#define PIPE_FRAME_HIGH_MASK 0x0000ffff +#define PIPE_FRAME_HIGH_SHIFT 0 +#define PIPEAFRAMEPIXEL 0x70044 +#define PIPE_FRAME_LOW_MASK 0xff000000 +#define PIPE_FRAME_LOW_SHIFT 24 +/* + * Pixel within the current frame is counted in the PIPEAFRAMEPIXEL register + * and is 24 bits wide. + */ +#define PIPE_PIXEL_MASK 0x00ffffff +#define PIPE_PIXEL_SHIFT 0 + +/* + * Computing GMCH M and N values. + * + * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes + * + * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) + * + * The GMCH value is used internally + */ +#define PIPEA_GMCH_DATA_M 0x70050 + +/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ +#define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25) +#define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25 + +#define PIPE_GMCH_DATA_M_MASK (0xffffff) + +#define PIPEA_GMCH_DATA_N 0x70054 +#define PIPE_GMCH_DATA_N_MASK (0xffffff) + +/* + * Computing Link M and N values. + * + * Link M / N = pixel_clock / ls_clk + * + * (the DP spec calls pixel_clock the 'strm_clk') + * + * The Link value is transmitted in the Main Stream + * Attributes and VB-ID. + */ + +#define PIPEA_DP_LINK_M 0x70060 +#define PIPEA_DP_LINK_M_MASK (0xffffff) + +#define PIPEA_DP_LINK_N 0x70064 +#define PIPEA_DP_LINK_N_MASK (0xffffff) + +#define PIPEB_DSL 0x71000 + +#define PIPEBCONF 0x71008 +#define PIPEBCONF_ENABLE (1<<31) +#define PIPEBCONF_DISABLE 0 +#define PIPEBCONF_DOUBLE_WIDE (1<<30) +#define PIPEBCONF_DISABLE 0 +#define PIPEBCONF_GAMMA (1<<24) +#define PIPEBCONF_PALETTE 0 + +#define PIPEBGCMAXRED 0x71010 +#define PIPEBGCMAXGREEN 0x71014 +#define PIPEBGCMAXBLUE 0x71018 +#define PIPEBSTAT 0x71024 +#define PIPEBFRAMEHIGH 0x71040 +#define PIPEBFRAMEPIXEL 0x71044 + +#define PIPEB_GMCH_DATA_M 0x71050 +#define PIPEB_GMCH_DATA_N 0x71054 +#define PIPEB_DP_LINK_M 0x71060 +#define PIPEB_DP_LINK_N 0x71064 + +#define DSPACNTR 0x70180 +#define DSPBCNTR 0x71180 +#define DISPLAY_PLANE_ENABLE (1<<31) +#define DISPLAY_PLANE_DISABLE 0 +#define DISPLAY_PLANE_TILED (1<<10) +#define DISPPLANE_GAMMA_ENABLE (1<<30) +#define DISPPLANE_GAMMA_DISABLE 0 +#define DISPPLANE_PIXFORMAT_MASK (0xf<<26) +#define DISPPLANE_8BPP (0x2<<26) +#define DISPPLANE_15_16BPP (0x4<<26) +#define DISPPLANE_16BPP (0x5<<26) +#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) /* IGDNG: BGRX */ +#define DISPPLANE_32BPP (0x7<<26) /* IGDNG: not support */ +/* IGDNG */ +#define DISPPLANE_32BPP_10 (0x8<<26) /* 2:10:10:10 */ +#define DISPPLANE_32BPP_BGRX (0xa<<26) +#define DISPPLANE_64BPP (0xc<<26) +#define DISPPLANE_32BPP_RGBX (0xe<<26) +#define DISPPLANE_STEREO_ENABLE (1<<25) +#define DISPPLANE_STEREO_DISABLE 0 +#define DISPPLANE_SEL_PIPE_MASK (1<<24) +#define DISPPLANE_SEL_PIPE_A 0 /* IGDNG: don't use */ +#define DISPPLANE_SEL_PIPE_B (1<<24) +#define DISPPLANE_NORMAL_RANGE (0<<25) +#define DISPPLANE_EXT_RANGE (1<<25) +/* IGDNG */ +#define DISPPLANE_CSC_BYPASS (0<<24) +#define DISPPLANE_CSC_PASSTHROUGH (1<<24) +#define DISPPLANE_SRC_KEY_ENABLE (1<<22) +#define DISPPLANE_SRC_KEY_DISABLE 0 +#define DISPPLANE_LINE_DOUBLE (1<<20) +#define DISPPLANE_NO_LINE_DOUBLE 0 +#define DISPPLANE_STEREO_POLARITY_FIRST 0 +#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) +/* plane B only */ +#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) +#define DISPPLANE_ALPHA_TRANS_DISABLE 0 +#define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0 +#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) +/* IGDNG */ +#define DISPPLANE_X_TILE (1<<10) +#define DISPPLANE_LINEAR (0<<10) +#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) + +#define DSPABASE 0x70184 +/* IGDNG */ +#define DSPALINOFF 0x70184 +#define DSPASTRIDE 0x70188 + +#define DSPBBASE 0x71184 +/* IGDNG */ +#define DSPBLINOFF 0x71184 +#define DSPBADDR DSPBBASE +#define DSPBSTRIDE 0x71188 + +#define DSPAKEYVAL 0x70194 +#define DSPAKEYMASK 0x70198 + +#define DSPAPOS 0x7018C /* reserved */ +#define DSPASIZE 0x70190 +#define DSPBPOS 0x7118C +#define DSPBSIZE 0x71190 + +#define DSPASURF 0x7019C +#define DSPATILEOFF 0x701A4 + +#define DSPBSURF 0x7119C +#define DSPBTILEOFF 0x711A4 + +#define VGACNTRL 0x71400 +# define VGA_DISP_DISABLE (1 << 31) +# define VGA_2X_MODE (1 << 30) +# define VGA_PIPE_B_SELECT (1 << 29) + +/* Various masks for reserved bits, etc. */ +#define I830_FWATER1_MASK (~((1<<11)|(1<<10)|(1<<9)| \ + (1<<8)|(1<<26)|(1<<25)|(1<<24)|(1<<5)|(1<<4)|(1<<3)| \ + (1<<2)|(1<<1)|1|(1<<20)|(1<<19)|(1<<18)|(1<<17)|(1<<16))) +#define I830_FWATER2_MASK ~(0) + +#define DV0A_RESERVED ((1<<26)|(1<<25)|(1<<24)|(1<<23)|(1<<22)|(1<<21)|(1<<20)|(1<<19)|(1<<18)|(1<<16)|(1<<5)|(1<<1)|1) +#define DV0B_RESERVED ((1<<27)|(1<<26)|(1<<25)|(1<<24)|(1<<23)|(1<<22)|(1<<21)|(1<<20)|(1<<19)|(1<<18)|(1<<16)|(1<<5)|(1<<1)|1) +#define VGA0_N_DIVISOR_MASK ((1<<21)|(1<<20)|(1<<19)|(1<<18)|(1<<17)|(1<<16)) +#define VGA0_M1_DIVISOR_MASK ((1<<13)|(1<<12)|(1<<11)|(1<<10)|(1<<9)|(1<<8)) +#define VGA0_M2_DIVISOR_MASK ((1<<5)|(1<<4)|(1<<3)|(1<<2)|(1<<1)|1) +#define VGA0_M1M2N_RESERVED ~(VGA0_N_DIVISOR_MASK|VGA0_M1_DIVISOR_MASK|VGA0_M2_DIVISOR_MASK) +#define VGA0_POSTDIV_MASK ((1<<7)|(1<<5)|(1<<4)|(1<<3)|(1<<2)|(1<<1)|1) +#define VGA1_POSTDIV_MASK ((1<<15)|(1<<13)|(1<<12)|(1<<11)|(1<<10)|(1<<9)|(1<<8)) +#define VGA_POSTDIV_RESERVED ~(VGA0_POSTDIV_MASK|VGA1_POSTDIV_MASK|(1<<7)|(1<<15)) +#define DPLLA_POSTDIV_MASK ((1<<23)|(1<<21)|(1<<20)|(1<<19)|(1<<18)|(1<<17)|(1<<16)) +#define DPLLA_RESERVED ((1<<27)|(1<<26)|(1<<25)|(1<<24)|(1<<22)|(1<<15)|(1<<12)|(1<<11)|(1<<10)|(1<<9)|(1<<8)|(1<<7)|(1<<6)|(1<<5)|(1<<4)|(1<<3)|(1<<2)|(1<<1)|1) +#define ADPA_RESERVED ((1<<2)|(1<<1)|1|(1<<9)|(1<<8)|(1<<7)|(1<<6)|(1<<5)|(1<<30)|(1<<29)|(1<<28)|(1<<27)|(1<<26)|(1<<25)|(1<<24)|(1<<23)|(1<<22)|(1<<21)|(1<<20)|(1<<19)|(1<<18)|(1<<17)|(1<<16)) +#define SUPER_WORD 32 +#define BURST_A_MASK ((1<<11)|(1<<10)|(1<<9)|(1<<8)) +#define BURST_B_MASK ((1<<26)|(1<<25)|(1<<24)) +#define WATER_A_MASK ((1<<5)|(1<<4)|(1<<3)|(1<<2)|(1<<1)|1) +#define WATER_B_MASK ((1<<20)|(1<<19)|(1<<18)|(1<<17)|(1<<16)) +#define WATER_RESERVED ((1<<31)|(1<<30)|(1<<29)|(1<<28)|(1<<27)|(1<<23)|(1<<22)|(1<<21)|(1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<7)|(1<<6)) +#define PIPEACONF_RESERVED ((1<<29)|(1<<28)|(1<<27)|(1<<23)|(1<<22)|(1<<21)|(1<<20)|(1<<19)|(1<<18)|(1<<17)|(1<<16)|0xffff) +#define PIPEBCONF_RESERVED ((1<<30)|(1<<29)|(1<<28)|(1<<27)|(1<<26)|(1<<25)|(1<<23)|(1<<22)|(1<<21)|(1<<20)|(1<<19)|(1<<18)|(1<<17)|(1<<16)|0xffff) +#define DSPACNTR_RESERVED ((1<<23)|(1<<19)|(1<<17)|(1<<16)|0xffff) +#define DSPBCNTR_RESERVED ((1<<23)|(1<<19)|(1<<17)|(1<<16)|0x7ffe) + +#define I830_GMCH_CTRL 0x52 + +#define I830_GMCH_ENABLED 0x4 +#define I830_GMCH_MEM_MASK 0x1 +#define I830_GMCH_MEM_64M 0x1 +#define I830_GMCH_MEM_128M 0 + +#define I830_GMCH_GMS_MASK 0x70 +#define I830_GMCH_GMS_DISABLED 0x00 +#define I830_GMCH_GMS_LOCAL 0x10 +#define I830_GMCH_GMS_STOLEN_512 0x20 +#define I830_GMCH_GMS_STOLEN_1024 0x30 +#define I830_GMCH_GMS_STOLEN_8192 0x40 + +#define I830_RDRAM_CHANNEL_TYPE 0x03010 +#define I830_RDRAM_ND(x) (((x) & 0x20) >> 5) +#define I830_RDRAM_DDT(x) (((x) & 0x18) >> 3) + +#define I855_GMCH_GMS_MASK (0xF << 4) +#define I855_GMCH_GMS_DISABLED 0x00 +#define I855_GMCH_GMS_STOLEN_1M (0x1 << 4) +#define I855_GMCH_GMS_STOLEN_4M (0x2 << 4) +#define I855_GMCH_GMS_STOLEN_8M (0x3 << 4) +#define I855_GMCH_GMS_STOLEN_16M (0x4 << 4) +#define I855_GMCH_GMS_STOLEN_32M (0x5 << 4) +#define I915G_GMCH_GMS_STOLEN_48M (0x6 << 4) +#define I915G_GMCH_GMS_STOLEN_64M (0x7 << 4) +#define G33_GMCH_GMS_STOLEN_128M (0x8 << 4) +#define G33_GMCH_GMS_STOLEN_256M (0x9 << 4) +#define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4) +#define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4) +#define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4) +#define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4) + + +#define I85X_CAPID 0x44 +#define I85X_VARIANT_MASK 0x7 +#define I85X_VARIANT_SHIFT 5 +#define I855_GME 0x0 +#define I855_GM 0x4 +#define I852_GME 0x2 +#define I852_GM 0x5 + +#define I915_GCFGC 0xf0 +#define I915_LOW_FREQUENCY_ENABLE (1 << 7) +#define I915_DISPLAY_CLOCK_190_200_MHZ (0 << 4) +#define I915_DISPLAY_CLOCK_333_MHZ (4 << 4) +#define I915_DISPLAY_CLOCK_MASK (7 << 4) + +#define I855_HPLLCC 0xc0 +#define I855_CLOCK_CONTROL_MASK (3 << 0) +#define I855_CLOCK_133_200 (0 << 0) +#define I855_CLOCK_100_200 (1 << 0) +#define I855_CLOCK_100_133 (2 << 0) +#define I855_CLOCK_166_250 (3 << 0) + +/* BLT commands */ +#define COLOR_BLT_CMD ((2<<29)|(0x40<<22)|(0x3)) +#define COLOR_BLT_WRITE_ALPHA (1<<21) +#define COLOR_BLT_WRITE_RGB (1<<20) + +#define XY_COLOR_BLT_CMD ((2<<29)|(0x50<<22)|(0x4)) +#define XY_COLOR_BLT_WRITE_ALPHA (1<<21) +#define XY_COLOR_BLT_WRITE_RGB (1<<20) +#define XY_COLOR_BLT_TILED (1<<11) + +#define XY_SETUP_CLIP_BLT_CMD ((2<<29)|(3<<22)|1) + +#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) +#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) +#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) +#define XY_SRC_COPY_BLT_SRC_TILED (1<<15) +#define XY_SRC_COPY_BLT_DST_TILED (1<<11) + +#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|0x4) +#define SRC_COPY_BLT_WRITE_ALPHA (1<<21) +#define SRC_COPY_BLT_WRITE_RGB (1<<20) + +#define XY_PAT_BLT_IMMEDIATE ((2<<29)|(0x72<<22)) + +#define XY_MONO_PAT_BLT_CMD ((0x2<<29)|(0x52<<22)|0x7) +#define XY_MONO_PAT_VERT_SEED ((1<<10)|(1<<9)|(1<<8)) +#define XY_MONO_PAT_HORT_SEED ((1<<14)|(1<<13)|(1<<12)) +#define XY_MONO_PAT_BLT_WRITE_ALPHA (1<<21) +#define XY_MONO_PAT_BLT_WRITE_RGB (1<<20) + +#define XY_MONO_SRC_BLT_CMD ((0x2<<29)|(0x54<<22)|(0x6)) +#define XY_MONO_SRC_BLT_WRITE_ALPHA (1<<21) +#define XY_MONO_SRC_BLT_WRITE_RGB (1<<20) + +#define STATE3D_FOG_MODE ((3<<29)|(0x1d<<24)|(0x89<<16)|2) +#define FOG_MODE_VERTEX (1<<31) + +#define DISABLE_TEX_TRANSFORM (1<<28) +#define TEXTURE_SET(x) (x<<29) + +#define STATE3D_VERTEX_TRANSFORM ((3<<29)|(0x1d<<24)|(0x8b<<16)) +#define DISABLE_VIEWPORT_TRANSFORM (1<<31) +#define DISABLE_PERSPECTIVE_DIVIDE (1<<29) + +#define MI_SET_CONTEXT (0x18<<23) +#define CTXT_NO_RESTORE (1) +#define CTXT_PALETTE_SAVE_DISABLE (1<<3) +#define CTXT_PALETTE_RESTORE_DISABLE (1<<2) + +/* Dword 0 */ +#define MI_VERTEX_BUFFER (0x17<<23) +#define MI_VERTEX_BUFFER_IDX(x) (x<<20) +#define MI_VERTEX_BUFFER_PITCH(x) (x<<13) +#define MI_VERTEX_BUFFER_WIDTH(x) (x<<6) +/* Dword 1 */ +#define MI_VERTEX_BUFFER_DISABLE (1) + +/* Overlay Flip */ +#define MI_OVERLAY_FLIP (0x11<<23) +#define MI_OVERLAY_FLIP_CONTINUE (0<<21) +#define MI_OVERLAY_FLIP_ON (1<<21) +#define MI_OVERLAY_FLIP_OFF (2<<21) + +/* Wait for Events */ +#define MI_WAIT_FOR_EVENT (0x03<<23) +#define MI_WAIT_FOR_PIPEB_SVBLANK (1<<18) +#define MI_WAIT_FOR_PIPEA_SVBLANK (1<<17) +#define MI_WAIT_FOR_OVERLAY_FLIP (1<<16) +#define MI_WAIT_FOR_PIPEB_VBLANK (1<<7) +#define MI_WAIT_FOR_PIPEB_SCAN_LINE_WINDOW (1<<5) +#define MI_WAIT_FOR_PIPEA_VBLANK (1<<3) +#define MI_WAIT_FOR_PIPEA_SCAN_LINE_WINDOW (1<<1) + +/* Set the scan line for MI_WAIT_FOR_PIPE?_SCAN_LINE_WINDOW */ +#define MI_LOAD_SCAN_LINES_INCL (0x12<<23) +#define MI_LOAD_SCAN_LINES_DISPLAY_PIPEA (0) +#define MI_LOAD_SCAN_LINES_DISPLAY_PIPEB (0x1<<20) + +/* Flush */ +#define MI_FLUSH (0x04<<23) +#define MI_WRITE_DIRTY_STATE (1<<4) +#define MI_END_SCENE (1<<3) +#define MI_GLOBAL_SNAPSHOT_COUNT_RESET (1<<3) +#define MI_INHIBIT_RENDER_CACHE_FLUSH (1<<2) +#define MI_STATE_INSTRUCTION_CACHE_FLUSH (1<<1) +#define MI_INVALIDATE_MAP_CACHE (1<<0) +/* broadwater flush bits */ +#define BRW_MI_GLOBAL_SNAPSHOT_RESET (1 << 3) + +/* Noop */ +#define MI_NOOP 0x00 +#define MI_NOOP_WRITE_ID (1<<22) +#define MI_NOOP_ID_MASK (1<<22 - 1) + +#define STATE3D_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x01<<16)) + +/* Batch */ +#define MI_BATCH_BUFFER ((0x30 << 23) | 1) +#define MI_BATCH_BUFFER_START (0x31 << 23) +#define MI_BATCH_BUFFER_END (0xA << 23) +#define MI_BATCH_NON_SECURE (1) +#define MI_BATCH_NON_SECURE_I965 (1 << 8) + +/* STATE3D_FOG_MODE stuff */ +#define ENABLE_FOG_SOURCE (1<<27) +#define ENABLE_FOG_CONST (1<<24) +#define ENABLE_FOG_DENSITY (1<<23) + +/* + * New regs for broadwater -- we need to split this file up sensibly somehow. + */ +#define BRW_3D(Pipeline,Opcode,Subopcode) ((3 << 29) | \ + ((Pipeline) << 27) | \ + ((Opcode) << 24) | \ + ((Subopcode) << 16)) + +#define BRW_URB_FENCE BRW_3D(0, 0, 0) +#define BRW_CS_URB_STATE BRW_3D(0, 0, 1) +#define BRW_CONSTANT_BUFFER BRW_3D(0, 0, 2) +#define BRW_STATE_PREFETCH BRW_3D(0, 0, 3) + +#define BRW_STATE_BASE_ADDRESS BRW_3D(0, 1, 1) +#define BRW_STATE_SIP BRW_3D(0, 1, 2) +#define BRW_PIPELINE_SELECT BRW_3D(0, 1, 4) + +#define NEW_PIPELINE_SELECT BRW_3D(1, 1, 4) + +#define BRW_MEDIA_STATE_POINTERS BRW_3D(2, 0, 0) +#define BRW_MEDIA_OBJECT BRW_3D(2, 1, 0) + +#define BRW_3DSTATE_PIPELINED_POINTERS BRW_3D(3, 0, 0) +#define BRW_3DSTATE_BINDING_TABLE_POINTERS BRW_3D(3, 0, 1) +#define BRW_3DSTATE_VERTEX_BUFFERS BRW_3D(3, 0, 8) +#define BRW_3DSTATE_VERTEX_ELEMENTS BRW_3D(3, 0, 9) +#define BRW_3DSTATE_INDEX_BUFFER BRW_3D(3, 0, 0xa) +#define BRW_3DSTATE_VF_STATISTICS BRW_3D(3, 0, 0xb) + +#define BRW_3DSTATE_DRAWING_RECTANGLE BRW_3D(3, 1, 0) +#define BRW_3DSTATE_CONSTANT_COLOR BRW_3D(3, 1, 1) +#define BRW_3DSTATE_SAMPLER_PALETTE_LOAD BRW_3D(3, 1, 2) +#define BRW_3DSTATE_CHROMA_KEY BRW_3D(3, 1, 4) +#define BRW_3DSTATE_DEPTH_BUFFER BRW_3D(3, 1, 5) +#define BRW_3DSTATE_POLY_STIPPLE_OFFSET BRW_3D(3, 1, 6) +#define BRW_3DSTATE_POLY_STIPPLE_PATTERN BRW_3D(3, 1, 7) +#define BRW_3DSTATE_LINE_STIPPLE BRW_3D(3, 1, 8) +#define BRW_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP BRW_3D(3, 1, 9) +/* These two are BLC and CTG only, not BW or CL */ +#define BRW_3DSTATE_AA_LINE_PARAMS BRW_3D(3, 1, 0xa) +#define BRW_3DSTATE_GS_SVB_INDEX BRW_3D(3, 1, 0xb) + +#define BRW_PIPE_CONTROL BRW_3D(3, 2, 0) + +#define BRW_3DPRIMITIVE BRW_3D(3, 3, 0) + +#define PIPELINE_SELECT_3D 0 +#define PIPELINE_SELECT_MEDIA 1 + +#define UF0_CS_REALLOC (1 << 13) +#define UF0_VFE_REALLOC (1 << 12) +#define UF0_SF_REALLOC (1 << 11) +#define UF0_CLIP_REALLOC (1 << 10) +#define UF0_GS_REALLOC (1 << 9) +#define UF0_VS_REALLOC (1 << 8) +#define UF1_CLIP_FENCE_SHIFT 20 +#define UF1_GS_FENCE_SHIFT 10 +#define UF1_VS_FENCE_SHIFT 0 +#define UF2_CS_FENCE_SHIFT 20 +#define UF2_VFE_FENCE_SHIFT 10 +#define UF2_SF_FENCE_SHIFT 0 + +/* for BRW_STATE_BASE_ADDRESS */ +#define BASE_ADDRESS_MODIFY (1 << 0) + +/* for BRW_3DSTATE_PIPELINED_POINTERS */ +#define BRW_GS_DISABLE 0 +#define BRW_GS_ENABLE 1 +#define BRW_CLIP_DISABLE 0 +#define BRW_CLIP_ENABLE 1 + +/* for BRW_PIPE_CONTROL */ +#define BRW_PIPE_CONTROL_NOWRITE (0 << 14) +#define BRW_PIPE_CONTROL_WRITE_QWORD (1 << 14) +#define BRW_PIPE_CONTROL_WRITE_DEPTH (2 << 14) +#define BRW_PIPE_CONTROL_WRITE_TIME (3 << 14) +#define BRW_PIPE_CONTROL_DEPTH_STALL (1 << 13) +#define BRW_PIPE_CONTROL_WC_FLUSH (1 << 12) +#define BRW_PIPE_CONTROL_IS_FLUSH (1 << 11) +#define BRW_PIPE_CONTROL_NOTIFY_ENABLE (1 << 8) +#define BRW_PIPE_CONTROL_GLOBAL_GTT (1 << 2) +#define BRW_PIPE_CONTROL_LOCAL_PGTT (0 << 2) + +/* VERTEX_BUFFER_STATE Structure */ +#define VB0_BUFFER_INDEX_SHIFT 27 +#define VB0_VERTEXDATA (0 << 26) +#define VB0_INSTANCEDATA (1 << 26) +#define VB0_BUFFER_PITCH_SHIFT 0 + +/* VERTEX_ELEMENT_STATE Structure */ +#define VE0_VERTEX_BUFFER_INDEX_SHIFT 27 +#define VE0_VALID (1 << 26) +#define VE0_FORMAT_SHIFT 16 +#define VE0_OFFSET_SHIFT 0 +#define VE1_VFCOMPONENT_0_SHIFT 28 +#define VE1_VFCOMPONENT_1_SHIFT 24 +#define VE1_VFCOMPONENT_2_SHIFT 20 +#define VE1_VFCOMPONENT_3_SHIFT 16 +#define VE1_DESTINATION_ELEMENT_OFFSET_SHIFT 0 + +/* 3DPRIMITIVE bits */ +#define BRW_3DPRIMITIVE_VERTEX_SEQUENTIAL (0 << 15) +#define BRW_3DPRIMITIVE_VERTEX_RANDOM (1 << 15) +/* Primitive types are in brw_defines.h */ +#define BRW_3DPRIMITIVE_TOPOLOGY_SHIFT 10 + +#define BRW_SVG_CTL 0x7400 + +#define BRW_SVG_CTL_GS_BA (0 << 8) +#define BRW_SVG_CTL_SS_BA (1 << 8) +#define BRW_SVG_CTL_IO_BA (2 << 8) +#define BRW_SVG_CTL_GS_AUB (3 << 8) +#define BRW_SVG_CTL_IO_AUB (4 << 8) +#define BRW_SVG_CTL_SIP (5 << 8) + +#define BRW_SVG_RDATA 0x7404 +#define BRW_SVG_WORK_CTL 0x7408 + +#define BRW_VF_CTL 0x7500 + +#define BRW_VF_CTL_SNAPSHOT_COMPLETE (1 << 31) +#define BRW_VF_CTL_SNAPSHOT_MUX_SELECT_THREADID (0 << 8) +#define BRW_VF_CTL_SNAPSHOT_MUX_SELECT_VF_DEBUG (1 << 8) +#define BRW_VF_CTL_SNAPSHOT_TYPE_VERTEX_SEQUENCE (0 << 4) +#define BRW_VF_CTL_SNAPSHOT_TYPE_VERTEX_INDEX (1 << 4) +#define BRW_VF_CTL_SKIP_INITIAL_PRIMITIVES (1 << 3) +#define BRW_VF_CTL_MAX_PRIMITIVES_LIMIT_ENABLE (1 << 2) +#define BRW_VF_CTL_VERTEX_RANGE_LIMIT_ENABLE (1 << 1) +#define BRW_VF_CTL_SNAPSHOT_ENABLE (1 << 0) + +#define BRW_VF_STRG_VAL 0x7504 +#define BRW_VF_STR_VL_OVR 0x7508 +#define BRW_VF_VC_OVR 0x750c +#define BRW_VF_STR_PSKIP 0x7510 +#define BRW_VF_MAX_PRIM 0x7514 +#define BRW_VF_RDATA 0x7518 + +#define BRW_VS_CTL 0x7600 +#define BRW_VS_CTL_SNAPSHOT_COMPLETE (1 << 31) +#define BRW_VS_CTL_SNAPSHOT_MUX_VERTEX_0 (0 << 8) +#define BRW_VS_CTL_SNAPSHOT_MUX_VERTEX_1 (1 << 8) +#define BRW_VS_CTL_SNAPSHOT_MUX_VALID_COUNT (2 << 8) +#define BRW_VS_CTL_SNAPSHOT_MUX_VS_KERNEL_POINTER (3 << 8) +#define BRW_VS_CTL_SNAPSHOT_ALL_THREADS (1 << 2) +#define BRW_VS_CTL_THREAD_SNAPSHOT_ENABLE (1 << 1) +#define BRW_VS_CTL_SNAPSHOT_ENABLE (1 << 0) + +#define BRW_VS_STRG_VAL 0x7604 +#define BRW_VS_RDATA 0x7608 + +#define BRW_SF_CTL 0x7b00 +#define BRW_SF_CTL_SNAPSHOT_COMPLETE (1 << 31) +#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_0_FF_ID (0 << 8) +#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_0_REL_COUNT (1 << 8) +#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_1_FF_ID (2 << 8) +#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_1_REL_COUNT (3 << 8) +#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_2_FF_ID (4 << 8) +#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_2_REL_COUNT (5 << 8) +#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_COUNT (6 << 8) +#define BRW_SF_CTL_SNAPSHOT_MUX_SF_KERNEL_POINTER (7 << 8) +#define BRW_SF_CTL_MIN_MAX_PRIMITIVE_RANGE_ENABLE (1 << 4) +#define BRW_SF_CTL_DEBUG_CLIP_RECTANGLE_ENABLE (1 << 3) +#define BRW_SF_CTL_SNAPSHOT_ALL_THREADS (1 << 2) +#define BRW_SF_CTL_THREAD_SNAPSHOT_ENABLE (1 << 1) +#define BRW_SF_CTL_SNAPSHOT_ENABLE (1 << 0) + +#define BRW_SF_STRG_VAL 0x7b04 +#define BRW_SF_RDATA 0x7b18 + +#define BRW_WIZ_CTL 0x7c00 +#define BRW_WIZ_CTL_SNAPSHOT_COMPLETE (1 << 31) +#define BRW_WIZ_CTL_SUBSPAN_INSTANCE_SHIFT 16 +#define BRW_WIZ_CTL_SNAPSHOT_MUX_WIZ_KERNEL_POINTER (0 << 8) +#define BRW_WIZ_CTL_SNAPSHOT_MUX_SUBSPAN_INSTANCE (1 << 8) +#define BRW_WIZ_CTL_SNAPSHOT_MUX_PRIMITIVE_SEQUENCE (2 << 8) +#define BRW_WIZ_CTL_SINGLE_SUBSPAN_DISPATCH (1 << 6) +#define BRW_WIZ_CTL_IGNORE_COLOR_SCOREBOARD_STALLS (1 << 5) +#define BRW_WIZ_CTL_ENABLE_SUBSPAN_INSTANCE_COMPARE (1 << 4) +#define BRW_WIZ_CTL_USE_UPSTREAM_SNAPSHOT_FLAG (1 << 3) +#define BRW_WIZ_CTL_SNAPSHOT_ALL_THREADS (1 << 2) +#define BRW_WIZ_CTL_THREAD_SNAPSHOT_ENABLE (1 << 1) +#define BRW_WIZ_CTL_SNAPSHOT_ENABLE (1 << 0) + +#define BRW_WIZ_STRG_VAL 0x7c04 +#define BRW_WIZ_RDATA 0x7c18 + +#define BRW_TS_CTL 0x7e00 +#define BRW_TS_CTL_SNAPSHOT_COMPLETE (1 << 31) +#define BRW_TS_CTL_SNAPSHOT_MESSAGE_ERROR (0 << 8) +#define BRW_TS_CTL_SNAPSHOT_INTERFACE_DESCRIPTOR (3 << 8) +#define BRW_TS_CTL_SNAPSHOT_ALL_CHILD_THREADS (1 << 2) +#define BRW_TS_CTL_SNAPSHOT_ALL_ROOT_THREADS (1 << 1) +#define BRW_TS_CTL_SNAPSHOT_ENABLE (1 << 0) + +#define BRW_TS_STRG_VAL 0x7e04 +#define BRW_TS_RDATA 0x7e08 + +#define BRW_TD_CTL 0x8000 +#define BRW_TD_CTL_MUX_SHIFT 8 +#define BRW_TD_CTL_EXTERNAL_HALT_R0_DEBUG_MATCH (1 << 7) +#define BRW_TD_CTL_FORCE_EXTERNAL_HALT (1 << 6) +#define BRW_TD_CTL_EXCEPTION_MASK_OVERRIDE (1 << 5) +#define BRW_TD_CTL_FORCE_THREAD_BREAKPOINT_ENABLE (1 << 4) +#define BRW_TD_CTL_BREAKPOINT_ENABLE (1 << 2) +#define BRW_TD_CTL2 0x8004 +#define BRW_TD_CTL2_ILLEGAL_OPCODE_EXCEPTION_OVERRIDE (1 << 28) +#define BRW_TD_CTL2_MASKSTACK_EXCEPTION_OVERRIDE (1 << 26) +#define BRW_TD_CTL2_SOFTWARE_EXCEPTION_OVERRIDE (1 << 25) +#define BRW_TD_CTL2_ACTIVE_THREAD_LIMIT_SHIFT 16 +#define BRW_TD_CTL2_ACTIVE_THREAD_LIMIT_ENABLE (1 << 8) +#define BRW_TD_CTL2_THREAD_SPAWNER_EXECUTION_MASK_ENABLE (1 << 7) +#define BRW_TD_CTL2_WIZ_EXECUTION_MASK_ENABLE (1 << 6) +#define BRW_TD_CTL2_SF_EXECUTION_MASK_ENABLE (1 << 5) +#define BRW_TD_CTL2_CLIPPER_EXECUTION_MASK_ENABLE (1 << 4) +#define BRW_TD_CTL2_GS_EXECUTION_MASK_ENABLE (1 << 3) +#define BRW_TD_CTL2_VS_EXECUTION_MASK_ENABLE (1 << 0) +#define BRW_TD_VF_VS_EMSK 0x8008 +#define BRW_TD_GS_EMSK 0x800c +#define BRW_TD_CLIP_EMSK 0x8010 +#define BRW_TD_SF_EMSK 0x8014 +#define BRW_TD_WIZ_EMSK 0x8018 +#define BRW_TD_0_6_EHTRG_VAL 0x801c +#define BRW_TD_0_7_EHTRG_VAL 0x8020 +#define BRW_TD_0_6_EHTRG_MSK 0x8024 +#define BRW_TD_0_7_EHTRG_MSK 0x8028 +#define BRW_TD_RDATA 0x802c +#define BRW_TD_TS_EMSK 0x8030 + +#define BRW_EU_CTL 0x8800 +#define BRW_EU_CTL_SELECT_SHIFT 16 +#define BRW_EU_CTL_DATA_MUX_SHIFT 8 +#define BRW_EU_ATT_0 0x8810 +#define BRW_EU_ATT_1 0x8814 +#define BRW_EU_ATT_DATA_0 0x8820 +#define BRW_EU_ATT_DATA_1 0x8824 +#define BRW_EU_ATT_CLR_0 0x8830 +#define BRW_EU_ATT_CLR_1 0x8834 +#define BRW_EU_RDATA 0x8840 + +/* End regs for broadwater */ + +#define MAX_DISPLAY_PIPES 2 + +typedef enum { + CrtIndex = 0, + TvIndex, + DfpIndex, + LfpIndex, + Crt2Index, + Tv2Index, + Dfp2Index, + Lfp2Index, + NumDisplayTypes +} DisplayType; + +/* What's connected to the pipes (as reported by the BIOS) */ +#define PIPE_ACTIVE_MASK 0xff +#define PIPE_CRT_ACTIVE (1 << CrtIndex) +#define PIPE_TV_ACTIVE (1 << TvIndex) +#define PIPE_DFP_ACTIVE (1 << DfpIndex) +#define PIPE_LCD_ACTIVE (1 << LfpIndex) +#define PIPE_CRT2_ACTIVE (1 << Crt2Index) +#define PIPE_TV2_ACTIVE (1 << Tv2Index) +#define PIPE_DFP2_ACTIVE (1 << Dfp2Index) +#define PIPE_LCD2_ACTIVE (1 << Lfp2Index) + +#define PIPE_SIZED_DISP_MASK (PIPE_DFP_ACTIVE | \ + PIPE_LCD_ACTIVE | \ + PIPE_DFP2_ACTIVE) + +#define PIPE_A_SHIFT 0 +#define PIPE_B_SHIFT 8 +#define PIPE_SHIFT(n) ((n) == 0 ? \ + PIPE_A_SHIFT : PIPE_B_SHIFT) + +/* + * Some BIOS scratch area registers. The 845 (and 830?) store the amount + * of video memory available to the BIOS in SWF1. + */ + +#define SWF0 0x71410 +#define SWF1 0x71414 +#define SWF2 0x71418 +#define SWF3 0x7141c +#define SWF4 0x71420 +#define SWF5 0x71424 +#define SWF6 0x71428 + +/* + * 855 scratch registers. + */ +#define SWF00 0x70410 +#define SWF01 0x70414 +#define SWF02 0x70418 +#define SWF03 0x7041c +#define SWF04 0x70420 +#define SWF05 0x70424 +#define SWF06 0x70428 + +#define SWF10 SWF0 +#define SWF11 SWF1 +#define SWF12 SWF2 +#define SWF13 SWF3 +#define SWF14 SWF4 +#define SWF15 SWF5 +#define SWF16 SWF6 + +#define SWF30 0x72414 +#define SWF31 0x72418 +#define SWF32 0x7241c + +/* + * Overlay registers. These are overlay registers accessed via MMIO. + * Those loaded via the overlay register page are defined in i830_video.c. + */ +#define OVADD 0x30000 + +#define DOVSTA 0x30008 +#define OC_BUF (0x3<<20) + +#define OGAMC5 0x30010 +#define OGAMC4 0x30014 +#define OGAMC3 0x30018 +#define OGAMC2 0x3001c +#define OGAMC1 0x30020 +#define OGAMC0 0x30024 + + +/* + * Palette registers + */ +#define PALETTE_A 0x0a000 +#define PALETTE_B 0x0a800 + +/* Framebuffer compression */ +#define FBC_CFB_BASE 0x03200 /* 4k page aligned */ +#define FBC_LL_BASE 0x03204 /* 4k page aligned */ +#define FBC_CONTROL 0x03208 +#define FBC_CTL_EN (1<<31) +#define FBC_CTL_PERIODIC (1<<30) +#define FBC_CTL_INTERVAL_SHIFT (16) +#define FBC_CTL_UNCOMPRESSIBLE (1<<14) +#define FBC_CTL_STRIDE_SHIFT (5) +#define FBC_CTL_FENCENO (1<<0) +#define FBC_COMMAND 0x0320c +#define FBC_CMD_COMPRESS (1<<0) +#define FBC_STATUS 0x03210 +#define FBC_STAT_COMPRESSING (1<<31) +#define FBC_STAT_COMPRESSED (1<<30) +#define FBC_STAT_MODIFIED (1<<29) +#define FBC_STAT_CURRENT_LINE (1<<0) +#define FBC_CONTROL2 0x03214 +#define FBC_CTL_FENCE_DBL (0<<4) +#define FBC_CTL_IDLE_IMM (0<<2) +#define FBC_CTL_IDLE_FULL (1<<2) +#define FBC_CTL_IDLE_LINE (2<<2) +#define FBC_CTL_IDLE_DEBUG (3<<2) +#define FBC_CTL_CPU_FENCE (1<<1) +#define FBC_CTL_PLANEA (0<<0) +#define FBC_CTL_PLANEB (1<<0) +#define FBC_FENCE_OFF 0x0321b +#define FBC_MOD_NUM 0x03220 +#define FBC_TAG_DEBUG 0x03300 + +#define FBC_LL_SIZE (1536) +#define FBC_LL_PAD (32) + +/* Framebuffer compression version 2 */ +#define DPFC_CB_BASE 0x3200 +#define DPFC_CONTROL 0x3208 +#define DPFC_CTL_EN (1<<31) +#define DPFC_CTL_PLANEA (0<<30) +#define DPFC_CTL_PLANEB (1<<30) +#define DPFC_CTL_FENCE_EN (1<<29) +#define DPFC_CTL_LIMIT_1X (0<<6) +#define DPFC_CTL_LIMIT_2X (1<<6) +#define DPFC_CTL_LIMIT_4X (2<<6) +#define DPFC_RECOMP_CTL 0x320c +#define DPFC_RECOMP_STALL_EN (1<<27) +#define DPFC_RECOMP_STALL_WM_SHIFT (16) +#define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000) +#define DPFC_RECOMP_TIMER_COUNT_SHIFT (0) +#define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f) +#define DPFC_STATUS 0x3210 +#define DPFC_INVAL_SEG_SHIFT (16) +#define DPFC_INVAL_SEG_MASK (0x07ff0000) +#define DPFC_COMP_SEG_SHIFT (0) +#define DPFC_COMP_SEG_MASK (0x000003ff) +#define DPFC_STATUS2 0x3214 +#define DPFC_FENCE_YOFF 0x3218 + +#define PEG_BAND_GAP_DATA 0x14d68 + +#define MCHBAR_RENDER_STANDBY 0x111B8 +#define RENDER_STANDBY_ENABLE (1 << 30) + +/* IGDNG */ + +/* warmup time in us */ +#define WARMUP_PCH_REF_CLK_SSC_MOD 1 +#define WARMUP_PCH_FDI_RECEIVER_PLL 25 +#define WARMUP_PCH_DPLL 50 +#define WARMUP_CPU_DP_PLL 20 +#define WARMUP_CPU_FDI_TRANSMITTER_PLL 10 +#define WARMUP_DMI_LATENCY 20 +#define FDI_TRAIN_PATTERN_1_TIME 0.5 +#define FDI_TRAIN_PATTERN_2_TIME 1.5 +#define FDI_ONE_IDLE_PATTERN_TIME 31 + +#define CPU_VGACNTRL 0x41000 + +#define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030 +#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) +#define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2) +#define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2) +#define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2) +#define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2) +#define DIGITAL_PORTA_NO_DETECT (0 << 0) +#define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1) +#define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0) + +/* refresh rate hardware control */ +#define RR_HW_CTL 0x45300 +#define RR_HW_LOW_POWER_FRAMES_MASK 0xff +#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 + +#define FDI_PLL_BIOS_0 0x46000 +#define FDI_PLL_BIOS_1 0x46004 +#define FDI_PLL_BIOS_2 0x46008 +#define DISPLAY_PORT_PLL_BIOS_0 0x4600c +#define DISPLAY_PORT_PLL_BIOS_1 0x46010 +#define DISPLAY_PORT_PLL_BIOS_2 0x46014 + +#define FDI_PLL_FREQ_CTL 0x46030 +#define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24) +#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 +#define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff + +#define PIPEA_DATA_M1 0x60030 +#define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */ +#define TU_SIZE_MASK 0x7e000000 +#define PIPEA_DATA_M1_OFFSET 0 +#define PIPEA_DATA_N1 0x60034 +#define PIPEA_DATA_N1_OFFSET 0 + +#define PIPEA_DATA_M2 0x60038 +#define PIPEA_DATA_M2_OFFSET 0 +#define PIPEA_DATA_N2 0x6003c +#define PIPEA_DATA_N2_OFFSET 0 + +#define PIPEA_LINK_M1 0x60040 +#define PIPEA_LINK_M1_OFFSET 0 +#define PIPEA_LINK_N1 0x60044 +#define PIPEA_LINK_N1_OFFSET 0 + +#define PIPEA_LINK_M2 0x60048 +#define PIPEA_LINK_M2_OFFSET 0 +#define PIPEA_LINK_N2 0x6004c +#define PIPEA_LINK_N2_OFFSET 0 + +/* PIPEB timing regs are same start from 0x61000 */ + +#define PIPEB_DATA_M1 0x61030 +#define PIPEB_DATA_M1_OFFSET 0 +#define PIPEB_DATA_N1 0x61034 +#define PIPEB_DATA_N1_OFFSET 0 + +#define PIPEB_DATA_M2 0x61038 +#define PIPEB_DATA_M2_OFFSET 0 +#define PIPEB_DATA_N2 0x6103c +#define PIPEB_DATA_N2_OFFSET 0 + +#define PIPEB_LINK_M1 0x61040 +#define PIPEB_LINK_M1_OFFSET 0 +#define PIPEB_LINK_N1 0x61044 +#define PIPEB_LINK_N1_OFFSET 0 + +#define PIPEB_LINK_M2 0x61048 +#define PIPEB_LINK_M2_OFFSET 0 +#define PIPEB_LINK_N2 0x6104c +#define PIPEB_LINK_N2_OFFSET 0 + +/* PIPECONF for pipe A/B addr is same */ + +/* cusor A is only connected to pipe A, + cursor B is connected to pipe B. Otherwise no change. */ + +/* Plane A/B, DSPACNTR/DSPBCNTR addr not changed */ + +/* CPU panel fitter */ +#define PFA_CTL_1 0x68080 +#define PFB_CTL_1 0x68880 +#define PF_ENABLE (1<<31) +#define PFA_WIN_SZ 0x68074 +#define PFB_WIN_SZ 0x68874 +#define PFA_WIN_POS 0x68070 +#define PFB_WIN_POS 0x68870 + +#define PFA_WIN_POS 0x68070 +#define PFB_WIN_POS 0x68870 +#define PFA_WIN_SIZE 0x68074 +#define PFB_WIN_SIZE 0x68874 + +/* legacy palette */ +#define LGC_PALETTE_A 0x4a000 +#define LGC_PALETTE_B 0x4a800 + +/* interrupts */ +#define DE_MASTER_IRQ_CONTROL (1 << 31) +#define DE_SPRITEB_FLIP_DONE (1 << 29) +#define DE_SPRITEA_FLIP_DONE (1 << 28) +#define DE_PLANEB_FLIP_DONE (1 << 27) +#define DE_PLANEA_FLIP_DONE (1 << 26) +#define DE_PCU_EVENT (1 << 25) +#define DE_GTT_FAULT (1 << 24) +#define DE_POISON (1 << 23) +#define DE_PERFORM_COUNTER (1 << 22) +#define DE_PCH_EVENT (1 << 21) +#define DE_AUX_CHANNEL_A (1 << 20) +#define DE_DP_A_HOTPLUG (1 << 19) +#define DE_GSE (1 << 18) +#define DE_PIPEB_VBLANK (1 << 15) +#define DE_PIPEB_EVEN_FIELD (1 << 14) +#define DE_PIPEB_ODD_FIELD (1 << 13) +#define DE_PIPEB_LINE_COMPARE (1 << 12) +#define DE_PIPEB_VSYNC (1 << 11) +#define DE_PIPEB_FIFO_UNDERRUN (1 << 8) +#define DE_PIPEA_VBLANK (1 << 7) +#define DE_PIPEA_EVEN_FIELD (1 << 6) +#define DE_PIPEA_ODD_FIELD (1 << 5) +#define DE_PIPEA_LINE_COMPARE (1 << 4) +#define DE_PIPEA_VSYNC (1 << 3) +#define DE_PIPEA_FIFO_UNDERRUN (1 << 0) + +#define DEISR 0x44000 +#define DEIMR 0x44004 +#define DEIIR 0x44008 +#define DEIER 0x4400c + +/* GT interrupt */ +#define GT_SYNC_STATUS (1 << 2) +#define GT_USER_INTERRUPT (1 << 0) + +#define GTISR 0x44010 +#define GTIMR 0x44014 +#define GTIIR 0x44018 +#define GTIER 0x4401c + + +#define DISP_ARB_CTL 0x45000 +#define DISP_TILE_SURFACE_SWIZZLING (1<<13) + +/* PCH */ + +/* south display engine interrupt */ +#define SDE_CRT_HOTPLUG (1 << 11) +#define SDE_PORTD_HOTPLUG (1 << 10) +#define SDE_PORTC_HOTPLUG (1 << 9) +#define SDE_PORTB_HOTPLUG (1 << 8) +#define SDE_SDVOB_HOTPLUG (1 << 6) + +#define SDEISR 0xc4000 +#define SDEIMR 0xc4004 +#define SDEIIR 0xc4008 +#define SDEIER 0xc400c + +/* digital port hotplug */ +#define PCH_PORT_HOTPLUG 0xc4030 +#define PORTD_HOTPLUG_ENABLE (1 << 20) +#define PORTD_PULSE_DURATION_2ms (0) +#define PORTD_PULSE_DURATION_4_5ms (1 << 18) +#define PORTD_PULSE_DURATION_6ms (2 << 18) +#define PORTD_PULSE_DURATION_100ms (3 << 18) +#define PORTD_HOTPLUG_NO_DETECT (0) +#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) +#define PORTD_HOTPLUG_LONG_DETECT (1 << 17) +#define PORTC_HOTPLUG_ENABLE (1 << 12) +#define PORTC_PULSE_DURATION_2ms (0) +#define PORTC_PULSE_DURATION_4_5ms (1 << 10) +#define PORTC_PULSE_DURATION_6ms (2 << 10) +#define PORTC_PULSE_DURATION_100ms (3 << 10) +#define PORTC_HOTPLUG_NO_DETECT (0) +#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) +#define PORTC_HOTPLUG_LONG_DETECT (1 << 9) +#define PORTB_HOTPLUG_ENABLE (1 << 4) +#define PORTB_PULSE_DURATION_2ms (0) +#define PORTB_PULSE_DURATION_4_5ms (1 << 2) +#define PORTB_PULSE_DURATION_6ms (2 << 2) +#define PORTB_PULSE_DURATION_100ms (3 << 2) +#define PORTB_HOTPLUG_NO_DETECT (0) +#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) +#define PORTB_HOTPLUG_LONG_DETECT (1 << 1) + +#define PCH_GPIOA 0xc5010 +#define PCH_GPIOB 0xc5014 +#define PCH_GPIOC 0xc5018 +#define PCH_GPIOD 0xc501c +#define PCH_GPIOE 0xc5020 +#define PCH_GPIOF 0xc5024 +#define PCH_GMBUS0 0xc5100 +#define PCH_GMBUS1 0xc5104 +#define PCH_GMBUS2 0xc5108 +#define PCH_GMBUS3 0xc510c +#define PCH_GMBUS4 0xc5110 +#define PCH_GMBUS5 0xc5120 + +#define PCH_DPLL_A 0xc6014 +#define PCH_DPLL_B 0xc6018 + +#define PCH_FPA0 0xc6040 +#define PCH_FPA1 0xc6044 +#define PCH_FPB0 0xc6048 +#define PCH_FPB1 0xc604c + +#define PCH_DPLL_TEST 0xc606c + +#define PCH_DREF_CONTROL 0xC6200 +#define DREF_CONTROL_MASK 0x7fc3 +#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13) +#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13) +#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13) +#define DREF_SSC_SOURCE_DISABLE (0<<11) +#define DREF_SSC_SOURCE_ENABLE (2<<11) +#define DREF_SSC_SOURCE_MASK (2<<11) +#define DREF_NONSPREAD_SOURCE_DISABLE (0<<9) +#define DREF_NONSPREAD_CK505_ENABLE (1<<9) +#define DREF_NONSPREAD_SOURCE_ENABLE (2<<9) +#define DREF_NONSPREAD_SOURCE_MASK (2<<9) +#define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7) +#define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7) +#define DREF_SSC4_DOWNSPREAD (0<<6) +#define DREF_SSC4_CENTERSPREAD (1<<6) +#define DREF_SSC1_DISABLE (0<<1) +#define DREF_SSC1_ENABLE (1<<1) +#define DREF_SSC4_DISABLE (0) +#define DREF_SSC4_ENABLE (1) + +#define PCH_RAWCLK_FREQ 0xc6204 +#define FDL_TP1_TIMER_SHIFT 12 +#define FDL_TP1_TIMER_MASK (3<<12) +#define FDL_TP2_TIMER_SHIFT 10 +#define FDL_TP2_TIMER_MASK (3<<10) +#define RAWCLK_FREQ_MASK 0x3ff + +#define PCH_DPLL_TMR_CFG 0xc6208 + +#define PCH_SSC4_PARMS 0xc6210 +#define PCH_SSC4_AUX_PARMS 0xc6214 + +/* transcoder */ + +#define TRANS_HTOTAL_A 0xe0000 +#define TRANS_HTOTAL_SHIFT 16 +#define TRANS_HACTIVE_SHIFT 0 +#define TRANS_HBLANK_A 0xe0004 +#define TRANS_HBLANK_END_SHIFT 16 +#define TRANS_HBLANK_START_SHIFT 0 +#define TRANS_HSYNC_A 0xe0008 +#define TRANS_HSYNC_END_SHIFT 16 +#define TRANS_HSYNC_START_SHIFT 0 +#define TRANS_VTOTAL_A 0xe000c +#define TRANS_VTOTAL_SHIFT 16 +#define TRANS_VACTIVE_SHIFT 0 +#define TRANS_VBLANK_A 0xe0010 +#define TRANS_VBLANK_END_SHIFT 16 +#define TRANS_VBLANK_START_SHIFT 0 +#define TRANS_VSYNC_A 0xe0014 +#define TRANS_VSYNC_END_SHIFT 16 +#define TRANS_VSYNC_START_SHIFT 0 + +#define TRANSA_DATA_M1 0xe0030 +#define TRANSA_DATA_N1 0xe0034 +#define TRANSA_DATA_M2 0xe0038 +#define TRANSA_DATA_N2 0xe003c +#define TRANSA_DP_LINK_M1 0xe0040 +#define TRANSA_DP_LINK_N1 0xe0044 +#define TRANSA_DP_LINK_M2 0xe0048 +#define TRANSA_DP_LINK_N2 0xe004c + +#define TRANS_HTOTAL_B 0xe1000 +#define TRANS_HBLANK_B 0xe1004 +#define TRANS_HSYNC_B 0xe1008 +#define TRANS_VTOTAL_B 0xe100c +#define TRANS_VBLANK_B 0xe1010 +#define TRANS_VSYNC_B 0xe1014 + +#define TRANSB_DATA_M1 0xe1030 +#define TRANSB_DATA_N1 0xe1034 +#define TRANSB_DATA_M2 0xe1038 +#define TRANSB_DATA_N2 0xe103c +#define TRANSB_DP_LINK_M1 0xe1040 +#define TRANSB_DP_LINK_N1 0xe1044 +#define TRANSB_DP_LINK_M2 0xe1048 +#define TRANSB_DP_LINK_N2 0xe104c + +#define TRANSACONF 0xf0008 +#define TRANSBCONF 0xf1008 +#define TRANS_DISABLE (0<<31) +#define TRANS_ENABLE (1<<31) +#define TRANS_STATE_MASK (1<<30) +#define TRANS_STATE_DISABLE (0<<30) +#define TRANS_STATE_ENABLE (1<<30) +#define TRANS_FSYNC_DELAY_HB1 (0<<27) +#define TRANS_FSYNC_DELAY_HB2 (1<<27) +#define TRANS_FSYNC_DELAY_HB3 (2<<27) +#define TRANS_FSYNC_DELAY_HB4 (3<<27) +#define TRANS_DP_AUDIO_ONLY (1<<26) +#define TRANS_DP_VIDEO_AUDIO (0<<26) +#define TRANS_PROGRESSIVE (0<<21) +#define TRANS_8BPC (0<<5) +#define TRANS_10BPC (1<<5) +#define TRANS_6BPC (2<<5) +#define TRANS_12BPC (3<<5) + +#define FDI_RXA_CHICKEN 0xc200c +#define FDI_RXB_CHICKEN 0xc2010 +#define FDI_RX_PHASE_SYNC_POINTER_ENABLE (1) + +/* CPU: FDI_TX */ +#define FDI_TXA_CTL 0x60100 +#define FDI_TXB_CTL 0x61100 +#define FDI_TX_DISABLE (0<<31) +#define FDI_TX_ENABLE (1<<31) +#define FDI_LINK_TRAIN_PATTERN_1 (0<<28) +#define FDI_LINK_TRAIN_PATTERN_2 (1<<28) +#define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28) +#define FDI_LINK_TRAIN_NONE (3<<28) +#define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25) +#define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25) +#define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25) +#define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25) +#define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22) +#define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22) +#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22) +#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22) +#define FDI_DP_PORT_WIDTH_X1 (0<<19) +#define FDI_DP_PORT_WIDTH_X2 (1<<19) +#define FDI_DP_PORT_WIDTH_X3 (2<<19) +#define FDI_DP_PORT_WIDTH_X4 (3<<19) +#define FDI_DP_PORT_WIDTH_MASK (7<<19) +#define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18) +/* IGDNG: hardwired to 1 */ +#define FDI_TX_PLL_ENABLE (1<<14) +/* both Tx and Rx */ +#define FDI_SCRAMBLING_ENABLE (0<<7) +#define FDI_SCRAMBLING_DISABLE (1<<7) + +/* FDI_RX, FDI_X is hard-wired to Transcoder_X */ +#define FDI_RXA_CTL 0xf000c +#define FDI_RXB_CTL 0xf100c +#define FDI_RX_ENABLE (1<<31) +#define FDI_RX_DISABLE (0<<31) +/* train, dp width same as FDI_TX */ +#define FDI_DP_PORT_WIDTH_X8 (7<<19) +#define FDI_8BPC (0<<16) +#define FDI_10BPC (1<<16) +#define FDI_6BPC (2<<16) +#define FDI_12BPC (3<<16) +#define FDI_BPC_MASK (3<<16) +#define FDI_LINK_REVERSE_OVERWRITE (1<<15) +#define FDI_DMI_LINK_REVERSE_MASK (1<<14) +#define FDI_RX_PLL_ENABLE (1<<13) +#define FDI_FS_ERR_CORRECT_ENABLE (1<<11) +#define FDI_FE_ERR_CORRECT_ENABLE (1<<10) +#define FDI_FS_ERR_REPORT_ENABLE (1<<9) +#define FDI_FE_ERR_REPORT_ENABLE (1<<8) +#define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6) +#define FDI_SEL_RAWCLK (0<<4) +#define FDI_SEL_PCDCLK (1<<4) + +#define FDI_RXA_MISC 0xf0010 +#define FDI_RXB_MISC 0xf1010 +#define FDI_RXA_TUSIZE1 0xf0030 +#define FDI_RXA_TUSIZE2 0xf0038 +#define FDI_RXB_TUSIZE1 0xf1030 +#define FDI_RXB_TUSIZE2 0xf1038 + +/* FDI_RX interrupt register format */ +#define FDI_RX_INTER_LANE_ALIGN (1<<10) +#define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */ +#define FDI_RX_BIT_LOCK (1<<8) /* train 1 */ +#define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7) +#define FDI_RX_FS_CODE_ERR (1<<6) +#define FDI_RX_FE_CODE_ERR (1<<5) +#define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4) +#define FDI_RX_HDCP_LINK_FAIL (1<<3) +#define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2) +#define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1) +#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0) + +#define FDI_RXA_IIR 0xf0014 +#define FDI_RXA_IMR 0xf0018 +#define FDI_RXB_IIR 0xf1014 +#define FDI_RXB_IMR 0xf1018 + +#define FDI_PLL_CTL_1 0xfe000 +#define FDI_PLL_CTL_2 0xfe004 + +/* CRT */ +#define PCH_ADPA 0xe1100 +#define ADPA_TRANS_SELECT_MASK (1<<30) +#define ADPA_TRANS_A_SELECT 0 +#define ADPA_TRANS_B_SELECT (1<<30) +/* HPD is here */ +#define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ +#define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24) +#define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24) +#define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24) +#define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24) +#define ADPA_CRT_HOTPLUG_ENABLE (1<<23) +#define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22) +#define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22) +#define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21) +#define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21) +#define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20) +#define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20) +#define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18) +#define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18) +#define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18) +#define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18) +#define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17) +#define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17) +#define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16) +/* polarity control not changed */ + +/* or SDVOB */ +#define HDMIB 0xe1140 +#define PORT_ENABLE (1 << 31) +#define TRANSCODER_A (0) +#define TRANSCODER_B (1 << 30) +#define COLOR_FORMAT_8bpc (0) +#define COLOR_FORMAT_12bpc (3 << 26) +#define SDVOB_HOTPLUG_ENABLE (1 << 23) +#define SDVO_ENCODING (0) +#define TMDS_ENCODING (2 << 10) +#define NULL_PACKET_VSYNC_ENABLE (1 << 9) +#define SDVOB_BORDER_ENABLE (1 << 7) +#define AUDIO_ENABLE (1 << 6) +#define VSYNC_ACTIVE_HIGH (1 << 4) +#define HSYNC_ACTIVE_HIGH (1 << 3) +#define PORT_DETECTED (1 << 2) + +#define HDMIC 0xe1150 +#define HDMID 0xe1160 +#define PCH_LVDS 0xe1180 +#define LVDS_DETECTED (1 << 1) + +#define PCH_DP_B 0xe4100 +#define PCH_DP_C 0xe4200 +#define PCH_DP_D 0xe4200 + +#define BLC_PWM_CPU_CTL2 0x48250 +#define PWM_ENABLE (1 << 31) +#define PWM_PIPE_A (0 << 29) +#define PWM_PIPE_B (1 << 29) +#define BLC_PWM_CPU_CTL 0x48254 + +#define BLC_PWM_PCH_CTL1 0xc8250 +#define PWM_PCH_ENABLE (1 << 31) +#define PWM_POLARITY_ACTIVE_LOW (1 << 29) +#define PWM_POLARITY_ACTIVE_HIGH (0 << 29) +#define PWM_POLARITY_ACTIVE_LOW2 (1 << 28) +#define PWM_POLARITY_ACTIVE_HIGH2 (0 << 28) + +#define BLC_PWM_PCH_CTL2 0xc8254 + +#define PCH_PP_STATUS 0xc7200 +#define PCH_PP_CONTROL 0xc7204 +#define EDP_FORCE_VDD (1 << 3) +#define EDP_BLC_ENABLE (1 << 2) +#define PANEL_POWER_RESET (1 << 1) +#define PANEL_POWER_OFF (0 << 0) +#define PANEL_POWER_ON (1 << 0) +#define PCH_PP_ON_DELAYS 0xc7208 +#define EDP_PANEL (1 << 30) +#define PCH_PP_OFF_DELAYS 0xc720c +#define PCH_PP_DIVISOR 0xc7210 + +#define DE_POWER1 0x42400 +#define WM0_PIPE_A 0x45100 +#define WM0_PIPE_B 0x45104 +#define WM1 0x45108 +#define WM2 0x4510C +#define WM3 0x45110 +#define WM1S 0x45120 + + + +#define AUD_CONFIG 0x62000 +#define AUD_DEBUG 0x62010 +#define AUD_VID_DID 0x62020 +#define AUD_RID 0x62024 +#define AUD_SUBN_CNT 0x62028 +#define AUD_FUNC_GRP 0x62040 +#define AUD_SUBN_CNT2 0x62044 +#define AUD_GRP_CAP 0x62048 +#define AUD_PWRST 0x6204c +#define AUD_SUPPWR 0x62050 +#define AUD_SID 0x62054 +#define AUD_OUT_CWCAP 0x62070 +#define AUD_OUT_PCMSIZE 0x62074 +#define AUD_OUT_STR 0x62078 +#define AUD_OUT_DIG_CNVT 0x6207c +#define AUD_OUT_CH_STR 0x62080 +#define AUD_OUT_STR_DESC 0x62084 +#define AUD_PINW_CAP 0x620a0 +#define AUD_PIN_CAP 0x620a4 +#define AUD_PINW_CONNLNG 0x620a8 +#define AUD_PINW_CONNLST 0x620ac +#define AUD_PINW_CNTR 0x620b0 +#define AUD_PINW_UNSOLRESP 0x620b8 +#define AUD_CNTL_ST 0x620b4 +#define AUD_PINW_CONFIG 0x620bc +#define AUD_HDMIW_STATUS 0x620d4 +#define AUD_HDMIW_HDMIEDID 0x6210c +#define AUD_HDMIW_INFOFR 0x62118 +#define AUD_CONV_CHCNT 0x62120 +#define AUD_CTS_ENABLE 0x62128 + +#define VIDEO_DIP_CTL 0x61170 + #endif diff --git a/driver/xf86-video-intel/src/i830_render.c b/driver/xf86-video-intel/src/i830_render.c index 43f4e28b9..37f2efa88 100644 --- a/driver/xf86-video-intel/src/i830_render.c +++ b/driver/xf86-video-intel/src/i830_render.c @@ -31,7 +31,7 @@ #endif #include "xf86.h" -#include "i830.h" +#include "intel.h" #include "i830_reg.h" struct blendinfo { @@ -231,7 +231,7 @@ static uint32_t i8xx_get_card_format(intel_screen_private *intel, return i830_tex_formats[i].card_fmt; } - if (IS_I85X(intel) || IS_I865G(intel)) { + if (!(IS_I830(intel) || IS_845G(intel))) { for (i = 0; i < sizeof(i855_tex_formats) / sizeof(i855_tex_formats[0]); i++) { if (i855_tex_formats[i].fmt == picture->format) @@ -251,12 +251,12 @@ static void i830_texture_setup(PicturePtr picture, PixmapPtr pixmap, int unit) uint32_t wrap_mode; uint32_t texcoordtype; - pitch = intel_get_pixmap_pitch(pixmap); + pitch = intel_pixmap_pitch(pixmap); intel->scale_units[unit][0] = pixmap->drawable.width; intel->scale_units[unit][1] = pixmap->drawable.height; intel->transform[unit] = picture->transform; - if (i830_transform_is_affine(intel->transform[unit])) + if (intel_transform_is_affine(intel->transform[unit])) texcoordtype = TEXCOORDTYPE_CARTESIAN; else texcoordtype = TEXCOORDTYPE_HOMOGENEOUS; @@ -293,9 +293,9 @@ static void i830_texture_setup(PicturePtr picture, PixmapPtr pixmap, int unit) } filter |= (MIPFILTER_NONE << TM0S3_MIP_FILTER_SHIFT); - if (i830_pixmap_tiled(pixmap)) { + if (intel_pixmap_tiled(pixmap)) { tiling_bits = TM0S1_TILED_SURFACE; - if (i830_get_pixmap_intel(pixmap)->tiling + if (intel_get_pixmap_private(pixmap)->tiling == I915_TILING_Y) tiling_bits |= TM0S1_TILE_WALK; } else @@ -451,9 +451,9 @@ i830_prepare_composite(int op, PicturePtr source_picture, intel_screen_private *intel = intel_get_screen_private(scrn); drm_intel_bo *bo_table[] = { NULL, /* batch_bo */ - i830_get_pixmap_bo(source), - mask ? i830_get_pixmap_bo(mask) : NULL, - i830_get_pixmap_bo(dest), + intel_get_pixmap_bo(source), + mask ? intel_get_pixmap_bo(mask) : NULL, + intel_get_pixmap_bo(dest), }; intel->render_source_picture = source_picture; @@ -489,7 +489,7 @@ i830_prepare_composite(int op, PicturePtr source_picture, if (!i830_get_dest_format(dest_picture, &intel->render_dest_format)) return FALSE; - if (!i830_get_aperture_space(scrn, bo_table, ARRAY_SIZE(bo_table))) + if (!intel_get_aperture_space(scrn, bo_table, ARRAY_SIZE(bo_table))) return FALSE; if (mask) { @@ -564,8 +564,8 @@ i830_prepare_composite(int op, PicturePtr source_picture, intel->s8_blendctl = blendctl; } - if(i830_uxa_pixmap_is_dirty(source) || - (mask && i830_uxa_pixmap_is_dirty(mask))) + if(intel_pixmap_is_dirty(source) || + (mask && intel_pixmap_is_dirty(mask))) intel_batch_emit_flush(scrn); intel->needs_render_state_emit = TRUE; @@ -586,9 +586,9 @@ static void i830_emit_composite_state(ScrnInfoPtr scrn) assert(intel->in_batch_atomic); - if (i830_pixmap_tiled(intel->render_dest)) { + if (intel_pixmap_tiled(intel->render_dest)) { tiling_bits = BUF_3D_TILED_SURFACE; - if (i830_get_pixmap_intel(intel->render_dest)->tiling + if (intel_get_pixmap_private(intel->render_dest)->tiling == I915_TILING_Y) tiling_bits |= BUF_3D_TILE_WALK_Y; } else @@ -596,7 +596,7 @@ static void i830_emit_composite_state(ScrnInfoPtr scrn) OUT_BATCH(_3DSTATE_BUF_INFO_CMD); OUT_BATCH(BUF_3D_ID_COLOR_BACK | tiling_bits | - BUF_3D_PITCH(intel_get_pixmap_pitch(intel->render_dest))); + BUF_3D_PITCH(intel_pixmap_pitch(intel->render_dest))); OUT_RELOC_PIXMAP(intel->render_dest, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0); @@ -637,12 +637,12 @@ static void i830_emit_composite_state(ScrnInfoPtr scrn) DISABLE_STENCIL_WRITE | ENABLE_TEX_CACHE | DISABLE_DITHER | ENABLE_COLOR_WRITE | DISABLE_DEPTH_WRITE); - if (i830_transform_is_affine(intel->render_source_picture->transform)) + if (intel_transform_is_affine(intel->render_source_picture->transform)) texcoordfmt |= (TEXCOORDFMT_2D << 0); else texcoordfmt |= (TEXCOORDFMT_3D << 0); if (intel->render_mask) { - if (i830_transform_is_affine + if (intel_transform_is_affine (intel->render_mask_picture->transform)) texcoordfmt |= (TEXCOORDFMT_2D << 2); else @@ -670,7 +670,7 @@ i830_emit_composite_primitive(PixmapPtr dest, ScrnInfoPtr scrn = xf86Screens[dest->drawable.pScreen->myNum]; intel_screen_private *intel = intel_get_screen_private(scrn); Bool is_affine_src, is_affine_mask = TRUE; - int per_vertex, num_floats; + int per_vertex; float src_x[3], src_y[3], src_w[3], mask_x[3], mask_y[3], mask_w[3]; per_vertex = 2; /* dest x/y */ @@ -678,23 +678,23 @@ i830_emit_composite_primitive(PixmapPtr dest, { float x = srcX, y = srcY; - is_affine_src = i830_transform_is_affine(intel->transform[0]); + is_affine_src = intel_transform_is_affine(intel->transform[0]); if (is_affine_src) { - if (!i830_get_transformed_coordinates(x, y, + if (!intel_get_transformed_coordinates(x, y, intel-> transform[0], &src_x[0], &src_y[0])) return; - if (!i830_get_transformed_coordinates(x, y + h, + if (!intel_get_transformed_coordinates(x, y + h, intel-> transform[0], &src_x[1], &src_y[1])) return; - if (!i830_get_transformed_coordinates(x + w, y + h, + if (!intel_get_transformed_coordinates(x + w, y + h, intel-> transform[0], &src_x[2], @@ -703,7 +703,7 @@ i830_emit_composite_primitive(PixmapPtr dest, per_vertex += 2; /* src x/y */ } else { - if (!i830_get_transformed_coordinates_3d(x, y, + if (!intel_get_transformed_coordinates_3d(x, y, intel-> transform[0], &src_x[0], @@ -711,7 +711,7 @@ i830_emit_composite_primitive(PixmapPtr dest, &src_w[0])) return; - if (!i830_get_transformed_coordinates_3d(x, y + h, + if (!intel_get_transformed_coordinates_3d(x, y + h, intel-> transform[0], &src_x[1], @@ -719,7 +719,7 @@ i830_emit_composite_primitive(PixmapPtr dest, &src_w[1])) return; - if (!i830_get_transformed_coordinates_3d(x + w, y + h, + if (!intel_get_transformed_coordinates_3d(x + w, y + h, intel-> transform[0], &src_x[2], @@ -734,23 +734,23 @@ i830_emit_composite_primitive(PixmapPtr dest, if (intel->render_mask) { float x = maskX, y = maskY; - is_affine_mask = i830_transform_is_affine(intel->transform[1]); + is_affine_mask = intel_transform_is_affine(intel->transform[1]); if (is_affine_mask) { - if (!i830_get_transformed_coordinates(x, y, + if (!intel_get_transformed_coordinates(x, y, intel-> transform[1], &mask_x[0], &mask_y[0])) return; - if (!i830_get_transformed_coordinates(x, y + h, + if (!intel_get_transformed_coordinates(x, y + h, intel-> transform[1], &mask_x[1], &mask_y[1])) return; - if (!i830_get_transformed_coordinates(x + w, y + h, + if (!intel_get_transformed_coordinates(x + w, y + h, intel-> transform[1], &mask_x[2], @@ -759,7 +759,7 @@ i830_emit_composite_primitive(PixmapPtr dest, per_vertex += 2; /* mask x/y */ } else { - if (!i830_get_transformed_coordinates_3d(x, y, + if (!intel_get_transformed_coordinates_3d(x, y, intel-> transform[1], &mask_x[0], @@ -767,7 +767,7 @@ i830_emit_composite_primitive(PixmapPtr dest, &mask_w[0])) return; - if (!i830_get_transformed_coordinates_3d(x, y + h, + if (!intel_get_transformed_coordinates_3d(x, y + h, intel-> transform[1], &mask_x[1], @@ -775,7 +775,7 @@ i830_emit_composite_primitive(PixmapPtr dest, &mask_w[1])) return; - if (!i830_get_transformed_coordinates_3d(x + w, y + h, + if (!intel_get_transformed_coordinates_3d(x + w, y + h, intel-> transform[1], &mask_x[2], @@ -787,9 +787,10 @@ i830_emit_composite_primitive(PixmapPtr dest, } } - num_floats = 3 * per_vertex; - - OUT_BATCH(PRIM3D_INLINE | PRIM3D_RECTLIST | (num_floats - 1)); + if (intel->vertex_count == 0) { + intel->vertex_index = intel->batch_used; + OUT_BATCH(PRIM3D_INLINE | PRIM3D_RECTLIST); + } OUT_BATCH_F(dstX + w); OUT_BATCH_F(dstY + h); OUT_BATCH_F(src_x[2] / intel->scale_units[0][0]); @@ -834,6 +835,17 @@ i830_emit_composite_primitive(PixmapPtr dest, OUT_BATCH_F(mask_w[0]); } } + + intel->vertex_count += 3 * per_vertex; + +} + +void i830_vertex_flush(intel_screen_private *intel) +{ + if (intel->vertex_count) { + intel->batch_ptr[intel->vertex_index] |= intel->vertex_count - 1; + intel->vertex_count = 0; + } } /** @@ -860,9 +872,7 @@ i830_composite(PixmapPtr dest, int srcX, int srcY, int maskX, int maskY, intel_batch_end_atomic(scrn); } -void i830_batch_flush_notify(ScrnInfoPtr scrn) +void i830_batch_commit_notify(intel_screen_private *intel) { - intel_screen_private *intel = intel_get_screen_private(scrn); - intel->needs_render_state_emit = TRUE; } diff --git a/driver/xf86-video-intel/src/i830_sdvo.c b/driver/xf86-video-intel/src/i830_sdvo.c index a9275afa3..ba272cb63 100644 --- a/driver/xf86-video-intel/src/i830_sdvo.c +++ b/driver/xf86-video-intel/src/i830_sdvo.c @@ -45,9 +45,9 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #include "xf86.h" #include "xf86_OSproc.h" #include "compiler.h" -#include "i830.h" +#include "intel.h" #include "i830_display.h" -#include "i810_reg.h" +#include "i830_reg.h" #include "i830_sdvo_regs.h" #include "X11/Xatom.h" @@ -2041,7 +2041,7 @@ i830_sdvo_get_crtc(xf86OutputPtr output) struct i830_sdvo_priv *dev_priv = intel_output->dev_priv; int pipe = !!(INREG(dev_priv->output_device) & SDVO_PIPE_B_SELECT); - return i830_pipe_to_crtc(scrn, pipe); + return intel_pipe_to_crtc(scrn, pipe); } #endif diff --git a/driver/xf86-video-intel/src/i830_tv.c b/driver/xf86-video-intel/src/i830_tv.c index 71fd7df21..5df44039e 100644 --- a/driver/xf86-video-intel/src/i830_tv.c +++ b/driver/xf86-video-intel/src/i830_tv.c @@ -34,9 +34,10 @@ #endif #include "xf86.h" -#include "i830.h" +#include "intel.h" #include "i830_display.h" #include "i830_bios.h" +#include "i830_reg.h" #include "X11/Xatom.h" #include <string.h> @@ -1907,7 +1908,7 @@ i830_tv_get_crtc(xf86OutputPtr output) intel_screen_private *intel = intel_get_screen_private(scrn); int pipe = !!(INREG(TV_CTL) & TV_ENC_PIPEB_SELECT); - return i830_pipe_to_crtc(scrn, pipe); + return intel_pipe_to_crtc(scrn, pipe); } #endif diff --git a/driver/xf86-video-intel/src/i915_3d.c b/driver/xf86-video-intel/src/i915_3d.c index 906043b16..77db56854 100644 --- a/driver/xf86-video-intel/src/i915_3d.c +++ b/driver/xf86-video-intel/src/i915_3d.c @@ -30,7 +30,7 @@ #endif #include "xf86.h" -#include "i830.h" +#include "intel.h" #include "i915_reg.h" @@ -106,7 +106,5 @@ void I915EmitInvarientState(ScrnInfoPtr scrn) OUT_BATCH(_3DSTATE_STIPPLE); OUT_BATCH(0x00000000); - OUT_BATCH(_3DSTATE_BACKFACE_STENCIL_OPS | BFO_ENABLE_STENCIL_TWO_SIDE | - 0); - OUT_BATCH(MI_NOOP); + OUT_BATCH(_3DSTATE_BACKFACE_STENCIL_OPS | BFO_ENABLE_STENCIL_TWO_SIDE | 0); } diff --git a/driver/xf86-video-intel/src/i915_render.c b/driver/xf86-video-intel/src/i915_render.c index 53c991420..dbaf1968d 100644 --- a/driver/xf86-video-intel/src/i915_render.c +++ b/driver/xf86-video-intel/src/i915_render.c @@ -31,7 +31,7 @@ #endif #include "xf86.h" -#include "i830.h" +#include "intel.h" #include "i915_reg.h" #include "i915_3d.h" @@ -77,16 +77,16 @@ static struct blendinfo i915_blend_op[] = { }; static struct formatinfo i915_tex_formats[] = { + {PICT_a8, MAPSURF_8BIT | MT_8BIT_A8}, {PICT_a8r8g8b8, MAPSURF_32BIT | MT_32BIT_ARGB8888}, {PICT_x8r8g8b8, MAPSURF_32BIT | MT_32BIT_XRGB8888}, {PICT_a8b8g8r8, MAPSURF_32BIT | MT_32BIT_ABGR8888}, {PICT_x8b8g8r8, MAPSURF_32BIT | MT_32BIT_XBGR8888}, + {PICT_a2r10g10b10, MAPSURF_32BIT | MT_32BIT_ARGB2101010}, + {PICT_a2b10g10r10, MAPSURF_32BIT | MT_32BIT_ABGR2101010}, {PICT_r5g6b5, MAPSURF_16BIT | MT_16BIT_RGB565}, {PICT_a1r5g5b5, MAPSURF_16BIT | MT_16BIT_ARGB1555}, - {PICT_x1r5g5b5, MAPSURF_16BIT | MT_16BIT_ARGB1555}, {PICT_a4r4g4b4, MAPSURF_16BIT | MT_16BIT_ARGB4444}, - {PICT_x4r4g4b4, MAPSURF_16BIT | MT_16BIT_ARGB4444}, - {PICT_a8, MAPSURF_8BIT | MT_8BIT_A8}, }; static uint32_t i915_get_blend_cntl(int op, PicturePtr mask, @@ -156,6 +156,10 @@ static Bool i915_get_dest_format(PicturePtr dest_picture, uint32_t * dst_format) case PICT_x1r5g5b5: *dst_format = COLR_BUF_ARGB1555; break; + case PICT_a2r10g10b10: + case PICT_x2r10g10b10: + *dst_format = COLR_BUF_ARGB2AAA; + break; case PICT_a8: *dst_format = COLR_BUF_8BIT; break; @@ -294,12 +298,10 @@ static Bool i915_texture_setup(PicturePtr picture, PixmapPtr pixmap, int unit) ScrnInfoPtr scrn = xf86Screens[picture->pDrawable->pScreen->myNum]; intel_screen_private *intel = intel_get_screen_private(scrn); uint32_t format, pitch, filter; - int w, h, i; uint32_t wrap_mode, tiling_bits; + int i; - pitch = intel_get_pixmap_pitch(pixmap); - w = picture->pDrawable->width; - h = picture->pDrawable->height; + pitch = intel_pixmap_pitch(pixmap); intel->scale_units[unit][0] = 1. / pixmap->drawable.width; intel->scale_units[unit][1] = 1. / pixmap->drawable.height; @@ -348,9 +350,9 @@ static Bool i915_texture_setup(PicturePtr picture, PixmapPtr pixmap, int unit) } /* offset filled in at emit time */ - if (i830_pixmap_tiled(pixmap)) { + if (intel_pixmap_tiled(pixmap)) { tiling_bits = MS3_TILED_SURFACE; - if (i830_get_pixmap_intel(pixmap)->tiling + if (intel_get_pixmap_private(pixmap)->tiling == I915_TILING_Y) tiling_bits |= MS3_TILE_WALK; } else @@ -381,15 +383,12 @@ static Bool i915_texture_setup(PicturePtr picture, PixmapPtr pixmap, int unit) } static void -i915_emit_composite_primitive_constant(PixmapPtr dest, +i915_emit_composite_primitive_constant(intel_screen_private *intel, int srcX, int srcY, int maskX, int maskY, int dstX, int dstY, int w, int h) { - ScrnInfoPtr scrn = xf86Screens[dest->drawable.pScreen->myNum]; - intel_screen_private *intel = intel_get_screen_private(scrn); - OUT_VERTEX(dstX + w); OUT_VERTEX(dstY + h); @@ -401,15 +400,12 @@ i915_emit_composite_primitive_constant(PixmapPtr dest, } static void -i915_emit_composite_primitive_identity_source(PixmapPtr dest, +i915_emit_composite_primitive_identity_source(intel_screen_private *intel, int srcX, int srcY, int maskX, int maskY, int dstX, int dstY, int w, int h) { - ScrnInfoPtr scrn = xf86Screens[dest->drawable.pScreen->myNum]; - intel_screen_private *intel = intel_get_screen_private(scrn); - OUT_VERTEX(dstX + w); OUT_VERTEX(dstY + h); OUT_VERTEX((srcX + w) * intel->scale_units[0][0]); @@ -427,29 +423,27 @@ i915_emit_composite_primitive_identity_source(PixmapPtr dest, } static void -i915_emit_composite_primitive_affine_source(PixmapPtr dest, +i915_emit_composite_primitive_affine_source(intel_screen_private *intel, int srcX, int srcY, int maskX, int maskY, int dstX, int dstY, int w, int h) { - ScrnInfoPtr scrn = xf86Screens[dest->drawable.pScreen->myNum]; - intel_screen_private *intel = intel_get_screen_private(scrn); float src_x[3], src_y[3]; - if (!i830_get_transformed_coordinates(srcX, srcY, + if (!intel_get_transformed_coordinates(srcX, srcY, intel->transform[0], &src_x[0], &src_y[0])) return; - if (!i830_get_transformed_coordinates(srcX, srcY + h, + if (!intel_get_transformed_coordinates(srcX, srcY + h, intel->transform[0], &src_x[1], &src_y[1])) return; - if (!i830_get_transformed_coordinates(srcX + w, srcY + h, + if (!intel_get_transformed_coordinates(srcX + w, srcY + h, intel->transform[0], &src_x[2], &src_y[2])) @@ -472,15 +466,12 @@ i915_emit_composite_primitive_affine_source(PixmapPtr dest, } static void -i915_emit_composite_primitive_constant_identity_mask(PixmapPtr dest, +i915_emit_composite_primitive_constant_identity_mask(intel_screen_private *intel, int srcX, int srcY, int maskX, int maskY, int dstX, int dstY, int w, int h) { - ScrnInfoPtr scrn = xf86Screens[dest->drawable.pScreen->myNum]; - intel_screen_private *intel = intel_get_screen_private(scrn); - OUT_VERTEX(dstX + w); OUT_VERTEX(dstY + h); OUT_VERTEX((maskX + w) * intel->scale_units[0][0]); @@ -498,15 +489,12 @@ i915_emit_composite_primitive_constant_identity_mask(PixmapPtr dest, } static void -i915_emit_composite_primitive_identity_source_mask(PixmapPtr dest, +i915_emit_composite_primitive_identity_source_mask(intel_screen_private *intel, int srcX, int srcY, int maskX, int maskY, int dstX, int dstY, int w, int h) { - ScrnInfoPtr scrn = xf86Screens[dest->drawable.pScreen->myNum]; - intel_screen_private *intel = intel_get_screen_private(scrn); - OUT_VERTEX(dstX + w); OUT_VERTEX(dstY + h); OUT_VERTEX((srcX + w) * intel->scale_units[0][0]); @@ -530,16 +518,14 @@ i915_emit_composite_primitive_identity_source_mask(PixmapPtr dest, } static void -i915_emit_composite_primitive(PixmapPtr dest, +i915_emit_composite_primitive(intel_screen_private *intel, int srcX, int srcY, int maskX, int maskY, int dstX, int dstY, int w, int h) { - ScrnInfoPtr scrn = xf86Screens[dest->drawable.pScreen->myNum]; - intel_screen_private *intel = intel_get_screen_private(scrn); - Bool is_affine_src, is_affine_mask = TRUE; - int per_vertex, num_floats; + Bool is_affine_src = TRUE, is_affine_mask = TRUE; + int per_vertex; int tex_unit = 0; int src_unit = -1, mask_unit = -1; float src_x[3], src_y[3], src_w[3], mask_x[3], mask_y[3], mask_w[3]; @@ -549,23 +535,23 @@ i915_emit_composite_primitive(PixmapPtr dest, if (! intel->render_source_is_solid) { src_unit = tex_unit++; - is_affine_src = i830_transform_is_affine(intel->transform[src_unit]); + is_affine_src = intel_transform_is_affine(intel->transform[src_unit]); if (is_affine_src) { - if (!i830_get_transformed_coordinates(srcX, srcY, + if (!intel_get_transformed_coordinates(srcX, srcY, intel-> transform[src_unit], &src_x[0], &src_y[0])) return; - if (!i830_get_transformed_coordinates(srcX, srcY + h, + if (!intel_get_transformed_coordinates(srcX, srcY + h, intel-> transform[src_unit], &src_x[1], &src_y[1])) return; - if (!i830_get_transformed_coordinates(srcX + w, srcY + h, + if (!intel_get_transformed_coordinates(srcX + w, srcY + h, intel-> transform[src_unit], &src_x[2], @@ -574,7 +560,7 @@ i915_emit_composite_primitive(PixmapPtr dest, per_vertex += 2; /* src x/y */ } else { - if (!i830_get_transformed_coordinates_3d(srcX, srcY, + if (!intel_get_transformed_coordinates_3d(srcX, srcY, intel-> transform[src_unit], &src_x[0], @@ -582,7 +568,7 @@ i915_emit_composite_primitive(PixmapPtr dest, &src_w[0])) return; - if (!i830_get_transformed_coordinates_3d(srcX, srcY + h, + if (!intel_get_transformed_coordinates_3d(srcX, srcY + h, intel-> transform[src_unit], &src_x[1], @@ -590,7 +576,7 @@ i915_emit_composite_primitive(PixmapPtr dest, &src_w[1])) return; - if (!i830_get_transformed_coordinates_3d(srcX + w, srcY + h, + if (!intel_get_transformed_coordinates_3d(srcX + w, srcY + h, intel-> transform[src_unit], &src_x[2], @@ -605,23 +591,23 @@ i915_emit_composite_primitive(PixmapPtr dest, if (intel->render_mask && ! intel->render_mask_is_solid) { mask_unit = tex_unit++; - is_affine_mask = i830_transform_is_affine(intel->transform[mask_unit]); + is_affine_mask = intel_transform_is_affine(intel->transform[mask_unit]); if (is_affine_mask) { - if (!i830_get_transformed_coordinates(maskX, maskY, + if (!intel_get_transformed_coordinates(maskX, maskY, intel-> transform[mask_unit], &mask_x[0], &mask_y[0])) return; - if (!i830_get_transformed_coordinates(maskX, maskY + h, + if (!intel_get_transformed_coordinates(maskX, maskY + h, intel-> transform[mask_unit], &mask_x[1], &mask_y[1])) return; - if (!i830_get_transformed_coordinates(maskX + w, maskY + h, + if (!intel_get_transformed_coordinates(maskX + w, maskY + h, intel-> transform[mask_unit], &mask_x[2], @@ -630,7 +616,7 @@ i915_emit_composite_primitive(PixmapPtr dest, per_vertex += 2; /* mask x/y */ } else { - if (!i830_get_transformed_coordinates_3d(maskX, maskY, + if (!intel_get_transformed_coordinates_3d(maskX, maskY, intel-> transform[mask_unit], &mask_x[0], @@ -638,7 +624,7 @@ i915_emit_composite_primitive(PixmapPtr dest, &mask_w[0])) return; - if (!i830_get_transformed_coordinates_3d(maskX, maskY + h, + if (!intel_get_transformed_coordinates_3d(maskX, maskY + h, intel-> transform[mask_unit], &mask_x[1], @@ -646,7 +632,7 @@ i915_emit_composite_primitive(PixmapPtr dest, &mask_w[1])) return; - if (!i830_get_transformed_coordinates_3d(maskX + w, maskY + h, + if (!intel_get_transformed_coordinates_3d(maskX + w, maskY + h, intel-> transform[mask_unit], &mask_x[2], @@ -658,8 +644,6 @@ i915_emit_composite_primitive(PixmapPtr dest, } } - num_floats = 3 * per_vertex; - OUT_VERTEX(dstX + w); OUT_VERTEX(dstY + h); if (! intel->render_source_is_solid) { @@ -727,9 +711,9 @@ i915_prepare_composite(int op, PicturePtr source_picture, intel_screen_private *intel = intel_get_screen_private(scrn); drm_intel_bo *bo_table[] = { NULL, /* batch_bo */ - i830_get_pixmap_bo(dest), - source ? i830_get_pixmap_bo(source) : NULL, - mask ? i830_get_pixmap_bo(mask) : NULL, + intel_get_pixmap_bo(dest), + source ? intel_get_pixmap_bo(source) : NULL, + mask ? intel_get_pixmap_bo(mask) : NULL, }; int tex_unit = 0; int floats_per_vertex; @@ -772,7 +756,7 @@ i915_prepare_composite(int op, PicturePtr source_picture, &intel->i915_render_state.dst_format)) return FALSE; - if (!i830_get_aperture_space(scrn, bo_table, ARRAY_SIZE(bo_table))) + if (!intel_get_aperture_space(scrn, bo_table, ARRAY_SIZE(bo_table))) return FALSE; intel->needs_render_ca_pass = FALSE; @@ -805,7 +789,7 @@ i915_prepare_composite(int op, PicturePtr source_picture, return FALSE; } - if (i830_transform_is_affine(source_picture->transform)) + if (intel_transform_is_affine(source_picture->transform)) floats_per_vertex += 2; /* src x/y */ else floats_per_vertex += 4; /* src x/y/z/w */ @@ -819,7 +803,7 @@ i915_prepare_composite(int op, PicturePtr source_picture, return FALSE; } - if (i830_transform_is_affine(mask_picture->transform)) + if (intel_transform_is_affine(mask_picture->transform)) floats_per_vertex += 2; /* mask x/y */ else floats_per_vertex += 4; /* mask x/y/z/w */ @@ -831,8 +815,8 @@ i915_prepare_composite(int op, PicturePtr source_picture, /* BUF_INFO is an implicit flush */ if (dest != intel->render_current_dest) intel_batch_do_flush(scrn); - else if((source && i830_uxa_pixmap_is_dirty(source)) || - (mask && i830_uxa_pixmap_is_dirty(mask))) + else if((source && intel_pixmap_is_dirty(source)) || + (mask && intel_pixmap_is_dirty(mask))) intel_batch_emit_flush(scrn); intel->needs_render_state_emit = TRUE; @@ -843,7 +827,7 @@ i915_prepare_composite(int op, PicturePtr source_picture, intel->prim_emit = i915_emit_composite_primitive_constant; else if (intel->transform[0] == NULL) intel->prim_emit = i915_emit_composite_primitive_identity_source; - else if (i830_transform_is_affine(intel->transform[0])) + else if (intel_transform_is_affine(intel->transform[0])) intel->prim_emit = i915_emit_composite_primitive_affine_source; } else { if (intel->transform[0] == NULL) { @@ -896,7 +880,7 @@ i915_composite_emit_shader(intel_screen_private *intel, CARD8 op) else src_reg = FS_OC; - if (i830_transform_is_affine(intel->transform[0])) + if (intel_transform_is_affine(intel->transform[0])) i915_fs_texld(src_reg, FS_S0, FS_T0); else i915_fs_texldp(src_reg, FS_S0, FS_T0); @@ -920,7 +904,7 @@ i915_composite_emit_shader(intel_screen_private *intel, CARD8 op) tex_unit = 0; if (! is_solid_src) { /* Load the source_picture texel */ - if (i830_transform_is_affine(intel->transform[tex_unit])) + if (intel_transform_is_affine(intel->transform[tex_unit])) i915_fs_texld(FS_R0, FS_S0, FS_T0); else i915_fs_texldp(FS_R0, FS_S0, FS_T0); @@ -931,7 +915,7 @@ i915_composite_emit_shader(intel_screen_private *intel, CARD8 op) if (! is_solid_mask) { /* Load the mask_picture texel */ - if (i830_transform_is_affine(intel->transform[tex_unit])) + if (intel_transform_is_affine(intel->transform[tex_unit])) i915_fs_texld(FS_R1, FS_S0 + t, FS_T0 + t); else i915_fs_texldp(FS_R1, FS_S0 + t, FS_T0 + t); @@ -1037,9 +1021,9 @@ static void i915_emit_composite_setup(ScrnInfoPtr scrn) intel_batch_do_flush(scrn); - if (i830_pixmap_tiled(dest)) { + if (intel_pixmap_tiled(dest)) { tiling_bits = BUF_3D_TILED_SURFACE; - if (i830_get_pixmap_intel(dest)->tiling + if (intel_get_pixmap_private(dest)->tiling == I915_TILING_Y) tiling_bits |= BUF_3D_TILE_WALK_Y; } else @@ -1047,7 +1031,7 @@ static void i915_emit_composite_setup(ScrnInfoPtr scrn) OUT_BATCH(_3DSTATE_BUF_INFO_CMD); OUT_BATCH(BUF_3D_ID_COLOR_BACK | tiling_bits | - BUF_3D_PITCH(intel_get_pixmap_pitch(dest))); + BUF_3D_PITCH(intel_pixmap_pitch(dest))); OUT_RELOC_PIXMAP(dest, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0); @@ -1074,14 +1058,14 @@ static void i915_emit_composite_setup(ScrnInfoPtr scrn) if (! is_solid_src) { ss2 &= ~S2_TEXCOORD_FMT(t, TEXCOORDFMT_NOT_PRESENT); ss2 |= S2_TEXCOORD_FMT(t, - i830_transform_is_affine(intel->transform[t]) ? + intel_transform_is_affine(intel->transform[t]) ? TEXCOORDFMT_2D : TEXCOORDFMT_4D); t++; } if (mask && ! is_solid_mask) { ss2 &= ~S2_TEXCOORD_FMT(t, TEXCOORDFMT_NOT_PRESENT); ss2 |= S2_TEXCOORD_FMT(t, - i830_transform_is_affine(intel->transform[t]) ? + intel_transform_is_affine(intel->transform[t]) ? TEXCOORDFMT_2D : TEXCOORDFMT_4D); t++; } @@ -1156,7 +1140,7 @@ i915_composite(PixmapPtr dest, int srcX, int srcY, int maskX, int maskY, } intel->vertex_count += 3; - intel->prim_emit(dest, + intel->prim_emit(intel, srcX, srcY, maskX, maskY, dstX, dstY, @@ -1189,10 +1173,8 @@ i915_vertex_flush(intel_screen_private *intel) } void -i915_batch_flush_notify(ScrnInfoPtr scrn) +i915_batch_commit_notify(intel_screen_private *intel) { - intel_screen_private *intel = intel_get_screen_private(scrn); - intel->needs_render_state_emit = TRUE; intel->render_current_dest = NULL; intel->last_floats_per_vertex = 0; diff --git a/driver/xf86-video-intel/src/i915_video.c b/driver/xf86-video-intel/src/i915_video.c index 893855bd6..d46c6d155 100644 --- a/driver/xf86-video-intel/src/i915_video.c +++ b/driver/xf86-video-intel/src/i915_video.c @@ -34,8 +34,8 @@ #include "xf86xv.h" #include "fourcc.h" -#include "i830.h" -#include "i830_video.h" +#include "intel.h" +#include "intel_video.h" #include "i915_reg.h" #include "i915_3d.h" @@ -69,7 +69,8 @@ I915DisplayVideoTextured(ScrnInfoPtr scrn, ScreenPtr screen = pixmap->drawable.pScreen; target = screen->CreatePixmap(screen, - drw_w, drw_h, + dstRegion->extents.x2 - dxo, + dstRegion->extents.y2 - dyo, pixmap->drawable.depth, CREATE_PIXMAP_USAGE_SCRATCH); @@ -149,15 +150,15 @@ I915DisplayVideoTextured(ScrnInfoPtr scrn, DSTORG_VERT_BIAS(0x8) | format); /* front buffer, pitch, offset */ - if (i830_pixmap_tiled(target)) { + if (intel_pixmap_tiled(target)) { tiling = BUF_3D_TILED_SURFACE; - if (i830_get_pixmap_intel(target)->tiling == I915_TILING_Y) + if (intel_get_pixmap_private(target)->tiling == I915_TILING_Y) tiling |= BUF_3D_TILE_WALK_Y; } else tiling = 0; OUT_BATCH(_3DSTATE_BUF_INFO_CMD); OUT_BATCH(BUF_3D_ID_COLOR_BACK | tiling | - BUF_3D_PITCH(intel_get_pixmap_pitch(target))); + BUF_3D_PITCH(intel_pixmap_pitch(target))); OUT_RELOC_PIXMAP(target, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0); @@ -454,11 +455,11 @@ I915DisplayVideoTextured(ScrnInfoPtr scrn, gc = GetScratchGC(pixmap->drawable.depth, pixmap->drawable.pScreen); if (gc) { - RegionPtr tmp; - - ValidateGC(&pixmap->drawable, gc); + gc->subWindowMode = ClipByChildren; if (REGION_NUM_RECTS(dstRegion) > 1) { + RegionPtr tmp; + tmp = REGION_CREATE(pixmap->drawable.pScreen, NULL, 0); if (tmp) { REGION_COPY(pixmap->drawable.pScreen, tmp, dstRegion); @@ -466,6 +467,7 @@ I915DisplayVideoTextured(ScrnInfoPtr scrn, } } + ValidateGC(&pixmap->drawable, gc); gc->ops->CopyArea(&target->drawable, &pixmap->drawable, gc, 0, 0, target->drawable.width, @@ -477,5 +479,5 @@ I915DisplayVideoTextured(ScrnInfoPtr scrn, target->drawable.pScreen->DestroyPixmap(target); } - i830_debug_flush(scrn); + intel_debug_flush(scrn); } diff --git a/driver/xf86-video-intel/src/i965_3d.c b/driver/xf86-video-intel/src/i965_3d.c new file mode 100644 index 000000000..d4d38e59e --- /dev/null +++ b/driver/xf86-video-intel/src/i965_3d.c @@ -0,0 +1,438 @@ +/* + * Copyright © 2011 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <string.h> + +#include "intel.h" +#include "i965_reg.h" +#include "brw_defines.h" +#include "brw_structs.h" + +void +gen6_upload_invariant_states(intel_screen_private *intel) +{ + Bool ivb = INTEL_INFO(intel)->gen >= 70; + + OUT_BATCH(BRW_PIPE_CONTROL | (4 - 2)); + OUT_BATCH(BRW_PIPE_CONTROL_IS_FLUSH | + BRW_PIPE_CONTROL_WC_FLUSH | + BRW_PIPE_CONTROL_DEPTH_CACHE_FLUSH | + BRW_PIPE_CONTROL_NOWRITE); + OUT_BATCH(0); /* write address */ + OUT_BATCH(0); /* write data */ + + OUT_BATCH(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D); + + OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE | ((ivb ? 4 : 3) - 2)); + OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER | + GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_1); /* 1 sample/pixel */ + OUT_BATCH(0); + if (ivb) + OUT_BATCH(0); + + OUT_BATCH(GEN6_3DSTATE_SAMPLE_MASK | (2 - 2)); + OUT_BATCH(1); + + /* Set system instruction pointer */ + OUT_BATCH(BRW_STATE_SIP | 0); + OUT_BATCH(0); +} + +void +gen6_upload_viewport_state_pointers(intel_screen_private *intel, + drm_intel_bo *cc_vp_bo) +{ + OUT_BATCH(GEN6_3DSTATE_VIEWPORT_STATE_POINTERS | + GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_CC | + (4 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_RELOC(cc_vp_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); +} + +void +gen7_upload_viewport_state_pointers(intel_screen_private *intel, + drm_intel_bo *cc_vp_bo) +{ + OUT_BATCH(GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC | (2 - 2)); + OUT_RELOC(cc_vp_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); + + OUT_BATCH(GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL | (2 - 2)); + OUT_BATCH(0); +} + +void +gen6_upload_urb(intel_screen_private *intel) +{ + OUT_BATCH(GEN6_3DSTATE_URB | (3 - 2)); + OUT_BATCH(((1 - 1) << GEN6_3DSTATE_URB_VS_SIZE_SHIFT) | + (24 << GEN6_3DSTATE_URB_VS_ENTRIES_SHIFT)); /* at least 24 on GEN6 */ + OUT_BATCH((0 << GEN6_3DSTATE_URB_GS_SIZE_SHIFT) | + (0 << GEN6_3DSTATE_URB_GS_ENTRIES_SHIFT)); /* no GS thread */ +} + +/* + * URB layout on GEN7 + * ---------------------------------------- + * | PS Push Constants (8KB) | VS entries | + * ---------------------------------------- + */ +void +gen7_upload_urb(intel_screen_private *intel) +{ + OUT_BATCH(GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS | (2 - 2)); + OUT_BATCH(8); /* in 1KBs */ + + OUT_BATCH(GEN7_3DSTATE_URB_VS | (2 - 2)); + OUT_BATCH( + (32 << GEN7_URB_ENTRY_NUMBER_SHIFT) | /* at least 32 */ + (2 - 1) << GEN7_URB_ENTRY_SIZE_SHIFT | + (1 << GEN7_URB_STARTING_ADDRESS_SHIFT)); + + OUT_BATCH(GEN7_3DSTATE_URB_GS | (2 - 2)); + OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) | + (1 << GEN7_URB_STARTING_ADDRESS_SHIFT)); + + OUT_BATCH(GEN7_3DSTATE_URB_HS | (2 - 2)); + OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) | + (2 << GEN7_URB_STARTING_ADDRESS_SHIFT)); + + OUT_BATCH(GEN7_3DSTATE_URB_DS | (2 - 2)); + OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) | + (2 << GEN7_URB_STARTING_ADDRESS_SHIFT)); +} + +void +gen6_upload_cc_state_pointers(intel_screen_private *intel, + drm_intel_bo *blend_bo, + drm_intel_bo *cc_bo, + drm_intel_bo *depth_stencil_bo, + uint32_t blend_offset) +{ + OUT_BATCH(GEN6_3DSTATE_CC_STATE_POINTERS | (4 - 2)); + if (blend_bo) + OUT_RELOC(blend_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, + blend_offset | 1); + else + OUT_BATCH(0); + + if (depth_stencil_bo) + OUT_RELOC(depth_stencil_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1); + else + OUT_BATCH(0); + + if (cc_bo) + OUT_RELOC(cc_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1); + else + OUT_BATCH(0); +} + +void +gen7_upload_cc_state_pointers(intel_screen_private *intel, + drm_intel_bo *blend_bo, + drm_intel_bo *cc_bo, + drm_intel_bo *depth_stencil_bo, + uint32_t blend_offset) +{ + OUT_BATCH(GEN7_3DSTATE_BLEND_STATE_POINTERS | (2 - 2)); + if (blend_bo) + OUT_RELOC(blend_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, + blend_offset | 1); + else + OUT_BATCH(0); + + OUT_BATCH(GEN6_3DSTATE_CC_STATE_POINTERS | (2 - 2)); + if (cc_bo) + OUT_RELOC(cc_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1); + else + OUT_BATCH(0); + + OUT_BATCH(GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS | (2 - 2)); + if (depth_stencil_bo) + OUT_RELOC(depth_stencil_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1); + else + OUT_BATCH(0); +} + +void +gen6_upload_sampler_state_pointers(intel_screen_private *intel, + drm_intel_bo *sampler_bo) +{ + OUT_BATCH(GEN6_3DSTATE_SAMPLER_STATE_POINTERS | + GEN6_3DSTATE_SAMPLER_STATE_MODIFY_PS | + (4 - 2)); + OUT_BATCH(0); /* VS */ + OUT_BATCH(0); /* GS */ + OUT_RELOC(sampler_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); +} + +void +gen7_upload_sampler_state_pointers(intel_screen_private *intel, + drm_intel_bo *sampler_bo) +{ + OUT_BATCH(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS | (2 - 2)); + OUT_RELOC(sampler_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); +} + +void +gen7_upload_bypass_states(intel_screen_private *intel) +{ + /* bypass GS */ + OUT_BATCH(GEN6_3DSTATE_CONSTANT_GS | (7 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + + OUT_BATCH(GEN6_3DSTATE_GS | (7 - 2)); + OUT_BATCH(0); /* without GS kernel */ + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); /* pass-through */ + + OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS | (2 - 2)); + OUT_BATCH(0); + + /* disable HS */ + OUT_BATCH(GEN7_3DSTATE_CONSTANT_HS | (7 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + + OUT_BATCH(GEN7_3DSTATE_HS | (7 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + + OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS | (2 - 2)); + OUT_BATCH(0); + + /* Disable TE */ + OUT_BATCH(GEN7_3DSTATE_TE | (4 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + + /* Disable DS */ + OUT_BATCH(GEN7_3DSTATE_CONSTANT_DS | (7 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + + OUT_BATCH(GEN7_3DSTATE_DS | (6 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + + OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS | (2 - 2)); + OUT_BATCH(0); + + /* Disable STREAMOUT */ + OUT_BATCH(GEN7_3DSTATE_STREAMOUT | (3 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); +} + +void +gen6_upload_vs_state(intel_screen_private *intel) +{ + Bool ivb = INTEL_INFO(intel)->gen >= 70; + /* disable VS constant buffer */ + OUT_BATCH(GEN6_3DSTATE_CONSTANT_VS | ((ivb ? 7 : 5) - 2)); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + if (ivb) { + OUT_BATCH(0); + OUT_BATCH(0); + } + + OUT_BATCH(GEN6_3DSTATE_VS | (6 - 2)); + OUT_BATCH(0); /* without VS kernel */ + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); /* pass-through */ +} + +void +gen6_upload_gs_state(intel_screen_private *intel) +{ + /* disable GS constant buffer */ + OUT_BATCH(GEN6_3DSTATE_CONSTANT_GS | (5 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + + OUT_BATCH(GEN6_3DSTATE_GS | (7 - 2)); + OUT_BATCH(0); /* without GS kernel */ + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); /* pass-through */ +} + +void +gen6_upload_clip_state(intel_screen_private *intel) +{ + OUT_BATCH(GEN6_3DSTATE_CLIP | (4 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); /* pass-through */ + OUT_BATCH(0); +} + +void +gen6_upload_sf_state(intel_screen_private *intel, + int num_sf_outputs, + int read_offset) +{ + OUT_BATCH(GEN6_3DSTATE_SF | (20 - 2)); + OUT_BATCH((num_sf_outputs << GEN6_3DSTATE_SF_NUM_OUTPUTS_SHIFT) | + (1 << GEN6_3DSTATE_SF_URB_ENTRY_READ_LENGTH_SHIFT) | + (read_offset << GEN6_3DSTATE_SF_URB_ENTRY_READ_OFFSET_SHIFT)); + OUT_BATCH(0); + OUT_BATCH(GEN6_3DSTATE_SF_CULL_NONE); + OUT_BATCH(2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT); /* DW4 */ + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); /* DW9 */ + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); /* DW14 */ + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); /* DW19 */ +} + +void +gen7_upload_sf_state(intel_screen_private *intel, + int num_sf_outputs, + int read_offset) +{ + OUT_BATCH(GEN7_3DSTATE_SBE | (14 - 2)); + OUT_BATCH((num_sf_outputs << GEN7_SBE_NUM_OUTPUTS_SHIFT) | + (1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT) | + (read_offset << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT)); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); /* DW4 */ + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); /* DW9 */ + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + + OUT_BATCH(GEN6_3DSTATE_SF | (7 - 2)); + OUT_BATCH(0); + OUT_BATCH(GEN6_3DSTATE_SF_CULL_NONE); + OUT_BATCH(2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); +} + +void +gen6_upload_binding_table(intel_screen_private *intel, + uint32_t ps_binding_table_offset) +{ + /* Binding table pointers */ + OUT_BATCH(BRW_3DSTATE_BINDING_TABLE_POINTERS | + GEN6_3DSTATE_BINDING_TABLE_MODIFY_PS | + (4 - 2)); + OUT_BATCH(0); /* VS */ + OUT_BATCH(0); /* GS */ + /* Only the PS uses the binding table */ + OUT_BATCH(ps_binding_table_offset); +} + +void +gen7_upload_binding_table(intel_screen_private *intel, + uint32_t ps_binding_table_offset) +{ + OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS | (2 - 2)); + OUT_BATCH(ps_binding_table_offset); +} + +void +gen6_upload_depth_buffer_state(intel_screen_private *intel) +{ + OUT_BATCH(BRW_3DSTATE_DEPTH_BUFFER | (7 - 2)); + OUT_BATCH((BRW_SURFACE_NULL << BRW_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT) | + (BRW_DEPTHFORMAT_D32_FLOAT << BRW_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT)); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + + OUT_BATCH(BRW_3DSTATE_CLEAR_PARAMS | (2 - 2)); + OUT_BATCH(0); +} + +void +gen7_upload_depth_buffer_state(intel_screen_private *intel) +{ + OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER | (7 - 2)); + OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) | (BRW_SURFACE_NULL << 29)); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + + OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS | (3 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); +} diff --git a/driver/xf86-video-intel/src/i965_reg.h b/driver/xf86-video-intel/src/i965_reg.h new file mode 100644 index 000000000..ab6c02053 --- /dev/null +++ b/driver/xf86-video-intel/src/i965_reg.h @@ -0,0 +1,472 @@ +/* + * New regs for broadwater -- we need to split this file up sensibly somehow. + */ +#define BRW_3D(Pipeline,Opcode,Subopcode) ((3 << 29) | \ + ((Pipeline) << 27) | \ + ((Opcode) << 24) | \ + ((Subopcode) << 16)) + +#define BRW_URB_FENCE BRW_3D(0, 0, 0) +#define BRW_CS_URB_STATE BRW_3D(0, 0, 1) +#define BRW_CONSTANT_BUFFER BRW_3D(0, 0, 2) +#define BRW_STATE_PREFETCH BRW_3D(0, 0, 3) + +#define BRW_STATE_BASE_ADDRESS BRW_3D(0, 1, 1) +#define BRW_STATE_SIP BRW_3D(0, 1, 2) +#define BRW_PIPELINE_SELECT BRW_3D(0, 1, 4) + +#define NEW_PIPELINE_SELECT BRW_3D(1, 1, 4) + +#define BRW_MEDIA_STATE_POINTERS BRW_3D(2, 0, 0) +#define BRW_MEDIA_OBJECT BRW_3D(2, 1, 0) + +#define BRW_3DSTATE_PIPELINED_POINTERS BRW_3D(3, 0, 0) +#define BRW_3DSTATE_BINDING_TABLE_POINTERS BRW_3D(3, 0, 1) +# define GEN6_3DSTATE_BINDING_TABLE_MODIFY_PS (1 << 12)/* for GEN6 */ +# define GEN6_3DSTATE_BINDING_TABLE_MODIFY_GS (1 << 9) /* for GEN6 */ +# define GEN6_3DSTATE_BINDING_TABLE_MODIFY_VS (1 << 8) /* for GEN6 */ + +#define BRW_3DSTATE_VERTEX_BUFFERS BRW_3D(3, 0, 8) +#define BRW_3DSTATE_VERTEX_ELEMENTS BRW_3D(3, 0, 9) +#define BRW_3DSTATE_INDEX_BUFFER BRW_3D(3, 0, 0xa) +#define BRW_3DSTATE_VF_STATISTICS BRW_3D(3, 0, 0xb) + +#define BRW_3DSTATE_DRAWING_RECTANGLE BRW_3D(3, 1, 0) +#define BRW_3DSTATE_CONSTANT_COLOR BRW_3D(3, 1, 1) +#define BRW_3DSTATE_SAMPLER_PALETTE_LOAD BRW_3D(3, 1, 2) +#define BRW_3DSTATE_CHROMA_KEY BRW_3D(3, 1, 4) +#define BRW_3DSTATE_DEPTH_BUFFER BRW_3D(3, 1, 5) +# define BRW_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT 29 +# define BRW_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT 18 + +#define BRW_3DSTATE_POLY_STIPPLE_OFFSET BRW_3D(3, 1, 6) +#define BRW_3DSTATE_POLY_STIPPLE_PATTERN BRW_3D(3, 1, 7) +#define BRW_3DSTATE_LINE_STIPPLE BRW_3D(3, 1, 8) +#define BRW_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP BRW_3D(3, 1, 9) +/* These two are BLC and CTG only, not BW or CL */ +#define BRW_3DSTATE_AA_LINE_PARAMS BRW_3D(3, 1, 0xa) +#define BRW_3DSTATE_GS_SVB_INDEX BRW_3D(3, 1, 0xb) + +#define BRW_PIPE_CONTROL BRW_3D(3, 2, 0) + +#define BRW_3DPRIMITIVE BRW_3D(3, 3, 0) + +#define BRW_3DSTATE_CLEAR_PARAMS BRW_3D(3, 1, 0x10) +/* DW1 */ +# define BRW_3DSTATE_DEPTH_CLEAR_VALID (1 << 15) + +/* for GEN6+ */ +#define GEN6_3DSTATE_SAMPLER_STATE_POINTERS BRW_3D(3, 0, 0x02) +# define GEN6_3DSTATE_SAMPLER_STATE_MODIFY_PS (1 << 12) +# define GEN6_3DSTATE_SAMPLER_STATE_MODIFY_GS (1 << 9) +# define GEN6_3DSTATE_SAMPLER_STATE_MODIFY_VS (1 << 8) + +#define GEN6_3DSTATE_URB BRW_3D(3, 0, 0x05) +/* DW1 */ +# define GEN6_3DSTATE_URB_VS_SIZE_SHIFT 16 +# define GEN6_3DSTATE_URB_VS_ENTRIES_SHIFT 0 +/* DW2 */ +# define GEN6_3DSTATE_URB_GS_ENTRIES_SHIFT 8 +# define GEN6_3DSTATE_URB_GS_SIZE_SHIFT 0 + +#define GEN6_3DSTATE_VIEWPORT_STATE_POINTERS BRW_3D(3, 0, 0x0d) +# define GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_CC (1 << 12) +# define GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_SF (1 << 11) +# define GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_CLIP (1 << 10) + +#define GEN6_3DSTATE_CC_STATE_POINTERS BRW_3D(3, 0, 0x0e) + +#define GEN6_3DSTATE_VS BRW_3D(3, 0, 0x10) + +#define GEN6_3DSTATE_GS BRW_3D(3, 0, 0x11) +/* DW4 */ +# define GEN6_3DSTATE_GS_DISPATCH_START_GRF_SHIFT 0 + +#define GEN6_3DSTATE_CLIP BRW_3D(3, 0, 0x12) + +#define GEN6_3DSTATE_SF BRW_3D(3, 0, 0x13) +/* DW1 */ +# define GEN6_3DSTATE_SF_NUM_OUTPUTS_SHIFT 22 +# define GEN6_3DSTATE_SF_URB_ENTRY_READ_LENGTH_SHIFT 11 +# define GEN6_3DSTATE_SF_URB_ENTRY_READ_OFFSET_SHIFT 4 +/* DW2 */ +/* DW3 */ +# define GEN6_3DSTATE_SF_CULL_BOTH (0 << 29) +# define GEN6_3DSTATE_SF_CULL_NONE (1 << 29) +# define GEN6_3DSTATE_SF_CULL_FRONT (2 << 29) +# define GEN6_3DSTATE_SF_CULL_BACK (3 << 29) +/* DW4 */ +# define GEN6_3DSTATE_SF_TRI_PROVOKE_SHIFT 29 +# define GEN6_3DSTATE_SF_LINE_PROVOKE_SHIFT 27 +# define GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT 25 + + +#define GEN6_3DSTATE_WM BRW_3D(3, 0, 0x14) +/* DW2 */ +# define GEN6_3DSTATE_WM_SAMPLER_COUNT_SHITF 27 +# define GEN6_3DSTATE_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT 18 +/* DW4 */ +# define GEN6_3DSTATE_WM_DISPATCH_START_GRF_0_SHIFT 16 +/* DW5 */ +# define GEN6_3DSTATE_WM_MAX_THREADS_SHIFT 25 +# define GEN6_3DSTATE_WM_DISPATCH_ENABLE (1 << 19) +# define GEN6_3DSTATE_WM_16_DISPATCH_ENABLE (1 << 1) +# define GEN6_3DSTATE_WM_8_DISPATCH_ENABLE (1 << 0) +/* DW6 */ +# define GEN6_3DSTATE_WM_NUM_SF_OUTPUTS_SHIFT 20 +# define GEN6_3DSTATE_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC (1 << 15) +# define GEN6_3DSTATE_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC (1 << 14) +# define GEN6_3DSTATE_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC (1 << 13) +# define GEN6_3DSTATE_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC (1 << 12) +# define GEN6_3DSTATE_WM_PERSPECTIVE_CENTROID_BARYCENTRIC (1 << 11) +# define GEN6_3DSTATE_WM_PERSPECTIVE_PIXEL_BARYCENTRIC (1 << 10) + + +#define GEN6_3DSTATE_CONSTANT_VS BRW_3D(3, 0, 0x15) +#define GEN6_3DSTATE_CONSTANT_GS BRW_3D(3, 0, 0x16) +#define GEN6_3DSTATE_CONSTANT_PS BRW_3D(3, 0, 0x17) + +#define GEN6_3DSTATE_SAMPLE_MASK BRW_3D(3, 0, 0x18) + +#define GEN6_3DSTATE_MULTISAMPLE BRW_3D(3, 1, 0x0d) +/* DW1 */ +# define GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER (0 << 4) +# define GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_UPPER_LEFT (1 << 4) +# define GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_1 (0 << 1) +# define GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_4 (2 << 1) +# define GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_8 (3 << 1) + +/* on GEN7+ */ +/* _3DSTATE_VERTEX_BUFFERS on GEN7*/ +/* DW1 */ +#define GEN7_VB0_ADDRESS_MODIFYENABLE (1 << 14) + +/* _3DPRIMITIVE on GEN7 */ +/* DW1 */ +# define GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL (0 << 8) +# define GEN7_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM (1 << 8) + +/* 3DSTATE_WM on GEN7 */ +/* DW1 */ +# define GEN7_WM_STATISTICS_ENABLE (1 << 31) +# define GEN7_WM_DEPTH_CLEAR (1 << 30) +# define GEN7_WM_DISPATCH_ENABLE (1 << 29) +# define GEN6_WM_DEPTH_RESOLVE (1 << 28) +# define GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE (1 << 27) +# define GEN7_WM_KILL_ENABLE (1 << 25) +# define GEN7_WM_PSCDEPTH_OFF (0 << 23) +# define GEN7_WM_PSCDEPTH_ON (1 << 23) +# define GEN7_WM_PSCDEPTH_ON_GE (2 << 23) +# define GEN7_WM_PSCDEPTH_ON_LE (3 << 23) +# define GEN7_WM_USES_SOURCE_DEPTH (1 << 20) +# define GEN7_WM_USES_SOURCE_W (1 << 19) +# define GEN7_WM_POSITION_ZW_PIXEL (0 << 17) +# define GEN7_WM_POSITION_ZW_CENTROID (2 << 17) +# define GEN7_WM_POSITION_ZW_SAMPLE (3 << 17) +# define GEN7_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC (1 << 16) +# define GEN7_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC (1 << 15) +# define GEN7_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC (1 << 14) +# define GEN7_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC (1 << 13) +# define GEN7_WM_PERSPECTIVE_CENTROID_BARYCENTRIC (1 << 12) +# define GEN7_WM_PERSPECTIVE_PIXEL_BARYCENTRIC (1 << 11) +# define GEN7_WM_USES_INPUT_COVERAGE_MASK (1 << 10) +# define GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5 (0 << 8) +# define GEN7_WM_LINE_END_CAP_AA_WIDTH_1_0 (1 << 8) +# define GEN7_WM_LINE_END_CAP_AA_WIDTH_2_0 (2 << 8) +# define GEN7_WM_LINE_END_CAP_AA_WIDTH_4_0 (3 << 8) +# define GEN7_WM_LINE_AA_WIDTH_0_5 (0 << 6) +# define GEN7_WM_LINE_AA_WIDTH_1_0 (1 << 6) +# define GEN7_WM_LINE_AA_WIDTH_2_0 (2 << 6) +# define GEN7_WM_LINE_AA_WIDTH_4_0 (3 << 6) +# define GEN7_WM_POLYGON_STIPPLE_ENABLE (1 << 4) +# define GEN7_WM_LINE_STIPPLE_ENABLE (1 << 3) +# define GEN7_WM_POINT_RASTRULE_UPPER_RIGHT (1 << 2) +# define GEN7_WM_MSRAST_OFF_PIXEL (0 << 0) +# define GEN7_WM_MSRAST_OFF_PATTERN (1 << 0) +# define GEN7_WM_MSRAST_ON_PIXEL (2 << 0) +# define GEN7_WM_MSRAST_ON_PATTERN (3 << 0) +/* DW2 */ +# define GEN7_WM_MSDISPMODE_PERPIXEL (1 << 31) + +#define GEN7_3DSTATE_CLEAR_PARAMS BRW_3D(3, 0, 0x04) +#define GEN7_3DSTATE_DEPTH_BUFFER BRW_3D(3, 0, 0x05) + +#define GEN7_3DSTATE_CONSTANT_HS BRW_3D(3, 0, 0x19) +#define GEN7_3DSTATE_CONSTANT_DS BRW_3D(3, 0, 0x1a) + +#define GEN7_3DSTATE_HS BRW_3D(3, 0, 0x1b) +#define GEN7_3DSTATE_TE BRW_3D(3, 0, 0x1c) +#define GEN7_3DSTATE_DS BRW_3D(3, 0, 0x1d) +#define GEN7_3DSTATE_STREAMOUT BRW_3D(3, 0, 0x1e) +#define GEN7_3DSTATE_SBE BRW_3D(3, 0, 0x1f) + +/* DW1 */ +# define GEN7_SBE_SWIZZLE_CONTROL_MODE (1 << 28) +# define GEN7_SBE_NUM_OUTPUTS_SHIFT 22 +# define GEN7_SBE_SWIZZLE_ENABLE (1 << 21) +# define GEN7_SBE_POINT_SPRITE_LOWERLEFT (1 << 20) +# define GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT 11 +# define GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT 4 + +#define GEN7_3DSTATE_PS BRW_3D(3, 0, 0x20) +/* DW1: kernel pointer */ +/* DW2 */ +# define GEN7_PS_SPF_MODE (1 << 31) +# define GEN7_PS_VECTOR_MASK_ENABLE (1 << 30) +# define GEN7_PS_SAMPLER_COUNT_SHIFT 27 +# define GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT 18 +# define GEN7_PS_FLOATING_POINT_MODE_IEEE_754 (0 << 16) +# define GEN7_PS_FLOATING_POINT_MODE_ALT (1 << 16) +/* DW3: scratch space */ +/* DW4 */ +# define GEN7_PS_MAX_THREADS_SHIFT 23 +# define GEN7_PS_PUSH_CONSTANT_ENABLE (1 << 11) +# define GEN7_PS_ATTRIBUTE_ENABLE (1 << 10) +# define GEN7_PS_OMASK_TO_RENDER_TARGET (1 << 9) +# define GEN7_PS_DUAL_SOURCE_BLEND_ENABLE (1 << 7) +# define GEN7_PS_POSOFFSET_NONE (0 << 3) +# define GEN7_PS_POSOFFSET_CENTROID (2 << 3) +# define GEN7_PS_POSOFFSET_SAMPLE (3 << 3) +# define GEN7_PS_32_DISPATCH_ENABLE (1 << 2) +# define GEN7_PS_16_DISPATCH_ENABLE (1 << 1) +# define GEN7_PS_8_DISPATCH_ENABLE (1 << 0) +/* DW5 */ +# define GEN7_PS_DISPATCH_START_GRF_SHIFT_0 16 +# define GEN7_PS_DISPATCH_START_GRF_SHIFT_1 8 +# define GEN7_PS_DISPATCH_START_GRF_SHIFT_2 0 +/* DW6: kernel 1 pointer */ +/* DW7: kernel 2 pointer */ + +#define GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL BRW_3D(3, 0, 0x21) +#define GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC BRW_3D(3, 0, 0x23) + +#define GEN7_3DSTATE_BLEND_STATE_POINTERS BRW_3D(3, 0, 0x24) +#define GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS BRW_3D(3, 0, 0x25) + +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS BRW_3D(3, 0, 0x26) +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS BRW_3D(3, 0, 0x27) +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS BRW_3D(3, 0, 0x28) +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS BRW_3D(3, 0, 0x29) +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS BRW_3D(3, 0, 0x2a) + +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS BRW_3D(3, 0, 0x2b) +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_GS BRW_3D(3, 0, 0x2e) +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS BRW_3D(3, 0, 0x2f) + +#define GEN7_3DSTATE_URB_VS BRW_3D(3, 0, 0x30) +#define GEN7_3DSTATE_URB_HS BRW_3D(3, 0, 0x31) +#define GEN7_3DSTATE_URB_DS BRW_3D(3, 0, 0x32) +#define GEN7_3DSTATE_URB_GS BRW_3D(3, 0, 0x33) +/* DW1 */ +# define GEN7_URB_ENTRY_NUMBER_SHIFT 0 +# define GEN7_URB_ENTRY_SIZE_SHIFT 16 +# define GEN7_URB_STARTING_ADDRESS_SHIFT 25 + +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS BRW_3D(3, 1, 0x12) +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS BRW_3D(3, 1, 0x16) +/* DW1 */ +# define GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT 16 + + +#define PIPELINE_SELECT_3D 0 +#define PIPELINE_SELECT_MEDIA 1 + +#define UF0_CS_REALLOC (1 << 13) +#define UF0_VFE_REALLOC (1 << 12) +#define UF0_SF_REALLOC (1 << 11) +#define UF0_CLIP_REALLOC (1 << 10) +#define UF0_GS_REALLOC (1 << 9) +#define UF0_VS_REALLOC (1 << 8) +#define UF1_CLIP_FENCE_SHIFT 20 +#define UF1_GS_FENCE_SHIFT 10 +#define UF1_VS_FENCE_SHIFT 0 +#define UF2_CS_FENCE_SHIFT 20 +#define UF2_VFE_FENCE_SHIFT 10 +#define UF2_SF_FENCE_SHIFT 0 + +/* for BRW_STATE_BASE_ADDRESS */ +#define BASE_ADDRESS_MODIFY (1 << 0) + +/* for BRW_3DSTATE_PIPELINED_POINTERS */ +#define BRW_GS_DISABLE 0 +#define BRW_GS_ENABLE 1 +#define BRW_CLIP_DISABLE 0 +#define BRW_CLIP_ENABLE 1 + +/* for BRW_PIPE_CONTROL */ +#define BRW_PIPE_CONTROL_NOWRITE (0 << 14) +#define BRW_PIPE_CONTROL_WRITE_QWORD (1 << 14) +#define BRW_PIPE_CONTROL_WRITE_DEPTH (2 << 14) +#define BRW_PIPE_CONTROL_WRITE_TIME (3 << 14) +#define BRW_PIPE_CONTROL_DEPTH_STALL (1 << 13) +#define BRW_PIPE_CONTROL_WC_FLUSH (1 << 12) +#define BRW_PIPE_CONTROL_IS_FLUSH (1 << 11) +#define BRW_PIPE_CONTROL_TC_FLUSH (1 << 10) +#define BRW_PIPE_CONTROL_NOTIFY_ENABLE (1 << 8) +#define BRW_PIPE_CONTROL_GLOBAL_GTT (1 << 2) +#define BRW_PIPE_CONTROL_LOCAL_PGTT (0 << 2) +#define BRW_PIPE_CONTROL_DEPTH_CACHE_FLUSH (1 << 0) + +/* VERTEX_BUFFER_STATE Structure */ +#define VB0_BUFFER_INDEX_SHIFT 27 +#define GEN6_VB0_BUFFER_INDEX_SHIFT 26 +#define VB0_VERTEXDATA (0 << 26) +#define VB0_INSTANCEDATA (1 << 26) +#define GEN6_VB0_VERTEXDATA (0 << 20) +#define GEN6_VB0_INSTANCEDATA (1 << 20) +#define VB0_BUFFER_PITCH_SHIFT 0 + +/* VERTEX_ELEMENT_STATE Structure */ +#define VE0_VERTEX_BUFFER_INDEX_SHIFT 27 +#define GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT 26 /* for GEN6 */ +#define VE0_VALID (1 << 26) +#define GEN6_VE0_VALID (1 << 25) /* for GEN6 */ +#define VE0_FORMAT_SHIFT 16 +#define VE0_OFFSET_SHIFT 0 +#define VE1_VFCOMPONENT_0_SHIFT 28 +#define VE1_VFCOMPONENT_1_SHIFT 24 +#define VE1_VFCOMPONENT_2_SHIFT 20 +#define VE1_VFCOMPONENT_3_SHIFT 16 +#define VE1_DESTINATION_ELEMENT_OFFSET_SHIFT 0 + +/* 3DPRIMITIVE bits */ +#define BRW_3DPRIMITIVE_VERTEX_SEQUENTIAL (0 << 15) +#define BRW_3DPRIMITIVE_VERTEX_RANDOM (1 << 15) +/* Primitive types are in brw_defines.h */ +#define BRW_3DPRIMITIVE_TOPOLOGY_SHIFT 10 + +#define BRW_SVG_CTL 0x7400 + +#define BRW_SVG_CTL_GS_BA (0 << 8) +#define BRW_SVG_CTL_SS_BA (1 << 8) +#define BRW_SVG_CTL_IO_BA (2 << 8) +#define BRW_SVG_CTL_GS_AUB (3 << 8) +#define BRW_SVG_CTL_IO_AUB (4 << 8) +#define BRW_SVG_CTL_SIP (5 << 8) + +#define BRW_SVG_RDATA 0x7404 +#define BRW_SVG_WORK_CTL 0x7408 + +#define BRW_VF_CTL 0x7500 + +#define BRW_VF_CTL_SNAPSHOT_COMPLETE (1 << 31) +#define BRW_VF_CTL_SNAPSHOT_MUX_SELECT_THREADID (0 << 8) +#define BRW_VF_CTL_SNAPSHOT_MUX_SELECT_VF_DEBUG (1 << 8) +#define BRW_VF_CTL_SNAPSHOT_TYPE_VERTEX_SEQUENCE (0 << 4) +#define BRW_VF_CTL_SNAPSHOT_TYPE_VERTEX_INDEX (1 << 4) +#define BRW_VF_CTL_SKIP_INITIAL_PRIMITIVES (1 << 3) +#define BRW_VF_CTL_MAX_PRIMITIVES_LIMIT_ENABLE (1 << 2) +#define BRW_VF_CTL_VERTEX_RANGE_LIMIT_ENABLE (1 << 1) +#define BRW_VF_CTL_SNAPSHOT_ENABLE (1 << 0) + +#define BRW_VF_STRG_VAL 0x7504 +#define BRW_VF_STR_VL_OVR 0x7508 +#define BRW_VF_VC_OVR 0x750c +#define BRW_VF_STR_PSKIP 0x7510 +#define BRW_VF_MAX_PRIM 0x7514 +#define BRW_VF_RDATA 0x7518 + +#define BRW_VS_CTL 0x7600 +#define BRW_VS_CTL_SNAPSHOT_COMPLETE (1 << 31) +#define BRW_VS_CTL_SNAPSHOT_MUX_VERTEX_0 (0 << 8) +#define BRW_VS_CTL_SNAPSHOT_MUX_VERTEX_1 (1 << 8) +#define BRW_VS_CTL_SNAPSHOT_MUX_VALID_COUNT (2 << 8) +#define BRW_VS_CTL_SNAPSHOT_MUX_VS_KERNEL_POINTER (3 << 8) +#define BRW_VS_CTL_SNAPSHOT_ALL_THREADS (1 << 2) +#define BRW_VS_CTL_THREAD_SNAPSHOT_ENABLE (1 << 1) +#define BRW_VS_CTL_SNAPSHOT_ENABLE (1 << 0) + +#define BRW_VS_STRG_VAL 0x7604 +#define BRW_VS_RDATA 0x7608 + +#define BRW_SF_CTL 0x7b00 +#define BRW_SF_CTL_SNAPSHOT_COMPLETE (1 << 31) +#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_0_FF_ID (0 << 8) +#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_0_REL_COUNT (1 << 8) +#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_1_FF_ID (2 << 8) +#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_1_REL_COUNT (3 << 8) +#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_2_FF_ID (4 << 8) +#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_2_REL_COUNT (5 << 8) +#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_COUNT (6 << 8) +#define BRW_SF_CTL_SNAPSHOT_MUX_SF_KERNEL_POINTER (7 << 8) +#define BRW_SF_CTL_MIN_MAX_PRIMITIVE_RANGE_ENABLE (1 << 4) +#define BRW_SF_CTL_DEBUG_CLIP_RECTANGLE_ENABLE (1 << 3) +#define BRW_SF_CTL_SNAPSHOT_ALL_THREADS (1 << 2) +#define BRW_SF_CTL_THREAD_SNAPSHOT_ENABLE (1 << 1) +#define BRW_SF_CTL_SNAPSHOT_ENABLE (1 << 0) + +#define BRW_SF_STRG_VAL 0x7b04 +#define BRW_SF_RDATA 0x7b18 + +#define BRW_WIZ_CTL 0x7c00 +#define BRW_WIZ_CTL_SNAPSHOT_COMPLETE (1 << 31) +#define BRW_WIZ_CTL_SUBSPAN_INSTANCE_SHIFT 16 +#define BRW_WIZ_CTL_SNAPSHOT_MUX_WIZ_KERNEL_POINTER (0 << 8) +#define BRW_WIZ_CTL_SNAPSHOT_MUX_SUBSPAN_INSTANCE (1 << 8) +#define BRW_WIZ_CTL_SNAPSHOT_MUX_PRIMITIVE_SEQUENCE (2 << 8) +#define BRW_WIZ_CTL_SINGLE_SUBSPAN_DISPATCH (1 << 6) +#define BRW_WIZ_CTL_IGNORE_COLOR_SCOREBOARD_STALLS (1 << 5) +#define BRW_WIZ_CTL_ENABLE_SUBSPAN_INSTANCE_COMPARE (1 << 4) +#define BRW_WIZ_CTL_USE_UPSTREAM_SNAPSHOT_FLAG (1 << 3) +#define BRW_WIZ_CTL_SNAPSHOT_ALL_THREADS (1 << 2) +#define BRW_WIZ_CTL_THREAD_SNAPSHOT_ENABLE (1 << 1) +#define BRW_WIZ_CTL_SNAPSHOT_ENABLE (1 << 0) + +#define BRW_WIZ_STRG_VAL 0x7c04 +#define BRW_WIZ_RDATA 0x7c18 + +#define BRW_TS_CTL 0x7e00 +#define BRW_TS_CTL_SNAPSHOT_COMPLETE (1 << 31) +#define BRW_TS_CTL_SNAPSHOT_MESSAGE_ERROR (0 << 8) +#define BRW_TS_CTL_SNAPSHOT_INTERFACE_DESCRIPTOR (3 << 8) +#define BRW_TS_CTL_SNAPSHOT_ALL_CHILD_THREADS (1 << 2) +#define BRW_TS_CTL_SNAPSHOT_ALL_ROOT_THREADS (1 << 1) +#define BRW_TS_CTL_SNAPSHOT_ENABLE (1 << 0) + +#define BRW_TS_STRG_VAL 0x7e04 +#define BRW_TS_RDATA 0x7e08 + +#define BRW_TD_CTL 0x8000 +#define BRW_TD_CTL_MUX_SHIFT 8 +#define BRW_TD_CTL_EXTERNAL_HALT_R0_DEBUG_MATCH (1 << 7) +#define BRW_TD_CTL_FORCE_EXTERNAL_HALT (1 << 6) +#define BRW_TD_CTL_EXCEPTION_MASK_OVERRIDE (1 << 5) +#define BRW_TD_CTL_FORCE_THREAD_BREAKPOINT_ENABLE (1 << 4) +#define BRW_TD_CTL_BREAKPOINT_ENABLE (1 << 2) +#define BRW_TD_CTL2 0x8004 +#define BRW_TD_CTL2_ILLEGAL_OPCODE_EXCEPTION_OVERRIDE (1 << 28) +#define BRW_TD_CTL2_MASKSTACK_EXCEPTION_OVERRIDE (1 << 26) +#define BRW_TD_CTL2_SOFTWARE_EXCEPTION_OVERRIDE (1 << 25) +#define BRW_TD_CTL2_ACTIVE_THREAD_LIMIT_SHIFT 16 +#define BRW_TD_CTL2_ACTIVE_THREAD_LIMIT_ENABLE (1 << 8) +#define BRW_TD_CTL2_THREAD_SPAWNER_EXECUTION_MASK_ENABLE (1 << 7) +#define BRW_TD_CTL2_WIZ_EXECUTION_MASK_ENABLE (1 << 6) +#define BRW_TD_CTL2_SF_EXECUTION_MASK_ENABLE (1 << 5) +#define BRW_TD_CTL2_CLIPPER_EXECUTION_MASK_ENABLE (1 << 4) +#define BRW_TD_CTL2_GS_EXECUTION_MASK_ENABLE (1 << 3) +#define BRW_TD_CTL2_VS_EXECUTION_MASK_ENABLE (1 << 0) +#define BRW_TD_VF_VS_EMSK 0x8008 +#define BRW_TD_GS_EMSK 0x800c +#define BRW_TD_CLIP_EMSK 0x8010 +#define BRW_TD_SF_EMSK 0x8014 +#define BRW_TD_WIZ_EMSK 0x8018 +#define BRW_TD_0_6_EHTRG_VAL 0x801c +#define BRW_TD_0_7_EHTRG_VAL 0x8020 +#define BRW_TD_0_6_EHTRG_MSK 0x8024 +#define BRW_TD_0_7_EHTRG_MSK 0x8028 +#define BRW_TD_RDATA 0x802c +#define BRW_TD_TS_EMSK 0x8030 + +#define BRW_EU_CTL 0x8800 +#define BRW_EU_CTL_SELECT_SHIFT 16 +#define BRW_EU_CTL_DATA_MUX_SHIFT 8 +#define BRW_EU_ATT_0 0x8810 +#define BRW_EU_ATT_1 0x8814 +#define BRW_EU_ATT_DATA_0 0x8820 +#define BRW_EU_ATT_DATA_1 0x8824 +#define BRW_EU_ATT_CLR_0 0x8830 +#define BRW_EU_ATT_CLR_1 0x8834 +#define BRW_EU_RDATA 0x8840 + +/* End regs for broadwater */ + diff --git a/driver/xf86-video-intel/src/i965_render.c b/driver/xf86-video-intel/src/i965_render.c index e2a32d1e6..a4c0f678b 100644 --- a/driver/xf86-video-intel/src/i965_render.c +++ b/driver/xf86-video-intel/src/i965_render.c @@ -35,38 +35,23 @@ #include <assert.h> #include "xf86.h" -#include "i830.h" -#include "i915_reg.h" +#include "intel.h" +#include "i830_reg.h" +#include "i965_reg.h" /* bring in brw structs */ #include "brw_defines.h" #include "brw_structs.h" -/* 24 = 4 vertices/composite * 3 texcoords/vertex * 2 floats/texcoord - * - * This is an upper-bound based on the case of a non-affine - * transformation and with a mask, but useful for sizing all cases for - * simplicity. - */ -#define VERTEX_FLOATS_PER_COMPOSITE 24 -#define VERTEX_BUFFER_SIZE (256 * VERTEX_FLOATS_PER_COMPOSITE) +// refer vol2, 3d rasterization 3.8.1 -struct blendinfo { +/* defined in brw_defines.h */ +static const struct blendinfo { Bool dst_alpha; Bool src_alpha; uint32_t src_blend; uint32_t dst_blend; -}; - -struct formatinfo { - int fmt; - uint32_t card_fmt; -}; - -// refer vol2, 3d rasterization 3.8.1 - -/* defined in brw_defines.h */ -static struct blendinfo i965_blend_op[] = { +} i965_blend_op[] = { /* Clear */ {0, 0, BRW_BLENDFACTOR_ZERO, BRW_BLENDFACTOR_ZERO}, /* Src */ @@ -107,14 +92,23 @@ static struct blendinfo i965_blend_op[] = { /* FIXME: surface format defined in brw_defines.h, shared Sampling engine * 1.7.2 */ -static struct formatinfo i965_tex_formats[] = { +static const struct formatinfo { + int fmt; + uint32_t card_fmt; +} i965_tex_formats[] = { + {PICT_a8, BRW_SURFACEFORMAT_A8_UNORM}, {PICT_a8r8g8b8, BRW_SURFACEFORMAT_B8G8R8A8_UNORM}, {PICT_x8r8g8b8, BRW_SURFACEFORMAT_B8G8R8X8_UNORM}, {PICT_a8b8g8r8, BRW_SURFACEFORMAT_R8G8B8A8_UNORM}, {PICT_x8b8g8r8, BRW_SURFACEFORMAT_R8G8B8X8_UNORM}, + {PICT_r8g8b8, BRW_SURFACEFORMAT_R8G8B8_UNORM}, {PICT_r5g6b5, BRW_SURFACEFORMAT_B5G6R5_UNORM}, {PICT_a1r5g5b5, BRW_SURFACEFORMAT_B5G5R5A1_UNORM}, - {PICT_a8, BRW_SURFACEFORMAT_A8_UNORM}, + {PICT_a2r10g10b10, BRW_SURFACEFORMAT_B10G10R10A2_UNORM}, + {PICT_x2r10g10b10, BRW_SURFACEFORMAT_B10G10R10X2_UNORM}, + {PICT_a2b10g10r10, BRW_SURFACEFORMAT_R10G10B10A2_UNORM}, + {PICT_x2r10g10b10, BRW_SURFACEFORMAT_B10G10R10X2_UNORM}, + {PICT_a4r4g4b4, BRW_SURFACEFORMAT_B4G4R4A4_UNORM}, }; static void i965_get_blend_cntl(int op, PicturePtr mask, uint32_t dst_format, @@ -149,38 +143,33 @@ static void i965_get_blend_cntl(int op, PicturePtr mask, uint32_t dst_format, } -static Bool i965_get_dest_format(PicturePtr dest_picture, uint32_t * dst_format) +static uint32_t i965_get_dest_format(PicturePtr dest_picture) { - ScrnInfoPtr scrn = xf86Screens[dest_picture->pDrawable->pScreen->myNum]; - switch (dest_picture->format) { case PICT_a8r8g8b8: case PICT_x8r8g8b8: - *dst_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM; + return BRW_SURFACEFORMAT_B8G8R8A8_UNORM; + case PICT_a8b8g8r8: + case PICT_x8b8g8r8: + return BRW_SURFACEFORMAT_R8G8B8A8_UNORM; break; - case PICT_r5g6b5: - *dst_format = BRW_SURFACEFORMAT_B5G6R5_UNORM; - break; - case PICT_a1r5g5b5: - *dst_format = BRW_SURFACEFORMAT_B5G5R5A1_UNORM; + case PICT_a2r10g10b10: + case PICT_x2r10g10b10: + return BRW_SURFACEFORMAT_B10G10R10A2_UNORM; break; + case PICT_r5g6b5: + return BRW_SURFACEFORMAT_B5G6R5_UNORM; case PICT_x1r5g5b5: - *dst_format = BRW_SURFACEFORMAT_B5G5R5X1_UNORM; - break; + case PICT_a1r5g5b5: + return BRW_SURFACEFORMAT_B5G5R5A1_UNORM; case PICT_a8: - *dst_format = BRW_SURFACEFORMAT_A8_UNORM; - break; + return BRW_SURFACEFORMAT_A8_UNORM; case PICT_a4r4g4b4: case PICT_x4r4g4b4: - *dst_format = BRW_SURFACEFORMAT_B4G4R4A4_UNORM; - break; + return BRW_SURFACEFORMAT_B4G4R4A4_UNORM; default: - intel_debug_fallback(scrn, "Unsupported dest format 0x%x\n", - (int)dest_picture->format); - return FALSE; + return -1; } - - return TRUE; } Bool @@ -191,7 +180,7 @@ i965_check_composite(int op, int width, int height) { ScrnInfoPtr scrn = xf86Screens[dest_picture->pDrawable->pScreen->myNum]; - uint32_t tmp1; + intel_screen_private *intel = intel_get_screen_private(scrn); /* Check for unsupported compositing operations. */ if (op >= sizeof(i965_blend_op) / sizeof(i965_blend_op[0])) { @@ -216,8 +205,9 @@ i965_check_composite(int op, } } - if (!i965_get_dest_format(dest_picture, &tmp1)) { - intel_debug_fallback(scrn, "Get Color buffer format\n"); + if (i965_get_dest_format(dest_picture) == -1) { + intel_debug_fallback(scrn, "Usupported Color buffer format 0x%x\n", + (int)dest_picture->format); return FALSE; } @@ -299,29 +289,6 @@ i965_check_composite_texture(ScreenPtr screen, PicturePtr picture) #define URB_SF_ENTRY_SIZE 2 #define URB_SF_ENTRIES 1 -static const uint32_t sip_kernel_static[][4] = { -/* wait (1) a0<1>UW a145<0,1,0>UW { align1 + } */ - {0x00000030, 0x20000108, 0x00001220, 0x00000000}, -/* nop (4) g0<1>UD { align1 + } */ - {0x0040007e, 0x20000c21, 0x00690000, 0x00000000}, -/* nop (4) g0<1>UD { align1 + } */ - {0x0040007e, 0x20000c21, 0x00690000, 0x00000000}, -/* nop (4) g0<1>UD { align1 + } */ - {0x0040007e, 0x20000c21, 0x00690000, 0x00000000}, -/* nop (4) g0<1>UD { align1 + } */ - {0x0040007e, 0x20000c21, 0x00690000, 0x00000000}, -/* nop (4) g0<1>UD { align1 + } */ - {0x0040007e, 0x20000c21, 0x00690000, 0x00000000}, -/* nop (4) g0<1>UD { align1 + } */ - {0x0040007e, 0x20000c21, 0x00690000, 0x00000000}, -/* nop (4) g0<1>UD { align1 + } */ - {0x0040007e, 0x20000c21, 0x00690000, 0x00000000}, -/* nop (4) g0<1>UD { align1 + } */ - {0x0040007e, 0x20000c21, 0x00690000, 0x00000000}, -/* nop (4) g0<1>UD { align1 + } */ - {0x0040007e, 0x20000c21, 0x00690000, 0x00000000}, -}; - /* * this program computes dA/dx and dA/dy for the texture coordinates along * with the base texture coordinate. It was extracted from the Mesa driver @@ -499,31 +466,155 @@ static const uint32_t ps_kernel_masknoca_projective_static_gen5[][4] = { #include "exa_wm_write.g4b.gen5" }; -#define WM_STATE_DECL(kernel) \ - struct brw_wm_unit_state wm_state_ ## kernel[SAMPLER_STATE_FILTER_COUNT] \ - [SAMPLER_STATE_EXTEND_COUNT] \ - [SAMPLER_STATE_FILTER_COUNT] \ - [SAMPLER_STATE_EXTEND_COUNT] +/* programs for GEN6 */ +static const uint32_t ps_kernel_nomask_affine_static_gen6[][4] = { +#include "exa_wm_src_affine.g6b" +#include "exa_wm_src_sample_argb.g6b" +#include "exa_wm_write.g6b" +}; + +static const uint32_t ps_kernel_nomask_projective_static_gen6[][4] = { +#include "exa_wm_src_projective.g6b" +#include "exa_wm_src_sample_argb.g6b" +#include "exa_wm_write.g6b" +}; + +static const uint32_t ps_kernel_maskca_affine_static_gen6[][4] = { +#include "exa_wm_src_affine.g6b" +#include "exa_wm_src_sample_argb.g6b" +#include "exa_wm_mask_affine.g6b" +#include "exa_wm_mask_sample_argb.g6b" +#include "exa_wm_ca.g6b" +#include "exa_wm_write.g6b" +}; + +static const uint32_t ps_kernel_maskca_projective_static_gen6[][4] = { +#include "exa_wm_src_projective.g6b" +#include "exa_wm_src_sample_argb.g6b" +#include "exa_wm_mask_projective.g6b" +#include "exa_wm_mask_sample_argb.g6b" +#include "exa_wm_ca.g4b.gen5" +#include "exa_wm_write.g6b" +}; + +static const uint32_t ps_kernel_maskca_srcalpha_affine_static_gen6[][4] = { +#include "exa_wm_src_affine.g6b" +#include "exa_wm_src_sample_a.g6b" +#include "exa_wm_mask_affine.g6b" +#include "exa_wm_mask_sample_argb.g6b" +#include "exa_wm_ca_srcalpha.g6b" +#include "exa_wm_write.g6b" +}; + +static const uint32_t ps_kernel_maskca_srcalpha_projective_static_gen6[][4] = { +#include "exa_wm_src_projective.g6b" +#include "exa_wm_src_sample_a.g6b" +#include "exa_wm_mask_projective.g6b" +#include "exa_wm_mask_sample_argb.g6b" +#include "exa_wm_ca_srcalpha.g6b" +#include "exa_wm_write.g6b" +}; + +static const uint32_t ps_kernel_masknoca_affine_static_gen6[][4] = { +#include "exa_wm_src_affine.g6b" +#include "exa_wm_src_sample_argb.g6b" +#include "exa_wm_mask_affine.g6b" +#include "exa_wm_mask_sample_a.g6b" +#include "exa_wm_noca.g6b" +#include "exa_wm_write.g6b" +}; + +static const uint32_t ps_kernel_masknoca_projective_static_gen6[][4] = { +#include "exa_wm_src_projective.g6b" +#include "exa_wm_src_sample_argb.g6b" +#include "exa_wm_mask_projective.g6b" +#include "exa_wm_mask_sample_a.g6b" +#include "exa_wm_noca.g6b" +#include "exa_wm_write.g6b" +}; + +/* programs for GEN7 */ +static const uint32_t ps_kernel_nomask_affine_static_gen7[][4] = { +#include "exa_wm_src_affine.g7b" +#include "exa_wm_src_sample_argb.g7b" +#include "exa_wm_write.g7b" +}; + +static const uint32_t ps_kernel_nomask_projective_static_gen7[][4] = { +#include "exa_wm_src_projective.g7b" +#include "exa_wm_src_sample_argb.g7b" +#include "exa_wm_write.g7b" +}; + +static const uint32_t ps_kernel_maskca_affine_static_gen7[][4] = { +#include "exa_wm_src_affine.g7b" +#include "exa_wm_src_sample_argb.g7b" +#include "exa_wm_mask_affine.g7b" +#include "exa_wm_mask_sample_argb.g7b" +#include "exa_wm_ca.g6b" +#include "exa_wm_write.g7b" +}; + +static const uint32_t ps_kernel_maskca_projective_static_gen7[][4] = { +#include "exa_wm_src_projective.g7b" +#include "exa_wm_src_sample_argb.g7b" +#include "exa_wm_mask_projective.g7b" +#include "exa_wm_mask_sample_argb.g7b" +#include "exa_wm_ca.g4b.gen5" +#include "exa_wm_write.g7b" +}; + +static const uint32_t ps_kernel_maskca_srcalpha_affine_static_gen7[][4] = { +#include "exa_wm_src_affine.g7b" +#include "exa_wm_src_sample_a.g7b" +#include "exa_wm_mask_affine.g7b" +#include "exa_wm_mask_sample_argb.g7b" +#include "exa_wm_ca_srcalpha.g6b" +#include "exa_wm_write.g7b" +}; + +static const uint32_t ps_kernel_maskca_srcalpha_projective_static_gen7[][4] = { +#include "exa_wm_src_projective.g7b" +#include "exa_wm_src_sample_a.g7b" +#include "exa_wm_mask_projective.g7b" +#include "exa_wm_mask_sample_argb.g7b" +#include "exa_wm_ca_srcalpha.g6b" +#include "exa_wm_write.g7b" +}; + +static const uint32_t ps_kernel_masknoca_affine_static_gen7[][4] = { +#include "exa_wm_src_affine.g7b" +#include "exa_wm_src_sample_argb.g7b" +#include "exa_wm_mask_affine.g7b" +#include "exa_wm_mask_sample_a.g7b" +#include "exa_wm_noca.g6b" +#include "exa_wm_write.g7b" +}; + +static const uint32_t ps_kernel_masknoca_projective_static_gen7[][4] = { +#include "exa_wm_src_projective.g7b" +#include "exa_wm_src_sample_argb.g7b" +#include "exa_wm_mask_projective.g7b" +#include "exa_wm_mask_sample_a.g7b" +#include "exa_wm_noca.g6b" +#include "exa_wm_write.g7b" +}; -/* Many of the fields in the state structure must be aligned to a - * 64-byte boundary, (or a 32-byte boundary, but 64 is good enough for - * those too). - */ -#define PAD64_MULTI(previous, idx, factor) char previous ## _pad ## idx [(64 - (sizeof(struct previous) * (factor)) % 64) % 64] -#define PAD64(previous, idx) PAD64_MULTI(previous, idx, 1) typedef enum { - SAMPLER_STATE_FILTER_NEAREST, - SAMPLER_STATE_FILTER_BILINEAR, - SAMPLER_STATE_FILTER_COUNT + SS_INVALID_FILTER = -1, + SS_FILTER_NEAREST, + SS_FILTER_BILINEAR, + FILTER_COUNT, } sampler_state_filter_t; typedef enum { - SAMPLER_STATE_EXTEND_NONE, - SAMPLER_STATE_EXTEND_REPEAT, - SAMPLER_STATE_EXTEND_PAD, - SAMPLER_STATE_EXTEND_REFLECT, - SAMPLER_STATE_EXTEND_COUNT + SS_INVALID_EXTEND = -1, + SS_EXTEND_NONE, + SS_EXTEND_REPEAT, + SS_EXTEND_PAD, + SS_EXTEND_REFLECT, + EXTEND_COUNT, } sampler_state_extend_t; typedef enum { @@ -535,18 +626,18 @@ typedef enum { WM_KERNEL_MASKCA_SRCALPHA_PROJECTIVE, WM_KERNEL_MASKNOCA_AFFINE, WM_KERNEL_MASKNOCA_PROJECTIVE, - WM_KERNEL_COUNT + KERNEL_COUNT } wm_kernel_t; #define KERNEL(kernel_enum, kernel, masked) \ [kernel_enum] = {&kernel, sizeof(kernel), masked} struct wm_kernel_info { - void *data; + const void *data; unsigned int size; Bool has_mask; }; -static struct wm_kernel_info wm_kernels[] = { +static const struct wm_kernel_info wm_kernels_gen4[] = { KERNEL(WM_KERNEL_NOMASK_AFFINE, ps_kernel_nomask_affine_static, FALSE), KERNEL(WM_KERNEL_NOMASK_PROJECTIVE, @@ -565,7 +656,7 @@ static struct wm_kernel_info wm_kernels[] = { ps_kernel_masknoca_projective_static, TRUE), }; -static struct wm_kernel_info wm_kernels_gen5[] = { +static const struct wm_kernel_info wm_kernels_gen5[] = { KERNEL(WM_KERNEL_NOMASK_AFFINE, ps_kernel_nomask_affine_static_gen5, FALSE), KERNEL(WM_KERNEL_NOMASK_PROJECTIVE, @@ -584,6 +675,44 @@ static struct wm_kernel_info wm_kernels_gen5[] = { ps_kernel_masknoca_projective_static_gen5, TRUE), }; +static const struct wm_kernel_info wm_kernels_gen6[] = { + KERNEL(WM_KERNEL_NOMASK_AFFINE, + ps_kernel_nomask_affine_static_gen6, FALSE), + KERNEL(WM_KERNEL_NOMASK_PROJECTIVE, + ps_kernel_nomask_projective_static_gen6, FALSE), + KERNEL(WM_KERNEL_MASKCA_AFFINE, + ps_kernel_maskca_affine_static_gen6, TRUE), + KERNEL(WM_KERNEL_MASKCA_PROJECTIVE, + ps_kernel_maskca_projective_static_gen6, TRUE), + KERNEL(WM_KERNEL_MASKCA_SRCALPHA_AFFINE, + ps_kernel_maskca_srcalpha_affine_static_gen6, TRUE), + KERNEL(WM_KERNEL_MASKCA_SRCALPHA_PROJECTIVE, + ps_kernel_maskca_srcalpha_projective_static_gen6, TRUE), + KERNEL(WM_KERNEL_MASKNOCA_AFFINE, + ps_kernel_masknoca_affine_static_gen6, TRUE), + KERNEL(WM_KERNEL_MASKNOCA_PROJECTIVE, + ps_kernel_masknoca_projective_static_gen6, TRUE), +}; + +static const struct wm_kernel_info wm_kernels_gen7[] = { + KERNEL(WM_KERNEL_NOMASK_AFFINE, + ps_kernel_nomask_affine_static_gen7, FALSE), + KERNEL(WM_KERNEL_NOMASK_PROJECTIVE, + ps_kernel_nomask_projective_static_gen7, FALSE), + KERNEL(WM_KERNEL_MASKCA_AFFINE, + ps_kernel_maskca_affine_static_gen7, TRUE), + KERNEL(WM_KERNEL_MASKCA_PROJECTIVE, + ps_kernel_maskca_projective_static_gen7, TRUE), + KERNEL(WM_KERNEL_MASKCA_SRCALPHA_AFFINE, + ps_kernel_maskca_srcalpha_affine_static_gen7, TRUE), + KERNEL(WM_KERNEL_MASKCA_SRCALPHA_PROJECTIVE, + ps_kernel_maskca_srcalpha_projective_static_gen7, TRUE), + KERNEL(WM_KERNEL_MASKNOCA_AFFINE, + ps_kernel_masknoca_affine_static_gen7, TRUE), + KERNEL(WM_KERNEL_MASKNOCA_PROJECTIVE, + ps_kernel_masknoca_projective_static_gen7, TRUE), +}; + #undef KERNEL typedef struct _brw_cc_unit_state_padded { @@ -591,28 +720,25 @@ typedef struct _brw_cc_unit_state_padded { char pad[64 - sizeof(struct brw_cc_unit_state)]; } brw_cc_unit_state_padded; -typedef struct brw_surface_state_padded { - struct brw_surface_state state; - char pad[32 - sizeof(struct brw_surface_state)]; -} brw_surface_state_padded; +#ifndef MAX +#define MAX(a, b) ((a) > (b) ? (a) : (b)) +#endif +#define SURFACE_STATE_PADDED_SIZE ALIGN(MAX(sizeof(struct brw_surface_state), sizeof(struct gen7_surface_state)), 32) struct gen4_cc_unit_state { /* Index by [src_blend][dst_blend] */ - brw_cc_unit_state_padded cc_state[BRW_BLENDFACTOR_COUNT] - [BRW_BLENDFACTOR_COUNT]; + brw_cc_unit_state_padded cc_state[BRW_BLENDFACTOR_COUNT][BRW_BLENDFACTOR_COUNT]; }; -typedef float gen4_vertex_buffer[VERTEX_BUFFER_SIZE]; - typedef struct gen4_composite_op { int op; - drm_intel_bo *binding_table_bo; sampler_state_filter_t src_filter; sampler_state_filter_t mask_filter; sampler_state_extend_t src_extend; sampler_state_extend_t mask_extend; Bool is_affine; wm_kernel_t wm_kernel; + int vertex_id; } gen4_composite_op; /** Private data for gen4 render accel implementation. */ @@ -621,22 +747,24 @@ struct gen4_render_state { drm_intel_bo *sf_state_bo; drm_intel_bo *sf_mask_state_bo; drm_intel_bo *cc_state_bo; - drm_intel_bo *wm_state_bo[WM_KERNEL_COUNT] - [SAMPLER_STATE_FILTER_COUNT] - [SAMPLER_STATE_EXTEND_COUNT] - [SAMPLER_STATE_FILTER_COUNT] - [SAMPLER_STATE_EXTEND_COUNT]; - drm_intel_bo *wm_kernel_bo[WM_KERNEL_COUNT]; - - drm_intel_bo *sip_kernel_bo; - dri_bo *vertex_buffer_bo; - + drm_intel_bo *wm_state_bo[KERNEL_COUNT] + [FILTER_COUNT] [EXTEND_COUNT] + [FILTER_COUNT] [EXTEND_COUNT]; + drm_intel_bo *wm_kernel_bo[KERNEL_COUNT]; + + drm_intel_bo *cc_vp_bo; + drm_intel_bo *gen6_blend_bo; + drm_intel_bo *gen6_depth_stencil_bo; + drm_intel_bo *ps_sampler_state_bo[FILTER_COUNT] + [EXTEND_COUNT] + [FILTER_COUNT] + [EXTEND_COUNT]; gen4_composite_op composite_op; - - int vb_offset; - int vertex_size; }; +static void gen6_emit_composite_state(struct intel_screen_private *intel); +static void gen6_render_state_init(ScrnInfoPtr scrn); + /** * Sets up the SF state pointing at an SF kernel. * @@ -644,10 +772,9 @@ struct gen4_render_state { * calculate dA/dx and dA/dy. Hand these interpolation coefficients * back to SF which then hands pixels off to WM. */ -static drm_intel_bo *gen4_create_sf_state(ScrnInfoPtr scrn, +static drm_intel_bo *gen4_create_sf_state(intel_screen_private *intel, drm_intel_bo * kernel_bo) { - intel_screen_private *intel = intel_get_screen_private(scrn); struct brw_sf_unit_state *sf_state; drm_intel_bo *sf_state_bo; @@ -682,7 +809,6 @@ static drm_intel_bo *gen4_create_sf_state(ScrnInfoPtr scrn, sf_state->thread4.max_threads = SF_MAX_THREADS - 1; sf_state->thread4.urb_entry_allocation_size = URB_SF_ENTRY_SIZE - 1; sf_state->thread4.nr_urb_entries = URB_SF_ENTRIES; - sf_state->thread4.stats_enable = 1; sf_state->sf5.viewport_transform = FALSE; /* skip viewport */ sf_state->sf6.cull_mode = BRW_CULLMODE_NONE; sf_state->sf6.scissor = 0; @@ -695,7 +821,7 @@ static drm_intel_bo *gen4_create_sf_state(ScrnInfoPtr scrn, return sf_state_bo; } -static drm_intel_bo *sampler_border_color_create(ScrnInfoPtr scrn) +static drm_intel_bo *sampler_border_color_create(intel_screen_private *intel) { struct brw_sampler_legacy_border_color sampler_border_color; @@ -706,14 +832,14 @@ static drm_intel_bo *sampler_border_color_create(ScrnInfoPtr scrn) sampler_border_color.color[2] = 0; /* B */ sampler_border_color.color[3] = 0; /* A */ - return intel_bo_alloc_for_data(scrn, + return intel_bo_alloc_for_data(intel, &sampler_border_color, sizeof(sampler_border_color), "gen4 render sampler border color"); } static void -sampler_state_init(drm_intel_bo * sampler_state_bo, +gen4_sampler_state_init(drm_intel_bo * sampler_state_bo, struct brw_sampler_state *sampler_state, sampler_state_filter_t filter, sampler_state_extend_t extend, @@ -735,11 +861,11 @@ sampler_state_init(drm_intel_bo * sampler_state_bo, switch (filter) { default: - case SAMPLER_STATE_FILTER_NEAREST: + case SS_FILTER_NEAREST: sampler_state->ss0.min_filter = BRW_MAPFILTER_NEAREST; sampler_state->ss0.mag_filter = BRW_MAPFILTER_NEAREST; break; - case SAMPLER_STATE_FILTER_BILINEAR: + case SS_FILTER_BILINEAR: sampler_state->ss0.min_filter = BRW_MAPFILTER_LINEAR; sampler_state->ss0.mag_filter = BRW_MAPFILTER_LINEAR; break; @@ -747,22 +873,22 @@ sampler_state_init(drm_intel_bo * sampler_state_bo, switch (extend) { default: - case SAMPLER_STATE_EXTEND_NONE: + case SS_EXTEND_NONE: sampler_state->ss1.r_wrap_mode = BRW_TEXCOORDMODE_CLAMP_BORDER; sampler_state->ss1.s_wrap_mode = BRW_TEXCOORDMODE_CLAMP_BORDER; sampler_state->ss1.t_wrap_mode = BRW_TEXCOORDMODE_CLAMP_BORDER; break; - case SAMPLER_STATE_EXTEND_REPEAT: + case SS_EXTEND_REPEAT: sampler_state->ss1.r_wrap_mode = BRW_TEXCOORDMODE_WRAP; sampler_state->ss1.s_wrap_mode = BRW_TEXCOORDMODE_WRAP; sampler_state->ss1.t_wrap_mode = BRW_TEXCOORDMODE_WRAP; break; - case SAMPLER_STATE_EXTEND_PAD: + case SS_EXTEND_PAD: sampler_state->ss1.r_wrap_mode = BRW_TEXCOORDMODE_CLAMP; sampler_state->ss1.s_wrap_mode = BRW_TEXCOORDMODE_CLAMP; sampler_state->ss1.t_wrap_mode = BRW_TEXCOORDMODE_CLAMP; break; - case SAMPLER_STATE_EXTEND_REFLECT: + case SS_EXTEND_REFLECT: sampler_state->ss1.r_wrap_mode = BRW_TEXCOORDMODE_MIRROR; sampler_state->ss1.s_wrap_mode = BRW_TEXCOORDMODE_MIRROR; sampler_state->ss1.t_wrap_mode = BRW_TEXCOORDMODE_MIRROR; @@ -778,18 +904,81 @@ sampler_state_init(drm_intel_bo * sampler_state_bo, sampler_state->ss3.chroma_key_enable = 0; /* disable chromakey */ } -static drm_intel_bo *gen4_create_sampler_state(ScrnInfoPtr scrn, - sampler_state_filter_t - src_filter, - sampler_state_extend_t - src_extend, - sampler_state_filter_t - mask_filter, - sampler_state_extend_t - mask_extend, +static void +gen7_sampler_state_init(drm_intel_bo * sampler_state_bo, + struct gen7_sampler_state *sampler_state, + sampler_state_filter_t filter, + sampler_state_extend_t extend, + drm_intel_bo * border_color_bo) +{ + uint32_t sampler_state_offset; + + sampler_state_offset = (char *)sampler_state - + (char *)sampler_state_bo->virtual; + + /* PS kernel use this sampler */ + memset(sampler_state, 0, sizeof(*sampler_state)); + + sampler_state->ss0.lod_preclamp = 1; /* GL mode */ + + /* We use the legacy mode to get the semantics specified by + * the Render extension. */ + sampler_state->ss0.default_color_mode = BRW_BORDER_COLOR_MODE_LEGACY; + + switch (filter) { + default: + case SS_FILTER_NEAREST: + sampler_state->ss0.min_filter = BRW_MAPFILTER_NEAREST; + sampler_state->ss0.mag_filter = BRW_MAPFILTER_NEAREST; + break; + case SS_FILTER_BILINEAR: + sampler_state->ss0.min_filter = BRW_MAPFILTER_LINEAR; + sampler_state->ss0.mag_filter = BRW_MAPFILTER_LINEAR; + break; + } + + switch (extend) { + default: + case SS_EXTEND_NONE: + sampler_state->ss3.r_wrap_mode = BRW_TEXCOORDMODE_CLAMP_BORDER; + sampler_state->ss3.s_wrap_mode = BRW_TEXCOORDMODE_CLAMP_BORDER; + sampler_state->ss3.t_wrap_mode = BRW_TEXCOORDMODE_CLAMP_BORDER; + break; + case SS_EXTEND_REPEAT: + sampler_state->ss3.r_wrap_mode = BRW_TEXCOORDMODE_WRAP; + sampler_state->ss3.s_wrap_mode = BRW_TEXCOORDMODE_WRAP; + sampler_state->ss3.t_wrap_mode = BRW_TEXCOORDMODE_WRAP; + break; + case SS_EXTEND_PAD: + sampler_state->ss3.r_wrap_mode = BRW_TEXCOORDMODE_CLAMP; + sampler_state->ss3.s_wrap_mode = BRW_TEXCOORDMODE_CLAMP; + sampler_state->ss3.t_wrap_mode = BRW_TEXCOORDMODE_CLAMP; + break; + case SS_EXTEND_REFLECT: + sampler_state->ss3.r_wrap_mode = BRW_TEXCOORDMODE_MIRROR; + sampler_state->ss3.s_wrap_mode = BRW_TEXCOORDMODE_MIRROR; + sampler_state->ss3.t_wrap_mode = BRW_TEXCOORDMODE_MIRROR; + break; + } + + sampler_state->ss2.default_color_pointer = + intel_emit_reloc(sampler_state_bo, sampler_state_offset + + offsetof(struct gen7_sampler_state, ss2), + border_color_bo, 0, + I915_GEM_DOMAIN_SAMPLER, 0) >> 5; + + sampler_state->ss3.chroma_key_enable = 0; /* disable chromakey */ +} + + + +static drm_intel_bo *gen4_create_sampler_state(intel_screen_private *intel, + sampler_state_filter_t src_filter, + sampler_state_extend_t src_extend, + sampler_state_filter_t mask_filter, + sampler_state_extend_t mask_extend, drm_intel_bo * border_color_bo) { - intel_screen_private *intel = intel_get_screen_private(scrn); drm_intel_bo *sampler_state_bo; struct brw_sampler_state *sampler_state; @@ -799,18 +988,65 @@ static drm_intel_bo *gen4_create_sampler_state(ScrnInfoPtr scrn, drm_intel_bo_map(sampler_state_bo, TRUE); sampler_state = sampler_state_bo->virtual; - sampler_state_init(sampler_state_bo, - &sampler_state[0], - src_filter, src_extend, border_color_bo); - sampler_state_init(sampler_state_bo, - &sampler_state[1], - mask_filter, mask_extend, border_color_bo); + gen4_sampler_state_init(sampler_state_bo, + &sampler_state[0], + src_filter, src_extend, border_color_bo); + gen4_sampler_state_init(sampler_state_bo, + &sampler_state[1], + mask_filter, mask_extend, border_color_bo); + + drm_intel_bo_unmap(sampler_state_bo); + + return sampler_state_bo; +} + +static drm_intel_bo * +gen7_create_sampler_state(intel_screen_private *intel, + sampler_state_filter_t src_filter, + sampler_state_extend_t src_extend, + sampler_state_filter_t mask_filter, + sampler_state_extend_t mask_extend, + drm_intel_bo * border_color_bo) +{ + drm_intel_bo *sampler_state_bo; + struct gen7_sampler_state *sampler_state; + + sampler_state_bo = + drm_intel_bo_alloc(intel->bufmgr, "gen7 sampler state", + sizeof(struct gen7_sampler_state) * 2, 4096); + drm_intel_bo_map(sampler_state_bo, TRUE); + sampler_state = sampler_state_bo->virtual; + + gen7_sampler_state_init(sampler_state_bo, + &sampler_state[0], + src_filter, src_extend, border_color_bo); + gen7_sampler_state_init(sampler_state_bo, + &sampler_state[1], + mask_filter, mask_extend, border_color_bo); drm_intel_bo_unmap(sampler_state_bo); return sampler_state_bo; } +static inline drm_intel_bo * +i965_create_sampler_state(intel_screen_private *intel, + sampler_state_filter_t src_filter, + sampler_state_extend_t src_extend, + sampler_state_filter_t mask_filter, + sampler_state_extend_t mask_extend, + drm_intel_bo * border_color_bo) +{ + if (INTEL_INFO(intel)->gen < 70) + return gen4_create_sampler_state(intel, src_filter, src_extend, + mask_filter, mask_extend, + border_color_bo); + return gen7_create_sampler_state(intel, src_filter, src_extend, + mask_filter, mask_extend, + border_color_bo); +} + + static void cc_state_init(drm_intel_bo * cc_state_bo, uint32_t cc_state_offset, @@ -852,109 +1088,103 @@ cc_state_init(drm_intel_bo * cc_state_bo, cc_state->cc6.dest_blend_factor = dst_blend; } -static drm_intel_bo *gen4_create_wm_state(ScrnInfoPtr scrn, +static drm_intel_bo *gen4_create_wm_state(intel_screen_private *intel, Bool has_mask, drm_intel_bo * kernel_bo, drm_intel_bo * sampler_bo) { - intel_screen_private *intel = intel_get_screen_private(scrn); - struct brw_wm_unit_state *wm_state; + struct brw_wm_unit_state *state; drm_intel_bo *wm_state_bo; wm_state_bo = drm_intel_bo_alloc(intel->bufmgr, "gen4 WM state", - sizeof(*wm_state), 4096); + sizeof(*state), 4096); drm_intel_bo_map(wm_state_bo, TRUE); - wm_state = wm_state_bo->virtual; + state = wm_state_bo->virtual; - memset(wm_state, 0, sizeof(*wm_state)); - wm_state->thread0.grf_reg_count = BRW_GRF_BLOCKS(PS_KERNEL_NUM_GRF); - wm_state->thread0.kernel_start_pointer = + memset(state, 0, sizeof(*state)); + state->thread0.grf_reg_count = BRW_GRF_BLOCKS(PS_KERNEL_NUM_GRF); + state->thread0.kernel_start_pointer = intel_emit_reloc(wm_state_bo, offsetof(struct brw_wm_unit_state, thread0), - kernel_bo, wm_state->thread0.grf_reg_count << 1, + kernel_bo, state->thread0.grf_reg_count << 1, I915_GEM_DOMAIN_INSTRUCTION, 0) >> 6; - wm_state->thread1.single_program_flow = 0; + state->thread1.single_program_flow = 0; /* scratch space is not used in our kernel */ - wm_state->thread2.scratch_space_base_pointer = 0; - wm_state->thread2.per_thread_scratch_space = 0; + state->thread2.scratch_space_base_pointer = 0; + state->thread2.per_thread_scratch_space = 0; - wm_state->thread3.const_urb_entry_read_length = 0; - wm_state->thread3.const_urb_entry_read_offset = 0; + state->thread3.const_urb_entry_read_length = 0; + state->thread3.const_urb_entry_read_offset = 0; - wm_state->thread3.urb_entry_read_offset = 0; + state->thread3.urb_entry_read_offset = 0; /* wm kernel use urb from 3, see wm_program in compiler module */ - wm_state->thread3.dispatch_grf_start_reg = 3; /* must match kernel */ - - wm_state->wm4.stats_enable = 1; /* statistic */ + state->thread3.dispatch_grf_start_reg = 3; /* must match kernel */ - if (IS_IGDNG(intel)) - wm_state->wm4.sampler_count = 0; /* hardware requirement */ + if (IS_GEN5(intel)) + state->wm4.sampler_count = 0; /* hardware requirement */ else - wm_state->wm4.sampler_count = 1; /* 1-4 samplers used */ + state->wm4.sampler_count = 1; /* 1-4 samplers used */ - wm_state->wm4.sampler_state_pointer = + state->wm4.sampler_state_pointer = intel_emit_reloc(wm_state_bo, offsetof(struct brw_wm_unit_state, wm4), sampler_bo, - wm_state->wm4.stats_enable + - (wm_state->wm4.sampler_count << 2), + state->wm4.sampler_count << 2, I915_GEM_DOMAIN_INSTRUCTION, 0) >> 5; - wm_state->wm5.max_threads = PS_MAX_THREADS - 1; - wm_state->wm5.transposed_urb_read = 0; - wm_state->wm5.thread_dispatch_enable = 1; + state->wm5.max_threads = PS_MAX_THREADS - 1; + state->wm5.transposed_urb_read = 0; + state->wm5.thread_dispatch_enable = 1; /* just use 16-pixel dispatch (4 subspans), don't need to change kernel * start point */ - wm_state->wm5.enable_16_pix = 1; - wm_state->wm5.enable_8_pix = 0; - wm_state->wm5.early_depth_test = 1; + state->wm5.enable_16_pix = 1; + state->wm5.enable_8_pix = 0; + state->wm5.early_depth_test = 1; /* Each pair of attributes (src/mask coords) is two URB entries */ if (has_mask) { - wm_state->thread1.binding_table_entry_count = 3; /* 2 tex and fb */ - wm_state->thread3.urb_entry_read_length = 4; + state->thread1.binding_table_entry_count = 3; /* 2 tex and fb */ + state->thread3.urb_entry_read_length = 4; } else { - wm_state->thread1.binding_table_entry_count = 2; /* 1 tex and fb */ - wm_state->thread3.urb_entry_read_length = 2; + state->thread1.binding_table_entry_count = 2; /* 1 tex and fb */ + state->thread3.urb_entry_read_length = 2; } /* binding table entry count is only used for prefetching, and it has to * be set 0 for IGDNG */ - if (IS_IGDNG(intel)) - wm_state->thread1.binding_table_entry_count = 0; + if (IS_GEN5(intel)) + state->thread1.binding_table_entry_count = 0; drm_intel_bo_unmap(wm_state_bo); return wm_state_bo; } -static drm_intel_bo *gen4_create_cc_viewport(ScrnInfoPtr scrn) +static drm_intel_bo *gen4_create_cc_viewport(intel_screen_private *intel) { - intel_screen_private *intel = intel_get_screen_private(scrn); drm_intel_bo *bo; - struct brw_cc_viewport cc_viewport; + struct brw_cc_viewport vp; - cc_viewport.min_depth = -1.e35; - cc_viewport.max_depth = 1.e35; + vp.min_depth = -1.e35; + vp.max_depth = 1.e35; bo = drm_intel_bo_alloc(intel->bufmgr, "gen4 render unit state", - sizeof(cc_viewport), 4096); - drm_intel_bo_subdata(bo, 0, sizeof(cc_viewport), &cc_viewport); + sizeof(vp), 4096); + drm_intel_bo_subdata(bo, 0, sizeof(vp), &vp); return bo; } -static drm_intel_bo *gen4_create_vs_unit_state(ScrnInfoPtr scrn) +static drm_intel_bo *gen4_create_vs_unit_state(intel_screen_private *intel) { - intel_screen_private *intel = intel_get_screen_private(scrn); struct brw_vs_unit_state vs_state; memset(&vs_state, 0, sizeof(vs_state)); /* Set up the vertex shader to be disabled (passthrough) */ - if (IS_IGDNG(intel)) + if (IS_GEN5(intel)) vs_state.thread4.nr_urb_entries = URB_VS_ENTRIES >> 2; /* hardware requirement */ else vs_state.thread4.nr_urb_entries = URB_VS_ENTRIES; @@ -962,7 +1192,7 @@ static drm_intel_bo *gen4_create_vs_unit_state(ScrnInfoPtr scrn) vs_state.vs6.vs_enable = 0; vs_state.vs6.vert_cache_disable = 1; - return intel_bo_alloc_for_data(scrn, &vs_state, sizeof(vs_state), + return intel_bo_alloc_for_data(intel, &vs_state, sizeof(vs_state), "gen4 render VS state"); } @@ -970,19 +1200,17 @@ static drm_intel_bo *gen4_create_vs_unit_state(ScrnInfoPtr scrn) * Set up all combinations of cc state: each blendfactor for source and * dest. */ -static drm_intel_bo *gen4_create_cc_unit_state(ScrnInfoPtr scrn) +static drm_intel_bo *gen4_create_cc_unit_state(intel_screen_private *intel) { - intel_screen_private *intel = intel_get_screen_private(scrn); - struct gen4_cc_unit_state *cc_state; drm_intel_bo *cc_state_bo, *cc_vp_bo; int i, j; - cc_vp_bo = gen4_create_cc_viewport(scrn); + cc_vp_bo = gen4_create_cc_viewport(intel); cc_state_bo = drm_intel_bo_alloc(intel->bufmgr, "gen4 CC state", - sizeof(*cc_state), 4096); + sizeof(struct gen4_cc_unit_state), + 4096); drm_intel_bo_map(cc_state_bo, TRUE); - cc_state = cc_state_bo->virtual; for (i = 0; i < BRW_BLENDFACTOR_COUNT; i++) { for (j = 0; j < BRW_BLENDFACTOR_COUNT; j++) { cc_state_init(cc_state_bo, @@ -1016,11 +1244,11 @@ static sampler_state_filter_t sampler_state_filter_from_picture(int filter) { switch (filter) { case PictFilterNearest: - return SAMPLER_STATE_FILTER_NEAREST; + return SS_FILTER_NEAREST; case PictFilterBilinear: - return SAMPLER_STATE_FILTER_BILINEAR; + return SS_FILTER_BILINEAR; default: - return -1; + return SS_INVALID_FILTER; } } @@ -1028,15 +1256,15 @@ static sampler_state_extend_t sampler_state_extend_from_picture(int repeat_type) { switch (repeat_type) { case RepeatNone: - return SAMPLER_STATE_EXTEND_NONE; + return SS_EXTEND_NONE; case RepeatNormal: - return SAMPLER_STATE_EXTEND_REPEAT; + return SS_EXTEND_REPEAT; case RepeatPad: - return SAMPLER_STATE_EXTEND_PAD; + return SS_EXTEND_PAD; case RepeatReflect: - return SAMPLER_STATE_EXTEND_REFLECT; + return SS_EXTEND_REFLECT; default: - return -1; + return SS_INVALID_EXTEND; } } @@ -1044,79 +1272,239 @@ static sampler_state_extend_t sampler_state_extend_from_picture(int repeat_type) * Sets up the common fields for a surface state buffer for the given * picture in the given surface state buffer. */ -static void -i965_set_picture_surface_state(intel_screen_private *intel, - dri_bo * ss_bo, int ss_index, +static int +gen4_set_picture_surface_state(intel_screen_private *intel, PicturePtr picture, PixmapPtr pixmap, Bool is_dst) { - struct brw_surface_state_padded *ss; - struct brw_surface_state local_ss; - struct intel_pixmap *priv = i830_get_pixmap_intel(pixmap); + struct intel_pixmap *priv = intel_get_pixmap_private(pixmap); + struct brw_surface_state *ss; + uint32_t write_domain, read_domains; + int offset; + + if (is_dst) { + write_domain = I915_GEM_DOMAIN_RENDER; + read_domains = I915_GEM_DOMAIN_RENDER; + } else { + write_domain = 0; + read_domains = I915_GEM_DOMAIN_SAMPLER; + } + intel_batch_mark_pixmap_domains(intel, priv, + read_domains, write_domain); + ss = (struct brw_surface_state *) + (intel->surface_data + intel->surface_used); + + memset(ss, 0, sizeof(*ss)); + ss->ss0.surface_type = BRW_SURFACE_2D; + if (is_dst) + ss->ss0.surface_format = i965_get_dest_format(picture); + else + ss->ss0.surface_format = i965_get_card_format(picture); - ss = (struct brw_surface_state_padded *)ss_bo->virtual + ss_index; + ss->ss0.data_return_format = BRW_SURFACERETURNFORMAT_FLOAT32; + ss->ss0.color_blend = 1; + ss->ss1.base_addr = priv->bo->offset; + + ss->ss2.height = pixmap->drawable.height - 1; + ss->ss2.width = pixmap->drawable.width - 1; + ss->ss3.pitch = intel_pixmap_pitch(pixmap) - 1; + ss->ss3.tile_walk = 0; /* Tiled X */ + ss->ss3.tiled_surface = intel_pixmap_tiled(pixmap) ? 1 : 0; + + dri_bo_emit_reloc(intel->surface_bo, + read_domains, write_domain, + 0, + intel->surface_used + + offsetof(struct brw_surface_state, ss1), + priv->bo); + + offset = intel->surface_used; + intel->surface_used += SURFACE_STATE_PADDED_SIZE; + + return offset; +} + +static int +gen7_set_picture_surface_state(intel_screen_private *intel, + PicturePtr picture, PixmapPtr pixmap, + Bool is_dst) +{ + struct intel_pixmap *priv = intel_get_pixmap_private(pixmap); + struct gen7_surface_state *ss; + uint32_t write_domain, read_domains; + int offset; - /* Since ss is a pointer to WC memory, do all of our bit operations - * into a local temporary first. - */ - memset(&local_ss, 0, sizeof(local_ss)); - local_ss.ss0.surface_type = BRW_SURFACE_2D; if (is_dst) { - uint32_t dst_format = 0; - Bool ret = TRUE; + write_domain = I915_GEM_DOMAIN_RENDER; + read_domains = I915_GEM_DOMAIN_RENDER; + } else { + write_domain = 0; + read_domains = I915_GEM_DOMAIN_SAMPLER; + } + intel_batch_mark_pixmap_domains(intel, priv, + read_domains, write_domain); + ss = (struct gen7_surface_state *) + (intel->surface_data + intel->surface_used); + + memset(ss, 0, sizeof(*ss)); + ss->ss0.surface_type = BRW_SURFACE_2D; + if (is_dst) + ss->ss0.surface_format = i965_get_dest_format(picture); + else + ss->ss0.surface_format = i965_get_card_format(picture); + + ss->ss0.tile_walk = 0; /* Tiled X */ + ss->ss0.tiled_surface = intel_pixmap_tiled(pixmap) ? 1 : 0; + ss->ss1.base_addr = priv->bo->offset; + + ss->ss2.height = pixmap->drawable.height - 1; + ss->ss2.width = pixmap->drawable.width - 1; + ss->ss3.pitch = intel_pixmap_pitch(pixmap) - 1; + + dri_bo_emit_reloc(intel->surface_bo, + read_domains, write_domain, + 0, + intel->surface_used + + offsetof(struct gen7_surface_state, ss1), + priv->bo); + + offset = intel->surface_used; + intel->surface_used += SURFACE_STATE_PADDED_SIZE; + + return offset; +} + +static inline int +i965_set_picture_surface_state(intel_screen_private *intel, + PicturePtr picture, PixmapPtr pixmap, + Bool is_dst) +{ + if (INTEL_INFO(intel)->gen < 70) + return gen4_set_picture_surface_state(intel, picture, pixmap, is_dst); + return gen7_set_picture_surface_state(intel, picture, pixmap, is_dst); +} + +static void gen4_composite_vertex_elements(struct intel_screen_private *intel) +{ + struct gen4_render_state *render_state = intel->gen4_render_state; + gen4_composite_op *composite_op = &render_state->composite_op; + Bool has_mask = intel->render_mask != NULL; + Bool is_affine = composite_op->is_affine; + /* + * number of extra parameters per vertex + */ + int nelem = has_mask ? 2 : 1; + /* + * size of extra parameters: + * 3 for homogenous (xyzw) + * 2 for cartesian (xy) + */ + int selem = is_affine ? 2 : 3; + uint32_t w_component; + uint32_t src_format; + int id; + + id = has_mask << 1 | is_affine; + + if (composite_op->vertex_id == id) + return; - ret = i965_get_dest_format(picture, &dst_format); - assert(ret == TRUE); - local_ss.ss0.surface_format = dst_format; + composite_op->vertex_id = id; + + if (is_affine) { + src_format = BRW_SURFACEFORMAT_R32G32_FLOAT; + w_component = BRW_VFCOMPONENT_STORE_1_FLT; } else { - local_ss.ss0.surface_format = i965_get_card_format(picture); + src_format = BRW_SURFACEFORMAT_R32G32B32_FLOAT; + w_component = BRW_VFCOMPONENT_STORE_SRC; } - local_ss.ss0.data_return_format = BRW_SURFACERETURNFORMAT_FLOAT32; - local_ss.ss0.writedisable_alpha = 0; - local_ss.ss0.writedisable_red = 0; - local_ss.ss0.writedisable_green = 0; - local_ss.ss0.writedisable_blue = 0; - local_ss.ss0.color_blend = 1; - local_ss.ss0.vert_line_stride = 0; - local_ss.ss0.vert_line_stride_ofs = 0; - local_ss.ss0.mipmap_layout_mode = 0; - local_ss.ss0.render_cache_read_mode = 0; - local_ss.ss1.base_addr = priv->bo->offset; - - local_ss.ss2.mip_count = 0; - local_ss.ss2.render_target_rotation = 0; - local_ss.ss2.height = pixmap->drawable.height - 1; - local_ss.ss2.width = pixmap->drawable.width - 1; - local_ss.ss3.pitch = intel_get_pixmap_pitch(pixmap) - 1; - local_ss.ss3.tile_walk = 0; /* Tiled X */ - local_ss.ss3.tiled_surface = i830_pixmap_tiled(pixmap) ? 1 : 0; - - memcpy(ss, &local_ss, sizeof(local_ss)); - - if (priv->bo != NULL) { - uint32_t write_domain, read_domains; - - if (is_dst) { - write_domain = I915_GEM_DOMAIN_RENDER; - read_domains = I915_GEM_DOMAIN_RENDER; - } else { - write_domain = 0; - read_domains = I915_GEM_DOMAIN_SAMPLER; - } + if (IS_GEN5(intel)) { + /* + * The reason to add this extra vertex element in the header is that + * Ironlake has different vertex header definition and origin method to + * set destination element offset doesn't exist anymore, which means + * hardware requires a predefined vertex element layout. + * + * haihao proposed this approach to fill the first vertex element, so + * origin layout for Gen4 doesn't need to change, and origin shader + * programs behavior is also kept. + * + * I think this is not bad. - zhenyu + */ + + OUT_BATCH(BRW_3DSTATE_VERTEX_ELEMENTS | + ((2 * (2 + nelem)) - 1)); + OUT_BATCH((id << VE0_VERTEX_BUFFER_INDEX_SHIFT) | VE0_VALID | + (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) | + (0 << VE0_OFFSET_SHIFT)); - intel_batch_mark_pixmap_domains(intel, priv, read_domains, write_domain); - dri_bo_emit_reloc(ss_bo, read_domains, write_domain, - 0, - ss_index * sizeof(*ss) + - offsetof(struct brw_surface_state, ss1), - priv->bo); + OUT_BATCH((BRW_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT) | + (BRW_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT) | + (BRW_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT) | + (BRW_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT)); + } else { + /* Set up our vertex elements, sourced from the single vertex buffer. + * that will be set up later. + */ + OUT_BATCH(BRW_3DSTATE_VERTEX_ELEMENTS | + ((2 * (1 + nelem)) - 1)); + } + + /* x,y */ + OUT_BATCH((id << VE0_VERTEX_BUFFER_INDEX_SHIFT) | VE0_VALID | + (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) | + (0 << VE0_OFFSET_SHIFT)); + + if (IS_GEN5(intel)) + OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) | + (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) | + (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) | + (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT)); + else + OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) | + (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) | + (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) | + (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) | + (4 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT)); + /* u0, v0, w0 */ + OUT_BATCH((id << VE0_VERTEX_BUFFER_INDEX_SHIFT) | VE0_VALID | + (src_format << VE0_FORMAT_SHIFT) | + ((2 * 4) << VE0_OFFSET_SHIFT)); /* offset vb in bytes */ + + if (IS_GEN5(intel)) + OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) | + (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) | + (w_component << VE1_VFCOMPONENT_2_SHIFT) | + (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT)); + else + OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) | + (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) | + (w_component << VE1_VFCOMPONENT_2_SHIFT) | + (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) | + ((4 + 4) << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT)); /* VUE offset in dwords */ + /* u1, v1, w1 */ + if (has_mask) { + OUT_BATCH((id << VE0_VERTEX_BUFFER_INDEX_SHIFT) | VE0_VALID | + (src_format << VE0_FORMAT_SHIFT) | + (((2 + selem) * 4) << VE0_OFFSET_SHIFT)); /* vb offset in bytes */ + + if (IS_GEN5(intel)) + OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) | + (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) | + (w_component << VE1_VFCOMPONENT_2_SHIFT) | + (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT)); + else + OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) | + (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) | + (w_component << VE1_VFCOMPONENT_2_SHIFT) | + (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) | + ((4 + 4 + 4) << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT)); /* VUE offset in dwords */ } } -static void i965_emit_composite_state(ScrnInfoPtr scrn) +static void i965_emit_composite_state(struct intel_screen_private *intel) { - intel_screen_private *intel = intel_get_screen_private(scrn); struct gen4_render_state *render_state = intel->gen4_render_state; gen4_composite_op *composite_op = &render_state->composite_op; int op = composite_op->op; @@ -1128,331 +1516,178 @@ static void i965_emit_composite_state(ScrnInfoPtr scrn) sampler_state_filter_t mask_filter = composite_op->mask_filter; sampler_state_extend_t src_extend = composite_op->src_extend; sampler_state_extend_t mask_extend = composite_op->mask_extend; - Bool is_affine = composite_op->is_affine; - int urb_vs_start, urb_vs_size; - int urb_gs_start, urb_gs_size; - int urb_clip_start, urb_clip_size; - int urb_sf_start, urb_sf_size; - int urb_cs_start, urb_cs_size; uint32_t src_blend, dst_blend; - dri_bo *binding_table_bo = composite_op->binding_table_bo; intel->needs_render_state_emit = FALSE; - IntelEmitInvarientState(scrn); - intel->last_3d = LAST_3D_RENDER; - - /* Mark the destination dirty within this batch */ - intel_batch_mark_pixmap_domains(intel, - i830_get_pixmap_intel(dest), - I915_GEM_DOMAIN_RENDER, - I915_GEM_DOMAIN_RENDER); - - urb_vs_start = 0; - urb_vs_size = URB_VS_ENTRIES * URB_VS_ENTRY_SIZE; - urb_gs_start = urb_vs_start + urb_vs_size; - urb_gs_size = URB_GS_ENTRIES * URB_GS_ENTRY_SIZE; - urb_clip_start = urb_gs_start + urb_gs_size; - urb_clip_size = URB_CLIP_ENTRIES * URB_CLIP_ENTRY_SIZE; - urb_sf_start = urb_clip_start + urb_clip_size; - urb_sf_size = URB_SF_ENTRIES * URB_SF_ENTRY_SIZE; - urb_cs_start = urb_sf_start + urb_sf_size; - urb_cs_size = URB_CS_ENTRIES * URB_CS_ENTRY_SIZE; - - i965_get_blend_cntl(op, mask_picture, dest_picture->format, - &src_blend, &dst_blend); - /* Begin the long sequence of commands needed to set up the 3D * rendering pipe */ - /* URB fence. Erratum (Vol 1a, p32): URB_FENCE must not cross a - * cache-line (64 bytes). Start by aligning this sequence of ops to - * a cache-line... - */ - ALIGN_BATCH(64); + if (intel->needs_3d_invariant) { + if (IS_GEN5(intel)) { + /* Ironlake errata workaround: Before disabling the clipper, + * you have to MI_FLUSH to get the pipeline idle. + */ + OUT_BATCH(MI_FLUSH | MI_INHIBIT_RENDER_CACHE_FLUSH); + } - assert(intel->in_batch_atomic); - { /* Match Mesa driver setup */ - OUT_BATCH(MI_FLUSH | - MI_STATE_INSTRUCTION_CACHE_FLUSH | - BRW_MI_GLOBAL_SNAPSHOT_RESET); - if (IS_G4X(intel) || IS_IGDNG(intel)) + if (INTEL_INFO(intel)->gen >= 45) OUT_BATCH(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D); else OUT_BATCH(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D); - OUT_BATCH(BRW_CS_URB_STATE | 0); - OUT_BATCH((0 << 4) | /* URB Entry Allocation Size */ - (0 << 0)); /* Number of URB Entries */ + /* Set system instruction pointer */ + OUT_BATCH(BRW_STATE_SIP | 0); + OUT_BATCH(0); + + intel->needs_3d_invariant = FALSE; + } + if (intel->surface_reloc == 0) { /* Zero out the two base address registers so all offsets are * absolute. */ - if (IS_IGDNG(intel)) { + if (IS_GEN5(intel)) { OUT_BATCH(BRW_STATE_BASE_ADDRESS | 6); OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Generate state base address */ - OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Surface state base address */ + intel->surface_reloc = intel->batch_used; + intel_batch_emit_dword(intel, + intel->surface_bo->offset | BASE_ADDRESS_MODIFY); OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* media base addr, don't care */ OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Instruction base address */ /* general state max addr, disabled */ - OUT_BATCH(0x10000000 | BASE_ADDRESS_MODIFY); + OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* media object state max addr, disabled */ - OUT_BATCH(0x10000000 | BASE_ADDRESS_MODIFY); + OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Instruction max addr, disabled */ - OUT_BATCH(0x10000000 | BASE_ADDRESS_MODIFY); + OUT_BATCH(0 | BASE_ADDRESS_MODIFY); } else { OUT_BATCH(BRW_STATE_BASE_ADDRESS | 4); OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Generate state base address */ - OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Surface state base address */ + intel->surface_reloc = intel->batch_used; + intel_batch_emit_dword(intel, + intel->surface_bo->offset | BASE_ADDRESS_MODIFY); OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* media base addr, don't care */ /* general state max addr, disabled */ - OUT_BATCH(0x10000000 | BASE_ADDRESS_MODIFY); + OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* media object state max addr, disabled */ - OUT_BATCH(0x10000000 | BASE_ADDRESS_MODIFY); + OUT_BATCH(0 | BASE_ADDRESS_MODIFY); } - /* Set system instruction pointer */ - OUT_BATCH(BRW_STATE_SIP | 0); - OUT_RELOC(render_state->sip_kernel_bo, - I915_GEM_DOMAIN_INSTRUCTION, 0, 0); - } - - if (IS_IGDNG(intel)) { - /* Ironlake errata workaround: Before disabling the clipper, - * you have to MI_FLUSH to get the pipeline idle. - */ - OUT_BATCH(MI_FLUSH); } - { - int pipe_ctrl; - /* Pipe control */ + i965_get_blend_cntl(op, mask_picture, dest_picture->format, + &src_blend, &dst_blend); - if (IS_IGDNG(intel)) - pipe_ctrl = BRW_PIPE_CONTROL_NOWRITE; - else - pipe_ctrl = - BRW_PIPE_CONTROL_NOWRITE | - BRW_PIPE_CONTROL_IS_FLUSH; - - OUT_BATCH(BRW_PIPE_CONTROL | pipe_ctrl | 2); - OUT_BATCH(0); /* Destination address */ - OUT_BATCH(0); /* Immediate data low DW */ - OUT_BATCH(0); /* Immediate data high DW */ - - /* Binding table pointers */ - OUT_BATCH(BRW_3DSTATE_BINDING_TABLE_POINTERS | 4); - OUT_BATCH(0); /* vs */ - OUT_BATCH(0); /* gs */ - OUT_BATCH(0); /* clip */ - OUT_BATCH(0); /* sf */ - /* Only the PS uses the binding table */ - OUT_RELOC(binding_table_bo, I915_GEM_DOMAIN_SAMPLER, 0, 0); - - /* The drawing rectangle clipping is always on. Set it to values that - * shouldn't do any clipping. - */ - OUT_BATCH(BRW_3DSTATE_DRAWING_RECTANGLE | 2); - OUT_BATCH(0x00000000); /* ymin, xmin */ - OUT_BATCH(DRAW_YMAX(dest->drawable.height - 1) | DRAW_XMAX(dest->drawable.width - 1)); /* ymax, xmax */ - OUT_BATCH(0x00000000); /* yorigin, xorigin */ - - /* skip the depth buffer */ - /* skip the polygon stipple */ - /* skip the polygon stipple offset */ - /* skip the line stipple */ - - /* Set the pointers to the 3d pipeline state */ - OUT_BATCH(BRW_3DSTATE_PIPELINED_POINTERS | 5); - OUT_RELOC(render_state->vs_state_bo, + /* Binding table pointers */ + OUT_BATCH(BRW_3DSTATE_BINDING_TABLE_POINTERS | 4); + OUT_BATCH(0); /* vs */ + OUT_BATCH(0); /* gs */ + OUT_BATCH(0); /* clip */ + OUT_BATCH(0); /* sf */ + /* Only the PS uses the binding table */ + OUT_BATCH(intel->surface_table); + + /* The drawing rectangle clipping is always on. Set it to values that + * shouldn't do any clipping. + */ + OUT_BATCH(BRW_3DSTATE_DRAWING_RECTANGLE | 2); + OUT_BATCH(0x00000000); /* ymin, xmin */ + OUT_BATCH(DRAW_YMAX(dest->drawable.height - 1) | + DRAW_XMAX(dest->drawable.width - 1)); /* ymax, xmax */ + OUT_BATCH(0x00000000); /* yorigin, xorigin */ + + /* skip the depth buffer */ + /* skip the polygon stipple */ + /* skip the polygon stipple offset */ + /* skip the line stipple */ + + /* Set the pointers to the 3d pipeline state */ + OUT_BATCH(BRW_3DSTATE_PIPELINED_POINTERS | 5); + OUT_RELOC(render_state->vs_state_bo, + I915_GEM_DOMAIN_INSTRUCTION, 0, 0); + OUT_BATCH(BRW_GS_DISABLE); /* disable GS, resulting in passthrough */ + OUT_BATCH(BRW_CLIP_DISABLE); /* disable CLIP, resulting in passthrough */ + if (mask) { + OUT_RELOC(render_state->sf_mask_state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); - OUT_BATCH(BRW_GS_DISABLE); /* disable GS, resulting in passthrough */ - OUT_BATCH(BRW_CLIP_DISABLE); /* disable CLIP, resulting in passthrough */ - if (mask) { - OUT_RELOC(render_state->sf_mask_state_bo, - I915_GEM_DOMAIN_INSTRUCTION, 0, 0); - } else { - OUT_RELOC(render_state->sf_state_bo, - I915_GEM_DOMAIN_INSTRUCTION, 0, 0); - } - - OUT_RELOC(render_state->wm_state_bo[composite_op->wm_kernel] - [src_filter][src_extend] - [mask_filter][mask_extend], + } else { + OUT_RELOC(render_state->sf_state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); + } - OUT_RELOC(render_state->cc_state_bo, - I915_GEM_DOMAIN_INSTRUCTION, 0, - offsetof(struct gen4_cc_unit_state, - cc_state[src_blend][dst_blend])); + OUT_RELOC(render_state->wm_state_bo[composite_op->wm_kernel] + [src_filter][src_extend] + [mask_filter][mask_extend], + I915_GEM_DOMAIN_INSTRUCTION, 0, 0); - /* URB fence. Erratum (Vol 1a, p32): URB_FENCE must not cross a - * cache-line (64 bytes). - * - * 21 preceding dwords since start of section: 84 bytes. - * 12 bytes for URB_FENCE, implies that the end-of-instruction - * does not cross the cache-line boundary... - * - * A total of 33 or 35 dwords since alignment: 132, 140 bytes. - * Again, the URB_FENCE will not cross a cache-line. + OUT_RELOC(render_state->cc_state_bo, + I915_GEM_DOMAIN_INSTRUCTION, 0, + offsetof(struct gen4_cc_unit_state, + cc_state[src_blend][dst_blend])); + + { + int urb_vs_start, urb_vs_size; + int urb_gs_start, urb_gs_size; + int urb_clip_start, urb_clip_size; + int urb_sf_start, urb_sf_size; + int urb_cs_start, urb_cs_size; + + urb_vs_start = 0; + urb_vs_size = URB_VS_ENTRIES * URB_VS_ENTRY_SIZE; + urb_gs_start = urb_vs_start + urb_vs_size; + urb_gs_size = URB_GS_ENTRIES * URB_GS_ENTRY_SIZE; + urb_clip_start = urb_gs_start + urb_gs_size; + urb_clip_size = URB_CLIP_ENTRIES * URB_CLIP_ENTRY_SIZE; + urb_sf_start = urb_clip_start + urb_clip_size; + urb_sf_size = URB_SF_ENTRIES * URB_SF_ENTRY_SIZE; + urb_cs_start = urb_sf_start + urb_sf_size; + urb_cs_size = URB_CS_ENTRIES * URB_CS_ENTRY_SIZE; + + /* Erratum (Vol 1a, p32): + * URB_FENCE must not cross a cache-line (64 bytes). */ + if ((intel->batch_used & 15) > (16 - 3)) { + int cnt = 16 - (intel->batch_used & 15); + while (cnt--) + OUT_BATCH(MI_NOOP); + } + OUT_BATCH(BRW_URB_FENCE | UF0_CS_REALLOC | UF0_SF_REALLOC | UF0_CLIP_REALLOC | - UF0_GS_REALLOC | UF0_VS_REALLOC | 1); - OUT_BATCH(((urb_clip_start + - urb_clip_size) << UF1_CLIP_FENCE_SHIFT) | - ((urb_gs_start + - urb_gs_size) << UF1_GS_FENCE_SHIFT) | ((urb_vs_start - + - urb_vs_size) - << - UF1_VS_FENCE_SHIFT)); - OUT_BATCH(((urb_cs_start + - urb_cs_size) << UF2_CS_FENCE_SHIFT) | ((urb_sf_start - + - urb_sf_size) - << - UF2_SF_FENCE_SHIFT)); + UF0_GS_REALLOC | + UF0_VS_REALLOC | + 1); + OUT_BATCH(((urb_clip_start + urb_clip_size) << UF1_CLIP_FENCE_SHIFT) | + ((urb_gs_start + urb_gs_size) << UF1_GS_FENCE_SHIFT) | + ((urb_vs_start + urb_vs_size) << UF1_VS_FENCE_SHIFT)); + OUT_BATCH(((urb_cs_start + urb_cs_size) << UF2_CS_FENCE_SHIFT) | + ((urb_sf_start + urb_sf_size) << UF2_SF_FENCE_SHIFT)); /* Constant buffer state */ OUT_BATCH(BRW_CS_URB_STATE | 0); OUT_BATCH(((URB_CS_ENTRY_SIZE - 1) << 4) | (URB_CS_ENTRIES << 0)); } - { - /* - * number of extra parameters per vertex - */ - int nelem = mask ? 2 : 1; - /* - * size of extra parameters: - * 3 for homogenous (xyzw) - * 2 for cartesian (xy) - */ - int selem = is_affine ? 2 : 3; - uint32_t w_component; - uint32_t src_format; - - render_state->vertex_size = 4 * (2 + nelem * selem); - - if (is_affine) { - src_format = BRW_SURFACEFORMAT_R32G32_FLOAT; - w_component = BRW_VFCOMPONENT_STORE_1_FLT; - } else { - src_format = BRW_SURFACEFORMAT_R32G32B32_FLOAT; - w_component = BRW_VFCOMPONENT_STORE_SRC; - } - - if (IS_IGDNG(intel)) { - /* - * The reason to add this extra vertex element in the header is that - * IGDNG has different vertex header definition and origin method to - * set destination element offset doesn't exist anymore, which means - * hardware requires a predefined vertex element layout. - * - * haihao proposed this approach to fill the first vertex element, so - * origin layout for Gen4 doesn't need to change, and origin shader - * programs behavior is also kept. - * - * I think this is not bad. - zhenyu - */ - OUT_BATCH(BRW_3DSTATE_VERTEX_ELEMENTS | - ((2 * (2 + nelem)) - 1)); - OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) | - VE0_VALID | (BRW_SURFACEFORMAT_R32G32_FLOAT << - VE0_FORMAT_SHIFT) | (0 << - VE0_OFFSET_SHIFT)); - - OUT_BATCH((BRW_VFCOMPONENT_STORE_0 << - VE1_VFCOMPONENT_0_SHIFT) | - (BRW_VFCOMPONENT_STORE_0 << - VE1_VFCOMPONENT_1_SHIFT) | - (BRW_VFCOMPONENT_STORE_0 << - VE1_VFCOMPONENT_2_SHIFT) | - (BRW_VFCOMPONENT_STORE_0 << - VE1_VFCOMPONENT_3_SHIFT)); - } else { - /* Set up our vertex elements, sourced from the single vertex buffer. - * that will be set up later. - */ - OUT_BATCH(BRW_3DSTATE_VERTEX_ELEMENTS | - ((2 * (1 + nelem)) - 1)); - } - - /* x,y */ - OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) | - VE0_VALID | - (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) | - (0 << VE0_OFFSET_SHIFT)); - - if (IS_IGDNG(intel)) - OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << - VE1_VFCOMPONENT_0_SHIFT) | - (BRW_VFCOMPONENT_STORE_SRC << - VE1_VFCOMPONENT_1_SHIFT) | - (BRW_VFCOMPONENT_STORE_1_FLT << - VE1_VFCOMPONENT_2_SHIFT) | - (BRW_VFCOMPONENT_STORE_1_FLT << - VE1_VFCOMPONENT_3_SHIFT)); - else - OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << - VE1_VFCOMPONENT_0_SHIFT) | - (BRW_VFCOMPONENT_STORE_SRC << - VE1_VFCOMPONENT_1_SHIFT) | - (BRW_VFCOMPONENT_STORE_1_FLT << - VE1_VFCOMPONENT_2_SHIFT) | - (BRW_VFCOMPONENT_STORE_1_FLT << - VE1_VFCOMPONENT_3_SHIFT) | (4 << - VE1_DESTINATION_ELEMENT_OFFSET_SHIFT)); - /* u0, v0, w0 */ - OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) | VE0_VALID | (src_format << VE0_FORMAT_SHIFT) | ((2 * 4) << VE0_OFFSET_SHIFT)); /* offset vb in bytes */ - - if (IS_IGDNG(intel)) - OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << - VE1_VFCOMPONENT_0_SHIFT) | - (BRW_VFCOMPONENT_STORE_SRC << - VE1_VFCOMPONENT_1_SHIFT) | (w_component << - VE1_VFCOMPONENT_2_SHIFT) - | (BRW_VFCOMPONENT_STORE_1_FLT << - VE1_VFCOMPONENT_3_SHIFT)); - else - OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) | (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) | (w_component << VE1_VFCOMPONENT_2_SHIFT) | (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) | ((4 + 4) << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT)); /* VUE offset in dwords */ - /* u1, v1, w1 */ - if (mask) { - OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) | VE0_VALID | (src_format << VE0_FORMAT_SHIFT) | (((2 + selem) * 4) << VE0_OFFSET_SHIFT)); /* vb offset in bytes */ - - if (IS_IGDNG(intel)) - OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << - VE1_VFCOMPONENT_0_SHIFT) | - (BRW_VFCOMPONENT_STORE_SRC << - VE1_VFCOMPONENT_1_SHIFT) | - (w_component << - VE1_VFCOMPONENT_2_SHIFT) | - (BRW_VFCOMPONENT_STORE_1_FLT << - VE1_VFCOMPONENT_3_SHIFT)); - else - OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) | (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) | (w_component << VE1_VFCOMPONENT_2_SHIFT) | (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) | ((4 + 4 + 4) << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT)); /* VUE offset in dwords */ - } - } + gen4_composite_vertex_elements(intel); } /** * Returns whether the current set of composite state plus vertex buffer is * expected to fit in the aperture. */ -static Bool i965_composite_check_aperture(ScrnInfoPtr scrn) +static Bool i965_composite_check_aperture(intel_screen_private *intel) { - intel_screen_private *intel = intel_get_screen_private(scrn); struct gen4_render_state *render_state = intel->gen4_render_state; gen4_composite_op *composite_op = &render_state->composite_op; drm_intel_bo *bo_table[] = { intel->batch_bo, - composite_op->binding_table_bo, - render_state->vertex_buffer_bo, + intel->vertex_bo, + intel->surface_bo, render_state->vs_state_bo, render_state->sf_state_bo, render_state->sf_mask_state_bo, @@ -1462,11 +1697,279 @@ static Bool i965_composite_check_aperture(ScrnInfoPtr scrn) [composite_op->mask_filter] [composite_op->mask_extend], render_state->cc_state_bo, - render_state->sip_kernel_bo, }; + drm_intel_bo *gen6_bo_table[] = { + intel->batch_bo, + intel->vertex_bo, + intel->surface_bo, + render_state->wm_kernel_bo[composite_op->wm_kernel], + render_state->ps_sampler_state_bo[composite_op->src_filter] + [composite_op->src_extend] + [composite_op->mask_filter] + [composite_op->mask_extend], + render_state->cc_vp_bo, + render_state->cc_state_bo, + render_state->gen6_blend_bo, + render_state->gen6_depth_stencil_bo, + }; + + if (INTEL_INFO(intel)->gen >= 60) + return drm_intel_bufmgr_check_aperture_space(gen6_bo_table, + ARRAY_SIZE(gen6_bo_table)) == 0; + else + return drm_intel_bufmgr_check_aperture_space(bo_table, + ARRAY_SIZE(bo_table)) == 0; +} + +static void i965_surface_flush(struct intel_screen_private *intel) +{ + drm_intel_bo_subdata(intel->surface_bo, + 0, intel->surface_used, + intel->surface_data); + intel->surface_used = 0; + + assert (intel->surface_reloc != 0); + drm_intel_bo_emit_reloc(intel->batch_bo, + intel->surface_reloc * 4, + intel->surface_bo, BASE_ADDRESS_MODIFY, + I915_GEM_DOMAIN_INSTRUCTION, 0); + intel->surface_reloc = 0; + + drm_intel_bo_unreference(intel->surface_bo); + intel->surface_bo = + drm_intel_bo_alloc(intel->bufmgr, "surface data", + sizeof(intel->surface_data), 4096); +} + +static void +i965_emit_composite_primitive_identity_source(intel_screen_private *intel, + int srcX, int srcY, + int maskX, int maskY, + int dstX, int dstY, + int w, int h) +{ + OUT_VERTEX(dstX + w); + OUT_VERTEX(dstY + h); + OUT_VERTEX((srcX + w) * intel->scale_units[0][0]); + OUT_VERTEX((srcY + h) * intel->scale_units[0][1]); + + OUT_VERTEX(dstX); + OUT_VERTEX(dstY + h); + OUT_VERTEX(srcX * intel->scale_units[0][0]); + OUT_VERTEX((srcY + h) * intel->scale_units[0][1]); + + OUT_VERTEX(dstX); + OUT_VERTEX(dstY); + OUT_VERTEX(srcX * intel->scale_units[0][0]); + OUT_VERTEX(srcY * intel->scale_units[0][1]); +} + +static void +i965_emit_composite_primitive_affine_source(intel_screen_private *intel, + int srcX, int srcY, + int maskX, int maskY, + int dstX, int dstY, + int w, int h) +{ + float src_x[3], src_y[3]; + + if (!intel_get_transformed_coordinates(srcX, srcY, + intel->transform[0], + &src_x[0], + &src_y[0])) + return; + + if (!intel_get_transformed_coordinates(srcX, srcY + h, + intel->transform[0], + &src_x[1], + &src_y[1])) + return; + + if (!intel_get_transformed_coordinates(srcX + w, srcY + h, + intel->transform[0], + &src_x[2], + &src_y[2])) + return; + + OUT_VERTEX(dstX + w); + OUT_VERTEX(dstY + h); + OUT_VERTEX(src_x[2] * intel->scale_units[0][0]); + OUT_VERTEX(src_y[2] * intel->scale_units[0][1]); + + OUT_VERTEX(dstX); + OUT_VERTEX(dstY + h); + OUT_VERTEX(src_x[1] * intel->scale_units[0][0]); + OUT_VERTEX(src_y[1] * intel->scale_units[0][1]); + + OUT_VERTEX(dstX); + OUT_VERTEX(dstY); + OUT_VERTEX(src_x[0] * intel->scale_units[0][0]); + OUT_VERTEX(src_y[0] * intel->scale_units[0][1]); +} + +static void +i965_emit_composite_primitive_identity_source_mask(intel_screen_private *intel, + int srcX, int srcY, + int maskX, int maskY, + int dstX, int dstY, + int w, int h) +{ + OUT_VERTEX(dstX + w); + OUT_VERTEX(dstY + h); + OUT_VERTEX((srcX + w) * intel->scale_units[0][0]); + OUT_VERTEX((srcY + h) * intel->scale_units[0][1]); + OUT_VERTEX((maskX + w) * intel->scale_units[1][0]); + OUT_VERTEX((maskY + h) * intel->scale_units[1][1]); + + OUT_VERTEX(dstX); + OUT_VERTEX(dstY + h); + OUT_VERTEX(srcX * intel->scale_units[0][0]); + OUT_VERTEX((srcY + h) * intel->scale_units[0][1]); + OUT_VERTEX(maskX * intel->scale_units[1][0]); + OUT_VERTEX((maskY + h) * intel->scale_units[1][1]); + + OUT_VERTEX(dstX); + OUT_VERTEX(dstY); + OUT_VERTEX(srcX * intel->scale_units[0][0]); + OUT_VERTEX(srcY * intel->scale_units[0][1]); + OUT_VERTEX(maskX * intel->scale_units[1][0]); + OUT_VERTEX(maskY * intel->scale_units[1][1]); +} + +static void +i965_emit_composite_primitive(intel_screen_private *intel, + int srcX, int srcY, + int maskX, int maskY, + int dstX, int dstY, + int w, int h) +{ + float src_x[3], src_y[3], src_w[3], mask_x[3], mask_y[3], mask_w[3]; + Bool is_affine = intel->gen4_render_state->composite_op.is_affine; + + if (! intel->render_source_is_solid) { + if (is_affine) { + if (!intel_get_transformed_coordinates(srcX, srcY, + intel->transform[0], + &src_x[0], + &src_y[0])) + return; + + if (!intel_get_transformed_coordinates(srcX, srcY + h, + intel->transform[0], + &src_x[1], + &src_y[1])) + return; + + if (!intel_get_transformed_coordinates(srcX + w, srcY + h, + intel->transform[0], + &src_x[2], + &src_y[2])) + return; + } else { + if (!intel_get_transformed_coordinates_3d(srcX, srcY, + intel->transform[0], + &src_x[0], + &src_y[0], + &src_w[0])) + return; + + if (!intel_get_transformed_coordinates_3d(srcX, srcY + h, + intel->transform[0], + &src_x[1], + &src_y[1], + &src_w[1])) + return; + + if (!intel_get_transformed_coordinates_3d(srcX + w, srcY + h, + intel->transform[0], + &src_x[2], + &src_y[2], + &src_w[2])) + return; + } + } + + if (intel->render_mask) { + if (is_affine) { + if (!intel_get_transformed_coordinates(maskX, maskY, + intel->transform[1], + &mask_x[0], + &mask_y[0])) + return; + + if (!intel_get_transformed_coordinates(maskX, maskY + h, + intel->transform[1], + &mask_x[1], + &mask_y[1])) + return; + + if (!intel_get_transformed_coordinates(maskX + w, maskY + h, + intel->transform[1], + &mask_x[2], + &mask_y[2])) + return; + } else { + if (!intel_get_transformed_coordinates_3d(maskX, maskY, + intel->transform[1], + &mask_x[0], + &mask_y[0], + &mask_w[0])) + return; + + if (!intel_get_transformed_coordinates_3d(maskX, maskY + h, + intel->transform[1], + &mask_x[1], + &mask_y[1], + &mask_w[1])) + return; + + if (!intel_get_transformed_coordinates_3d(maskX + w, maskY + h, + intel->transform[1], + &mask_x[2], + &mask_y[2], + &mask_w[2])) + return; + } + } - return drm_intel_bufmgr_check_aperture_space(bo_table, - ARRAY_SIZE(bo_table)) == 0; + OUT_VERTEX(dstX + w); + OUT_VERTEX(dstY + h); + OUT_VERTEX(src_x[2] * intel->scale_units[0][0]); + OUT_VERTEX(src_y[2] * intel->scale_units[0][1]); + if (!is_affine) + OUT_VERTEX(src_w[2]); + if (intel->render_mask) { + OUT_VERTEX(mask_x[2] * intel->scale_units[1][0]); + OUT_VERTEX(mask_y[2] * intel->scale_units[1][1]); + if (!is_affine) + OUT_VERTEX(mask_w[2]); + } + + OUT_VERTEX(dstX); + OUT_VERTEX(dstY + h); + OUT_VERTEX(src_x[1] * intel->scale_units[0][0]); + OUT_VERTEX(src_y[1] * intel->scale_units[0][1]); + if (!is_affine) + OUT_VERTEX(src_w[1]); + if (intel->render_mask) { + OUT_VERTEX(mask_x[1] * intel->scale_units[1][0]); + OUT_VERTEX(mask_y[1] * intel->scale_units[1][1]); + if (!is_affine) + OUT_VERTEX(mask_w[1]); + } + + OUT_VERTEX(dstX); + OUT_VERTEX(dstY); + OUT_VERTEX(src_x[0] * intel->scale_units[0][0]); + OUT_VERTEX(src_y[0] * intel->scale_units[0][1]); + if (!is_affine) + OUT_VERTEX(src_w[0]); + if (intel->render_mask) { + OUT_VERTEX(mask_x[0] * intel->scale_units[1][0]); + OUT_VERTEX(mask_y[0] * intel->scale_units[1][1]); + if (!is_affine) + OUT_VERTEX(mask_w[0]); + } } Bool @@ -1477,25 +1980,18 @@ i965_prepare_composite(int op, PicturePtr source_picture, ScrnInfoPtr scrn = xf86Screens[dest_picture->pDrawable->pScreen->myNum]; intel_screen_private *intel = intel_get_screen_private(scrn); struct gen4_render_state *render_state = intel->gen4_render_state; - gen4_composite_op *composite_op; - uint32_t *binding_table; - drm_intel_bo *binding_table_bo, *surface_state_bo; - - if (render_state == NULL) - return FALSE; - - composite_op = &render_state->composite_op; + gen4_composite_op *composite_op = &render_state->composite_op; composite_op->src_filter = sampler_state_filter_from_picture(source_picture->filter); - if (composite_op->src_filter < 0) { + if (composite_op->src_filter == SS_INVALID_FILTER) { intel_debug_fallback(scrn, "Bad src filter 0x%x\n", source_picture->filter); return FALSE; } composite_op->src_extend = sampler_state_extend_from_picture(source_picture->repeatType); - if (composite_op->src_extend < 0) { + if (composite_op->src_extend == SS_INVALID_EXTEND) { intel_debug_fallback(scrn, "Bad src repeat 0x%x\n", source_picture->repeatType); return FALSE; @@ -1520,90 +2016,28 @@ i965_prepare_composite(int op, PicturePtr source_picture, composite_op->mask_filter = sampler_state_filter_from_picture(mask_picture->filter); - if (composite_op->mask_filter < 0) { + if (composite_op->mask_filter == SS_INVALID_FILTER) { intel_debug_fallback(scrn, "Bad mask filter 0x%x\n", mask_picture->filter); return FALSE; } composite_op->mask_extend = sampler_state_extend_from_picture(mask_picture->repeatType); - if (composite_op->mask_extend < 0) { + if (composite_op->mask_extend == SS_INVALID_EXTEND) { intel_debug_fallback(scrn, "Bad mask repeat 0x%x\n", mask_picture->repeatType); return FALSE; } } else { - composite_op->mask_filter = SAMPLER_STATE_FILTER_NEAREST; - composite_op->mask_extend = SAMPLER_STATE_EXTEND_NONE; + composite_op->mask_filter = SS_FILTER_NEAREST; + composite_op->mask_extend = SS_EXTEND_NONE; } /* Flush any pending writes prior to relocating the textures. */ - if(i830_uxa_pixmap_is_dirty(source) || - (mask && i830_uxa_pixmap_is_dirty(mask))) + if (intel_pixmap_is_dirty(source) || + (mask && intel_pixmap_is_dirty(mask))) intel_batch_emit_flush(scrn); - - /* Set up the surface states. */ - surface_state_bo = dri_bo_alloc(intel->bufmgr, "surface_state", - 3 * sizeof(brw_surface_state_padded), - 4096); - if (dri_bo_map(surface_state_bo, 1) != 0) { - dri_bo_unreference(surface_state_bo); - return FALSE; - } - /* Set up the state buffer for the destination surface */ - i965_set_picture_surface_state(intel, surface_state_bo, 0, - dest_picture, dest, TRUE); - /* Set up the source surface state buffer */ - i965_set_picture_surface_state(intel, surface_state_bo, 1, - source_picture, source, FALSE); - if (mask) { - /* Set up the mask surface state buffer */ - i965_set_picture_surface_state(intel, surface_state_bo, 2, - mask_picture, mask, FALSE); - } - dri_bo_unmap(surface_state_bo); - - /* Set up the binding table of surface indices to surface state. */ - binding_table_bo = dri_bo_alloc(intel->bufmgr, "binding_table", - 3 * sizeof(uint32_t), 4096); - if (dri_bo_map(binding_table_bo, 1) != 0) { - dri_bo_unreference(binding_table_bo); - dri_bo_unreference(surface_state_bo); - return FALSE; - } - - binding_table = binding_table_bo->virtual; - binding_table[0] = intel_emit_reloc(binding_table_bo, - 0 * sizeof(uint32_t), - surface_state_bo, - 0 * - sizeof(brw_surface_state_padded), - I915_GEM_DOMAIN_INSTRUCTION, 0); - - binding_table[1] = intel_emit_reloc(binding_table_bo, - 1 * sizeof(uint32_t), - surface_state_bo, - 1 * - sizeof(brw_surface_state_padded), - I915_GEM_DOMAIN_INSTRUCTION, 0); - - if (mask) { - binding_table[2] = intel_emit_reloc(binding_table_bo, - 2 * sizeof(uint32_t), - surface_state_bo, - 2 * - sizeof - (brw_surface_state_padded), - I915_GEM_DOMAIN_INSTRUCTION, - 0); - } else { - binding_table[2] = 0; - } - dri_bo_unmap(binding_table_bo); - /* All refs to surface_state are now contained in binding_table_bo. */ - drm_intel_bo_unreference(surface_state_bo); - composite_op->op = op; intel->render_source_picture = source_picture; intel->render_mask_picture = mask_picture; @@ -1611,14 +2045,12 @@ i965_prepare_composite(int op, PicturePtr source_picture, intel->render_source = source; intel->render_mask = mask; intel->render_dest = dest; - drm_intel_bo_unreference(composite_op->binding_table_bo); - composite_op->binding_table_bo = binding_table_bo; - intel->scale_units[0][0] = source->drawable.width; - intel->scale_units[0][1] = source->drawable.height; + intel->scale_units[0][0] = 1. / source->drawable.width; + intel->scale_units[0][1] = 1. / source->drawable.height; intel->transform[0] = source_picture->transform; - composite_op->is_affine = i830_transform_is_affine(intel->transform[0]); + composite_op->is_affine = intel_transform_is_affine(intel->transform[0]); if (!mask) { intel->transform[1] = NULL; @@ -1626,10 +2058,10 @@ i965_prepare_composite(int op, PicturePtr source_picture, intel->scale_units[1][1] = -1; } else { intel->transform[1] = mask_picture->transform; - intel->scale_units[1][0] = mask->drawable.width; - intel->scale_units[1][1] = mask->drawable.height; + intel->scale_units[1][0] = 1. / mask->drawable.width; + intel->scale_units[1][1] = 1. / mask->drawable.height; composite_op->is_affine &= - i830_transform_is_affine(intel->transform[1]); + intel_transform_is_affine(intel->transform[1]); } if (mask) { @@ -1665,9 +2097,23 @@ i965_prepare_composite(int op, PicturePtr source_picture, composite_op->wm_kernel = WM_KERNEL_NOMASK_PROJECTIVE; } - if (!i965_composite_check_aperture(scrn)) { - intel_batch_submit(scrn, FALSE); - if (!i965_composite_check_aperture(scrn)) { + intel->prim_emit = i965_emit_composite_primitive; + if (!mask) { + if (intel->transform[0] == NULL) + intel->prim_emit = i965_emit_composite_primitive_identity_source; + else if (composite_op->is_affine) + intel->prim_emit = i965_emit_composite_primitive_affine_source; + } else { + if (intel->transform[0] == NULL && intel->transform[1] == NULL) + intel->prim_emit = i965_emit_composite_primitive_identity_source_mask; + } + + intel->floats_per_vertex = + 2 + (mask ? 2 : 1) * (composite_op->is_affine ? 2: 3); + + if (!i965_composite_check_aperture(intel)) { + intel_batch_submit(scrn); + if (!i965_composite_check_aperture(intel)) { intel_debug_fallback(scrn, "Couldn't fit render operation " "in aperture\n"); @@ -1675,35 +2121,81 @@ i965_prepare_composite(int op, PicturePtr source_picture, } } + if (sizeof(intel->surface_data) - intel->surface_used < + 4 * SURFACE_STATE_PADDED_SIZE) + i965_surface_flush(intel); + intel->needs_render_state_emit = TRUE; return TRUE; } -static drm_intel_bo *i965_get_vb_space(ScrnInfoPtr scrn) +static void i965_select_vertex_buffer(struct intel_screen_private *intel) { - intel_screen_private *intel = intel_get_screen_private(scrn); - struct gen4_render_state *render_state = intel->gen4_render_state; + int id = intel->gen4_render_state->composite_op.vertex_id; + int modifyenable = 0; + + if (intel->vertex_id & (1 << id)) + return; + + if (INTEL_INFO(intel)->gen >= 70) + modifyenable = GEN7_VB0_ADDRESS_MODIFYENABLE; - /* If the vertex buffer is too full, then we free the old and a new one - * gets made. + /* Set up the pointer to our (single) vertex buffer */ + OUT_BATCH(BRW_3DSTATE_VERTEX_BUFFERS | 3); + + /* XXX could use multiple vbo to reduce relocations if + * frequently switching between vertex sizes, like rgb10text. */ - if (render_state->vb_offset + VERTEX_FLOATS_PER_COMPOSITE > - VERTEX_BUFFER_SIZE) { - drm_intel_bo_unreference(render_state->vertex_buffer_bo); - render_state->vertex_buffer_bo = NULL; + if (INTEL_INFO(intel)->gen >= 60) { + OUT_BATCH((id << GEN6_VB0_BUFFER_INDEX_SHIFT) | + GEN6_VB0_VERTEXDATA | + modifyenable | + (4*intel->floats_per_vertex << VB0_BUFFER_PITCH_SHIFT)); + } else { + OUT_BATCH((id << VB0_BUFFER_INDEX_SHIFT) | + VB0_VERTEXDATA | + (4*intel->floats_per_vertex << VB0_BUFFER_PITCH_SHIFT)); } + OUT_RELOC(intel->vertex_bo, I915_GEM_DOMAIN_VERTEX, 0, 0); + if (INTEL_INFO(intel)->gen >= 50) + OUT_RELOC(intel->vertex_bo, + I915_GEM_DOMAIN_VERTEX, 0, + sizeof(intel->vertex_ptr) - 1); + else + OUT_BATCH(0); + OUT_BATCH(0); // ignore for VERTEXDATA, but still there - /* Alloc a new vertex buffer if necessary. */ - if (render_state->vertex_buffer_bo == NULL) { - render_state->vertex_buffer_bo = - drm_intel_bo_alloc(intel->bufmgr, "vb", - sizeof(gen4_vertex_buffer), 4096); - render_state->vb_offset = 0; - } + intel->vertex_id |= 1 << id; +} - drm_intel_bo_reference(render_state->vertex_buffer_bo); - return render_state->vertex_buffer_bo; +static void i965_bind_surfaces(struct intel_screen_private *intel) +{ + uint32_t *binding_table; + + assert(intel->surface_used + 4 * SURFACE_STATE_PADDED_SIZE <= sizeof(intel->surface_data)); + + binding_table = (uint32_t*) (intel->surface_data + intel->surface_used); + intel->surface_table = intel->surface_used; + intel->surface_used += SURFACE_STATE_PADDED_SIZE; + + binding_table[0] = + i965_set_picture_surface_state(intel, + intel->render_dest_picture, + intel->render_dest, + TRUE); + binding_table[1] = + i965_set_picture_surface_state(intel, + intel->render_source_picture, + intel->render_source, + FALSE); + if (intel->render_mask) { + binding_table[2] = + i965_set_picture_surface_state(intel, + intel->render_mask_picture, + intel->render_mask, + FALSE); + } } void @@ -1712,184 +2204,82 @@ i965_composite(PixmapPtr dest, int srcX, int srcY, int maskX, int maskY, { ScrnInfoPtr scrn = xf86Screens[dest->drawable.pScreen->myNum]; intel_screen_private *intel = intel_get_screen_private(scrn); - struct gen4_render_state *render_state = intel->gen4_render_state; - Bool has_mask; - float src_x[3], src_y[3], src_w[3], mask_x[3], mask_y[3], mask_w[3]; - int i; - drm_intel_bo *vb_bo; - float vb[24]; /* 3 * (2 dst + 3 src + 3 mask) */ - Bool is_affine = render_state->composite_op.is_affine; - if (is_affine) { - if (!i830_get_transformed_coordinates(srcX, srcY, - intel->transform[0], - &src_x[0], &src_y[0])) - return; - if (!i830_get_transformed_coordinates(srcX, srcY + h, - intel->transform[0], - &src_x[1], &src_y[1])) - return; - if (!i830_get_transformed_coordinates(srcX + w, srcY + h, - intel->transform[0], - &src_x[2], &src_y[2])) - return; - } else { - if (!i830_get_transformed_coordinates_3d(srcX, srcY, - intel->transform[0], - &src_x[0], &src_y[0], - &src_w[0])) - return; - if (!i830_get_transformed_coordinates_3d(srcX, srcY + h, - intel->transform[0], - &src_x[1], &src_y[1], - &src_w[1])) - return; - if (!i830_get_transformed_coordinates_3d(srcX + w, srcY + h, - intel->transform[0], - &src_x[2], &src_y[2], - &src_w[2])) - return; - } + intel_batch_start_atomic(scrn, 200); + if (intel->needs_render_state_emit) { + i965_bind_surfaces(intel); - if (intel->scale_units[1][0] == -1 || intel->scale_units[1][1] == -1) { - has_mask = FALSE; - } else { - has_mask = TRUE; - if (is_affine) { - if (!i830_get_transformed_coordinates(maskX, maskY, - intel-> - transform[1], - &mask_x[0], - &mask_y[0])) - return; - if (!i830_get_transformed_coordinates(maskX, maskY + h, - intel-> - transform[1], - &mask_x[1], - &mask_y[1])) - return; - if (!i830_get_transformed_coordinates - (maskX + w, maskY + h, intel->transform[1], - &mask_x[2], &mask_y[2])) - return; - } else { - if (!i830_get_transformed_coordinates_3d(maskX, maskY, - intel-> - transform[1], - &mask_x[0], - &mask_y[0], - &mask_w[0])) - return; - if (!i830_get_transformed_coordinates_3d - (maskX, maskY + h, intel->transform[1], &mask_x[1], - &mask_y[1], &mask_w[1])) - return; - if (!i830_get_transformed_coordinates_3d - (maskX + w, maskY + h, intel->transform[1], - &mask_x[2], &mask_y[2], &mask_w[2])) - return; - } + if (INTEL_INFO(intel)->gen >= 60) + gen6_emit_composite_state(intel); + else + i965_emit_composite_state(intel); } - vb_bo = i965_get_vb_space(scrn); - if (vb_bo == NULL) - return; - i = 0; - /* rect (x2,y2) */ - vb[i++] = (float)(dstX + w); - vb[i++] = (float)(dstY + h); - vb[i++] = src_x[2] / intel->scale_units[0][0]; - vb[i++] = src_y[2] / intel->scale_units[0][1]; - if (!is_affine) - vb[i++] = src_w[2]; - if (has_mask) { - vb[i++] = mask_x[2] / intel->scale_units[1][0]; - vb[i++] = mask_y[2] / intel->scale_units[1][1]; - if (!is_affine) - vb[i++] = mask_w[2]; + if (intel->floats_per_vertex != intel->last_floats_per_vertex) { + intel->vertex_index = (intel->vertex_used + intel->floats_per_vertex - 1) / intel->floats_per_vertex; + intel->vertex_used = intel->vertex_index * intel->floats_per_vertex; + intel->last_floats_per_vertex = intel->floats_per_vertex; } - - /* rect (x1,y2) */ - vb[i++] = (float)dstX; - vb[i++] = (float)(dstY + h); - vb[i++] = src_x[1] / intel->scale_units[0][0]; - vb[i++] = src_y[1] / intel->scale_units[0][1]; - if (!is_affine) - vb[i++] = src_w[1]; - if (has_mask) { - vb[i++] = mask_x[1] / intel->scale_units[1][0]; - vb[i++] = mask_y[1] / intel->scale_units[1][1]; - if (!is_affine) - vb[i++] = mask_w[1]; + if (intel_vertex_space(intel) < 3*4*intel->floats_per_vertex) { + i965_vertex_flush(intel); + intel_next_vertex(intel); + intel->vertex_index = 0; } + i965_select_vertex_buffer(intel); - /* rect (x1,y1) */ - vb[i++] = (float)dstX; - vb[i++] = (float)dstY; - vb[i++] = src_x[0] / intel->scale_units[0][0]; - vb[i++] = src_y[0] / intel->scale_units[0][1]; - if (!is_affine) - vb[i++] = src_w[0]; - if (has_mask) { - vb[i++] = mask_x[0] / intel->scale_units[1][0]; - vb[i++] = mask_y[0] / intel->scale_units[1][1]; - if (!is_affine) - vb[i++] = mask_w[0]; + if (intel->vertex_offset == 0) { + if (INTEL_INFO(intel)->gen >= 70) { + OUT_BATCH(BRW_3DPRIMITIVE | (7 - 2)); + OUT_BATCH(BRW_3DPRIMITIVE_VERTEX_SEQUENTIAL | + _3DPRIM_RECTLIST); + } else { + OUT_BATCH(BRW_3DPRIMITIVE | + BRW_3DPRIMITIVE_VERTEX_SEQUENTIAL | + (_3DPRIM_RECTLIST << BRW_3DPRIMITIVE_TOPOLOGY_SHIFT) | + (0 << 9) | + 4); + } + intel->vertex_offset = intel->batch_used; + OUT_BATCH(0); /* vertex count, to be filled in later */ + OUT_BATCH(intel->vertex_index); + OUT_BATCH(1); /* single instance */ + OUT_BATCH(0); /* start instance location */ + OUT_BATCH(0); /* index buffer offset, ignored */ + intel->vertex_count = intel->vertex_index; } - drm_intel_bo_subdata(vb_bo, render_state->vb_offset * 4, i * 4, vb); - - if (!i965_composite_check_aperture(scrn)) - intel_batch_submit(scrn, FALSE); - - intel_batch_start_atomic(scrn, 200); - if (intel->needs_render_state_emit) - i965_emit_composite_state(scrn); - - OUT_BATCH(MI_FLUSH); - /* Set up the pointer to our (single) vertex buffer */ - OUT_BATCH(BRW_3DSTATE_VERTEX_BUFFERS | 3); - OUT_BATCH((0 << VB0_BUFFER_INDEX_SHIFT) | - VB0_VERTEXDATA | - (render_state->vertex_size << VB0_BUFFER_PITCH_SHIFT)); - OUT_RELOC(vb_bo, I915_GEM_DOMAIN_VERTEX, 0, - render_state->vb_offset * 4); - - if (IS_IGDNG(intel)) - OUT_RELOC(vb_bo, I915_GEM_DOMAIN_VERTEX, 0, - render_state->vb_offset * 4 + i * 4); - else - OUT_BATCH(3); - - OUT_BATCH(0); // ignore for VERTEXDATA, but still there - OUT_BATCH(BRW_3DPRIMITIVE | BRW_3DPRIMITIVE_VERTEX_SEQUENTIAL | (_3DPRIM_RECTLIST << BRW_3DPRIMITIVE_TOPOLOGY_SHIFT) | (0 << 9) | /* CTG - indirect vertex count */ - 4); - OUT_BATCH(3); /* vertex count per instance */ - OUT_BATCH(0); /* start vertex offset */ - OUT_BATCH(1); /* single instance */ - OUT_BATCH(0); /* start instance location */ - OUT_BATCH(0); /* index buffer offset, ignored */ - - render_state->vb_offset += i; - drm_intel_bo_unreference(vb_bo); + intel->prim_emit(intel, + srcX, srcY, + maskX, maskY, + dstX, dstY, + w, h); + intel->vertex_index += 3; + + if (INTEL_INFO(intel)->gen < 50) { + /* XXX OMG! */ + i965_vertex_flush(intel); + OUT_BATCH(MI_FLUSH | MI_INHIBIT_RENDER_CACHE_FLUSH); + } intel_batch_end_atomic(scrn); } -void i965_batch_flush_notify(ScrnInfoPtr scrn) +void i965_batch_commit_notify(intel_screen_private *intel) { - intel_screen_private *intel = intel_get_screen_private(scrn); - struct gen4_render_state *render_state = intel->gen4_render_state; + intel->needs_render_state_emit = TRUE; + intel->needs_3d_invariant = TRUE; + intel->last_floats_per_vertex = 0; + intel->vertex_index = 0; - /* Once a batch is emitted, we never want to map again any buffer - * object being referenced by that batch, (which would be very - * expensive). */ - if (render_state->vertex_buffer_bo) { - dri_bo_unreference(render_state->vertex_buffer_bo); - render_state->vertex_buffer_bo = NULL; - } + intel->gen4_render_state->composite_op.vertex_id = -1; - intel->needs_render_state_emit = TRUE; + intel->gen6_render_state.num_sf_outputs = 0; + intel->gen6_render_state.samplers = NULL; + intel->gen6_render_state.blend = -1; + intel->gen6_render_state.kernel = NULL; + intel->gen6_render_state.drawrect = -1; + + assert(intel->surface_reloc == 0); } /** @@ -1898,116 +2288,98 @@ void i965_batch_flush_notify(ScrnInfoPtr scrn) void gen4_render_state_init(ScrnInfoPtr scrn) { intel_screen_private *intel = intel_get_screen_private(scrn); - struct gen4_render_state *render_state; + struct gen4_render_state *render; + const struct wm_kernel_info *wm_kernels; int i, j, k, l, m; drm_intel_bo *sf_kernel_bo, *sf_kernel_mask_bo; drm_intel_bo *border_color_bo; + intel->needs_3d_invariant = TRUE; + + intel->surface_bo = + drm_intel_bo_alloc(intel->bufmgr, "surface data", + sizeof(intel->surface_data), 4096); + intel->surface_used = 0; + if (intel->gen4_render_state == NULL) - intel->gen4_render_state = calloc(sizeof(*render_state), 1); + intel->gen4_render_state = calloc(sizeof(*render), 1); - render_state = intel->gen4_render_state; - render_state->vb_offset = 0; + if (INTEL_INFO(intel)->gen >= 60) + return gen6_render_state_init(scrn); - render_state->vs_state_bo = gen4_create_vs_unit_state(scrn); + render = intel->gen4_render_state; + render->composite_op.vertex_id = -1; + + render->vs_state_bo = gen4_create_vs_unit_state(intel); /* Set up the two SF states (one for blending with a mask, one without) */ - if (IS_IGDNG(intel)) { - sf_kernel_bo = intel_bo_alloc_for_data(scrn, + if (IS_GEN5(intel)) { + sf_kernel_bo = intel_bo_alloc_for_data(intel, sf_kernel_static_gen5, sizeof (sf_kernel_static_gen5), "sf kernel gen5"); sf_kernel_mask_bo = - intel_bo_alloc_for_data(scrn, sf_kernel_mask_static_gen5, + intel_bo_alloc_for_data(intel, sf_kernel_mask_static_gen5, sizeof(sf_kernel_mask_static_gen5), "sf mask kernel"); } else { - sf_kernel_bo = intel_bo_alloc_for_data(scrn, + sf_kernel_bo = intel_bo_alloc_for_data(intel, sf_kernel_static, sizeof(sf_kernel_static), "sf kernel"); - sf_kernel_mask_bo = intel_bo_alloc_for_data(scrn, + sf_kernel_mask_bo = intel_bo_alloc_for_data(intel, sf_kernel_mask_static, sizeof (sf_kernel_mask_static), "sf mask kernel"); } - render_state->sf_state_bo = gen4_create_sf_state(scrn, sf_kernel_bo); - render_state->sf_mask_state_bo = gen4_create_sf_state(scrn, - sf_kernel_mask_bo); + render->sf_state_bo = gen4_create_sf_state(intel, sf_kernel_bo); + render->sf_mask_state_bo = gen4_create_sf_state(intel, sf_kernel_mask_bo); drm_intel_bo_unreference(sf_kernel_bo); drm_intel_bo_unreference(sf_kernel_mask_bo); - for (m = 0; m < WM_KERNEL_COUNT; m++) { - if (IS_IGDNG(intel)) - render_state->wm_kernel_bo[m] = - intel_bo_alloc_for_data(scrn, - wm_kernels_gen5[m].data, - wm_kernels_gen5[m].size, - "WM kernel gen5"); - else - render_state->wm_kernel_bo[m] = - intel_bo_alloc_for_data(scrn, - wm_kernels[m].data, - wm_kernels[m].size, - "WM kernel"); + wm_kernels = IS_GEN5(intel) ? wm_kernels_gen5 : wm_kernels_gen4; + for (m = 0; m < KERNEL_COUNT; m++) { + render->wm_kernel_bo[m] = + intel_bo_alloc_for_data(intel, + wm_kernels[m].data, + wm_kernels[m].size, + "WM kernel"); } /* Set up the WM states: each filter/extend type for source and mask, per * kernel. */ - border_color_bo = sampler_border_color_create(scrn); - for (i = 0; i < SAMPLER_STATE_FILTER_COUNT; i++) { - for (j = 0; j < SAMPLER_STATE_EXTEND_COUNT; j++) { - for (k = 0; k < SAMPLER_STATE_FILTER_COUNT; k++) { - for (l = 0; l < SAMPLER_STATE_EXTEND_COUNT; l++) { + border_color_bo = sampler_border_color_create(intel); + for (i = 0; i < FILTER_COUNT; i++) { + for (j = 0; j < EXTEND_COUNT; j++) { + for (k = 0; k < FILTER_COUNT; k++) { + for (l = 0; l < EXTEND_COUNT; l++) { drm_intel_bo *sampler_state_bo; sampler_state_bo = - gen4_create_sampler_state(scrn, + i965_create_sampler_state(intel, i, j, k, l, border_color_bo); - for (m = 0; m < WM_KERNEL_COUNT; m++) { - if (IS_IGDNG(intel)) - render_state-> - wm_state_bo[m][i][j] - [k][l] = - gen4_create_wm_state - (scrn, - wm_kernels_gen5[m]. - has_mask, - render_state-> - wm_kernel_bo[m], - sampler_state_bo); - else - render_state-> - wm_state_bo[m][i][j] - [k][l] = - gen4_create_wm_state - (scrn, - wm_kernels[m]. - has_mask, - render_state-> - wm_kernel_bo[m], - sampler_state_bo); + for (m = 0; m < KERNEL_COUNT; m++) { + render->wm_state_bo[m][i][j][k][l] = + gen4_create_wm_state + (intel, + wm_kernels[m]. has_mask, + render->wm_kernel_bo[m], + sampler_state_bo); } - drm_intel_bo_unreference - (sampler_state_bo); + drm_intel_bo_unreference(sampler_state_bo); } } } } drm_intel_bo_unreference(border_color_bo); - render_state->cc_state_bo = gen4_create_cc_unit_state(scrn); - render_state->sip_kernel_bo = intel_bo_alloc_for_data(scrn, - sip_kernel_static, - sizeof - (sip_kernel_static), - "sip kernel"); + render->cc_state_bo = gen4_create_cc_unit_state(intel); } /** @@ -2018,31 +2390,496 @@ void gen4_render_state_cleanup(ScrnInfoPtr scrn) intel_screen_private *intel = intel_get_screen_private(scrn); struct gen4_render_state *render_state = intel->gen4_render_state; int i, j, k, l, m; - gen4_composite_op *composite_op = &render_state->composite_op; - - drm_intel_bo_unreference(composite_op->binding_table_bo); - drm_intel_bo_unreference(render_state->vertex_buffer_bo); + drm_intel_bo_unreference(intel->surface_bo); drm_intel_bo_unreference(render_state->vs_state_bo); drm_intel_bo_unreference(render_state->sf_state_bo); drm_intel_bo_unreference(render_state->sf_mask_state_bo); - for (i = 0; i < WM_KERNEL_COUNT; i++) + for (i = 0; i < KERNEL_COUNT; i++) drm_intel_bo_unreference(render_state->wm_kernel_bo[i]); - for (i = 0; i < SAMPLER_STATE_FILTER_COUNT; i++) - for (j = 0; j < SAMPLER_STATE_EXTEND_COUNT; j++) - for (k = 0; k < SAMPLER_STATE_FILTER_COUNT; k++) - for (l = 0; l < SAMPLER_STATE_EXTEND_COUNT; l++) - for (m = 0; m < WM_KERNEL_COUNT; m++) + for (i = 0; i < FILTER_COUNT; i++) + for (j = 0; j < EXTEND_COUNT; j++) + for (k = 0; k < FILTER_COUNT; k++) + for (l = 0; l < EXTEND_COUNT; l++) + for (m = 0; m < KERNEL_COUNT; m++) drm_intel_bo_unreference (render_state-> wm_state_bo[m][i][j][k] [l]); + for (i = 0; i < FILTER_COUNT; i++) + for (j = 0; j < EXTEND_COUNT; j++) + for (k = 0; k < FILTER_COUNT; k++) + for (l = 0; l < EXTEND_COUNT; l++) + drm_intel_bo_unreference(render_state->ps_sampler_state_bo[i][j][k][l]); + drm_intel_bo_unreference(render_state->cc_state_bo); - drm_intel_bo_unreference(render_state->sip_kernel_bo); + + drm_intel_bo_unreference(render_state->cc_vp_bo); + drm_intel_bo_unreference(render_state->gen6_blend_bo); + drm_intel_bo_unreference(render_state->gen6_depth_stencil_bo); free(intel->gen4_render_state); intel->gen4_render_state = NULL; } + +/* + * for GEN6+ + */ +#define GEN6_BLEND_STATE_PADDED_SIZE ALIGN(sizeof(struct gen6_blend_state), 64) + +static drm_intel_bo * +gen6_composite_create_cc_state(intel_screen_private *intel) +{ + struct gen6_color_calc_state *state; + drm_intel_bo *cc_bo; + + cc_bo = drm_intel_bo_alloc(intel->bufmgr, + "gen6 CC state", + sizeof(*state), + 4096); + drm_intel_bo_map(cc_bo, TRUE); + state = cc_bo->virtual; + memset(state, 0, sizeof(*state)); + state->constant_r = 1.0; + state->constant_g = 0.0; + state->constant_b = 1.0; + state->constant_a = 1.0; + drm_intel_bo_unmap(cc_bo); + + return cc_bo; +} + +static drm_intel_bo * +gen6_composite_create_blend_state(intel_screen_private *intel) +{ + drm_intel_bo *blend_bo; + int src, dst; + + blend_bo = drm_intel_bo_alloc(intel->bufmgr, + "gen6 BLEND state", + BRW_BLENDFACTOR_COUNT * BRW_BLENDFACTOR_COUNT * GEN6_BLEND_STATE_PADDED_SIZE, + 4096); + drm_intel_bo_map(blend_bo, TRUE); + memset(blend_bo->virtual, 0, blend_bo->size); + + for (src = 0; src < BRW_BLENDFACTOR_COUNT; src++) { + for (dst = 0; dst < BRW_BLENDFACTOR_COUNT; dst++) { + uint32_t blend_state_offset = (src * BRW_BLENDFACTOR_COUNT + dst) * GEN6_BLEND_STATE_PADDED_SIZE; + struct gen6_blend_state *blend; + + blend = (struct gen6_blend_state *)((char *)blend_bo->virtual + blend_state_offset); + blend->blend0.dest_blend_factor = dst; + blend->blend0.source_blend_factor = src; + blend->blend0.blend_func = BRW_BLENDFUNCTION_ADD; + blend->blend0.blend_enable = 1; + + blend->blend1.post_blend_clamp_enable = 1; + blend->blend1.pre_blend_clamp_enable = 1; + } + } + + drm_intel_bo_unmap(blend_bo); + return blend_bo; +} + +static drm_intel_bo * +gen6_composite_create_depth_stencil_state(intel_screen_private *intel) +{ + struct gen6_depth_stencil_state *state; + drm_intel_bo *depth_stencil_bo; + + depth_stencil_bo = drm_intel_bo_alloc(intel->bufmgr, + "gen6 DEPTH_STENCIL state", + sizeof(*state), + 4096); + drm_intel_bo_map(depth_stencil_bo, TRUE); + state = depth_stencil_bo->virtual; + memset(state, 0, sizeof(*state)); + drm_intel_bo_unmap(depth_stencil_bo); + + return depth_stencil_bo; +} + +static void +gen6_composite_state_base_address(intel_screen_private *intel) +{ + OUT_BATCH(BRW_STATE_BASE_ADDRESS | (10 - 2)); + OUT_BATCH(BASE_ADDRESS_MODIFY); /* General state base address */ + intel->surface_reloc = intel->batch_used; + intel_batch_emit_dword(intel, + intel->surface_bo->offset | BASE_ADDRESS_MODIFY); + OUT_BATCH(BASE_ADDRESS_MODIFY); /* Dynamic state base address */ + OUT_BATCH(BASE_ADDRESS_MODIFY); /* Indirect object base address */ + OUT_BATCH(BASE_ADDRESS_MODIFY); /* Instruction base address */ + OUT_BATCH(BASE_ADDRESS_MODIFY); /* General state upper bound */ + OUT_BATCH(BASE_ADDRESS_MODIFY); /* Dynamic state upper bound */ + OUT_BATCH(BASE_ADDRESS_MODIFY); /* Indirect object upper bound */ + OUT_BATCH(BASE_ADDRESS_MODIFY); /* Instruction access upper bound */ +} + +static void +gen6_composite_cc_state_pointers(intel_screen_private *intel, + uint32_t blend_offset) +{ + struct gen4_render_state *render_state = intel->gen4_render_state; + drm_intel_bo *cc_bo = NULL; + drm_intel_bo *depth_stencil_bo = NULL; + + if (intel->gen6_render_state.blend == blend_offset) + return; + + if (intel->gen6_render_state.blend == -1) { + cc_bo = render_state->cc_state_bo; + depth_stencil_bo = render_state->gen6_depth_stencil_bo; + } + if (INTEL_INFO(intel)->gen >= 70) { + gen7_upload_cc_state_pointers(intel, render_state->gen6_blend_bo, cc_bo, depth_stencil_bo, blend_offset); + } else { + gen6_upload_cc_state_pointers(intel, render_state->gen6_blend_bo, cc_bo, depth_stencil_bo, blend_offset); + } + + intel->gen6_render_state.blend = blend_offset; +} + +static void +gen6_composite_sampler_state_pointers(intel_screen_private *intel, + drm_intel_bo *bo) +{ + if (intel->gen6_render_state.samplers == bo) + return; + + intel->gen6_render_state.samplers = bo; + + if (INTEL_INFO(intel)->gen >= 70) + gen7_upload_sampler_state_pointers(intel, bo); + else + gen6_upload_sampler_state_pointers(intel, bo); +} + +static void +gen6_composite_wm_constants(intel_screen_private *intel) +{ + Bool ivb = INTEL_INFO(intel)->gen >= 70; + /* disable WM constant buffer */ + OUT_BATCH(GEN6_3DSTATE_CONSTANT_PS | ((ivb ? 7 : 5) - 2)); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + if (ivb) { + OUT_BATCH(0); + OUT_BATCH(0); + } +} + +static void +gen6_composite_sf_state(intel_screen_private *intel, + Bool has_mask) +{ + int num_sf_outputs = has_mask ? 2 : 1; + + if (intel->gen6_render_state.num_sf_outputs == num_sf_outputs) + return; + + intel->gen6_render_state.num_sf_outputs = num_sf_outputs; + + if (INTEL_INFO(intel)->gen >= 70) + gen7_upload_sf_state(intel, num_sf_outputs, 1); + else + gen6_upload_sf_state(intel, num_sf_outputs, 1); +} + +static void +gen6_composite_wm_state(intel_screen_private *intel, + Bool has_mask, + drm_intel_bo *bo) +{ + int num_surfaces = has_mask ? 3 : 2; + int num_sf_outputs = has_mask ? 2 : 1; + + if (intel->gen6_render_state.kernel == bo) + return; + + intel->gen6_render_state.kernel = bo; + + OUT_BATCH(GEN6_3DSTATE_WM | (9 - 2)); + OUT_RELOC(bo, + I915_GEM_DOMAIN_INSTRUCTION, 0, + 0); + OUT_BATCH((1 << GEN6_3DSTATE_WM_SAMPLER_COUNT_SHITF) | + (num_surfaces << GEN6_3DSTATE_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT)); + OUT_BATCH(0); + OUT_BATCH((6 << GEN6_3DSTATE_WM_DISPATCH_START_GRF_0_SHIFT)); /* DW4 */ + OUT_BATCH(((40 - 1) << GEN6_3DSTATE_WM_MAX_THREADS_SHIFT) | + GEN6_3DSTATE_WM_DISPATCH_ENABLE | + GEN6_3DSTATE_WM_16_DISPATCH_ENABLE); + OUT_BATCH((num_sf_outputs << GEN6_3DSTATE_WM_NUM_SF_OUTPUTS_SHIFT) | + GEN6_3DSTATE_WM_PERSPECTIVE_PIXEL_BARYCENTRIC); + OUT_BATCH(0); + OUT_BATCH(0); +} + +static void +gen7_composite_wm_state(intel_screen_private *intel, + Bool has_mask, + drm_intel_bo *bo) +{ + int num_surfaces = has_mask ? 3 : 2; + + if (intel->gen6_render_state.kernel == bo) + return; + + intel->gen6_render_state.kernel = bo; + + OUT_BATCH(GEN6_3DSTATE_WM | (3 - 2)); + OUT_BATCH(GEN7_WM_DISPATCH_ENABLE | + GEN7_WM_PERSPECTIVE_PIXEL_BARYCENTRIC); + OUT_BATCH(0); + + OUT_BATCH(GEN7_3DSTATE_PS | (8 - 2)); + OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); + OUT_BATCH((1 << GEN7_PS_SAMPLER_COUNT_SHIFT) | + (num_surfaces << GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT)); + OUT_BATCH(0); /* scratch space base offset */ + OUT_BATCH(((86 - 1) << GEN7_PS_MAX_THREADS_SHIFT) | + GEN7_PS_ATTRIBUTE_ENABLE | + GEN7_PS_16_DISPATCH_ENABLE); + OUT_BATCH((6 << GEN7_PS_DISPATCH_START_GRF_SHIFT_0)); + OUT_BATCH(0); /* kernel 1 pointer */ + OUT_BATCH(0); /* kernel 2 pointer */ +} + + +static void +gen6_composite_drawing_rectangle(intel_screen_private *intel, + PixmapPtr dest) +{ + uint32_t dw = + DRAW_YMAX(dest->drawable.height - 1) | + DRAW_XMAX(dest->drawable.width - 1); + + /* XXX cacomposite depends upon the implicit non-pipelined flush */ + if (0 && intel->gen6_render_state.drawrect == dw) + return; + intel->gen6_render_state.drawrect = dw; + + OUT_BATCH(BRW_3DSTATE_DRAWING_RECTANGLE | (4 - 2)); + OUT_BATCH(0x00000000); /* ymin, xmin */ + OUT_BATCH(dw); /* ymax, xmax */ + OUT_BATCH(0x00000000); /* yorigin, xorigin */ +} + +static void +gen6_composite_vertex_element_state(intel_screen_private *intel, + Bool has_mask, + Bool is_affine) +{ + /* + * vertex data in vertex buffer + * position: (x, y) + * texture coordinate 0: (u0, v0) if (is_affine is TRUE) else (u0, v0, w0) + * texture coordinate 1 if (has_mask is TRUE): same as above + */ + gen4_composite_op *composite_op = &intel->gen4_render_state->composite_op; + int nelem = has_mask ? 2 : 1; + int selem = is_affine ? 2 : 3; + uint32_t w_component; + uint32_t src_format; + int id; + + id = has_mask << 1 | is_affine; + + if (composite_op->vertex_id == id) + return; + + composite_op->vertex_id = id; + + if (is_affine) { + src_format = BRW_SURFACEFORMAT_R32G32_FLOAT; + w_component = BRW_VFCOMPONENT_STORE_1_FLT; + } else { + src_format = BRW_SURFACEFORMAT_R32G32B32_FLOAT; + w_component = BRW_VFCOMPONENT_STORE_SRC; + } + + /* The VUE layout + * dword 0-3: pad (0.0, 0.0, 0.0. 0.0) + * dword 4-7: position (x, y, 1.0, 1.0), + * dword 8-11: texture coordinate 0 (u0, v0, w0, 1.0) + * dword 12-15: texture coordinate 1 (u1, v1, w1, 1.0) + * + * dword 4-15 are fetched from vertex buffer + */ + OUT_BATCH(BRW_3DSTATE_VERTEX_ELEMENTS | + ((2 * (2 + nelem)) + 1 - 2)); + + OUT_BATCH((id << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) | GEN6_VE0_VALID | + (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) | + (0 << VE0_OFFSET_SHIFT)); + OUT_BATCH((BRW_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT) | + (BRW_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT) | + (BRW_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT) | + (BRW_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT)); + + /* x,y */ + OUT_BATCH((id << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) | GEN6_VE0_VALID | + (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) | + (0 << VE0_OFFSET_SHIFT)); /* offsets vb in bytes */ + OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) | + (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) | + (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) | + (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT)); + + /* u0, v0, w0 */ + OUT_BATCH((id << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) | GEN6_VE0_VALID | + (src_format << VE0_FORMAT_SHIFT) | + ((2 * 4) << VE0_OFFSET_SHIFT)); /* offset vb in bytes */ + OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) | + (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) | + (w_component << VE1_VFCOMPONENT_2_SHIFT) | + (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT)); + + /* u1, v1, w1 */ + if (has_mask) { + OUT_BATCH((id << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) | + GEN6_VE0_VALID | + (src_format << VE0_FORMAT_SHIFT) | + (((2 + selem) * 4) << VE0_OFFSET_SHIFT)); /* vb offset in bytes */ + OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) | + (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) | + (w_component << VE1_VFCOMPONENT_2_SHIFT) | + (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT)); + } +} + +static void +gen6_emit_composite_state(struct intel_screen_private *intel) +{ + struct gen4_render_state *render = intel->gen4_render_state; + gen4_composite_op *composite_op = &render->composite_op; + sampler_state_filter_t src_filter = composite_op->src_filter; + sampler_state_filter_t mask_filter = composite_op->mask_filter; + sampler_state_extend_t src_extend = composite_op->src_extend; + sampler_state_extend_t mask_extend = composite_op->mask_extend; + Bool is_affine = composite_op->is_affine; + Bool has_mask = intel->render_mask != NULL; + Bool ivb = INTEL_INFO(intel)->gen >= 70; + uint32_t src, dst; + drm_intel_bo *ps_sampler_state_bo = render->ps_sampler_state_bo[src_filter][src_extend][mask_filter][mask_extend]; + + intel->needs_render_state_emit = FALSE; + if (intel->needs_3d_invariant) { + gen6_upload_invariant_states(intel); + + if (ivb) { + gen7_upload_viewport_state_pointers(intel, render->cc_vp_bo); + gen7_upload_urb(intel); + gen7_upload_bypass_states(intel); + gen7_upload_depth_buffer_state(intel); + } else { + gen6_upload_invariant_states(intel); + gen6_upload_viewport_state_pointers(intel, render->cc_vp_bo); + gen6_upload_urb(intel); + + gen6_upload_gs_state(intel); + gen6_upload_depth_buffer_state(intel); + } + gen6_composite_wm_constants(intel); + gen6_upload_vs_state(intel); + gen6_upload_clip_state(intel); + + intel->needs_3d_invariant = FALSE; + } + + i965_get_blend_cntl(composite_op->op, + intel->render_mask_picture, + intel->render_dest_picture->format, + &src, &dst); + + if (intel->surface_reloc == 0) + gen6_composite_state_base_address(intel); + + gen6_composite_cc_state_pointers(intel, + (src * BRW_BLENDFACTOR_COUNT + dst) * GEN6_BLEND_STATE_PADDED_SIZE); + gen6_composite_sampler_state_pointers(intel, ps_sampler_state_bo); + gen6_composite_sf_state(intel, has_mask); + if (ivb) { + gen7_composite_wm_state(intel, has_mask, + render->wm_kernel_bo[composite_op->wm_kernel]); + gen7_upload_binding_table(intel, intel->surface_table); + } else { + gen6_composite_wm_state(intel, has_mask, + render->wm_kernel_bo[composite_op->wm_kernel]); + gen6_upload_binding_table(intel, intel->surface_table); + } + gen6_composite_drawing_rectangle(intel, intel->render_dest); + gen6_composite_vertex_element_state(intel, has_mask, is_affine); +} + +static void +gen6_render_state_init(ScrnInfoPtr scrn) +{ + intel_screen_private *intel = intel_get_screen_private(scrn); + struct gen4_render_state *render; + int i, j, k, l, m; + drm_intel_bo *border_color_bo; + const struct wm_kernel_info *wm_kernels; + + render= intel->gen4_render_state; + render->composite_op.vertex_id = -1; + + intel->gen6_render_state.num_sf_outputs = 0; + intel->gen6_render_state.samplers = NULL; + intel->gen6_render_state.blend = -1; + intel->gen6_render_state.kernel = NULL; + intel->gen6_render_state.drawrect = -1; + + wm_kernels = IS_GEN7(intel) ? wm_kernels_gen7 : wm_kernels_gen6; + for (m = 0; m < KERNEL_COUNT; m++) { + render->wm_kernel_bo[m] = + intel_bo_alloc_for_data(intel, + wm_kernels[m].data, + wm_kernels[m].size, + "WM kernel gen6/7"); + } + + border_color_bo = sampler_border_color_create(intel); + + for (i = 0; i < FILTER_COUNT; i++) { + for (j = 0; j < EXTEND_COUNT; j++) { + for (k = 0; k < FILTER_COUNT; k++) { + for (l = 0; l < EXTEND_COUNT; l++) { + render->ps_sampler_state_bo[i][j][k][l] = + i965_create_sampler_state(intel, + i, j, + k, l, + border_color_bo); + } + } + } + } + + drm_intel_bo_unreference(border_color_bo); + render->cc_vp_bo = gen4_create_cc_viewport(intel); + render->cc_state_bo = gen6_composite_create_cc_state(intel); + render->gen6_blend_bo = gen6_composite_create_blend_state(intel); + render->gen6_depth_stencil_bo = gen6_composite_create_depth_stencil_state(intel); +} + +void i965_vertex_flush(struct intel_screen_private *intel) +{ + if (intel->vertex_offset) { + intel->batch_ptr[intel->vertex_offset] = + intel->vertex_index - intel->vertex_count; + intel->vertex_offset = 0; + } +} + +void i965_batch_flush(struct intel_screen_private *intel) +{ + if (intel->surface_used) + i965_surface_flush(intel); +} diff --git a/driver/xf86-video-intel/src/i965_video.c b/driver/xf86-video-intel/src/i965_video.c index e25184b6a..7b30ac503 100644 --- a/driver/xf86-video-intel/src/i965_video.c +++ b/driver/xf86-video-intel/src/i965_video.c @@ -35,13 +35,16 @@ #include "xf86xv.h" #include "fourcc.h" -#include "i830.h" -#include "i830_video.h" -#include "i830_hwmc.h" +#include "intel.h" +#include "intel_hwmc.h" +#include "intel_video.h" +#include "i830_reg.h" +#include "i965_reg.h" #include "brw_defines.h" #include "brw_structs.h" #include <string.h> + /* Make assert() work. */ #undef NDEBUG #include <assert.h> @@ -131,6 +134,45 @@ static const uint32_t ps_kernel_planar_static_gen5[][4] = { #include "exa_wm_write.g4b.gen5" }; +/* programs for Sandybridge */ +static const uint32_t ps_kernel_packed_static_gen6[][4] = { +#include "exa_wm_src_affine.g6b" +#include "exa_wm_src_sample_argb.g6b" +#include "exa_wm_yuv_rgb.g6b" +#include "exa_wm_write.g6b" +}; + +static const uint32_t ps_kernel_planar_static_gen6[][4] = { +#include "exa_wm_src_affine.g6b" +#include "exa_wm_src_sample_planar.g6b" +#include "exa_wm_yuv_rgb.g6b" +#include "exa_wm_write.g6b" +}; + +/* programs for Ivybridge */ +static const uint32_t ps_kernel_packed_static_gen7[][4] = { +#include "exa_wm_src_affine.g7b" +#include "exa_wm_src_sample_argb.g7b" +#include "exa_wm_yuv_rgb.g7b" +#include "exa_wm_write.g7b" +}; + +static const uint32_t ps_kernel_planar_static_gen7[][4] = { +#include "exa_wm_src_affine.g7b" +#include "exa_wm_src_sample_planar.g7b" +#include "exa_wm_yuv_rgb.g7b" +#include "exa_wm_write.g7b" +}; + +#ifndef MAX2 +#define MAX2(a,b) ((a) > (b) ? (a) : (b)) +#endif + +#define SURFACE_STATE_PADDED_SIZE_I965 ALIGN(sizeof(struct brw_surface_state), 32) +#define SURFACE_STATE_PADDED_SIZE_GEN7 ALIGN(sizeof(struct gen7_surface_state), 32) +#define SURFACE_STATE_PADDED_SIZE MAX2(SURFACE_STATE_PADDED_SIZE_I965, SURFACE_STATE_PADDED_SIZE_GEN7) +#define SURFACE_STATE_OFFSET(index) (SURFACE_STATE_PADDED_SIZE * index) + static uint32_t float_to_uint(float f) { union { @@ -358,17 +400,20 @@ intel_alloc_and_map(intel_screen_private *intel, char *name, int size, return 0; } -static drm_intel_bo *i965_create_dst_surface_state(ScrnInfoPtr scrn, - PixmapPtr pixmap) +static void i965_create_dst_surface_state(ScrnInfoPtr scrn, + PixmapPtr pixmap, + drm_intel_bo *surf_bo, + uint32_t offset) { intel_screen_private *intel = intel_get_screen_private(scrn); struct brw_surface_state *dest_surf_state; - drm_intel_bo *pixmap_bo = i830_get_pixmap_bo(pixmap); - drm_intel_bo *surf_bo; + drm_intel_bo *pixmap_bo = intel_get_pixmap_bo(pixmap); - if (intel_alloc_and_map(intel, "textured video surface state", 4096, - &surf_bo, &dest_surf_state) != 0) - return NULL; + if (drm_intel_bo_map(surf_bo, TRUE) != 0) + return; + + dest_surf_state = (struct brw_surface_state *)((char *)surf_bo->virtual + offset); + memset(dest_surf_state, 0, sizeof(*dest_surf_state)); dest_surf_state->ss0.surface_type = BRW_SURFACE_2D; dest_surf_state->ss0.data_return_format = @@ -391,36 +436,37 @@ static drm_intel_bo *i965_create_dst_surface_state(ScrnInfoPtr scrn, dest_surf_state->ss0.render_cache_read_mode = 0; dest_surf_state->ss1.base_addr = - intel_emit_reloc(surf_bo, offsetof(struct brw_surface_state, ss1), + intel_emit_reloc(surf_bo, offset + offsetof(struct brw_surface_state, ss1), pixmap_bo, 0, I915_GEM_DOMAIN_SAMPLER, 0); - dest_surf_state->ss2.height = scrn->virtualY - 1; - dest_surf_state->ss2.width = scrn->virtualX - 1; + dest_surf_state->ss2.height = pixmap->drawable.height - 1; + dest_surf_state->ss2.width = pixmap->drawable.width - 1; dest_surf_state->ss2.mip_count = 0; dest_surf_state->ss2.render_target_rotation = 0; - dest_surf_state->ss3.pitch = intel_get_pixmap_pitch(pixmap) - 1; - dest_surf_state->ss3.tiled_surface = i830_pixmap_tiled(pixmap); + dest_surf_state->ss3.pitch = intel_pixmap_pitch(pixmap) - 1; + dest_surf_state->ss3.tiled_surface = intel_pixmap_tiled(pixmap); dest_surf_state->ss3.tile_walk = 0; /* TileX */ drm_intel_bo_unmap(surf_bo); - return surf_bo; } -static drm_intel_bo *i965_create_src_surface_state(ScrnInfoPtr scrn, - drm_intel_bo * src_bo, - uint32_t src_offset, - int src_width, - int src_height, - int src_pitch, - uint32_t src_surf_format) +static void i965_create_src_surface_state(ScrnInfoPtr scrn, + drm_intel_bo * src_bo, + uint32_t src_offset, + int src_width, + int src_height, + int src_pitch, + uint32_t src_surf_format, + drm_intel_bo *surface_bo, + uint32_t offset) { - intel_screen_private *intel = intel_get_screen_private(scrn); - drm_intel_bo *surface_bo; struct brw_surface_state *src_surf_state; - if (intel_alloc_and_map(intel, "textured video surface state", 4096, - &surface_bo, &src_surf_state) != 0) - return NULL; + if (drm_intel_bo_map(surface_bo, TRUE) != 0) + return; + + src_surf_state = (struct brw_surface_state *)((char *)surface_bo->virtual + offset); + memset(src_surf_state, 0, sizeof(*src_surf_state)); /* Set up the source surface state buffer */ src_surf_state->ss0.surface_type = BRW_SURFACE_2D; @@ -444,7 +490,7 @@ static drm_intel_bo *i965_create_src_surface_state(ScrnInfoPtr scrn, if (src_bo) { src_surf_state->ss1.base_addr = intel_emit_reloc(surface_bo, - offsetof(struct brw_surface_state, ss1), + offset + offsetof(struct brw_surface_state, ss1), src_bo, src_offset, I915_GEM_DOMAIN_SAMPLER, 0); } else { @@ -452,31 +498,103 @@ static drm_intel_bo *i965_create_src_surface_state(ScrnInfoPtr scrn, } drm_intel_bo_unmap(surface_bo); - return surface_bo; } -static drm_intel_bo *i965_create_binding_table(ScrnInfoPtr scrn, - drm_intel_bo ** surf_bos, - int n_surf) +static void gen7_create_dst_surface_state(ScrnInfoPtr scrn, + PixmapPtr pixmap, + drm_intel_bo *surf_bo, + uint32_t offset) { intel_screen_private *intel = intel_get_screen_private(scrn); - drm_intel_bo *bind_bo; + struct gen7_surface_state *dest_surf_state; + drm_intel_bo *pixmap_bo = intel_get_pixmap_bo(pixmap); + + if (drm_intel_bo_map(surf_bo, TRUE) != 0) + return; + + dest_surf_state = (struct gen7_surface_state *)((char *)surf_bo->virtual + offset); + memset(dest_surf_state, 0, sizeof(*dest_surf_state)); + + dest_surf_state->ss0.surface_type = BRW_SURFACE_2D; + dest_surf_state->ss0.tiled_surface = intel_pixmap_tiled(pixmap); + dest_surf_state->ss0.tile_walk = 0; /* TileX */ + + if (intel->cpp == 2) { + dest_surf_state->ss0.surface_format = BRW_SURFACEFORMAT_B5G6R5_UNORM; + } else { + dest_surf_state->ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM; + } + + dest_surf_state->ss1.base_addr = + intel_emit_reloc(surf_bo, + offset + offsetof(struct gen7_surface_state, ss1), + pixmap_bo, 0, + I915_GEM_DOMAIN_SAMPLER, 0); + + dest_surf_state->ss2.height = pixmap->drawable.height - 1; + dest_surf_state->ss2.width = pixmap->drawable.width - 1; + + dest_surf_state->ss3.pitch = intel_pixmap_pitch(pixmap) - 1; + + drm_intel_bo_unmap(surf_bo); +} + +static void gen7_create_src_surface_state(ScrnInfoPtr scrn, + drm_intel_bo * src_bo, + uint32_t src_offset, + int src_width, + int src_height, + int src_pitch, + uint32_t src_surf_format, + drm_intel_bo *surface_bo, + uint32_t offset) +{ + struct gen7_surface_state *src_surf_state; + + if (drm_intel_bo_map(surface_bo, TRUE) != 0) + return; + + src_surf_state = (struct gen7_surface_state *)((char *)surface_bo->virtual + offset); + memset(src_surf_state, 0, sizeof(*src_surf_state)); + + src_surf_state->ss0.surface_type = BRW_SURFACE_2D; + src_surf_state->ss0.surface_format = src_surf_format; + + if (src_bo) { + src_surf_state->ss1.base_addr = + intel_emit_reloc(surface_bo, + offset + offsetof(struct gen7_surface_state, ss1), + src_bo, src_offset, + I915_GEM_DOMAIN_SAMPLER, 0); + } else { + src_surf_state->ss1.base_addr = src_offset; + } + + src_surf_state->ss2.width = src_width - 1; + src_surf_state->ss2.height = src_height - 1; + + src_surf_state->ss3.pitch = src_pitch - 1; + + drm_intel_bo_unmap(surface_bo); +} + +static void i965_create_binding_table(ScrnInfoPtr scrn, + drm_intel_bo *bind_bo, + int n_surf) +{ uint32_t *binding_table; int i; /* Set up a binding table for our surfaces. Only the PS will use it */ + if (drm_intel_bo_map(bind_bo, TRUE) != 0) + return; - if (intel_alloc_and_map(intel, "textured video binding table", 4096, - &bind_bo, &binding_table) != 0) - return NULL; + binding_table = (uint32_t*)((char *)bind_bo->virtual + n_surf * SURFACE_STATE_PADDED_SIZE); for (i = 0; i < n_surf; i++) - binding_table[i] = - intel_emit_reloc(bind_bo, i * sizeof(uint32_t), surf_bos[i], - 0, I915_GEM_DOMAIN_INSTRUCTION, 0); + binding_table[i] = i * SURFACE_STATE_PADDED_SIZE; drm_intel_bo_unmap(bind_bo); - return bind_bo; } static drm_intel_bo *i965_create_sampler_state(ScrnInfoPtr scrn) @@ -499,6 +617,26 @@ static drm_intel_bo *i965_create_sampler_state(ScrnInfoPtr scrn) return sampler_bo; } +static drm_intel_bo *gen7_create_sampler_state(ScrnInfoPtr scrn) +{ + intel_screen_private *intel = intel_get_screen_private(scrn); + drm_intel_bo *sampler_bo; + struct gen7_sampler_state *sampler_state; + + if (intel_alloc_and_map(intel, "textured video sampler state", 4096, + &sampler_bo, &sampler_state) != 0) + return NULL; + + sampler_state->ss0.min_filter = BRW_MAPFILTER_LINEAR; + sampler_state->ss0.mag_filter = BRW_MAPFILTER_LINEAR; + sampler_state->ss3.r_wrap_mode = BRW_TEXCOORDMODE_CLAMP; + sampler_state->ss3.s_wrap_mode = BRW_TEXCOORDMODE_CLAMP; + sampler_state->ss3.t_wrap_mode = BRW_TEXCOORDMODE_CLAMP; + + drm_intel_bo_unmap(sampler_bo); + return sampler_bo; +} + static drm_intel_bo *i965_create_vs_state(ScrnInfoPtr scrn) { intel_screen_private *intel = intel_get_screen_private(scrn); @@ -510,7 +648,7 @@ static drm_intel_bo *i965_create_vs_state(ScrnInfoPtr scrn) return NULL; /* Set up the vertex shader to be disabled (passthrough) */ - if (IS_IGDNG(intel)) + if (IS_GEN5(intel)) vs_state->thread4.nr_urb_entries = URB_VS_ENTRIES >> 2; else vs_state->thread4.nr_urb_entries = URB_VS_ENTRIES; @@ -545,7 +683,7 @@ static drm_intel_bo *i965_create_sf_state(ScrnInfoPtr scrn) drm_intel_bo *sf_bo, *kernel_bo; struct brw_sf_unit_state *sf_state; - if (IS_IGDNG(intel)) + if (IS_GEN5(intel)) kernel_bo = i965_create_program(scrn, &sf_kernel_static_gen5[0][0], sizeof(sf_kernel_static_gen5)); @@ -610,7 +748,7 @@ static drm_intel_bo *i965_create_wm_state(ScrnInfoPtr scrn, struct brw_wm_unit_state *wm_state; if (is_packed) { - if (IS_IGDNG(intel)) + if (IS_GEN5(intel)) kernel_bo = i965_create_program(scrn, &ps_kernel_packed_static_gen5[0] @@ -624,7 +762,7 @@ static drm_intel_bo *i965_create_wm_state(ScrnInfoPtr scrn, sizeof (ps_kernel_packed_static)); } else { - if (IS_IGDNG(intel)) + if (IS_GEN5(intel)) kernel_bo = i965_create_program(scrn, &ps_kernel_planar_static_gen5[0] @@ -662,7 +800,7 @@ static drm_intel_bo *i965_create_wm_state(ScrnInfoPtr scrn, /* binding table entry count is only used for prefetching, and it has to * be set 0 for IGDNG */ - if (IS_IGDNG(intel)) + if (IS_GEN5(intel)) wm_state->thread1.binding_table_entry_count = 0; /* Though we never use the scratch space in our WM kernel, it has to be @@ -680,7 +818,7 @@ static drm_intel_bo *i965_create_wm_state(ScrnInfoPtr scrn, intel_emit_reloc(wm_bo, offsetof(struct brw_wm_unit_state, wm4), sampler_bo, 0, I915_GEM_DOMAIN_INSTRUCTION, 0) >> 5; - if (IS_IGDNG(intel)) + if (IS_GEN5(intel)) wm_state->wm4.sampler_count = 0; else wm_state->wm4.sampler_count = 1; /* 1-4 samplers used */ @@ -755,7 +893,7 @@ static drm_intel_bo *i965_create_cc_state(ScrnInfoPtr scrn) } static void -i965_emit_video_setup(ScrnInfoPtr scrn, drm_intel_bo * bind_bo, int n_src_surf) +i965_emit_video_setup(ScrnInfoPtr scrn, drm_intel_bo * surface_state_binding_table_bo, int n_src_surf, PixmapPtr pixmap) { intel_screen_private *intel = intel_get_screen_private(scrn); int urb_vs_start, urb_vs_size; @@ -786,7 +924,7 @@ i965_emit_video_setup(ScrnInfoPtr scrn, drm_intel_bo * bind_bo, int n_src_surf) /* brw_debug (scrn, "before base address modify"); */ /* Match Mesa driver setup */ - if (IS_G4X(intel) || IS_IGDNG(intel)) + if (INTEL_INFO(intel)->gen >= 45) OUT_BATCH(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D); else OUT_BATCH(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D); @@ -799,27 +937,27 @@ i965_emit_video_setup(ScrnInfoPtr scrn, drm_intel_bo * bind_bo, int n_src_surf) /* Zero out the two base address registers so all offsets are * absolute */ - if (IS_IGDNG(intel)) { + if (IS_GEN5(intel)) { OUT_BATCH(BRW_STATE_BASE_ADDRESS | 6); OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Generate state base address */ - OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Surface state base address */ + OUT_RELOC(surface_state_binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */ OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* media base addr, don't care */ OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Instruction base address */ /* general state max addr, disabled */ - OUT_BATCH(0x10000000 | BASE_ADDRESS_MODIFY); + OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* media object state max addr, disabled */ - OUT_BATCH(0x10000000 | BASE_ADDRESS_MODIFY); + OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Instruction max addr, disabled */ - OUT_BATCH(0x10000000 | BASE_ADDRESS_MODIFY); + OUT_BATCH(0 | BASE_ADDRESS_MODIFY); } else { OUT_BATCH(BRW_STATE_BASE_ADDRESS | 4); OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Generate state base address */ - OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Surface state base address */ + OUT_RELOC(surface_state_binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */ OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* media base addr, don't care */ /* general state max addr, disabled */ - OUT_BATCH(0x10000000 | BASE_ADDRESS_MODIFY); + OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* media object state max addr, disabled */ - OUT_BATCH(0x10000000 | BASE_ADDRESS_MODIFY); + OUT_BATCH(0 | BASE_ADDRESS_MODIFY); } /* Set system instruction pointer */ @@ -830,7 +968,7 @@ i965_emit_video_setup(ScrnInfoPtr scrn, drm_intel_bo * bind_bo, int n_src_surf) /* brw_debug (scrn, "after base address modify"); */ - if (IS_IGDNG(intel)) + if (IS_GEN5(intel)) pipe_ctl = BRW_PIPE_CONTROL_NOWRITE; else pipe_ctl = BRW_PIPE_CONTROL_NOWRITE | BRW_PIPE_CONTROL_IS_FLUSH; @@ -848,7 +986,7 @@ i965_emit_video_setup(ScrnInfoPtr scrn, drm_intel_bo * bind_bo, int n_src_surf) OUT_BATCH(0); /* clip */ OUT_BATCH(0); /* sf */ /* Only the PS uses the binding table */ - OUT_RELOC(bind_bo, I915_GEM_DOMAIN_SAMPLER, 0, 0); + OUT_BATCH((n_src_surf + 1) * SURFACE_STATE_PADDED_SIZE); /* Blend constant color (magenta is fun) */ OUT_BATCH(BRW_3DSTATE_CONSTANT_COLOR | 3); @@ -862,7 +1000,7 @@ i965_emit_video_setup(ScrnInfoPtr scrn, drm_intel_bo * bind_bo, int n_src_surf) */ OUT_BATCH(BRW_3DSTATE_DRAWING_RECTANGLE | 2); /* XXX 3 for BLC or CTG */ OUT_BATCH(0x00000000); /* ymin, xmin */ - OUT_BATCH((scrn->virtualX - 1) | (scrn->virtualY - 1) << 16); /* ymax, xmax */ + OUT_BATCH((pixmap->drawable.width - 1) | (pixmap->drawable.height - 1) << 16); /* ymax, xmax */ OUT_BATCH(0x00000000); /* yorigin, xorigin */ /* skip the depth buffer */ @@ -903,7 +1041,7 @@ i965_emit_video_setup(ScrnInfoPtr scrn, drm_intel_bo * bind_bo, int n_src_surf) /* Set up our vertex elements, sourced from the single vertex buffer. */ - if (IS_IGDNG(intel)) { + if (IS_GEN5(intel)) { OUT_BATCH(BRW_3DSTATE_VERTEX_ELEMENTS | 3); /* offset 0: X,Y -> {X, Y, 1.0, 1.0} */ OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) | @@ -973,14 +1111,14 @@ I965DisplayVideoTextured(ScrnInfoPtr scrn, BoxPtr pbox; int nbox, dxo, dyo, pix_xoff, pix_yoff; float src_scale_x, src_scale_y; - int src_surf, i; + int src_surf; int n_src_surf; uint32_t src_surf_format; uint32_t src_surf_base[6]; int src_width[6]; int src_height[6]; int src_pitch[6]; - drm_intel_bo *bind_bo, *surf_bos[7]; + drm_intel_bo *surface_state_binding_table_bo; #if 0 ErrorF("BroadwaterDisplayVideoTextured: %dx%d (pitch %d)\n", width, @@ -1038,35 +1176,30 @@ I965DisplayVideoTextured(ScrnInfoPtr scrn, * I830PutImage. */ - /* Upload kernels */ - surf_bos[0] = i965_create_dst_surface_state(scrn, pixmap); - if (!surf_bos[0]) + surface_state_binding_table_bo = + drm_intel_bo_alloc(intel->bufmgr, + "surface state & binding table", + (n_src_surf + 1) * (SURFACE_STATE_PADDED_SIZE + sizeof(uint32_t)), + 4096); + + if (!surface_state_binding_table_bo) return; + + i965_create_dst_surface_state(scrn, pixmap, surface_state_binding_table_bo, 0); for (src_surf = 0; src_surf < n_src_surf; src_surf++) { - drm_intel_bo *surf_bo = - i965_create_src_surface_state(scrn, - adaptor_priv->buf, - src_surf_base[src_surf], - src_width[src_surf], - src_height[src_surf], - src_pitch[src_surf], - src_surf_format); - if (!surf_bo) { - int q; - for (q = 0; q < src_surf + 1; q++) - drm_intel_bo_unreference(surf_bos[q]); - return; - } - surf_bos[src_surf + 1] = surf_bo; + i965_create_src_surface_state(scrn, + adaptor_priv->buf, + src_surf_base[src_surf], + src_width[src_surf], + src_height[src_surf], + src_pitch[src_surf], + src_surf_format, + surface_state_binding_table_bo, + (src_surf + 1) * SURFACE_STATE_PADDED_SIZE); } - bind_bo = i965_create_binding_table(scrn, surf_bos, n_src_surf + 1); - for (i = 0; i < n_src_surf + 1; i++) { - drm_intel_bo_unreference(surf_bos[i]); - surf_bos[i] = NULL; - } - if (!bind_bo) - return; + + i965_create_binding_table(scrn, surface_state_binding_table_bo, n_src_surf + 1); if (intel->video.gen4_sampler_bo == NULL) intel->video.gen4_sampler_bo = i965_create_sampler_state(scrn); @@ -1075,7 +1208,7 @@ I965DisplayVideoTextured(ScrnInfoPtr scrn, i965_create_program(scrn, &sip_kernel_static[0][0], sizeof(sip_kernel_static)); if (!intel->video.gen4_sip_kernel_bo) { - drm_intel_bo_unreference(bind_bo); + drm_intel_bo_unreference(surface_state_binding_table_bo); return; } } @@ -1083,14 +1216,14 @@ I965DisplayVideoTextured(ScrnInfoPtr scrn, if (intel->video.gen4_vs_bo == NULL) { intel->video.gen4_vs_bo = i965_create_vs_state(scrn); if (!intel->video.gen4_vs_bo) { - drm_intel_bo_unreference(bind_bo); + drm_intel_bo_unreference(surface_state_binding_table_bo); return; } } if (intel->video.gen4_sf_bo == NULL) { intel->video.gen4_sf_bo = i965_create_sf_state(scrn); if (!intel->video.gen4_sf_bo) { - drm_intel_bo_unreference(bind_bo); + drm_intel_bo_unreference(surface_state_binding_table_bo); return; } } @@ -1099,7 +1232,7 @@ I965DisplayVideoTextured(ScrnInfoPtr scrn, i965_create_wm_state(scrn, intel->video.gen4_sampler_bo, TRUE); if (!intel->video.gen4_wm_packed_bo) { - drm_intel_bo_unreference(bind_bo); + drm_intel_bo_unreference(surface_state_binding_table_bo); return; } } @@ -1109,7 +1242,7 @@ I965DisplayVideoTextured(ScrnInfoPtr scrn, i965_create_wm_state(scrn, intel->video.gen4_sampler_bo, FALSE); if (!intel->video.gen4_wm_planar_bo) { - drm_intel_bo_unreference(bind_bo); + drm_intel_bo_unreference(surface_state_binding_table_bo); return; } } @@ -1117,7 +1250,7 @@ I965DisplayVideoTextured(ScrnInfoPtr scrn, if (intel->video.gen4_cc_bo == NULL) { intel->video.gen4_cc_bo = i965_create_cc_state(scrn); if (!intel->video.gen4_cc_bo) { - drm_intel_bo_unreference(bind_bo); + drm_intel_bo_unreference(surface_state_binding_table_bo); return; } } @@ -1153,7 +1286,7 @@ I965DisplayVideoTextured(ScrnInfoPtr scrn, drm_intel_bo *bo_table[] = { NULL, /* vb_bo */ intel->batch_bo, - bind_bo, + surface_state_binding_table_bo, intel->video.gen4_sampler_bo, intel->video.gen4_sip_kernel_bo, intel->video.gen4_vs_bo, @@ -1188,7 +1321,7 @@ I965DisplayVideoTextured(ScrnInfoPtr scrn, drm_intel_bo_unmap(vb_bo); - if (!IS_IGDNG(intel)) + if (IS_GEN4(intel)) i965_pre_draw_debug(scrn); /* If this command won't fit in the current batch, flush. @@ -1197,12 +1330,12 @@ I965DisplayVideoTextured(ScrnInfoPtr scrn, if (drm_intel_bufmgr_check_aperture_space(bo_table, ARRAY_SIZE(bo_table)) < 0) { - intel_batch_submit(scrn, FALSE); + intel_batch_submit(scrn); } - intel_batch_start_atomic(scrn, 100); + intel_batch_start_atomic(scrn, 150); - i965_emit_video_setup(scrn, bind_bo, n_src_surf); + i965_emit_video_setup(scrn, surface_state_binding_table_bo, n_src_surf, pixmap); /* Set up the pointer to our vertex buffer */ OUT_BATCH(BRW_3DSTATE_VERTEX_BUFFERS | 3); @@ -1210,7 +1343,7 @@ I965DisplayVideoTextured(ScrnInfoPtr scrn, OUT_BATCH((0 << VB0_BUFFER_INDEX_SHIFT) | VB0_VERTEXDATA | ((4 * 4) << VB0_BUFFER_PITCH_SHIFT)); OUT_RELOC(vb_bo, I915_GEM_DOMAIN_VERTEX, 0, 0); - if (IS_IGDNG(intel)) + if (IS_GEN5(intel)) OUT_RELOC(vb_bo, I915_GEM_DOMAIN_VERTEX, 0, i * 4); else @@ -1230,19 +1363,15 @@ I965DisplayVideoTextured(ScrnInfoPtr scrn, drm_intel_bo_unreference(vb_bo); - if (!IS_IGDNG(intel)) + if (IS_GEN4(intel)) i965_post_draw_debug(scrn); } /* release reference once we're finished */ - drm_intel_bo_unreference(bind_bo); - -#if WATCH_STATS - /* i830_dump_error_state(scrn); */ -#endif + drm_intel_bo_unreference(surface_state_binding_table_bo); - i830_debug_flush(scrn); + intel_debug_flush(scrn); } void i965_free_video(ScrnInfoPtr scrn) @@ -1265,4 +1394,592 @@ void i965_free_video(ScrnInfoPtr scrn) intel->video.gen4_sampler_bo = NULL; drm_intel_bo_unreference(intel->video.gen4_sip_kernel_bo); intel->video.gen4_sip_kernel_bo = NULL; + drm_intel_bo_unreference(intel->video.wm_prog_packed_bo); + intel->video.wm_prog_packed_bo = NULL; + drm_intel_bo_unreference(intel->video.wm_prog_planar_bo); + intel->video.wm_prog_planar_bo = NULL; + drm_intel_bo_unreference(intel->video.gen6_blend_bo); + intel->video.gen6_blend_bo = NULL; + drm_intel_bo_unreference(intel->video.gen6_depth_stencil_bo); + intel->video.gen6_depth_stencil_bo = NULL; +} + +/* for GEN6+ */ +static drm_intel_bo * +gen6_create_cc_state(ScrnInfoPtr scrn) +{ + intel_screen_private *intel = intel_get_screen_private(scrn); + struct gen6_color_calc_state *cc_state; + drm_intel_bo *cc_bo; + + if (intel_alloc_and_map( + intel, + "textured video cc state", + sizeof(*cc_state), + &cc_bo, + &cc_state) != 0) + return NULL; + + cc_state->constant_r = 1.0; + cc_state->constant_g = 0.0; + cc_state->constant_b = 1.0; + cc_state->constant_a = 1.0; + + drm_intel_bo_unmap(cc_bo); + return cc_bo; +} + +static drm_intel_bo * +gen6_create_blend_state(ScrnInfoPtr scrn) +{ + intel_screen_private *intel = intel_get_screen_private(scrn); + struct gen6_blend_state *blend_state; + drm_intel_bo *blend_bo; + + if (intel_alloc_and_map( + intel, + "textured video blend state", + sizeof(*blend_state), + &blend_bo, + &blend_state) != 0) + return NULL; + + blend_state->blend1.logic_op_enable = 1; + blend_state->blend1.logic_op_func = 0xc; + blend_state->blend1.pre_blend_clamp_enable = 1; + + drm_intel_bo_unmap(blend_bo); + return blend_bo; +} + +static drm_intel_bo * +gen6_create_depth_stencil_state(ScrnInfoPtr scrn) +{ + intel_screen_private *intel = intel_get_screen_private(scrn); + struct gen6_depth_stencil_state *depth_stencil_state; + drm_intel_bo *depth_stencil_bo; + + if (intel_alloc_and_map( + intel, + "textured video blend state", + sizeof(*depth_stencil_state), + &depth_stencil_bo, + &depth_stencil_state) != 0) + return NULL; + + drm_intel_bo_unmap(depth_stencil_bo); + return depth_stencil_bo; +} + +static Bool +gen6_create_vidoe_objects(ScrnInfoPtr scrn) +{ + intel_screen_private *intel = intel_get_screen_private(scrn); + drm_intel_bo *(*create_sampler_state)(ScrnInfoPtr); + const uint32_t *packed_ps_kernel, *planar_ps_kernel; + unsigned int packed_ps_size, planar_ps_size; + + if (INTEL_INFO(intel)->gen >= 70) { + create_sampler_state = gen7_create_sampler_state; + packed_ps_kernel = &ps_kernel_packed_static_gen7[0][0]; + packed_ps_size = sizeof(ps_kernel_packed_static_gen7); + planar_ps_kernel = &ps_kernel_planar_static_gen7[0][0]; + planar_ps_size = sizeof(ps_kernel_planar_static_gen7); + } else { + create_sampler_state = i965_create_sampler_state; + packed_ps_kernel = &ps_kernel_packed_static_gen6[0][0]; + packed_ps_size = sizeof(ps_kernel_packed_static_gen6); + planar_ps_kernel = &ps_kernel_planar_static_gen6[0][0]; + planar_ps_size = sizeof(ps_kernel_planar_static_gen6); + } + + if (intel->video.gen4_sampler_bo == NULL) + intel->video.gen4_sampler_bo = create_sampler_state(scrn); + + if (intel->video.wm_prog_packed_bo == NULL) + intel->video.wm_prog_packed_bo = + i965_create_program(scrn, + packed_ps_kernel, + packed_ps_size); + + if (intel->video.wm_prog_planar_bo == NULL) + intel->video.wm_prog_planar_bo = + i965_create_program(scrn, + planar_ps_kernel, + planar_ps_size); + + if (intel->video.gen4_cc_vp_bo == NULL) + intel->video.gen4_cc_vp_bo = i965_create_cc_vp_state(scrn); + + if (intel->video.gen4_cc_bo == NULL) + intel->video.gen4_cc_bo = gen6_create_cc_state(scrn); + + if (intel->video.gen6_blend_bo == NULL) + intel->video.gen6_blend_bo = gen6_create_blend_state(scrn); + + if (intel->video.gen6_depth_stencil_bo == NULL) + intel->video.gen6_depth_stencil_bo = gen6_create_depth_stencil_state(scrn); + + + return (intel->video.gen4_sampler_bo != NULL && + intel->video.wm_prog_packed_bo != NULL && + intel->video.wm_prog_planar_bo != NULL && + intel->video.gen4_cc_vp_bo != NULL && + intel->video.gen4_cc_bo != NULL && + intel->video.gen6_blend_bo != NULL && + intel->video.gen6_depth_stencil_bo != NULL); +} + +static void +gen6_upload_state_base_address(ScrnInfoPtr scrn, drm_intel_bo *surface_state_binding_table_bo) +{ + intel_screen_private *intel = intel_get_screen_private(scrn); + + OUT_BATCH(BRW_STATE_BASE_ADDRESS | (10 - 2)); + OUT_BATCH(BASE_ADDRESS_MODIFY); /* General state base address */ + OUT_RELOC(surface_state_binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */ + OUT_BATCH(BASE_ADDRESS_MODIFY); /* Dynamic state base address */ + OUT_BATCH(BASE_ADDRESS_MODIFY); /* Indirect object base address */ + OUT_BATCH(BASE_ADDRESS_MODIFY); /* Instruction base address */ + OUT_BATCH(BASE_ADDRESS_MODIFY); /* General state upper bound */ + OUT_BATCH(BASE_ADDRESS_MODIFY); /* Dynamic state upper bound */ + OUT_BATCH(BASE_ADDRESS_MODIFY); /* Indirect object upper bound */ + OUT_BATCH(BASE_ADDRESS_MODIFY); /* Instruction access upper bound */ +} + +static void +gen6_upload_drawing_rectangle(ScrnInfoPtr scrn, PixmapPtr pixmap) +{ + intel_screen_private *intel = intel_get_screen_private(scrn); + + OUT_BATCH(BRW_3DSTATE_DRAWING_RECTANGLE | 2); + OUT_BATCH(0x00000000); /* ymin, xmin */ + OUT_BATCH((pixmap->drawable.width - 1) | (pixmap->drawable.height - 1) << 16); /* ymax, xmax */ + OUT_BATCH(0x00000000); /* yorigin, xorigin */ +} + +static void +gen6_upload_wm_state(ScrnInfoPtr scrn, Bool is_packed) +{ + intel_screen_private *intel = intel_get_screen_private(scrn); + + /* disable WM constant buffer */ + OUT_BATCH(GEN6_3DSTATE_CONSTANT_PS | (5 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + + OUT_BATCH(GEN6_3DSTATE_WM | (9 - 2)); + if (is_packed) { + OUT_RELOC(intel->video.wm_prog_packed_bo, + I915_GEM_DOMAIN_INSTRUCTION, 0, + 0); + OUT_BATCH((1 << GEN6_3DSTATE_WM_SAMPLER_COUNT_SHITF) | + (2 << GEN6_3DSTATE_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT)); + } else { + OUT_RELOC(intel->video.wm_prog_planar_bo, + I915_GEM_DOMAIN_INSTRUCTION, 0, + 0); + OUT_BATCH((1 << GEN6_3DSTATE_WM_SAMPLER_COUNT_SHITF) | + (7 << GEN6_3DSTATE_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT)); + } + OUT_BATCH(0); + OUT_BATCH((6 << GEN6_3DSTATE_WM_DISPATCH_START_GRF_0_SHIFT)); /* DW4 */ + OUT_BATCH(((40 - 1) << GEN6_3DSTATE_WM_MAX_THREADS_SHIFT) | + GEN6_3DSTATE_WM_DISPATCH_ENABLE | + GEN6_3DSTATE_WM_16_DISPATCH_ENABLE); + OUT_BATCH((1 << GEN6_3DSTATE_WM_NUM_SF_OUTPUTS_SHIFT) | + GEN6_3DSTATE_WM_PERSPECTIVE_PIXEL_BARYCENTRIC); + OUT_BATCH(0); + OUT_BATCH(0); +} + +static void +gen6_upload_vertex_element_state(ScrnInfoPtr scrn) +{ + intel_screen_private *intel = intel_get_screen_private(scrn); + + /* Set up our vertex elements, sourced from the single vertex buffer. */ + OUT_BATCH(BRW_3DSTATE_VERTEX_ELEMENTS | (5 - 2)); + /* offset 0: X,Y -> {X, Y, 1.0, 1.0} */ + OUT_BATCH((0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) | + GEN6_VE0_VALID | + (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) | + (0 << VE0_OFFSET_SHIFT)); + OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) | + (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) | + (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) | + (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT)); + /* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */ + OUT_BATCH((0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) | + GEN6_VE0_VALID | + (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) | + (8 << VE0_OFFSET_SHIFT)); + OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) | + (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) | + (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) | + (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT)); +} + +static void +gen6_upload_vertex_buffer(ScrnInfoPtr scrn, drm_intel_bo *vertex_bo, uint32_t end_address_offset) +{ + intel_screen_private *intel = intel_get_screen_private(scrn); + + /* Set up the pointer to our vertex buffer */ + OUT_BATCH(BRW_3DSTATE_VERTEX_BUFFERS | (5 - 2)); + /* four 32-bit floats per vertex */ + OUT_BATCH((0 << GEN6_VB0_BUFFER_INDEX_SHIFT) | + GEN6_VB0_VERTEXDATA | + ((4 * 4) << VB0_BUFFER_PITCH_SHIFT)); + OUT_RELOC(vertex_bo, I915_GEM_DOMAIN_VERTEX, 0, 0); + OUT_RELOC(vertex_bo, I915_GEM_DOMAIN_VERTEX, 0, end_address_offset); + OUT_BATCH(0); /* reserved */ +} + +static void +gen6_upload_primitive(ScrnInfoPtr scrn) +{ + intel_screen_private *intel = intel_get_screen_private(scrn); + + OUT_BATCH(BRW_3DPRIMITIVE | + BRW_3DPRIMITIVE_VERTEX_SEQUENTIAL | + (_3DPRIM_RECTLIST << BRW_3DPRIMITIVE_TOPOLOGY_SHIFT) | + (0 << 9) | /* Internal Vertex Count */ + (6 - 2)); + OUT_BATCH(3); /* vertex count per instance */ + OUT_BATCH(0); /* start vertex offset */ + OUT_BATCH(1); /* single instance */ + OUT_BATCH(0); /* start instance location */ + OUT_BATCH(0); /* index buffer offset, ignored */ +} + +static void +gen6_emit_video_setup(ScrnInfoPtr scrn, + drm_intel_bo *surface_state_binding_table_bo, int n_src_surf, + PixmapPtr pixmap, + drm_intel_bo *vertex_bo, uint32_t end_address_offset) +{ + intel_screen_private *intel = intel_get_screen_private(scrn); + + assert(n_src_surf == 1 || n_src_surf == 6); + IntelEmitInvarientState(scrn); + intel->last_3d = LAST_3D_VIDEO; + + gen6_upload_invariant_states(intel); + gen6_upload_state_base_address(scrn, surface_state_binding_table_bo); + gen6_upload_viewport_state_pointers(intel, intel->video.gen4_cc_vp_bo); + gen6_upload_urb(intel); + gen6_upload_cc_state_pointers(intel, intel->video.gen6_blend_bo, intel->video.gen4_cc_bo, intel->video.gen6_depth_stencil_bo, 0); + gen6_upload_sampler_state_pointers(intel, intel->video.gen4_sampler_bo); + gen6_upload_vs_state(intel); + gen6_upload_gs_state(intel); + gen6_upload_clip_state(intel); + gen6_upload_sf_state(intel, 1, 0); + gen6_upload_wm_state(scrn, n_src_surf == 1 ? TRUE : FALSE); + gen6_upload_binding_table(intel, (n_src_surf + 1) * SURFACE_STATE_PADDED_SIZE); + gen6_upload_depth_buffer_state(intel); + gen6_upload_drawing_rectangle(scrn, pixmap); + gen6_upload_vertex_element_state(scrn); + gen6_upload_vertex_buffer(scrn, vertex_bo, end_address_offset); + gen6_upload_primitive(scrn); +} + +static void +gen7_upload_wm_state(ScrnInfoPtr scrn, Bool is_packed) +{ + intel_screen_private *intel = intel_get_screen_private(scrn); + + /* disable WM constant buffer */ + OUT_BATCH(GEN6_3DSTATE_CONSTANT_PS | (7 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + + OUT_BATCH(GEN6_3DSTATE_WM | (3 - 2)); + OUT_BATCH(GEN7_WM_DISPATCH_ENABLE | + GEN7_WM_PERSPECTIVE_PIXEL_BARYCENTRIC); + OUT_BATCH(0); + + OUT_BATCH(GEN7_3DSTATE_PS | (8 - 2)); + + if (is_packed) { + OUT_RELOC(intel->video.wm_prog_packed_bo, + I915_GEM_DOMAIN_INSTRUCTION, 0, + 0); + OUT_BATCH((1 << GEN7_PS_SAMPLER_COUNT_SHIFT) | + (2 << GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT)); + } else { + OUT_RELOC(intel->video.wm_prog_planar_bo, + I915_GEM_DOMAIN_INSTRUCTION, 0, + 0); + OUT_BATCH((1 << GEN7_PS_SAMPLER_COUNT_SHIFT) | + (7 << GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT)); + } + + OUT_BATCH(0); /* scratch space base offset */ + OUT_BATCH( + ((86 - 1) << GEN7_PS_MAX_THREADS_SHIFT) | + GEN7_PS_ATTRIBUTE_ENABLE | + GEN7_PS_16_DISPATCH_ENABLE); + OUT_BATCH( + (6 << GEN7_PS_DISPATCH_START_GRF_SHIFT_0)); + OUT_BATCH(0); /* kernel 1 pointer */ + OUT_BATCH(0); /* kernel 2 pointer */ +} + +static void +gen7_upload_vertex_buffer(ScrnInfoPtr scrn, drm_intel_bo *vertex_bo, uint32_t end_address_offset) +{ + intel_screen_private *intel = intel_get_screen_private(scrn); + + /* Set up the pointer to our vertex buffer */ + OUT_BATCH(BRW_3DSTATE_VERTEX_BUFFERS | (5 - 2)); + /* four 32-bit floats per vertex */ + OUT_BATCH((0 << GEN6_VB0_BUFFER_INDEX_SHIFT) | + GEN6_VB0_VERTEXDATA | + GEN7_VB0_ADDRESS_MODIFYENABLE | + ((4 * 4) << VB0_BUFFER_PITCH_SHIFT)); + OUT_RELOC(vertex_bo, I915_GEM_DOMAIN_VERTEX, 0, 0); + OUT_RELOC(vertex_bo, I915_GEM_DOMAIN_VERTEX, 0, end_address_offset); + OUT_BATCH(0); /* reserved */ +} + +static void +gen7_upload_primitive(ScrnInfoPtr scrn) +{ + intel_screen_private *intel = intel_get_screen_private(scrn); + + OUT_BATCH(BRW_3DPRIMITIVE | (7 - 2)); + OUT_BATCH(_3DPRIM_RECTLIST | + GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL); + OUT_BATCH(3); /* vertex count per instance */ + OUT_BATCH(0); /* start vertex offset */ + OUT_BATCH(1); /* single instance */ + OUT_BATCH(0); /* start instance location */ + OUT_BATCH(0); +} + +static void +gen7_emit_video_setup(ScrnInfoPtr scrn, + drm_intel_bo *surface_state_binding_table_bo, int n_src_surf, + PixmapPtr pixmap, + drm_intel_bo *vertex_bo, uint32_t end_address_offset) +{ + intel_screen_private *intel = intel_get_screen_private(scrn); + + assert(n_src_surf == 1 || n_src_surf == 6); + IntelEmitInvarientState(scrn); + intel->last_3d = LAST_3D_VIDEO; + + gen6_upload_invariant_states(intel); + gen6_upload_state_base_address(scrn, surface_state_binding_table_bo); + gen7_upload_viewport_state_pointers(intel, intel->video.gen4_cc_vp_bo); + gen7_upload_urb(intel); + gen7_upload_cc_state_pointers(intel, intel->video.gen6_blend_bo, intel->video.gen4_cc_bo, intel->video.gen6_depth_stencil_bo, 0); + gen7_upload_sampler_state_pointers(intel, intel->video.gen4_sampler_bo); + gen7_upload_bypass_states(intel); + gen6_upload_vs_state(intel); + gen6_upload_clip_state(intel); + gen7_upload_sf_state(intel, 1, 0); + gen7_upload_wm_state(scrn, n_src_surf == 1 ? TRUE : FALSE); + gen7_upload_binding_table(intel, (n_src_surf + 1) * SURFACE_STATE_PADDED_SIZE); + gen7_upload_depth_buffer_state(intel); + gen6_upload_drawing_rectangle(scrn, pixmap); + gen6_upload_vertex_element_state(scrn); + gen7_upload_vertex_buffer(scrn, vertex_bo, end_address_offset); + gen7_upload_primitive(scrn); +} + +void Gen6DisplayVideoTextured(ScrnInfoPtr scrn, + intel_adaptor_private *adaptor_priv, int id, + RegionPtr dstRegion, + short width, short height, + int video_pitch, int video_pitch2, + short src_w, short src_h, + short drw_w, short drw_h, PixmapPtr pixmap) +{ + intel_screen_private *intel = intel_get_screen_private(scrn); + BoxPtr pbox; + int nbox, dxo, dyo, pix_xoff, pix_yoff; + float src_scale_x, src_scale_y; + int src_surf; + int n_src_surf; + uint32_t src_surf_format; + uint32_t src_surf_base[6]; + int src_width[6]; + int src_height[6]; + int src_pitch[6]; + drm_intel_bo *surface_state_binding_table_bo; + void (*create_dst_surface_state)(ScrnInfoPtr, + PixmapPtr, + drm_intel_bo *, + uint32_t); + void (*create_src_surface_state)(ScrnInfoPtr, + drm_intel_bo *, + uint32_t, int, + int, int, uint32_t, + drm_intel_bo *, uint32_t); + void (*emit_video_setup)(ScrnInfoPtr, + drm_intel_bo *, int, + PixmapPtr, + drm_intel_bo *, uint32_t); + + if (INTEL_INFO(intel)->gen >= 70) { + create_dst_surface_state = gen7_create_dst_surface_state; + create_src_surface_state = gen7_create_src_surface_state; + emit_video_setup = gen7_emit_video_setup; + } else { + create_dst_surface_state = i965_create_dst_surface_state; + create_src_surface_state = i965_create_src_surface_state; + emit_video_setup = gen6_emit_video_setup; + } + + src_surf_base[0] = adaptor_priv->YBufOffset; + src_surf_base[1] = adaptor_priv->YBufOffset; + src_surf_base[2] = adaptor_priv->VBufOffset; + src_surf_base[3] = adaptor_priv->VBufOffset; + src_surf_base[4] = adaptor_priv->UBufOffset; + src_surf_base[5] = adaptor_priv->UBufOffset; + + if (is_planar_fourcc(id)) { + src_surf_format = BRW_SURFACEFORMAT_R8_UNORM; + src_width[1] = src_width[0] = width; + src_height[1] = src_height[0] = height; + src_pitch[1] = src_pitch[0] = video_pitch2; + src_width[4] = src_width[5] = src_width[2] = src_width[3] = + width / 2; + src_height[4] = src_height[5] = src_height[2] = src_height[3] = + height / 2; + src_pitch[4] = src_pitch[5] = src_pitch[2] = src_pitch[3] = + video_pitch; + n_src_surf = 6; + } else { + if (id == FOURCC_UYVY) + src_surf_format = BRW_SURFACEFORMAT_YCRCB_SWAPY; + else + src_surf_format = BRW_SURFACEFORMAT_YCRCB_NORMAL; + + src_width[0] = width; + src_height[0] = height; + src_pitch[0] = video_pitch; + n_src_surf = 1; + } + + surface_state_binding_table_bo = + drm_intel_bo_alloc(intel->bufmgr, + "surface state & binding table", + (n_src_surf + 1) * (SURFACE_STATE_PADDED_SIZE + sizeof(uint32_t)), + 4096); + + if (!surface_state_binding_table_bo) + return; + + create_dst_surface_state(scrn, pixmap, surface_state_binding_table_bo, 0); + + for (src_surf = 0; src_surf < n_src_surf; src_surf++) { + create_src_surface_state(scrn, + adaptor_priv->buf, + src_surf_base[src_surf], + src_width[src_surf], + src_height[src_surf], + src_pitch[src_surf], + src_surf_format, + surface_state_binding_table_bo, + (src_surf + 1) * SURFACE_STATE_PADDED_SIZE); + } + + i965_create_binding_table(scrn, surface_state_binding_table_bo, n_src_surf + 1); + + if (!gen6_create_vidoe_objects(scrn)) { + drm_intel_bo_unreference(surface_state_binding_table_bo); + return; + } + + /* Set up the offset for translating from the given region (in screen + * coordinates) to the backing pixmap. + */ +#ifdef COMPOSITE + pix_xoff = -pixmap->screen_x + pixmap->drawable.x; + pix_yoff = -pixmap->screen_y + pixmap->drawable.y; +#else + pix_xoff = 0; + pix_yoff = 0; +#endif + + dxo = dstRegion->extents.x1; + dyo = dstRegion->extents.y1; + + /* Use normalized texture coordinates */ + src_scale_x = ((float)src_w / width) / (float)drw_w; + src_scale_y = ((float)src_h / height) / (float)drw_h; + + pbox = REGION_RECTS(dstRegion); + nbox = REGION_NUM_RECTS(dstRegion); + while (nbox--) { + int box_x1 = pbox->x1; + int box_y1 = pbox->y1; + int box_x2 = pbox->x2; + int box_y2 = pbox->y2; + int i; + drm_intel_bo *vb_bo; + float *vb; + drm_intel_bo *bo_table[] = { + NULL, /* vb_bo */ + intel->batch_bo, + surface_state_binding_table_bo, + intel->video.gen4_sampler_bo, + intel->video.wm_prog_packed_bo, + intel->video.wm_prog_planar_bo, + intel->video.gen4_cc_vp_bo, + intel->video.gen4_cc_bo, + intel->video.gen6_blend_bo, + intel->video.gen6_depth_stencil_bo, + }; + + pbox++; + + if (intel_alloc_and_map(intel, "textured video vb", 4096, + &vb_bo, &vb) != 0) + break; + bo_table[0] = vb_bo; + + i = 0; + vb[i++] = (box_x2 - dxo) * src_scale_x; + vb[i++] = (box_y2 - dyo) * src_scale_y; + vb[i++] = (float)box_x2 + pix_xoff; + vb[i++] = (float)box_y2 + pix_yoff; + + vb[i++] = (box_x1 - dxo) * src_scale_x; + vb[i++] = (box_y2 - dyo) * src_scale_y; + vb[i++] = (float)box_x1 + pix_xoff; + vb[i++] = (float)box_y2 + pix_yoff; + + vb[i++] = (box_x1 - dxo) * src_scale_x; + vb[i++] = (box_y1 - dyo) * src_scale_y; + vb[i++] = (float)box_x1 + pix_xoff; + vb[i++] = (float)box_y1 + pix_yoff; + + drm_intel_bo_unmap(vb_bo); + + /* If this command won't fit in the current batch, flush. + * Assume that it does after being flushed. + */ + if (drm_intel_bufmgr_check_aperture_space(bo_table, ARRAY_SIZE(bo_table)) < 0) + intel_batch_submit(scrn); + + intel_batch_start_atomic(scrn, 200); + emit_video_setup(scrn, surface_state_binding_table_bo, n_src_surf, pixmap, vb_bo, i * 4); + intel_batch_end_atomic(scrn); + + drm_intel_bo_unreference(vb_bo); + } + + /* release reference once we're finished */ + drm_intel_bo_unreference(surface_state_binding_table_bo); + intel_debug_flush(scrn); } diff --git a/driver/xf86-video-intel/src/i830.h b/driver/xf86-video-intel/src/intel.h index d7a3aa9cd..3cb1a5d4b 100644 --- a/driver/xf86-video-intel/src/i830.h +++ b/driver/xf86-video-intel/src/intel.h @@ -51,7 +51,6 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "compiler.h" #include "xf86PciInfo.h" #include "xf86Pci.h" -#include "i810_reg.h" #include "xf86Cursor.h" #include "xf86xv.h" #include "vgaHW.h" @@ -67,17 +66,13 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "sarea.h" #define _XF86DRI_SERVER_ #include "dri.h" -#include "GL/glxint.h" +#include "dri2.h" #include "intel_bufmgr.h" #include "i915_drm.h" -#include "uxa.h" -Bool i830_uxa_init(ScreenPtr pScreen); -void i830_uxa_create_screen_resources(ScreenPtr pScreen); -void i830_uxa_block_handler(ScreenPtr pScreen); -Bool i830_get_aperture_space(ScrnInfoPtr scrn, drm_intel_bo ** bo_table, - int num_bos); +#include "intel_driver.h" +#include "uxa.h" /* XXX * The X server gained an *almost* identical implementation in 1.9. * @@ -136,6 +131,9 @@ list_is_empty(struct list *head) } #endif +/* XXX work around a broken define in list.h currently [ickle 20100713] */ +#undef container_of + #ifndef container_of #define container_of(ptr, type, member) \ (type *)((char *)(ptr) - (char *) &((type *)0)->member) @@ -164,6 +162,11 @@ list_is_empty(struct list *head) pos = list_entry(pos->member.next, type, member)) #endif +/* remain compatible to xorg-server 1.6 */ +#ifndef MONITOR_EDID_COMPLETE_RAWDATA +#define MONITOR_EDID_COMPLETE_RAWDATA EDID_COMPLETE_RAWDATA +#endif + struct intel_pixmap { dri_bo *bo; @@ -173,6 +176,8 @@ struct intel_pixmap { uint8_t tiling; int8_t busy :2; int8_t batch_write :1; + int8_t offscreen :1; + int8_t pinned :1; }; #if HAS_DEVPRIVATEKEYREC @@ -181,7 +186,7 @@ extern DevPrivateKeyRec uxa_pixmap_index; extern int uxa_pixmap_index; #endif -static inline struct intel_pixmap *i830_get_pixmap_intel(PixmapPtr pixmap) +static inline struct intel_pixmap *intel_get_pixmap_private(PixmapPtr pixmap) { #if HAS_DEVPRIVATEKEYREC return dixGetPrivate(&pixmap->devPrivates, &uxa_pixmap_index); @@ -197,23 +202,23 @@ static inline Bool intel_pixmap_is_busy(struct intel_pixmap *priv) return priv->busy; } -static inline void i830_set_pixmap_intel(PixmapPtr pixmap, struct intel_pixmap *intel) +static inline void intel_set_pixmap_private(PixmapPtr pixmap, struct intel_pixmap *intel) { dixSetPrivate(&pixmap->devPrivates, &uxa_pixmap_index, intel); } -static inline Bool i830_uxa_pixmap_is_dirty(PixmapPtr pixmap) +static inline Bool intel_pixmap_is_dirty(PixmapPtr pixmap) { - return !list_is_empty(&i830_get_pixmap_intel(pixmap)->flush); + return !list_is_empty(&intel_get_pixmap_private(pixmap)->flush); } -static inline Bool i830_pixmap_tiled(PixmapPtr pixmap) +static inline Bool intel_pixmap_tiled(PixmapPtr pixmap) { - return i830_get_pixmap_intel(pixmap)->tiling != I915_TILING_NONE; + return intel_get_pixmap_private(pixmap)->tiling != I915_TILING_NONE; } -dri_bo *i830_get_pixmap_bo(PixmapPtr pixmap); -void i830_set_pixmap_bo(PixmapPtr pixmap, dri_bo * bo); +dri_bo *intel_get_pixmap_bo(PixmapPtr pixmap); +void intel_set_pixmap_bo(PixmapPtr pixmap, dri_bo * bo); typedef struct _I830OutputRec I830OutputRec, *I830OutputPtr; @@ -242,17 +247,11 @@ typedef void (*I830WriteByteFunc) (struct intel_screen_private *intel, typedef uint8_t(*I830ReadByteFunc) (struct intel_screen_private *intel, IOADDRESS addr); -enum tile_format { - TILE_NONE, - TILE_XMAJOR, - TILE_YMAJOR -}; - #define PITCH_NONE 0 /** Record of a linear allocation in the aperture. */ -typedef struct _i830_memory i830_memory; -struct _i830_memory { +typedef struct _intel_memory intel_memory; +struct _intel_memory { /** Offset of the allocation in card VM */ unsigned long offset; /** End of the allocation in card VM */ @@ -285,8 +284,6 @@ struct _i830_memory { * This is either @offset or intel->stolen_size */ unsigned long agp_offset; - - enum tile_format tiling; /** * Index of the fence register representing the tiled surface, when * bound. @@ -301,8 +298,8 @@ struct _i830_memory { /** @{ * Memory allocator linked list pointers */ - i830_memory *next; - i830_memory *prev; + intel_memory *next; + intel_memory *prev; /** @} */ dri_bo *bo; @@ -356,7 +353,8 @@ typedef struct _I830CrtcPrivateRec { /* Lookup table values to be set when the CRTC is enabled */ uint8_t lut_r[256], lut_g[256], lut_b[256]; - i830_memory *rotate_mem; + drm_intel_bo *rotate_bo; + uint32_t rotate_pitch; /* Card virtual address of the cursor */ unsigned long cursor_offset; unsigned long cursor_argb_offset; @@ -464,11 +462,16 @@ struct sdvo_device_mapping { }; typedef struct intel_screen_private { + ScrnInfoPtr scrn; unsigned char *MMIOBase; unsigned char *GTTBase; unsigned char *FbBase; int cpp; +#define RENDER_BATCH I915_EXEC_RENDER +#define BLT_BATCH I915_EXEC_BLT + unsigned int current_batch; + unsigned int bufferOffset; /* for I830SelectBuffer */ /* These are set in PreInit and never changed. */ @@ -479,22 +482,24 @@ typedef struct intel_screen_private { * Linked list of video memory allocations. The head and tail are * dummy entries that bound the allocation area. */ - i830_memory *memory_list; + intel_memory *memory_list; /** Linked list of buffer object memory allocations */ - i830_memory *bo_list; + intel_memory *bo_list; long stolen_size; /**< bytes of pre-bound stolen memory */ int gtt_acquired; /**< whether we currently own the AGP */ - i830_memory *front_buffer; - i830_memory *compressed_front_buffer; - i830_memory *compressed_ll_buffer; + drm_intel_bo *front_buffer; + long front_pitch, front_tiling; + void *shadow_buffer; + int shadow_stride; + DamagePtr shadow_damage; /* One big buffer for all cursors for kernels that support this */ - i830_memory *cursor_mem; + intel_memory *cursor_mem; /* separate small buffers for kernels that support this */ - i830_memory *cursor_mem_classic[2]; + intel_memory *cursor_mem_classic[2]; /* One big buffer for all cursors for kernels that support this */ - i830_memory *cursor_mem_argb[2]; + intel_memory *cursor_mem_argb[2]; dri_bufmgr *bufmgr; @@ -506,17 +511,16 @@ typedef struct intel_screen_private { /** Number of bytes to be emitted in the current BEGIN_BATCH. */ uint32_t batch_emitting; dri_bo *batch_bo; - dri_bo *last_batch_bo; /** Whether we're in a section of code that can't tolerate flushing */ Bool in_batch_atomic; - /** Ending batch_used that was verified by i830_start_batch_atomic() */ + /** Ending batch_used that was verified by intel_start_batch_atomic() */ int batch_atomic_limit; struct list batch_pixmaps; struct list flush_pixmaps; struct list in_flight; /* For Xvideo */ - i830_memory *overlay_regs; + intel_memory *overlay_regs; void *offscreenImages; /**< remembered memory block for release */ Bool use_drmmode_overlay; #ifdef INTEL_XVMC @@ -528,15 +532,20 @@ typedef struct intel_screen_private { CreateScreenResourcesProcPtr CreateScreenResources; - i830_memory *power_context; + intel_memory *power_context; - i830_memory *memory_manager; /**< DRI memory manager aperture */ + intel_memory *memory_manager; /**< DRI memory manager aperture */ - Bool need_mi_flush; + Bool shadow_present; + + unsigned int tiling; +#define INTEL_TILING_FB 0x1 +#define INTEL_TILING_2D 0x2 +#define INTEL_TILING_3D 0x4 +#define INTEL_TILING_ALL (~0) - Bool tiling; - Bool fb_compression; Bool swapbuffers_wait; + Bool has_relaxed_fencing; Bool CursorNeedsPhysical; @@ -547,20 +556,20 @@ typedef struct intel_screen_private { IOADDRESS ioBase; EntityInfoPtr pEnt; struct pci_device *PciInfo; - uint8_t variant; + struct intel_chipset chipset; unsigned int BR[20]; - Bool fence_used[FENCE_NEW_NR]; - CloseScreenProcPtr CloseScreen; + void (*context_switch) (struct intel_screen_private *intel, + int new_mode); void (*vertex_flush) (struct intel_screen_private *intel); - void (*batch_flush_notify) (ScrnInfoPtr scrn); + void (*batch_flush) (struct intel_screen_private *intel); + void (*batch_commit_notify) (struct intel_screen_private *intel); uxa_driver_t *uxa_driver; - Bool need_flush; - int accel_pixmap_pitch_alignment; + Bool need_sync; int accel_pixmap_offset_alignment; int accel_max_x; int accel_max_y; @@ -591,6 +600,10 @@ typedef struct intel_screen_private { drm_intel_bo *gen4_cc_vp_bo; drm_intel_bo *gen4_sampler_bo; drm_intel_bo *gen4_sip_kernel_bo; + drm_intel_bo *wm_prog_packed_bo; + drm_intel_bo *wm_prog_planar_bo; + drm_intel_bo *gen6_blend_bo; + drm_intel_bo *gen6_depth_stencil_bo; } video; /* Render accel state */ @@ -605,6 +618,7 @@ typedef struct intel_screen_private { PixmapPtr render_current_dest; Bool render_source_is_solid; Bool render_mask_is_solid; + Bool needs_3d_invariant; Bool needs_render_state_emit; Bool needs_render_vertex_emit; Bool needs_render_ca_pass; @@ -623,20 +637,36 @@ typedef struct intel_screen_private { uint32_t dst_format; } i915_render_state; + struct { + int num_sf_outputs; + int drawrect; + uint32_t blend; + dri_bo *samplers; + dri_bo *kernel; + } gen6_render_state; + uint32_t prim_offset; - void (*prim_emit)(PixmapPtr dest, + void (*prim_emit)(struct intel_screen_private *intel, int srcX, int srcY, int maskX, int maskY, int dstX, int dstY, int w, int h); int floats_per_vertex; int last_floats_per_vertex; - uint32_t vertex_count; - uint32_t vertex_index; - uint32_t vertex_used; + uint16_t vertex_offset; + uint16_t vertex_count; + uint16_t vertex_index; + uint16_t vertex_used; + uint32_t vertex_id; float vertex_ptr[4*1024]; dri_bo *vertex_bo; + uint8_t surface_data[16*1024]; + uint16_t surface_used; + uint16_t surface_table; + uint32_t surface_reloc; + dri_bo *surface_bo; + /* 965 render acceleration state */ struct gen4_render_state *gen4_render_state; @@ -649,6 +679,12 @@ typedef struct intel_screen_private { #endif char *deviceName; + Bool force_fallback; + Bool can_blt; + Bool has_kernel_flush; + Bool needs_flush; + Bool use_shadow; + /* Broken-out options. */ OptionInfoPtr Options; @@ -664,11 +700,8 @@ typedef struct intel_screen_private { Bool tv_present; /* TV connector present (from VBIOS) */ /* Driver phase/state information */ - Bool preinit; Bool starting; - Bool closing; Bool suspended; - Bool leaving; unsigned int SaveGeneration; @@ -778,6 +811,43 @@ enum { DEBUG_FLUSH_WAIT = 0x4, }; +extern Bool intel_mode_pre_init(ScrnInfoPtr pScrn, int fd, int cpp); +extern void intel_mode_init(struct intel_screen_private *intel); +extern void intel_mode_remove_fb(intel_screen_private *intel); +extern void intel_mode_fini(intel_screen_private *intel); + +extern int intel_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, xf86CrtcPtr crtc); +extern int intel_crtc_id(xf86CrtcPtr crtc); +extern int intel_output_dpms_status(xf86OutputPtr output); + +enum DRI2FrameEventType { + DRI2_SWAP, + DRI2_FLIP, + DRI2_WAITMSC, +}; + +#if XORG_VERSION_CURRENT <= XORG_VERSION_NUMERIC(1,7,99,3,0) +typedef void (*DRI2SwapEventPtr)(ClientPtr client, void *data, int type, + CARD64 ust, CARD64 msc, CARD64 sbc); +#endif + +typedef struct _DRI2FrameEvent { + XID drawable_id; + XID client_id; /* fake client ID to track client destruction */ + ClientPtr client; + enum DRI2FrameEventType type; + int frame; + + /* for swaps & flips only */ + DRI2SwapEventPtr event_complete; + void *event_data; + DRI2BufferPtr front; + DRI2BufferPtr back; +} DRI2FrameEventRec, *DRI2FrameEventPtr; + +extern Bool intel_do_pageflip(intel_screen_private *intel, + dri_bo *new_front, + DRI2FrameEventPtr flip_info, int ref_crtc_hw_id); static inline intel_screen_private * intel_get_screen_private(ScrnInfoPtr scrn) @@ -789,16 +859,13 @@ intel_get_screen_private(ScrnInfoPtr scrn) #define ALIGN(i,m) (((i) + (m) - 1) & ~((m) - 1)) #define MIN(a,b) ((a) < (b) ? (a) : (b)) -#define I830_SELECT_FRONT 0 -#define I830_SELECT_BACK 1 -#define I830_SELECT_DEPTH 2 -#define I830_SELECT_THIRD 3 - -unsigned long intel_get_pixmap_offset(PixmapPtr pixmap); -unsigned long intel_get_pixmap_pitch(PixmapPtr pixmap); +static inline unsigned long intel_pixmap_pitch(PixmapPtr pixmap) +{ + return (unsigned long)pixmap->devKind; +} /* Batchbuffer support macros and functions */ -#include "i830_batchbuffer.h" +#include "intel_batchbuffer.h" /* I830 specific functions */ extern void I830SetPIOAccess(intel_screen_private *intel); @@ -838,12 +905,12 @@ extern void I830EmitFlush(ScrnInfoPtr scrn); extern void I830InitVideo(ScreenPtr pScreen); extern void i830_crtc_dpms_video(xf86CrtcPtr crtc, Bool on); -extern xf86CrtcPtr i830_covering_crtc(ScrnInfoPtr scrn, BoxPtr box, +extern xf86CrtcPtr intel_covering_crtc(ScrnInfoPtr scrn, BoxPtr box, xf86CrtcPtr desired, BoxPtr crtc_box_ret); int i830_crtc_pipe (xf86CrtcPtr crtc); -extern xf86CrtcPtr i830_pipe_to_crtc(ScrnInfoPtr scrn, int pipe); +extern xf86CrtcPtr intel_pipe_to_crtc(ScrnInfoPtr scrn, int pipe); Bool i830_pipe_a_require_activate (ScrnInfoPtr scrn); @@ -864,8 +931,9 @@ extern int drmmode_output_dpms_status(xf86OutputPtr output); extern int drmmode_crtc_id(xf86CrtcPtr crtc); void drmmode_crtc_set_cursor_bo(xf86CrtcPtr crtc, dri_bo * cursor); -extern Bool i830_crtc_on(xf86CrtcPtr crtc); -extern int i830_crtc_to_pipe(xf86CrtcPtr crtc); +extern Bool intel_crtc_on(xf86CrtcPtr crtc); +extern int intel_crtc_to_pipe(xf86CrtcPtr crtc); + extern Bool I830AccelInit(ScreenPtr pScreen); extern void I830SetupForScreenToScreenCopy(ScrnInfoPtr scrn, int xdir, int ydir, int rop, @@ -881,31 +949,19 @@ extern void I830SubsequentSolidFillRect(ScrnInfoPtr scrn, int x, int y, Bool i830_allocator_init(ScrnInfoPtr scrn, unsigned long size); void i830_allocator_fini(ScrnInfoPtr scrn); -i830_memory *i830_allocate_memory(ScrnInfoPtr scrn, const char *name, +intel_memory *i830_allocate_memory(ScrnInfoPtr scrn, const char *name, unsigned long size, unsigned long pitch, - unsigned long alignment, int flags, - enum tile_format tile_format); + unsigned long alignment, int flags); void i830_describe_allocations(ScrnInfoPtr scrn, int verbosity, const char *prefix); -void i830_reset_allocations(ScrnInfoPtr scrn); -void i830_free_3d_memory(ScrnInfoPtr scrn); -void i830_free_memory(ScrnInfoPtr scrn, i830_memory *mem); +void i830_free_memory(ScrnInfoPtr scrn, intel_memory *mem); extern long I830CheckAvailableMemory(ScrnInfoPtr scrn); Bool i830_allocate_2d_memory(ScrnInfoPtr scrn); Bool i830_allocate_pwrctx(ScrnInfoPtr scrn); -Bool i830_allocate_3d_memory(ScrnInfoPtr scrn); -void i830_init_bufmgr(ScrnInfoPtr scrn); -#ifdef INTEL_XVMC -Bool i830_allocate_xvmc_buffer(ScrnInfoPtr scrn, const char *name, - i830_memory ** buffer, unsigned long size, - int flags); -void i830_free_xvmc_buffer(ScrnInfoPtr scrn, i830_memory * buffer); -#endif +void intel_init_bufmgr(ScrnInfoPtr scrn); extern uint32_t i830_create_new_fb(ScrnInfoPtr scrn, int width, int height, int *pitch); -Bool i830_tiled_width(intel_screen_private *intel, int *width, int cpp); - extern Bool I830I2CInit(ScrnInfoPtr scrn, I2CBusPtr *bus_ptr, int i2c_reg, char *name); @@ -924,16 +980,24 @@ void i830_hdmi_init(ScrnInfoPtr scrn, int output_reg); /* i830_lvds.c */ void i830_lvds_init(ScrnInfoPtr scrn); - -/* i830_memory.c */ + +/* intel_memory.c */ Bool i830_bind_all_memory(ScrnInfoPtr scrn); Bool i830_unbind_all_memory(ScrnInfoPtr scrn); unsigned long i830_get_fence_size(intel_screen_private *intel, unsigned long size); unsigned long i830_get_fence_pitch(intel_screen_private *intel, unsigned long pitch, int format); -void i830_set_gem_max_sizes(ScrnInfoPtr scrn); - -i830_memory *i830_allocate_framebuffer(ScrnInfoPtr scrn); +void intel_set_gem_max_sizes(ScrnInfoPtr scrn); +/* intel_memory.c */ +unsigned long intel_get_fence_size(intel_screen_private *intel, unsigned long size); +unsigned long intel_get_fence_pitch(intel_screen_private *intel, unsigned long pitch, + uint32_t tiling_mode); +void intel_set_gem_max_sizes(ScrnInfoPtr scrn); + +drm_intel_bo *intel_allocate_framebuffer(ScrnInfoPtr scrn, + int w, int h, int cpp, + unsigned long *pitch, + uint32_t *tiling); /* i830_modes.c */ DisplayModePtr i830_ddc_get_modes(xf86OutputPtr output); @@ -950,11 +1014,10 @@ Bool i830_check_composite_texture(ScreenPtr screen, PicturePtr picture); Bool i830_prepare_composite(int op, PicturePtr sourcec, PicturePtr mask, PicturePtr dest, PixmapPtr sourcecPixmap, PixmapPtr maskPixmap, PixmapPtr destPixmap); -Bool i830_transform_is_affine(PictTransformPtr t); - void i830_composite(PixmapPtr dest, int srcX, int srcY, int maskX, int maskY, int dstX, int dstY, int w, int h); -void i830_done_composite(PixmapPtr dest); +void i830_vertex_flush(intel_screen_private *intel); + /* i915_render.c */ Bool i915_check_composite(int op, PicturePtr sourcec, PicturePtr mask, PicturePtr dest, @@ -967,8 +1030,8 @@ Bool i915_prepare_composite(int op, PicturePtr sourcec, PicturePtr mask, void i915_composite(PixmapPtr dest, int srcX, int srcY, int maskX, int maskY, int dstX, int dstY, int w, int h); void i915_vertex_flush(intel_screen_private *intel); -void i915_batch_flush_notify(ScrnInfoPtr scrn); -void i830_batch_flush_notify(ScrnInfoPtr scrn); +void i915_batch_commit_notify(intel_screen_private *intel); +void i830_batch_commit_notify(intel_screen_private *intel); /* i965_render.c */ unsigned int gen4_render_state_size(ScrnInfoPtr scrn); void gen4_render_state_init(ScrnInfoPtr scrn); @@ -983,44 +1046,52 @@ Bool i965_prepare_composite(int op, PicturePtr sourcec, PicturePtr mask, void i965_composite(PixmapPtr dest, int srcX, int srcY, int maskX, int maskY, int dstX, int dstY, int w, int h); -void i965_batch_flush_notify(ScrnInfoPtr scrn); - +void i965_vertex_flush(intel_screen_private *intel); +void i965_batch_flush(intel_screen_private *intel); +void i965_batch_commit_notify(intel_screen_private *intel); + +/* i965_3d.c */ +void gen6_upload_invariant_states(intel_screen_private *intel); +void gen6_upload_viewport_state_pointers(intel_screen_private *intel, + drm_intel_bo *cc_vp_bo); +void gen7_upload_viewport_state_pointers(intel_screen_private *intel, + drm_intel_bo *cc_vp_bo); +void gen6_upload_urb(intel_screen_private *intel); +void gen7_upload_urb(intel_screen_private *intel); +void gen6_upload_cc_state_pointers(intel_screen_private *intel, + drm_intel_bo *blend_bo, drm_intel_bo *cc_bo, + drm_intel_bo *depth_stencil_bo, + uint32_t blend_offset); +void gen7_upload_cc_state_pointers(intel_screen_private *intel, + drm_intel_bo *blend_bo, drm_intel_bo *cc_bo, + drm_intel_bo *depth_stencil_bo, + uint32_t blend_offset); +void gen6_upload_sampler_state_pointers(intel_screen_private *intel, + drm_intel_bo *sampler_bo); +void gen7_upload_sampler_state_pointers(intel_screen_private *intel, + drm_intel_bo *sampler_bo); +void gen7_upload_bypass_states(intel_screen_private *intel); +void gen6_upload_gs_state(intel_screen_private *intel); +void gen6_upload_vs_state(intel_screen_private *intel); +void gen6_upload_clip_state(intel_screen_private *intel); +void gen6_upload_sf_state(intel_screen_private *intel, int num_sf_outputs, int read_offset); +void gen7_upload_sf_state(intel_screen_private *intel, int num_sf_outputs, int read_offset); +void gen6_upload_binding_table(intel_screen_private *intel, uint32_t ps_binding_table_offset); +void gen7_upload_binding_table(intel_screen_private *intel, uint32_t ps_binding_table_offset); +void gen6_upload_depth_buffer_state(intel_screen_private *intel); +void gen7_upload_depth_buffer_state(intel_screen_private *intel); + +Bool intel_transform_is_affine(PictTransformPtr t); Bool -i830_get_transformed_coordinates(int x, int y, PictTransformPtr transform, +intel_get_transformed_coordinates(int x, int y, PictTransformPtr transform, float *x_out, float *y_out); Bool -i830_get_transformed_coordinates_3d(int x, int y, PictTransformPtr transform, +intel_get_transformed_coordinates_3d(int x, int y, PictTransformPtr transform, float *x_out, float *y_out, float *z_out); -void i830_enter_render(ScrnInfoPtr); - extern void intel_sync(ScrnInfoPtr scrn); -static inline int i830_fb_compression_supported(intel_screen_private *intel) -{ - if (!IS_MOBILE(intel)) - return FALSE; - if (IS_I810(intel) || IS_I815(intel) || IS_I830(intel)) - return FALSE; - if (IS_IGD(intel)) - return FALSE; - if (IS_IGDNG(intel)) - return FALSE; - /* fbc depends on tiled surface. - */ - if (!intel->tiling) - return FALSE; - /* We have not gotten FBC to work consistently on 965GM. Our best - * working theory right now is that FBC simply isn't reliable on - * that device. See this bug report for more details: - * https://bugs.freedesktop.org/show_bug.cgi?id=16257 - */ - if (IS_I965GM(intel) || IS_I915GM(intel) || IS_I945GM(intel)) - return FALSE; - return TRUE; -} - static inline void intel_debug_fallback(ScrnInfoPtr scrn, char *format, ...) { @@ -1040,7 +1111,7 @@ Bool i830_pixmap_tiled(PixmapPtr p); static inline Bool intel_check_pitch_2d(PixmapPtr pixmap) { - uint32_t pitch = intel_get_pixmap_pitch(pixmap); + uint32_t pitch = intel_pixmap_pitch(pixmap); if (pitch > KB(32)) { ScrnInfoPtr scrn = xf86Screens[pixmap->drawable.pScreen->myNum]; intel_debug_fallback(scrn, "pitch exceeds 2d limit 32K\n"); @@ -1053,7 +1124,7 @@ intel_check_pitch_2d(PixmapPtr pixmap) static inline Bool intel_check_pitch_3d(PixmapPtr pixmap) { - uint32_t pitch = intel_get_pixmap_pitch(pixmap); + uint32_t pitch = intel_pixmap_pitch(pixmap); if (pitch > KB(8)) { ScrnInfoPtr scrn = xf86Screens[pixmap->drawable.pScreen->myNum]; intel_debug_fallback(scrn, "pitch exceeds 3d limit 8K\n"); @@ -1079,24 +1150,49 @@ intel_emit_reloc(drm_intel_bo * bo, uint32_t offset, return target_bo->offset + target_offset; } -static inline drm_intel_bo *intel_bo_alloc_for_data(ScrnInfoPtr scrn, - void *data, +static inline drm_intel_bo *intel_bo_alloc_for_data(intel_screen_private *intel, + const void *data, unsigned int size, char *name) { - intel_screen_private *intel = intel_get_screen_private(scrn); drm_intel_bo *bo; bo = drm_intel_bo_alloc(intel->bufmgr, name, size, 4096); - if (!bo) - return NULL; - drm_intel_bo_subdata(bo, 0, size, data); - + if (bo) + drm_intel_bo_subdata(bo, 0, size, data); return bo; } -extern const int I830PatternROP[16]; -extern const int I830CopyROP[16]; +void intel_debug_flush(ScrnInfoPtr scrn); + +static inline PixmapPtr get_drawable_pixmap(DrawablePtr drawable) +{ + ScreenPtr screen = drawable->pScreen; + + if (drawable->type == DRAWABLE_PIXMAP) + return (PixmapPtr) drawable; + else + return screen->GetWindowPixmap((WindowPtr) drawable); +} + +static inline Bool pixmap_is_scanout(PixmapPtr pixmap) +{ + ScreenPtr screen = pixmap->drawable.pScreen; + + return pixmap == screen->GetScreenPixmap(screen); +} + +const OptionInfoRec *intel_uxa_available_options(int chipid, int busid); + +Bool intel_uxa_init(ScreenPtr pScreen); +Bool intel_uxa_create_screen_resources(ScreenPtr pScreen); +void intel_uxa_block_handler(intel_screen_private *intel); +Bool intel_get_aperture_space(ScrnInfoPtr scrn, drm_intel_bo ** bo_table, + int num_bos); + +/* intel_shadow.c */ +void intel_shadow_blt(intel_screen_private *intel); +void intel_shadow_create(struct intel_screen_private *intel); /* Flags for memory allocation function */ #define NEED_PHYSICAL_ADDR 0x00000001 @@ -1123,32 +1219,4 @@ extern const int I830CopyROP[16]; #define QUIRK_BROKEN_ACPI_LID 0x00000100 extern void i830_fixup_devices(ScrnInfoPtr); -void i830_debug_flush(ScrnInfoPtr scrn); - -static inline PixmapPtr get_drawable_pixmap(DrawablePtr drawable) -{ - ScreenPtr screen = drawable->pScreen; - - if (drawable->type == DRAWABLE_PIXMAP) - return (PixmapPtr) drawable; - else - return screen->GetWindowPixmap((WindowPtr) drawable); -} - -static inline Bool pixmap_is_scanout(PixmapPtr pixmap) -{ - ScreenPtr screen = pixmap->drawable.pScreen; - - return pixmap == screen->GetScreenPixmap(screen); -} - -/* - * Pad to accelerator requirement - */ -static inline int i830_pad_drawable_width(int width) -{ - return (width + 63) & ~63; -} - - #endif /* _I830_H_ */ diff --git a/driver/xf86-video-intel/src/i830_batchbuffer.c b/driver/xf86-video-intel/src/intel_batchbuffer.c index 2ef89f246..e01294892 100644 --- a/driver/xf86-video-intel/src/i830_batchbuffer.c +++ b/driver/xf86-video-intel/src/intel_batchbuffer.c @@ -32,23 +32,29 @@ #include <assert.h> #include <stdlib.h> +#include <errno.h> #include "xf86.h" -#include "i830.h" -#include "i830_ring.h" +#include "intel.h" +#include "i830_reg.h" #include "i915_drm.h" +#include "i965_reg.h" -#define DUMP_BATCHBUFFERS NULL /* "/tmp/i915-batchbuffers.dump" */ +#define DUMP_BATCHBUFFERS NULL // "/tmp/i915-batchbuffers.dump" static void intel_end_vertex(intel_screen_private *intel) { if (intel->vertex_bo) { - if (intel->vertex_used) + if (intel->vertex_used) { dri_bo_subdata(intel->vertex_bo, 0, intel->vertex_used*4, intel->vertex_ptr); + intel->vertex_used = 0; + } dri_bo_unreference(intel->vertex_bo); intel->vertex_bo = NULL; } + + intel->vertex_id = 0; } void intel_next_vertex(intel_screen_private *intel) @@ -57,7 +63,6 @@ void intel_next_vertex(intel_screen_private *intel) intel->vertex_bo = dri_bo_alloc(intel->bufmgr, "vertex", sizeof (intel->vertex_ptr), 4096); - intel->vertex_used = 0; } static void intel_next_batch(ScrnInfoPtr scrn) @@ -86,6 +91,7 @@ void intel_batch_init(ScrnInfoPtr scrn) intel->batch_emit_start = 0; intel->batch_emitting = 0; + intel->vertex_id = 0; intel_next_batch(scrn); } @@ -99,11 +105,6 @@ void intel_batch_teardown(ScrnInfoPtr scrn) intel->batch_bo = NULL; } - if (intel->last_batch_bo != NULL) { - dri_bo_unreference(intel->last_batch_bo); - intel->last_batch_bo = NULL; - } - if (intel->vertex_bo) { dri_bo_unreference(intel->vertex_bo); intel->vertex_bo = NULL; @@ -134,8 +135,6 @@ void intel_batch_do_flush(ScrnInfoPtr scrn) while (!list_is_empty(&intel->flush_pixmaps)) list_del(intel->flush_pixmaps.next); - - intel->need_mi_flush = FALSE; } void intel_batch_emit_flush(ScrnInfoPtr scrn) @@ -146,18 +145,44 @@ void intel_batch_emit_flush(ScrnInfoPtr scrn) assert (!intel->in_batch_atomic); /* Big hammer, look to the pipelined flushes in future. */ - flags = MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE; - if (IS_I965G(intel)) - flags = 0; - - BEGIN_BATCH(1); - OUT_BATCH(MI_FLUSH | flags); - ADVANCE_BATCH(); - + if ((INTEL_INFO(intel)->gen >= 60)) { + if (intel->current_batch == BLT_BATCH) { + BEGIN_BATCH_BLT(4); + OUT_BATCH(MI_FLUSH_DW | 2); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + ADVANCE_BATCH(); + } else { + BEGIN_BATCH(4); + OUT_BATCH(BRW_PIPE_CONTROL | (4 - 2)); + OUT_BATCH(BRW_PIPE_CONTROL_WC_FLUSH | + BRW_PIPE_CONTROL_TC_FLUSH | + BRW_PIPE_CONTROL_NOWRITE); + OUT_BATCH(0); /* write address */ + OUT_BATCH(0); /* write data */ + ADVANCE_BATCH(); + } + } else { + flags = MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE; + if (INTEL_INFO(intel)->gen >= 40) + flags = 0; + + BEGIN_BATCH(1); + OUT_BATCH(MI_FLUSH | flags); + ADVANCE_BATCH(); + } intel_batch_do_flush(scrn); } -void intel_batch_submit(ScrnInfoPtr scrn, int flush) +static Bool intel_batch_needs_flush(intel_screen_private *intel) +{ + ScreenPtr screen = intel->scrn->pScreen; + PixmapPtr pixmap = screen->GetScreenPixmap(screen); + return intel_get_pixmap_private(pixmap)->batch_write; +} + +void intel_batch_submit(ScrnInfoPtr scrn) { intel_screen_private *intel = intel_get_screen_private(scrn); int ret; @@ -168,8 +193,8 @@ void intel_batch_submit(ScrnInfoPtr scrn, int flush) intel->vertex_flush(intel); intel_end_vertex(intel); - if (flush) - intel_batch_emit_flush(scrn); + if (intel->batch_flush) + intel->batch_flush(intel); if (intel->batch_used == 0) return; @@ -189,21 +214,36 @@ void intel_batch_submit(ScrnInfoPtr scrn, int flush) } ret = dri_bo_subdata(intel->batch_bo, 0, intel->batch_used*4, intel->batch_ptr); - if (ret == 0) - ret = dri_bo_exec(intel->batch_bo, intel->batch_used*4, - NULL, 0, 0xffffffff); - if (ret != 0) { - static int once; + if (ret == 0) { + ret = drm_intel_bo_mrb_exec(intel->batch_bo, + intel->batch_used*4, + NULL, 0, 0xffffffff, + (HAS_BLT(intel) ? + intel->current_batch: + I915_EXEC_DEFAULT)); + } - if (!once) { + if (ret != 0) { + if (ret == -EIO) { + static int once; + + /* The GPU has hung and unlikely to recover by this point. */ + if (!once) { + xf86DrvMsg(scrn->scrnIndex, X_ERROR, "Detected a hung GPU, disabling acceleration.\n"); + uxa_set_force_fallback(screenInfo.screens[scrn->scrnIndex], TRUE); + intel->force_fallback = TRUE; + once = 1; + } + } else { xf86DrvMsg(scrn->scrnIndex, X_ERROR, "Failed to submit batch buffer, expect rendering corruption " "or even a frozen display: %s.\n", strerror(-ret)); - once = 1; } } + intel->needs_flush |= intel_batch_needs_flush(intel); + while (!list_is_empty(&intel->batch_pixmaps)) { struct intel_pixmap *entry; @@ -216,7 +256,6 @@ void intel_batch_submit(ScrnInfoPtr scrn, int flush) list_del(&entry->batch); } - intel->need_mi_flush |= !list_is_empty(&intel->flush_pixmaps); while (!list_is_empty(&intel->flush_pixmaps)) list_del(intel->flush_pixmaps.next); @@ -232,44 +271,42 @@ void intel_batch_submit(ScrnInfoPtr scrn, int flush) free(entry); } - /* Save a ref to the last batch emitted, which we use for syncing - * in debug code. - */ - dri_bo_unreference(intel->last_batch_bo); - intel->last_batch_bo = intel->batch_bo; - intel->batch_bo = NULL; + if (intel->debug_flush & DEBUG_FLUSH_WAIT) + drm_intel_bo_wait_rendering(intel->batch_bo); + dri_bo_unreference(intel->batch_bo); intel_next_batch(scrn); - if (intel->debug_flush & DEBUG_FLUSH_WAIT) - intel_batch_wait_last(scrn); + if (intel->batch_commit_notify) + intel->batch_commit_notify(intel); - if (intel->batch_flush_notify) - intel->batch_flush_notify(scrn); + intel->current_batch = 0; } -/** Waits on the last emitted batchbuffer to be completed. */ -void intel_batch_wait_last(ScrnInfoPtr scrn) +void intel_debug_flush(ScrnInfoPtr scrn) { intel_screen_private *intel = intel_get_screen_private(scrn); - /* Map it CPU write, which guarantees it's done. This is a completely - * non performance path, so we don't need anything better. - */ - drm_intel_gem_bo_map_gtt(intel->last_batch_bo); - drm_intel_gem_bo_unmap_gtt(intel->last_batch_bo); + if (intel->debug_flush & DEBUG_FLUSH_CACHES) + intel_batch_emit_flush(scrn); + + if (intel->debug_flush & DEBUG_FLUSH_BATCHES) + intel_batch_submit(scrn); } void intel_sync(ScrnInfoPtr scrn) { intel_screen_private *intel = intel_get_screen_private(scrn); - - if (I810_DEBUG & (DEBUG_VERBOSE_ACCEL | DEBUG_VERBOSE_SYNC)) - ErrorF("I830Sync\n"); + int had; if (!scrn->vtSema || !intel->batch_bo || !intel->batch_ptr) return; - intel_batch_submit(scrn, TRUE); - intel_batch_wait_last(scrn); + + /* XXX hack while we still need this for ums */ + had = intel->debug_flush & DEBUG_FLUSH_WAIT; + intel->debug_flush |= DEBUG_FLUSH_WAIT; + intel_batch_submit(scrn); + if (!had) + intel->debug_flush &= ~DEBUG_FLUSH_WAIT; } diff --git a/driver/xf86-video-intel/src/i830_batchbuffer.h b/driver/xf86-video-intel/src/intel_batchbuffer.h index 30680855d..6cba76dcf 100644 --- a/driver/xf86-video-intel/src/i830_batchbuffer.h +++ b/driver/xf86-video-intel/src/intel_batchbuffer.h @@ -37,8 +37,7 @@ void intel_batch_init(ScrnInfoPtr scrn); void intel_batch_teardown(ScrnInfoPtr scrn); void intel_batch_emit_flush(ScrnInfoPtr scrn); void intel_batch_do_flush(ScrnInfoPtr scrn); -void intel_batch_submit(ScrnInfoPtr scrn, int flush); -void intel_batch_wait_last(ScrnInfoPtr scrn); +void intel_batch_submit(ScrnInfoPtr scrn); static inline int intel_batch_space(intel_screen_private *intel) { @@ -51,19 +50,26 @@ static inline int intel_vertex_space(intel_screen_private *intel) } static inline void -intel_batch_require_space(ScrnInfoPtr scrn, intel_screen_private *intel, GLuint sz) +intel_batch_require_space(ScrnInfoPtr scrn, intel_screen_private *intel, int sz) { assert(sz < intel->batch_bo->size - 8); if (intel_batch_space(intel) < sz) - intel_batch_submit(scrn, FALSE); + intel_batch_submit(scrn); } -static inline void intel_batch_start_atomic(ScrnInfoPtr scrn, unsigned int sz) +static inline void intel_batch_start_atomic(ScrnInfoPtr scrn, int sz) { intel_screen_private *intel = intel_get_screen_private(scrn); assert(!intel->in_batch_atomic); + + if (intel->current_batch != RENDER_BATCH) { + if (intel->current_batch && intel->context_switch) + intel->context_switch(intel, RENDER_BATCH); + } + intel_batch_require_space(scrn, intel, sz * 4); + intel->current_batch = RENDER_BATCH; intel->in_batch_atomic = TRUE; intel->batch_atomic_limit = intel->batch_used + sz; @@ -131,6 +137,8 @@ intel_batch_mark_pixmap_domains(intel_screen_private *intel, priv->batch_write |= write_domain != 0; priv->busy = 1; + + intel->needs_flush |= write_domain != 0; } static inline void @@ -138,7 +146,7 @@ intel_batch_emit_reloc_pixmap(intel_screen_private *intel, PixmapPtr pixmap, uint32_t read_domains, uint32_t write_domain, uint32_t delta, int needs_fence) { - struct intel_pixmap *priv = i830_get_pixmap_intel(pixmap); + struct intel_pixmap *priv = intel_get_pixmap_private(pixmap); intel_batch_mark_pixmap_domains(intel, priv, read_domains, write_domain); @@ -152,6 +160,9 @@ intel_batch_emit_reloc_pixmap(intel_screen_private *intel, PixmapPtr pixmap, #define OUT_RELOC(bo, read_domains, write_domains, delta) \ intel_batch_emit_reloc(intel, bo, read_domains, write_domains, delta, 0) +#define OUT_RELOC_FENCED(bo, read_domains, write_domains, delta) \ + intel_batch_emit_reloc(intel, bo, read_domains, write_domains, delta, 1) + #define OUT_RELOC_PIXMAP(pixmap, reads, write, delta) \ intel_batch_emit_reloc_pixmap(intel, pixmap, reads, write, delta, 0) @@ -169,17 +180,25 @@ union intfloat { OUT_BATCH(tmp.ui); \ } while(0) -#define BEGIN_BATCH(n) \ +#define __BEGIN_BATCH(n,batch_idx) \ do { \ if (intel->batch_emitting != 0) \ FatalError("%s: BEGIN_BATCH called without closing " \ "ADVANCE_BATCH\n", __FUNCTION__); \ assert(!intel->in_batch_atomic); \ + if (intel->current_batch != batch_idx) { \ + if (intel->current_batch && intel->context_switch) \ + intel->context_switch(intel, batch_idx); \ + } \ intel_batch_require_space(scrn, intel, (n) * 4); \ + intel->current_batch = batch_idx; \ intel->batch_emitting = (n); \ intel->batch_emit_start = intel->batch_used; \ } while (0) +#define BEGIN_BATCH(n) __BEGIN_BATCH(n,RENDER_BATCH) +#define BEGIN_BATCH_BLT(n) __BEGIN_BATCH(n,BLT_BATCH) + #define ADVANCE_BATCH() do { \ if (intel->batch_emitting == 0) \ FatalError("%s: ADVANCE_BATCH called with no matching " \ @@ -196,11 +215,6 @@ do { \ __FUNCTION__, \ intel->batch_used - intel->batch_emit_start, \ intel->batch_emitting); \ - if ((intel->batch_emitting > 8) && \ - (I810_DEBUG & DEBUG_ALWAYS_SYNC)) { \ - /* Note: not actually syncing, just flushing each batch. */ \ - intel_batch_submit(scrn, FALSE); \ - } \ intel->batch_emitting = 0; \ } while (0) diff --git a/driver/xf86-video-intel/src/i830_dri.c b/driver/xf86-video-intel/src/intel_dri.c index ab895df73..a19148714 100644 --- a/driver/xf86-video-intel/src/i830_dri.c +++ b/driver/xf86-video-intel/src/intel_dri.c @@ -58,9 +58,10 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #include "windowstr.h" #include "shadow.h" -#include "GL/glxtokens.h" +#include "xaarop.h" -#include "i830.h" +#include "intel.h" +#include "i830_reg.h" #include "i915_drm.h" @@ -80,7 +81,121 @@ typedef struct { unsigned int attachment; } I830DRI2BufferPrivateRec, *I830DRI2BufferPrivatePtr; -#ifndef USE_DRI2_1_1_0 +static uint32_t pixmap_flink(PixmapPtr pixmap) +{ + struct intel_pixmap *priv = intel_get_pixmap_private(pixmap); + uint32_t name; + + if (priv == NULL || priv->bo == NULL) + return 0; + + if (dri_bo_flink(priv->bo, &name) != 0) + return 0; + + priv->pinned = 1; + return name; +} + +static PixmapPtr get_front_buffer(DrawablePtr drawable) +{ + ScreenPtr screen = drawable->pScreen; + ScrnInfoPtr scrn = xf86Screens[screen->myNum]; + intel_screen_private *intel = intel_get_screen_private(scrn); + PixmapPtr pixmap; + + pixmap = get_drawable_pixmap(drawable); + if (!intel->use_shadow) { + pixmap->refcnt++; + } else if (pixmap_is_scanout(pixmap)) { + pixmap = fbCreatePixmap(screen, 0, 0, drawable->depth, 0); + if (pixmap) { + screen->ModifyPixmapHeader(pixmap, + drawable->width, + drawable->height, + 0, 0, + intel->front_pitch, + intel->front_buffer->virtual); + + intel_set_pixmap_bo(pixmap, intel->front_buffer); + intel_get_pixmap_private(pixmap)->offscreen = 0; + if (WindowDrawable(drawable->type)) + screen->SetWindowPixmap((WindowPtr)drawable, + pixmap); + } + } else if (intel_get_pixmap_bo(pixmap)) { + pixmap->refcnt++; + } else + pixmap = NULL; + return pixmap; +} + +static PixmapPtr fixup_shadow(DrawablePtr drawable, PixmapPtr pixmap) +{ + ScreenPtr screen = drawable->pScreen; + PixmapPtr old = get_drawable_pixmap(drawable); + struct intel_pixmap *priv = intel_get_pixmap_private(pixmap); + GCPtr gc; + + /* With an active shadow buffer, 2D pixmaps are created in + * system memory and GPU acceleration of 2D render operations + * is *disabled*. As DRI is still enabled, we create hardware + * buffers for the clients, and need to mix this with the + * 2D rendering. So we replace the system pixmap with a GTT + * mapping (with the kernel enforcing coherency between + * CPU and GPU) for 2D and provide the bo so that clients + * can write directly to it (or read from it in the case + * of TextureFromPixmap) using the GPU. + * + * So for a compositor with a GL backend (i.e. compiz) we have + * smooth wobbly windows but incur the cost of uncached 2D rendering, + * however 3D applications (games and clutter) are still fully + * accelerated. + */ + + if (drm_intel_gem_bo_map_gtt(priv->bo)) + return pixmap; + + screen->ModifyPixmapHeader(pixmap, + drawable->width, + drawable->height, + 0, 0, + priv->stride, + priv->bo->virtual); + priv->offscreen = 0; + + /* Copy the current contents of the pixmap to the bo. */ + gc = GetScratchGC(drawable->depth, screen); + if (gc) { + ValidateGC(&pixmap->drawable, gc); + gc->ops->CopyArea(drawable, &pixmap->drawable, + gc, + 0, 0, + drawable->width, + drawable->height, + 0, 0); + FreeScratchGC(gc); + } + + intel_set_pixmap_private(pixmap, NULL); + screen->DestroyPixmap(pixmap); + + /* Redirect 2D rendering to the uncached GTT map of the bo */ + screen->ModifyPixmapHeader(old, + drawable->width, + drawable->height, + 0, 0, + priv->stride, + priv->bo->virtual); + + /* And redirect the pixmap to the new bo (for 3D). */ + intel_set_pixmap_private(old, priv); + old->refcnt++; + + intel_get_screen_private(xf86Screens[screen->myNum])->needs_flush = TRUE; + return old; +} + +#if DRI2INFOREC_VERSION < 2 static DRI2BufferPtr I830DRI2CreateBuffers(DrawablePtr drawable, unsigned int *attachments, int count) @@ -89,10 +204,9 @@ I830DRI2CreateBuffers(DrawablePtr drawable, unsigned int *attachments, ScrnInfoPtr scrn = xf86Screens[screen->myNum]; intel_screen_private *intel = intel_get_screen_private(scrn); DRI2BufferPtr buffers; - dri_bo *bo; - int i; I830DRI2BufferPrivatePtr privates; PixmapPtr pixmap, pDepthPixmap; + int i; buffers = calloc(count, sizeof *buffers); if (buffers == NULL) @@ -105,39 +219,48 @@ I830DRI2CreateBuffers(DrawablePtr drawable, unsigned int *attachments, pDepthPixmap = NULL; for (i = 0; i < count; i++) { + pixmap = NULL; if (attachments[i] == DRI2BufferFrontLeft) { - pixmap = get_drawable_pixmap(drawable); - pixmap->refcnt++; + pixmap = get_front_buffer(drawable); } else if (attachments[i] == DRI2BufferStencil && pDepthPixmap) { pixmap = pDepthPixmap; pixmap->refcnt++; - } else { - unsigned int hint = 0; - - switch (attachments[i]) { - case DRI2BufferDepth: - if (SUPPORTS_YTILING(intel)) - hint = INTEL_CREATE_PIXMAP_TILING_Y; - else - hint = INTEL_CREATE_PIXMAP_TILING_X; - break; - case DRI2BufferFakeFrontLeft: - case DRI2BufferFakeFrontRight: - case DRI2BufferBackLeft: - case DRI2BufferBackRight: - hint = INTEL_CREATE_PIXMAP_TILING_X; - break; + } + if (pixmap == NULL) { + unsigned int hint = INTEL_CREATE_PIXMAP_DRI2; + + if (intel->tiling & INTEL_TILING_3D) { + switch (attachments[i]) { + case DRI2BufferDepth: + if (SUPPORTS_YTILING(intel)) + hint |= INTEL_CREATE_PIXMAP_TILING_Y; + else + hint |= INTEL_CREATE_PIXMAP_TILING_X; + break; + case DRI2BufferFakeFrontLeft: + case DRI2BufferFakeFrontRight: + case DRI2BufferBackLeft: + case DRI2BufferBackRight: + hint |= INTEL_CREATE_PIXMAP_TILING_X; + break; + } } - if (!intel->tiling) - hint = 0; - pixmap = screen->CreatePixmap(screen, drawable->width, drawable->height, drawable->depth, hint); + if (pixmap == NULL || + intel_get_pixmap_bo(pixmap) == NULL) + { + if (pixmap) + screen->DestroyPixmap(pixmap); + goto unwind; + } + if (attachment == DRI2BufferFrontLeft) + pixmap = fixup_shadow(drawable, pixmap); } if (attachments[i] == DRI2BufferDepth) @@ -152,13 +275,21 @@ I830DRI2CreateBuffers(DrawablePtr drawable, unsigned int *attachments, privates[i].pixmap = pixmap; privates[i].attachment = attachments[i]; - bo = i830_get_pixmap_bo(pixmap); - if (bo != NULL && dri_bo_flink(bo, &buffers[i].name) != 0) { + if ((buffers[i].name = pixmap_flink(pixmap)) == 0) { /* failed to name buffer */ + screen->DestroyPixmap(pixmap); + goto unwind; } } return buffers; + +unwind: + while (i--) + screen->DestroyPixmap(privates[i].pixmap); + free(privates); + free(buffers); + return NULL; } #else @@ -171,7 +302,6 @@ I830DRI2CreateBuffer(DrawablePtr drawable, unsigned int attachment, ScrnInfoPtr scrn = xf86Screens[screen->myNum]; intel_screen_private *intel = intel_get_screen_private(scrn); DRI2Buffer2Ptr buffer; - dri_bo *bo; I830DRI2BufferPrivatePtr privates; PixmapPtr pixmap; @@ -184,30 +314,35 @@ I830DRI2CreateBuffer(DrawablePtr drawable, unsigned int attachment, return NULL; } - if (attachment == DRI2BufferFrontLeft) { - pixmap = get_drawable_pixmap(drawable); - pixmap->refcnt++; - } else { - unsigned int hint = 0; - - switch (attachment) { - case DRI2BufferDepth: - case DRI2BufferDepthStencil: - if (SUPPORTS_YTILING(intel)) - hint = INTEL_CREATE_PIXMAP_TILING_Y; - else - hint = INTEL_CREATE_PIXMAP_TILING_X; - break; - case DRI2BufferFakeFrontLeft: - case DRI2BufferFakeFrontRight: - case DRI2BufferBackLeft: - case DRI2BufferBackRight: - hint = INTEL_CREATE_PIXMAP_TILING_X; - break; - } + pixmap = NULL; + if (attachment == DRI2BufferFrontLeft) + pixmap = get_front_buffer(drawable); + if (pixmap == NULL) { + unsigned int hint = INTEL_CREATE_PIXMAP_DRI2; - if (!intel->tiling) - hint = 0; + if (intel->tiling & INTEL_TILING_3D) { + switch (attachment) { + case DRI2BufferDepth: + case DRI2BufferDepthStencil: + if (SUPPORTS_YTILING(intel)) { + hint |= INTEL_CREATE_PIXMAP_TILING_Y; + break; + } + case DRI2BufferAccum: + case DRI2BufferBackLeft: + case DRI2BufferBackRight: + case DRI2BufferFakeFrontLeft: + case DRI2BufferFakeFrontRight: + case DRI2BufferFrontLeft: + case DRI2BufferFrontRight: + hint |= INTEL_CREATE_PIXMAP_TILING_X; + break; + default: + free(privates); + free(buffer); + return NULL; + } + } pixmap = screen->CreatePixmap(screen, drawable->width, @@ -215,12 +350,16 @@ I830DRI2CreateBuffer(DrawablePtr drawable, unsigned int attachment, (format != 0) ? format : drawable->depth, hint); - if (pixmap == NULL) { + if (pixmap == NULL || intel_get_pixmap_bo(pixmap) == NULL) { + if (pixmap) + screen->DestroyPixmap(pixmap); free(privates); free(buffer); return NULL; } + if (attachment == DRI2BufferFrontLeft) + pixmap = fixup_shadow(drawable, pixmap); } buffer->attachment = attachment; @@ -233,8 +372,7 @@ I830DRI2CreateBuffer(DrawablePtr drawable, unsigned int attachment, privates->pixmap = pixmap; privates->attachment = attachment; - bo = i830_get_pixmap_bo(pixmap); - if (bo == NULL || dri_bo_flink(bo, &buffer->name) != 0) { + if ((buffer->name = pixmap_flink(pixmap)) == 0) { /* failed to name buffer */ screen->DestroyPixmap(pixmap); free(privates); @@ -271,17 +409,17 @@ I830DRI2DestroyBuffers(DrawablePtr drawable, DRI2BufferPtr buffers, int count) static void I830DRI2DestroyBuffer(DrawablePtr drawable, DRI2Buffer2Ptr buffer) { - if (buffer) { + if (buffer && buffer->driverPrivate) { I830DRI2BufferPrivatePtr private = buffer->driverPrivate; if (--private->refcnt == 0) { ScreenPtr screen = private->pixmap->drawable.pScreen; - screen->DestroyPixmap(private->pixmap); free(private); free(buffer); } - } + } else + free(buffer); } #endif @@ -304,9 +442,9 @@ I830DRI2CopyRegion(DrawablePtr drawable, RegionPtr pRegion, ScrnInfoPtr scrn = xf86Screens[screen->myNum]; intel_screen_private *intel = intel_get_screen_private(scrn); DrawablePtr src = (srcPrivate->attachment == DRI2BufferFrontLeft) - ? drawable : &srcPrivate->pixmap->drawable; + ? drawable : &srcPrivate->pixmap->drawable; DrawablePtr dst = (dstPrivate->attachment == DRI2BufferFrontLeft) - ? drawable : &dstPrivate->pixmap->drawable; + ? drawable : &dstPrivate->pixmap->drawable; RegionPtr pCopyClip; GCPtr gc; @@ -320,8 +458,9 @@ I830DRI2CopyRegion(DrawablePtr drawable, RegionPtr pRegion, ValidateGC(dst, gc); /* Wait for the scanline to be outside the region to be copied */ - if (pixmap_is_scanout(get_drawable_pixmap(dst)) - && intel->swapbuffers_wait) { + if (pixmap_is_scanout(get_drawable_pixmap(dst)) && + intel->swapbuffers_wait && + scrn->currentMode) { BoxPtr box; BoxRec crtcbox; int y1, y2; @@ -330,14 +469,14 @@ I830DRI2CopyRegion(DrawablePtr drawable, RegionPtr pRegion, Bool full_height = FALSE; box = REGION_EXTENTS(unused, gc->pCompositeClip); - crtc = i830_covering_crtc(scrn, box, NULL, &crtcbox); + crtc = intel_covering_crtc(scrn, box, NULL, &crtcbox); /* * Make sure the CRTC is valid and this is the real front * buffer */ if (crtc != NULL && !crtc->rotatedData) { - pipe = i830_crtc_to_pipe(crtc); + pipe = intel_crtc_to_pipe(crtc); /* * Make sure we don't wait for a scanline that will @@ -355,23 +494,29 @@ I830DRI2CopyRegion(DrawablePtr drawable, RegionPtr pRegion, * of extra time for the blitter to start up and * do its job for a full height blit */ - if (full_height && !IS_I965G(intel)) + if (full_height && INTEL_INFO(intel)->gen < 40) y2 -= 2; if (pipe == 0) { event = MI_WAIT_FOR_PIPEA_SCAN_LINE_WINDOW; load_scan_lines_pipe = MI_LOAD_SCAN_LINES_DISPLAY_PIPEA; - if (full_height && IS_I965G(intel)) + if (full_height && INTEL_INFO(intel)->gen >= 40) event = MI_WAIT_FOR_PIPEA_SVBLANK; } else { event = MI_WAIT_FOR_PIPEB_SCAN_LINE_WINDOW; load_scan_lines_pipe = MI_LOAD_SCAN_LINES_DISPLAY_PIPEB; - if (full_height && IS_I965G(intel)) + if (full_height && INTEL_INFO(intel)->gen >= 40) event = MI_WAIT_FOR_PIPEB_SVBLANK; } + if (crtc->mode.Flags & V_INTERLACE) { + /* DSL count field lines */ + y1 /= 2; + y2 /= 2; + } + BEGIN_BATCH(5); /* * The documentation says that the LOAD_SCAN_LINES @@ -379,54 +524,62 @@ I830DRI2CopyRegion(DrawablePtr drawable, RegionPtr pRegion, */ OUT_BATCH(MI_LOAD_SCAN_LINES_INCL | load_scan_lines_pipe); - OUT_BATCH((y1 << 16) | y2); + OUT_BATCH((y1 << 16) | (y2-1)); OUT_BATCH(MI_LOAD_SCAN_LINES_INCL | load_scan_lines_pipe); - OUT_BATCH((y1 << 16) | y2); + OUT_BATCH((y1 << 16) | (y2-1)); OUT_BATCH(MI_WAIT_FOR_EVENT | event); ADVANCE_BATCH(); } } - (*gc->ops->CopyArea) (src, dst, - gc, - 0, 0, - drawable->width, drawable->height, - 0, 0); - FreeScratchGC(gc); + /* It's important that this copy gets submitted before the + * direct rendering client submits rendering for the next + * frame, but we don't actually need to submit right now. The + * client will wait for the DRI2CopyRegion reply or the swap + * buffer event before rendering, and we'll hit the flush + * callback chain before those messages are sent. We submit + * our batch buffers from the flush callback chain so we know + * that will happen before the client tries to render + * again. */ + + /* Re-enable 2D acceleration... */ + if (intel->use_shadow) { + struct intel_pixmap *src_pixmap, *dst_pixmap; + + src_pixmap = intel_get_pixmap_private(get_drawable_pixmap(src)); + if (src_pixmap) { + src_pixmap->offscreen = 1; + src_pixmap->busy = 1; + } - /* Emit a flush of the rendering cache, or on the 965 and beyond - * rendering results may not hit the framebuffer until significantly - * later. - * - * We can't rely on getting into the block handler before the DRI - * client gets to run again so flush now. - */ - intel_batch_submit(scrn, TRUE); - drmCommandNone(intel->drmSubFD, DRM_I915_GEM_THROTTLE); + dst_pixmap = intel_get_pixmap_private(get_drawable_pixmap(dst)); + if (dst_pixmap) { + dst_pixmap->offscreen = 1; + dst_pixmap->busy = 1; + } + + gc->ops->CopyArea(src, dst, gc, + 0, 0, + drawable->width, drawable->height, + 0, 0); + + /* and restore 2D/3D coherency */ + if (src_pixmap) + src_pixmap->offscreen = 0; + if (dst_pixmap) + dst_pixmap->offscreen = 0; + } else { + gc->ops->CopyArea(src, dst, gc, + 0, 0, + drawable->width, drawable->height, + 0, 0); + } + FreeScratchGC(gc); } #if DRI2INFOREC_VERSION >= 4 -enum DRI2FrameEventType { - DRI2_SWAP, - DRI2_FLIP, - DRI2_WAITMSC, -}; - -typedef struct _DRI2FrameEvent { - XID drawable_id; - ClientPtr client; - enum DRI2FrameEventType type; - int frame; - - /* for swaps & flips only */ - DRI2SwapEventPtr event_complete; - void *event_data; - DRI2BufferPtr front; - DRI2BufferPtr back; -} DRI2FrameEventRec, *DRI2FrameEventPtr; - static int I830DRI2DrawablePipe(DrawablePtr pDraw) { @@ -441,11 +594,11 @@ I830DRI2DrawablePipe(DrawablePtr pDraw) box.x2 = box.x1 + pDraw->width; box.y2 = box.y1 + pDraw->height; - crtc = i830_covering_crtc(pScrn, &box, NULL, &crtcbox); + crtc = intel_covering_crtc(pScrn, &box, NULL, &crtcbox); /* Make sure the CRTC is valid and this is the real front buffer */ if (crtc != NULL && !crtc->rotatedData) - pipe = i830_crtc_to_pipe(crtc); + pipe = intel_crtc_to_pipe(crtc); return pipe; } @@ -469,24 +622,58 @@ I830DRI2ExchangeBuffers(DrawablePtr draw, DRI2BufferPtr front, back->name = tmp; /* Swap pixmap bos */ - front_intel = i830_get_pixmap_intel(front_priv->pixmap); - back_intel = i830_get_pixmap_intel(back_priv->pixmap); - i830_set_pixmap_intel(front_priv->pixmap, back_intel); - i830_set_pixmap_intel(back_priv->pixmap, front_intel); /* should be screen */ + front_intel = intel_get_pixmap_private(front_priv->pixmap); + back_intel = intel_get_pixmap_private(back_priv->pixmap); + intel_set_pixmap_private(front_priv->pixmap, back_intel); + intel_set_pixmap_private(back_priv->pixmap, front_intel); /* should be screen */ /* Do we need to update the Screen? */ screen = draw->pScreen; intel = intel_get_screen_private(xf86Screens[screen->myNum]); - if (front_intel->bo == intel->front_buffer->bo) { - dri_bo_unreference (intel->front_buffer->bo); - intel->front_buffer->bo = back_intel->bo; - dri_bo_reference (intel->front_buffer->bo); - i830_set_pixmap_intel(screen->GetScreenPixmap(screen), - back_intel); + if (front_intel->bo == intel->front_buffer) { + dri_bo_unreference (intel->front_buffer); + intel->front_buffer = back_intel->bo; + dri_bo_reference (intel->front_buffer); + intel_set_pixmap_private(screen->GetScreenPixmap(screen), + back_intel); + back_intel->busy = 1; + front_intel->busy = -1; } } #ifdef notyet +static Bool +can_exchange(DRI2BufferPtr front, DRI2BufferPtr back) +{ + I830DRI2BufferPrivatePtr front_priv = front->driverPrivate; + I830DRI2BufferPrivatePtr back_priv = back->driverPrivate; + PixmapPtr front_pixmap = front_priv->pixmap; + PixmapPtr back_pixmap = back_priv->pixmap; + struct intel_pixmap *front_intel = intel_get_pixmap_private(front_pixmap); + struct intel_pixmap *back_intel = intel_get_pixmap_private(back_pixmap); + + if (front_pixmap->drawable.width != back_pixmap->drawable.width) + return FALSE; + + if (front_pixmap->drawable.height != back_pixmap->drawable.height) + return FALSE; + + /* XXX should we be checking depth instead of bpp? */ +#if 0 + if (front_pixmap->drawable.depth != back_pixmap->drawable.depth) + return FALSE; +#else + if (front_pixmap->drawable.bitsPerPixel != back_pixmap->drawable.bitsPerPixel) + return FALSE; +#endif + + /* prevent an implicit tiling mode change */ + if (front_intel->tiling != back_intel->tiling) + return FALSE; + + return TRUE; +} + void I830DRI2FrameEventHandler(unsigned int frame, unsigned int tv_sec, unsigned int tv_usec, void *event_data) { @@ -804,8 +991,14 @@ I830DRI2GetMSC(DrawablePtr draw, CARD64 *ust, CARD64 *msc) ret = drmWaitVBlank(intel->drmSubFD, &vbl); if (ret) { - xf86DrvMsg(scrn->scrnIndex, X_WARNING, - "get vblank counter failed: %s\n", strerror(errno)); + static int limit = 5; + if (limit) { + xf86DrvMsg(scrn->scrnIndex, X_WARNING, + "%s:%d get vblank counter failed: %s\n", + __FUNCTION__, __LINE__, + strerror(errno)); + limit--; + } return FALSE; } @@ -858,8 +1051,14 @@ I830DRI2ScheduleWaitMSC(ClientPtr client, DrawablePtr draw, CARD64 target_msc, vbl.request.sequence = 0; ret = drmWaitVBlank(intel->drmSubFD, &vbl); if (ret) { - xf86DrvMsg(scrn->scrnIndex, X_WARNING, - "get vblank counter failed: %s\n", strerror(errno)); + static int limit = 5; + if (limit) { + xf86DrvMsg(scrn->scrnIndex, X_WARNING, + "%s:%d get vblank counter failed: %s\n", + __FUNCTION__, __LINE__, + strerror(errno)); + limit--; + } goto out_complete; } @@ -886,8 +1085,14 @@ I830DRI2ScheduleWaitMSC(ClientPtr client, DrawablePtr draw, CARD64 target_msc, vbl.request.signal = (unsigned long)wait_info; ret = drmWaitVBlank(intel->drmSubFD, &vbl); if (ret) { - xf86DrvMsg(scrn->scrnIndex, X_WARNING, - "get vblank counter failed: %s\n", strerror(errno)); + static int limit = 5; + if (limit) { + xf86DrvMsg(scrn->scrnIndex, X_WARNING, + "%s:%d get vblank counter failed: %s\n", + __FUNCTION__, __LINE__, + strerror(errno)); + limit--; + } goto out_complete; } @@ -919,8 +1124,14 @@ I830DRI2ScheduleWaitMSC(ClientPtr client, DrawablePtr draw, CARD64 target_msc, vbl.request.signal = (unsigned long)wait_info; ret = drmWaitVBlank(intel->drmSubFD, &vbl); if (ret) { - xf86DrvMsg(scrn->scrnIndex, X_WARNING, - "get vblank counter failed: %s\n", strerror(errno)); + static int limit = 5; + if (limit) { + xf86DrvMsg(scrn->scrnIndex, X_WARNING, + "%s:%d get vblank counter failed: %s\n", + __FUNCTION__, __LINE__, + strerror(errno)); + limit--; + } goto out_complete; } @@ -964,7 +1175,7 @@ Bool I830DRI2ScreenInit(ScreenPtr screen) intel->deviceName = drmGetDeviceNameFromFd(intel->drmSubFD); memset(&info, '\0', sizeof(info)); info.fd = intel->drmSubFD; - info.driverName = IS_I965G(intel) ? "i965" : "i915"; + info.driverName = INTEL_INFO(intel)->gen < 40 ? "i915" : "i965"; info.deviceName = intel->deviceName; #if DRI2INFOREC_VERSION >= 3 diff --git a/driver/xf86-video-intel/src/i830_driver.c b/driver/xf86-video-intel/src/intel_driver.c index 05664533c..5d9980ebf 100644 --- a/driver/xf86-video-intel/src/i830_driver.c +++ b/driver/xf86-video-intel/src/intel_driver.c @@ -67,19 +67,19 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #include "xf86xv.h" #include <X11/extensions/Xv.h> #include "shadow.h" -#include "i830.h" +#include "intel.h" +#include "i830_reg.h" #include "i830_display.h" #include "i830_bios.h" -#include "i830_video.h" -#if HAVE_SYS_MMAN_H && HAVE_MPROTECT -#include <sys/mman.h> -#endif +#include "intel_video.h" #ifdef INTEL_XVMC #define _INTEL_XVMC_SERVER_ -#include "i830_hwmc.h" +#include "intel_hwmc.h" #endif +#include "legacy/legacy.h" + #include <sys/ioctl.h> #include "i915_drm.h" #include <xf86drmMode.h> @@ -89,72 +89,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #define NB_OF(x) (sizeof (x) / sizeof (*x)) /* *INDENT-OFF* */ -static SymTabRec I830Chipsets[] = { - {PCI_CHIP_I830_M, "i830"}, - {PCI_CHIP_845_G, "845G"}, - {PCI_CHIP_I855_GM, "852GM/855GM"}, - {PCI_CHIP_I865_G, "865G"}, - {PCI_CHIP_I915_G, "915G"}, - {PCI_CHIP_E7221_G, "E7221 (i915)"}, - {PCI_CHIP_I915_GM, "915GM"}, - {PCI_CHIP_I945_G, "945G"}, - {PCI_CHIP_I945_GM, "945GM"}, - {PCI_CHIP_I945_GME, "945GME"}, - {PCI_CHIP_IGD_GM, "Pineview GM"}, - {PCI_CHIP_IGD_G, "Pineview G"}, - {PCI_CHIP_I965_G, "965G"}, - {PCI_CHIP_G35_G, "G35"}, - {PCI_CHIP_I965_Q, "965Q"}, - {PCI_CHIP_I946_GZ, "946GZ"}, - {PCI_CHIP_I965_GM, "965GM"}, - {PCI_CHIP_I965_GME, "965GME/GLE"}, - {PCI_CHIP_G33_G, "G33"}, - {PCI_CHIP_Q35_G, "Q35"}, - {PCI_CHIP_Q33_G, "Q33"}, - {PCI_CHIP_GM45_GM, "GM45"}, - {PCI_CHIP_IGD_E_G, "4 Series"}, - {PCI_CHIP_G45_G, "G45/G43"}, - {PCI_CHIP_Q45_G, "Q45/Q43"}, - {PCI_CHIP_G41_G, "G41"}, - {PCI_CHIP_B43_G, "B43"}, - {PCI_CHIP_IGDNG_D_G, "Clarkdale"}, - {PCI_CHIP_IGDNG_M_G, "Arrandale"}, - {-1, NULL} -}; - -static PciChipsets I830PciChipsets[] = { - {PCI_CHIP_I830_M, PCI_CHIP_I830_M, NULL}, - {PCI_CHIP_845_G, PCI_CHIP_845_G, NULL}, - {PCI_CHIP_I855_GM, PCI_CHIP_I855_GM, NULL}, - {PCI_CHIP_I865_G, PCI_CHIP_I865_G, NULL}, - {PCI_CHIP_I915_G, PCI_CHIP_I915_G, NULL}, - {PCI_CHIP_E7221_G, PCI_CHIP_E7221_G, NULL}, - {PCI_CHIP_I915_GM, PCI_CHIP_I915_GM, NULL}, - {PCI_CHIP_I945_G, PCI_CHIP_I945_G, NULL}, - {PCI_CHIP_I945_GM, PCI_CHIP_I945_GM, NULL}, - {PCI_CHIP_I945_GME, PCI_CHIP_I945_GME, NULL}, - {PCI_CHIP_IGD_GM, PCI_CHIP_IGD_GM, NULL}, - {PCI_CHIP_IGD_G, PCI_CHIP_IGD_G, NULL}, - {PCI_CHIP_I965_G, PCI_CHIP_I965_G, NULL}, - {PCI_CHIP_G35_G, PCI_CHIP_G35_G, NULL}, - {PCI_CHIP_I965_Q, PCI_CHIP_I965_Q, NULL}, - {PCI_CHIP_I946_GZ, PCI_CHIP_I946_GZ, NULL}, - {PCI_CHIP_I965_GM, PCI_CHIP_I965_GM, NULL}, - {PCI_CHIP_I965_GME, PCI_CHIP_I965_GME, NULL}, - {PCI_CHIP_G33_G, PCI_CHIP_G33_G, NULL}, - {PCI_CHIP_Q35_G, PCI_CHIP_Q35_G, NULL}, - {PCI_CHIP_Q33_G, PCI_CHIP_Q33_G, NULL}, - {PCI_CHIP_GM45_GM, PCI_CHIP_GM45_GM, NULL}, - {PCI_CHIP_IGD_E_G, PCI_CHIP_IGD_E_G, NULL}, - {PCI_CHIP_G45_G, PCI_CHIP_G45_G, NULL}, - {PCI_CHIP_Q45_G, PCI_CHIP_Q45_G, NULL}, - {PCI_CHIP_G41_G, PCI_CHIP_G41_G, NULL}, - {PCI_CHIP_B43_G, PCI_CHIP_B43_G, NULL}, - {PCI_CHIP_IGDNG_D_G, PCI_CHIP_IGDNG_D_G, NULL}, - {PCI_CHIP_IGDNG_M_G, PCI_CHIP_IGDNG_M_G, NULL}, - {-1, -1, NULL} -}; - /* * Note: "ColorKey" is provided for compatibility with the i810 driver. * However, the correct option name is "VideoKey". "ColorKey" usually @@ -169,7 +103,9 @@ typedef enum { OPTION_FALLBACKDEBUG, OPTION_LVDS24BITMODE, OPTION_FBC, - OPTION_TILING, + OPTION_TILING_FB, + OPTION_TILING_2D, + OPTION_SHADOW, OPTION_SWAPBUFFERS_WAIT, OPTION_LVDSFIXEDMODE, OPTION_FORCEENABLEPIPEA, @@ -190,7 +126,9 @@ static OptionInfoRec I830Options[] = { {OPTION_FALLBACKDEBUG, "FallbackDebug", OPTV_BOOLEAN, {0}, FALSE}, {OPTION_LVDS24BITMODE, "LVDS24Bit", OPTV_BOOLEAN, {0}, FALSE}, {OPTION_FBC, "FramebufferCompression", OPTV_BOOLEAN, {0}, TRUE}, - {OPTION_TILING, "Tiling", OPTV_BOOLEAN, {0}, TRUE}, + {OPTION_TILING_2D, "Tiling", OPTV_BOOLEAN, {0}, TRUE}, + {OPTION_TILING_FB, "LinearFramebuffer", OPTV_BOOLEAN, {0}, FALSE}, + {OPTION_SHADOW, "Shadow", OPTV_BOOLEAN, {0}, FALSE}, {OPTION_SWAPBUFFERS_WAIT, "SwapbuffersWait", OPTV_BOOLEAN, {0}, TRUE}, {OPTION_LVDSFIXEDMODE, "LVDSFixedMode", OPTV_BOOLEAN, {0}, FALSE}, {OPTION_FORCEENABLEPIPEA, "ForceEnablePipeA", OPTV_BOOLEAN, {0}, FALSE}, @@ -232,15 +170,9 @@ I830DPRINTF(const char *filename, int line, const char *function, #endif /* #ifdef I830DEBUG */ /* Export I830 options to i830 driver where necessary */ -const OptionInfoRec *I830AvailableOptions(int chipid, int busid) +const OptionInfoRec *intel_uxa_available_options(int chipid, int busid) { - int i; - - for (i = 0; I830PciChipsets[i].PCIid > 0; i++) { - if (chipid == I830PciChipsets[i].PCIid) - return I830Options; - } - return NULL; + return I830Options; } static Bool I830GetRec(ScrnInfoPtr scrn) @@ -612,9 +544,7 @@ static Bool i830CreateScreenResources(ScreenPtr screen) if (!(*screen->CreateScreenResources) (screen)) return FALSE; - i830_uxa_create_screen_resources(screen); - - return TRUE; + return intel_uxa_create_screen_resources(screen); } static int i830_output_clones (ScrnInfoPtr scrn, int type_mask) @@ -817,110 +747,64 @@ static void PreInitCleanup(ScrnInfoPtr scrn) I830FreeRec(scrn); } -/* - * Adjust *width to allow for tiling if possible - */ -Bool i830_tiled_width(intel_screen_private *intel, int *width, int cpp) -{ - Bool tiled = FALSE; - - /* - * Adjust the display width to allow for front buffer tiling if possible - */ - if (intel->tiling) { - if (IS_I965G(intel)) { - int tile_pixels = 512 / cpp; - *width = (*width + tile_pixels - 1) & - ~(tile_pixels - 1); - tiled = TRUE; - } else { - /* Good pitches to allow tiling. Don't care about pitches < 1024 - * pixels. - */ - static const int pitches[] = { - 1024, - 2048, - 4096, - 8192, - 0 - }; - int pitch; - int i; - - pitch = *width * cpp; - for (i = 0; pitches[i] != 0; i++) { - if (pitches[i] >= pitch) { - *width = pitches[i] / cpp; - tiled = TRUE; - break; - } - } - } - } - return tiled; -} - static Bool i830_xf86crtc_resize(ScrnInfoPtr scrn, int width, int height) { -#ifdef DRI2 intel_screen_private *intel = intel_get_screen_private(scrn); - int old_width = scrn->displayWidth; -#endif - int old_x = scrn->virtualX; - int old_y = scrn->virtualY; + int old_width, old_height, old_pitch; + drm_intel_bo *old_front; + unsigned long pitch; + uint32_t tiling; - if (old_x == width && old_y == height) + if (scrn->virtualX == width && scrn->virtualY == height) return TRUE; + old_width = scrn->virtualX; + old_height = scrn->virtualY; + old_pitch = scrn->displayWidth; + old_front = intel->front_buffer; + + intel->front_buffer = intel_allocate_framebuffer(scrn, + width, height, + intel->cpp, + &pitch, + &tiling); + if (!intel->front_buffer) + goto fail; + + intel->front_pitch = pitch; + intel->front_tiling = tiling; + scrn->virtualX = width; scrn->virtualY = height; -#ifdef DRI2 - if (intel->front_buffer) { - i830_memory *new_front, *old_front; - Bool tiled; - ScreenPtr screen = screenInfo.screens[scrn->scrnIndex]; - scrn->displayWidth = i830_pad_drawable_width(width); - tiled = i830_tiled_width(intel, &scrn->displayWidth, intel->cpp); - xf86DrvMsg(scrn->scrnIndex, X_INFO, - "Allocate new frame buffer %dx%d stride %d\n", width, - height, scrn->displayWidth); - intel_sync(scrn); - i830WaitForVblank(scrn); - new_front = i830_allocate_framebuffer(scrn); - if (!new_front) { - scrn->virtualX = old_x; - scrn->virtualY = old_y; - scrn->displayWidth = old_width; - return FALSE; - } - old_front = intel->front_buffer; - intel->front_buffer = new_front; - i830_set_pixmap_bo(screen->GetScreenPixmap(screen), - new_front->bo); - scrn->fbOffset = intel->front_buffer->offset; - - screen->ModifyPixmapHeader(screen->GetScreenPixmap(screen), - width, height, -1, -1, - scrn->displayWidth * intel->cpp, - intel->FbBase + scrn->fbOffset); - - /* ick. xf86EnableDisableFBAccess smashes the screen pixmap devPrivate, - * so update the value it uses - */ -#if XORG_VERSION_CURRENT < XORG_VERSION_NUMERIC(1,9,99,1,0) - scrn->pixmapPrivate.ptr = intel->FbBase + scrn->fbOffset; -#endif - xf86DrvMsg(scrn->scrnIndex, X_INFO, - "New front buffer at 0x%lx\n", - intel->front_buffer->offset); - i830_set_new_crtc_bo(scrn); - intel_sync(scrn); - i830WaitForVblank(scrn); - i830_free_memory(scrn, old_front); + intel_sync(scrn); + i830WaitForVblank(scrn); + + xf86DrvMsg(scrn->scrnIndex, X_INFO, + "New front buffer at 0x%lx\n", + intel->front_buffer->offset); + i830_set_new_crtc_bo(scrn); + intel_sync(scrn); + i830WaitForVblank(scrn); + + intel_uxa_create_screen_resources(scrn->pScreen); + + if (old_front) { + /* if we own the vt, don't forget to unpin */ + if (scrn->vtSema) + (void)dri_bo_unpin(old_front); + drm_intel_bo_unreference(old_front); } -#endif + return TRUE; + +fail: + intel->front_buffer = old_front; + scrn->virtualX = old_width; + scrn->virtualY = old_height; + scrn->displayWidth = old_pitch; + + return FALSE; } static const xf86CrtcConfigFuncsRec i830_xf86crtc_config_funcs = { @@ -960,175 +844,49 @@ i830SetHotkeyControl(ScrnInfoPtr scrn, int mode) * DRM mode setting Linux only at this point... later on we could * add a wrapper here. */ -static Bool i830_kernel_mode_enabled(ScrnInfoPtr scrn) +static Bool intel_kernel_mode_enabled(ScrnInfoPtr scrn) { - struct pci_device *PciInfo; - EntityInfoPtr pEnt; - char *busIdString; + struct pci_device *dev; + char id[20]; int ret; - pEnt = xf86GetEntityInfo(scrn->entityList[0]); - PciInfo = xf86GetPciInfoForEntity(pEnt->index); - - if (!xf86LoaderCheckSymbol("DRICreatePCIBusID")) - return FALSE; + dev = xf86GetPciInfoForEntity(xf86GetEntityInfo(scrn->entityList[0])->index); + snprintf(id, sizeof(id), + "pci:%04x:%02x:%02x.%d", + dev->domain, dev->bus, dev->dev, dev->func); - busIdString = DRICreatePCIBusID(PciInfo); - - ret = drmCheckModesettingSupported(busIdString); + ret = drmCheckModesettingSupported(id); if (ret) { if (xf86LoadKernelModule("i915")) - ret = drmCheckModesettingSupported(busIdString); + ret = drmCheckModesettingSupported(id); } /* Be nice to the user and load fbcon too */ if (!ret) (void)xf86LoadKernelModule("fbcon"); - free(busIdString); - if (ret) - return FALSE; - return TRUE; + return ret == 0; } -static Bool i830_detect_chipset(ScrnInfoPtr scrn) +static Bool intel_check_chipset_option(ScrnInfoPtr scrn) { intel_screen_private *intel = intel_get_screen_private(scrn); MessageType from = X_PROBED; - const char *chipname; - uint32_t capid; int fb_bar, mmio_bar; - /* We have to use PIO to probe, because we haven't mapped yet. */ if (!intel->use_drm_mode) I830SetPIOAccess(intel); - switch (DEVICE_ID(intel->PciInfo)) { - case PCI_CHIP_I830_M: - chipname = "830M"; - break; - case PCI_CHIP_845_G: - chipname = "845G"; - break; - case PCI_CHIP_I855_GM: - /* Check capid register to find the chipset variant */ - pci_device_cfg_read_u32(intel->PciInfo, &capid, I85X_CAPID); - intel->variant = - (capid >> I85X_VARIANT_SHIFT) & I85X_VARIANT_MASK; - switch (intel->variant) { - case I855_GM: - chipname = "855GM"; - break; - case I855_GME: - chipname = "855GME"; - break; - case I852_GM: - chipname = "852GM"; - break; - case I852_GME: - chipname = "852GME"; - break; - default: - xf86DrvMsg(scrn->scrnIndex, X_INFO, - "Unknown 852GM/855GM variant: 0x%x)\n", - intel->variant); - chipname = "852GM/855GM (unknown variant)"; - break; - } - break; - case PCI_CHIP_I865_G: - chipname = "865G"; - break; - case PCI_CHIP_I915_G: - chipname = "915G"; - break; - case PCI_CHIP_E7221_G: - chipname = "E7221 (i915)"; - break; - case PCI_CHIP_I915_GM: - chipname = "915GM"; - break; - case PCI_CHIP_I945_G: - chipname = "945G"; - break; - case PCI_CHIP_I945_GM: - chipname = "945GM"; - break; - case PCI_CHIP_I945_GME: - chipname = "945GME"; - break; - case PCI_CHIP_IGD_GM: - chipname = "Pineview GM"; - break; - case PCI_CHIP_IGD_G: - chipname = "Pineview G"; - break; - case PCI_CHIP_I965_G: - chipname = "965G"; - break; - case PCI_CHIP_G35_G: - chipname = "G35"; - break; - case PCI_CHIP_I965_Q: - chipname = "965Q"; - break; - case PCI_CHIP_I946_GZ: - chipname = "946GZ"; - break; - case PCI_CHIP_I965_GM: - chipname = "965GM"; - break; - case PCI_CHIP_I965_GME: - chipname = "965GME/GLE"; - break; - case PCI_CHIP_G33_G: - chipname = "G33"; - break; - case PCI_CHIP_Q35_G: - chipname = "Q35"; - break; - case PCI_CHIP_Q33_G: - chipname = "Q33"; - break; - case PCI_CHIP_GM45_GM: - chipname = "GM45"; - break; - case PCI_CHIP_IGD_E_G: - chipname = "4 Series"; - break; - case PCI_CHIP_G45_G: - chipname = "G45/G43"; - break; - case PCI_CHIP_Q45_G: - chipname = "Q45/Q43"; - break; - case PCI_CHIP_G41_G: - chipname = "G41"; - break; - case PCI_CHIP_B43_G: - chipname = "B43"; - break; - case PCI_CHIP_IGDNG_D_G: - chipname = "Clarkdale"; - break; - case PCI_CHIP_IGDNG_M_G: - chipname = "Arrandale"; - break; - default: - chipname = "unknown chipset"; - break; - } - - xf86DrvMsg(scrn->scrnIndex, X_INFO, - "Integrated Graphics Chipset: Intel(R) %s\n", chipname); + intel_detect_chipset(scrn, + intel->PciInfo, + &intel->chipset); /* Set the Chipset and ChipRev, allowing config file entries to override. */ if (intel->pEnt->device->chipset && *intel->pEnt->device->chipset) { scrn->chipset = intel->pEnt->device->chipset; from = X_CONFIG; } else if (intel->pEnt->device->chipID >= 0) { - scrn->chipset = (char *)xf86TokenToString(I830Chipsets, - intel->pEnt->device-> - chipID); + scrn->chipset = (char *)xf86TokenToString(intel_chipsets, + intel->pEnt->device->chipID); from = X_CONFIG; xf86DrvMsg(scrn->scrnIndex, X_CONFIG, "ChipID override: 0x%04X\n", @@ -1136,9 +894,8 @@ static Bool i830_detect_chipset(ScrnInfoPtr scrn) DEVICE_ID(intel->PciInfo) = intel->pEnt->device->chipID; } else { from = X_PROBED; - scrn->chipset = (char *)xf86TokenToString(I830Chipsets, - DEVICE_ID(intel-> - PciInfo)); + scrn->chipset = (char *)xf86TokenToString(intel_chipsets, + DEVICE_ID(intel->PciInfo)); } if (intel->pEnt->device->chipRev >= 0) { @@ -1329,17 +1086,17 @@ I830PreInitCrtcConfig(ScrnInfoPtr scrn) xf86CrtcSetSizeRange (scrn, 320, 200, max_width, max_height); } -static void i830_check_dri_option(ScrnInfoPtr scrn) +static void intel_check_dri_option(ScrnInfoPtr scrn) { intel_screen_private *intel = intel_get_screen_private(scrn); intel->directRenderingType = DRI_NONE; if (!xf86ReturnOptValBool(intel->Options, OPTION_DRI, TRUE)) intel->directRenderingType = DRI_DISABLED; - if (scrn->depth != 16 && scrn->depth != 24) { + if (scrn->depth != 16 && scrn->depth != 24 && scrn->depth != 30) { xf86DrvMsg(scrn->scrnIndex, X_CONFIG, "DRI is disabled because it " - "runs only at depths 16 and 24.\n"); + "runs only at depths 16, 24, and 30.\n"); intel->directRenderingType = DRI_DISABLED; } } @@ -1400,39 +1157,32 @@ static Bool i830_user_modesetting_init(ScrnInfoPtr scrn) #ifdef notyet intel->event_context.version = DRM_EVENT_CONTEXT_VERSION; intel->event_context.vblank_handler = drm_vblank_handler; - AddGeneralSocket(intel->drmSubFD); - RegisterBlockAndWakeupHandlers((BlockHandlerProcPtr)NoopDDA, - drm_wakeup_handler, intel); #endif return TRUE; } -static Bool i830_open_drm_master(ScrnInfoPtr scrn) +static Bool intel_open_drm_master(ScrnInfoPtr scrn) { intel_screen_private *intel = intel_get_screen_private(scrn); struct pci_device *dev = intel->PciInfo; - char *busid; drmSetVersion sv; struct drm_i915_getparam gp; int err, has_gem; + char busid[20]; - /* We wish we had asprintf, but all we get is XNFprintf. */ - busid = XNFprintf("pci:%04x:%02x:%02x.%d", - dev->domain, dev->bus, dev->dev, dev->func); + snprintf(busid, sizeof(busid), "pci:%04x:%02x:%02x.%d", + dev->domain, dev->bus, dev->dev, dev->func); intel->drmSubFD = drmOpen("i915", busid); if (intel->drmSubFD == -1) { xf86DrvMsg(scrn->scrnIndex, X_ERROR, "[drm] Failed to open DRM device for %s: %s\n", busid, strerror(errno)); - free(busid); return FALSE; } - free(busid); - /* Check that what we opened was a master or a master-capable FD, * by setting the version of the interface we'll use to talk to it. * (see DRIOpenDRMMaster() in DRI1) @@ -1466,7 +1216,7 @@ static Bool i830_open_drm_master(ScrnInfoPtr scrn) return TRUE; } -static void i830_close_drm_master(ScrnInfoPtr scrn) +static void intel_close_drm_master(ScrnInfoPtr scrn) { intel_screen_private *intel = intel_get_screen_private(scrn); if (intel && intel->drmSubFD > 0) { @@ -1475,6 +1225,29 @@ static void i830_close_drm_master(ScrnInfoPtr scrn) } } +void intel_init_bufmgr(ScrnInfoPtr scrn) +{ + intel_screen_private *intel = intel_get_screen_private(scrn); + int batch_size; + + if (intel->bufmgr) + return; + + batch_size = 4096 * 4; + + /* The 865 has issues with larger-than-page-sized batch buffers. */ + if (IS_I865G(intel)) + batch_size = 4096; + + intel->bufmgr = drm_intel_bufmgr_gem_init(intel->drmSubFD, batch_size); + drm_intel_bufmgr_gem_enable_reuse(intel->bufmgr); + drm_intel_bufmgr_gem_enable_fenced_relocs(intel->bufmgr); + + list_init(&intel->batch_pixmaps); + list_init(&intel->flush_pixmaps); + list_init(&intel->in_flight); +} + static Bool I830DrmModeInit(ScrnInfoPtr scrn) { intel_screen_private *intel = intel_get_screen_private(scrn); @@ -1486,7 +1259,7 @@ static Bool I830DrmModeInit(ScrnInfoPtr scrn) return FALSE; } - i830_init_bufmgr(scrn); + intel_init_bufmgr(scrn); return TRUE; } @@ -1516,6 +1289,67 @@ static void I830XvInit(ScrnInfoPtr scrn) intel->colorKey); } +static Bool has_kernel_flush(struct intel_screen_private *intel) +{ + drm_i915_getparam_t gp; + int value; + + /* The BLT ring was introduced at the same time as the + * automatic flush for the busy-ioctl. + */ + + gp.value = &value; + gp.param = I915_PARAM_HAS_BLT; + if (drmIoctl(intel->drmSubFD, DRM_IOCTL_I915_GETPARAM, &gp)) + return FALSE; + + return value; +} + +static Bool can_accelerate_blt(struct intel_screen_private *intel) +{ + if (0 && (IS_I830(intel) || IS_845G(intel))) { + /* These pair of i8xx chipsets have a crippling erratum + * that prevents the use of a PTE entry by the BLT + * engine immediately following updating that + * entry in the GATT. + * + * As the BLT is fundamental to our 2D acceleration, + * and the workaround is lost in the midst of time, + * fallback. + * + * XXX disabled for release as causes regressions in GL. + */ + return FALSE; + } + + if (INTEL_INFO(intel)->gen >= 60) { + drm_i915_getparam_t gp; + int value; + + /* On Sandybridge we need the BLT in order to do anything since + * it so frequently used in the acceleration code paths. + */ + gp.value = &value; + gp.param = I915_PARAM_HAS_BLT; + if (drmIoctl(intel->drmSubFD, DRM_IOCTL_I915_GETPARAM, &gp)) + return FALSE; + } + + if (INTEL_INFO(intel)->gen == 60) { + struct pci_device *const device = intel->PciInfo; + + /* Sandybridge rev07 locks up easily, even with the + * BLT ring workaround in place. + * Thus use shadowfb by default. + */ + if (device->revision < 8) + return FALSE; + } + + return TRUE; +} + /** * This is called before ScreenInit to do any require probing of screen * configuration. @@ -1542,7 +1376,7 @@ static Bool I830PreInit(ScrnInfoPtr scrn, int flags) if (scrn->numEntities != 1) return FALSE; - drm_mode_setting = i830_kernel_mode_enabled(scrn); + drm_mode_setting = intel_kernel_mode_enabled(scrn); pEnt = xf86GetEntityInfo(scrn->entityList[0]); @@ -1556,6 +1390,7 @@ static Bool I830PreInit(ScrnInfoPtr scrn, int flags) intel = intel_get_screen_private(scrn); intel->SaveGeneration = -1; intel->pEnt = pEnt; + intel->scrn = scrn; intel->use_drm_mode = drm_mode_setting; if (!I830LoadSyms(scrn)) @@ -1575,7 +1410,7 @@ static Bool I830PreInit(ScrnInfoPtr scrn, int flags) intel->PciInfo = xf86GetPciInfoForEntity(intel->pEnt->index); - if (!i830_open_drm_master(scrn)) + if (!intel_open_drm_master(scrn)) xf86DrvMsg(scrn->scrnIndex, X_ERROR, "Failed to become DRM master.\n"); @@ -1593,6 +1428,7 @@ static Bool I830PreInit(ScrnInfoPtr scrn, int flags) case 15: case 16: case 24: + case 30: break; default: xf86DrvMsg(scrn->scrnIndex, X_ERROR, @@ -1612,15 +1448,13 @@ static Bool I830PreInit(ScrnInfoPtr scrn, int flags) intel->cpp = scrn->bitsPerPixel / 8; - intel->preinit = TRUE; - if (!I830GetEarlyOptions(scrn)) return FALSE; - if (!i830_detect_chipset(scrn)) + if (!intel_check_chipset_option(scrn)) return FALSE; - i830_check_dri_option(scrn); + intel_check_dri_option(scrn); if (intel->use_drm_mode) { if (!I830DrmModeInit(scrn)) @@ -1694,8 +1528,6 @@ static Bool I830PreInit(ScrnInfoPtr scrn, int flags) xf86LoadSubModule(scrn, "dri2"); } - intel->preinit = FALSE; - return TRUE; } @@ -1770,14 +1602,6 @@ static Bool SaveHWState(ScrnInfoPtr scrn) if (IS_IGDNG(intel)) return TRUE; - if (intel->fb_compression) { - intel->saveFBC_CFB_BASE = INREG(FBC_CFB_BASE); - intel->saveFBC_LL_BASE = INREG(FBC_LL_BASE); - intel->saveFBC_CONTROL2 = INREG(FBC_CONTROL2); - intel->saveFBC_CONTROL = INREG(FBC_CONTROL); - intel->saveFBC_FENCE_OFF = INREG(FBC_FENCE_OFF); - } - /* Save video mode information for native mode-setting. */ if (!DSPARB_HWCONTROL(intel)) intel->saveDSPARB = INREG(DSPARB); @@ -2113,14 +1937,6 @@ static Bool RestoreHWState(ScrnInfoPtr scrn) OUTREG(SWF31, intel->saveSWF[15]); OUTREG(SWF32, intel->saveSWF[16]); - if (intel->fb_compression) { - OUTREG(FBC_CFB_BASE, intel->saveFBC_CFB_BASE); - OUTREG(FBC_LL_BASE, intel->saveFBC_LL_BASE); - OUTREG(FBC_FENCE_OFF, intel->saveFBC_FENCE_OFF); - OUTREG(FBC_CONTROL2, intel->saveFBC_CONTROL2); - OUTREG(FBC_CONTROL, intel->saveFBC_CONTROL); - } - vgaHWRestore(scrn, vgaReg, VGA_SR_FONTS); vgaHWLock(hwp); @@ -2144,12 +1960,10 @@ void IntelEmitInvarientState(ScrnInfoPtr scrn) if (intel->last_3d != LAST_3D_OTHER) return; - if (!IS_I965G(intel)) { - if (IS_I9XX(intel)) - I915EmitInvarientState(scrn); - else - I830EmitInvarientState(scrn); - } + if (IS_GEN2(intel)) + I830EmitInvarientState(scrn); + else if IS_GEN3(intel) + I915EmitInvarientState(scrn); } static void @@ -2166,23 +1980,11 @@ I830BlockHandler(int i, pointer blockData, pointer pTimeout, pointer pReadmask) intel->BlockHandler = screen->BlockHandler; screen->BlockHandler = I830BlockHandler; - if (scrn->vtSema) { - /* Emit a flush of the rendering cache, or on the 965 and beyond - * rendering results may not hit the framebuffer until significantly - * later. - */ - intel_batch_submit(scrn, - intel->need_mi_flush || - !list_is_empty(&intel->flush_pixmaps)); - drmCommandNone(intel->drmSubFD, DRM_I915_GEM_THROTTLE); - } - - i830_uxa_block_handler(screen); - - I830VideoBlockHandler(i, blockData, pTimeout, pReadmask); + intel_uxa_block_handler(intel); + intel_video_block_handler(scrn); } -static void i830_fixup_mtrrs(ScrnInfoPtr scrn) +static void intel_fixup_mtrrs(ScrnInfoPtr scrn) { #ifdef HAS_MTRR_SUPPORT intel_screen_private *intel = intel_get_screen_private(scrn); @@ -2226,47 +2028,13 @@ static void i830_fixup_mtrrs(ScrnInfoPtr scrn) #endif } -static Bool i830_try_memory_allocation(ScrnInfoPtr scrn) -{ - intel_screen_private *intel = intel_get_screen_private(scrn); - Bool tiled = intel->tiling; - - xf86DrvMsg(scrn->scrnIndex, X_INFO, - "Attempting memory allocation with %stiled buffers.\n", - tiled ? "" : "un"); - - if (!i830_allocate_2d_memory(scrn)) - goto failed; - - if (IS_I965GM(intel) || IS_GM45(intel)) - if (!i830_allocate_pwrctx(scrn)) - goto failed; - xf86DrvMsg(scrn->scrnIndex, X_INFO, "%siled allocation successful.\n", - tiled ? "T" : "Unt"); - return TRUE; - -failed: - xf86DrvMsg(scrn->scrnIndex, X_INFO, "%siled allocation failed.\n", - tiled ? "T" : "Unt"); - return FALSE; -} - /* - * Try to allocate memory in several ways: - * 1) If direct rendering is enabled, try to allocate enough memory for tiled - * surfaces by rounding up the display width to a tileable one. - * 2) If that fails or the allocations themselves fail, try again with untiled - * allocations (if this works DRI will stay enabled). - * 3) And if all else fails, disable DRI and try just 2D allocations. - * 4) Give up and fail ScreenInit. + * Try to allocate memory for rendering */ static Bool i830_memory_init(ScrnInfoPtr scrn) { intel_screen_private *intel = intel_get_screen_private(scrn); - int savedDisplayWidth = scrn->displayWidth; - Bool tiled = FALSE; - tiled = i830_tiled_width(intel, &scrn->displayWidth, intel->cpp); /* Set up our video memory allocator for the chosen videoRam */ if (!i830_allocator_init(scrn, scrn->videoRam * KB(1))) { xf86DrvMsg(scrn->scrnIndex, X_ERROR, @@ -2279,54 +2047,16 @@ static Bool i830_memory_init(ScrnInfoPtr scrn) intel->pEnt->device->videoRam ? X_CONFIG : X_DEFAULT, "VideoRam: %d KB\n", scrn->videoRam); - /* Tiled first if we got a good displayWidth */ - if (tiled) { - if (i830_try_memory_allocation(scrn)) - return TRUE; - else { - i830_reset_allocations(scrn); - intel->tiling = FALSE; - } - } - - /* If tiling fails we have to disable FBC */ - scrn->displayWidth = savedDisplayWidth; - if (intel->fb_compression) - xf86DrvMsg(scrn->scrnIndex, X_WARNING, - "Couldn't allocate tiled memory, fb compression " - "disabled\n"); - intel->fb_compression = FALSE; - - if (i830_try_memory_allocation(scrn)) - return TRUE; - - return FALSE; -} - -void i830_init_bufmgr(ScrnInfoPtr scrn) -{ - intel_screen_private *intel = intel_get_screen_private(scrn); - int batch_size; - - if (intel->bufmgr) - return; - - batch_size = 4096 * 4; - - /* The 865 has issues with larger-than-page-sized batch buffers. */ - if (IS_I865G(intel)) - batch_size = 4096; - - intel->bufmgr = intel_bufmgr_gem_init(intel->drmSubFD, batch_size); - intel_bufmgr_gem_enable_reuse(intel->bufmgr); - drm_intel_bufmgr_gem_enable_fenced_relocs(intel->bufmgr); + if (!i830_allocate_2d_memory(scrn)) + return FALSE; - list_init(&intel->batch_pixmaps); - list_init(&intel->flush_pixmaps); - list_init(&intel->in_flight); + if (IS_I965GM(intel) || IS_GM45(intel)) + if (!i830_allocate_pwrctx(scrn)) + return FALSE; + return TRUE; } -Bool i830_crtc_on(xf86CrtcPtr crtc) +Bool intel_crtc_on(xf86CrtcPtr crtc) { ScrnInfoPtr scrn = crtc->scrn; xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(scrn); @@ -2335,6 +2065,9 @@ Bool i830_crtc_on(xf86CrtcPtr crtc) if (intel->use_drm_mode) { int i, active_outputs = 0; + if (!crtc->enabled) + return FALSE; + /* Kernel manages CRTC status based out output config */ for (i = 0; i < xf86_config->num_output; i++) { xf86OutputPtr output = xf86_config->output[i]; @@ -2349,13 +2082,16 @@ Bool i830_crtc_on(xf86CrtcPtr crtc) } else { I830CrtcPrivatePtr intel_crtc = crtc->driver_private; + if (!crtc->enabled) + return FALSE; + if (intel_crtc->dpms_mode == DPMSModeOn) return TRUE; return FALSE; } } -int i830_crtc_to_pipe(xf86CrtcPtr crtc) +int intel_crtc_to_pipe(xf86CrtcPtr crtc) { ScrnInfoPtr scrn = crtc->scrn; intel_screen_private *intel = intel_get_screen_private(scrn); @@ -2427,38 +2163,6 @@ I830AdjustMemory(ScreenPtr screen) } static void -I830SwapPipes(ScrnInfoPtr scrn) -{ - intel_screen_private *intel = intel_get_screen_private(scrn); - xf86CrtcConfigPtr config; - int c; - - config = XF86_CRTC_CONFIG_PTR(scrn); - - /* - * If an LVDS display is present, swap the plane/pipe mappings so we can - * use FBC on the builtin display. - * Note: 965+ chips can compress either plane, so we leave the mapping - * alone in that case. - * Also make sure the DRM can handle the swap. - */ - if (I830LVDSPresent(scrn) && !IS_I965GM(intel) && !IS_GM45(intel) && - !IS_IGDNG(intel)) { - xf86DrvMsg(scrn->scrnIndex, X_INFO, "adjusting plane->pipe " - "mappings to allow for framebuffer compression\n"); - for (c = 0; c < config->num_crtc; c++) { - xf86CrtcPtr crtc = config->crtc[c]; - I830CrtcPrivatePtr intel_crtc = crtc->driver_private; - - if (intel_crtc->pipe == 0) - intel_crtc->plane = 1; - else if (intel_crtc->pipe == 1) - intel_crtc->plane = 0; - } - } -} - -static void i830_disable_render_standby(ScrnInfoPtr scrn) { intel_screen_private *intel = intel_get_screen_private(scrn); @@ -2475,6 +2179,15 @@ i830_disable_render_standby(ScrnInfoPtr scrn) } } +static void +intel_flush_callback(CallbackListPtr *list, + pointer user_data, pointer call_data) +{ + ScrnInfoPtr scrn = user_data; + if (scrn->vtSema) + intel_batch_submit(scrn); +} + static Bool I830ScreenInit(int scrnIndex, ScreenPtr screen, int argc, char **argv) { @@ -2487,8 +2200,6 @@ I830ScreenInit(int scrnIndex, ScreenPtr screen, int argc, char **argv) if (!intel->use_drm_mode) hwp = VGAHWPTR(scrn); - scrn->displayWidth = i830_pad_drawable_width(scrn->virtualX); - /* * The "VideoRam" config file parameter specifies the maximum amount of * memory that will be used/allocated. When not present, we allow the @@ -2534,7 +2245,7 @@ I830ScreenInit(int scrnIndex, ScreenPtr screen, int argc, char **argv) if (intel->use_drm_mode) { struct pci_device *const device = intel->PciInfo; - int fb_bar = IS_I9XX(intel) ? 2 : 0; + int fb_bar = IS_GEN2(intel) ? 0 : 2; scrn->videoRam = device->regions[fb_bar].size / 1024; } else { @@ -2547,35 +2258,32 @@ I830ScreenInit(int scrnIndex, ScreenPtr screen, int argc, char **argv) intel->directRenderingType = DRI_DRI2; #endif + intel->force_fallback = FALSE; + intel->can_blt = can_accelerate_blt(intel); +#if 0 /* XXX oga */ + intel->has_kernel_flush = has_kernel_flush(intel); +#endif + intel->has_kernel_flush = TRUE; + intel->use_shadow = !intel->can_blt; + /* Enable tiling by default */ - intel->tiling = TRUE; + intel->tiling = INTEL_TILING_ALL; /* Allow user override if they set a value */ - if (xf86IsOptionSet(intel->Options, OPTION_TILING)) { - if (xf86ReturnOptValBool(intel->Options, OPTION_TILING, FALSE)) - intel->tiling = TRUE; - else - intel->tiling = FALSE; - } + if (!xf86ReturnOptValBool(intel->Options, OPTION_TILING_2D, TRUE)) + intel->tiling &= ~INTEL_TILING_2D; + if (xf86ReturnOptValBool(intel->Options, OPTION_TILING_FB, FALSE)) + intel->tiling &= ~INTEL_TILING_FB; - /* Enable FB compression if possible */ - if (i830_fb_compression_supported(intel)) - intel->fb_compression = TRUE; - else - intel->fb_compression = FALSE; - - /* Again, allow user override if set */ - if (xf86IsOptionSet(intel->Options, OPTION_FBC)) { - if (xf86ReturnOptValBool(intel->Options, OPTION_FBC, FALSE)) - intel->fb_compression = TRUE; - else - intel->fb_compression = FALSE; + if (xf86IsOptionSet(intel->Options, OPTION_SHADOW)) { + if (xf86ReturnOptValBool(intel->Options, OPTION_SHADOW, FALSE)) + intel->use_shadow = TRUE; } - if (intel->use_drm_mode && intel->fb_compression == TRUE) { + if (intel->use_shadow) { xf86DrvMsg(scrn->scrnIndex, X_CONFIG, - "Kernel mode setting active, disabling FBC.\n"); - intel->fb_compression = FALSE; + "Shadow buffer enabled," + " 2D GPU acceleration disabled.\n"); } /* SwapBuffers delays to avoid tearing */ @@ -2590,10 +2298,12 @@ I830ScreenInit(int scrnIndex, ScreenPtr screen, int argc, char **argv) intel->swapbuffers_wait = FALSE; } - xf86DrvMsg(scrn->scrnIndex, X_CONFIG, "Framebuffer compression %sabled\n", - intel->fb_compression ? "en" : "dis"); - xf86DrvMsg(scrn->scrnIndex, X_CONFIG, "Tiling %sabled\n", - intel->tiling ? "en" : "dis"); + xf86DrvMsg(scrn->scrnIndex, X_CONFIG, "Framebuffer %s\n", + intel->tiling & INTEL_TILING_FB ? "tiled" : "linear"); + xf86DrvMsg(scrn->scrnIndex, X_CONFIG, "Pixmaps %s\n", + intel->tiling & INTEL_TILING_2D ? "tiled" : "linear"); + xf86DrvMsg(scrn->scrnIndex, X_CONFIG, "3D buffers %s\n", + intel->tiling & INTEL_TILING_3D ? "tiled" : "linear"); xf86DrvMsg(scrn->scrnIndex, X_CONFIG, "SwapBuffers wait %sabled\n", intel->swapbuffers_wait ? "en" : "dis"); @@ -2625,9 +2335,12 @@ I830ScreenInit(int scrnIndex, ScreenPtr screen, int argc, char **argv) return FALSE; } - i830_fixup_mtrrs(scrn); + intel_fixup_mtrrs(scrn); + + intel_batch_init(scrn); - intel->starting = TRUE; + if (INTEL_INFO(intel)->gen >= 40) + gen4_render_state_init(scrn); miClearVisualTypes(); if (!miSetVisualTypes(scrn->depth, @@ -2647,15 +2360,6 @@ I830ScreenInit(int scrnIndex, ScreenPtr screen, int argc, char **argv) DPRINTF(PFX, "assert( if(!I830EnterVT(scrnIndex, 0)) )\n"); - if (scrn->virtualX > scrn->displayWidth) - scrn->displayWidth = scrn->virtualX; - - /* If the front buffer is not a BO, we need to - * set the initial framebuffer pixmap to point at - * it - */ - scrn->fbOffset = intel->front_buffer->offset; - DPRINTF(PFX, "assert( if(!fbScreenInit(screen, ...) )\n"); if (!fbScreenInit(screen, NULL, scrn->virtualX, scrn->virtualY, @@ -2682,20 +2386,12 @@ I830ScreenInit(int scrnIndex, ScreenPtr screen, int argc, char **argv) xf86SetBlackWhitePixels(screen); - if (!I830AccelInit(screen)) { + if (!intel_uxa_init(screen)) { xf86DrvMsg(scrn->scrnIndex, X_ERROR, "Hardware acceleration initialization failed\n"); return FALSE; } - if (IS_I965G(intel)) { - intel->batch_flush_notify = i965_batch_flush_notify; - } else if (IS_I9XX(intel)) { - intel->vertex_flush = i915_vertex_flush; - intel->batch_flush_notify = i915_batch_flush_notify; - } else - intel->batch_flush_notify = i830_batch_flush_notify; - miInitializeBackingStore(screen); xf86SetBackingStore(screen); xf86SetSilkenMouse(screen); @@ -2716,6 +2412,9 @@ I830ScreenInit(int scrnIndex, ScreenPtr screen, int argc, char **argv) intel->BlockHandler = screen->BlockHandler; screen->BlockHandler = I830BlockHandler; + if (!AddCallback(&FlushCallback, intel_flush_callback, scrn)) + return FALSE; + screen->SaveScreen = xf86SaveScreen; intel->CloseScreen = screen->CloseScreen; screen->CloseScreen = I830CloseScreen; @@ -2739,7 +2438,7 @@ I830ScreenInit(int scrnIndex, ScreenPtr screen, int argc, char **argv) xf86DPMSInit(screen, xf86DPMSSet, 0); #ifdef INTEL_XVMC - if (IS_I965G(intel)) + if (INTEL_INFO(intel)->gen >= 40) intel->XvMCEnabled = TRUE; from = ((intel->directRenderingType == DRI_DRI2) && xf86GetOptValBool(intel->Options, OPTION_XVMC, @@ -2775,11 +2474,18 @@ I830ScreenInit(int scrnIndex, ScreenPtr screen, int argc, char **argv) if (serverGeneration == 1) xf86ShowUnusedOptions(scrn->scrnIndex, scrn->options); +#ifdef notyet + if (!intel->use_drm_mode { + AddGeneralSocket(intel->drmSubFD); + RegisterBlockAndWakeupHandlers((BlockHandlerProcPtr)NoopDDA, + drm_wakeup_handler, intel); + } +#endif + intel->starting = FALSE; - intel->closing = FALSE; intel->suspended = FALSE; - return uxa_resources_init(screen); + return TRUE; } static void i830AdjustFrame(int scrnIndex, int x, int y, int flags) @@ -2810,7 +2516,7 @@ static void I830FreeScreen(int scrnIndex, int flags) { ScrnInfoPtr scrn = xf86Screens[scrnIndex]; - i830_close_drm_master(scrn); + intel_close_drm_master(scrn); I830FreeRec(xf86Screens[scrnIndex]); if (xf86LoaderCheckSymbol("vgaHWFreeHWRec")) @@ -2825,8 +2531,6 @@ static void I830LeaveVT(int scrnIndex, int flags) DPRINTF(PFX, "Leave VT\n"); - intel->leaving = TRUE; - i830SetHotkeyControl(scrn, HOTKEY_BIOS_SWITCH); xf86RotateFreeShadow(scrn); @@ -2850,8 +2554,6 @@ static void I830LeaveVT(int scrnIndex, int flags) } - intel_batch_teardown(scrn); - i830_unbind_all_memory(scrn); if (!intel->use_drm_mode) { @@ -2866,9 +2568,6 @@ static void I830LeaveVT(int scrnIndex, int flags) strerror(ret)); } - if (IS_I965G(intel)) - gen4_render_state_cleanup(scrn); - ret = drmDropMaster(intel->drmSubFD); if (ret) xf86DrvMsg(scrn->scrnIndex, X_WARNING, @@ -2912,9 +2611,6 @@ static Bool I830EnterVT(int scrnIndex, int flags) /* Get the hardware into a known state if needed */ if (!intel->use_drm_mode) { - - I830SwapPipes(scrn); - /* Disable outputs */ for (i = 0; i < xf86_config->num_output; i++) { xf86OutputPtr output = xf86_config->output[i]; @@ -2933,8 +2629,6 @@ static Bool I830EnterVT(int scrnIndex, int flags) i830WaitForVblank(scrn); } - intel->leaving = FALSE; - if (!intel->use_drm_mode) { int ret; @@ -2954,11 +2648,6 @@ static Bool I830EnterVT(int scrnIndex, int flags) i830_describe_allocations(scrn, 1, ""); - intel_batch_init(scrn); - - if (IS_I965G(intel)) - gen4_render_state_init(scrn); - if (!intel->use_drm_mode) { I830InitHWCursor(scrn); @@ -2970,8 +2659,8 @@ static Bool I830EnterVT(int scrnIndex, int flags) if (intel->power_context) OUTREG(PWRCTXA, intel->power_context->offset | PWRCTX_EN); - /* Clear the framebuffer */ - memset(intel->FbBase + scrn->fbOffset, 0, + /* Clear the framebuffer XXX drm_bo_map */ + memset(intel->FbBase + intel->front_buffer->offset, 0, scrn->virtualY * scrn->displayWidth * intel->cpp); } @@ -3005,12 +2694,12 @@ static Bool I830CloseScreen(int scrnIndex, ScreenPtr screen) ScrnInfoPtr scrn = xf86Screens[scrnIndex]; intel_screen_private *intel = intel_get_screen_private(scrn); - intel->closing = TRUE; - if (scrn->vtSema == TRUE) { I830LeaveVT(scrnIndex, 0); } + DeleteCallback(&FlushCallback, intel_flush_callback, scrn); + if (!intel->use_drm_mode) { DPRINTF(PFX, "\nUnmapping memory\n"); I830UnmapMem(scrn); @@ -3023,13 +2712,33 @@ static Bool I830CloseScreen(int scrnIndex, ScreenPtr screen) intel->uxa_driver = NULL; } if (intel->front_buffer) { - i830_set_pixmap_bo(screen->GetScreenPixmap(screen), NULL); + if (!intel->use_shadow) + intel_set_pixmap_bo(screen->GetScreenPixmap(screen), + NULL); if (intel->use_drm_mode) drmmode_closefb(scrn); - i830_free_memory(scrn, intel->front_buffer); + /* already unpinned by leavevt */ + drm_intel_bo_unreference(intel->front_buffer); intel->front_buffer = NULL; } + if (intel->shadow_buffer) { + free(intel->shadow_buffer); + intel->shadow_buffer = NULL; + } + + if (intel->shadow_damage) { + DamageUnregister(&screen->GetScreenPixmap(screen)->drawable, + intel->shadow_damage); + DamageDestroy(intel->shadow_damage); + intel->shadow_damage = NULL; + } + + intel_batch_teardown(scrn); + + if (INTEL_INFO(intel)->gen >= 40) + gen4_render_state_cleanup(scrn); + xf86_cursors_fini(screen); i830_allocator_fini(scrn); @@ -3050,7 +2759,6 @@ static Bool I830CloseScreen(int scrnIndex, ScreenPtr screen) xf86GARTCloseScreen(scrnIndex); scrn->vtSema = FALSE; - intel->closing = FALSE; return TRUE; } @@ -3137,7 +2845,7 @@ static Bool I830PMEvent(int scrnIndex, pmEvent event, Bool undo) return TRUE; } -xf86CrtcPtr i830_pipe_to_crtc(ScrnInfoPtr scrn, int pipe) +xf86CrtcPtr intel_pipe_to_crtc(ScrnInfoPtr scrn, int pipe) { xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(scrn); int c; diff --git a/driver/xf86-video-intel/src/intel_driver.h b/driver/xf86-video-intel/src/intel_driver.h new file mode 100644 index 000000000..c1fb92b96 --- /dev/null +++ b/driver/xf86-video-intel/src/intel_driver.h @@ -0,0 +1,299 @@ +#ifndef INTEL_DRIVER_H +#define INTEL_DRIVER_H + +#define INTEL_VERSION 4000 +#define INTEL_NAME "intel" +#define INTEL_DRIVER_NAME "intel" + +#define INTEL_VERSION_MAJOR PACKAGE_VERSION_MAJOR +#define INTEL_VERSION_MINOR PACKAGE_VERSION_MINOR +#define INTEL_VERSION_PATCH PACKAGE_VERSION_PATCHLEVEL + +#ifndef PCI_CHIP_I810 +#define PCI_CHIP_I810 0x7121 +#define PCI_CHIP_I810_DC100 0x7123 +#define PCI_CHIP_I810_E 0x7125 +#define PCI_CHIP_I815 0x1132 +#define PCI_CHIP_I810_BRIDGE 0x7120 +#define PCI_CHIP_I810_DC100_BRIDGE 0x7122 +#define PCI_CHIP_I810_E_BRIDGE 0x7124 +#define PCI_CHIP_I815_BRIDGE 0x1130 +#endif + +#ifndef PCI_CHIP_I830_M +#define PCI_CHIP_I830_M 0x3577 +#define PCI_CHIP_I830_M_BRIDGE 0x3575 +#endif + +#ifndef PCI_CHIP_845_G +#define PCI_CHIP_845_G 0x2562 +#define PCI_CHIP_845_G_BRIDGE 0x2560 +#endif + +#ifndef PCI_CHIP_I854 +#define PCI_CHIP_I854 0x358E +#define PCI_CHIP_I854_BRIDGE 0x358C +#endif + +#ifndef PCI_CHIP_I855_GM +#define PCI_CHIP_I855_GM 0x3582 +#define PCI_CHIP_I855_GM_BRIDGE 0x3580 +#endif + +#ifndef PCI_CHIP_I865_G +#define PCI_CHIP_I865_G 0x2572 +#define PCI_CHIP_I865_G_BRIDGE 0x2570 +#endif + +#ifndef PCI_CHIP_I915_G +#define PCI_CHIP_I915_G 0x2582 +#define PCI_CHIP_I915_G_BRIDGE 0x2580 +#endif + +#ifndef PCI_CHIP_I915_GM +#define PCI_CHIP_I915_GM 0x2592 +#define PCI_CHIP_I915_GM_BRIDGE 0x2590 +#endif + +#ifndef PCI_CHIP_E7221_G +#define PCI_CHIP_E7221_G 0x258A +/* Same as I915_G_BRIDGE */ +#define PCI_CHIP_E7221_G_BRIDGE 0x2580 +#endif + +#ifndef PCI_CHIP_I945_G +#define PCI_CHIP_I945_G 0x2772 +#define PCI_CHIP_I945_G_BRIDGE 0x2770 +#endif + +#ifndef PCI_CHIP_I945_GM +#define PCI_CHIP_I945_GM 0x27A2 +#define PCI_CHIP_I945_GM_BRIDGE 0x27A0 +#endif + +#ifndef PCI_CHIP_I945_GME +#define PCI_CHIP_I945_GME 0x27AE +#define PCI_CHIP_I945_GME_BRIDGE 0x27AC +#endif + +#ifndef PCI_CHIP_PINEVIEW_M +#define PCI_CHIP_PINEVIEW_M 0xA011 +#define PCI_CHIP_PINEVIEW_M_BRIDGE 0xA010 +#define PCI_CHIP_PINEVIEW_G 0xA001 +#define PCI_CHIP_PINEVIEW_G_BRIDGE 0xA000 +#endif + +#ifndef PCI_CHIP_G35_G +#define PCI_CHIP_G35_G 0x2982 +#define PCI_CHIP_G35_G_BRIDGE 0x2980 +#endif + +#ifndef PCI_CHIP_I965_Q +#define PCI_CHIP_I965_Q 0x2992 +#define PCI_CHIP_I965_Q_BRIDGE 0x2990 +#endif + +#ifndef PCI_CHIP_I965_G +#define PCI_CHIP_I965_G 0x29A2 +#define PCI_CHIP_I965_G_BRIDGE 0x29A0 +#endif + +#ifndef PCI_CHIP_I946_GZ +#define PCI_CHIP_I946_GZ 0x2972 +#define PCI_CHIP_I946_GZ_BRIDGE 0x2970 +#endif + +#ifndef PCI_CHIP_I965_GM +#define PCI_CHIP_I965_GM 0x2A02 +#define PCI_CHIP_I965_GM_BRIDGE 0x2A00 +#endif + +#ifndef PCI_CHIP_I965_GME +#define PCI_CHIP_I965_GME 0x2A12 +#define PCI_CHIP_I965_GME_BRIDGE 0x2A10 +#endif + +#ifndef PCI_CHIP_G33_G +#define PCI_CHIP_G33_G 0x29C2 +#define PCI_CHIP_G33_G_BRIDGE 0x29C0 +#endif + +#ifndef PCI_CHIP_Q35_G +#define PCI_CHIP_Q35_G 0x29B2 +#define PCI_CHIP_Q35_G_BRIDGE 0x29B0 +#endif + +#ifndef PCI_CHIP_Q33_G +#define PCI_CHIP_Q33_G 0x29D2 +#define PCI_CHIP_Q33_G_BRIDGE 0x29D0 +#endif + +#ifndef PCI_CHIP_GM45_GM +#define PCI_CHIP_GM45_GM 0x2A42 +#define PCI_CHIP_GM45_BRIDGE 0x2A40 +#endif + +#ifndef PCI_CHIP_G45_E_G +#define PCI_CHIP_G45_E_G 0x2E02 +#define PCI_CHIP_G45_E_G_BRIDGE 0x2E00 +#endif + +#ifndef PCI_CHIP_G45_G +#define PCI_CHIP_G45_G 0x2E22 +#define PCI_CHIP_G45_G_BRIDGE 0x2E20 +#endif + +#ifndef PCI_CHIP_Q45_G +#define PCI_CHIP_Q45_G 0x2E12 +#define PCI_CHIP_Q45_G_BRIDGE 0x2E10 +#endif + +#ifndef PCI_CHIP_G41_G +#define PCI_CHIP_G41_G 0x2E32 +#define PCI_CHIP_G41_G_BRIDGE 0x2E30 +#endif + +#ifndef PCI_CHIP_B43_G +#define PCI_CHIP_B43_G 0x2E42 +#define PCI_CHIP_B43_G_BRIDGE 0x2E40 +#endif + +#ifndef PCI_CHIP_B43_G1 +#define PCI_CHIP_B43_G1 0x2E92 +#define PCI_CHIP_B43_G1_BRIDGE 0x2E90 +#endif + +#ifndef PCI_CHIP_IRONLAKE_D_G +#define PCI_CHIP_IRONLAKE_D_G 0x0042 +#define PCI_CHIP_IRONLAKE_D_G_BRIDGE 0x0040 +#endif + +#ifndef PCI_CHIP_IRONLAKE_M_G +#define PCI_CHIP_IRONLAKE_M_G 0x0046 +#define PCI_CHIP_IRONLAKE_M_G_BRIDGE 0x0044 +#endif + +#ifndef PCI_CHIP_SANDYBRIDGE_BRIDGE +#define PCI_CHIP_SANDYBRIDGE_BRIDGE 0x0100 /* Desktop */ +#define PCI_CHIP_SANDYBRIDGE_GT1 0x0102 +#define PCI_CHIP_SANDYBRIDGE_GT2 0x0112 +#define PCI_CHIP_SANDYBRIDGE_GT2_PLUS 0x0122 +#define PCI_CHIP_SANDYBRIDGE_BRIDGE_M 0x0104 /* Mobile */ +#define PCI_CHIP_SANDYBRIDGE_M_GT1 0x0106 +#define PCI_CHIP_SANDYBRIDGE_M_GT2 0x0116 +#define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS 0x0126 +#define PCI_CHIP_SANDYBRIDGE_BRIDGE_S 0x0108 /* Server */ +#define PCI_CHIP_SANDYBRIDGE_S_GT 0x010A + +#define PCI_CHIP_IVYBRIDGE_M_GT1 0x0156 +#define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166 +#define PCI_CHIP_IVYBRIDGE_D_GT1 0x0152 +#define PCI_CHIP_IVYBRIDGE_D_GT2 0x0162 +#define PCI_CHIP_IVYBRIDGE_S_GT1 0x015a + +#endif + +#define I85X_CAPID 0x44 +#define I85X_VARIANT_MASK 0x7 +#define I85X_VARIANT_SHIFT 5 +#define I855_GME 0x0 +#define I855_GM 0x4 +#define I852_GME 0x2 +#define I852_GM 0x5 + +#define I810_MEMBASE(p,n) (p)->regions[(n)].base_addr +#define VENDOR_ID(p) (p)->vendor_id +#define DEVICE_ID(p) (p)->device_id +#define SUBVENDOR_ID(p) (p)->subvendor_id +#define SUBSYS_ID(p) (p)->subdevice_id +#define CHIP_REVISION(p) (p)->revision + +#define INTEL_INFO(intel) ((intel)->chipset.info) +#define IS_GENx(intel, X) (INTEL_INFO(intel)->gen >= 10*(X) && INTEL_INFO(intel)->gen < 10*((X)+1)) +#define IS_GEN1(intel) IS_GENx(intel, 1) +#define IS_GEN2(intel) IS_GENx(intel, 2) +#define IS_GEN3(intel) IS_GENx(intel, 3) +#define IS_GEN4(intel) IS_GENx(intel, 4) +#define IS_GEN5(intel) IS_GENx(intel, 5) +#define IS_GEN6(intel) IS_GENx(intel, 6) +#define IS_GEN7(intel) IS_GENx(intel, 7) + +/* Some chips have specific errata (or limits) that we need to workaround. */ +#define IS_I830(intel) (DEVICE_ID((intel)->PciInfo) == PCI_CHIP_I830_M) +#define IS_845G(intel) (DEVICE_ID((intel)->PciInfo) == PCI_CHIP_845_G) +#define IS_I85X(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I855_GM || \ + DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I854) +#define IS_I855(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I855_GM && (pI810->chipset.variant == I855_GM || pI810->chipset.variant == I855_GME)) +#define IS_I865G(intel) (DEVICE_ID((intel)->PciInfo) == PCI_CHIP_I865_G) + +#define IS_I915G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I915_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_E7221_G) +#define IS_I915GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I915_GM) + #define IS_I945G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_G) + #define IS_I945GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GME) + #define IS_IGDGM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_PINEVIEW_M) + #define IS_IGDG(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_PINEVIEW_G) + #define IS_IGD(pI810) (IS_IGDG(pI810) || IS_IGDGM(pI810)) + #define IS_GM45(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_GM45_GM) + #define IS_G4X(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G45_E_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G45_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q45_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G41_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_B43_G || IS_GM45(pI810)) + #define IS_I965GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME) + +#define IS_965_Q(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q) +#define IS_IGDNG_D(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IRONLAKE_D_G) +#define IS_IGDNG_M(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IRONLAKE_M_G) +#define IS_IGDNG(pI810) (IS_IGDNG_D(pI810) || IS_IGDNG_M(pI810)) +#define IS_I965G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_G || \ + DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G35_G || \ + DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q || \ + DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I946_GZ || \ + DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || \ + DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME || \ + IS_G4X(pI810) || \ + IS_IGDNG(pI810) || \ + IS_GEN6(pI810)) +#define IS_G33CLASS(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G33_G ||\ + DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q35_G ||\ + DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q33_G || \ + IS_IGD(pI810)) + +#define IS_I9XX(pI810) (IS_I915G(pI810) || \ + IS_I915GM(pI810) || \ + IS_I945G(pI810) || \ + IS_I945GM(pI810) || \ + IS_I965G(pI810) || \ + IS_G33CLASS(pI810)) + +#define IS_I915(pI810) (IS_I915G(pI810) || IS_I915GM(pI810) || IS_I945G(pI810) || IS_I945GM(pI810) || IS_G33CLASS(pI810)) + +#define IS_MOBILE(pI810) (IS_I830(pI810) || IS_I85X(pI810) || IS_I915GM(pI810) || IS_I945GM(pI810) || IS_I965GM(pI810) || IS_GM45(pI810) || IS_IGD(pI810) || IS_IGDNG_M(pI810)) +/* mark chipsets for using gfx VM offset for overlay */ +#define OVERLAY_NOPHYSICAL(pI810) (IS_G33CLASS(pI810) || IS_I965G(pI810)) +/* mark chipsets without overlay hw */ +#define OVERLAY_NOEXIST(pI810) (IS_G4X(pI810) || IS_IGDNG(pI810)) +/* chipsets require graphics mem for hardware status page */ +#define HWS_NEED_GFX(pI810) (!pI810->use_drm_mode && \ + (IS_G33CLASS(pI810) ||\ + IS_G4X(pI810) || IS_IGDNG(pI810))) +/* chipsets require status page in non stolen memory */ +#define HWS_NEED_NONSTOLEN(pI810) (IS_G4X(pI810) || IS_IGDNG(pI810)) +#define SUPPORTS_INTEGRATED_HDMI(pI810) (IS_G4X(pI810) || IS_IGDNG(pI810)) +/* dsparb controlled by hw only */ +#define DSPARB_HWCONTROL(pI810) (IS_G4X(pI810) || IS_IGDNG(pI810)) +/* supports Y tiled surfaces (pre-965 Mesa isn't ready yet) */ +#define SUPPORTS_YTILING(pI810) (INTEL_INFO(intel)->gen >= 40) +#define HAS_BLT(pI810) (INTEL_INFO(intel)->gen >= 60) + +extern SymTabRec *intel_chipsets; + +struct intel_chipset { + const char *name; + int variant; + const struct intel_device_info { + int gen; + } *info; +}; + +void intel_detect_chipset(ScrnInfoPtr scrn, + struct pci_device *pci, + struct intel_chipset *chipset); + +#endif /* INTEL_DRIVER_H */ diff --git a/driver/xf86-video-intel/src/i830_hwmc.c b/driver/xf86-video-intel/src/intel_hwmc.c index 9aa0af33b..d6267256c 100644 --- a/driver/xf86-video-intel/src/i830_hwmc.c +++ b/driver/xf86-video-intel/src/intel_hwmc.c @@ -29,8 +29,8 @@ #endif #define _INTEL_XVMC_SERVER_ -#include "i830.h" -#include "i830_hwmc.h" +#include "intel.h" +#include "intel_hwmc.h" #include <X11/extensions/Xv.h> #include <X11/extensions/XvMC.h> @@ -71,17 +71,17 @@ static int create_context(ScrnInfoPtr scrn, XvMCContextPtr pContext, *num_priv = sizeof(struct intel_xvmc_hw_context) >> 2; - if (IS_I915(intel)) { + if (IS_GEN3(intel)) { contextRec->type = XVMC_I915_MPEG2_MC; contextRec->i915.use_phys_addr = 0; } else { - if (IS_G4X(intel) || IS_IGDNG(intel)) + if (INTEL_INFO(intel)->gen >= 45) contextRec->type = XVMC_I965_MPEG2_VLD; else contextRec->type = XVMC_I965_MPEG2_MC; - contextRec->i965.is_g4x = IS_G4X(intel); + contextRec->i965.is_g4x = INTEL_INFO(intel)->gen == 45; contextRec->i965.is_965_q = IS_965_Q(intel); - contextRec->i965.is_igdng = IS_IGDNG(intel); + contextRec->i965.is_igdng = IS_GEN5(intel); } return Success; @@ -202,7 +202,7 @@ Bool intel_xvmc_adaptor_init(ScreenPtr pScreen) if (IS_I915G(intel) || IS_I915GM(intel)) return FALSE; - if (!IS_I9XX(intel)) { + if (IS_GEN2(intel)) { ErrorF("Your chipset doesn't support XvMC.\n"); return FALSE; } @@ -223,11 +223,11 @@ Bool intel_xvmc_adaptor_init(ScreenPtr pScreen) pAdapt->CreateSubpicture = create_subpicture; pAdapt->DestroySubpicture = destroy_subpicture; - if (IS_I915(intel)) { + if (IS_GEN3(intel)) { name = "i915_xvmc", pAdapt->num_surfaces = ARRAY_SIZE(surface_info_i915); pAdapt->surfaces = surface_info_i915; - } else if (IS_G4X(intel) || IS_IGDNG(intel)) { + } else if (INTEL_INFO(intel)->gen >= 45) { name = "xvmc_vld", pAdapt->num_surfaces = ARRAY_SIZE(surface_info_vld); pAdapt->surfaces = surface_info_vld; diff --git a/driver/xf86-video-intel/src/i830_hwmc.h b/driver/xf86-video-intel/src/intel_hwmc.h index 8682fe0ec..8682fe0ec 100644 --- a/driver/xf86-video-intel/src/i830_hwmc.h +++ b/driver/xf86-video-intel/src/intel_hwmc.h diff --git a/driver/xf86-video-intel/src/i830_memory.c b/driver/xf86-video-intel/src/intel_memory.c index 0e523b7ca..017a28988 100644 --- a/driver/xf86-video-intel/src/i830_memory.c +++ b/driver/xf86-video-intel/src/intel_memory.c @@ -37,7 +37,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ /** - * @file i830_memory.c + * @file intel_memory.c * * This is the video memory allocator. Our memory allocation is different from * other graphics chips, where you have a fixed amount of graphics memory @@ -84,42 +84,36 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "xf86.h" #include "xf86_OSproc.h" -#include "i830.h" -#include "i810_reg.h" +#include "intel.h" +#include "i830_reg.h" #include "i915_drm.h" /* Our hardware status area is just a single page */ #define HWSTATUS_PAGE_SIZE GTT_PAGE_SIZE #define PWRCTX_SIZE GTT_PAGE_SIZE -static i830_memory * +static intel_memory * i830_allocate_aperture(ScrnInfoPtr scrn, const char *name, unsigned long size, unsigned long pitch, - unsigned long alignment, int flags, - enum tile_format tile_format); + unsigned long alignment, int flags); -static int i830_set_tiling(ScrnInfoPtr scrn, unsigned int offset, - unsigned int pitch, unsigned int size, - enum tile_format tile_format); - -static void i830_clear_tiling(ScrnInfoPtr scrn, unsigned int fence_nr); /** * Returns the fence size for a tiled area of the given size. */ -unsigned long i830_get_fence_size(intel_screen_private *intel, unsigned long size) +unsigned long intel_get_fence_size(intel_screen_private *intel, unsigned long size) { unsigned long i; unsigned long start; - if (IS_I965G(intel)) { + if (INTEL_INFO(intel)->gen >= 40 || intel->has_relaxed_fencing) { /* The 965 can have fences at any page boundary. */ return ALIGN(size, GTT_PAGE_SIZE); } else { /* Align the size to a power of two greater than the smallest fence * size. */ - if (IS_I9XX(intel)) + if (IS_GEN3(intel)) start = MB(1); else start = KB(512); @@ -135,17 +129,18 @@ unsigned long i830_get_fence_size(intel_screen_private *intel, unsigned long siz * calculate that here. */ unsigned long -i830_get_fence_pitch(intel_screen_private *intel, unsigned long pitch, int format) +intel_get_fence_pitch(intel_screen_private *intel, unsigned long pitch, + uint32_t format) { unsigned long i; unsigned long tile_width = (format == I915_TILING_Y) ? 128 : 512; - if (format == TILE_NONE) + if (format == I915_TILING_NONE) return pitch; - /* 965 is flexible */ - if (IS_I965G(intel)) - return ROUND_TO(pitch, tile_width); + /* 965+ is flexible */ + if (INTEL_INFO(intel)->gen >= 40) + return ALIGN(pitch, tile_width); /* Pre-965 needs power of two tile width */ for (i = tile_width; i < pitch; i <<= 1) ; @@ -153,37 +148,24 @@ i830_get_fence_pitch(intel_screen_private *intel, unsigned long pitch, int forma return i; } -/** - * On some chips, pitch width has to be a power of two tile width, so - * calculate that here. - */ -static unsigned long i830_get_fence_alignment(intel_screen_private *intel, unsigned long size) -{ - if (IS_I965G(intel)) - return 4096; - else - return i830_get_fence_size(intel, size); -} - static Bool -i830_check_display_stride(ScrnInfoPtr scrn, int stride, Bool tiling) +intel_check_display_stride(ScrnInfoPtr scrn, int stride, Bool tiling) { intel_screen_private *intel = intel_get_screen_private(scrn); int limit = KB(32); /* 8xx spec has always 8K limit, but tests show larger limit in non-tiling mode, which makes large monitor work. */ - if ((IS_845G(intel) || IS_I85X(intel)) && tiling) - limit = KB(8); - - if (IS_I915(intel) && tiling) - limit = KB(8); - - if (IS_I965G(intel) && tiling) - limit = KB(16); - - if (IS_IGDNG(intel) && tiling) - limit = KB(32); + if (tiling) { + if (IS_GEN2(intel)) + limit = KB(8); + else if (IS_GEN3(intel)) + limit = KB(8); + else if (IS_GEN4(intel)) + limit = KB(16); + else + limit = KB(32); + } if (stride <= limit) return TRUE; @@ -191,7 +173,7 @@ i830_check_display_stride(ScrnInfoPtr scrn, int stride, Bool tiling) return FALSE; } -static Bool i830_bind_memory(ScrnInfoPtr scrn, i830_memory *mem) +static Bool i830_bind_memory(ScrnInfoPtr scrn, intel_memory *mem) { intel_screen_private *intel = intel_get_screen_private(scrn); @@ -226,7 +208,7 @@ static Bool i830_bind_memory(ScrnInfoPtr scrn, i830_memory *mem) return TRUE; } -static Bool i830_unbind_memory(ScrnInfoPtr scrn, i830_memory *mem) +static Bool i830_unbind_memory(ScrnInfoPtr scrn, intel_memory *mem) { intel_screen_private *intel = intel_get_screen_private(scrn); @@ -255,7 +237,7 @@ static Bool i830_unbind_memory(ScrnInfoPtr scrn, i830_memory *mem) } } -void i830_free_memory(ScrnInfoPtr scrn, i830_memory * mem) +void i830_free_memory(ScrnInfoPtr scrn, intel_memory * mem) { if (mem == NULL) return; @@ -295,45 +277,6 @@ void i830_free_memory(ScrnInfoPtr scrn, i830_memory * mem) free(mem); } -/* Resets the state of the aperture allocator, freeing all memory that had - * been allocated. - */ -void i830_reset_allocations(ScrnInfoPtr scrn) -{ - intel_screen_private *intel = intel_get_screen_private(scrn); - int p; - - /* While there is any memory between the start and end markers, free it. */ - while (intel->memory_list->next->next != NULL) { - i830_memory *mem = intel->memory_list->next; - - /* Don't reset BO allocator, which we set up at init. */ - if (intel->memory_manager == mem) { - mem = mem->next; - if (mem->next == NULL) - break; - } - - i830_free_memory(scrn, mem); - } - - /* Free any allocations in buffer objects */ - while (intel->bo_list != NULL) - i830_free_memory(scrn, intel->bo_list); - - /* Null out the pointers for all the allocations we just freed. This is - * kind of gross, but at least it's just one place now. - */ - intel->cursor_mem = NULL; - for (p = 0; p < 2; p++) { - intel->cursor_mem_classic[p] = NULL; - intel->cursor_mem_argb[p] = NULL; - } - intel->front_buffer = NULL; - intel->overlay_regs = NULL; - intel->power_context = NULL; -} - /** * Initialize's the driver's video memory allocator to allocate in the * given range. @@ -346,7 +289,7 @@ void i830_reset_allocations(ScrnInfoPtr scrn) Bool i830_allocator_init(ScrnInfoPtr scrn, unsigned long size) { intel_screen_private *intel = intel_get_screen_private(scrn); - i830_memory *start, *end; + intel_memory *start, *end; struct drm_i915_setparam sp; start = calloc(1, sizeof(*start)); @@ -403,15 +346,12 @@ Bool i830_allocator_init(ScrnInfoPtr scrn, unsigned long size) * outside of the kernel memory manager. */ if (!OVERLAY_NOPHYSICAL(intel) && !OVERLAY_NOEXIST(intel)) { - mmsize -= ROUND_TO(OVERLAY_SIZE, GTT_PAGE_SIZE); + mmsize -= ALIGN(OVERLAY_SIZE, GTT_PAGE_SIZE); } if (intel->CursorNeedsPhysical) { - mmsize -= 2 * (ROUND_TO(HWCURSOR_SIZE, GTT_PAGE_SIZE) + - ROUND_TO(HWCURSOR_SIZE_ARGB, GTT_PAGE_SIZE)); + mmsize -= 2 * (ALIGN(HWCURSOR_SIZE, GTT_PAGE_SIZE) + + ALIGN(HWCURSOR_SIZE_ARGB, GTT_PAGE_SIZE)); } - if (intel->fb_compression) - mmsize -= MB(6) + ROUND_TO_PAGE(FBC_LL_SIZE + - FBC_LL_PAD); /* Can't do GEM on stolen memory */ mmsize -= intel->stolen_size; @@ -419,8 +359,7 @@ Bool i830_allocator_init(ScrnInfoPtr scrn, unsigned long size) /* Create the aperture allocation */ intel->memory_manager = i830_allocate_aperture(scrn, "DRI memory manager", - mmsize, 0, GTT_PAGE_SIZE, ALIGN_BOTH_ENDS | NEED_NON_STOLEN, - TILE_NONE); + mmsize, 0, GTT_PAGE_SIZE, ALIGN_BOTH_ENDS | NEED_NON_STOLEN); if (intel->memory_manager != NULL) { struct drm_i915_gem_init init; @@ -447,7 +386,7 @@ Bool i830_allocator_init(ScrnInfoPtr scrn, unsigned long size) intel->memory_manager = NULL; return FALSE; } - i830_init_bufmgr(scrn); + intel_init_bufmgr(scrn); } else { xf86DrvMsg(scrn->scrnIndex, X_ERROR, "Failed to allocate space for kernel memory manager\n"); @@ -460,6 +399,36 @@ Bool i830_allocator_init(ScrnInfoPtr scrn, unsigned long size) void i830_allocator_fini(ScrnInfoPtr scrn) { intel_screen_private *intel = intel_get_screen_private(scrn); + int p; + + /* While there is any memory between the start and end markers, free it. */ + while (intel->memory_list->next->next != NULL) { + intel_memory *mem = intel->memory_list->next; + + /* Don't reset BO allocator, which we set up at init. */ + if (intel->memory_manager == mem) { + mem = mem->next; + if (mem->next == NULL) + break; + } + + i830_free_memory(scrn, mem); + } + + /* Free any allocations in buffer objects */ + while (intel->bo_list != NULL) + i830_free_memory(scrn, intel->bo_list); + + /* Null out the pointers for all the allocations we just freed. This is + * kind of gross, but at least it's just one place now. + */ + intel->cursor_mem = NULL; + for (p = 0; p < 2; p++) { + intel->cursor_mem_classic[p] = NULL; + intel->cursor_mem_argb[p] = NULL; + } + intel->overlay_regs = NULL; + intel->power_context = NULL; /* The memory manager is more special */ if (intel->memory_manager) { @@ -556,13 +525,12 @@ static uint64_t i830_get_stolen_physical(ScrnInfoPtr scrn, * * Allocations are a minimum of a page, and will be at least page-aligned. */ -static i830_memory * +static intel_memory * i830_allocate_aperture(ScrnInfoPtr scrn, const char *name, unsigned long size, - unsigned long pitch, unsigned long alignment, int flags, - enum tile_format tile_format) + unsigned long pitch, unsigned long alignment, int flags) { intel_screen_private *intel = intel_get_screen_private(scrn); - i830_memory *mem, *scan; + intel_memory *mem, *scan; mem = calloc(1, sizeof(*mem)); if (mem == NULL) @@ -581,15 +549,13 @@ i830_allocate_aperture(ScrnInfoPtr scrn, const char *name, unsigned long size, mem->size = size; mem->allocated_size = size; mem->alignment = alignment; - mem->tiling = tile_format; mem->pitch = pitch; - mem->fence_nr = -1; if (alignment < GTT_PAGE_SIZE) alignment = GTT_PAGE_SIZE; for (scan = intel->memory_list; scan->next != NULL; scan = scan->next) { - mem->offset = ROUND_TO(scan->end, alignment); + mem->offset = ALIGN(scan->end, alignment); if ((flags & NEED_PHYSICAL_ADDR) && mem->offset < intel->stolen_size) { /* If the allocation is entirely within stolen memory, @@ -607,18 +573,18 @@ i830_allocate_aperture(ScrnInfoPtr scrn, const char *name, unsigned long size, /* Move the start of the allocation to just * past the end of stolen memory. */ - mem->offset = ROUND_TO(intel->stolen_size, + mem->offset = ALIGN(intel->stolen_size, alignment); } } if ((flags & NEED_NON_STOLEN) && mem->offset < intel->stolen_size) { - mem->offset = ROUND_TO(intel->stolen_size, alignment); + mem->offset = ALIGN(intel->stolen_size, alignment); } mem->end = mem->offset + size; if (flags & ALIGN_BOTH_ENDS) - mem->end = ROUND_TO(mem->end, alignment); + mem->end = ALIGN(mem->end, alignment); if (mem->end <= scan->next->offset) break; } @@ -644,7 +610,7 @@ i830_allocate_aperture(ScrnInfoPtr scrn, const char *name, unsigned long size, * The memory is automatically bound if we have the VT. */ static Bool -i830_allocate_agp_memory(ScrnInfoPtr scrn, i830_memory *mem, int flags) +i830_allocate_agp_memory(ScrnInfoPtr scrn, intel_memory *mem, int flags) { intel_screen_private *intel = intel_get_screen_private(scrn); unsigned long size; @@ -680,22 +646,18 @@ i830_allocate_agp_memory(ScrnInfoPtr scrn, i830_memory *mem, int flags) return TRUE; } -static i830_memory *i830_allocate_memory_bo(ScrnInfoPtr scrn, const char *name, +static intel_memory *i830_allocate_memory_bo(ScrnInfoPtr scrn, const char *name, unsigned long size, unsigned long pitch, - unsigned long align, int flags, - enum tile_format tile_format) + unsigned long align, int flags) { intel_screen_private *intel = intel_get_screen_private(scrn); - i830_memory *mem; - uint32_t bo_tiling_mode = I915_TILING_NONE; - int ret; + intel_memory *mem; assert((flags & NEED_PHYSICAL_ADDR) == 0); /* Only allocate page-sized increments. */ size = ALIGN(size, GTT_PAGE_SIZE); - align = i830_get_fence_alignment(intel, size); mem = calloc(1, sizeof(*mem)); if (mem == NULL) @@ -721,36 +683,12 @@ static i830_memory *i830_allocate_memory_bo(ScrnInfoPtr scrn, const char *name, mem->size = size; mem->allocated_size = size; mem->alignment = align; - mem->tiling = tile_format; mem->pitch = pitch; - mem->fence_nr = -1; /* Give buffer obviously wrong offset/end until it's pinned. */ if (flags & NEED_LIFETIME_FIXED) mem->lifetime_fixed_offset = TRUE; - switch (tile_format) { - case TILE_XMAJOR: - bo_tiling_mode = I915_TILING_X; - break; - case TILE_YMAJOR: - bo_tiling_mode = I915_TILING_Y; - break; - case TILE_NONE: - default: - bo_tiling_mode = I915_TILING_NONE; - break; - } - - ret = drm_intel_bo_set_tiling(mem->bo, &bo_tiling_mode, pitch); - if (ret != 0 - || (bo_tiling_mode == I915_TILING_NONE - && tile_format != TILE_NONE)) { - xf86DrvMsg(scrn->scrnIndex, X_ERROR, - "Failed to set tiling on %s: %s\n", mem->name, - ret == 0 ? "rejected by kernel" : strerror(-ret)); - } - /* Bind it if we currently control the VT */ if (scrn->vtSema || intel->use_drm_mode) { if (!i830_bind_memory(scrn, mem)) { @@ -793,33 +731,13 @@ static i830_memory *i830_allocate_memory_bo(ScrnInfoPtr scrn, const char *name, * the entire Screen lifetime. This means not using buffer objects, which * get their offsets chosen at each EnterVT time. */ -i830_memory *i830_allocate_memory(ScrnInfoPtr scrn, const char *name, +intel_memory *i830_allocate_memory(ScrnInfoPtr scrn, const char *name, unsigned long size, unsigned long pitch, - unsigned long alignment, int flags, - enum tile_format tile_format) + unsigned long alignment, int flags) { - i830_memory *mem; + intel_memory *mem; intel_screen_private *intel = intel_get_screen_private(scrn); - /* Manage tile alignment and size constraints */ - if (tile_format != TILE_NONE) { - /* Only allocate page-sized increments. */ - size = ALIGN(size, GTT_PAGE_SIZE); - - /* Check for maximum tiled region size */ - if (IS_I9XX(intel)) { - if (size > MB(128)) - return NULL; - } else { - if (size > MB(64)) - return NULL; - } - - /* round to size necessary for the fence register to work */ - size = i830_get_fence_size(intel, size); - alignment = i830_get_fence_alignment(intel, size); - } - /* * Create a kernel buffer object when suitable. * Under KMS, all graphics memory must be managed by the @@ -829,10 +747,10 @@ i830_memory *i830_allocate_memory(ScrnInfoPtr scrn, const char *name, if ((intel->use_drm_mode || !(flags & (NEED_PHYSICAL_ADDR|NEED_LIFETIME_FIXED)))) { return i830_allocate_memory_bo(scrn, name, size, pitch, - alignment, flags, tile_format); + alignment, flags); } else { mem = i830_allocate_aperture(scrn, name, size, pitch, - alignment, flags, tile_format); + alignment, flags); if (mem == NULL) return NULL; @@ -854,7 +772,7 @@ void i830_describe_allocations(ScrnInfoPtr scrn, int verbosity, const char *prefix) { intel_screen_private *intel = intel_get_screen_private(scrn); - i830_memory *mem; + intel_memory *mem; if (intel->memory_list == NULL) { xf86DrvMsgVerb(scrn->scrnIndex, X_INFO, verbosity, @@ -873,7 +791,6 @@ i830_describe_allocations(ScrnInfoPtr scrn, int verbosity, const char *prefix) for (mem = intel->memory_list->next; mem->next != NULL; mem = mem->next) { char phys_suffix[32] = ""; - char *tile_suffix = ""; if (mem->offset >= intel->stolen_size && mem->prev->offset < intel->stolen_size) { @@ -885,15 +802,11 @@ i830_describe_allocations(ScrnInfoPtr scrn, int verbosity, const char *prefix) if (mem->bus_addr != 0) snprintf(phys_suffix, sizeof(phys_suffix), ", 0x%016" PRIx64 " physical\n", mem->bus_addr); - if (mem->tiling == TILE_XMAJOR) - tile_suffix = " X tiled"; - else if (mem->tiling == TILE_YMAJOR) - tile_suffix = " Y tiled"; xf86DrvMsgVerb(scrn->scrnIndex, X_INFO, verbosity, - "%s0x%08lx-0x%08lx: %s (%ld kB%s)%s\n", prefix, + "%s0x%08lx-0x%08lx: %s (%ld kB%s)\n", prefix, mem->offset, mem->end - 1, mem->name, - mem->size / 1024, phys_suffix, tile_suffix); + mem->size / 1024, phys_suffix); } xf86DrvMsgVerb(scrn->scrnIndex, X_INFO, verbosity, "%s0x%08lx: end of aperture\n", prefix, intel->FbMapSize); @@ -906,22 +819,15 @@ i830_describe_allocations(ScrnInfoPtr scrn, int verbosity, const char *prefix) prefix, intel->memory_manager->offset); } for (mem = intel->bo_list; mem != NULL; mem = mem->next) { - char *tile_suffix = ""; - - if (mem->tiling == TILE_XMAJOR) - tile_suffix = " X tiled"; - else if (mem->tiling == TILE_YMAJOR) - tile_suffix = " Y tiled"; - if (mem->bound) { xf86DrvMsgVerb(scrn->scrnIndex, X_INFO, verbosity, - "%s0x%08lx-0x%08lx: %s (%ld kB)%s\n", prefix, + "%s0x%08lx-0x%08lx: %s (%ld kB)\n", prefix, mem->offset, mem->end - 1, mem->name, - mem->size / 1024, tile_suffix); + mem->size / 1024); } else { xf86DrvMsgVerb(scrn->scrnIndex, X_INFO, verbosity, - "%sunpinned : %s (%ld kB)%s\n", prefix, - mem->name, mem->size / 1024, tile_suffix); + "%sunpinned : %s (%ld kB)\n", prefix, + mem->name, mem->size / 1024); } } if (intel->memory_manager) { @@ -953,7 +859,7 @@ static Bool i830_allocate_overlay(ScrnInfoPtr scrn) } intel->overlay_regs = i830_allocate_memory(scrn, "overlay registers", - OVERLAY_SIZE, PITCH_NONE, GTT_PAGE_SIZE, flags, TILE_NONE); + OVERLAY_SIZE, PITCH_NONE, GTT_PAGE_SIZE, flags); if (intel->overlay_regs == NULL) { xf86DrvMsg(scrn->scrnIndex, X_WARNING, "Failed to allocate Overlay register space.\n"); @@ -967,37 +873,12 @@ static Bool i830_allocate_overlay(ScrnInfoPtr scrn) return TRUE; } -static Bool IsTileable(ScrnInfoPtr scrn, int pitch) +/* + * Pad to accelerator requirement + */ +static inline int intel_pad_drawable_width(int width) { - intel_screen_private *intel = intel_get_screen_private(scrn); - - if (IS_I965G(intel)) { - if (pitch / 512 * 512 == pitch && pitch <= KB(128)) - return TRUE; - else - return FALSE; - } - - /* - * Allow tiling for pitches that are a power of 2 multiple of 128 bytes, - * up to 64 * 128 (= 8192) bytes. - */ - switch (pitch) { - case 128: - case 256: - if (IS_I945G(intel) || IS_I945GM(intel) || IS_G33CLASS(intel)) - return TRUE; - else - return FALSE; - case 512: - case KB(1): - case KB(2): - case KB(4): - case KB(8): - return TRUE; - default: - return FALSE; - } + return ALIGN(width, 64); } /** @@ -1006,66 +887,109 @@ static Bool IsTileable(ScrnInfoPtr scrn, int pitch) * Used once for each X screen, so once with RandR 1.2 and twice with classic * dualhead. */ -i830_memory *i830_allocate_framebuffer(ScrnInfoPtr scrn) +drm_intel_bo *intel_allocate_framebuffer(ScrnInfoPtr scrn, + int width, int height, int cpp, + unsigned long *out_pitch, + uint32_t *out_tiling) { intel_screen_private *intel = intel_get_screen_private(scrn); - unsigned int pitch = scrn->displayWidth * intel->cpp; - unsigned long minspace; - int align; - long size, fb_height; - int flags; - i830_memory *front_buffer = NULL; - enum tile_format tile_format = TILE_NONE; - - flags = ALLOW_SHARING | DISABLE_REUSE; - - /* We'll allocate the fb such that the root window will fit regardless of - * rotation. - */ - fb_height = scrn->virtualY; - - /* Calculate how much framebuffer memory to allocate. For the - * initial allocation, calculate a reasonable minimum. This is - * enough for the virtual screen size. - */ - minspace = pitch * scrn->virtualY; + drm_intel_bo *front_buffer; + uint32_t tiling_mode; + unsigned long pitch; - size = ROUND_TO_PAGE(pitch * fb_height); - - if (intel->tiling) - tile_format = TILE_XMAJOR; - - if (!IsTileable(scrn, pitch)) - tile_format = TILE_NONE; - - if (!i830_check_display_stride(scrn, pitch, tile_format != TILE_NONE)) { + if (intel->tiling & INTEL_TILING_FB) + tiling_mode = I915_TILING_X; + else + tiling_mode = I915_TILING_NONE; + + width = intel_pad_drawable_width(width); + if (!intel_check_display_stride(scrn, width * intel->cpp, + tiling_mode != I915_TILING_NONE)) + tiling_mode = I915_TILING_NONE; + if (!intel_check_display_stride(scrn, width * intel->cpp, + tiling_mode != I915_TILING_NONE)) { xf86DrvMsg(scrn->scrnIndex, X_ERROR, - "Front buffer stride %d kB " - "exceed display limit\n", pitch / 1024); + "Expected front buffer stride %d kB " + "will exceed display limit\n", + width * intel->cpp / 1024); return NULL; } - /* Attempt to allocate it tiled first if we have page flipping on. */ - if (tile_format != TILE_NONE) { - /* XXX: probably not the case on 965 */ - if (IS_I9XX(intel)) - align = MB(1); - else - align = KB(512); - } else - align = KB(64); - front_buffer = i830_allocate_memory(scrn, "front buffer", size, - pitch, align, flags, tile_format); - +retry: + front_buffer = drm_intel_bo_alloc_tiled(intel->bufmgr, "front buffer", + width, height, intel->cpp, + &tiling_mode, &pitch, 0); if (front_buffer == NULL) { + if (tiling_mode != I915_TILING_NONE) { + tiling_mode = I915_TILING_NONE; + goto retry; + } xf86DrvMsg(scrn->scrnIndex, X_ERROR, "Failed to allocate framebuffer.\n"); return NULL; } - if (intel->FbBase && front_buffer->bound) - memset (intel->FbBase + front_buffer->offset, 0, size); - i830_set_gem_max_sizes(scrn); + if (!intel_check_display_stride(scrn, pitch, + tiling_mode != I915_TILING_NONE)) { + drm_intel_bo_unreference(front_buffer); + if (tiling_mode != I915_TILING_NONE) { + tiling_mode = I915_TILING_NONE; + goto retry; + } + + xf86DrvMsg(scrn->scrnIndex, X_ERROR, + "Front buffer stride %ld kB " + "exceeds display limit\n", pitch / 1024); + return NULL; + } + + if ((intel->tiling & INTEL_TILING_FB) && tiling_mode != I915_TILING_X) { + xf86DrvMsg(scrn->scrnIndex, X_WARNING, + "Failed to set tiling on frontbuffer.\n"); + } + + xf86DrvMsg(scrn->scrnIndex, X_INFO, + "Allocated new frame buffer %dx%d stride %ld, %s\n", + width, height, pitch, + tiling_mode == I915_TILING_NONE ? "untiled" : "tiled"); + + /* set up alignment for pinning. note that for tiled framebuffers + * the required alignment is the same as tiled alignment anyway + * so in that case we just set it to zero so the kernel can handle it. + */ + if (tiling_mode == I915_TILING_NONE) { + /* broadwater and crestline... */ + if (DEVICE_ID(intel->PciInfo) == 0x2a02 || + DEVICE_ID(intel->PciInfo) == 0x2a12 || + DEVICE_ID(intel->PciInfo) == 0x2972 || + DEVICE_ID(intel->PciInfo) == 0x2982 || + DEVICE_ID(intel->PciInfo) == 0x2992 || + DEVICE_ID(intel->PciInfo) == 0x29a2) + front_buffer->align = 128 * 1024; + else if (IS_I965G(intel)) + front_buffer->align = 4 * 1024; + else + front_buffer->align = 64 * 1024; + } else { + front_buffer->align = 0; + } + + /* pin it if we control the vt */ + if (!intel->use_drm_mode && scrn->vtSema) { + if (dri_bo_pin(front_buffer, front_buffer->align) != 0) { + xf86DrvMsg(scrn->scrnIndex, X_ERROR, + "Failed to pin new front buffer: %s", + strerror(errno)); + drm_intel_bo_unreference(front_buffer); + return NULL; + } + } + + drm_intel_bo_disable_reuse(front_buffer); + + intel_set_gem_max_sizes(scrn); + *out_pitch = pitch; + *out_tiling = tiling_mode; return front_buffer; } @@ -1095,7 +1019,7 @@ static Bool i830_allocate_cursor_buffers(ScrnInfoPtr scrn) HWCURSOR_SIZE_ARGB); intel->cursor_mem = i830_allocate_memory(scrn, "HW cursors", - size, PITCH_NONE, GTT_PAGE_SIZE, flags, TILE_NONE); + size, PITCH_NONE, GTT_PAGE_SIZE, flags); if (intel->cursor_mem != NULL) return TRUE; } @@ -1110,14 +1034,14 @@ static Bool i830_allocate_cursor_buffers(ScrnInfoPtr scrn) intel->cursor_mem_classic[i] = i830_allocate_memory(scrn, "Core cursor", HWCURSOR_SIZE, PITCH_NONE, GTT_PAGE_SIZE, - flags, TILE_NONE); + flags); if (!intel->cursor_mem_classic[i]) return FALSE; } intel->cursor_mem_argb[i] = i830_allocate_memory(scrn, "ARGB cursor", HWCURSOR_SIZE_ARGB, PITCH_NONE, - GTT_PAGE_SIZE, flags, TILE_NONE); + GTT_PAGE_SIZE, flags); if (!intel->cursor_mem_argb[i]) return FALSE; @@ -1125,73 +1049,6 @@ static Bool i830_allocate_cursor_buffers(ScrnInfoPtr scrn) return TRUE; } -static void i830_setup_fb_compression(ScrnInfoPtr scrn) -{ - intel_screen_private *intel = intel_get_screen_private(scrn); - unsigned long compressed_size; - unsigned long fb_height; - - if (scrn->virtualX > scrn->virtualY) - fb_height = scrn->virtualX; - else - fb_height = scrn->virtualY; - - /* Only mobile chips since 845 support this feature */ - if (!IS_MOBILE(intel)) { - intel->fb_compression = FALSE; - goto out; - } - - if (IS_GM45(intel)) { - /* Update i830_display.c too if compression ratio changes */ - compressed_size = fb_height * (scrn->displayWidth / 4); - } else { - compressed_size = MB(6); - } - - /* - * Compressed framebuffer limitations: - * - contiguous, physical, uncached memory - * - ideally as large as the front buffer(s), smaller sizes cache less - * - uncompressed buffer must be tiled w/pitch 2k-16k - * - uncompressed fb is <= 2048 in width, 0 mod 8 - * - uncompressed fb is <= 1536 in height, 0 mod 2 - * - compressed fb stride is <= uncompressed stride - * - SR display watermarks must be equal between 16bpp and 32bpp? - * - both compressed and line buffers must be in stolen memory - */ - intel->compressed_front_buffer = - i830_allocate_memory(scrn, "compressed frame buffer", - compressed_size, PITCH_NONE, - KB(4), NEED_PHYSICAL_ADDR, - TILE_NONE); - - if (!intel->compressed_front_buffer) { - intel->fb_compression = FALSE; - goto out; - } - - if (!IS_GM45(intel)) { - intel->compressed_ll_buffer = - i830_allocate_memory(scrn, "compressed ll buffer", - FBC_LL_SIZE + FBC_LL_PAD, - PITCH_NONE, KB(4), - NEED_PHYSICAL_ADDR, - TILE_NONE); - if (!intel->compressed_ll_buffer) { - i830_free_memory(scrn, intel->compressed_front_buffer); - intel->fb_compression = FALSE; - goto out; - } - } - -out: - if (!intel->fb_compression) - xf86DrvMsg(scrn->scrnIndex, X_WARNING, "Allocation error, framebuffer" - " compression disabled\n"); - - return; -} /* * Allocate memory for 2D operation. This includes the (front) framebuffer, * ring buffer, scratch memory, HW cursor. @@ -1199,6 +1056,10 @@ out: Bool i830_allocate_2d_memory(ScrnInfoPtr scrn) { intel_screen_private *intel = intel_get_screen_private(scrn); + int width = scrn->virtualX; + int height = scrn->virtualY; + unsigned long pitch; + uint32_t tiling; if (!intel->use_drm_mode) { if (!xf86AgpGARTSupported() || @@ -1212,9 +1073,6 @@ Bool i830_allocate_2d_memory(ScrnInfoPtr scrn) } } - if (intel->fb_compression) - i830_setup_fb_compression(scrn); - /* Next, allocate other fixed-size allocations we have. */ if (!i830_allocate_cursor_buffers(scrn)) { xf86DrvMsg(scrn->scrnIndex, X_ERROR, @@ -1225,9 +1083,19 @@ Bool i830_allocate_2d_memory(ScrnInfoPtr scrn) if (!intel->use_drm_mode) i830_allocate_overlay(scrn); - intel->front_buffer = i830_allocate_framebuffer(scrn); - if (intel->front_buffer == NULL) + intel->front_buffer = intel_allocate_framebuffer(scrn, + width, height, + intel->cpp, + &pitch, + &tiling); + if (intel->front_buffer == NULL) { + xf86DrvMsg(scrn->scrnIndex, X_ERROR, + "Couldn't allocate initial framebuffer.\n"); return FALSE; + } + intel->front_pitch = pitch; + intel->front_tiling = tiling; + scrn->displayWidth = pitch / intel->cpp; return TRUE; } @@ -1243,8 +1111,7 @@ i830_allocate_pwrctx(ScrnInfoPtr scrn) intel->power_context = i830_allocate_memory(scrn, "power context", PWRCTX_SIZE, PITCH_NONE, GTT_PAGE_SIZE, - NEED_LIFETIME_FIXED, - TILE_NONE); + NEED_LIFETIME_FIXED); if (!intel->power_context) { xf86DrvMsg(scrn->scrnIndex, X_WARNING, "Failed to allocate power context.\n"); @@ -1254,221 +1121,6 @@ i830_allocate_pwrctx(ScrnInfoPtr scrn) } /** - * Sets up tiled surface registers ("fences") for the hardware. - * - * The fences control automatic tiled address swizzling for CPU access of the - * framebuffer, and may be used in many rendering operations instead of - * manually supplying tiling enables per surface. - */ -static int -i830_set_tiling(ScrnInfoPtr scrn, unsigned int offset, - unsigned int pitch, unsigned int size, - enum tile_format tile_format) -{ - intel_screen_private *intel = intel_get_screen_private(scrn); - uint32_t val; - uint32_t fence_mask = 0; - unsigned int fence_pitch; - unsigned int max_fence; - unsigned int fence_nr; - - DPRINTF(PFX, "i830_set_tiling(): 0x%08x, %d, %d kByte\n", - offset, pitch, size / 1024); - - assert(tile_format != TILE_NONE); - - intel_sync(scrn); - - if (IS_I965G(intel)) - max_fence = FENCE_NEW_NR; - else - max_fence = FENCE_NR; - - for (fence_nr = 0; fence_nr < max_fence; fence_nr++) { - if (!intel->fence_used[fence_nr]) - break; - } - if (fence_nr == max_fence) - FatalError("Ran out of fence registers at %d\n", fence_nr); - - intel->fence_used[fence_nr] = TRUE; - - if (IS_I965G(intel)) { - uint32_t fence_start, fence_end; - - switch (tile_format) { - case TILE_XMAJOR: - fence_start = (((pitch / 128) - 1) << 2) | offset | 1; - fence_start |= I965_FENCE_X_MAJOR; - break; - case TILE_YMAJOR: - /* YMajor can be 128B aligned but the current code dictates - * otherwise. This isn't a problem apart from memory waste. - * FIXME */ - fence_start = (((pitch / 128) - 1) << 2) | offset | 1; - fence_start |= I965_FENCE_Y_MAJOR; - break; - default: - return -1; - } - - /* The end marker is the address of the last page in the allocation. */ - fence_end = offset + size - 4096; - - OUTREG(FENCE_NEW + fence_nr * 8, fence_start); - OUTREG(FENCE_NEW + fence_nr * 8 + 4, fence_end); - } else { - if (IS_I9XX(intel)) - fence_mask = ~I915G_FENCE_START_MASK; - else - fence_mask = ~I830_FENCE_START_MASK; - - if (offset & fence_mask) { - FatalError("i830_set_tiling(): %d: offset (0x%08x) is not %s " - "aligned\n", - fence_nr, offset, (IS_I9XX(intel)) ? "1MB" : "512k"); - } - - if (offset % size) { - FatalError("i830_set_tiling(): %d: offset (0x%08x) is not " - "size (%dk) aligned\n", - fence_nr, offset, size / 1024); - } - - if (pitch & 127) { - FatalError("i830_set_tiling(): %d: pitch (%d) not a multiple of " - "128 bytes\n", - fence_nr, pitch); - } - - val = offset | FENCE_VALID; - - switch (tile_format) { - case TILE_XMAJOR: - val |= FENCE_X_MAJOR; - break; - case TILE_YMAJOR: - val |= FENCE_Y_MAJOR; - break; - case TILE_NONE: - break; - } - - if (IS_I9XX(intel)) { - switch (size) { - case MB(1): - val |= I915G_FENCE_SIZE_1M; - break; - case MB(2): - val |= I915G_FENCE_SIZE_2M; - break; - case MB(4): - val |= I915G_FENCE_SIZE_4M; - break; - case MB(8): - val |= I915G_FENCE_SIZE_8M; - break; - case MB(16): - val |= I915G_FENCE_SIZE_16M; - break; - case MB(32): - val |= I915G_FENCE_SIZE_32M; - break; - case MB(64): - val |= I915G_FENCE_SIZE_64M; - break; - default: - FatalError("i830_set_tiling(): %d: illegal size (%d kByte)\n", - fence_nr, size / 1024); - } - } else { - switch (size) { - case KB(512): - val |= FENCE_SIZE_512K; - break; - case MB(1): - val |= FENCE_SIZE_1M; - break; - case MB(2): - val |= FENCE_SIZE_2M; - break; - case MB(4): - val |= FENCE_SIZE_4M; - break; - case MB(8): - val |= FENCE_SIZE_8M; - break; - case MB(16): - val |= FENCE_SIZE_16M; - break; - case MB(32): - val |= FENCE_SIZE_32M; - break; - case MB(64): - val |= FENCE_SIZE_64M; - break; - default: - FatalError("i830_set_tiling(): %d: illegal size (%d kByte)\n", - fence_nr, size / 1024); - } - } - - if ((IS_I945G(intel) || IS_I945GM(intel) || IS_G33CLASS(intel)) && - tile_format == TILE_YMAJOR) - fence_pitch = pitch / 128; - else if (IS_I9XX(intel)) - fence_pitch = pitch / 512; - else - fence_pitch = pitch / 128; - - switch (fence_pitch) { - case 1: - val |= FENCE_PITCH_1; - break; - case 2: - val |= FENCE_PITCH_2; - break; - case 4: - val |= FENCE_PITCH_4; - break; - case 8: - val |= FENCE_PITCH_8; - break; - case 16: - val |= FENCE_PITCH_16; - break; - case 32: - val |= FENCE_PITCH_32; - break; - case 64: - val |= FENCE_PITCH_64; - break; - default: - FatalError("i830_set_tiling(): %d: illegal pitch (%d)\n", - fence_nr, pitch); - } - - OUTREG(FENCE + fence_nr * 4, val); - } - - return fence_nr; -} - -static void -i830_clear_tiling(ScrnInfoPtr scrn, unsigned int fence_nr) -{ - intel_screen_private *intel = intel_get_screen_private(scrn); - - if (IS_I965G(intel)) { - OUTREG(FENCE_NEW + fence_nr * 8, 0); - OUTREG(FENCE_NEW + fence_nr * 8 + 4, 0); - } else { - OUTREG(FENCE + fence_nr * 4, 0); - } - intel->fence_used[fence_nr] = FALSE; -} - -/** * Called at EnterVT to grab the AGP GART and bind our allocations. * * In zaphod mode, this will walk the list trying to bind twice, since each @@ -1479,12 +1131,38 @@ Bool i830_bind_all_memory(ScrnInfoPtr scrn) { intel_screen_private *intel = intel_get_screen_private(scrn); + if (!intel->use_drm_mode) { + xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(scrn); + int i; + + if (intel->front_buffer) { + if (dri_bo_pin(intel->front_buffer, + intel->front_buffer->align) != 0) { + FatalError("Couldn't bind memory for front buffer: %s\n", + strerror(errno)); + } + } + + for (i = 0; i < xf86_config->num_crtc; i++) { + xf86CrtcPtr crtc = xf86_config->crtc[i]; + I830CrtcPrivatePtr intel_crtc = crtc->driver_private; + + if (intel_crtc->rotate_bo) { + if (dri_bo_pin(intel_crtc->rotate_bo, + intel_crtc->rotate_bo->align) != 0) + FatalError("Couldn't bind memory for " + "front buffer: %s\n", + strerror(errno)); + } + } + } + if (intel->memory_list == NULL) return TRUE; if (intel->use_drm_mode || (xf86AgpGARTSupported() && !intel->gtt_acquired)) { - i830_memory *mem; + intel_memory *mem; if (!intel->use_drm_mode) { if (!xf86AcquireGART(scrn->scrnIndex)) @@ -1517,10 +1195,7 @@ Bool i830_bind_all_memory(ScrnInfoPtr scrn) intel->cursor_mem_argb[i]->bo); } else i830_update_cursor_offsets(scrn); - i830_set_gem_max_sizes(scrn); - - if (intel->front_buffer) - scrn->fbOffset = intel->front_buffer->offset; + intel_set_gem_max_sizes(scrn); return TRUE; } @@ -1533,7 +1208,23 @@ i830_unbind_all_memory(ScrnInfoPtr scrn) if (intel->use_drm_mode || (xf86AgpGARTSupported() && intel->gtt_acquired)) { - i830_memory *mem; + intel_memory *mem; + + if (!intel->use_drm_mode) { + xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(scrn); + int i; + + if (intel->front_buffer) + dri_bo_unpin(intel->front_buffer); + + for (i = 0; i < xf86_config->num_crtc; i++) { + xf86CrtcPtr crtc = xf86_config->crtc[i]; + I830CrtcPrivatePtr intel_crtc = crtc->driver_private; + + if (intel_crtc->rotate_bo) + dri_bo_unpin(intel_crtc->rotate_bo); + } + } for (mem = intel->memory_list->next; mem->next != NULL; mem = mem->next) @@ -1582,52 +1273,7 @@ I830CheckAvailableMemory(ScrnInfoPtr scrn) return maxPages * 4; } -#ifdef INTEL_XVMC -/* - * Allocate memory for MC compensation - */ -Bool i830_allocate_xvmc_buffer(ScrnInfoPtr scrn, const char *name, - i830_memory ** buffer, unsigned long size, - int flags) -{ - intel_screen_private *intel = intel_get_screen_private(scrn); - - *buffer = i830_allocate_memory(scrn, name, size, PITCH_NONE, - GTT_PAGE_SIZE, flags, TILE_NONE); - - if (!*buffer) { - xf86DrvMsg(scrn->scrnIndex, X_ERROR, - "Failed to allocate memory for %s.\n", name); - return FALSE; - } - - if (intel->use_drm_mode && (*buffer)->bo) { - if (drm_intel_bo_pin((*buffer)->bo, GTT_PAGE_SIZE)) { - i830_free_memory(scrn, *buffer); - xf86DrvMsg(scrn->scrnIndex, X_ERROR, - "Failed to bind XvMC buffer bo!\n"); - return FALSE; - } - - (*buffer)->offset = (*buffer)->bo->offset; - } - - return TRUE; -} - -void i830_free_xvmc_buffer(ScrnInfoPtr scrn, i830_memory * buffer) -{ - intel_screen_private *intel = intel_get_screen_private(scrn); - - if (intel->use_drm_mode && buffer->bo) - drm_intel_bo_unpin(buffer->bo); - - i830_free_memory(scrn, buffer); -} - -#endif - -static void i830_set_max_bo_size(intel_screen_private *intel, +static void intel_set_max_bo_size(intel_screen_private *intel, const struct drm_i915_gem_get_aperture *aperture) { if (aperture->aper_available_size) @@ -1641,7 +1287,7 @@ static void i830_set_max_bo_size(intel_screen_private *intel, intel->max_bo_size = 64 * 1024 * 1024; } -static void i830_set_max_gtt_map_size(intel_screen_private *intel, +static void intel_set_max_gtt_map_size(intel_screen_private *intel, const struct drm_i915_gem_get_aperture *aperture) { if (aperture->aper_available_size) @@ -1655,7 +1301,7 @@ static void i830_set_max_gtt_map_size(intel_screen_private *intel, intel->max_gtt_map_size = 16 * 1024 * 1024; } -static void i830_set_max_tiling_size(intel_screen_private *intel, +static void intel_set_max_tiling_size(intel_screen_private *intel, const struct drm_i915_gem_get_aperture *aperture) { if (aperture->aper_available_size) @@ -1667,15 +1313,22 @@ static void i830_set_max_tiling_size(intel_screen_private *intel, intel->max_tiling_size = 4 * 1024 * 1024; } -void i830_set_gem_max_sizes(ScrnInfoPtr scrn) +void intel_set_gem_max_sizes(ScrnInfoPtr scrn) { intel_screen_private *intel = intel_get_screen_private(scrn); struct drm_i915_gem_get_aperture aperture; + drm_i915_getparam_t gp; + int ret, value; aperture.aper_available_size = 0; - ioctl(intel->drmSubFD, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture); + drmIoctl(intel->drmSubFD, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture); + + intel_set_max_bo_size(intel, &aperture); + intel_set_max_gtt_map_size(intel, &aperture); + intel_set_max_tiling_size(intel, &aperture); - i830_set_max_bo_size(intel, &aperture); - i830_set_max_gtt_map_size(intel, &aperture); - i830_set_max_tiling_size(intel, &aperture); + gp.value = &value; + gp.param = I915_PARAM_HAS_RELAXED_FENCING; + ret = drmIoctl(intel->drmSubFD, DRM_IOCTL_I915_GETPARAM, &gp); + intel->has_relaxed_fencing = ret == 0; } diff --git a/driver/xf86-video-intel/src/intel_module.c b/driver/xf86-video-intel/src/intel_module.c new file mode 100644 index 000000000..0a059de05 --- /dev/null +++ b/driver/xf86-video-intel/src/intel_module.c @@ -0,0 +1,385 @@ +/* + * Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas. + * All Rights Reserved. + * Copyright © 2010 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include "xf86.h" +#include "xf86_OSproc.h" +#include "xf86cmap.h" + +#include "common.h" +#include "intel.h" +#include "intel_driver.h" +#include "legacy/legacy.h" + + +static struct intel_device_info *chipset_info; + +static const struct intel_device_info intel_i81x_info = { + .gen = 10, +}; + +static const struct intel_device_info intel_i8xx_info = { + .gen = 20, +}; + +static const struct intel_device_info intel_i915_info = { + .gen = 30, +}; + +static const struct intel_device_info intel_g33_info = { + .gen = 33, +}; + +static const struct intel_device_info intel_i965_info = { + .gen = 40, +}; + +static const struct intel_device_info intel_g4x_info = { + .gen = 45, +}; + +static const struct intel_device_info intel_ironlake_info = { + .gen = 50, +}; + +static const struct intel_device_info intel_sandybridge_info = { + .gen = 60, +}; + +static const struct intel_device_info intel_ivybridge_info = { + .gen = 70, +}; + +static const SymTabRec _intel_chipsets[] = { + {PCI_CHIP_I810, "i810"}, + {PCI_CHIP_I810_DC100, "i810-dc100"}, + {PCI_CHIP_I810_E, "i810e"}, + {PCI_CHIP_I815, "i815"}, + {PCI_CHIP_I830_M, "i830M"}, + {PCI_CHIP_845_G, "845G"}, + {PCI_CHIP_I854, "854"}, + {PCI_CHIP_I855_GM, "852GM/855GM"}, + {PCI_CHIP_I865_G, "865G"}, + {PCI_CHIP_I915_G, "915G"}, + {PCI_CHIP_E7221_G, "E7221 (i915)"}, + {PCI_CHIP_I915_GM, "915GM"}, + {PCI_CHIP_I945_G, "945G"}, + {PCI_CHIP_I945_GM, "945GM"}, + {PCI_CHIP_I945_GME, "945GME"}, + {PCI_CHIP_PINEVIEW_M, "Pineview GM"}, + {PCI_CHIP_PINEVIEW_G, "Pineview G"}, + {PCI_CHIP_I965_G, "965G"}, + {PCI_CHIP_G35_G, "G35"}, + {PCI_CHIP_I965_Q, "965Q"}, + {PCI_CHIP_I946_GZ, "946GZ"}, + {PCI_CHIP_I965_GM, "965GM"}, + {PCI_CHIP_I965_GME, "965GME/GLE"}, + {PCI_CHIP_G33_G, "G33"}, + {PCI_CHIP_Q35_G, "Q35"}, + {PCI_CHIP_Q33_G, "Q33"}, + {PCI_CHIP_GM45_GM, "GM45"}, + {PCI_CHIP_G45_E_G, "4 Series"}, + {PCI_CHIP_G45_G, "G45/G43"}, + {PCI_CHIP_Q45_G, "Q45/Q43"}, + {PCI_CHIP_G41_G, "G41"}, + {PCI_CHIP_B43_G, "B43"}, + {PCI_CHIP_B43_G1, "B43"}, + {PCI_CHIP_IRONLAKE_D_G, "Clarkdale"}, + {PCI_CHIP_IRONLAKE_M_G, "Arrandale"}, +#if 0 + {PCI_CHIP_SANDYBRIDGE_GT1, "Sandybridge Desktop (GT1)" }, + {PCI_CHIP_SANDYBRIDGE_GT2, "Sandybridge Desktop (GT2)" }, + {PCI_CHIP_SANDYBRIDGE_GT2_PLUS, "Sandybridge Desktop (GT2+)" }, + {PCI_CHIP_SANDYBRIDGE_M_GT1, "Sandybridge Mobile (GT1)" }, + {PCI_CHIP_SANDYBRIDGE_M_GT2, "Sandybridge Mobile (GT2)" }, + {PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS, "Sandybridge Mobile (GT2+)" }, + {PCI_CHIP_SANDYBRIDGE_S_GT, "Sandybridge Server" }, + {PCI_CHIP_IVYBRIDGE_M_GT1, "Ivybridge Mobile (GT1)" }, + {PCI_CHIP_IVYBRIDGE_M_GT2, "Ivybridge Mobile (GT2)" }, + {PCI_CHIP_IVYBRIDGE_D_GT1, "Ivybridge Desktop (GT1)" }, + {PCI_CHIP_IVYBRIDGE_D_GT2, "Ivybridge Desktop (GT2)" }, + {PCI_CHIP_IVYBRIDGE_S_GT1, "Ivybridge Server" }, +#endif + {-1, NULL} +}; +SymTabRec *intel_chipsets = (SymTabRec *) _intel_chipsets; + +#define INTEL_DEVICE_MATCH(d,i) \ + { 0x8086, (d), PCI_MATCH_ANY, PCI_MATCH_ANY, 0, 0, (intptr_t)(i) } + +static const struct pci_id_match intel_device_match[] = { + INTEL_DEVICE_MATCH (PCI_CHIP_I810, &intel_i81x_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_I810_DC100, &intel_i81x_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_I810_E, &intel_i81x_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_I815, &intel_i81x_info ), + + INTEL_DEVICE_MATCH (PCI_CHIP_I830_M, &intel_i8xx_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_845_G, &intel_i8xx_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_I854, &intel_i8xx_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_I855_GM, &intel_i8xx_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_I865_G, &intel_i8xx_info ), + + INTEL_DEVICE_MATCH (PCI_CHIP_I915_G, &intel_i915_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_E7221_G, &intel_i915_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_I915_GM, &intel_i915_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_I945_G, &intel_i915_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_I945_GM, &intel_i915_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_I945_GME, &intel_i915_info ), + + INTEL_DEVICE_MATCH (PCI_CHIP_PINEVIEW_M, &intel_g33_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_PINEVIEW_G, &intel_g33_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_G33_G, &intel_g33_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_Q33_G, &intel_g33_info ), + /* Another marketing win: Q35 is another g33 device not a gen4 part + * like its G35 brethren. + */ + INTEL_DEVICE_MATCH (PCI_CHIP_Q35_G, &intel_g33_info ), + + INTEL_DEVICE_MATCH (PCI_CHIP_I965_G, &intel_i965_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_G35_G, &intel_i965_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_I965_Q, &intel_i965_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_I946_GZ, &intel_i965_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_I965_GM, &intel_i965_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_I965_GME, &intel_i965_info ), + + INTEL_DEVICE_MATCH (PCI_CHIP_GM45_GM, &intel_g4x_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_G45_E_G, &intel_g4x_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_G45_G, &intel_g4x_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_Q45_G, &intel_g4x_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_G41_G, &intel_g4x_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_B43_G, &intel_g4x_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_B43_G1, &intel_g4x_info ), + + INTEL_DEVICE_MATCH (PCI_CHIP_IRONLAKE_D_G, &intel_ironlake_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_IRONLAKE_M_G, &intel_ironlake_info ), + +#if 0 + INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT1, &intel_sandybridge_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT2, &intel_sandybridge_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT2_PLUS, &intel_sandybridge_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT1, &intel_sandybridge_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT2, &intel_sandybridge_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS, &intel_sandybridge_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_S_GT, &intel_sandybridge_info ), + + INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_M_GT1, &intel_ivybridge_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_M_GT2, &intel_ivybridge_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_D_GT1, &intel_ivybridge_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_D_GT2, &intel_ivybridge_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_S_GT1, &intel_ivybridge_info ), +#endif + + { 0, 0, 0 }, +}; + +void intel_detect_chipset(ScrnInfoPtr scrn, + struct pci_device *pci, + struct intel_chipset *chipset) +{ + int i; + + chipset->info = chipset_info; + + for (i = 0; intel_chipsets[i].name != NULL; i++) { + if (DEVICE_ID(pci) == intel_chipsets[i].token) { + chipset->name = intel_chipsets[i].name; + break; + } + } + if (intel_chipsets[i].name == NULL) { + chipset->name = "unknown chipset"; + } + + xf86DrvMsg(scrn->scrnIndex, X_INFO, + "Integrated Graphics Chipset: Intel(R) %s\n", chipset->name); +} + +/* + * intel_identify -- + * + * Returns the string name for the driver based on the chipset. + * + */ +static void intel_identify(int flags) +{ + xf86PrintChipsets(INTEL_NAME, + "Driver for Intel Integrated Graphics Chipsets", + intel_chipsets); +} + +static Bool intel_driver_func(ScrnInfoPtr pScrn, + xorgDriverFuncOp op, + pointer ptr) +{ + xorgHWFlags *flag; + + switch (op) { + case GET_REQUIRED_HW_INTERFACES: + flag = (CARD32*)ptr; +#ifdef KMS_ONLY + (*flag) = 0; +#else + (*flag) = HW_IO | HW_MMIO; +#endif + return TRUE; + default: + /* Unknown or deprecated function */ + return FALSE; + } +} + +/* + * intel_pci_probe -- + * + * Look through the PCI bus to find cards that are intel boards. + * Setup the dispatch table for the rest of the driver functions. + * + */ +static Bool intel_pci_probe(DriverPtr driver, + int entity_num, + struct pci_device *device, + intptr_t match_data) +{ + ScrnInfoPtr scrn; + PciChipsets intel_pci_chipsets[ARRAY_SIZE(intel_chipsets)]; + int i; + + chipset_info = (void *)match_data; + + + for (i = 0; i < ARRAY_SIZE(intel_chipsets); i++) { + intel_pci_chipsets[i].numChipset = intel_chipsets[i].token; + intel_pci_chipsets[i].PCIid = intel_chipsets[i].token; + intel_pci_chipsets[i].dummy = NULL; + } + + scrn = xf86ConfigPciEntity(NULL, 0, entity_num, intel_pci_chipsets, + NULL, NULL, NULL, NULL, NULL); + if (scrn != NULL) { + scrn->driverVersion = INTEL_VERSION; + scrn->driverName = INTEL_DRIVER_NAME; + scrn->name = INTEL_NAME; + scrn->Probe = NULL; + +#if KMS_ONLY + intel_init_scrn(scrn); +#else + switch (DEVICE_ID(device)) { + case PCI_CHIP_I810: + case PCI_CHIP_I810_DC100: + case PCI_CHIP_I810_E: + case PCI_CHIP_I815: + lg_i810_init(scrn); + break; + + default: + intel_init_scrn(scrn); + break; + } +#endif + } + return scrn != NULL; +} + +#ifdef XFree86LOADER + +static MODULESETUPPROTO(intel_setup); + +static XF86ModuleVersionInfo intel_version = { + "intel", + MODULEVENDORSTRING, + MODINFOSTRING1, + MODINFOSTRING2, + XORG_VERSION_CURRENT, + INTEL_VERSION_MAJOR, INTEL_VERSION_MINOR, INTEL_VERSION_PATCH, + ABI_CLASS_VIDEODRV, + ABI_VIDEODRV_VERSION, + MOD_CLASS_VIDEODRV, + {0, 0, 0, 0} +}; + +static const OptionInfoRec * +intel_available_options(int chipid, int busid) +{ +#if KMS_ONLY + return intel_uxa_available_options(chipid, busid); +#else + switch (chipid) { + case PCI_CHIP_I810: + case PCI_CHIP_I810_DC100: + case PCI_CHIP_I810_E: + case PCI_CHIP_I815: + return lg_i810_available_options(chipid, busid); + + default: + return intel_uxa_available_options(chipid, busid); + } +#endif +} + +static DriverRec intel = { + INTEL_VERSION, + INTEL_DRIVER_NAME, + intel_identify, + NULL, + intel_available_options, + NULL, + 0, + intel_driver_func, + intel_device_match, + intel_pci_probe +}; + +static pointer intel_setup(pointer module, + pointer opts, + int *errmaj, + int *errmin) +{ + static Bool setupDone = 0; + + /* This module should be loaded only once, but check to be sure. + */ + if (!setupDone) { + setupDone = 1; + xf86AddDriver(&intel, module, HaveDriverFuncs); + + /* + * The return value must be non-NULL on success even though there + * is no TearDownProc. + */ + return (pointer) 1; + } else { + if (errmaj) + *errmaj = LDR_ONCEONLY; + return NULL; + } +} + +_X_EXPORT XF86ModuleData intelModuleData = { &intel_version, intel_setup, NULL }; +#endif diff --git a/driver/xf86-video-intel/src/intel_shadow.c b/driver/xf86-video-intel/src/intel_shadow.c new file mode 100644 index 000000000..b86530a9c --- /dev/null +++ b/driver/xf86-video-intel/src/intel_shadow.c @@ -0,0 +1,204 @@ +/************************************************************************** + +Copyright 2010 Intel Corporation +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sub license, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial portions +of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR +ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +*/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include "xf86.h" +#include "xaarop.h" +#include "intel.h" +#include "i830_reg.h" + +static dri_bo * +intel_shadow_create_bo(intel_screen_private *intel, + int16_t x1, int16_t y1, + int16_t x2, int16_t y2, + int *pitch) +{ + int w = x2 - x1, h = y2 - y1; + int size = h * w * intel->cpp; + dri_bo *bo; + + bo = drm_intel_bo_alloc(intel->bufmgr, "shadow", size, 0); + if (bo && drm_intel_gem_bo_map_gtt(bo) == 0) { + char *dst = bo->virtual; + char *src = intel->shadow_buffer; + int src_pitch = intel->shadow_stride; + int row_length = w * intel->cpp; + int num_rows = h; + src += y1 * src_pitch + x1 * intel->cpp; + do { + memcpy (dst, src, row_length); + src += src_pitch; + dst += row_length; + } while (--num_rows); + drm_intel_gem_bo_unmap_gtt(bo); + } + + *pitch = w * intel->cpp; + return bo; +} + +static void intel_shadow_memcpy(intel_screen_private *intel) +{ + char *src_data, *dst_data; + unsigned int src_pitch, dst_pitch; + RegionPtr region; + BoxPtr box; + int n; + + if (drm_intel_gem_bo_map_gtt(intel->front_buffer)) + return; + + src_data = intel->shadow_buffer; + dst_data = intel->front_buffer->virtual; + + src_pitch = intel->shadow_stride; + dst_pitch = intel->front_pitch; + + region = DamageRegion(intel->shadow_damage); + box = REGION_RECTS(region); + n = REGION_NUM_RECTS(region); + while (n--) { + char *src = src_data + box->y1*src_pitch + box->x1*intel->cpp; + char *dst = dst_data + box->y1*dst_pitch + box->x1*intel->cpp; + int len = (box->x2 - box->x1)*intel->cpp; + int row = box->y2 - box->y1; + while (row--) { + memcpy(dst, src, len); + src += src_pitch; + dst += dst_pitch; + } + box++; + } +} + +void intel_shadow_blt(intel_screen_private *intel) +{ + ScrnInfoPtr scrn = intel->scrn; + unsigned int dst_pitch; + uint32_t blt, br13; + RegionPtr region; + BoxPtr box; + int n; + + /* Can we trust the BLT? Otherwise do an uncached mmecy. */ + if (!intel->can_blt || IS_GEN2(intel)) { + intel_shadow_memcpy(intel); + return; + } + + dst_pitch = intel->front_pitch; + + blt = XY_SRC_COPY_BLT_CMD; + if (intel->cpp == 4) + blt |= (XY_SRC_COPY_BLT_WRITE_ALPHA | + XY_SRC_COPY_BLT_WRITE_RGB); + + if (INTEL_INFO(intel)->gen >= 40) { + if (intel->front_tiling) { + dst_pitch >>= 2; + blt |= XY_SRC_COPY_BLT_DST_TILED; + } + } + + br13 = ROP_S << 16 | dst_pitch; + switch (intel->cpp) { + default: + case 4: br13 |= 1 << 25; /* RGB8888 */ + case 2: br13 |= 1 << 24; /* RGB565 */ + case 1: break; + } + + region = DamageRegion(intel->shadow_damage); + box = REGION_RECTS(region); + n = REGION_NUM_RECTS(region); + while (n--) { + int pitch; + dri_bo *bo; + + bo = intel_shadow_create_bo(intel, + box->x1, box->y1, + box->x2, box->y2, + &pitch); + if (bo == NULL) + return; + + BEGIN_BATCH_BLT(8); + OUT_BATCH(blt); + OUT_BATCH(br13); + OUT_BATCH(box->y1 << 16 | box->x1); + OUT_BATCH(box->y2 << 16 | box->x2); + OUT_RELOC_FENCED(intel->front_buffer, + I915_GEM_DOMAIN_RENDER, + I915_GEM_DOMAIN_RENDER, + 0); + OUT_BATCH(0); + OUT_BATCH(pitch); + OUT_RELOC(bo, I915_GEM_DOMAIN_RENDER, 0, 0); + + ADVANCE_BATCH(); + + drm_intel_bo_unreference(bo); + box++; + } +} + +void intel_shadow_create(struct intel_screen_private *intel) +{ + ScrnInfoPtr scrn = intel->scrn; + ScreenPtr screen = scrn->pScreen; + PixmapPtr pixmap; + int stride; + void *buffer; + + pixmap = screen->GetScreenPixmap(screen); + stride = intel->cpp*scrn->virtualX; + buffer = malloc(stride * scrn->virtualY); + if (buffer && + screen->ModifyPixmapHeader(pixmap, + scrn->virtualX, scrn->virtualY, + -1, -1, + stride, buffer)) { + free(intel->shadow_buffer); + intel->shadow_buffer = buffer; + } else + stride = intel->shadow_stride; + + if (!intel->shadow_damage) { + intel->shadow_damage = + DamageCreate(NULL, NULL, + DamageReportNone, TRUE, + screen, intel); + DamageRegister(&pixmap->drawable, intel->shadow_damage); + DamageSetReportAfterOp(intel->shadow_damage, TRUE); + } + + scrn->displayWidth = stride / intel->cpp; + intel->shadow_stride = stride; +} diff --git a/driver/xf86-video-intel/src/i830_uxa.c b/driver/xf86-video-intel/src/intel_uxa.c index 03a013728..29b196191 100644 --- a/driver/xf86-video-intel/src/i830_uxa.c +++ b/driver/xf86-video-intel/src/intel_uxa.c @@ -33,15 +33,15 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "xf86.h" #include "xaarop.h" -#include "i830.h" -#include "i810_reg.h" +#include "intel.h" +#include "i830_reg.h" #include "i915_drm.h" #include "brw_defines.h" #include <string.h> #include <sys/mman.h> #include <errno.h> -const int I830CopyROP[16] = { +static const int I830CopyROP[16] = { ROP_0, /* GXclear */ ROP_DSa, /* GXand */ ROP_SDna, /* GXandReverse */ @@ -60,7 +60,7 @@ const int I830CopyROP[16] = { ROP_1 /* GXset */ }; -const int I830PatternROP[16] = { +static const int I830PatternROP[16] = { ROP_0, ROP_DPa, ROP_PDna, @@ -86,10 +86,16 @@ int uxa_pixmap_index; #endif static void -ironlake_blt_workaround(ScrnInfoPtr scrn) +gen6_context_switch(intel_screen_private *intel, + int new_mode) { - intel_screen_private *intel = intel_get_screen_private(scrn); + intel_batch_submit(intel->scrn); +} +static void +gen5_context_switch(intel_screen_private *intel, + int new_mode) +{ /* Ironlake has a limitation that a 3D or Media command can't * be the first command after a BLT, unless it's * non-pipelined. Instead of trying to track it and emit a @@ -97,17 +103,30 @@ ironlake_blt_workaround(ScrnInfoPtr scrn) * non-pipelined 3D instruction after each blit. */ - if (IS_IGDNG(intel)) { - BEGIN_BATCH(2); + if (new_mode == I915_EXEC_BLT) { + OUT_BATCH(MI_FLUSH | + MI_STATE_INSTRUCTION_CACHE_FLUSH | + MI_INHIBIT_RENDER_CACHE_FLUSH); + } else { OUT_BATCH(CMD_POLY_STIPPLE_OFFSET << 16); OUT_BATCH(0); - ADVANCE_BATCH(); + } +} + +static void +gen4_context_switch(intel_screen_private *intel, + int new_mode) +{ + if (new_mode == I915_EXEC_BLT) { + OUT_BATCH(MI_FLUSH | + MI_STATE_INSTRUCTION_CACHE_FLUSH | + MI_INHIBIT_RENDER_CACHE_FLUSH); } } Bool -i830_get_aperture_space(ScrnInfoPtr scrn, drm_intel_bo ** bo_table, - int num_bos) +intel_get_aperture_space(ScrnInfoPtr scrn, drm_intel_bo ** bo_table, + int num_bos) { intel_screen_private *intel = intel_get_screen_private(scrn); @@ -118,7 +137,7 @@ i830_get_aperture_space(ScrnInfoPtr scrn, drm_intel_bo ** bo_table, bo_table[0] = intel->batch_bo; if (drm_intel_bufmgr_check_aperture_space(bo_table, num_bos) != 0) { - intel_batch_submit(scrn, FALSE); + intel_batch_submit(scrn); bo_table[0] = intel->batch_bo; if (drm_intel_bufmgr_check_aperture_space(bo_table, num_bos) != 0) { @@ -130,25 +149,12 @@ i830_get_aperture_space(ScrnInfoPtr scrn, drm_intel_bo ** bo_table, return TRUE; } -static unsigned long i830_pixmap_pitch(PixmapPtr pixmap) -{ - return pixmap->devKind; -} - -static int i830_pixmap_pitch_is_aligned(PixmapPtr pixmap) -{ - ScrnInfoPtr scrn = xf86Screens[pixmap->drawable.pScreen->myNum]; - intel_screen_private *intel = intel_get_screen_private(scrn); - - return i830_pixmap_pitch(pixmap) % - intel->accel_pixmap_pitch_alignment == 0; -} - static unsigned int -i830_uxa_pixmap_compute_size(PixmapPtr pixmap, - int w, int h, - uint32_t *tiling, - int *stride) +intel_uxa_pixmap_compute_size(PixmapPtr pixmap, + int w, int h, + uint32_t *tiling, + int *stride, + unsigned usage) { ScrnInfoPtr scrn = xf86Screens[pixmap->drawable.pScreen->myNum]; intel_screen_private *intel = intel_get_screen_private(scrn); @@ -157,22 +163,26 @@ i830_uxa_pixmap_compute_size(PixmapPtr pixmap, if (*tiling != I915_TILING_NONE) { /* First check whether tiling is necessary. */ pitch = (w * pixmap->drawable.bitsPerPixel + 7) / 8; - pitch = ROUND_TO(pitch, intel->accel_pixmap_pitch_alignment); + pitch = ALIGN(pitch, 64); size = pitch * ALIGN (h, 2); - if (!IS_I965G(intel)) { - /* Older hardware requires fences to be pot size - * aligned with a minimum of 1 MiB, so causes - * massive overallocation for small textures. - */ - if (size < 1024*1024/2) - *tiling = I915_TILING_NONE; - + if (INTEL_INFO(intel)->gen < 40) { /* Gen 2/3 has a maximum stride for tiling of * 8192 bytes. */ if (pitch > KB(8)) *tiling = I915_TILING_NONE; - } else if (size <= 4096) { + + /* Narrower than half a tile? */ + if (pitch < 256) + *tiling = I915_TILING_NONE; + + /* Older hardware requires fences to be pot size + * aligned with a minimum of 1 MiB, so causes + * massive overallocation for small textures. + */ + if (size < 1024*1024/2 && !intel->has_relaxed_fencing) + *tiling = I915_TILING_NONE; + } else if (!(usage & INTEL_CREATE_PIXMAP_DRI2) && size <= 4096) { /* Disable tiling beneath a page size, we will not see * any benefit from reducing TLB misses and instead * just incur extra cost when we require a fence. @@ -182,20 +192,23 @@ i830_uxa_pixmap_compute_size(PixmapPtr pixmap, } pitch = (w * pixmap->drawable.bitsPerPixel + 7) / 8; - if (pitch <= 256) + if (!(usage & INTEL_CREATE_PIXMAP_DRI2) && pitch <= 256) *tiling = I915_TILING_NONE; if (*tiling != I915_TILING_NONE) { - int aligned_h; + int aligned_h, tile_height; - if (*tiling == I915_TILING_X) - aligned_h = ALIGN(h, 8); + if (IS_GEN2(intel)) + tile_height = 16; + else if (*tiling == I915_TILING_X) + tile_height = 8; else - aligned_h = ALIGN(h, 32); + tile_height = 32; + aligned_h = ALIGN(h, tile_height); - *stride = i830_get_fence_pitch(intel, - ROUND_TO(pitch, 512), - *tiling); + *stride = intel_get_fence_pitch(intel, + ALIGN(pitch, 512), + *tiling); /* Round the object up to the size of the fence it will live in * if necessary. We could potentially make the kernel allocate @@ -203,7 +216,7 @@ i830_uxa_pixmap_compute_size(PixmapPtr pixmap, * but this is easier and also keeps us out of trouble (as much) * with drm_intel_bufmgr_check_aperture(). */ - size = i830_get_fence_size(intel, *stride * aligned_h); + size = intel_get_fence_size(intel, *stride * aligned_h); if (size > intel->max_tiling_size) *tiling = I915_TILING_NONE; @@ -214,7 +227,7 @@ i830_uxa_pixmap_compute_size(PixmapPtr pixmap, * subspan doesn't address an invalid page offset beyond the * end of the GTT. */ - *stride = ROUND_TO(pitch, intel->accel_pixmap_pitch_alignment); + *stride = ALIGN(pitch, 64); size = *stride * ALIGN(h, 2); } @@ -222,7 +235,7 @@ i830_uxa_pixmap_compute_size(PixmapPtr pixmap, } static Bool -i830_uxa_check_solid(DrawablePtr drawable, int alu, Pixel planemask) +intel_uxa_check_solid(DrawablePtr drawable, int alu, Pixel planemask) { ScrnInfoPtr scrn = xf86Screens[drawable->pScreen->myNum]; @@ -247,24 +260,19 @@ i830_uxa_check_solid(DrawablePtr drawable, int alu, Pixel planemask) * Sets up hardware state for a series of solid fills. */ static Bool -i830_uxa_prepare_solid(PixmapPtr pixmap, int alu, Pixel planemask, Pixel fg) +intel_uxa_prepare_solid(PixmapPtr pixmap, int alu, Pixel planemask, Pixel fg) { ScrnInfoPtr scrn = xf86Screens[pixmap->drawable.pScreen->myNum]; intel_screen_private *intel = intel_get_screen_private(scrn); drm_intel_bo *bo_table[] = { NULL, /* batch_bo */ - i830_get_pixmap_bo(pixmap), + intel_get_pixmap_bo(pixmap), }; if (!intel_check_pitch_2d(pixmap)) return FALSE; - if (!i830_pixmap_pitch_is_aligned(pixmap)) { - intel_debug_fallback(scrn, "pixmap pitch not aligned"); - return FALSE; - } - - if (!i830_get_aperture_space(scrn, bo_table, ARRAY_SIZE(bo_table))) + if (!intel_get_aperture_space(scrn, bo_table, ARRAY_SIZE(bo_table))) return FALSE; intel->BR[13] = (I830PatternROP[alu] & 0xff) << 16; @@ -285,7 +293,7 @@ i830_uxa_prepare_solid(PixmapPtr pixmap, int alu, Pixel planemask, Pixel fg) return TRUE; } -static void i830_uxa_solid(PixmapPtr pixmap, int x1, int y1, int x2, int y2) +static void intel_uxa_solid(PixmapPtr pixmap, int x1, int y1, int x2, int y2) { ScrnInfoPtr scrn = xf86Screens[pixmap->drawable.pScreen->myNum]; intel_screen_private *intel = intel_get_screen_private(scrn); @@ -304,10 +312,10 @@ static void i830_uxa_solid(PixmapPtr pixmap, int x1, int y1, int x2, int y2) if (x2 <= x1 || y2 <= y1) return; - pitch = i830_pixmap_pitch(pixmap); + pitch = intel_pixmap_pitch(pixmap); { - BEGIN_BATCH(6); + BEGIN_BATCH_BLT(6); cmd = XY_COLOR_BLT_CMD; @@ -315,7 +323,7 @@ static void i830_uxa_solid(PixmapPtr pixmap, int x1, int y1, int x2, int y2) cmd |= XY_COLOR_BLT_WRITE_ALPHA | XY_COLOR_BLT_WRITE_RGB; - if (IS_I965G(intel) && i830_pixmap_tiled(pixmap)) { + if (INTEL_INFO(intel)->gen >= 40 && intel_pixmap_tiled(pixmap)) { assert((pitch % 512) == 0); pitch >>= 2; cmd |= XY_COLOR_BLT_TILED; @@ -331,15 +339,13 @@ static void i830_uxa_solid(PixmapPtr pixmap, int x1, int y1, int x2, int y2) OUT_BATCH(intel->BR[16]); ADVANCE_BATCH(); } - - ironlake_blt_workaround(scrn); } -static void i830_uxa_done_solid(PixmapPtr pixmap) +static void intel_uxa_done_solid(PixmapPtr pixmap) { ScrnInfoPtr scrn = xf86Screens[pixmap->drawable.pScreen->myNum]; - i830_debug_flush(scrn); + intel_debug_flush(scrn); } /** @@ -347,12 +353,10 @@ static void i830_uxa_done_solid(PixmapPtr pixmap) * - support planemask using FULL_BLT_CMD? */ static Bool -i830_uxa_check_copy(PixmapPtr source, PixmapPtr dest, +intel_uxa_check_copy(PixmapPtr source, PixmapPtr dest, int alu, Pixel planemask) { ScrnInfoPtr scrn = xf86Screens[dest->drawable.pScreen->myNum]; - intel_screen_private *intel = intel_get_screen_private(scrn); - if (!UXA_PM_IS_SOLID(&source->drawable, planemask)) { intel_debug_fallback(scrn, "planemask is not solid"); @@ -381,18 +385,18 @@ i830_uxa_check_copy(PixmapPtr source, PixmapPtr dest, } static Bool -i830_uxa_prepare_copy(PixmapPtr source, PixmapPtr dest, int xdir, +intel_uxa_prepare_copy(PixmapPtr source, PixmapPtr dest, int xdir, int ydir, int alu, Pixel planemask) { ScrnInfoPtr scrn = xf86Screens[dest->drawable.pScreen->myNum]; intel_screen_private *intel = intel_get_screen_private(scrn); drm_intel_bo *bo_table[] = { NULL, /* batch_bo */ - i830_get_pixmap_bo(source), - i830_get_pixmap_bo(dest), + intel_get_pixmap_bo(source), + intel_get_pixmap_bo(dest), }; - if (!i830_get_aperture_space(scrn, bo_table, ARRAY_SIZE(bo_table))) + if (!intel_get_aperture_space(scrn, bo_table, ARRAY_SIZE(bo_table))) return FALSE; intel->render_source = source; @@ -413,23 +417,50 @@ i830_uxa_prepare_copy(PixmapPtr source, PixmapPtr dest, int xdir, } static void -i830_uxa_copy(PixmapPtr dest, int src_x1, int src_y1, int dst_x1, +intel_uxa_copy(PixmapPtr dest, int src_x1, int src_y1, int dst_x1, int dst_y1, int w, int h) { ScrnInfoPtr scrn = xf86Screens[dest->drawable.pScreen->myNum]; intel_screen_private *intel = intel_get_screen_private(scrn); uint32_t cmd; - int dst_x2, dst_y2; + int dst_x2, dst_y2, src_x2, src_y2; unsigned int dst_pitch, src_pitch; dst_x2 = dst_x1 + w; dst_y2 = dst_y1 + h; - dst_pitch = i830_pixmap_pitch(dest); - src_pitch = i830_pixmap_pitch(intel->render_source); + /* XXX Fixup extents as a lamentable workaround for missing + * source clipping in the upper layers. + */ + if (dst_x1 < 0) + src_x1 -= dst_x1, dst_x1 = 0; + if (dst_y1 < 0) + src_y1 -= dst_y1, dst_y1 = 0; + if (dst_x2 > dest->drawable.width) + dst_x2 = dest->drawable.width; + if (dst_y2 > dest->drawable.height) + dst_y2 = dest->drawable.height; + + src_x2 = src_x1 + (dst_x2 - dst_x1); + src_y2 = src_y1 + (dst_y2 - dst_y1); + + if (src_x1 < 0) + dst_x1 -= src_x1, src_x1 = 0; + if (src_y1 < 0) + dst_y1 -= src_y1, src_y1 = 0; + if (src_x2 > intel->render_source->drawable.width) + dst_x2 -= src_x2 - intel->render_source->drawable.width; + if (src_y2 > intel->render_source->drawable.height) + dst_y2 -= src_y2 - intel->render_source->drawable.height; + + if (dst_x2 <= dst_x1 || dst_y2 <= dst_y1) + return; + + dst_pitch = intel_pixmap_pitch(dest); + src_pitch = intel_pixmap_pitch(intel->render_source); { - BEGIN_BATCH(8); + BEGIN_BATCH_BLT(8); cmd = XY_SRC_COPY_BLT_CMD; @@ -438,14 +469,14 @@ i830_uxa_copy(PixmapPtr dest, int src_x1, int src_y1, int dst_x1, XY_SRC_COPY_BLT_WRITE_ALPHA | XY_SRC_COPY_BLT_WRITE_RGB; - if (IS_I965G(intel)) { - if (i830_pixmap_tiled(dest)) { + if (INTEL_INFO(intel)->gen >= 40) { + if (intel_pixmap_tiled(dest)) { assert((dst_pitch % 512) == 0); dst_pitch >>= 2; cmd |= XY_SRC_COPY_BLT_DST_TILED; } - if (i830_pixmap_tiled(intel->render_source)) { + if (intel_pixmap_tiled(intel->render_source)) { assert((src_pitch % 512) == 0); src_pitch >>= 2; cmd |= XY_SRC_COPY_BLT_SRC_TILED; @@ -469,14 +500,13 @@ i830_uxa_copy(PixmapPtr dest, int src_x1, int src_y1, int dst_x1, ADVANCE_BATCH(); } - ironlake_blt_workaround(scrn); } -static void i830_uxa_done_copy(PixmapPtr dest) +static void intel_uxa_done_copy(PixmapPtr dest) { ScrnInfoPtr scrn = xf86Screens[dest->drawable.pScreen->myNum]; - i830_debug_flush(scrn); + intel_debug_flush(scrn); } /** @@ -484,7 +514,7 @@ static void i830_uxa_done_copy(PixmapPtr dest) * * This is shared between i830 through i965. */ -void i830_done_composite(PixmapPtr dest) +static void i830_done_composite(PixmapPtr dest) { ScrnInfoPtr scrn = xf86Screens[dest->drawable.pScreen->myNum]; intel_screen_private *intel = intel_get_screen_private(scrn); @@ -492,15 +522,15 @@ void i830_done_composite(PixmapPtr dest) if (intel->vertex_flush) intel->vertex_flush(intel); - i830_debug_flush(scrn); + intel_debug_flush(scrn); } #define xFixedToFloat(val) \ ((float)xFixedToInt(val) + ((float)xFixedFrac(val) / 65536.0)) static Bool -_i830_transform_point(PictTransformPtr transform, - float x, float y, float result[3]) +_intel_transform_point(PictTransformPtr transform, + float x, float y, float result[3]) { int j; @@ -520,8 +550,8 @@ _i830_transform_point(PictTransformPtr transform, * transform may be null. */ Bool -i830_get_transformed_coordinates(int x, int y, PictTransformPtr transform, - float *x_out, float *y_out) +intel_get_transformed_coordinates(int x, int y, PictTransformPtr transform, + float *x_out, float *y_out) { if (transform == NULL) { *x_out = x; @@ -529,8 +559,9 @@ i830_get_transformed_coordinates(int x, int y, PictTransformPtr transform, } else { float result[3]; - if (!_i830_transform_point - (transform, (float)x, (float)y, result)) + if (!_intel_transform_point(transform, + x, y, + result)) return FALSE; *x_out = result[0] / result[2]; *y_out = result[1] / result[2]; @@ -544,8 +575,8 @@ i830_get_transformed_coordinates(int x, int y, PictTransformPtr transform, * transform may be null. */ Bool -i830_get_transformed_coordinates_3d(int x, int y, PictTransformPtr transform, - float *x_out, float *y_out, float *w_out) +intel_get_transformed_coordinates_3d(int x, int y, PictTransformPtr transform, + float *x_out, float *y_out, float *w_out) { if (transform == NULL) { *x_out = x; @@ -554,8 +585,9 @@ i830_get_transformed_coordinates_3d(int x, int y, PictTransformPtr transform, } else { float result[3]; - if (!_i830_transform_point - (transform, (float)x, (float)y, result)) + if (!_intel_transform_point(transform, + x, y, + result)) return FALSE; *x_out = result[0]; *y_out = result[1]; @@ -569,31 +601,31 @@ i830_get_transformed_coordinates_3d(int x, int y, PictTransformPtr transform, * * transform may be null. */ -Bool i830_transform_is_affine(PictTransformPtr t) +Bool intel_transform_is_affine(PictTransformPtr t) { if (t == NULL) return TRUE; return t->matrix[2][0] == 0 && t->matrix[2][1] == 0; } -dri_bo *i830_get_pixmap_bo(PixmapPtr pixmap) +dri_bo *intel_get_pixmap_bo(PixmapPtr pixmap) { struct intel_pixmap *intel; - intel = i830_get_pixmap_intel(pixmap); + intel = intel_get_pixmap_private(pixmap); if (intel == NULL) return NULL; return intel->bo; } -void i830_set_pixmap_bo(PixmapPtr pixmap, dri_bo * bo) +void intel_set_pixmap_bo(PixmapPtr pixmap, dri_bo * bo) { ScrnInfoPtr scrn = xf86Screens[pixmap->drawable.pScreen->myNum]; intel_screen_private *intel = intel_get_screen_private(scrn); struct intel_pixmap *priv; - priv = i830_get_pixmap_intel(pixmap); + priv = intel_get_pixmap_private(pixmap); if (priv == NULL && bo == NULL) return; @@ -633,11 +665,9 @@ void i830_set_pixmap_bo(PixmapPtr pixmap, dri_bo * bo) dri_bo_reference(bo); priv->bo = bo; - priv->stride = i830_pixmap_pitch(pixmap); + priv->stride = intel_pixmap_pitch(pixmap); - ret = drm_intel_bo_get_tiling(bo, - &tiling, - &swizzle_mode); + ret = drm_intel_bo_get_tiling(bo, &tiling, &swizzle_mode); if (ret != 0) { FatalError("Couldn't get tiling on bo %p: %s\n", bo, strerror(-ret)); @@ -645,6 +675,7 @@ void i830_set_pixmap_bo(PixmapPtr pixmap, dri_bo * bo) priv->tiling = tiling; priv->busy = -1; + priv->offscreen = 1; } else { if (priv != NULL) { free(priv); @@ -653,39 +684,37 @@ void i830_set_pixmap_bo(PixmapPtr pixmap, dri_bo * bo) } BAIL: - i830_set_pixmap_intel(pixmap, priv); + intel_set_pixmap_private(pixmap, priv); } -static Bool i830_uxa_prepare_access(PixmapPtr pixmap, uxa_access_t access) +static Bool intel_uxa_pixmap_is_offscreen(PixmapPtr pixmap) +{ + struct intel_pixmap *priv = intel_get_pixmap_private(pixmap); + return priv && priv->offscreen; +} + +static Bool intel_uxa_prepare_access(PixmapPtr pixmap, uxa_access_t access) { ScrnInfoPtr scrn = xf86Screens[pixmap->drawable.pScreen->myNum]; intel_screen_private *intel = intel_get_screen_private(scrn); - struct intel_pixmap *priv = i830_get_pixmap_intel(pixmap); + struct intel_pixmap *priv = intel_get_pixmap_private(pixmap); dri_bo *bo = priv->bo; int ret; if (!list_is_empty(&priv->batch) && (access == UXA_ACCESS_RW || priv->batch_write)) - intel_batch_submit(scrn, FALSE); + intel_batch_submit(scrn); - if (bo->size > intel->max_gtt_map_size) { - ret = dri_bo_map(bo, access == UXA_ACCESS_RW); - if (ret != 0) { - xf86DrvMsg(scrn->scrnIndex, X_WARNING, - "%s: bo map failed: %s\n", - __FUNCTION__, - strerror(-ret)); - return FALSE; - } - } else { + if (priv->tiling || bo->size <= intel->max_gtt_map_size) ret = drm_intel_gem_bo_map_gtt(bo); - if (ret != 0) { - xf86DrvMsg(scrn->scrnIndex, X_WARNING, - "%s: gtt bo map failed: %s\n", - __FUNCTION__, - strerror(-ret)); - return FALSE; - } + else + ret = dri_bo_map(bo, access == UXA_ACCESS_RW); + if (ret) { + xf86DrvMsg(scrn->scrnIndex, X_WARNING, + "%s: bo map failed: %s\n", + __FUNCTION__, + strerror(-ret)); + return FALSE; } pixmap->devPrivate.ptr = bo->virtual; priv->busy = 0; @@ -693,36 +722,23 @@ static Bool i830_uxa_prepare_access(PixmapPtr pixmap, uxa_access_t access) return TRUE; } -static void i830_uxa_finish_access(PixmapPtr pixmap) +static Bool intel_uxa_pixmap_put_image(PixmapPtr pixmap, + char *src, int src_pitch, + int x, int y, int w, int h) { - dri_bo *bo = i830_get_pixmap_bo(pixmap); - ScreenPtr screen = pixmap->drawable.pScreen; - ScrnInfoPtr scrn = xf86Screens[screen->myNum]; - intel_screen_private *intel = intel_get_screen_private(scrn); - - if (bo == intel->front_buffer->bo) - intel->need_flush = TRUE; - - if (bo->size > intel->max_gtt_map_size) - dri_bo_unmap(bo); - else - drm_intel_gem_bo_unmap_gtt(bo); - pixmap->devPrivate.ptr = NULL; -} - -static Bool i830_uxa_pixmap_put_image(PixmapPtr pixmap, - char *src, int src_pitch, - int x, int y, int w, int h) -{ - struct intel_pixmap *priv = i830_get_pixmap_intel(pixmap); - int stride = i830_pixmap_pitch(pixmap); + struct intel_pixmap *priv = intel_get_pixmap_private(pixmap); + int stride = intel_pixmap_pitch(pixmap); + int cpp = pixmap->drawable.bitsPerPixel/8; int ret = FALSE; - if (src_pitch == stride && w == pixmap->drawable.width && priv->tiling == I915_TILING_NONE) { - ret = drm_intel_bo_subdata(priv->bo, y * stride, stride * h, src) == 0; + if (priv == NULL || priv->bo == NULL) + return FALSE; + + if (priv->tiling == I915_TILING_NONE && + (h == 1 || (src_pitch == stride && w == pixmap->drawable.width))) { + return drm_intel_bo_subdata(priv->bo, y*stride + x*cpp, stride*(h-1) + w*cpp, src) == 0; } else if (drm_intel_gem_bo_map_gtt(priv->bo) == 0) { char *dst = priv->bo->virtual; - int cpp = pixmap->drawable.bitsPerPixel/8; int row_length = w * cpp; int num_rows = h; if (row_length == src_pitch && src_pitch == stride) @@ -740,21 +756,22 @@ static Bool i830_uxa_pixmap_put_image(PixmapPtr pixmap, return ret; } -static Bool i830_uxa_put_image(PixmapPtr pixmap, - int x, int y, - int w, int h, - char *src, int src_pitch) +static Bool intel_uxa_put_image(PixmapPtr pixmap, + int x, int y, + int w, int h, + char *src, int src_pitch) { struct intel_pixmap *priv; - priv = i830_get_pixmap_intel(pixmap); + priv = intel_get_pixmap_private(pixmap); if (!intel_pixmap_is_busy(priv)) { /* bo is not busy so can be replaced without a stall, upload in-place. */ - return i830_uxa_pixmap_put_image(pixmap, src, src_pitch, x, y, w, h); + return intel_uxa_pixmap_put_image(pixmap, src, src_pitch, x, y, w, h); } else { ScreenPtr screen = pixmap->drawable.pScreen; - if (x == 0 && y == 0 && + if (!priv->pinned && + x == 0 && y == 0 && w == pixmap->drawable.width && h == pixmap->drawable.height) { @@ -764,8 +781,8 @@ static Bool i830_uxa_put_image(PixmapPtr pixmap, dri_bo *bo; /* Replace busy bo. */ - size = i830_uxa_pixmap_compute_size (pixmap, w, h, - &tiling, &stride); + size = intel_uxa_pixmap_compute_size (pixmap, w, h, + &tiling, &stride, 0); if (size > intel->max_gtt_map_size) return FALSE; @@ -775,15 +792,17 @@ static Bool i830_uxa_put_image(PixmapPtr pixmap, if (tiling != I915_TILING_NONE) drm_intel_bo_set_tiling(bo, &tiling, stride); + priv->stride = stride; + priv->tiling = tiling; screen->ModifyPixmapHeader(pixmap, w, h, 0, 0, stride, NULL); - i830_set_pixmap_bo(pixmap, bo); + intel_set_pixmap_bo(pixmap, bo); dri_bo_unreference(bo); - return i830_uxa_pixmap_put_image(pixmap, src, src_pitch, 0, 0, w, h); + return intel_uxa_pixmap_put_image(pixmap, src, src_pitch, 0, 0, w, h); } else { @@ -797,7 +816,12 @@ static Bool i830_uxa_put_image(PixmapPtr pixmap, if (!scratch) return FALSE; - ret = i830_uxa_pixmap_put_image(scratch, src, src_pitch, 0, 0, w, h); + if (!intel_uxa_pixmap_is_offscreen(scratch)) { + screen->DestroyPixmap(scratch); + return FALSE; + } + + ret = intel_uxa_pixmap_put_image(scratch, src, src_pitch, 0, 0, w, h); if (ret) { GCPtr gc = GetScratchGC(pixmap->drawable.depth, screen); if (gc) { @@ -818,23 +842,23 @@ static Bool i830_uxa_put_image(PixmapPtr pixmap, } } -static Bool i830_uxa_pixmap_get_image(PixmapPtr pixmap, - int x, int y, int w, int h, - char *dst, int dst_pitch) +static Bool intel_uxa_pixmap_get_image(PixmapPtr pixmap, + int x, int y, int w, int h, + char *dst, int dst_pitch) { - struct intel_pixmap *priv = i830_get_pixmap_intel(pixmap); - int stride = i830_pixmap_pitch(pixmap); + struct intel_pixmap *priv = intel_get_pixmap_private(pixmap); + int stride = intel_pixmap_pitch(pixmap); + int cpp = pixmap->drawable.bitsPerPixel/8; - if (dst_pitch == stride && w == pixmap->drawable.width) { - return drm_intel_bo_get_subdata(priv->bo, y * stride, stride * h, dst) == 0; + /* assert(priv->tiling == I915_TILING_NONE); */ + if (h == 1 || (dst_pitch == stride && w == pixmap->drawable.width)) { + return drm_intel_bo_get_subdata(priv->bo, y*stride + x*cpp, (h-1)*stride + w*cpp, dst) == 0; } else { char *src; - int cpp; - if (drm_intel_bo_map(priv->bo, FALSE)) + if (drm_intel_gem_bo_map_gtt(priv->bo)) return FALSE; - cpp = pixmap->drawable.bitsPerPixel/8; src = (char *) priv->bo->virtual + y * stride + x * cpp; w *= cpp; do { @@ -843,16 +867,16 @@ static Bool i830_uxa_pixmap_get_image(PixmapPtr pixmap, dst += dst_pitch; } while (--h); - drm_intel_bo_unmap(priv->bo); + drm_intel_gem_bo_unmap_gtt(priv->bo); return TRUE; } } -static Bool i830_uxa_get_image(PixmapPtr pixmap, - int x, int y, - int w, int h, - char *dst, int dst_pitch) +static Bool intel_uxa_get_image(PixmapPtr pixmap, + int x, int y, + int w, int h, + char *dst, int dst_pitch) { struct intel_pixmap *priv; PixmapPtr scratch = NULL; @@ -865,7 +889,7 @@ static Bool i830_uxa_get_image(PixmapPtr pixmap, * Also the gpu is much faster at detiling. */ - priv = i830_get_pixmap_intel(pixmap); + priv = intel_get_pixmap_private(pixmap); if (intel_pixmap_is_busy(priv) || priv->tiling != I915_TILING_NONE) { ScreenPtr screen = pixmap->drawable.pScreen; GCPtr gc; @@ -877,6 +901,11 @@ static Bool i830_uxa_get_image(PixmapPtr pixmap, if (!scratch) return FALSE; + if (!intel_uxa_pixmap_is_offscreen(scratch)) { + screen->DestroyPixmap(scratch); + return FALSE; + } + gc = GetScratchGC(pixmap->drawable.depth, screen); if (!gc) { screen->DestroyPixmap(scratch); @@ -891,46 +920,58 @@ static Bool i830_uxa_get_image(PixmapPtr pixmap, FreeScratchGC(gc); - intel_batch_submit(xf86Screens[screen->myNum], FALSE); + intel_batch_submit(xf86Screens[screen->myNum]); x = y = 0; pixmap = scratch; } - ret = i830_uxa_pixmap_get_image(pixmap, x, y, w, h, dst, dst_pitch); + ret = intel_uxa_pixmap_get_image(pixmap, x, y, w, h, dst, dst_pitch); if (scratch) scratch->drawable.pScreen->DestroyPixmap(scratch); return ret; - } -void i830_uxa_block_handler(ScreenPtr screen) +static void intel_flush_rendering(intel_screen_private *intel) { - ScrnInfoPtr scrn = xf86Screens[screen->myNum]; - intel_screen_private *intel = intel_get_screen_private(scrn); + if (intel->needs_flush == 0) + return; - if (intel->need_flush) { - dri_bo_wait_rendering(intel->front_buffer->bo); - intel->need_flush = FALSE; + if (intel->has_kernel_flush) { + intel_batch_submit(intel->scrn); + drm_intel_bo_busy(intel->front_buffer); + } else { + intel_batch_emit_flush(intel->scrn); + intel_batch_submit(intel->scrn); } + + intel->needs_flush = 0; } -static Bool i830_uxa_pixmap_is_offscreen(PixmapPtr pixmap) +void intel_uxa_block_handler(intel_screen_private *intel) { - ScreenPtr screen = pixmap->drawable.pScreen; - - /* The front buffer is always in memory and pinned */ - if (screen->GetScreenPixmap(screen) == pixmap) - return TRUE; + /* don't call this if switche,d doesn't matter and we won't complain + that way */ + if (!intel->scrn->vtSema) + return; + if (intel->shadow_damage && + pixman_region_not_empty(DamageRegion(intel->shadow_damage))) { + intel_shadow_blt(intel); + DamageEmpty(intel->shadow_damage); + } - return i830_get_pixmap_bo(pixmap) != NULL; + /* Emit a flush of the rendering cache, or on the 965 + * and beyond rendering results may not hit the + * framebuffer until significantly later. + */ + intel_flush_rendering(intel); } static PixmapPtr -i830_uxa_create_pixmap(ScreenPtr screen, int w, int h, int depth, - unsigned usage) +intel_uxa_create_pixmap(ScreenPtr screen, int w, int h, int depth, + unsigned usage) { ScrnInfoPtr scrn = xf86Screens[screen->myNum]; intel_screen_private *intel = intel_get_screen_private(scrn); @@ -939,7 +980,10 @@ i830_uxa_create_pixmap(ScreenPtr screen, int w, int h, int depth, if (w > 32767 || h > 32767) return NullPixmap; - if (depth == 1) + if (depth == 1 || intel->force_fallback) + return fbCreatePixmap(screen, w, h, depth, usage); + + if (intel->use_shadow && (usage & INTEL_CREATE_PIXMAP_DRI2) == 0) return fbCreatePixmap(screen, w, h, depth, usage); if (usage == CREATE_PIXMAP_USAGE_GLYPH_PICTURE && w <= 32 && h <= 32) @@ -957,18 +1001,22 @@ i830_uxa_create_pixmap(ScreenPtr screen, int w, int h, int depth, * to be effectively tiled. */ tiling = I915_TILING_X; - if (usage == INTEL_CREATE_PIXMAP_TILING_Y) + if (usage & INTEL_CREATE_PIXMAP_TILING_Y) tiling = I915_TILING_Y; - if (usage == UXA_CREATE_PIXMAP_FOR_MAP || usage == INTEL_CREATE_PIXMAP_TILING_NONE) + if (usage == UXA_CREATE_PIXMAP_FOR_MAP || usage & INTEL_CREATE_PIXMAP_TILING_NONE) tiling = I915_TILING_NONE; - if (tiling != I915_TILING_NONE) { + /* if tiling is off force to none */ + if (!intel->tiling) + tiling = I915_TILING_NONE; + + if (tiling != I915_TILING_NONE && !(usage & INTEL_CREATE_PIXMAP_DRI2)) { if (h <= 4) tiling = I915_TILING_NONE; if (h <= 16 && tiling == I915_TILING_Y) tiling = I915_TILING_X; } - size = i830_uxa_pixmap_compute_size(pixmap, w, h, &tiling, &stride); + size = intel_uxa_pixmap_compute_size(pixmap, w, h, &tiling, &stride, usage); /* Fail very large allocations. Large BOs will tend to hit SW fallbacks * frequently, and also will tend to fail to successfully map when doing @@ -1011,7 +1059,7 @@ i830_uxa_create_pixmap(ScreenPtr screen, int w, int h, int depth, list_del(&priv->in_flight); screen->ModifyPixmapHeader(pixmap, w, h, 0, 0, stride, NULL); - i830_set_pixmap_intel(pixmap, priv); + intel_set_pixmap_private(pixmap, priv); return pixmap; } } @@ -1044,40 +1092,108 @@ i830_uxa_create_pixmap(ScreenPtr screen, int w, int h, int depth, drm_intel_bo_set_tiling(priv->bo, &tiling, stride); priv->stride = stride; priv->tiling = tiling; + priv->offscreen = 1; screen->ModifyPixmapHeader(pixmap, w, h, 0, 0, stride, NULL); list_init(&priv->batch); list_init(&priv->flush); - i830_set_pixmap_intel(pixmap, priv); + intel_set_pixmap_private(pixmap, priv); } return pixmap; } -static Bool i830_uxa_destroy_pixmap(PixmapPtr pixmap) +static Bool intel_uxa_destroy_pixmap(PixmapPtr pixmap) { if (pixmap->refcnt == 1) - i830_set_pixmap_bo(pixmap, NULL); + intel_set_pixmap_bo(pixmap, NULL); fbDestroyPixmap(pixmap); return TRUE; } - -void i830_uxa_create_screen_resources(ScreenPtr screen) +Bool intel_uxa_create_screen_resources(ScreenPtr screen) { ScrnInfoPtr scrn = xf86Screens[screen->myNum]; intel_screen_private *intel = intel_get_screen_private(scrn); - dri_bo *bo = intel->front_buffer->bo; + dri_bo *bo = intel->front_buffer; - if (bo != NULL) { + if (!uxa_resources_init(screen)) + return FALSE; + + drm_intel_gem_bo_map_gtt(bo); + + if (intel->use_shadow) { + intel_shadow_create(intel); + } else { PixmapPtr pixmap = screen->GetScreenPixmap(screen); - i830_set_pixmap_bo(pixmap, bo); - i830_get_pixmap_intel(pixmap)->busy = 1; + intel_set_pixmap_bo(pixmap, bo); + intel_get_pixmap_private(pixmap)->pinned = 1; + screen->ModifyPixmapHeader(pixmap, + scrn->virtualX, + scrn->virtualY, + -1, -1, + intel->front_pitch, + NULL); + scrn->displayWidth = intel->front_pitch / intel->cpp; } + + return TRUE; } -Bool i830_uxa_init(ScreenPtr screen) +static void +intel_limits_init(intel_screen_private *intel) +{ + /* Limits are described in the BLT engine chapter under Graphics Data Size + * Limitations, and the descriptions of SURFACE_STATE, 3DSTATE_BUFFER_INFO, + * 3DSTATE_DRAWING_RECTANGLE, 3DSTATE_MAP_INFO, and 3DSTATE_MAP_INFO. + * + * i845 through i965 limits 2D rendering to 65536 lines and pitch of 32768. + * + * i965 limits 3D surface to (2*element size)-aligned offset if un-tiled. + * i965 limits 3D surface to 4kB-aligned offset if tiled. + * i965 limits 3D surfaces to w,h of ?,8192. + * i965 limits 3D surface to pitch of 1B - 128kB. + * i965 limits 3D surface pitch alignment to 1 or 2 times the element size. + * i965 limits 3D surface pitch alignment to 512B if tiled. + * i965 limits 3D destination drawing rect to w,h of 8192,8192. + * + * i915 limits 3D textures to 4B-aligned offset if un-tiled. + * i915 limits 3D textures to ~4kB-aligned offset if tiled. + * i915 limits 3D textures to width,height of 2048,2048. + * i915 limits 3D textures to pitch of 16B - 8kB, in dwords. + * i915 limits 3D destination to ~4kB-aligned offset if tiled. + * i915 limits 3D destination to pitch of 16B - 8kB, in dwords, if un-tiled. + * i915 limits 3D destination to pitch 64B-aligned if used with depth. + * i915 limits 3D destination to pitch of 512B - 8kB, in tiles, if tiled. + * i915 limits 3D destination to POT aligned pitch if tiled. + * i915 limits 3D destination drawing rect to w,h of 2048,2048. + * + * i845 limits 3D textures to 4B-aligned offset if un-tiled. + * i845 limits 3D textures to ~4kB-aligned offset if tiled. + * i845 limits 3D textures to width,height of 2048,2048. + * i845 limits 3D textures to pitch of 4B - 8kB, in dwords. + * i845 limits 3D destination to 4B-aligned offset if un-tiled. + * i845 limits 3D destination to ~4kB-aligned offset if tiled. + * i845 limits 3D destination to pitch of 8B - 8kB, in dwords. + * i845 limits 3D destination drawing rect to w,h of 2048,2048. + * + * For the tiled issues, the only tiled buffer we draw to should be + * the front, which will have an appropriate pitch/offset already set up, + * so UXA doesn't need to worry. + */ + if (INTEL_INFO(intel)->gen >= 40) { + intel->accel_pixmap_offset_alignment = 4 * 2; + intel->accel_max_x = 8192; + intel->accel_max_y = 8192; + } else { + intel->accel_pixmap_offset_alignment = 4; + intel->accel_max_x = 2048; + intel->accel_max_y = 2048; + } +} + +Bool intel_uxa_init(ScreenPtr screen) { ScrnInfoPtr scrn = xf86Screens[screen->myNum]; intel_screen_private *intel = intel_get_screen_private(scrn); @@ -1089,6 +1205,8 @@ Bool i830_uxa_init(ScreenPtr screen) #endif return FALSE; + intel_limits_init(intel); + intel->uxa_driver = uxa_driver_alloc(); if (intel->uxa_driver == NULL) return FALSE; @@ -1102,56 +1220,76 @@ Bool i830_uxa_init(ScreenPtr screen) intel->render_current_dest = NULL; intel->prim_offset = 0; intel->vertex_count = 0; + intel->vertex_offset = 0; + intel->vertex_used = 0; intel->floats_per_vertex = 0; intel->last_floats_per_vertex = 0; intel->vertex_bo = NULL; + intel->surface_used = 0; + intel->surface_reloc = 0; /* Solid fill */ - intel->uxa_driver->check_solid = i830_uxa_check_solid; - intel->uxa_driver->prepare_solid = i830_uxa_prepare_solid; - intel->uxa_driver->solid = i830_uxa_solid; - intel->uxa_driver->done_solid = i830_uxa_done_solid; + intel->uxa_driver->check_solid = intel_uxa_check_solid; + intel->uxa_driver->prepare_solid = intel_uxa_prepare_solid; + intel->uxa_driver->solid = intel_uxa_solid; + intel->uxa_driver->done_solid = intel_uxa_done_solid; /* Copy */ - intel->uxa_driver->check_copy = i830_uxa_check_copy; - intel->uxa_driver->prepare_copy = i830_uxa_prepare_copy; - intel->uxa_driver->copy = i830_uxa_copy; - intel->uxa_driver->done_copy = i830_uxa_done_copy; + intel->uxa_driver->check_copy = intel_uxa_check_copy; + intel->uxa_driver->prepare_copy = intel_uxa_prepare_copy; + intel->uxa_driver->copy = intel_uxa_copy; + intel->uxa_driver->done_copy = intel_uxa_done_copy; /* Composite */ - if (!IS_I9XX(intel)) { + if (IS_GEN2(intel)) { intel->uxa_driver->check_composite = i830_check_composite; intel->uxa_driver->check_composite_target = i830_check_composite_target; intel->uxa_driver->check_composite_texture = i830_check_composite_texture; intel->uxa_driver->prepare_composite = i830_prepare_composite; intel->uxa_driver->composite = i830_composite; intel->uxa_driver->done_composite = i830_done_composite; - } else if (IS_I915G(intel) || IS_I915GM(intel) || - IS_I945G(intel) || IS_I945GM(intel) || IS_G33CLASS(intel)) { + + intel->vertex_flush = i830_vertex_flush; + intel->batch_commit_notify = i830_batch_commit_notify; + } else if (IS_GEN3(intel)) { intel->uxa_driver->check_composite = i915_check_composite; intel->uxa_driver->check_composite_target = i915_check_composite_target; intel->uxa_driver->check_composite_texture = i915_check_composite_texture; intel->uxa_driver->prepare_composite = i915_prepare_composite; intel->uxa_driver->composite = i915_composite; intel->uxa_driver->done_composite = i830_done_composite; + + intel->vertex_flush = i915_vertex_flush; + intel->batch_commit_notify = i915_batch_commit_notify; } else { intel->uxa_driver->check_composite = i965_check_composite; intel->uxa_driver->check_composite_texture = i965_check_composite_texture; intel->uxa_driver->prepare_composite = i965_prepare_composite; intel->uxa_driver->composite = i965_composite; intel->uxa_driver->done_composite = i830_done_composite; + + intel->vertex_flush = i965_vertex_flush; + intel->batch_flush = i965_batch_flush; + intel->batch_commit_notify = i965_batch_commit_notify; + + if (IS_GEN4(intel)) { + intel->context_switch = gen4_context_switch; + } else if (IS_GEN5(intel)) { + intel->context_switch = gen5_context_switch; + } else { + intel->context_switch = gen6_context_switch; + } } /* PutImage */ - intel->uxa_driver->put_image = i830_uxa_put_image; - intel->uxa_driver->get_image = i830_uxa_get_image; + intel->uxa_driver->put_image = intel_uxa_put_image; + intel->uxa_driver->get_image = intel_uxa_get_image; - intel->uxa_driver->prepare_access = i830_uxa_prepare_access; - intel->uxa_driver->finish_access = i830_uxa_finish_access; - intel->uxa_driver->pixmap_is_offscreen = i830_uxa_pixmap_is_offscreen; + intel->uxa_driver->prepare_access = intel_uxa_prepare_access; + intel->uxa_driver->pixmap_is_offscreen = intel_uxa_pixmap_is_offscreen; - screen->CreatePixmap = i830_uxa_create_pixmap; - screen->DestroyPixmap = i830_uxa_destroy_pixmap; + screen->CreatePixmap = intel_uxa_create_pixmap; + screen->DestroyPixmap = intel_uxa_destroy_pixmap; if (!uxa_driver_init(screen, intel->uxa_driver)) { xf86DrvMsg(scrn->scrnIndex, X_ERROR, @@ -1161,6 +1299,7 @@ Bool i830_uxa_init(ScreenPtr screen) } uxa_set_fallback_debug(screen, intel->fallback_debug); + uxa_set_force_fallback(screen, intel->force_fallback); return TRUE; } diff --git a/driver/xf86-video-intel/src/i830_video.c b/driver/xf86-video-intel/src/intel_video.c index 7aa16bb6d..7de8d2b48 100644 --- a/driver/xf86-video-intel/src/i830_video.c +++ b/driver/xf86-video-intel/src/intel_video.c @@ -64,8 +64,9 @@ #include "randrstr.h" #include "windowstr.h" #include "damage.h" -#include "i830.h" -#include "i830_video.h" +#include "intel.h" +#include "intel_video.h" +#include "i830_reg.h" #include "xf86xv.h" #include <X11/extensions/Xv.h> #include "dixstruct.h" @@ -73,7 +74,7 @@ #ifdef INTEL_XVMC #define _INTEL_XVMC_SERVER_ -#include "i830_hwmc.h" +#include "intel_hwmc.h" #endif #define OFF_DELAY 250 /* milliseconds */ @@ -196,7 +197,7 @@ static Atom xvSyncToVblank; (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3)) /* client libraries expect an encoding */ -static XF86VideoEncodingRec DummyEncoding[1] = { +static const XF86VideoEncodingRec DummyEncoding[1] = { { 0, "XV_IMAGE", @@ -574,7 +575,9 @@ void I830InitVideo(ScreenPtr screen) /* Set up textured video if we can do it at this depth and we are on * supported hardware. */ - if (scrn->bitsPerPixel >= 16 && (IS_I9XX(intel) || IS_I965G(intel))) { + if (scrn->bitsPerPixel >= 16 && + INTEL_INFO(intel)->gen >= 30 && + !intel->use_shadow) { texturedAdaptor = I830SetupImageVideoTextured(screen); if (texturedAdaptor != NULL) { xf86DrvMsg(scrn->scrnIndex, X_INFO, @@ -817,16 +820,18 @@ static XF86VideoAdaptorPtr I830SetupImageVideoOverlay(ScreenPtr screen) OVERLAY_DEBUG("I830SetupImageVideoOverlay\n"); - if (!(adapt = calloc(1, sizeof(XF86VideoAdaptorRec) + - sizeof(intel_adaptor_private) + sizeof(DevUnion)))) + if (!(adapt = calloc(1, + sizeof(XF86VideoAdaptorRec) + + sizeof(intel_adaptor_private) + + sizeof(DevUnion)))) return NULL; adapt->type = XvWindowMask | XvInputMask | XvImageMask; adapt->flags = VIDEO_OVERLAID_IMAGES /*| VIDEO_CLIP_TO_VIEWPORT */ ; adapt->name = "Intel(R) Video Overlay"; adapt->nEncodings = 1; - adapt->pEncodings = DummyEncoding; - /* update the DummyEncoding for these two chipsets */ + adapt->pEncodings = xnfalloc(sizeof(DummyEncoding)); + memcpy(adapt->pEncodings, DummyEncoding, sizeof(DummyEncoding)); if (IS_845G(intel) || IS_I830(intel)) { adapt->pEncodings->width = IMAGE_MAX_WIDTH_LEGACY; adapt->pEncodings->height = IMAGE_MAX_HEIGHT_LEGACY; @@ -842,6 +847,7 @@ static XF86VideoAdaptorPtr I830SetupImageVideoOverlay(ScreenPtr screen) adapt->nAttributes = NUM_ATTRIBUTES; adapt->nAttributes += CLONE_ATTRIBUTES; if (IS_I9XX(intel)) + if (INTEL_INFO(intel)->gen >= 30) adapt->nAttributes += GAMMA_ATTRIBUTES; /* has gamma */ adapt->pAttributes = xnfalloc(sizeof(XF86AttributeRec) * adapt->nAttributes); @@ -853,7 +859,7 @@ static XF86VideoAdaptorPtr I830SetupImageVideoOverlay(ScreenPtr screen) memcpy((char *)att, (char *)CloneAttributes, sizeof(XF86AttributeRec) * CLONE_ATTRIBUTES); att += CLONE_ATTRIBUTES; - if (IS_I9XX(intel)) { + if (INTEL_INFO(intel)->gen >= 30) { memcpy((char *)att, (char *)GammaAttributes, sizeof(XF86AttributeRec) * GAMMA_ATTRIBUTES); att += GAMMA_ATTRIBUTES; @@ -918,7 +924,7 @@ static XF86VideoAdaptorPtr I830SetupImageVideoOverlay(ScreenPtr screen) /* Allow the pipe to be switched from pipe A to B when in clone mode */ xvPipe = MAKE_ATOM("XV_PIPE"); - if (IS_I9XX(intel)) { + if (INTEL_INFO(intel)->gen >= 30) { xvGamma0 = MAKE_ATOM("XV_GAMMA0"); xvGamma1 = MAKE_ATOM("XV_GAMMA1"); xvGamma2 = MAKE_ATOM("XV_GAMMA2"); @@ -966,7 +972,8 @@ static XF86VideoAdaptorPtr I830SetupImageVideoTextured(ScreenPtr screen) adapt->flags = 0; adapt->name = "Intel(R) Textured Video"; adapt->nEncodings = 1; - adapt->pEncodings = DummyEncoding; + adapt->pEncodings = xnfalloc(sizeof(DummyEncoding)); + memcpy(adapt->pEncodings, DummyEncoding, sizeof(DummyEncoding)); adapt->nFormats = NUM_FORMATS; adapt->pFormats = Formats; adapt->nPorts = nports; @@ -1015,7 +1022,7 @@ static XF86VideoAdaptorPtr I830SetupImageVideoTextured(ScreenPtr screen) return adapt; } -static void i830_free_video_buffers(intel_adaptor_private *adaptor_priv) +static void intel_free_video_buffers(intel_adaptor_private *adaptor_priv) { if (adaptor_priv->buf) { drm_intel_bo_unreference(adaptor_priv->buf); @@ -1052,7 +1059,7 @@ static void I830StopVideo(ScrnInfoPtr scrn, pointer data, Bool shutdown) if (adaptor_priv->videoStatus & CLIENT_VIDEO_ON) ums_overlay_off(scrn); - i830_free_video_buffers(adaptor_priv); + intel_free_video_buffers(adaptor_priv); adaptor_priv->videoStatus = 0; } else { if (adaptor_priv->videoStatus & CLIENT_VIDEO_ON) { @@ -1147,20 +1154,17 @@ I830SetPortAttributeOverlay(ScrnInfoPtr scrn, adaptor_priv->desired_crtc = NULL; else adaptor_priv->desired_crtc = xf86_config->crtc[value]; - /* - * Leave this to be updated at the next frame - */ - } else if (attribute == xvGamma0 && (IS_I9XX(intel))) { + } else if (attribute == xvGamma0 && (INTEL_INFO(intel)->gen >= 30)) { adaptor_priv->gamma0 = value; - } else if (attribute == xvGamma1 && (IS_I9XX(intel))) { + } else if (attribute == xvGamma1 && (INTEL_INFO(intel)->gen >= 30)) { adaptor_priv->gamma1 = value; - } else if (attribute == xvGamma2 && (IS_I9XX(intel))) { + } else if (attribute == xvGamma2 && (INTEL_INFO(intel)->gen >= 30)) { adaptor_priv->gamma2 = value; - } else if (attribute == xvGamma3 && (IS_I9XX(intel))) { + } else if (attribute == xvGamma3 && (INTEL_INFO(intel)->gen >= 30)) { adaptor_priv->gamma3 = value; - } else if (attribute == xvGamma4 && (IS_I9XX(intel))) { + } else if (attribute == xvGamma4 && (INTEL_INFO(intel)->gen >= 30)) { adaptor_priv->gamma4 = value; - } else if (attribute == xvGamma5 && (IS_I9XX(intel))) { + } else if (attribute == xvGamma5 && (INTEL_INFO(intel)->gen >= 30)) { adaptor_priv->gamma5 = value; } else if (attribute == xvColorKey) { adaptor_priv->colorKey = value; @@ -1170,11 +1174,11 @@ I830SetPortAttributeOverlay(ScrnInfoPtr scrn, /* Ensure that the overlay is off, ready for updating */ if ((attribute == xvGamma0 || - attribute == xvGamma1 || - attribute == xvGamma2 || - attribute == xvGamma3 || - attribute == xvGamma4 || - attribute == xvGamma5) && (IS_I9XX(intel))) { + attribute == xvGamma1 || + attribute == xvGamma2 || + attribute == xvGamma3 || + attribute == xvGamma4 || + attribute == xvGamma5) && (INTEL_INFO(intel)->gen >= 30)) { OVERLAY_DEBUG("GAMMA\n"); } @@ -1183,9 +1187,6 @@ I830SetPortAttributeOverlay(ScrnInfoPtr scrn, if (attribute == xvColorKey) REGION_EMPTY(scrn->screen, &adaptor_priv->clip); - if (attribute == xvColorKey) - REGION_EMPTY(scrn->screen, &adaptor_priv->clip); - return Success; } @@ -1211,17 +1212,17 @@ I830GetPortAttribute(ScrnInfoPtr scrn, if (c == xf86_config->num_crtc) c = -1; *value = c; - } else if (attribute == xvGamma0 && (IS_I9XX(intel))) { + } else if (attribute == xvGamma0 && (INTEL_INFO(intel)->gen >= 30)) { *value = adaptor_priv->gamma0; - } else if (attribute == xvGamma1 && (IS_I9XX(intel))) { + } else if (attribute == xvGamma1 && (INTEL_INFO(intel)->gen >= 30)) { *value = adaptor_priv->gamma1; - } else if (attribute == xvGamma2 && (IS_I9XX(intel))) { + } else if (attribute == xvGamma2 && (INTEL_INFO(intel)->gen >= 30)) { *value = adaptor_priv->gamma2; - } else if (attribute == xvGamma3 && (IS_I9XX(intel))) { + } else if (attribute == xvGamma3 && (INTEL_INFO(intel)->gen >= 30)) { *value = adaptor_priv->gamma3; - } else if (attribute == xvGamma4 && (IS_I9XX(intel))) { + } else if (attribute == xvGamma4 && (INTEL_INFO(intel)->gen >= 30)) { *value = adaptor_priv->gamma4; - } else if (attribute == xvGamma5 && (IS_I9XX(intel))) { + } else if (attribute == xvGamma5 && (INTEL_INFO(intel)->gen >= 30)) { *value = adaptor_priv->gamma5; } else if (attribute == xvColorKey) { *value = adaptor_priv->colorKey; @@ -1360,9 +1361,9 @@ I830CopyPackedData(intel_adaptor_private *adaptor_priv, drm_intel_bo_unmap(adaptor_priv->buf); } -static void i830_memcpy_plane(unsigned char *dst, unsigned char *src, - int height, int width, - int dstPitch, int srcPitch, Rotation rotation) +static void intel_memcpy_plane(unsigned char *dst, unsigned char *src, + int height, int width, + int dstPitch, int srcPitch, Rotation rotation) { int i, j = 0; unsigned char *s; @@ -1437,13 +1438,13 @@ I830CopyPlanarData(intel_adaptor_private *adaptor_priv, dst1 = dst_base + adaptor_priv->YBufOffset; - i830_memcpy_plane(dst1, src1, h, w, dstPitch2, srcPitch, + intel_memcpy_plane(dst1, src1, h, w, dstPitch2, srcPitch, adaptor_priv->rotation); /* Copy V data for YV12, or U data for I420 */ src2 = buf + /* start of YUV data */ (srcH * srcPitch) + /* move over Luma plane */ - ((top * srcPitch) >> 2) + /* move down from by top lines */ + ((top >> 1) * srcPitch2) + /* move down from by top lines */ (left >> 1); /* move left by left pixels */ #if 0 @@ -1455,14 +1456,14 @@ I830CopyPlanarData(intel_adaptor_private *adaptor_priv, else dst2 = dst_base + adaptor_priv->VBufOffset; - i830_memcpy_plane(dst2, src2, h / 2, w / 2, + intel_memcpy_plane(dst2, src2, h / 2, w / 2, dstPitch, srcPitch2, adaptor_priv->rotation); /* Copy U data for YV12, or V data for I420 */ src3 = buf + /* start of YUV data */ (srcH * srcPitch) + /* move over Luma plane */ ((srcH >> 1) * srcPitch2) + /* move over Chroma plane */ - ((top * srcPitch) >> 2) + /* move down from by top lines */ + ((top >> 1) * srcPitch2) + /* move down from by top lines */ (left >> 1); /* move left by left pixels */ #if 0 ErrorF("src3 is %p, offset is %ld\n", src3, @@ -1473,7 +1474,7 @@ I830CopyPlanarData(intel_adaptor_private *adaptor_priv, else dst3 = dst_base + adaptor_priv->UBufOffset; - i830_memcpy_plane(dst3, src3, h / 2, w / 2, + intel_memcpy_plane(dst3, src3, h / 2, w / 2, dstPitch, srcPitch2, adaptor_priv->rotation); drm_intel_bo_unmap(adaptor_priv->buf); @@ -1609,7 +1610,7 @@ UpdateCoeff(int taps, double fCutoff, Bool isHoriz, Bool isY, coeffPtr pCoeff) } } -static void i830_box_intersect(BoxPtr dest, BoxPtr a, BoxPtr b) +static void intel_box_intersect(BoxPtr dest, BoxPtr a, BoxPtr b) { dest->x1 = a->x1 > b->x1 ? a->x1 : b->x1; dest->x2 = a->x2 < b->x2 ? a->x2 : b->x2; @@ -1619,7 +1620,7 @@ static void i830_box_intersect(BoxPtr dest, BoxPtr a, BoxPtr b) dest->x1 = dest->x2 = dest->y1 = dest->y2 = 0; } -static void i830_crtc_box(xf86CrtcPtr crtc, BoxPtr crtc_box) +static void intel_crtc_box(xf86CrtcPtr crtc, BoxPtr crtc_box) { if (crtc->enabled) { crtc_box->x1 = crtc->x; @@ -1632,7 +1633,7 @@ static void i830_crtc_box(xf86CrtcPtr crtc, BoxPtr crtc_box) crtc_box->x1 = crtc_box->x2 = crtc_box->y1 = crtc_box->y2 = 0; } -static int i830_box_area(BoxPtr box) +static int intel_box_area(BoxPtr box) { return (int)(box->x2 - box->x1) * (int)(box->y2 - box->y1); } @@ -1644,8 +1645,8 @@ static int i830_box_area(BoxPtr box) */ xf86CrtcPtr -i830_covering_crtc(ScrnInfoPtr scrn, - BoxPtr box, xf86CrtcPtr desired, BoxPtr crtc_box_ret) +intel_covering_crtc(ScrnInfoPtr scrn, + BoxPtr box, xf86CrtcPtr desired, BoxPtr crtc_box_ret) { xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(scrn); xf86CrtcPtr crtc, best_crtc; @@ -1663,12 +1664,12 @@ i830_covering_crtc(ScrnInfoPtr scrn, crtc = xf86_config->crtc[c]; /* If the CRTC is off, treat it as not covering */ - if (!i830_crtc_on(crtc)) + if (!intel_crtc_on(crtc)) continue; - i830_crtc_box(crtc, &crtc_box); - i830_box_intersect(&cover_box, &crtc_box, box); - coverage = i830_box_area(&cover_box); + intel_crtc_box(crtc, &crtc_box); + intel_box_intersect(&cover_box, &crtc_box, box); + coverage = intel_box_area(&cover_box); if (coverage && crtc == desired) { *crtc_box_ret = crtc_box; return crtc; @@ -1730,8 +1731,8 @@ i830_calc_src_regs(intel_screen_private *intel, int planar, short width, } static void -i830_update_dst_box_to_crtc_coords(ScrnInfoPtr scrn, xf86CrtcPtr crtc, - BoxPtr dstBox) +intel_update_dst_box_to_crtc_coords(ScrnInfoPtr scrn, xf86CrtcPtr crtc, + BoxPtr dstBox) { int tmp; @@ -2073,7 +2074,7 @@ ums_overlay_put_image(ScrnInfoPtr scrn, xf86CrtcPtr crtc, } static Bool -i830_display_overlay(ScrnInfoPtr scrn, xf86CrtcPtr crtc, +intel_display_overlay(ScrnInfoPtr scrn, xf86CrtcPtr crtc, int id, short width, short height, int dstPitch, int dstPitch2, BoxPtr dstBox, short src_w, short src_h, short drw_w, @@ -2100,7 +2101,7 @@ i830_display_overlay(ScrnInfoPtr scrn, xf86CrtcPtr crtc, return TRUE; } - i830_update_dst_box_to_crtc_coords(scrn, crtc, dstBox); + intel_update_dst_box_to_crtc_coords(scrn, crtc, dstBox); if (crtc->rotation & (RR_Rotate_90 | RR_Rotate_270)) { tmp = width; @@ -2119,17 +2120,17 @@ i830_display_overlay(ScrnInfoPtr scrn, xf86CrtcPtr crtc, } static Bool -i830_clip_video_helper(ScrnInfoPtr scrn, - intel_adaptor_private *adaptor_priv, - xf86CrtcPtr * crtc_ret, - BoxPtr dst, - short src_x, short src_y, - short drw_x, short drw_y, - short src_w, short src_h, - short drw_w, short drw_h, - int id, - int *top, int* left, int* npixels, int *nlines, - RegionPtr reg, INT32 width, INT32 height) +intel_clip_video_helper(ScrnInfoPtr scrn, + intel_adaptor_private *adaptor_priv, + xf86CrtcPtr * crtc_ret, + BoxPtr dst, + short src_x, short src_y, + short drw_x, short drw_y, + short src_w, short src_h, + short drw_w, short drw_h, + int id, + int *top, int* left, int* npixels, int *nlines, + RegionPtr reg, INT32 width, INT32 height) { Bool ret; RegionRec crtc_region_local; @@ -2152,8 +2153,8 @@ i830_clip_video_helper(ScrnInfoPtr scrn, * For overlay video, compute the relevant CRTC and * clip video to that */ - crtc = i830_covering_crtc(scrn, dst, adaptor_priv->desired_crtc, - &crtc_box); + crtc = intel_covering_crtc(scrn, dst, adaptor_priv->desired_crtc, + &crtc_box); /* For textured video, we don't actually want to clip at all. */ if (crtc && !adaptor_priv->textured) { @@ -2171,10 +2172,10 @@ i830_clip_video_helper(ScrnInfoPtr scrn, *top = y1 >> 16; *left = (x1 >> 16) & ~1; - *npixels = ((((x2 + 0xffff) >> 16) + 1) & ~1) - *left; + *npixels = ALIGN(((x2 + 0xffff) >> 16), 2) - *left; if (is_planar_fourcc(id)) { *top &= ~1; - *nlines = ((((y2 + 0xffff) >> 16) + 1) & ~1) - *top; + *nlines = ALIGN(((y2 + 0xffff) >> 16), 2) - *top; } else *nlines = ((y2 + 0xffff) >> 16) - *top; @@ -2182,49 +2183,84 @@ i830_clip_video_helper(ScrnInfoPtr scrn, } static void -i830_wait_for_scanline(ScrnInfoPtr scrn, PixmapPtr pixmap, +intel_wait_for_scanline(ScrnInfoPtr scrn, PixmapPtr pixmap, xf86CrtcPtr crtc, RegionPtr clipBoxes) { intel_screen_private *intel = intel_get_screen_private(scrn); - BoxPtr box; - pixman_box16_t box_in_crtc_coordinates; - int pipe = -1, event, load_scan_lines_pipe; + pixman_box16_t box, crtc_box; + int pipe, event; + Bool full_height; + int y1, y2; + pipe = -1; if (pixmap_is_scanout(pixmap)) - pipe = i830_crtc_to_pipe(crtc); + pipe = intel_crtc_to_pipe(crtc); + if (pipe < 0) + return; - if (pipe >= 0) { - if (pipe == 0) { - event = MI_WAIT_FOR_PIPEA_SCAN_LINE_WINDOW; - load_scan_lines_pipe = MI_LOAD_SCAN_LINES_DISPLAY_PIPEA; - } else { - event = MI_WAIT_FOR_PIPEB_SCAN_LINE_WINDOW; - load_scan_lines_pipe = MI_LOAD_SCAN_LINES_DISPLAY_PIPEB; - } + box = *REGION_EXTENTS(unused, clipBoxes); + + if (crtc->transform_in_use) + pixman_f_transform_bounds(&crtc->f_framebuffer_to_crtc, &box); + + /* We could presume the clip was correctly computed... */ + intel_crtc_box(crtc, &crtc_box); + intel_box_intersect(&box, &crtc_box, &box); + + /* + * Make sure we don't wait for a scanline that will + * never occur + */ + y1 = (crtc_box.y1 <= box.y1) ? box.y1 - crtc_box.y1 : 0; + y2 = (box.y2 <= crtc_box.y2) ? + box.y2 - crtc_box.y1 : crtc_box.y2 - crtc_box.y1; + if (y2 <= y1) + return; + + full_height = FALSE; + if (y1 == 0 && y2 == (crtc_box.y2 - crtc_box.y1)) + full_height = TRUE; + + /* + * Pre-965 doesn't have SVBLANK, so we need a bit + * of extra time for the blitter to start up and + * do its job for a full height blit + */ + if (full_height && INTEL_INFO(intel)->gen < 40) + y2 -= 2; + + if (pipe == 0) { + pipe = MI_LOAD_SCAN_LINES_DISPLAY_PIPEA; + event = MI_WAIT_FOR_PIPEA_SCAN_LINE_WINDOW; + if (full_height && INTEL_INFO(intel)->gen >= 40) + event = MI_WAIT_FOR_PIPEA_SVBLANK; + } else { + pipe = MI_LOAD_SCAN_LINES_DISPLAY_PIPEB; + event = MI_WAIT_FOR_PIPEB_SCAN_LINE_WINDOW; + if (full_height && INTEL_INFO(intel)->gen >= 40) + event = MI_WAIT_FOR_PIPEB_SVBLANK; + } - box = REGION_EXTENTS(unused, clipBoxes); - box_in_crtc_coordinates = *box; - if (crtc->transform_in_use) - pixman_f_transform_bounds(&crtc->f_framebuffer_to_crtc, - &box_in_crtc_coordinates); - - BEGIN_BATCH(5); - /* The documentation says that the LOAD_SCAN_LINES command - * always comes in pairs. Don't ask me why. */ - OUT_BATCH(MI_LOAD_SCAN_LINES_INCL | load_scan_lines_pipe); - OUT_BATCH((box_in_crtc_coordinates. - y1 << 16) | box_in_crtc_coordinates.y2); - OUT_BATCH(MI_LOAD_SCAN_LINES_INCL | load_scan_lines_pipe); - OUT_BATCH((box_in_crtc_coordinates. - y1 << 16) | box_in_crtc_coordinates.y2); - OUT_BATCH(MI_WAIT_FOR_EVENT | event); - ADVANCE_BATCH(); + if (crtc->mode.Flags & V_INTERLACE) { + /* DSL count field lines */ + y1 /= 2; + y2 /= 2; } + + BEGIN_BATCH(5); + /* The documentation says that the LOAD_SCAN_LINES command + * always comes in pairs. Don't ask me why. */ + OUT_BATCH(MI_LOAD_SCAN_LINES_INCL | pipe); + OUT_BATCH((y1 << 16) | (y2-1)); + OUT_BATCH(MI_LOAD_SCAN_LINES_INCL | pipe); + OUT_BATCH((y1 << 16) | (y2-1)); + OUT_BATCH(MI_WAIT_FOR_EVENT | event); + ADVANCE_BATCH(); } static Bool -i830_setup_video_buffer(ScrnInfoPtr scrn, intel_adaptor_private *adaptor_priv, - int alloc_size, int id, unsigned char *buf) +intel_setup_video_buffer(ScrnInfoPtr scrn, intel_adaptor_private *adaptor_priv, + int alloc_size, int id, unsigned char *buf) { intel_screen_private *intel = intel_get_screen_private(scrn); @@ -2246,32 +2282,37 @@ i830_setup_video_buffer(ScrnInfoPtr scrn, intel_adaptor_private *adaptor_priv, } static void -i830_setup_dst_params(ScrnInfoPtr scrn, intel_adaptor_private *adaptor_priv, short width, - short height, int *dstPitch, int *dstPitch2, int *size, - int id) +intel_setup_dst_params(ScrnInfoPtr scrn, intel_adaptor_private *adaptor_priv, short width, + short height, int *dstPitch, int *dstPitch2, int *size, + int id) { intel_screen_private *intel = intel_get_screen_private(scrn); - int pitchAlignMask; + int pitchAlign; /* Only needs to be DWORD-aligned for textured on i915, but overlay has * stricter requirements. */ if (adaptor_priv->textured) { - pitchAlignMask = 3; + pitchAlign = 4; } else { - if (IS_I965G(intel)) + if (INTEL_INFO(intel)->gen >= 40) /* Actually the alignment is 64 bytes, too. But the * stride must be at least 512 bytes. Take the easy fix * and align on 512 bytes unconditionally. */ - pitchAlignMask = 511; + pitchAlign = 512; + else if (IS_I830(intel) || IS_845G(intel)) + /* Harsh, errata on these chipsets limit the stride to be + * a multiple of 256 bytes. + */ + pitchAlign = 256; else - pitchAlignMask = 63; + pitchAlign = 64; } #if INTEL_XVMC /* for i915 xvmc, hw requires 1kb aligned surfaces */ - if ((id == FOURCC_XVMC) && IS_I915(intel)) - pitchAlignMask = 0x3ff; + if ((id == FOURCC_XVMC) && IS_GEN3(intel)) + pitchAlign = 1024; #endif /* Determine the desired destination pitch (representing the chroma's pitch, @@ -2279,26 +2320,20 @@ i830_setup_dst_params(ScrnInfoPtr scrn, intel_adaptor_private *adaptor_priv, sho */ if (is_planar_fourcc(id)) { if (adaptor_priv->rotation & (RR_Rotate_90 | RR_Rotate_270)) { - *dstPitch = - ((height / 2) + pitchAlignMask) & ~pitchAlignMask; - *dstPitch2 = - (height + pitchAlignMask) & ~pitchAlignMask; + *dstPitch = ALIGN((height / 2), pitchAlign); + *dstPitch2 = ALIGN(height, pitchAlign); *size = *dstPitch * width * 3; } else { - *dstPitch = - ((width / 2) + pitchAlignMask) & ~pitchAlignMask; - *dstPitch2 = - (width + pitchAlignMask) & ~pitchAlignMask; + *dstPitch = ALIGN((width / 2), pitchAlign); + *dstPitch2 = ALIGN(width, pitchAlign); *size = *dstPitch * height * 3; } } else { if (adaptor_priv->rotation & (RR_Rotate_90 | RR_Rotate_270)) { - *dstPitch = - ((height << 1) + pitchAlignMask) & ~pitchAlignMask; + *dstPitch = ALIGN((height << 1), pitchAlign); *size = *dstPitch * width; } else { - *dstPitch = - ((width << 1) + pitchAlignMask) & ~pitchAlignMask; + *dstPitch = ALIGN((width << 1), pitchAlign); *size = *dstPitch * height; } *dstPitch2 = 0; @@ -2324,7 +2359,7 @@ i830_setup_dst_params(ScrnInfoPtr scrn, intel_adaptor_private *adaptor_priv, sho } static Bool -i830_copy_video_data(ScrnInfoPtr scrn, intel_adaptor_private *adaptor_priv, +intel_copy_video_data(ScrnInfoPtr scrn, intel_adaptor_private *adaptor_priv, short width, short height, int *dstPitch, int *dstPitch2, int top, int left, int npixels, int nlines, int id, unsigned char *buf) @@ -2333,16 +2368,16 @@ i830_copy_video_data(ScrnInfoPtr scrn, intel_adaptor_private *adaptor_priv, int size; if (is_planar_fourcc(id)) { - srcPitch = (width + 0x3) & ~0x3; - srcPitch2 = ((width >> 1) + 0x3) & ~0x3; + srcPitch = ALIGN(width, 0x4); + srcPitch2 = ALIGN((width >> 1), 0x4); } else { srcPitch = width << 1; } - i830_setup_dst_params(scrn, adaptor_priv, width, height, dstPitch, + intel_setup_dst_params(scrn, adaptor_priv, width, height, dstPitch, dstPitch2, &size, id); - if (!i830_setup_video_buffer(scrn, adaptor_priv, size, id, buf)) + if (!intel_setup_video_buffer(scrn, adaptor_priv, size, id, buf)) return FALSE; /* copy data */ @@ -2374,14 +2409,14 @@ i830_copy_video_data(ScrnInfoPtr scrn, intel_adaptor_private *adaptor_priv, */ static int I830PutImageTextured(ScrnInfoPtr scrn, - short src_x, short src_y, - short drw_x, short drw_y, - short src_w, short src_h, - short drw_w, short drw_h, - int id, unsigned char *buf, - short width, short height, - Bool sync, RegionPtr clipBoxes, pointer data, - DrawablePtr drawable) + short src_x, short src_y, + short drw_x, short drw_y, + short src_w, short src_h, + short drw_w, short drw_h, + int id, unsigned char *buf, + short width, short height, + Bool sync, RegionPtr clipBoxes, pointer data, + DrawablePtr drawable) { intel_screen_private *intel = intel_get_screen_private(scrn); intel_adaptor_private *adaptor_priv = (intel_adaptor_private *) data; @@ -2397,7 +2432,7 @@ I830PutImageTextured(ScrnInfoPtr scrn, drw_y, drw_w, drw_h, width, height); #endif - if (!i830_clip_video_helper(scrn, + if (!intel_clip_video_helper(scrn, adaptor_priv, &crtc, &dstBox, @@ -2412,9 +2447,9 @@ I830PutImageTextured(ScrnInfoPtr scrn, int size; uint32_t *gem_handle = (uint32_t *)buf; - i830_free_video_buffers(adaptor_priv); + intel_free_video_buffers(adaptor_priv); - i830_setup_dst_params(scrn, adaptor_priv, width, height, + intel_setup_dst_params(scrn, adaptor_priv, width, height, &dstPitch, &dstPitch2, &size, id); if (IS_I915G(intel) || IS_I915GM(intel)) { @@ -2428,17 +2463,22 @@ I830PutImageTextured(ScrnInfoPtr scrn, "xvmc surface", *gem_handle); } else { - if (!i830_copy_video_data(scrn, adaptor_priv, width, height, + if (!intel_copy_video_data(scrn, adaptor_priv, width, height, &dstPitch, &dstPitch2, top, left, npixels, nlines, id, buf)) return BadAlloc; } - if (crtc && adaptor_priv->SyncToVblank != 0) { - i830_wait_for_scanline(scrn, pixmap, crtc, clipBoxes); + if (crtc && adaptor_priv->SyncToVblank != 0 && INTEL_INFO(intel)->gen < 60) { + intel_wait_for_scanline(scrn, pixmap, crtc, clipBoxes); } - if (IS_I965G(intel)) { + if (INTEL_INFO(intel)->gen >= 60) { + Gen6DisplayVideoTextured(scrn, adaptor_priv, id, clipBoxes, + width, height, dstPitch, dstPitch2, + src_w, src_h, + drw_w, drw_h, pixmap); + } else if (INTEL_INFO(intel)->gen >= 40) { I965DisplayVideoTextured(scrn, adaptor_priv, id, clipBoxes, width, height, dstPitch, dstPitch2, src_w, src_h, @@ -2450,6 +2490,7 @@ I830PutImageTextured(ScrnInfoPtr scrn, pixmap); } + intel_get_screen_private(scrn)->needs_flush = TRUE; DamageDamageRegion(drawable, clipBoxes); return Success; @@ -2486,7 +2527,7 @@ I830PutImageOverlay(ScrnInfoPtr scrn, if (src_h >= (drw_h * 8)) drw_h = src_h / 7; - if (!i830_clip_video_helper(scrn, + if (!intel_clip_video_helper(scrn, adaptor_priv, &crtc, &dstBox, @@ -2506,12 +2547,12 @@ I830PutImageOverlay(ScrnInfoPtr scrn, return Success; } - if (!i830_copy_video_data(scrn, adaptor_priv, width, height, + if (!intel_copy_video_data(scrn, adaptor_priv, width, height, &dstPitch, &dstPitch2, top, left, npixels, nlines, id, buf)) return BadAlloc; - if (!i830_display_overlay + if (!intel_display_overlay (scrn, crtc, id, width, height, dstPitch, dstPitch2, &dstBox, src_w, src_h, drw_w, drw_h)) return BadAlloc; @@ -2616,10 +2657,8 @@ I830QueryImageAttributes(ScrnInfoPtr scrn, } void -I830VideoBlockHandler(int i, pointer blockData, pointer pTimeout, - pointer pReadmask) +intel_video_block_handler(ScrnInfoPtr scrn) { - ScrnInfoPtr scrn = xf86Screens[i]; intel_screen_private *intel = intel_get_screen_private(scrn); intel_adaptor_private *adaptor_priv; @@ -2627,7 +2666,7 @@ I830VideoBlockHandler(int i, pointer blockData, pointer pTimeout, if (intel->adaptor == NULL) return; - adaptor_priv = intel_get_adaptor_private(scrn); + adaptor_priv = intel_get_adaptor_private(intel); if (adaptor_priv->videoStatus & TIMER_MASK) { #if 1 @@ -2647,7 +2686,7 @@ I830VideoBlockHandler(int i, pointer blockData, pointer pTimeout, } } else { /* FREE_TIMER */ if (adaptor_priv->freeTime < now) { - i830_free_video_buffers(adaptor_priv); + intel_free_video_buffers(adaptor_priv); adaptor_priv->videoStatus = 0; } } diff --git a/driver/xf86-video-intel/src/i830_video.h b/driver/xf86-video-intel/src/intel_video.h index ec7b25597..b28b40590 100644 --- a/driver/xf86-video-intel/src/i830_video.h +++ b/driver/xf86-video-intel/src/intel_video.h @@ -67,9 +67,9 @@ typedef struct { } intel_adaptor_private; static inline intel_adaptor_private * -intel_get_adaptor_private(ScrnInfoPtr scrn) +intel_get_adaptor_private(intel_screen_private *intel) { - return intel_get_screen_private(scrn)->adaptor->pPortPrivates[0].ptr; + return intel->adaptor->pPortPrivates[0].ptr; } void I915DisplayVideoTextured(ScrnInfoPtr scrn, @@ -86,8 +86,15 @@ void I965DisplayVideoTextured(ScrnInfoPtr scrn, short src_w, short src_h, short drw_w, short drw_h, PixmapPtr pixmap); -void I830VideoBlockHandler(int i, pointer blockData, pointer pTimeout, - pointer pReadmask); +void Gen6DisplayVideoTextured(ScrnInfoPtr scrn, + intel_adaptor_private *adaptor_priv, + int id, RegionPtr dstRegion, short width, + short height, int video_pitch, int video_pitch2, + short src_w, short src_h, + short drw_w, short drw_h, PixmapPtr pixmap); + void i965_free_video(ScrnInfoPtr scrn); int is_planar_fourcc(int id); + +void intel_video_block_handler(ScrnInfoPtr scrn); diff --git a/driver/xf86-video-intel/src/ivch/Makefile.in b/driver/xf86-video-intel/src/ivch/Makefile.in index a21e621c0..51e26603f 100644 --- a/driver/xf86-video-intel/src/ivch/Makefile.in +++ b/driver/xf86-video-intel/src/ivch/Makefile.in @@ -87,10 +87,6 @@ AUTOCONF = @AUTOCONF@ AUTOHEADER = @AUTOHEADER@ AUTOMAKE = @AUTOMAKE@ AWK = @AWK@ -BUILD_LINUXDOC_FALSE = @BUILD_LINUXDOC_FALSE@ -BUILD_LINUXDOC_TRUE = @BUILD_LINUXDOC_TRUE@ -BUILD_PDFDOC_FALSE = @BUILD_PDFDOC_FALSE@ -BUILD_PDFDOC_TRUE = @BUILD_PDFDOC_TRUE@ CC = @CC@ CCDEPMODE = @CCDEPMODE@ CFLAGS = @CFLAGS@ @@ -130,8 +126,6 @@ GEN4ASM_LIBS = @GEN4ASM_LIBS@ GREP = @GREP@ HAVE_GEN4ASM_FALSE = @HAVE_GEN4ASM_FALSE@ HAVE_GEN4ASM_TRUE = @HAVE_GEN4ASM_TRUE@ -HAVE_XEXTPROTO_71_FALSE = @HAVE_XEXTPROTO_71_FALSE@ -HAVE_XEXTPROTO_71_TRUE = @HAVE_XEXTPROTO_71_TRUE@ INSTALL_CMD = @INSTALL_CMD@ INSTALL_DATA = @INSTALL_DATA@ INSTALL_PROGRAM = @INSTALL_PROGRAM@ @@ -145,17 +139,13 @@ LIBS = @LIBS@ LIBTOOL = @LIBTOOL@ LIB_MAN_DIR = @LIB_MAN_DIR@ LIB_MAN_SUFFIX = @LIB_MAN_SUFFIX@ -LINUXDOC = @LINUXDOC@ LN_S = @LN_S@ LTLIBOBJS = @LTLIBOBJS@ MAINT = @MAINT@ MAINTAINER_MODE_FALSE = @MAINTAINER_MODE_FALSE@ MAINTAINER_MODE_TRUE = @MAINTAINER_MODE_TRUE@ MAKEINFO = @MAKEINFO@ -MAKE_HTML = @MAKE_HTML@ -MAKE_PDF = @MAKE_PDF@ -MAKE_PS = @MAKE_PS@ -MAKE_TEXT = @MAKE_TEXT@ +MAN_SUBSTS = @MAN_SUBSTS@ MISC_MAN_DIR = @MISC_MAN_DIR@ MISC_MAN_SUFFIX = @MISC_MAN_SUFFIX@ NMEDIT = @NMEDIT@ @@ -170,19 +160,15 @@ PATH_SEPARATOR = @PATH_SEPARATOR@ PCIACCESS_CFLAGS = @PCIACCESS_CFLAGS@ PCIACCESS_LIBS = @PCIACCESS_LIBS@ PKG_CONFIG = @PKG_CONFIG@ -PS2PDF = @PS2PDF@ RANLIB = @RANLIB@ SED = @SED@ SET_MAKE = @SET_MAKE@ SHELL = @SHELL@ STRIP = @STRIP@ VERSION = @VERSION@ -VIDEO_DEBUG_FALSE = @VIDEO_DEBUG_FALSE@ -VIDEO_DEBUG_TRUE = @VIDEO_DEBUG_TRUE@ -XEXT_CFLAGS = @XEXT_CFLAGS@ -XEXT_LIBS = @XEXT_LIBS@ XORG_CFLAGS = @XORG_CFLAGS@ XORG_LIBS = @XORG_LIBS@ +XORG_MAN_PAGE = @XORG_MAN_PAGE@ XVMCLIB_CFLAGS = @XVMCLIB_CFLAGS@ XVMCLIB_LIBS = @XVMCLIB_LIBS@ XVMC_FALSE = @XVMC_FALSE@ diff --git a/driver/xf86-video-intel/src/legacy/Makefile.am b/driver/xf86-video-intel/src/legacy/Makefile.am new file mode 100644 index 000000000..af10c0165 --- /dev/null +++ b/driver/xf86-video-intel/src/legacy/Makefile.am @@ -0,0 +1,17 @@ +SUBDIRS = +noinst_LTLIBRARIES = liblegacy.la + +NULL:=# + +liblegacy_la_SOURCES = +liblegacy_la_LIBADD = + +if ! KMS_ONLY +SUBDIRS += i810 +liblegacy_la_SOURCES += +liblegacy_la_LIBADD += \ + i810/liblegacy-i810.la \ + $(NULL) +endif + +EXTRA_DIST = README diff --git a/driver/xf86-video-intel/src/legacy/Makefile.in b/driver/xf86-video-intel/src/legacy/Makefile.in new file mode 100644 index 000000000..9d7598ca9 --- /dev/null +++ b/driver/xf86-video-intel/src/legacy/Makefile.in @@ -0,0 +1,567 @@ +# Makefile.in generated by automake 1.9.6 from Makefile.am. +# @configure_input@ + +# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, +# 2003, 2004, 2005 Free Software Foundation, Inc. +# This Makefile.in is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY, to the extent permitted by law; without +# even the implied warranty of MERCHANTABILITY or FITNESS FOR A +# PARTICULAR PURPOSE. + +@SET_MAKE@ + +srcdir = @srcdir@ +top_srcdir = @top_srcdir@ +VPATH = @srcdir@ +pkgdatadir = $(datadir)/@PACKAGE@ +pkglibdir = $(libdir)/@PACKAGE@ +pkgincludedir = $(includedir)/@PACKAGE@ +top_builddir = ../.. +am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd +INSTALL = @INSTALL@ +install_sh_DATA = $(install_sh) -c -m 644 +install_sh_PROGRAM = $(install_sh) -c +install_sh_SCRIPT = $(install_sh) -c +INSTALL_HEADER = $(INSTALL_DATA) +transform = $(program_transform_name) +NORMAL_INSTALL = : +PRE_INSTALL = : +POST_INSTALL = : +NORMAL_UNINSTALL = : +PRE_UNINSTALL = : +POST_UNINSTALL = : +build_triplet = @build@ +host_triplet = @host@ +@KMS_ONLY_FALSE@am__append_1 = i810 +@KMS_ONLY_FALSE@am__append_2 = +@KMS_ONLY_FALSE@am__append_3 = \ +@KMS_ONLY_FALSE@ i810/liblegacy-i810.la \ +@KMS_ONLY_FALSE@ $(NULL) + +subdir = src/legacy +DIST_COMMON = README $(srcdir)/Makefile.am $(srcdir)/Makefile.in +ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 +am__aclocal_m4_deps = $(top_srcdir)/configure.ac +am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \ + $(ACLOCAL_M4) +mkinstalldirs = $(SHELL) $(install_sh) -d +CONFIG_HEADER = $(top_builddir)/config.h +CONFIG_CLEAN_FILES = +LTLIBRARIES = $(noinst_LTLIBRARIES) +am__DEPENDENCIES_1 = +@KMS_ONLY_FALSE@am__DEPENDENCIES_2 = i810/liblegacy-i810.la \ +@KMS_ONLY_FALSE@ $(am__DEPENDENCIES_1) +liblegacy_la_DEPENDENCIES = $(am__DEPENDENCIES_2) +am__objects_1 = +am_liblegacy_la_OBJECTS = $(am__objects_1) +liblegacy_la_OBJECTS = $(am_liblegacy_la_OBJECTS) +DEFAULT_INCLUDES = -I. -I$(srcdir) -I$(top_builddir) +COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \ + $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) +LTCOMPILE = $(LIBTOOL) --tag=CC --mode=compile $(CC) $(DEFS) \ + $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) \ + $(AM_CFLAGS) $(CFLAGS) +CCLD = $(CC) +LINK = $(LIBTOOL) --tag=CC --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \ + $(AM_LDFLAGS) $(LDFLAGS) -o $@ +SOURCES = $(liblegacy_la_SOURCES) +DIST_SOURCES = $(liblegacy_la_SOURCES) +RECURSIVE_TARGETS = all-recursive check-recursive dvi-recursive \ + html-recursive info-recursive install-data-recursive \ + install-exec-recursive install-info-recursive \ + install-recursive installcheck-recursive installdirs-recursive \ + pdf-recursive ps-recursive uninstall-info-recursive \ + uninstall-recursive +ETAGS = etags +CTAGS = ctags +DIST_SUBDIRS = i810 +DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST) +ACLOCAL = @ACLOCAL@ +ADMIN_MAN_DIR = @ADMIN_MAN_DIR@ +ADMIN_MAN_SUFFIX = @ADMIN_MAN_SUFFIX@ +AMDEP_FALSE = @AMDEP_FALSE@ +AMDEP_TRUE = @AMDEP_TRUE@ +AMTAR = @AMTAR@ +AM_DEFAULT_VERBOSITY = @AM_DEFAULT_VERBOSITY@ +APP_MAN_DIR = @APP_MAN_DIR@ +APP_MAN_SUFFIX = @APP_MAN_SUFFIX@ +AR = @AR@ +AUTOCONF = @AUTOCONF@ +AUTOHEADER = @AUTOHEADER@ +AUTOMAKE = @AUTOMAKE@ +AWK = @AWK@ +CC = @CC@ +CCDEPMODE = @CCDEPMODE@ +CFLAGS = @CFLAGS@ +CHANGELOG_CMD = @CHANGELOG_CMD@ +CPP = @CPP@ +CPPFLAGS = @CPPFLAGS@ +CWARNFLAGS = @CWARNFLAGS@ +CXX = @CXX@ +CXXCPP = @CXXCPP@ +CXXDEPMODE = @CXXDEPMODE@ +CXXFLAGS = @CXXFLAGS@ +CYGPATH_W = @CYGPATH_W@ +DEFS = @DEFS@ +DEPDIR = @DEPDIR@ +DRIVER_MAN_DIR = @DRIVER_MAN_DIR@ +DRIVER_MAN_SUFFIX = @DRIVER_MAN_SUFFIX@ +DRIVER_NAME = @DRIVER_NAME@ +DRI_CFLAGS = @DRI_CFLAGS@ +DRI_FALSE = @DRI_FALSE@ +DRI_LIBS = @DRI_LIBS@ +DRI_TRUE = @DRI_TRUE@ +DRM_CFLAGS = @DRM_CFLAGS@ +DRM_LIBS = @DRM_LIBS@ +DSYMUTIL = @DSYMUTIL@ +ECHO = @ECHO@ +ECHO_C = @ECHO_C@ +ECHO_N = @ECHO_N@ +ECHO_T = @ECHO_T@ +EGREP = @EGREP@ +EXEEXT = @EXEEXT@ +F77 = @F77@ +FFLAGS = @FFLAGS@ +FILE_MAN_DIR = @FILE_MAN_DIR@ +FILE_MAN_SUFFIX = @FILE_MAN_SUFFIX@ +GEN4ASM_CFLAGS = @GEN4ASM_CFLAGS@ +GEN4ASM_LIBS = @GEN4ASM_LIBS@ +GREP = @GREP@ +HAVE_GEN4ASM_FALSE = @HAVE_GEN4ASM_FALSE@ +HAVE_GEN4ASM_TRUE = @HAVE_GEN4ASM_TRUE@ +INSTALL_CMD = @INSTALL_CMD@ +INSTALL_DATA = @INSTALL_DATA@ +INSTALL_PROGRAM = @INSTALL_PROGRAM@ +INSTALL_SCRIPT = @INSTALL_SCRIPT@ +INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@ +KMS_ONLY_FALSE = @KMS_ONLY_FALSE@ +KMS_ONLY_TRUE = @KMS_ONLY_TRUE@ +LDFLAGS = @LDFLAGS@ +LIBOBJS = @LIBOBJS@ +LIBS = @LIBS@ +LIBTOOL = @LIBTOOL@ +LIB_MAN_DIR = @LIB_MAN_DIR@ +LIB_MAN_SUFFIX = @LIB_MAN_SUFFIX@ +LN_S = @LN_S@ +LTLIBOBJS = @LTLIBOBJS@ +MAINT = @MAINT@ +MAINTAINER_MODE_FALSE = @MAINTAINER_MODE_FALSE@ +MAINTAINER_MODE_TRUE = @MAINTAINER_MODE_TRUE@ +MAKEINFO = @MAKEINFO@ +MAN_SUBSTS = @MAN_SUBSTS@ +MISC_MAN_DIR = @MISC_MAN_DIR@ +MISC_MAN_SUFFIX = @MISC_MAN_SUFFIX@ +NMEDIT = @NMEDIT@ +OBJEXT = @OBJEXT@ +PACKAGE = @PACKAGE@ +PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@ +PACKAGE_NAME = @PACKAGE_NAME@ +PACKAGE_STRING = @PACKAGE_STRING@ +PACKAGE_TARNAME = @PACKAGE_TARNAME@ +PACKAGE_VERSION = @PACKAGE_VERSION@ +PATH_SEPARATOR = @PATH_SEPARATOR@ +PCIACCESS_CFLAGS = @PCIACCESS_CFLAGS@ +PCIACCESS_LIBS = @PCIACCESS_LIBS@ +PKG_CONFIG = @PKG_CONFIG@ +RANLIB = @RANLIB@ +SED = @SED@ +SET_MAKE = @SET_MAKE@ +SHELL = @SHELL@ +STRIP = @STRIP@ +VERSION = @VERSION@ +XORG_CFLAGS = @XORG_CFLAGS@ +XORG_LIBS = @XORG_LIBS@ +XORG_MAN_PAGE = @XORG_MAN_PAGE@ +XVMCLIB_CFLAGS = @XVMCLIB_CFLAGS@ +XVMCLIB_LIBS = @XVMCLIB_LIBS@ +XVMC_FALSE = @XVMC_FALSE@ +XVMC_TRUE = @XVMC_TRUE@ +ac_ct_CC = @ac_ct_CC@ +ac_ct_CXX = @ac_ct_CXX@ +ac_ct_F77 = @ac_ct_F77@ +am__fastdepCC_FALSE = @am__fastdepCC_FALSE@ +am__fastdepCC_TRUE = @am__fastdepCC_TRUE@ +am__fastdepCXX_FALSE = @am__fastdepCXX_FALSE@ +am__fastdepCXX_TRUE = @am__fastdepCXX_TRUE@ +am__include = @am__include@ +am__leading_dot = @am__leading_dot@ +am__quote = @am__quote@ +am__tar = @am__tar@ +am__untar = @am__untar@ +bindir = @bindir@ +build = @build@ +build_alias = @build_alias@ +build_cpu = @build_cpu@ +build_os = @build_os@ +build_vendor = @build_vendor@ +datadir = @datadir@ +datarootdir = @datarootdir@ +docdir = @docdir@ +dvidir = @dvidir@ +exec_prefix = @exec_prefix@ +host = @host@ +host_alias = @host_alias@ +host_cpu = @host_cpu@ +host_os = @host_os@ +host_vendor = @host_vendor@ +htmldir = @htmldir@ +includedir = @includedir@ +infodir = @infodir@ +install_sh = @install_sh@ +libdir = @libdir@ +libexecdir = @libexecdir@ +localedir = @localedir@ +localstatedir = @localstatedir@ +mandir = @mandir@ +mkdir_p = @mkdir_p@ +moduledir = @moduledir@ +oldincludedir = @oldincludedir@ +pdfdir = @pdfdir@ +prefix = @prefix@ +program_transform_name = @program_transform_name@ +psdir = @psdir@ +sbindir = @sbindir@ +sharedstatedir = @sharedstatedir@ +sysconfdir = @sysconfdir@ +target_alias = @target_alias@ +SUBDIRS = $(am__append_1) +noinst_LTLIBRARIES = liblegacy.la +NULL := # +liblegacy_la_SOURCES = $(am__append_2) +liblegacy_la_LIBADD = $(am__append_3) +EXTRA_DIST = README +all: all-recursive + +.SUFFIXES: +$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(am__configure_deps) + @for dep in $?; do \ + case '$(am__configure_deps)' in \ + *$$dep*) \ + cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh \ + && exit 0; \ + exit 1;; \ + esac; \ + done; \ + echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign src/legacy/Makefile'; \ + cd $(top_srcdir) && \ + $(AUTOMAKE) --foreign src/legacy/Makefile +.PRECIOUS: Makefile +Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status + @case '$?' in \ + *config.status*) \ + cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \ + *) \ + echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \ + cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \ + esac; + +$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES) + cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh + +$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps) + cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh +$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps) + cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh + +clean-noinstLTLIBRARIES: + -test -z "$(noinst_LTLIBRARIES)" || rm -f $(noinst_LTLIBRARIES) + @list='$(noinst_LTLIBRARIES)'; for p in $$list; do \ + dir="`echo $$p | sed -e 's|/[^/]*$$||'`"; \ + test "$$dir" != "$$p" || dir=.; \ + echo "rm -f \"$${dir}/so_locations\""; \ + rm -f "$${dir}/so_locations"; \ + done +liblegacy.la: $(liblegacy_la_OBJECTS) $(liblegacy_la_DEPENDENCIES) + $(LINK) $(liblegacy_la_LDFLAGS) $(liblegacy_la_OBJECTS) $(liblegacy_la_LIBADD) $(LIBS) + +mostlyclean-compile: + -rm -f *.$(OBJEXT) + +distclean-compile: + -rm -f *.tab.c + +mostlyclean-libtool: + -rm -f *.lo + +clean-libtool: + -rm -rf .libs _libs + +distclean-libtool: + -rm -f libtool +uninstall-info-am: + +# This directory's subdirectories are mostly independent; you can cd +# into them and run `make' without going through this Makefile. +# To change the values of `make' variables: instead of editing Makefiles, +# (1) if the variable is set in `config.status', edit `config.status' +# (which will cause the Makefiles to be regenerated when you run `make'); +# (2) otherwise, pass the desired values on the `make' command line. +$(RECURSIVE_TARGETS): + @failcom='exit 1'; \ + for f in x $$MAKEFLAGS; do \ + case $$f in \ + *=* | --[!k]*);; \ + *k*) failcom='fail=yes';; \ + esac; \ + done; \ + dot_seen=no; \ + target=`echo $@ | sed s/-recursive//`; \ + list='$(SUBDIRS)'; for subdir in $$list; do \ + echo "Making $$target in $$subdir"; \ + if test "$$subdir" = "."; then \ + dot_seen=yes; \ + local_target="$$target-am"; \ + else \ + local_target="$$target"; \ + fi; \ + (cd $$subdir && $(MAKE) $(AM_MAKEFLAGS) $$local_target) \ + || eval $$failcom; \ + done; \ + if test "$$dot_seen" = "no"; then \ + $(MAKE) $(AM_MAKEFLAGS) "$$target-am" || exit 1; \ + fi; test -z "$$fail" + +mostlyclean-recursive clean-recursive distclean-recursive \ +maintainer-clean-recursive: + @failcom='exit 1'; \ + for f in x $$MAKEFLAGS; do \ + case $$f in \ + *=* | --[!k]*);; \ + *k*) failcom='fail=yes';; \ + esac; \ + done; \ + dot_seen=no; \ + case "$@" in \ + distclean-* | maintainer-clean-*) list='$(DIST_SUBDIRS)' ;; \ + *) list='$(SUBDIRS)' ;; \ + esac; \ + rev=''; for subdir in $$list; do \ + if test "$$subdir" = "."; then :; else \ + rev="$$subdir $$rev"; \ + fi; \ + done; \ + rev="$$rev ."; \ + target=`echo $@ | sed s/-recursive//`; \ + for subdir in $$rev; do \ + echo "Making $$target in $$subdir"; \ + if test "$$subdir" = "."; then \ + local_target="$$target-am"; \ + else \ + local_target="$$target"; \ + fi; \ + (cd $$subdir && $(MAKE) $(AM_MAKEFLAGS) $$local_target) \ + || eval $$failcom; \ + done && test -z "$$fail" +tags-recursive: + list='$(SUBDIRS)'; for subdir in $$list; do \ + test "$$subdir" = . || (cd $$subdir && $(MAKE) $(AM_MAKEFLAGS) tags); \ + done +ctags-recursive: + list='$(SUBDIRS)'; for subdir in $$list; do \ + test "$$subdir" = . || (cd $$subdir && $(MAKE) $(AM_MAKEFLAGS) ctags); \ + done + +ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES) + list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \ + unique=`for i in $$list; do \ + if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \ + done | \ + $(AWK) ' { files[$$0] = 1; } \ + END { for (i in files) print i; }'`; \ + mkid -fID $$unique +tags: TAGS + +TAGS: tags-recursive $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \ + $(TAGS_FILES) $(LISP) + tags=; \ + here=`pwd`; \ + if ($(ETAGS) --etags-include --version) >/dev/null 2>&1; then \ + include_option=--etags-include; \ + empty_fix=.; \ + else \ + include_option=--include; \ + empty_fix=; \ + fi; \ + list='$(SUBDIRS)'; for subdir in $$list; do \ + if test "$$subdir" = .; then :; else \ + test ! -f $$subdir/TAGS || \ + tags="$$tags $$include_option=$$here/$$subdir/TAGS"; \ + fi; \ + done; \ + list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \ + unique=`for i in $$list; do \ + if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \ + done | \ + $(AWK) ' { files[$$0] = 1; } \ + END { for (i in files) print i; }'`; \ + if test -z "$(ETAGS_ARGS)$$tags$$unique"; then :; else \ + test -n "$$unique" || unique=$$empty_fix; \ + $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \ + $$tags $$unique; \ + fi +ctags: CTAGS +CTAGS: ctags-recursive $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \ + $(TAGS_FILES) $(LISP) + tags=; \ + here=`pwd`; \ + list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \ + unique=`for i in $$list; do \ + if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \ + done | \ + $(AWK) ' { files[$$0] = 1; } \ + END { for (i in files) print i; }'`; \ + test -z "$(CTAGS_ARGS)$$tags$$unique" \ + || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \ + $$tags $$unique + +GTAGS: + here=`$(am__cd) $(top_builddir) && pwd` \ + && cd $(top_srcdir) \ + && gtags -i $(GTAGS_ARGS) $$here + +distclean-tags: + -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags + +distdir: $(DISTFILES) + @srcdirstrip=`echo "$(srcdir)" | sed 's|.|.|g'`; \ + topsrcdirstrip=`echo "$(top_srcdir)" | sed 's|.|.|g'`; \ + list='$(DISTFILES)'; for file in $$list; do \ + case $$file in \ + $(srcdir)/*) file=`echo "$$file" | sed "s|^$$srcdirstrip/||"`;; \ + $(top_srcdir)/*) file=`echo "$$file" | sed "s|^$$topsrcdirstrip/|$(top_builddir)/|"`;; \ + esac; \ + if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \ + dir=`echo "$$file" | sed -e 's,/[^/]*$$,,'`; \ + if test "$$dir" != "$$file" && test "$$dir" != "."; then \ + dir="/$$dir"; \ + $(mkdir_p) "$(distdir)$$dir"; \ + else \ + dir=''; \ + fi; \ + if test -d $$d/$$file; then \ + if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \ + cp -pR $(srcdir)/$$file $(distdir)$$dir || exit 1; \ + fi; \ + cp -pR $$d/$$file $(distdir)$$dir || exit 1; \ + else \ + test -f $(distdir)/$$file \ + || cp -p $$d/$$file $(distdir)/$$file \ + || exit 1; \ + fi; \ + done + list='$(DIST_SUBDIRS)'; for subdir in $$list; do \ + if test "$$subdir" = .; then :; else \ + test -d "$(distdir)/$$subdir" \ + || $(mkdir_p) "$(distdir)/$$subdir" \ + || exit 1; \ + distdir=`$(am__cd) $(distdir) && pwd`; \ + top_distdir=`$(am__cd) $(top_distdir) && pwd`; \ + (cd $$subdir && \ + $(MAKE) $(AM_MAKEFLAGS) \ + top_distdir="$$top_distdir" \ + distdir="$$distdir/$$subdir" \ + distdir) \ + || exit 1; \ + fi; \ + done +check-am: all-am +check: check-recursive +all-am: Makefile $(LTLIBRARIES) +installdirs: installdirs-recursive +installdirs-am: +install: install-recursive +install-exec: install-exec-recursive +install-data: install-data-recursive +uninstall: uninstall-recursive + +install-am: all-am + @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am + +installcheck: installcheck-recursive +install-strip: + $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \ + install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \ + `test -z '$(STRIP)' || \ + echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install +mostlyclean-generic: + +clean-generic: + +distclean-generic: + -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES) + +maintainer-clean-generic: + @echo "This command is intended for maintainers to use" + @echo "it deletes files that may require special tools to rebuild." +clean: clean-recursive + +clean-am: clean-generic clean-libtool clean-noinstLTLIBRARIES \ + mostlyclean-am + +distclean: distclean-recursive + -rm -f Makefile +distclean-am: clean-am distclean-compile distclean-generic \ + distclean-libtool distclean-tags + +dvi: dvi-recursive + +dvi-am: + +html: html-recursive + +info: info-recursive + +info-am: + +install-data-am: + +install-exec-am: + +install-info: install-info-recursive + +install-man: + +installcheck-am: + +maintainer-clean: maintainer-clean-recursive + -rm -f Makefile +maintainer-clean-am: distclean-am maintainer-clean-generic + +mostlyclean: mostlyclean-recursive + +mostlyclean-am: mostlyclean-compile mostlyclean-generic \ + mostlyclean-libtool + +pdf: pdf-recursive + +pdf-am: + +ps: ps-recursive + +ps-am: + +uninstall-am: uninstall-info-am + +uninstall-info: uninstall-info-recursive + +.PHONY: $(RECURSIVE_TARGETS) CTAGS GTAGS all all-am check check-am \ + clean clean-generic clean-libtool clean-noinstLTLIBRARIES \ + clean-recursive ctags ctags-recursive distclean \ + distclean-compile distclean-generic distclean-libtool \ + distclean-recursive distclean-tags distdir dvi dvi-am html \ + html-am info info-am install install-am install-data \ + install-data-am install-exec install-exec-am install-info \ + install-info-am install-man install-strip installcheck \ + installcheck-am installdirs installdirs-am maintainer-clean \ + maintainer-clean-generic maintainer-clean-recursive \ + mostlyclean mostlyclean-compile mostlyclean-generic \ + mostlyclean-libtool mostlyclean-recursive pdf pdf-am ps ps-am \ + tags tags-recursive uninstall uninstall-am uninstall-info-am + +# Tell versions [3.59,3.63) of GNU make to not export all variables. +# Otherwise a system limit (for SysV at least) may be exceeded. +.NOEXPORT: diff --git a/driver/xf86-video-intel/src/legacy/README b/driver/xf86-video-intel/src/legacy/README new file mode 100644 index 000000000..65c32f6c6 --- /dev/null +++ b/driver/xf86-video-intel/src/legacy/README @@ -0,0 +1,6 @@ +Welcome to the attic! + +The code contained herein is no longer under active development and is not the +target for new features or other improvements. Instead, we have placed it here +to mature gracefully and still provide hardware compatibility for those +antiquated devices that turn up when you least expect them. diff --git a/driver/xf86-video-intel/src/legacy/i810/Makefile.am b/driver/xf86-video-intel/src/legacy/i810/Makefile.am new file mode 100644 index 000000000..aab7f512a --- /dev/null +++ b/driver/xf86-video-intel/src/legacy/i810/Makefile.am @@ -0,0 +1,33 @@ +SUBDIRS = xvmc + +noinst_LTLIBRARIES = liblegacy-i810.la + +AM_CFLAGS = @CWARNFLAGS@ @XORG_CFLAGS@ @DRM_CFLAGS@ @DRI_CFLAGS@ @PCIACCESS_CFLAGS@ -I$(top_srcdir)/src + +liblegacy_i810_la_SOURCES = \ + i810_accel.c \ + i810_common.h \ + i810_cursor.c \ + i810_dga.c \ + i810_driver.c \ + i810.h \ + i810_io.c \ + i810_memory.c \ + i810_reg.h \ + i810_ring.h \ + i810_video.c \ + i810_wmark.c + +if DRI +liblegacy_i810_la_SOURCES +=\ + i810_dri.c \ + i810_dri.h \ + $(NULL) +endif + +if XVMC +liblegacy_i810_la_SOURCES += \ + i810_hwmc.h \ + i810_hwmc.c \ + $(NULL) +endif diff --git a/driver/xf86-video-intel/src/legacy/i810/Makefile.in b/driver/xf86-video-intel/src/legacy/i810/Makefile.in new file mode 100644 index 000000000..a25b98e0f --- /dev/null +++ b/driver/xf86-video-intel/src/legacy/i810/Makefile.in @@ -0,0 +1,613 @@ +# Makefile.in generated by automake 1.9.6 from Makefile.am. +# @configure_input@ + +# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, +# 2003, 2004, 2005 Free Software Foundation, Inc. +# This Makefile.in is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY, to the extent permitted by law; without +# even the implied warranty of MERCHANTABILITY or FITNESS FOR A +# PARTICULAR PURPOSE. + +@SET_MAKE@ + +srcdir = @srcdir@ +top_srcdir = @top_srcdir@ +VPATH = @srcdir@ +pkgdatadir = $(datadir)/@PACKAGE@ +pkglibdir = $(libdir)/@PACKAGE@ +pkgincludedir = $(includedir)/@PACKAGE@ +top_builddir = ../../.. +am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd +INSTALL = @INSTALL@ +install_sh_DATA = $(install_sh) -c -m 644 +install_sh_PROGRAM = $(install_sh) -c +install_sh_SCRIPT = $(install_sh) -c +INSTALL_HEADER = $(INSTALL_DATA) +transform = $(program_transform_name) +NORMAL_INSTALL = : +PRE_INSTALL = : +POST_INSTALL = : +NORMAL_UNINSTALL = : +PRE_UNINSTALL = : +POST_UNINSTALL = : +build_triplet = @build@ +host_triplet = @host@ +@DRI_TRUE@am__append_1 = \ +@DRI_TRUE@ i810_dri.c \ +@DRI_TRUE@ i810_dri.h \ +@DRI_TRUE@ $(NULL) + +@XVMC_TRUE@am__append_2 = \ +@XVMC_TRUE@ i810_hwmc.h \ +@XVMC_TRUE@ i810_hwmc.c \ +@XVMC_TRUE@ $(NULL) + +subdir = src/legacy/i810 +DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in +ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 +am__aclocal_m4_deps = $(top_srcdir)/configure.ac +am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \ + $(ACLOCAL_M4) +mkinstalldirs = $(SHELL) $(install_sh) -d +CONFIG_HEADER = $(top_builddir)/config.h +CONFIG_CLEAN_FILES = +LTLIBRARIES = $(noinst_LTLIBRARIES) +liblegacy_i810_la_LIBADD = +am__liblegacy_i810_la_SOURCES_DIST = i810_accel.c i810_common.h \ + i810_cursor.c i810_dga.c i810_driver.c i810.h i810_io.c \ + i810_memory.c i810_reg.h i810_ring.h i810_video.c i810_wmark.c \ + i810_dri.c i810_dri.h i810_hwmc.h i810_hwmc.c +@DRI_TRUE@am__objects_1 = i810_dri.lo +@XVMC_TRUE@am__objects_2 = i810_hwmc.lo +am_liblegacy_i810_la_OBJECTS = i810_accel.lo i810_cursor.lo \ + i810_dga.lo i810_driver.lo i810_io.lo i810_memory.lo \ + i810_video.lo i810_wmark.lo $(am__objects_1) $(am__objects_2) +liblegacy_i810_la_OBJECTS = $(am_liblegacy_i810_la_OBJECTS) +DEFAULT_INCLUDES = -I. -I$(srcdir) -I$(top_builddir) +depcomp = $(SHELL) $(top_srcdir)/depcomp +am__depfiles_maybe = depfiles +COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \ + $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) +LTCOMPILE = $(LIBTOOL) --tag=CC --mode=compile $(CC) $(DEFS) \ + $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) \ + $(AM_CFLAGS) $(CFLAGS) +CCLD = $(CC) +LINK = $(LIBTOOL) --tag=CC --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \ + $(AM_LDFLAGS) $(LDFLAGS) -o $@ +SOURCES = $(liblegacy_i810_la_SOURCES) +DIST_SOURCES = $(am__liblegacy_i810_la_SOURCES_DIST) +RECURSIVE_TARGETS = all-recursive check-recursive dvi-recursive \ + html-recursive info-recursive install-data-recursive \ + install-exec-recursive install-info-recursive \ + install-recursive installcheck-recursive installdirs-recursive \ + pdf-recursive ps-recursive uninstall-info-recursive \ + uninstall-recursive +ETAGS = etags +CTAGS = ctags +DIST_SUBDIRS = $(SUBDIRS) +DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST) +ACLOCAL = @ACLOCAL@ +ADMIN_MAN_DIR = @ADMIN_MAN_DIR@ +ADMIN_MAN_SUFFIX = @ADMIN_MAN_SUFFIX@ +AMDEP_FALSE = @AMDEP_FALSE@ +AMDEP_TRUE = @AMDEP_TRUE@ +AMTAR = @AMTAR@ +AM_DEFAULT_VERBOSITY = @AM_DEFAULT_VERBOSITY@ +APP_MAN_DIR = @APP_MAN_DIR@ +APP_MAN_SUFFIX = @APP_MAN_SUFFIX@ +AR = @AR@ +AUTOCONF = @AUTOCONF@ +AUTOHEADER = @AUTOHEADER@ +AUTOMAKE = @AUTOMAKE@ +AWK = @AWK@ +CC = @CC@ +CCDEPMODE = @CCDEPMODE@ +CFLAGS = @CFLAGS@ +CHANGELOG_CMD = @CHANGELOG_CMD@ +CPP = @CPP@ +CPPFLAGS = @CPPFLAGS@ +CWARNFLAGS = @CWARNFLAGS@ +CXX = @CXX@ +CXXCPP = @CXXCPP@ +CXXDEPMODE = @CXXDEPMODE@ +CXXFLAGS = @CXXFLAGS@ +CYGPATH_W = @CYGPATH_W@ +DEFS = @DEFS@ +DEPDIR = @DEPDIR@ +DRIVER_MAN_DIR = @DRIVER_MAN_DIR@ +DRIVER_MAN_SUFFIX = @DRIVER_MAN_SUFFIX@ +DRIVER_NAME = @DRIVER_NAME@ +DRI_CFLAGS = @DRI_CFLAGS@ +DRI_FALSE = @DRI_FALSE@ +DRI_LIBS = @DRI_LIBS@ +DRI_TRUE = @DRI_TRUE@ +DRM_CFLAGS = @DRM_CFLAGS@ +DRM_LIBS = @DRM_LIBS@ +DSYMUTIL = @DSYMUTIL@ +ECHO = @ECHO@ +ECHO_C = @ECHO_C@ +ECHO_N = @ECHO_N@ +ECHO_T = @ECHO_T@ +EGREP = @EGREP@ +EXEEXT = @EXEEXT@ +F77 = @F77@ +FFLAGS = @FFLAGS@ +FILE_MAN_DIR = @FILE_MAN_DIR@ +FILE_MAN_SUFFIX = @FILE_MAN_SUFFIX@ +GEN4ASM_CFLAGS = @GEN4ASM_CFLAGS@ +GEN4ASM_LIBS = @GEN4ASM_LIBS@ +GREP = @GREP@ +HAVE_GEN4ASM_FALSE = @HAVE_GEN4ASM_FALSE@ +HAVE_GEN4ASM_TRUE = @HAVE_GEN4ASM_TRUE@ +INSTALL_CMD = @INSTALL_CMD@ +INSTALL_DATA = @INSTALL_DATA@ +INSTALL_PROGRAM = @INSTALL_PROGRAM@ +INSTALL_SCRIPT = @INSTALL_SCRIPT@ +INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@ +KMS_ONLY_FALSE = @KMS_ONLY_FALSE@ +KMS_ONLY_TRUE = @KMS_ONLY_TRUE@ +LDFLAGS = @LDFLAGS@ +LIBOBJS = @LIBOBJS@ +LIBS = @LIBS@ +LIBTOOL = @LIBTOOL@ +LIB_MAN_DIR = @LIB_MAN_DIR@ +LIB_MAN_SUFFIX = @LIB_MAN_SUFFIX@ +LN_S = @LN_S@ +LTLIBOBJS = @LTLIBOBJS@ +MAINT = @MAINT@ +MAINTAINER_MODE_FALSE = @MAINTAINER_MODE_FALSE@ +MAINTAINER_MODE_TRUE = @MAINTAINER_MODE_TRUE@ +MAKEINFO = @MAKEINFO@ +MAN_SUBSTS = @MAN_SUBSTS@ +MISC_MAN_DIR = @MISC_MAN_DIR@ +MISC_MAN_SUFFIX = @MISC_MAN_SUFFIX@ +NMEDIT = @NMEDIT@ +OBJEXT = @OBJEXT@ +PACKAGE = @PACKAGE@ +PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@ +PACKAGE_NAME = @PACKAGE_NAME@ +PACKAGE_STRING = @PACKAGE_STRING@ +PACKAGE_TARNAME = @PACKAGE_TARNAME@ +PACKAGE_VERSION = @PACKAGE_VERSION@ +PATH_SEPARATOR = @PATH_SEPARATOR@ +PCIACCESS_CFLAGS = @PCIACCESS_CFLAGS@ +PCIACCESS_LIBS = @PCIACCESS_LIBS@ +PKG_CONFIG = @PKG_CONFIG@ +RANLIB = @RANLIB@ +SED = @SED@ +SET_MAKE = @SET_MAKE@ +SHELL = @SHELL@ +STRIP = @STRIP@ +VERSION = @VERSION@ +XORG_CFLAGS = @XORG_CFLAGS@ +XORG_LIBS = @XORG_LIBS@ +XORG_MAN_PAGE = @XORG_MAN_PAGE@ +XVMCLIB_CFLAGS = @XVMCLIB_CFLAGS@ +XVMCLIB_LIBS = @XVMCLIB_LIBS@ +XVMC_FALSE = @XVMC_FALSE@ +XVMC_TRUE = @XVMC_TRUE@ +ac_ct_CC = @ac_ct_CC@ +ac_ct_CXX = @ac_ct_CXX@ +ac_ct_F77 = @ac_ct_F77@ +am__fastdepCC_FALSE = @am__fastdepCC_FALSE@ +am__fastdepCC_TRUE = @am__fastdepCC_TRUE@ +am__fastdepCXX_FALSE = @am__fastdepCXX_FALSE@ +am__fastdepCXX_TRUE = @am__fastdepCXX_TRUE@ +am__include = @am__include@ +am__leading_dot = @am__leading_dot@ +am__quote = @am__quote@ +am__tar = @am__tar@ +am__untar = @am__untar@ +bindir = @bindir@ +build = @build@ +build_alias = @build_alias@ +build_cpu = @build_cpu@ +build_os = @build_os@ +build_vendor = @build_vendor@ +datadir = @datadir@ +datarootdir = @datarootdir@ +docdir = @docdir@ +dvidir = @dvidir@ +exec_prefix = @exec_prefix@ +host = @host@ +host_alias = @host_alias@ +host_cpu = @host_cpu@ +host_os = @host_os@ +host_vendor = @host_vendor@ +htmldir = @htmldir@ +includedir = @includedir@ +infodir = @infodir@ +install_sh = @install_sh@ +libdir = @libdir@ +libexecdir = @libexecdir@ +localedir = @localedir@ +localstatedir = @localstatedir@ +mandir = @mandir@ +mkdir_p = @mkdir_p@ +moduledir = @moduledir@ +oldincludedir = @oldincludedir@ +pdfdir = @pdfdir@ +prefix = @prefix@ +program_transform_name = @program_transform_name@ +psdir = @psdir@ +sbindir = @sbindir@ +sharedstatedir = @sharedstatedir@ +sysconfdir = @sysconfdir@ +target_alias = @target_alias@ +SUBDIRS = xvmc +noinst_LTLIBRARIES = liblegacy-i810.la +AM_CFLAGS = @CWARNFLAGS@ @XORG_CFLAGS@ @DRM_CFLAGS@ @DRI_CFLAGS@ @PCIACCESS_CFLAGS@ -I$(top_srcdir)/src +liblegacy_i810_la_SOURCES = i810_accel.c i810_common.h i810_cursor.c \ + i810_dga.c i810_driver.c i810.h i810_io.c i810_memory.c \ + i810_reg.h i810_ring.h i810_video.c i810_wmark.c \ + $(am__append_1) $(am__append_2) +all: all-recursive + +.SUFFIXES: +.SUFFIXES: .c .lo .o .obj +$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(am__configure_deps) + @for dep in $?; do \ + case '$(am__configure_deps)' in \ + *$$dep*) \ + cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh \ + && exit 0; \ + exit 1;; \ + esac; \ + done; \ + echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign src/legacy/i810/Makefile'; \ + cd $(top_srcdir) && \ + $(AUTOMAKE) --foreign src/legacy/i810/Makefile +.PRECIOUS: Makefile +Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status + @case '$?' in \ + *config.status*) \ + cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \ + *) \ + echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \ + cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \ + esac; + +$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES) + cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh + +$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps) + cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh +$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps) + cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh + +clean-noinstLTLIBRARIES: + -test -z "$(noinst_LTLIBRARIES)" || rm -f $(noinst_LTLIBRARIES) + @list='$(noinst_LTLIBRARIES)'; for p in $$list; do \ + dir="`echo $$p | sed -e 's|/[^/]*$$||'`"; \ + test "$$dir" != "$$p" || dir=.; \ + echo "rm -f \"$${dir}/so_locations\""; \ + rm -f "$${dir}/so_locations"; \ + done +liblegacy-i810.la: $(liblegacy_i810_la_OBJECTS) $(liblegacy_i810_la_DEPENDENCIES) + $(LINK) $(liblegacy_i810_la_LDFLAGS) $(liblegacy_i810_la_OBJECTS) $(liblegacy_i810_la_LIBADD) $(LIBS) + +mostlyclean-compile: + -rm -f *.$(OBJEXT) + +distclean-compile: + -rm -f *.tab.c + +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i810_accel.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i810_cursor.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i810_dga.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i810_dri.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i810_driver.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i810_hwmc.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i810_io.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i810_memory.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i810_video.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i810_wmark.Plo@am__quote@ + +.c.o: +@am__fastdepCC_TRUE@ if $(COMPILE) -MT $@ -MD -MP -MF "$(DEPDIR)/$*.Tpo" -c -o $@ $<; \ +@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/$*.Tpo" "$(DEPDIR)/$*.Po"; else rm -f "$(DEPDIR)/$*.Tpo"; exit 1; fi +@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(COMPILE) -c $< + +.c.obj: +@am__fastdepCC_TRUE@ if $(COMPILE) -MT $@ -MD -MP -MF "$(DEPDIR)/$*.Tpo" -c -o $@ `$(CYGPATH_W) '$<'`; \ +@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/$*.Tpo" "$(DEPDIR)/$*.Po"; else rm -f "$(DEPDIR)/$*.Tpo"; exit 1; fi +@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(COMPILE) -c `$(CYGPATH_W) '$<'` + +.c.lo: +@am__fastdepCC_TRUE@ if $(LTCOMPILE) -MT $@ -MD -MP -MF "$(DEPDIR)/$*.Tpo" -c -o $@ $<; \ +@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/$*.Tpo" "$(DEPDIR)/$*.Plo"; else rm -f "$(DEPDIR)/$*.Tpo"; exit 1; fi +@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=yes @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(LTCOMPILE) -c -o $@ $< + +mostlyclean-libtool: + -rm -f *.lo + +clean-libtool: + -rm -rf .libs _libs + +distclean-libtool: + -rm -f libtool +uninstall-info-am: + +# This directory's subdirectories are mostly independent; you can cd +# into them and run `make' without going through this Makefile. +# To change the values of `make' variables: instead of editing Makefiles, +# (1) if the variable is set in `config.status', edit `config.status' +# (which will cause the Makefiles to be regenerated when you run `make'); +# (2) otherwise, pass the desired values on the `make' command line. +$(RECURSIVE_TARGETS): + @failcom='exit 1'; \ + for f in x $$MAKEFLAGS; do \ + case $$f in \ + *=* | --[!k]*);; \ + *k*) failcom='fail=yes';; \ + esac; \ + done; \ + dot_seen=no; \ + target=`echo $@ | sed s/-recursive//`; \ + list='$(SUBDIRS)'; for subdir in $$list; do \ + echo "Making $$target in $$subdir"; \ + if test "$$subdir" = "."; then \ + dot_seen=yes; \ + local_target="$$target-am"; \ + else \ + local_target="$$target"; \ + fi; \ + (cd $$subdir && $(MAKE) $(AM_MAKEFLAGS) $$local_target) \ + || eval $$failcom; \ + done; \ + if test "$$dot_seen" = "no"; then \ + $(MAKE) $(AM_MAKEFLAGS) "$$target-am" || exit 1; \ + fi; test -z "$$fail" + +mostlyclean-recursive clean-recursive distclean-recursive \ +maintainer-clean-recursive: + @failcom='exit 1'; \ + for f in x $$MAKEFLAGS; do \ + case $$f in \ + *=* | --[!k]*);; \ + *k*) failcom='fail=yes';; \ + esac; \ + done; \ + dot_seen=no; \ + case "$@" in \ + distclean-* | maintainer-clean-*) list='$(DIST_SUBDIRS)' ;; \ + *) list='$(SUBDIRS)' ;; \ + esac; \ + rev=''; for subdir in $$list; do \ + if test "$$subdir" = "."; then :; else \ + rev="$$subdir $$rev"; \ + fi; \ + done; \ + rev="$$rev ."; \ + target=`echo $@ | sed s/-recursive//`; \ + for subdir in $$rev; do \ + echo "Making $$target in $$subdir"; \ + if test "$$subdir" = "."; then \ + local_target="$$target-am"; \ + else \ + local_target="$$target"; \ + fi; \ + (cd $$subdir && $(MAKE) $(AM_MAKEFLAGS) $$local_target) \ + || eval $$failcom; \ + done && test -z "$$fail" +tags-recursive: + list='$(SUBDIRS)'; for subdir in $$list; do \ + test "$$subdir" = . || (cd $$subdir && $(MAKE) $(AM_MAKEFLAGS) tags); \ + done +ctags-recursive: + list='$(SUBDIRS)'; for subdir in $$list; do \ + test "$$subdir" = . || (cd $$subdir && $(MAKE) $(AM_MAKEFLAGS) ctags); \ + done + +ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES) + list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \ + unique=`for i in $$list; do \ + if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \ + done | \ + $(AWK) ' { files[$$0] = 1; } \ + END { for (i in files) print i; }'`; \ + mkid -fID $$unique +tags: TAGS + +TAGS: tags-recursive $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \ + $(TAGS_FILES) $(LISP) + tags=; \ + here=`pwd`; \ + if ($(ETAGS) --etags-include --version) >/dev/null 2>&1; then \ + include_option=--etags-include; \ + empty_fix=.; \ + else \ + include_option=--include; \ + empty_fix=; \ + fi; \ + list='$(SUBDIRS)'; for subdir in $$list; do \ + if test "$$subdir" = .; then :; else \ + test ! -f $$subdir/TAGS || \ + tags="$$tags $$include_option=$$here/$$subdir/TAGS"; \ + fi; \ + done; \ + list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \ + unique=`for i in $$list; do \ + if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \ + done | \ + $(AWK) ' { files[$$0] = 1; } \ + END { for (i in files) print i; }'`; \ + if test -z "$(ETAGS_ARGS)$$tags$$unique"; then :; else \ + test -n "$$unique" || unique=$$empty_fix; \ + $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \ + $$tags $$unique; \ + fi +ctags: CTAGS +CTAGS: ctags-recursive $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \ + $(TAGS_FILES) $(LISP) + tags=; \ + here=`pwd`; \ + list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \ + unique=`for i in $$list; do \ + if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \ + done | \ + $(AWK) ' { files[$$0] = 1; } \ + END { for (i in files) print i; }'`; \ + test -z "$(CTAGS_ARGS)$$tags$$unique" \ + || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \ + $$tags $$unique + +GTAGS: + here=`$(am__cd) $(top_builddir) && pwd` \ + && cd $(top_srcdir) \ + && gtags -i $(GTAGS_ARGS) $$here + +distclean-tags: + -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags + +distdir: $(DISTFILES) + @srcdirstrip=`echo "$(srcdir)" | sed 's|.|.|g'`; \ + topsrcdirstrip=`echo "$(top_srcdir)" | sed 's|.|.|g'`; \ + list='$(DISTFILES)'; for file in $$list; do \ + case $$file in \ + $(srcdir)/*) file=`echo "$$file" | sed "s|^$$srcdirstrip/||"`;; \ + $(top_srcdir)/*) file=`echo "$$file" | sed "s|^$$topsrcdirstrip/|$(top_builddir)/|"`;; \ + esac; \ + if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \ + dir=`echo "$$file" | sed -e 's,/[^/]*$$,,'`; \ + if test "$$dir" != "$$file" && test "$$dir" != "."; then \ + dir="/$$dir"; \ + $(mkdir_p) "$(distdir)$$dir"; \ + else \ + dir=''; \ + fi; \ + if test -d $$d/$$file; then \ + if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \ + cp -pR $(srcdir)/$$file $(distdir)$$dir || exit 1; \ + fi; \ + cp -pR $$d/$$file $(distdir)$$dir || exit 1; \ + else \ + test -f $(distdir)/$$file \ + || cp -p $$d/$$file $(distdir)/$$file \ + || exit 1; \ + fi; \ + done + list='$(DIST_SUBDIRS)'; for subdir in $$list; do \ + if test "$$subdir" = .; then :; else \ + test -d "$(distdir)/$$subdir" \ + || $(mkdir_p) "$(distdir)/$$subdir" \ + || exit 1; \ + distdir=`$(am__cd) $(distdir) && pwd`; \ + top_distdir=`$(am__cd) $(top_distdir) && pwd`; \ + (cd $$subdir && \ + $(MAKE) $(AM_MAKEFLAGS) \ + top_distdir="$$top_distdir" \ + distdir="$$distdir/$$subdir" \ + distdir) \ + || exit 1; \ + fi; \ + done +check-am: all-am +check: check-recursive +all-am: Makefile $(LTLIBRARIES) +installdirs: installdirs-recursive +installdirs-am: +install: install-recursive +install-exec: install-exec-recursive +install-data: install-data-recursive +uninstall: uninstall-recursive + +install-am: all-am + @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am + +installcheck: installcheck-recursive +install-strip: + $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \ + install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \ + `test -z '$(STRIP)' || \ + echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install +mostlyclean-generic: + +clean-generic: + +distclean-generic: + -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES) + +maintainer-clean-generic: + @echo "This command is intended for maintainers to use" + @echo "it deletes files that may require special tools to rebuild." +clean: clean-recursive + +clean-am: clean-generic clean-libtool clean-noinstLTLIBRARIES \ + mostlyclean-am + +distclean: distclean-recursive + -rm -rf ./$(DEPDIR) + -rm -f Makefile +distclean-am: clean-am distclean-compile distclean-generic \ + distclean-libtool distclean-tags + +dvi: dvi-recursive + +dvi-am: + +html: html-recursive + +info: info-recursive + +info-am: + +install-data-am: + +install-exec-am: + +install-info: install-info-recursive + +install-man: + +installcheck-am: + +maintainer-clean: maintainer-clean-recursive + -rm -rf ./$(DEPDIR) + -rm -f Makefile +maintainer-clean-am: distclean-am maintainer-clean-generic + +mostlyclean: mostlyclean-recursive + +mostlyclean-am: mostlyclean-compile mostlyclean-generic \ + mostlyclean-libtool + +pdf: pdf-recursive + +pdf-am: + +ps: ps-recursive + +ps-am: + +uninstall-am: uninstall-info-am + +uninstall-info: uninstall-info-recursive + +.PHONY: $(RECURSIVE_TARGETS) CTAGS GTAGS all all-am check check-am \ + clean clean-generic clean-libtool clean-noinstLTLIBRARIES \ + clean-recursive ctags ctags-recursive distclean \ + distclean-compile distclean-generic distclean-libtool \ + distclean-recursive distclean-tags distdir dvi dvi-am html \ + html-am info info-am install install-am install-data \ + install-data-am install-exec install-exec-am install-info \ + install-info-am install-man install-strip installcheck \ + installcheck-am installdirs installdirs-am maintainer-clean \ + maintainer-clean-generic maintainer-clean-recursive \ + mostlyclean mostlyclean-compile mostlyclean-generic \ + mostlyclean-libtool mostlyclean-recursive pdf pdf-am ps ps-am \ + tags tags-recursive uninstall uninstall-am uninstall-info-am + +# Tell versions [3.59,3.63) of GNU make to not export all variables. +# Otherwise a system limit (for SysV at least) may be exceeded. +.NOEXPORT: diff --git a/driver/xf86-video-intel/src/i810.h b/driver/xf86-video-intel/src/legacy/i810/i810.h index 93b8b7609..662069518 100644 --- a/driver/xf86-video-intel/src/i810.h +++ b/driver/xf86-video-intel/src/legacy/i810/i810.h @@ -57,20 +57,13 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "sarea.h" #define _XF86DRI_SERVER_ #include "dri.h" -#include "GL/glxint.h" #include "i810_dri.h" #endif -#include "common.h" +#include "i810_common.h" #include "i810_ring.h" -#define I810_VERSION 4000 -#define I810_NAME "intel" -#define I810_DRIVER_NAME "intel" - -#define INTEL_VERSION_MAJOR PACKAGE_VERSION_MAJOR -#define INTEL_VERSION_MINOR PACKAGE_VERSION_MINOR -#define INTEL_VERSION_PATCH PACKAGE_VERSION_PATCHLEVEL +#include "intel_driver.h" /* HWMC Surfaces */ #define I810_MAX_SURFACES 7 @@ -236,8 +229,6 @@ typedef struct _I810Rec { DRIInfoPtr pDRIInfo; int drmSubFD; int numVisualConfigs; - __GLXvisualConfig *pVisualConfigs; - I810ConfigPrivPtr pVisualConfigsPriv; unsigned long dcacheHandle; unsigned long backHandle; unsigned long zHandle; diff --git a/driver/xf86-video-intel/src/i810_accel.c b/driver/xf86-video-intel/src/legacy/i810/i810_accel.c index ae4a6544e..9aa3e42cc 100644 --- a/driver/xf86-video-intel/src/i810_accel.c +++ b/driver/xf86-video-intel/src/legacy/i810/i810_accel.c @@ -129,7 +129,7 @@ I810AccelInit(ScreenPtr pScreen) */ if (pI810->Scratch.Size != 0) { int i; - int width = ((pScrn->displayWidth + 31) & ~31) / 8; + int width = ALIGN(pScrn->displayWidth, 32) / 8; int nr_buffers = pI810->Scratch.Size / width; unsigned char *ptr = pI810->FbBase + pI810->Scratch.Start; diff --git a/driver/xf86-video-intel/src/i810_common.h b/driver/xf86-video-intel/src/legacy/i810/i810_common.h index 29be444b4..14b299396 100644 --- a/driver/xf86-video-intel/src/i810_common.h +++ b/driver/xf86-video-intel/src/legacy/i810/i810_common.h @@ -35,6 +35,136 @@ #ifndef _I810_COMMON_H_ #define _I810_COMMON_H_ +/* Provide substitutes for gcc's __FUNCTION__ on other compilers */ +#if !defined(__GNUC__) && !defined(__FUNCTION__) +# if defined(__STDC__) && (__STDC_VERSION__>=199901L) /* C99 */ +# define __FUNCTION__ __func__ +# else +# define __FUNCTION__ "" +# endif +#endif + +#define PFX __FILE__,__LINE__,__FUNCTION__ +#define FUNCTION_NAME __FUNCTION__ + +#define KB(x) ((x) * 1024) +#define MB(x) ((x) * KB(1024)) + +#define ALIGN(i,m) (((i) + (m) - 1) & ~((m) - 1)) + +/* Using usleep() makes things noticably slow. */ +#if 0 +#define DELAY(x) usleep(x) +#else +#define DELAY(x) do {;} while (0) +#endif + +#define PrintErrorState I810PrintErrorState +#define WaitRingFunc I810WaitLpRing +#define RecPtr pI810 + +static inline void memset_volatile(volatile void *b, int c, size_t len) +{ + int i; + + for (i = 0; i < len; i++) + ((volatile char *)b)[i] = c; +} + +static inline void memcpy_volatile(volatile void *dst, const void *src, + size_t len) +{ + int i; + + for (i = 0; i < len; i++) + ((volatile char *)dst)[i] = ((volatile char *)src)[i]; +} + +/* Memory mapped register access macros */ +#define INREG8(addr) *(volatile uint8_t *)(RecPtr->MMIOBase + (addr)) +#define INREG16(addr) *(volatile uint16_t *)(RecPtr->MMIOBase + (addr)) +#define INREG(addr) *(volatile uint32_t *)(RecPtr->MMIOBase + (addr)) +#define INGTT(addr) *(volatile uint32_t *)(RecPtr->GTTBase + (addr)) +#define POSTING_READ(addr) (void)INREG(addr) + +#define OUTREG8(addr, val) do { \ + *(volatile uint8_t *)(RecPtr->MMIOBase + (addr)) = (val); \ + if (I810_DEBUG&DEBUG_VERBOSE_OUTREG) { \ + ErrorF("OUTREG8(0x%lx, 0x%lx) in %s\n", (unsigned long)(addr), \ + (unsigned long)(val), FUNCTION_NAME); \ + } \ +} while (0) + +#define OUTREG16(addr, val) do { \ + *(volatile uint16_t *)(RecPtr->MMIOBase + (addr)) = (val); \ + if (I810_DEBUG&DEBUG_VERBOSE_OUTREG) { \ + ErrorF("OUTREG16(0x%lx, 0x%lx) in %s\n", (unsigned long)(addr), \ + (unsigned long)(val), FUNCTION_NAME); \ + } \ +} while (0) + +#define OUTREG(addr, val) do { \ + *(volatile uint32_t *)(RecPtr->MMIOBase + (addr)) = (val); \ + if (I810_DEBUG&DEBUG_VERBOSE_OUTREG) { \ + ErrorF("OUTREG(0x%lx, 0x%lx) in %s\n", (unsigned long)(addr), \ + (unsigned long)(val), FUNCTION_NAME); \ + } \ +} while (0) + +/* To remove all debugging, make sure I810_DEBUG is defined as a + * preprocessor symbol, and equal to zero. + */ +#if 1 +#define I810_DEBUG 0 +#endif +#ifndef I810_DEBUG +#warning "Debugging enabled - expect reduced performance" +extern int I810_DEBUG; +#endif + +#define DEBUG_VERBOSE_ACCEL 0x1 +#define DEBUG_VERBOSE_SYNC 0x2 +#define DEBUG_VERBOSE_VGA 0x4 +#define DEBUG_VERBOSE_RING 0x8 +#define DEBUG_VERBOSE_OUTREG 0x10 +#define DEBUG_VERBOSE_MEMORY 0x20 +#define DEBUG_VERBOSE_CURSOR 0x40 +#define DEBUG_ALWAYS_SYNC 0x80 +#define DEBUG_VERBOSE_DRI 0x100 +#define DEBUG_VERBOSE_BIOS 0x200 + +/* Size of the mmio region. + */ +#define I810_REG_SIZE 0x80000 + +#define GTT_PAGE_SIZE KB(4) +#define PRIMARY_RINGBUFFER_SIZE KB(128) +#define MIN_SCRATCH_BUFFER_SIZE KB(16) +#define MAX_SCRATCH_BUFFER_SIZE KB(64) +#define HWCURSOR_SIZE GTT_PAGE_SIZE +#define HWCURSOR_SIZE_ARGB GTT_PAGE_SIZE * 4 + +/* Use a 64x64 HW cursor */ +#define I810_CURSOR_X 64 +#define I810_CURSOR_Y I810_CURSOR_X + +#define PIPE_NAME(n) ('A' + (n)) + +extern struct pci_device * +intel_host_bridge (void); + +/** + * Hints to CreatePixmap to tell the driver how the pixmap is going to be + * used. + * + * Compare to CREATE_PIXMAP_USAGE_* in the server. + */ +enum { + INTEL_CREATE_PIXMAP_TILING_X = 0x10000000, + INTEL_CREATE_PIXMAP_TILING_Y, + INTEL_CREATE_PIXMAP_TILING_NONE, +}; + #ifndef _I810_DEFINES_ #define _I810_DEFINES_ #define I810_USE_BATCH 1 diff --git a/driver/xf86-video-intel/src/i810_cursor.c b/driver/xf86-video-intel/src/legacy/i810/i810_cursor.c index 898a13642..898a13642 100644 --- a/driver/xf86-video-intel/src/i810_cursor.c +++ b/driver/xf86-video-intel/src/legacy/i810/i810_cursor.c diff --git a/driver/xf86-video-intel/src/i810_dga.c b/driver/xf86-video-intel/src/legacy/i810/i810_dga.c index 52a01b76f..d9ddda045 100644 --- a/driver/xf86-video-intel/src/i810_dga.c +++ b/driver/xf86-video-intel/src/legacy/i810/i810_dga.c @@ -78,8 +78,6 @@ I810DGAInit(ScreenPtr pScreen) int Bpp = pScrn->bitsPerPixel >> 3; int num = 0; - MARKER(); - pMode = firstMode = pScrn->modes; while (pMode) { @@ -148,10 +146,7 @@ I810_SetMode(ScrnInfoPtr pScrn, DGAModePtr pMode) int index = pScrn->pScreen->myNum; I810Ptr pI810 = I810PTR(pScrn); - MARKER(); - if (!pMode) { /* restore the original mode */ - DPRINTF(PFX, "Restoring original mode (from DGA mode)\n"); if (pI810->DGAactive) { pScrn->currentMode = I810SavedDGAModes[index]; pScrn->SwitchMode(index, pScrn->currentMode, 0); @@ -160,7 +155,6 @@ I810_SetMode(ScrnInfoPtr pScrn, DGAModePtr pMode) } } else { if (!pI810->DGAactive) { - DPRINTF(PFX, "Setting DGA mode\n"); I810SavedDGAModes[index] = pScrn->currentMode; pI810->DGAactive = TRUE; } @@ -176,8 +170,6 @@ I810_GetViewport(ScrnInfoPtr pScrn) { I810Ptr pI810 = I810PTR(pScrn); - MARKER(); - return pI810->DGAViewportStatus; } @@ -187,8 +179,6 @@ I810_SetViewport(ScrnInfoPtr pScrn, int x, int y, int flags) I810Ptr pI810 = I810PTR(pScrn); vgaHWPtr hwp = VGAHWPTR(pScrn); - MARKER(); - pScrn->AdjustFrame(pScrn->pScreen->myNum, x, y, flags); /* wait for retrace */ @@ -204,8 +194,6 @@ I810_FillRect(ScrnInfoPtr pScrn, { I810Ptr pI810 = I810PTR(pScrn); - MARKER(); - if (pI810->AccelInfoRec) { (*pI810->AccelInfoRec->SetupForSolidFill) (pScrn, color, GXcopy, ~0); (*pI810->AccelInfoRec->SubsequentSolidFillRect) (pScrn, x, y, w, h); @@ -218,8 +206,6 @@ I810_Sync(ScrnInfoPtr pScrn) { I810Ptr pI810 = I810PTR(pScrn); - MARKER(); - if (pI810->AccelInfoRec) { (*pI810->AccelInfoRec->Sync) (pScrn); } @@ -231,8 +217,6 @@ I810_BlitRect(ScrnInfoPtr pScrn, { I810Ptr pI810 = I810PTR(pScrn); - MARKER(); - if (pI810->AccelInfoRec) { int xdir = ((srcx < dstx) && (srcy == dsty)) ? -1 : 1; int ydir = (srcy < dsty) ? -1 : 1; @@ -252,8 +236,6 @@ I810_BlitTransRect(ScrnInfoPtr pScrn, int w, int h, int dstx, int dsty, unsigned long color) { - MARKER(); - /* this one should be separate since the XAA function would * prohibit usage of ~0 as the key */ } @@ -266,17 +248,11 @@ I810_OpenFramebuffer(ScrnInfoPtr pScrn, { I810Ptr pI810 = I810PTR(pScrn); - MARKER(); - *name = NULL; /* no special device */ *mem = (unsigned char *)pI810->LinearAddr; *size = pI810->FbMapSize; *offset = 0; *flags = DGA_NEED_ROOT; - DPRINTF(PFX, - " mem == 0x%.8x (pI810->LinearAddr)\n" - "size == %lu (pI810->FbMapSize)\n", *mem, *size); - return TRUE; } diff --git a/driver/xf86-video-intel/src/i810_dri.c b/driver/xf86-video-intel/src/legacy/i810/i810_dri.c index c40224238..c7a2db32d 100644 --- a/driver/xf86-video-intel/src/i810_dri.c +++ b/driver/xf86-video-intel/src/legacy/i810/i810_dri.c @@ -18,15 +18,12 @@ #include "shadow.h" #include "shadowfb.h" -#include "GL/glxtokens.h" - #include "i810.h" #include "i810_dri.h" static char I810KernelDriverName[] = "i810"; static char I810ClientDriverName[] = "i810"; -static Bool I810InitVisualConfigs(ScreenPtr pScreen); static Bool I810CreateContext(ScreenPtr pScreen, VisualPtr visual, drm_context_t hwContext, void *pVisualConfigPriv, DRIContextType contextStore); @@ -51,10 +48,6 @@ static void I810DRITransitionTo2d(ScreenPtr pScreen); static void I810DRIRefreshArea(ScrnInfoPtr pScrn, int num, BoxPtr pbox); -extern void GlxSetVisualConfigs(int nconfigs, - __GLXvisualConfig * configs, - void **configprivs); - static int i810_pitches[] = { 512, 1024, @@ -151,116 +144,6 @@ I810InitDma(ScrnInfoPtr pScrn) return TRUE; } -static Bool -I810InitVisualConfigs(ScreenPtr pScreen) -{ - ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; - I810Ptr pI810 = I810PTR(pScrn); - int numConfigs = 0; - __GLXvisualConfig *pConfigs = NULL; - I810ConfigPrivPtr pI810Configs = NULL; - I810ConfigPrivPtr *pI810ConfigPtrs = NULL; - int accum, stencil, db, depth; - int i; - - switch (pScrn->bitsPerPixel) { - case 8: - case 24: - case 32: - break; - case 16: - numConfigs = 8; - - pConfigs = - (__GLXvisualConfig *) calloc(sizeof(__GLXvisualConfig), - numConfigs); - if (!pConfigs) - return FALSE; - - pI810Configs = - (I810ConfigPrivPtr) calloc(sizeof(I810ConfigPrivRec), - numConfigs); - if (!pI810Configs) { - free(pConfigs); - return FALSE; - } - - pI810ConfigPtrs = - (I810ConfigPrivPtr *) calloc(sizeof(I810ConfigPrivPtr), - numConfigs); - if (!pI810ConfigPtrs) { - free(pConfigs); - free(pI810Configs); - return FALSE; - } - - for (i = 0; i < numConfigs; i++) - pI810ConfigPtrs[i] = &pI810Configs[i]; - - i = 0; - depth = 1; - for (accum = 0; accum <= 1; accum++) { - for (stencil = 0; stencil <= 1; stencil++) { - for (db = 1; db >= 0; db--) { - pConfigs[i].vid = -1; - pConfigs[i].class = -1; - pConfigs[i].rgba = TRUE; - pConfigs[i].redSize = 5; - pConfigs[i].greenSize = 6; - pConfigs[i].blueSize = 5; - pConfigs[i].alphaSize = 0; - pConfigs[i].redMask = 0x0000F800; - pConfigs[i].greenMask = 0x000007E0; - pConfigs[i].blueMask = 0x0000001F; - pConfigs[i].alphaMask = 0; - if (accum) { - pConfigs[i].accumRedSize = 16; - pConfigs[i].accumGreenSize = 16; - pConfigs[i].accumBlueSize = 16; - pConfigs[i].accumAlphaSize = 0; - } else { - pConfigs[i].accumRedSize = 0; - pConfigs[i].accumGreenSize = 0; - pConfigs[i].accumBlueSize = 0; - pConfigs[i].accumAlphaSize = 0; - } - pConfigs[i].doubleBuffer = db ? TRUE : FALSE; - pConfigs[i].stereo = FALSE; - pConfigs[i].bufferSize = 16; - if (depth) - pConfigs[i].depthSize = 16; - else - pConfigs[i].depthSize = 0; - if (stencil) - pConfigs[i].stencilSize = 8; - else - pConfigs[i].stencilSize = 0; - pConfigs[i].auxBuffers = 0; - pConfigs[i].level = 0; - if (stencil || accum) - pConfigs[i].visualRating = GLX_SLOW_CONFIG; - else - pConfigs[i].visualRating = GLX_NONE; - pConfigs[i].transparentPixel = GLX_NONE; - pConfigs[i].transparentRed = 0; - pConfigs[i].transparentGreen = 0; - pConfigs[i].transparentBlue = 0; - pConfigs[i].transparentAlpha = 0; - pConfigs[i].transparentIndex = 0; - i++; - } - } - } - assert(i == numConfigs); - break; - } - pI810->numVisualConfigs = numConfigs; - pI810->pVisualConfigs = pConfigs; - pI810->pVisualConfigsPriv = pI810Configs; - GlxSetVisualConfigs(numConfigs, pConfigs, (void **)pI810ConfigPtrs); - return TRUE; -} - static unsigned int mylog2(unsigned int n) { @@ -293,10 +176,8 @@ I810DRIScreenInit(ScreenPtr pScreen) if (pScrn->depth != 16) return FALSE; - /* Check that the GLX, DRI, and DRM modules have been loaded by testing + /* Check that the DRI, and DRM modules have been loaded by testing * for known symbols in each module. */ - if (!xf86LoaderCheckSymbol("GlxSetVisualConfigs")) - return FALSE; if (!xf86LoaderCheckSymbol("drmAvailable")) return FALSE; if (!xf86LoaderCheckSymbol("DRIQueryVersion")) { @@ -999,13 +880,6 @@ I810DRIScreenInit(ScreenPtr pScreen) pI810DRI->auxPitchBits = pI810->auxPitchBits; pI810DRI->sarea_priv_offset = sizeof(XF86DRISAREARec); - if (!(I810InitVisualConfigs(pScreen))) { - xf86DrvMsg(pScreen->myNum, X_ERROR, - "[dri] I810InitVisualConfigs failed. Disabling DRI.\n"); - DRICloseScreen(pScreen); - return FALSE; - } - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "[dri] visual configs initialized.\n"); pI810->pDRIInfo->driverSwapMethod = DRI_HIDE_X_CONTEXT; @@ -1061,10 +935,6 @@ I810DRICloseScreen(ScreenPtr pScreen) DRIDestroyInfoRec(pI810->pDRIInfo); pI810->pDRIInfo = NULL; } - if (pI810->pVisualConfigs) - free(pI810->pVisualConfigs); - if (pI810->pVisualConfigsPriv) - free(pI810->pVisualConfigsPriv); } static Bool diff --git a/driver/xf86-video-intel/src/i810_dri.h b/driver/xf86-video-intel/src/legacy/i810/i810_dri.h index 16b6f087c..16b6f087c 100644 --- a/driver/xf86-video-intel/src/i810_dri.h +++ b/driver/xf86-video-intel/src/legacy/i810/i810_dri.h diff --git a/driver/xf86-video-intel/src/i810_driver.c b/driver/xf86-video-intel/src/legacy/i810/i810_driver.c index 345854f2d..fa9989625 100644 --- a/driver/xf86-video-intel/src/i810_driver.c +++ b/driver/xf86-video-intel/src/legacy/i810/i810_driver.c @@ -70,22 +70,13 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "vbe.h" #include "i810.h" -#include "i830.h" #ifdef XF86DRI #include "dri.h" #endif -/* Required Functions: */ +#include "../legacy.h" -static void I810Identify(int flags); -static Bool I810DriverFunc(ScrnInfoPtr pScrn, xorgDriverFuncOp op, pointer ptr); -static Bool intel_pci_probe (DriverPtr drv, - int entity_num, - struct pci_device *dev, - intptr_t match_data); - -#ifndef I830_ONLY static Bool I810PreInit(ScrnInfoPtr pScrn, int flags); static Bool I810ScreenInit(int Index, ScreenPtr pScreen, int argc, char **argv); @@ -99,144 +90,7 @@ static void I810DisplayPowerManagementSet(ScrnInfoPtr pScrn, int flags); static ModeStatus I810ValidMode(int scrnIndex, DisplayModePtr mode, Bool verbose, int flags); -#endif /* I830_ONLY */ - -#define INTEL_DEVICE_MATCH(d,i) \ - { 0x8086, (d), PCI_MATCH_ANY, PCI_MATCH_ANY, 0, 0, (i) } - -static const struct pci_id_match intel_device_match[] = { -#ifndef I830_ONLY - INTEL_DEVICE_MATCH (PCI_CHIP_I810, 0 ), - INTEL_DEVICE_MATCH (PCI_CHIP_I810_DC100, 0 ), - INTEL_DEVICE_MATCH (PCI_CHIP_I810_E, 0 ), - INTEL_DEVICE_MATCH (PCI_CHIP_I815, 0 ), -#endif - INTEL_DEVICE_MATCH (PCI_CHIP_I830_M, 0 ), - INTEL_DEVICE_MATCH (PCI_CHIP_845_G, 0 ), - INTEL_DEVICE_MATCH (PCI_CHIP_I855_GM, 0 ), - INTEL_DEVICE_MATCH (PCI_CHIP_I865_G, 0 ), - INTEL_DEVICE_MATCH (PCI_CHIP_I915_G, 0 ), - INTEL_DEVICE_MATCH (PCI_CHIP_E7221_G, 0 ), - INTEL_DEVICE_MATCH (PCI_CHIP_I915_GM, 0 ), - INTEL_DEVICE_MATCH (PCI_CHIP_I945_G, 0 ), - INTEL_DEVICE_MATCH (PCI_CHIP_I945_GM, 0 ), - INTEL_DEVICE_MATCH (PCI_CHIP_I945_GME, 0 ), - INTEL_DEVICE_MATCH (PCI_CHIP_IGD_GM, 0 ), - INTEL_DEVICE_MATCH (PCI_CHIP_IGD_G, 0 ), - INTEL_DEVICE_MATCH (PCI_CHIP_I965_G, 0 ), - INTEL_DEVICE_MATCH (PCI_CHIP_G35_G, 0 ), - INTEL_DEVICE_MATCH (PCI_CHIP_I965_Q, 0 ), - INTEL_DEVICE_MATCH (PCI_CHIP_I946_GZ, 0 ), - INTEL_DEVICE_MATCH (PCI_CHIP_I965_GM, 0 ), - INTEL_DEVICE_MATCH (PCI_CHIP_I965_GME, 0 ), - INTEL_DEVICE_MATCH (PCI_CHIP_G33_G, 0 ), - INTEL_DEVICE_MATCH (PCI_CHIP_Q35_G, 0 ), - INTEL_DEVICE_MATCH (PCI_CHIP_Q33_G, 0 ), - INTEL_DEVICE_MATCH (PCI_CHIP_GM45_GM, 0 ), - INTEL_DEVICE_MATCH (PCI_CHIP_IGD_E_G, 0 ), - INTEL_DEVICE_MATCH (PCI_CHIP_G45_G, 0 ), - INTEL_DEVICE_MATCH (PCI_CHIP_Q45_G, 0 ), - INTEL_DEVICE_MATCH (PCI_CHIP_G41_G, 0 ), - INTEL_DEVICE_MATCH (PCI_CHIP_B43_G, 0 ), - INTEL_DEVICE_MATCH (PCI_CHIP_IGDNG_D_G, 0 ), - INTEL_DEVICE_MATCH (PCI_CHIP_IGDNG_M_G, 0 ), - { 0, 0, 0 }, -}; - -_X_EXPORT DriverRec I810 = { - I810_VERSION, - I810_DRIVER_NAME, - I810Identify, - NULL, - I810AvailableOptions, - NULL, - 0, - I810DriverFunc, - intel_device_match, - intel_pci_probe -}; - -/* *INDENT-OFF* */ -/* Chipsets */ -static SymTabRec I810Chipsets[] = { -#ifndef I830_ONLY - {PCI_CHIP_I810, "i810"}, - {PCI_CHIP_I810_DC100, "i810-dc100"}, - {PCI_CHIP_I810_E, "i810e"}, - {PCI_CHIP_I815, "i815"}, -#endif - {PCI_CHIP_I830_M, "i830M"}, - {PCI_CHIP_845_G, "845G"}, - {PCI_CHIP_I855_GM, "852GM/855GM"}, - {PCI_CHIP_I865_G, "865G"}, - {PCI_CHIP_I915_G, "915G"}, - {PCI_CHIP_E7221_G, "E7221 (i915)"}, - {PCI_CHIP_I915_GM, "915GM"}, - {PCI_CHIP_I945_G, "945G"}, - {PCI_CHIP_I945_GM, "945GM"}, - {PCI_CHIP_I945_GME, "945GME"}, - {PCI_CHIP_IGD_GM, "Pineview GM"}, - {PCI_CHIP_IGD_G, "Pineview G"}, - {PCI_CHIP_I965_G, "965G"}, - {PCI_CHIP_G35_G, "G35"}, - {PCI_CHIP_I965_Q, "965Q"}, - {PCI_CHIP_I946_GZ, "946GZ"}, - {PCI_CHIP_I965_GM, "965GM"}, - {PCI_CHIP_I965_GME, "965GME/GLE"}, - {PCI_CHIP_G33_G, "G33"}, - {PCI_CHIP_Q35_G, "Q35"}, - {PCI_CHIP_Q33_G, "Q33"}, - {PCI_CHIP_GM45_GM, "GM45"}, - {PCI_CHIP_IGD_E_G, "4 Series"}, - {PCI_CHIP_G45_G, "G45/G43"}, - {PCI_CHIP_Q45_G, "Q45/Q43"}, - {PCI_CHIP_G41_G, "G41"}, - {PCI_CHIP_B43_G, "B43"}, - {PCI_CHIP_IGDNG_D_G, "Clarkdale"}, - {PCI_CHIP_IGDNG_M_G, "Arrandale"}, - {-1, NULL} -}; -static PciChipsets I810PciChipsets[] = { -#ifndef I830_ONLY - {PCI_CHIP_I810, PCI_CHIP_I810, NULL}, - {PCI_CHIP_I810_DC100, PCI_CHIP_I810_DC100, NULL}, - {PCI_CHIP_I810_E, PCI_CHIP_I810_E, NULL}, - {PCI_CHIP_I815, PCI_CHIP_I815, NULL}, -#endif - {PCI_CHIP_I830_M, PCI_CHIP_I830_M, NULL}, - {PCI_CHIP_845_G, PCI_CHIP_845_G, NULL}, - {PCI_CHIP_I855_GM, PCI_CHIP_I855_GM, NULL}, - {PCI_CHIP_I865_G, PCI_CHIP_I865_G, NULL}, - {PCI_CHIP_I915_G, PCI_CHIP_I915_G, NULL}, - {PCI_CHIP_E7221_G, PCI_CHIP_E7221_G, NULL}, - {PCI_CHIP_I915_GM, PCI_CHIP_I915_GM, NULL}, - {PCI_CHIP_I945_G, PCI_CHIP_I945_G, NULL}, - {PCI_CHIP_I945_GM, PCI_CHIP_I945_GM, NULL}, - {PCI_CHIP_I945_GME, PCI_CHIP_I945_GME, NULL}, - {PCI_CHIP_IGD_GM, PCI_CHIP_IGD_GM, NULL}, - {PCI_CHIP_IGD_G, PCI_CHIP_IGD_G, NULL}, - {PCI_CHIP_I965_G, PCI_CHIP_I965_G, NULL}, - {PCI_CHIP_G35_G, PCI_CHIP_G35_G, NULL}, - {PCI_CHIP_I965_Q, PCI_CHIP_I965_Q, NULL}, - {PCI_CHIP_I946_GZ, PCI_CHIP_I946_GZ, NULL}, - {PCI_CHIP_I965_GM, PCI_CHIP_I965_GM, NULL}, - {PCI_CHIP_I965_GME, PCI_CHIP_I965_GME, NULL}, - {PCI_CHIP_G33_G, PCI_CHIP_G33_G, NULL}, - {PCI_CHIP_Q35_G, PCI_CHIP_Q35_G, NULL}, - {PCI_CHIP_Q33_G, PCI_CHIP_Q33_G, NULL}, - {PCI_CHIP_GM45_GM, PCI_CHIP_GM45_GM, NULL}, - {PCI_CHIP_IGD_E_G, PCI_CHIP_IGD_E_G, NULL}, - {PCI_CHIP_G45_G, PCI_CHIP_G45_G, NULL}, - {PCI_CHIP_Q45_G, PCI_CHIP_Q45_G, NULL}, - {PCI_CHIP_G41_G, PCI_CHIP_G41_G, NULL}, - {PCI_CHIP_B43_G, PCI_CHIP_B43_G, NULL}, - {PCI_CHIP_IGDNG_D_G, PCI_CHIP_IGDNG_D_G, NULL}, - {PCI_CHIP_IGDNG_M_G, PCI_CHIP_IGDNG_M_G, NULL}, - {-1, -1, NULL } -}; - -#ifndef I830_ONLY typedef enum { OPTION_NOACCEL, OPTION_SW_CURSOR, @@ -264,7 +118,6 @@ static const OptionInfoRec I810Options[] = { {-1, NULL, OPTV_NONE, {0}, FALSE} }; /* *INDENT-ON* */ -#endif #ifndef I810_DEBUG int I810_DEBUG = (0 @@ -279,7 +132,6 @@ int I810_DEBUG = (0 ); #endif -#ifndef I830_ONLY #ifdef XF86DRI static int i810_pitches[] = { 512, @@ -289,57 +141,9 @@ static int i810_pitches[] = { 0 }; #endif -#endif int I830EntityIndex = -1; -#ifdef XFree86LOADER - -static MODULESETUPPROTO(i810Setup); - -static XF86ModuleVersionInfo intelVersRec = { - "intel", - MODULEVENDORSTRING, - MODINFOSTRING1, - MODINFOSTRING2, - XORG_VERSION_CURRENT, - INTEL_VERSION_MAJOR, INTEL_VERSION_MINOR, INTEL_VERSION_PATCH, - ABI_CLASS_VIDEODRV, - ABI_VIDEODRV_VERSION, - MOD_CLASS_VIDEODRV, - {0, 0, 0, 0} -}; - -_X_EXPORT XF86ModuleData intelModuleData = { &intelVersRec, i810Setup, NULL }; - -static pointer -i810Setup(pointer module, pointer opts, int *errmaj, int *errmin) -{ - static Bool setupDone = 0; - - /* This module should be loaded only once, but check to be sure. - */ - if (!setupDone) { - setupDone = 1; - xf86AddDriver(&I810, module, - HaveDriverFuncs - ); - - /* - * The return value must be non-NULL on success even though there - * is no TearDownProc. - */ - return (pointer) 1; - } else { - if (errmaj) - *errmaj = LDR_ONCEONLY; - return NULL; - } -} - -#endif - -#ifndef I830_ONLY /* * I810GetRec and I810FreeRec -- * @@ -367,55 +171,6 @@ I810FreeRec(ScrnInfoPtr pScrn) free(pScrn->driverPrivate); pScrn->driverPrivate = NULL; } -#endif - -/* - * I810Identify -- - * - * Returns the string name for the driver based on the chipset. In this - * case it will always be an I810, so we can return a static string. - * - */ -static void -I810Identify(int flags) -{ - xf86PrintChipsets(I810_NAME, "Driver for Intel Integrated Graphics Chipsets", - I810Chipsets); -} - -const OptionInfoRec * -I810AvailableOptions(int chipid, int busid) -{ -#ifndef I830_ONLY - const OptionInfoRec *pOptions; - - if ((pOptions = I830AvailableOptions(chipid, busid))) - return pOptions; - return I810Options; -#else - return I830AvailableOptions(chipid, busid); -#endif -} - -static Bool -I810DriverFunc(ScrnInfoPtr pScrn, xorgDriverFuncOp op, pointer ptr) -{ - xorgHWFlags *flag; - - switch (op) { - case GET_REQUIRED_HW_INTERFACES: - flag = (CARD32*)ptr; -#ifdef KMS_ONLY - (*flag) = 0; -#else - (*flag) = HW_IO | HW_MMIO; -#endif - return TRUE; - default: - /* Unknown or deprecated function */ - return FALSE; - } -} struct pci_device * intel_host_bridge (void) @@ -432,58 +187,6 @@ intel_host_bridge (void) return bridge; } -/* - * intel_pci_probe -- - * - * Look through the PCI bus to find cards that are intel boards. - * Setup the dispatch table for the rest of the driver functions. - * - */ -static Bool intel_pci_probe (DriverPtr driver, - int entity_num, - struct pci_device *device, - intptr_t match_data) -{ - ScrnInfoPtr scrn = NULL; - EntityInfoPtr entity; - - scrn = xf86ConfigPciEntity (scrn, 0, entity_num, I810PciChipsets, - NULL, - NULL, NULL, NULL, NULL); - if (scrn != NULL) - { - scrn->driverVersion = I810_VERSION; - scrn->driverName = I810_DRIVER_NAME; - scrn->name = I810_NAME; - scrn->Probe = NULL; - - entity = xf86GetEntityInfo (entity_num); - - switch (DEVICE_ID(device)) { -#ifndef I830_ONLY - case PCI_CHIP_I810: - case PCI_CHIP_I810_DC100: - case PCI_CHIP_I810_E: - case PCI_CHIP_I815: - scrn->PreInit = I810PreInit; - scrn->ScreenInit = I810ScreenInit; - scrn->SwitchMode = I810SwitchMode; - scrn->AdjustFrame = I810AdjustFrame; - scrn->EnterVT = I810EnterVT; - scrn->LeaveVT = I810LeaveVT; - scrn->FreeScreen = I810FreeScreen; - scrn->ValidMode = I810ValidMode; - break; -#endif - default: - intel_init_scrn(scrn); - break; - } - } - return scrn != NULL; -} - -#ifndef I830_ONLY static void I810ProbeDDC(ScrnInfoPtr pScrn, int index) { @@ -540,6 +243,7 @@ I810PreInit(ScrnInfoPtr pScrn, int flags) rgb defaultWeight = { 0, 0, 0 }; int mem; Bool enable; + struct intel_chipset chipset; if (pScrn->numEntities != 1) return FALSE; @@ -677,6 +381,8 @@ I810PreInit(ScrnInfoPtr pScrn, int flags) /* We have to use PIO to probe, because we haven't mapped yet */ I810SetPIOAccess(pI810); + intel_detect_chipset(pScrn, pI810->PciInfo, &chipset); + /* * Set the Chipset and ChipRev, allowing config file entries to * override. @@ -685,14 +391,14 @@ I810PreInit(ScrnInfoPtr pScrn, int flags) pScrn->chipset = pI810->pEnt->device->chipset; from = X_CONFIG; } else if (pI810->pEnt->device->chipID >= 0) { - pScrn->chipset = (char *)xf86TokenToString(I810Chipsets, + pScrn->chipset = (char *)xf86TokenToString(intel_chipsets, pI810->pEnt->device->chipID); from = X_CONFIG; xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "ChipID override: 0x%04X\n", pI810->pEnt->device->chipID); } else { from = X_PROBED; - pScrn->chipset = (char *)xf86TokenToString(I810Chipsets, + pScrn->chipset = (char *)xf86TokenToString(intel_chipsets, DEVICE_ID(pI810->PciInfo)); } if (pI810->pEnt->device->chipRev >= 0) { @@ -1854,24 +1560,14 @@ I810AllocateFront(ScrnInfoPtr pScrn) if (!I810AllocLow(&(pI810->FrontBuffer), &(pI810->SysMem), - ((pI810->FbMemBox.x2 * - pI810->FbMemBox.y2 * pI810->cpp) + 4095) & ~4095)) { + ALIGN((pI810->FbMemBox.x2 * pI810->FbMemBox.y2 * pI810->cpp), 4096))) { xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Framebuffer allocation failed\n"); return FALSE; - } else - DPRINTF(PFX, - "Frame buffer at 0x%.8x (%luk, %lu bytes)\n", - pI810->FrontBuffer.Start, - pI810->FrontBuffer.Size / 1024, pI810->FrontBuffer.Size); + } memset(pI810->LpRing, 0, sizeof(I810RingBuffer)); if (I810AllocLow(&(pI810->LpRing->mem), &(pI810->SysMem), 16 * 4096)) { - DPRINTF(PFX, - "Ring buffer at 0x%.8x (%luk, %lu bytes)\n", - pI810->LpRing->mem.Start, - pI810->LpRing->mem.Size / 1024, pI810->LpRing->mem.Size); - pI810->LpRing->tail_mask = pI810->LpRing->mem.Size - 1; pI810->LpRing->virtual_start = pI810->FbBase + pI810->LpRing->mem.Start; pI810->LpRing->head = 0; @@ -1885,11 +1581,6 @@ I810AllocateFront(ScrnInfoPtr pScrn) if (I810AllocLow(&pI810->Scratch, &(pI810->SysMem), 64 * 1024) || I810AllocLow(&pI810->Scratch, &(pI810->SysMem), 16 * 1024)) { - DPRINTF(PFX, - "Scratch memory at 0x%.8x (%luk, %lu bytes)\n", - pI810->Scratch.Start, - pI810->Scratch.Size / 1024, pI810->Scratch.Size); - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Allocated Scratch Memory\n"); } else { xf86DrvMsg(pScrn->scrnIndex, X_ERROR, @@ -2427,4 +2118,22 @@ I810DisplayPowerManagementSet(ScrnInfoPtr pScrn, int PowerManagementMode, /* Set the DPMS mode */ OUTREG8(DPMS_SYNC_SELECT, DPMSSyncSelect); } -#endif /* I830_ONLY */ + +const OptionInfoRec * +lg_i810_available_options(int chipid, int busid) +{ + return I810Options; +} + + +void lg_i810_init(ScrnInfoPtr scrn) +{ + scrn->PreInit = I810PreInit; + scrn->ScreenInit = I810ScreenInit; + scrn->SwitchMode = I810SwitchMode; + scrn->AdjustFrame = I810AdjustFrame; + scrn->EnterVT = I810EnterVT; + scrn->LeaveVT = I810LeaveVT; + scrn->FreeScreen = I810FreeScreen; + scrn->ValidMode = I810ValidMode; +} diff --git a/driver/xf86-video-intel/src/i810_hwmc.c b/driver/xf86-video-intel/src/legacy/i810/i810_hwmc.c index 724e1beab..724e1beab 100644 --- a/driver/xf86-video-intel/src/i810_hwmc.c +++ b/driver/xf86-video-intel/src/legacy/i810/i810_hwmc.c diff --git a/driver/xf86-video-intel/src/i810_io.c b/driver/xf86-video-intel/src/legacy/i810/i810_io.c index b67f2ca27..b67f2ca27 100644 --- a/driver/xf86-video-intel/src/i810_io.c +++ b/driver/xf86-video-intel/src/legacy/i810/i810_io.c diff --git a/driver/xf86-video-intel/src/i810_memory.c b/driver/xf86-video-intel/src/legacy/i810/i810_memory.c index f57ddbe22..f57ddbe22 100644 --- a/driver/xf86-video-intel/src/i810_memory.c +++ b/driver/xf86-video-intel/src/legacy/i810/i810_memory.c diff --git a/driver/xf86-video-intel/src/i810_reg.h b/driver/xf86-video-intel/src/legacy/i810/i810_reg.h index 9f78eb1d5..f350de480 100644 --- a/driver/xf86-video-intel/src/i810_reg.h +++ b/driver/xf86-video-intel/src/legacy/i810/i810_reg.h @@ -2452,14 +2452,6 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4) -#define I85X_CAPID 0x44 -#define I85X_VARIANT_MASK 0x7 -#define I85X_VARIANT_SHIFT 5 -#define I855_GME 0x0 -#define I855_GM 0x4 -#define I852_GME 0x2 -#define I852_GM 0x5 - #define I915_GCFGC 0xf0 #define I915_LOW_FREQUENCY_ENABLE (1 << 7) #define I915_DISPLAY_CLOCK_190_200_MHZ (0 << 4) @@ -2581,247 +2573,6 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define ENABLE_FOG_CONST (1<<24) #define ENABLE_FOG_DENSITY (1<<23) -/* - * New regs for broadwater -- we need to split this file up sensibly somehow. - */ -#define BRW_3D(Pipeline,Opcode,Subopcode) ((3 << 29) | \ - ((Pipeline) << 27) | \ - ((Opcode) << 24) | \ - ((Subopcode) << 16)) - -#define BRW_URB_FENCE BRW_3D(0, 0, 0) -#define BRW_CS_URB_STATE BRW_3D(0, 0, 1) -#define BRW_CONSTANT_BUFFER BRW_3D(0, 0, 2) -#define BRW_STATE_PREFETCH BRW_3D(0, 0, 3) - -#define BRW_STATE_BASE_ADDRESS BRW_3D(0, 1, 1) -#define BRW_STATE_SIP BRW_3D(0, 1, 2) -#define BRW_PIPELINE_SELECT BRW_3D(0, 1, 4) - -#define NEW_PIPELINE_SELECT BRW_3D(1, 1, 4) - -#define BRW_MEDIA_STATE_POINTERS BRW_3D(2, 0, 0) -#define BRW_MEDIA_OBJECT BRW_3D(2, 1, 0) - -#define BRW_3DSTATE_PIPELINED_POINTERS BRW_3D(3, 0, 0) -#define BRW_3DSTATE_BINDING_TABLE_POINTERS BRW_3D(3, 0, 1) -#define BRW_3DSTATE_VERTEX_BUFFERS BRW_3D(3, 0, 8) -#define BRW_3DSTATE_VERTEX_ELEMENTS BRW_3D(3, 0, 9) -#define BRW_3DSTATE_INDEX_BUFFER BRW_3D(3, 0, 0xa) -#define BRW_3DSTATE_VF_STATISTICS BRW_3D(3, 0, 0xb) - -#define BRW_3DSTATE_DRAWING_RECTANGLE BRW_3D(3, 1, 0) -#define BRW_3DSTATE_CONSTANT_COLOR BRW_3D(3, 1, 1) -#define BRW_3DSTATE_SAMPLER_PALETTE_LOAD BRW_3D(3, 1, 2) -#define BRW_3DSTATE_CHROMA_KEY BRW_3D(3, 1, 4) -#define BRW_3DSTATE_DEPTH_BUFFER BRW_3D(3, 1, 5) -#define BRW_3DSTATE_POLY_STIPPLE_OFFSET BRW_3D(3, 1, 6) -#define BRW_3DSTATE_POLY_STIPPLE_PATTERN BRW_3D(3, 1, 7) -#define BRW_3DSTATE_LINE_STIPPLE BRW_3D(3, 1, 8) -#define BRW_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP BRW_3D(3, 1, 9) -/* These two are BLC and CTG only, not BW or CL */ -#define BRW_3DSTATE_AA_LINE_PARAMS BRW_3D(3, 1, 0xa) -#define BRW_3DSTATE_GS_SVB_INDEX BRW_3D(3, 1, 0xb) - -#define BRW_PIPE_CONTROL BRW_3D(3, 2, 0) - -#define BRW_3DPRIMITIVE BRW_3D(3, 3, 0) - -#define PIPELINE_SELECT_3D 0 -#define PIPELINE_SELECT_MEDIA 1 - -#define UF0_CS_REALLOC (1 << 13) -#define UF0_VFE_REALLOC (1 << 12) -#define UF0_SF_REALLOC (1 << 11) -#define UF0_CLIP_REALLOC (1 << 10) -#define UF0_GS_REALLOC (1 << 9) -#define UF0_VS_REALLOC (1 << 8) -#define UF1_CLIP_FENCE_SHIFT 20 -#define UF1_GS_FENCE_SHIFT 10 -#define UF1_VS_FENCE_SHIFT 0 -#define UF2_CS_FENCE_SHIFT 20 -#define UF2_VFE_FENCE_SHIFT 10 -#define UF2_SF_FENCE_SHIFT 0 - -/* for BRW_STATE_BASE_ADDRESS */ -#define BASE_ADDRESS_MODIFY (1 << 0) - -/* for BRW_3DSTATE_PIPELINED_POINTERS */ -#define BRW_GS_DISABLE 0 -#define BRW_GS_ENABLE 1 -#define BRW_CLIP_DISABLE 0 -#define BRW_CLIP_ENABLE 1 - -/* for BRW_PIPE_CONTROL */ -#define BRW_PIPE_CONTROL_NOWRITE (0 << 14) -#define BRW_PIPE_CONTROL_WRITE_QWORD (1 << 14) -#define BRW_PIPE_CONTROL_WRITE_DEPTH (2 << 14) -#define BRW_PIPE_CONTROL_WRITE_TIME (3 << 14) -#define BRW_PIPE_CONTROL_DEPTH_STALL (1 << 13) -#define BRW_PIPE_CONTROL_WC_FLUSH (1 << 12) -#define BRW_PIPE_CONTROL_IS_FLUSH (1 << 11) -#define BRW_PIPE_CONTROL_NOTIFY_ENABLE (1 << 8) -#define BRW_PIPE_CONTROL_GLOBAL_GTT (1 << 2) -#define BRW_PIPE_CONTROL_LOCAL_PGTT (0 << 2) - -/* VERTEX_BUFFER_STATE Structure */ -#define VB0_BUFFER_INDEX_SHIFT 27 -#define VB0_VERTEXDATA (0 << 26) -#define VB0_INSTANCEDATA (1 << 26) -#define VB0_BUFFER_PITCH_SHIFT 0 - -/* VERTEX_ELEMENT_STATE Structure */ -#define VE0_VERTEX_BUFFER_INDEX_SHIFT 27 -#define VE0_VALID (1 << 26) -#define VE0_FORMAT_SHIFT 16 -#define VE0_OFFSET_SHIFT 0 -#define VE1_VFCOMPONENT_0_SHIFT 28 -#define VE1_VFCOMPONENT_1_SHIFT 24 -#define VE1_VFCOMPONENT_2_SHIFT 20 -#define VE1_VFCOMPONENT_3_SHIFT 16 -#define VE1_DESTINATION_ELEMENT_OFFSET_SHIFT 0 - -/* 3DPRIMITIVE bits */ -#define BRW_3DPRIMITIVE_VERTEX_SEQUENTIAL (0 << 15) -#define BRW_3DPRIMITIVE_VERTEX_RANDOM (1 << 15) -/* Primitive types are in brw_defines.h */ -#define BRW_3DPRIMITIVE_TOPOLOGY_SHIFT 10 - -#define BRW_SVG_CTL 0x7400 - -#define BRW_SVG_CTL_GS_BA (0 << 8) -#define BRW_SVG_CTL_SS_BA (1 << 8) -#define BRW_SVG_CTL_IO_BA (2 << 8) -#define BRW_SVG_CTL_GS_AUB (3 << 8) -#define BRW_SVG_CTL_IO_AUB (4 << 8) -#define BRW_SVG_CTL_SIP (5 << 8) - -#define BRW_SVG_RDATA 0x7404 -#define BRW_SVG_WORK_CTL 0x7408 - -#define BRW_VF_CTL 0x7500 - -#define BRW_VF_CTL_SNAPSHOT_COMPLETE (1 << 31) -#define BRW_VF_CTL_SNAPSHOT_MUX_SELECT_THREADID (0 << 8) -#define BRW_VF_CTL_SNAPSHOT_MUX_SELECT_VF_DEBUG (1 << 8) -#define BRW_VF_CTL_SNAPSHOT_TYPE_VERTEX_SEQUENCE (0 << 4) -#define BRW_VF_CTL_SNAPSHOT_TYPE_VERTEX_INDEX (1 << 4) -#define BRW_VF_CTL_SKIP_INITIAL_PRIMITIVES (1 << 3) -#define BRW_VF_CTL_MAX_PRIMITIVES_LIMIT_ENABLE (1 << 2) -#define BRW_VF_CTL_VERTEX_RANGE_LIMIT_ENABLE (1 << 1) -#define BRW_VF_CTL_SNAPSHOT_ENABLE (1 << 0) - -#define BRW_VF_STRG_VAL 0x7504 -#define BRW_VF_STR_VL_OVR 0x7508 -#define BRW_VF_VC_OVR 0x750c -#define BRW_VF_STR_PSKIP 0x7510 -#define BRW_VF_MAX_PRIM 0x7514 -#define BRW_VF_RDATA 0x7518 - -#define BRW_VS_CTL 0x7600 -#define BRW_VS_CTL_SNAPSHOT_COMPLETE (1 << 31) -#define BRW_VS_CTL_SNAPSHOT_MUX_VERTEX_0 (0 << 8) -#define BRW_VS_CTL_SNAPSHOT_MUX_VERTEX_1 (1 << 8) -#define BRW_VS_CTL_SNAPSHOT_MUX_VALID_COUNT (2 << 8) -#define BRW_VS_CTL_SNAPSHOT_MUX_VS_KERNEL_POINTER (3 << 8) -#define BRW_VS_CTL_SNAPSHOT_ALL_THREADS (1 << 2) -#define BRW_VS_CTL_THREAD_SNAPSHOT_ENABLE (1 << 1) -#define BRW_VS_CTL_SNAPSHOT_ENABLE (1 << 0) - -#define BRW_VS_STRG_VAL 0x7604 -#define BRW_VS_RDATA 0x7608 - -#define BRW_SF_CTL 0x7b00 -#define BRW_SF_CTL_SNAPSHOT_COMPLETE (1 << 31) -#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_0_FF_ID (0 << 8) -#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_0_REL_COUNT (1 << 8) -#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_1_FF_ID (2 << 8) -#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_1_REL_COUNT (3 << 8) -#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_2_FF_ID (4 << 8) -#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_2_REL_COUNT (5 << 8) -#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_COUNT (6 << 8) -#define BRW_SF_CTL_SNAPSHOT_MUX_SF_KERNEL_POINTER (7 << 8) -#define BRW_SF_CTL_MIN_MAX_PRIMITIVE_RANGE_ENABLE (1 << 4) -#define BRW_SF_CTL_DEBUG_CLIP_RECTANGLE_ENABLE (1 << 3) -#define BRW_SF_CTL_SNAPSHOT_ALL_THREADS (1 << 2) -#define BRW_SF_CTL_THREAD_SNAPSHOT_ENABLE (1 << 1) -#define BRW_SF_CTL_SNAPSHOT_ENABLE (1 << 0) - -#define BRW_SF_STRG_VAL 0x7b04 -#define BRW_SF_RDATA 0x7b18 - -#define BRW_WIZ_CTL 0x7c00 -#define BRW_WIZ_CTL_SNAPSHOT_COMPLETE (1 << 31) -#define BRW_WIZ_CTL_SUBSPAN_INSTANCE_SHIFT 16 -#define BRW_WIZ_CTL_SNAPSHOT_MUX_WIZ_KERNEL_POINTER (0 << 8) -#define BRW_WIZ_CTL_SNAPSHOT_MUX_SUBSPAN_INSTANCE (1 << 8) -#define BRW_WIZ_CTL_SNAPSHOT_MUX_PRIMITIVE_SEQUENCE (2 << 8) -#define BRW_WIZ_CTL_SINGLE_SUBSPAN_DISPATCH (1 << 6) -#define BRW_WIZ_CTL_IGNORE_COLOR_SCOREBOARD_STALLS (1 << 5) -#define BRW_WIZ_CTL_ENABLE_SUBSPAN_INSTANCE_COMPARE (1 << 4) -#define BRW_WIZ_CTL_USE_UPSTREAM_SNAPSHOT_FLAG (1 << 3) -#define BRW_WIZ_CTL_SNAPSHOT_ALL_THREADS (1 << 2) -#define BRW_WIZ_CTL_THREAD_SNAPSHOT_ENABLE (1 << 1) -#define BRW_WIZ_CTL_SNAPSHOT_ENABLE (1 << 0) - -#define BRW_WIZ_STRG_VAL 0x7c04 -#define BRW_WIZ_RDATA 0x7c18 - -#define BRW_TS_CTL 0x7e00 -#define BRW_TS_CTL_SNAPSHOT_COMPLETE (1 << 31) -#define BRW_TS_CTL_SNAPSHOT_MESSAGE_ERROR (0 << 8) -#define BRW_TS_CTL_SNAPSHOT_INTERFACE_DESCRIPTOR (3 << 8) -#define BRW_TS_CTL_SNAPSHOT_ALL_CHILD_THREADS (1 << 2) -#define BRW_TS_CTL_SNAPSHOT_ALL_ROOT_THREADS (1 << 1) -#define BRW_TS_CTL_SNAPSHOT_ENABLE (1 << 0) - -#define BRW_TS_STRG_VAL 0x7e04 -#define BRW_TS_RDATA 0x7e08 - -#define BRW_TD_CTL 0x8000 -#define BRW_TD_CTL_MUX_SHIFT 8 -#define BRW_TD_CTL_EXTERNAL_HALT_R0_DEBUG_MATCH (1 << 7) -#define BRW_TD_CTL_FORCE_EXTERNAL_HALT (1 << 6) -#define BRW_TD_CTL_EXCEPTION_MASK_OVERRIDE (1 << 5) -#define BRW_TD_CTL_FORCE_THREAD_BREAKPOINT_ENABLE (1 << 4) -#define BRW_TD_CTL_BREAKPOINT_ENABLE (1 << 2) -#define BRW_TD_CTL2 0x8004 -#define BRW_TD_CTL2_ILLEGAL_OPCODE_EXCEPTION_OVERRIDE (1 << 28) -#define BRW_TD_CTL2_MASKSTACK_EXCEPTION_OVERRIDE (1 << 26) -#define BRW_TD_CTL2_SOFTWARE_EXCEPTION_OVERRIDE (1 << 25) -#define BRW_TD_CTL2_ACTIVE_THREAD_LIMIT_SHIFT 16 -#define BRW_TD_CTL2_ACTIVE_THREAD_LIMIT_ENABLE (1 << 8) -#define BRW_TD_CTL2_THREAD_SPAWNER_EXECUTION_MASK_ENABLE (1 << 7) -#define BRW_TD_CTL2_WIZ_EXECUTION_MASK_ENABLE (1 << 6) -#define BRW_TD_CTL2_SF_EXECUTION_MASK_ENABLE (1 << 5) -#define BRW_TD_CTL2_CLIPPER_EXECUTION_MASK_ENABLE (1 << 4) -#define BRW_TD_CTL2_GS_EXECUTION_MASK_ENABLE (1 << 3) -#define BRW_TD_CTL2_VS_EXECUTION_MASK_ENABLE (1 << 0) -#define BRW_TD_VF_VS_EMSK 0x8008 -#define BRW_TD_GS_EMSK 0x800c -#define BRW_TD_CLIP_EMSK 0x8010 -#define BRW_TD_SF_EMSK 0x8014 -#define BRW_TD_WIZ_EMSK 0x8018 -#define BRW_TD_0_6_EHTRG_VAL 0x801c -#define BRW_TD_0_7_EHTRG_VAL 0x8020 -#define BRW_TD_0_6_EHTRG_MSK 0x8024 -#define BRW_TD_0_7_EHTRG_MSK 0x8028 -#define BRW_TD_RDATA 0x802c -#define BRW_TD_TS_EMSK 0x8030 - -#define BRW_EU_CTL 0x8800 -#define BRW_EU_CTL_SELECT_SHIFT 16 -#define BRW_EU_CTL_DATA_MUX_SHIFT 8 -#define BRW_EU_ATT_0 0x8810 -#define BRW_EU_ATT_1 0x8814 -#define BRW_EU_ATT_DATA_0 0x8820 -#define BRW_EU_ATT_DATA_1 0x8824 -#define BRW_EU_ATT_CLR_0 0x8830 -#define BRW_EU_ATT_CLR_1 0x8834 -#define BRW_EU_RDATA 0x8840 - -/* End regs for broadwater */ - #define MAX_DISPLAY_PIPES 2 typedef enum { diff --git a/driver/xf86-video-intel/src/i810_ring.h b/driver/xf86-video-intel/src/legacy/i810/i810_ring.h index e6e354fdd..e6e354fdd 100644 --- a/driver/xf86-video-intel/src/i810_ring.h +++ b/driver/xf86-video-intel/src/legacy/i810/i810_ring.h diff --git a/driver/xf86-video-intel/src/i810_video.c b/driver/xf86-video-intel/src/legacy/i810/i810_video.c index 85b5b65c6..91af7da58 100644 --- a/driver/xf86-video-intel/src/i810_video.c +++ b/driver/xf86-video-intel/src/legacy/i810/i810_video.c @@ -750,14 +750,14 @@ I810DisplayVideo( switch(id) { case FOURCC_YV12: case FOURCC_I420: - swidth = (width + 7) & ~7; + swidth = ALIGN(width, 8); overlay->SWID = (swidth << 15) | swidth; overlay->SWIDQW = (swidth << 12) | (swidth >> 3); break; case FOURCC_UYVY: case FOURCC_YUY2: default: - swidth = ((width + 3) & ~3) << 1; + swidth = ALIGN(width, 4) << 1; overlay->SWID = swidth; overlay->SWIDQW = swidth >> 3; break; @@ -1013,15 +1013,15 @@ I810PutImage( switch(id) { case FOURCC_YV12: case FOURCC_I420: - srcPitch = (width + 3) & ~3; - dstPitch = ((width >> 1) + 7) & ~7; /* of chroma */ + srcPitch = ALIGN(width, 4); + dstPitch = ALIGN((width >> 1), 8); /* of chroma */ size = dstPitch * height * 3; break; case FOURCC_UYVY: case FOURCC_YUY2: default: srcPitch = (width << 1); - dstPitch = (srcPitch + 7) & ~7; + dstPitch = ALIGN(srcPitch, 8); size = dstPitch * height; break; } @@ -1062,13 +1062,13 @@ I810PutImage( /* copy data */ top = y1 >> 16; left = (x1 >> 16) & ~1; - npixels = ((((x2 + 0xffff) >> 16) + 1) & ~1) - left; + npixels = ALIGN(((x2 + 0xffff) >> 16), 2) - left; switch(id) { case FOURCC_YV12: case FOURCC_I420: top &= ~1; - nlines = ((((y2 + 0xffff) >> 16) + 1) & ~1) - top; + nlines = ALIGN(((y2 + 0xffff) >> 16), 2) - top; I810CopyPlanarData(pScrn, buf, srcPitch, dstPitch, height, top, left, nlines, npixels, id); break; @@ -1213,8 +1213,8 @@ I810AllocateSurface( if((w > 1024) || (h > 1024)) return BadAlloc; - w = (w + 1) & ~1; - pitch = ((w << 1) + 15) & ~15; + w = ALIGN(w, 2); + pitch = ALIGN((w << 1), 16); bpp = pScrn->bitsPerPixel >> 3; fbpitch = bpp * pScrn->displayWidth; size = ((pitch * h) + bpp - 1) / bpp; diff --git a/driver/xf86-video-intel/src/i810_wmark.c b/driver/xf86-video-intel/src/legacy/i810/i810_wmark.c index 71b2a825b..71b2a825b 100644 --- a/driver/xf86-video-intel/src/i810_wmark.c +++ b/driver/xf86-video-intel/src/legacy/i810/i810_wmark.c diff --git a/driver/xf86-video-intel/src/xvmc/I810XvMC.c b/driver/xf86-video-intel/src/legacy/i810/xvmc/I810XvMC.c index 0754ff44b..0754ff44b 100644 --- a/driver/xf86-video-intel/src/xvmc/I810XvMC.c +++ b/driver/xf86-video-intel/src/legacy/i810/xvmc/I810XvMC.c diff --git a/driver/xf86-video-intel/src/xvmc/I810XvMC.h b/driver/xf86-video-intel/src/legacy/i810/xvmc/I810XvMC.h index 9de32ebac..9e3114733 100644 --- a/driver/xf86-video-intel/src/xvmc/I810XvMC.h +++ b/driver/xf86-video-intel/src/legacy/i810/xvmc/I810XvMC.h @@ -42,7 +42,7 @@ THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include <stdint.h> #include "xf86drm.h" -#include "i810_common.h" +#include "../i810_common.h" #include <X11/Xlibint.h> diff --git a/driver/xf86-video-intel/src/legacy/i810/xvmc/Makefile.am b/driver/xf86-video-intel/src/legacy/i810/xvmc/Makefile.am new file mode 100644 index 000000000..1bac3119a --- /dev/null +++ b/driver/xf86-video-intel/src/legacy/i810/xvmc/Makefile.am @@ -0,0 +1,11 @@ +if XVMC +lib_LTLIBRARIES=libI810XvMC.la +endif + +libI810XvMC_la_SOURCES = I810XvMC.c \ + I810XvMC.h + +AM_CFLAGS = @CWARNFLAGS@ @XORG_CFLAGS@ @DRM_CFLAGS@ @DRI_CFLAGS@ -DTRUE=1 -DFALSE=0 + +libI810XvMC_la_LDFLAGS = -version-number 1:0:0 +libI810XvMC_la_LIBADD = @DRI_LIBS@ @DRM_LIBS@ @XVMCLIB_LIBS@ diff --git a/driver/xf86-video-intel/src/legacy/i810/xvmc/Makefile.in b/driver/xf86-video-intel/src/legacy/i810/xvmc/Makefile.in new file mode 100644 index 000000000..caad473ad --- /dev/null +++ b/driver/xf86-video-intel/src/legacy/i810/xvmc/Makefile.in @@ -0,0 +1,506 @@ +# Makefile.in generated by automake 1.9.6 from Makefile.am. +# @configure_input@ + +# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, +# 2003, 2004, 2005 Free Software Foundation, Inc. +# This Makefile.in is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY, to the extent permitted by law; without +# even the implied warranty of MERCHANTABILITY or FITNESS FOR A +# PARTICULAR PURPOSE. + +@SET_MAKE@ + +srcdir = @srcdir@ +top_srcdir = @top_srcdir@ +VPATH = @srcdir@ +pkgdatadir = $(datadir)/@PACKAGE@ +pkglibdir = $(libdir)/@PACKAGE@ +pkgincludedir = $(includedir)/@PACKAGE@ +top_builddir = ../../../.. +am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd +INSTALL = @INSTALL@ +install_sh_DATA = $(install_sh) -c -m 644 +install_sh_PROGRAM = $(install_sh) -c +install_sh_SCRIPT = $(install_sh) -c +INSTALL_HEADER = $(INSTALL_DATA) +transform = $(program_transform_name) +NORMAL_INSTALL = : +PRE_INSTALL = : +POST_INSTALL = : +NORMAL_UNINSTALL = : +PRE_UNINSTALL = : +POST_UNINSTALL = : +build_triplet = @build@ +host_triplet = @host@ +subdir = src/legacy/i810/xvmc +DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in +ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 +am__aclocal_m4_deps = $(top_srcdir)/configure.ac +am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \ + $(ACLOCAL_M4) +mkinstalldirs = $(SHELL) $(install_sh) -d +CONFIG_HEADER = $(top_builddir)/config.h +CONFIG_CLEAN_FILES = +am__vpath_adj_setup = srcdirstrip=`echo "$(srcdir)" | sed 's|.|.|g'`; +am__vpath_adj = case $$p in \ + $(srcdir)/*) f=`echo "$$p" | sed "s|^$$srcdirstrip/||"`;; \ + *) f=$$p;; \ + esac; +am__strip_dir = `echo $$p | sed -e 's|^.*/||'`; +am__installdirs = "$(DESTDIR)$(libdir)" +libLTLIBRARIES_INSTALL = $(INSTALL) +LTLIBRARIES = $(lib_LTLIBRARIES) +libI810XvMC_la_DEPENDENCIES = +am_libI810XvMC_la_OBJECTS = I810XvMC.lo +libI810XvMC_la_OBJECTS = $(am_libI810XvMC_la_OBJECTS) +@XVMC_TRUE@am_libI810XvMC_la_rpath = -rpath $(libdir) +DEFAULT_INCLUDES = -I. -I$(srcdir) -I$(top_builddir) +depcomp = $(SHELL) $(top_srcdir)/depcomp +am__depfiles_maybe = depfiles +COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \ + $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) +LTCOMPILE = $(LIBTOOL) --tag=CC --mode=compile $(CC) $(DEFS) \ + $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) \ + $(AM_CFLAGS) $(CFLAGS) +CCLD = $(CC) +LINK = $(LIBTOOL) --tag=CC --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \ + $(AM_LDFLAGS) $(LDFLAGS) -o $@ +SOURCES = $(libI810XvMC_la_SOURCES) +DIST_SOURCES = $(libI810XvMC_la_SOURCES) +ETAGS = etags +CTAGS = ctags +DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST) +ACLOCAL = @ACLOCAL@ +ADMIN_MAN_DIR = @ADMIN_MAN_DIR@ +ADMIN_MAN_SUFFIX = @ADMIN_MAN_SUFFIX@ +AMDEP_FALSE = @AMDEP_FALSE@ +AMDEP_TRUE = @AMDEP_TRUE@ +AMTAR = @AMTAR@ +AM_DEFAULT_VERBOSITY = @AM_DEFAULT_VERBOSITY@ +APP_MAN_DIR = @APP_MAN_DIR@ +APP_MAN_SUFFIX = @APP_MAN_SUFFIX@ +AR = @AR@ +AUTOCONF = @AUTOCONF@ +AUTOHEADER = @AUTOHEADER@ +AUTOMAKE = @AUTOMAKE@ +AWK = @AWK@ +CC = @CC@ +CCDEPMODE = @CCDEPMODE@ +CFLAGS = @CFLAGS@ +CHANGELOG_CMD = @CHANGELOG_CMD@ +CPP = @CPP@ +CPPFLAGS = @CPPFLAGS@ +CWARNFLAGS = @CWARNFLAGS@ +CXX = @CXX@ +CXXCPP = @CXXCPP@ +CXXDEPMODE = @CXXDEPMODE@ +CXXFLAGS = @CXXFLAGS@ +CYGPATH_W = @CYGPATH_W@ +DEFS = @DEFS@ +DEPDIR = @DEPDIR@ +DRIVER_MAN_DIR = @DRIVER_MAN_DIR@ +DRIVER_MAN_SUFFIX = @DRIVER_MAN_SUFFIX@ +DRIVER_NAME = @DRIVER_NAME@ +DRI_CFLAGS = @DRI_CFLAGS@ +DRI_FALSE = @DRI_FALSE@ +DRI_LIBS = @DRI_LIBS@ +DRI_TRUE = @DRI_TRUE@ +DRM_CFLAGS = @DRM_CFLAGS@ +DRM_LIBS = @DRM_LIBS@ +DSYMUTIL = @DSYMUTIL@ +ECHO = @ECHO@ +ECHO_C = @ECHO_C@ +ECHO_N = @ECHO_N@ +ECHO_T = @ECHO_T@ +EGREP = @EGREP@ +EXEEXT = @EXEEXT@ +F77 = @F77@ +FFLAGS = @FFLAGS@ +FILE_MAN_DIR = @FILE_MAN_DIR@ +FILE_MAN_SUFFIX = @FILE_MAN_SUFFIX@ +GEN4ASM_CFLAGS = @GEN4ASM_CFLAGS@ +GEN4ASM_LIBS = @GEN4ASM_LIBS@ +GREP = @GREP@ +HAVE_GEN4ASM_FALSE = @HAVE_GEN4ASM_FALSE@ +HAVE_GEN4ASM_TRUE = @HAVE_GEN4ASM_TRUE@ +INSTALL_CMD = @INSTALL_CMD@ +INSTALL_DATA = @INSTALL_DATA@ +INSTALL_PROGRAM = @INSTALL_PROGRAM@ +INSTALL_SCRIPT = @INSTALL_SCRIPT@ +INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@ +KMS_ONLY_FALSE = @KMS_ONLY_FALSE@ +KMS_ONLY_TRUE = @KMS_ONLY_TRUE@ +LDFLAGS = @LDFLAGS@ +LIBOBJS = @LIBOBJS@ +LIBS = @LIBS@ +LIBTOOL = @LIBTOOL@ +LIB_MAN_DIR = @LIB_MAN_DIR@ +LIB_MAN_SUFFIX = @LIB_MAN_SUFFIX@ +LN_S = @LN_S@ +LTLIBOBJS = @LTLIBOBJS@ +MAINT = @MAINT@ +MAINTAINER_MODE_FALSE = @MAINTAINER_MODE_FALSE@ +MAINTAINER_MODE_TRUE = @MAINTAINER_MODE_TRUE@ +MAKEINFO = @MAKEINFO@ +MAN_SUBSTS = @MAN_SUBSTS@ +MISC_MAN_DIR = @MISC_MAN_DIR@ +MISC_MAN_SUFFIX = @MISC_MAN_SUFFIX@ +NMEDIT = @NMEDIT@ +OBJEXT = @OBJEXT@ +PACKAGE = @PACKAGE@ +PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@ +PACKAGE_NAME = @PACKAGE_NAME@ +PACKAGE_STRING = @PACKAGE_STRING@ +PACKAGE_TARNAME = @PACKAGE_TARNAME@ +PACKAGE_VERSION = @PACKAGE_VERSION@ +PATH_SEPARATOR = @PATH_SEPARATOR@ +PCIACCESS_CFLAGS = @PCIACCESS_CFLAGS@ +PCIACCESS_LIBS = @PCIACCESS_LIBS@ +PKG_CONFIG = @PKG_CONFIG@ +RANLIB = @RANLIB@ +SED = @SED@ +SET_MAKE = @SET_MAKE@ +SHELL = @SHELL@ +STRIP = @STRIP@ +VERSION = @VERSION@ +XORG_CFLAGS = @XORG_CFLAGS@ +XORG_LIBS = @XORG_LIBS@ +XORG_MAN_PAGE = @XORG_MAN_PAGE@ +XVMCLIB_CFLAGS = @XVMCLIB_CFLAGS@ +XVMCLIB_LIBS = @XVMCLIB_LIBS@ +XVMC_FALSE = @XVMC_FALSE@ +XVMC_TRUE = @XVMC_TRUE@ +ac_ct_CC = @ac_ct_CC@ +ac_ct_CXX = @ac_ct_CXX@ +ac_ct_F77 = @ac_ct_F77@ +am__fastdepCC_FALSE = @am__fastdepCC_FALSE@ +am__fastdepCC_TRUE = @am__fastdepCC_TRUE@ +am__fastdepCXX_FALSE = @am__fastdepCXX_FALSE@ +am__fastdepCXX_TRUE = @am__fastdepCXX_TRUE@ +am__include = @am__include@ +am__leading_dot = @am__leading_dot@ +am__quote = @am__quote@ +am__tar = @am__tar@ +am__untar = @am__untar@ +bindir = @bindir@ +build = @build@ +build_alias = @build_alias@ +build_cpu = @build_cpu@ +build_os = @build_os@ +build_vendor = @build_vendor@ +datadir = @datadir@ +datarootdir = @datarootdir@ +docdir = @docdir@ +dvidir = @dvidir@ +exec_prefix = @exec_prefix@ +host = @host@ +host_alias = @host_alias@ +host_cpu = @host_cpu@ +host_os = @host_os@ +host_vendor = @host_vendor@ +htmldir = @htmldir@ +includedir = @includedir@ +infodir = @infodir@ +install_sh = @install_sh@ +libdir = @libdir@ +libexecdir = @libexecdir@ +localedir = @localedir@ +localstatedir = @localstatedir@ +mandir = @mandir@ +mkdir_p = @mkdir_p@ +moduledir = @moduledir@ +oldincludedir = @oldincludedir@ +pdfdir = @pdfdir@ +prefix = @prefix@ +program_transform_name = @program_transform_name@ +psdir = @psdir@ +sbindir = @sbindir@ +sharedstatedir = @sharedstatedir@ +sysconfdir = @sysconfdir@ +target_alias = @target_alias@ +@XVMC_TRUE@lib_LTLIBRARIES = libI810XvMC.la +libI810XvMC_la_SOURCES = I810XvMC.c \ + I810XvMC.h + +AM_CFLAGS = @CWARNFLAGS@ @XORG_CFLAGS@ @DRM_CFLAGS@ @DRI_CFLAGS@ -DTRUE=1 -DFALSE=0 +libI810XvMC_la_LDFLAGS = -version-number 1:0:0 +libI810XvMC_la_LIBADD = @DRI_LIBS@ @DRM_LIBS@ @XVMCLIB_LIBS@ +all: all-am + +.SUFFIXES: +.SUFFIXES: .c .lo .o .obj +$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(am__configure_deps) + @for dep in $?; do \ + case '$(am__configure_deps)' in \ + *$$dep*) \ + cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh \ + && exit 0; \ + exit 1;; \ + esac; \ + done; \ + echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign src/legacy/i810/xvmc/Makefile'; \ + cd $(top_srcdir) && \ + $(AUTOMAKE) --foreign src/legacy/i810/xvmc/Makefile +.PRECIOUS: Makefile +Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status + @case '$?' in \ + *config.status*) \ + cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \ + *) \ + echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \ + cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \ + esac; + +$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES) + cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh + +$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps) + cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh +$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps) + cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh +install-libLTLIBRARIES: $(lib_LTLIBRARIES) + @$(NORMAL_INSTALL) + test -z "$(libdir)" || $(mkdir_p) "$(DESTDIR)$(libdir)" + @list='$(lib_LTLIBRARIES)'; for p in $$list; do \ + if test -f $$p; then \ + f=$(am__strip_dir) \ + echo " $(LIBTOOL) --mode=install $(libLTLIBRARIES_INSTALL) $(INSTALL_STRIP_FLAG) '$$p' '$(DESTDIR)$(libdir)/$$f'"; \ + $(LIBTOOL) --mode=install $(libLTLIBRARIES_INSTALL) $(INSTALL_STRIP_FLAG) "$$p" "$(DESTDIR)$(libdir)/$$f"; \ + else :; fi; \ + done + +uninstall-libLTLIBRARIES: + @$(NORMAL_UNINSTALL) + @set -x; list='$(lib_LTLIBRARIES)'; for p in $$list; do \ + p=$(am__strip_dir) \ + echo " $(LIBTOOL) --mode=uninstall rm -f '$(DESTDIR)$(libdir)/$$p'"; \ + $(LIBTOOL) --mode=uninstall rm -f "$(DESTDIR)$(libdir)/$$p"; \ + done + +clean-libLTLIBRARIES: + -test -z "$(lib_LTLIBRARIES)" || rm -f $(lib_LTLIBRARIES) + @list='$(lib_LTLIBRARIES)'; for p in $$list; do \ + dir="`echo $$p | sed -e 's|/[^/]*$$||'`"; \ + test "$$dir" != "$$p" || dir=.; \ + echo "rm -f \"$${dir}/so_locations\""; \ + rm -f "$${dir}/so_locations"; \ + done +libI810XvMC.la: $(libI810XvMC_la_OBJECTS) $(libI810XvMC_la_DEPENDENCIES) + $(LINK) $(am_libI810XvMC_la_rpath) $(libI810XvMC_la_LDFLAGS) $(libI810XvMC_la_OBJECTS) $(libI810XvMC_la_LIBADD) $(LIBS) + +mostlyclean-compile: + -rm -f *.$(OBJEXT) + +distclean-compile: + -rm -f *.tab.c + +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/I810XvMC.Plo@am__quote@ + +.c.o: +@am__fastdepCC_TRUE@ if $(COMPILE) -MT $@ -MD -MP -MF "$(DEPDIR)/$*.Tpo" -c -o $@ $<; \ +@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/$*.Tpo" "$(DEPDIR)/$*.Po"; else rm -f "$(DEPDIR)/$*.Tpo"; exit 1; fi +@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(COMPILE) -c $< + +.c.obj: +@am__fastdepCC_TRUE@ if $(COMPILE) -MT $@ -MD -MP -MF "$(DEPDIR)/$*.Tpo" -c -o $@ `$(CYGPATH_W) '$<'`; \ +@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/$*.Tpo" "$(DEPDIR)/$*.Po"; else rm -f "$(DEPDIR)/$*.Tpo"; exit 1; fi +@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(COMPILE) -c `$(CYGPATH_W) '$<'` + +.c.lo: +@am__fastdepCC_TRUE@ if $(LTCOMPILE) -MT $@ -MD -MP -MF "$(DEPDIR)/$*.Tpo" -c -o $@ $<; \ +@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/$*.Tpo" "$(DEPDIR)/$*.Plo"; else rm -f "$(DEPDIR)/$*.Tpo"; exit 1; fi +@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=yes @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(LTCOMPILE) -c -o $@ $< + +mostlyclean-libtool: + -rm -f *.lo + +clean-libtool: + -rm -rf .libs _libs + +distclean-libtool: + -rm -f libtool +uninstall-info-am: + +ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES) + list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \ + unique=`for i in $$list; do \ + if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \ + done | \ + $(AWK) ' { files[$$0] = 1; } \ + END { for (i in files) print i; }'`; \ + mkid -fID $$unique +tags: TAGS + +TAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \ + $(TAGS_FILES) $(LISP) + tags=; \ + here=`pwd`; \ + list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \ + unique=`for i in $$list; do \ + if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \ + done | \ + $(AWK) ' { files[$$0] = 1; } \ + END { for (i in files) print i; }'`; \ + if test -z "$(ETAGS_ARGS)$$tags$$unique"; then :; else \ + test -n "$$unique" || unique=$$empty_fix; \ + $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \ + $$tags $$unique; \ + fi +ctags: CTAGS +CTAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \ + $(TAGS_FILES) $(LISP) + tags=; \ + here=`pwd`; \ + list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \ + unique=`for i in $$list; do \ + if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \ + done | \ + $(AWK) ' { files[$$0] = 1; } \ + END { for (i in files) print i; }'`; \ + test -z "$(CTAGS_ARGS)$$tags$$unique" \ + || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \ + $$tags $$unique + +GTAGS: + here=`$(am__cd) $(top_builddir) && pwd` \ + && cd $(top_srcdir) \ + && gtags -i $(GTAGS_ARGS) $$here + +distclean-tags: + -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags + +distdir: $(DISTFILES) + @srcdirstrip=`echo "$(srcdir)" | sed 's|.|.|g'`; \ + topsrcdirstrip=`echo "$(top_srcdir)" | sed 's|.|.|g'`; \ + list='$(DISTFILES)'; for file in $$list; do \ + case $$file in \ + $(srcdir)/*) file=`echo "$$file" | sed "s|^$$srcdirstrip/||"`;; \ + $(top_srcdir)/*) file=`echo "$$file" | sed "s|^$$topsrcdirstrip/|$(top_builddir)/|"`;; \ + esac; \ + if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \ + dir=`echo "$$file" | sed -e 's,/[^/]*$$,,'`; \ + if test "$$dir" != "$$file" && test "$$dir" != "."; then \ + dir="/$$dir"; \ + $(mkdir_p) "$(distdir)$$dir"; \ + else \ + dir=''; \ + fi; \ + if test -d $$d/$$file; then \ + if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \ + cp -pR $(srcdir)/$$file $(distdir)$$dir || exit 1; \ + fi; \ + cp -pR $$d/$$file $(distdir)$$dir || exit 1; \ + else \ + test -f $(distdir)/$$file \ + || cp -p $$d/$$file $(distdir)/$$file \ + || exit 1; \ + fi; \ + done +check-am: all-am +check: check-am +all-am: Makefile $(LTLIBRARIES) +installdirs: + for dir in "$(DESTDIR)$(libdir)"; do \ + test -z "$$dir" || $(mkdir_p) "$$dir"; \ + done +install: install-am +install-exec: install-exec-am +install-data: install-data-am +uninstall: uninstall-am + +install-am: all-am + @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am + +installcheck: installcheck-am +install-strip: + $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \ + install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \ + `test -z '$(STRIP)' || \ + echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install +mostlyclean-generic: + +clean-generic: + +distclean-generic: + -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES) + +maintainer-clean-generic: + @echo "This command is intended for maintainers to use" + @echo "it deletes files that may require special tools to rebuild." +clean: clean-am + +clean-am: clean-generic clean-libLTLIBRARIES clean-libtool \ + mostlyclean-am + +distclean: distclean-am + -rm -rf ./$(DEPDIR) + -rm -f Makefile +distclean-am: clean-am distclean-compile distclean-generic \ + distclean-libtool distclean-tags + +dvi: dvi-am + +dvi-am: + +html: html-am + +info: info-am + +info-am: + +install-data-am: + +install-exec-am: install-libLTLIBRARIES + +install-info: install-info-am + +install-man: + +installcheck-am: + +maintainer-clean: maintainer-clean-am + -rm -rf ./$(DEPDIR) + -rm -f Makefile +maintainer-clean-am: distclean-am maintainer-clean-generic + +mostlyclean: mostlyclean-am + +mostlyclean-am: mostlyclean-compile mostlyclean-generic \ + mostlyclean-libtool + +pdf: pdf-am + +pdf-am: + +ps: ps-am + +ps-am: + +uninstall-am: uninstall-info-am uninstall-libLTLIBRARIES + +.PHONY: CTAGS GTAGS all all-am check check-am clean clean-generic \ + clean-libLTLIBRARIES clean-libtool ctags distclean \ + distclean-compile distclean-generic distclean-libtool \ + distclean-tags distdir dvi dvi-am html html-am info info-am \ + install install-am install-data install-data-am install-exec \ + install-exec-am install-info install-info-am \ + install-libLTLIBRARIES install-man install-strip installcheck \ + installcheck-am installdirs maintainer-clean \ + maintainer-clean-generic mostlyclean mostlyclean-compile \ + mostlyclean-generic mostlyclean-libtool pdf pdf-am ps ps-am \ + tags uninstall uninstall-am uninstall-info-am \ + uninstall-libLTLIBRARIES + +# Tell versions [3.59,3.63) of GNU make to not export all variables. +# Otherwise a system limit (for SysV at least) may be exceeded. +.NOEXPORT: diff --git a/driver/xf86-video-intel/src/legacy/legacy.h b/driver/xf86-video-intel/src/legacy/legacy.h new file mode 100644 index 000000000..7bdd1729d --- /dev/null +++ b/driver/xf86-video-intel/src/legacy/legacy.h @@ -0,0 +1,3 @@ +/* The old i810 (only) driver. */ +const OptionInfoRec *lg_i810_available_options(int chipid, int busid); +void lg_i810_init(ScrnInfoPtr scrn); diff --git a/driver/xf86-video-intel/src/offset b/driver/xf86-video-intel/src/offset new file mode 100644 index 000000000..61f3ac1a8 --- /dev/null +++ b/driver/xf86-video-intel/src/offset @@ -0,0 +1,5 @@ +intel_memory.c: init.gtt_start = intel->memory_manager->offset; +intel_memory.c: init.gtt_end = intel->memory_manager->offset + +intel_memory.c: intel->memory_manager->size; +intel_memory.c: prefix, intel->memory_manager->offset); +intel_memory.c: prefix, intel->memory_manager->end); diff --git a/driver/xf86-video-intel/src/reg_dumper/Makefile.in b/driver/xf86-video-intel/src/reg_dumper/Makefile.in index ca905c3d0..e2b09a1d2 100644 --- a/driver/xf86-video-intel/src/reg_dumper/Makefile.in +++ b/driver/xf86-video-intel/src/reg_dumper/Makefile.in @@ -98,10 +98,6 @@ AUTOCONF = @AUTOCONF@ AUTOHEADER = @AUTOHEADER@ AUTOMAKE = @AUTOMAKE@ AWK = @AWK@ -BUILD_LINUXDOC_FALSE = @BUILD_LINUXDOC_FALSE@ -BUILD_LINUXDOC_TRUE = @BUILD_LINUXDOC_TRUE@ -BUILD_PDFDOC_FALSE = @BUILD_PDFDOC_FALSE@ -BUILD_PDFDOC_TRUE = @BUILD_PDFDOC_TRUE@ CC = @CC@ CCDEPMODE = @CCDEPMODE@ CFLAGS = @CFLAGS@ @@ -141,8 +137,6 @@ GEN4ASM_LIBS = @GEN4ASM_LIBS@ GREP = @GREP@ HAVE_GEN4ASM_FALSE = @HAVE_GEN4ASM_FALSE@ HAVE_GEN4ASM_TRUE = @HAVE_GEN4ASM_TRUE@ -HAVE_XEXTPROTO_71_FALSE = @HAVE_XEXTPROTO_71_FALSE@ -HAVE_XEXTPROTO_71_TRUE = @HAVE_XEXTPROTO_71_TRUE@ INSTALL_CMD = @INSTALL_CMD@ INSTALL_DATA = @INSTALL_DATA@ INSTALL_PROGRAM = @INSTALL_PROGRAM@ @@ -156,17 +150,13 @@ LIBS = @LIBS@ LIBTOOL = @LIBTOOL@ LIB_MAN_DIR = @LIB_MAN_DIR@ LIB_MAN_SUFFIX = @LIB_MAN_SUFFIX@ -LINUXDOC = @LINUXDOC@ LN_S = @LN_S@ LTLIBOBJS = @LTLIBOBJS@ MAINT = @MAINT@ MAINTAINER_MODE_FALSE = @MAINTAINER_MODE_FALSE@ MAINTAINER_MODE_TRUE = @MAINTAINER_MODE_TRUE@ MAKEINFO = @MAKEINFO@ -MAKE_HTML = @MAKE_HTML@ -MAKE_PDF = @MAKE_PDF@ -MAKE_PS = @MAKE_PS@ -MAKE_TEXT = @MAKE_TEXT@ +MAN_SUBSTS = @MAN_SUBSTS@ MISC_MAN_DIR = @MISC_MAN_DIR@ MISC_MAN_SUFFIX = @MISC_MAN_SUFFIX@ NMEDIT = @NMEDIT@ @@ -181,19 +171,15 @@ PATH_SEPARATOR = @PATH_SEPARATOR@ PCIACCESS_CFLAGS = @PCIACCESS_CFLAGS@ PCIACCESS_LIBS = @PCIACCESS_LIBS@ PKG_CONFIG = @PKG_CONFIG@ -PS2PDF = @PS2PDF@ RANLIB = @RANLIB@ SED = @SED@ SET_MAKE = @SET_MAKE@ SHELL = @SHELL@ STRIP = @STRIP@ VERSION = @VERSION@ -VIDEO_DEBUG_FALSE = @VIDEO_DEBUG_FALSE@ -VIDEO_DEBUG_TRUE = @VIDEO_DEBUG_TRUE@ -XEXT_CFLAGS = @XEXT_CFLAGS@ -XEXT_LIBS = @XEXT_LIBS@ XORG_CFLAGS = @XORG_CFLAGS@ XORG_LIBS = @XORG_LIBS@ +XORG_MAN_PAGE = @XORG_MAN_PAGE@ XVMCLIB_CFLAGS = @XVMCLIB_CFLAGS@ XVMCLIB_LIBS = @XVMCLIB_LIBS@ XVMC_FALSE = @XVMC_FALSE@ diff --git a/driver/xf86-video-intel/src/reg_dumper/README.OpenBSD b/driver/xf86-video-intel/src/reg_dumper/README.OpenBSD deleted file mode 100644 index b3f6606fa..000000000 --- a/driver/xf86-video-intel/src/reg_dumper/README.OpenBSD +++ /dev/null @@ -1,5 +0,0 @@ -To use the reg dumper program on a running X server you need : - -- to build a kernel with 'options INSECURE' and reboot in it -- to set 'securelevel=-1' in /etc/rc.securelevel -- to run intel_reg_dumper as root. diff --git a/driver/xf86-video-intel/src/render_program/Makefile.am b/driver/xf86-video-intel/src/render_program/Makefile.am index c9a0bfcc0..c70b1f7d5 100644 --- a/driver/xf86-video-intel/src/render_program/Makefile.am +++ b/driver/xf86-video-intel/src/render_program/Makefile.am @@ -20,7 +20,9 @@ INTEL_G4A = \ INTEL_G4I = \ exa_wm.g4i \ exa_wm_affine.g4i \ - exa_wm_projective.g4i + exa_wm_projective.g4i \ + exa_wm_sample_planar.g4i \ + exa_wm_src_sample_argb.g4i INTEL_G4B = \ exa_sf.g4b \ @@ -61,22 +63,99 @@ INTEL_G4B_GEN5 = \ exa_wm_yuv_rgb.g4b.gen5 \ exa_wm_xy.g4b.gen5 +INTEL_G6I = \ + exa_wm_affine.g6i \ + exa_wm_write.g6i + +INTEL_G6A = \ + exa_wm_src_affine.g6a \ + exa_wm_src_projective.g6a \ + exa_wm_src_sample_argb.g6a \ + exa_wm_src_sample_planar.g6a \ + exa_wm_src_sample_a.g6a \ + exa_wm_mask_affine.g6a \ + exa_wm_mask_projective.g6a \ + exa_wm_mask_sample_argb.g6a \ + exa_wm_mask_sample_a.g6a \ + exa_wm_ca.g6a \ + exa_wm_ca_srcalpha.g6a \ + exa_wm_noca.g6a \ + exa_wm_write.g6a \ + exa_wm_yuv_rgb.g6a + +INTEL_G6B = \ + exa_wm_src_affine.g6b \ + exa_wm_src_projective.g6b \ + exa_wm_src_sample_argb.g6b \ + exa_wm_src_sample_planar.g6b \ + exa_wm_src_sample_a.g6b \ + exa_wm_mask_affine.g6b \ + exa_wm_mask_projective.g6b \ + exa_wm_mask_sample_argb.g6b \ + exa_wm_mask_sample_a.g6b \ + exa_wm_ca.g6b \ + exa_wm_ca_srcalpha.g6b \ + exa_wm_noca.g6b \ + exa_wm_write.g6b \ + exa_wm_yuv_rgb.g6b + +INTEL_G7A = \ + exa_wm_mask_affine.g7a \ + exa_wm_mask_projective.g7a \ + exa_wm_mask_sample_a.g7a \ + exa_wm_mask_sample_argb.g7a \ + exa_wm_src_affine.g7a \ + exa_wm_src_projective.g7a \ + exa_wm_src_sample_a.g7a \ + exa_wm_src_sample_argb.g7a \ + exa_wm_src_sample_planar.g7a \ + exa_wm_write.g7a \ + exa_wm_yuv_rgb.g7a + +INTEL_G7B = \ + exa_wm_mask_affine.g7b \ + exa_wm_mask_projective.g7b \ + exa_wm_mask_sample_a.g7b \ + exa_wm_mask_sample_argb.g7b \ + exa_wm_src_affine.g7b \ + exa_wm_src_projective.g7b \ + exa_wm_src_sample_a.g7b \ + exa_wm_src_sample_argb.g7b \ + exa_wm_src_sample_planar.g7b \ + exa_wm_write.g7b \ + exa_wm_yuv_rgb.g7b + EXTRA_DIST = \ $(INTEL_G4A) \ $(INTEL_G4I) \ $(INTEL_G4B) \ - $(INTEL_G4B_GEN5) + $(INTEL_G4B_GEN5)\ + $(INTEL_G6A) \ + $(INTEL_G6B) \ + $(INTEL_G6I) \ + $(INTEL_G7A) \ + $(INTEL_G7B) if HAVE_GEN4ASM -SUFFIXES = .g4a .g4b +SUFFIXES = .g4a .g4b .g6a .g6b .g7a .g7b .g4a.g4b: m4 -I$(srcdir) -s $< > $*.g4m && intel-gen4asm -o $@ $*.g4m && intel-gen4asm -g 5 -o $@.gen5 $*.g4m && rm $*.g4m +.g6a.g6b: + m4 -I$(srcdir) -s $< > $*.g6m && intel-gen4asm -g 6 -o $@ $*.g6m && rm $*.g6m + +.g7a.g7b: + m4 -I$(srcdir) -s $< > $*.g7m && intel-gen4asm -g 7 -o $@ $*.g7m && rm $*.g7m + $(INTEL_G4B): $(INTEL_G4I) +$(INTEL_G6B): $(INTEL_G4I) $(INTEL_G6I) +$(INTEL_G7B): $(INTEL_G4I) $(INTEL_G6I) -BUILT_SOURCES= $(INTEL_G4B) +BUILT_SOURCES= $(INTEL_G4B) $(INTEL_G6B) $(INTEL_G7B) clean-local: -rm -f $(INTEL_G4B) $(INTEL_G4B_GEN5) + -rm -f $(INTEL_G6B) + -rm -f $(INTEL_G7B) endif diff --git a/driver/xf86-video-intel/src/render_program/Makefile.in b/driver/xf86-video-intel/src/render_program/Makefile.in index 3519c545b..80d6ea7d3 100644 --- a/driver/xf86-video-intel/src/render_program/Makefile.in +++ b/driver/xf86-video-intel/src/render_program/Makefile.in @@ -61,10 +61,6 @@ AUTOCONF = @AUTOCONF@ AUTOHEADER = @AUTOHEADER@ AUTOMAKE = @AUTOMAKE@ AWK = @AWK@ -BUILD_LINUXDOC_FALSE = @BUILD_LINUXDOC_FALSE@ -BUILD_LINUXDOC_TRUE = @BUILD_LINUXDOC_TRUE@ -BUILD_PDFDOC_FALSE = @BUILD_PDFDOC_FALSE@ -BUILD_PDFDOC_TRUE = @BUILD_PDFDOC_TRUE@ CC = @CC@ CCDEPMODE = @CCDEPMODE@ CFLAGS = @CFLAGS@ @@ -104,8 +100,6 @@ GEN4ASM_LIBS = @GEN4ASM_LIBS@ GREP = @GREP@ HAVE_GEN4ASM_FALSE = @HAVE_GEN4ASM_FALSE@ HAVE_GEN4ASM_TRUE = @HAVE_GEN4ASM_TRUE@ -HAVE_XEXTPROTO_71_FALSE = @HAVE_XEXTPROTO_71_FALSE@ -HAVE_XEXTPROTO_71_TRUE = @HAVE_XEXTPROTO_71_TRUE@ INSTALL_CMD = @INSTALL_CMD@ INSTALL_DATA = @INSTALL_DATA@ INSTALL_PROGRAM = @INSTALL_PROGRAM@ @@ -119,17 +113,13 @@ LIBS = @LIBS@ LIBTOOL = @LIBTOOL@ LIB_MAN_DIR = @LIB_MAN_DIR@ LIB_MAN_SUFFIX = @LIB_MAN_SUFFIX@ -LINUXDOC = @LINUXDOC@ LN_S = @LN_S@ LTLIBOBJS = @LTLIBOBJS@ MAINT = @MAINT@ MAINTAINER_MODE_FALSE = @MAINTAINER_MODE_FALSE@ MAINTAINER_MODE_TRUE = @MAINTAINER_MODE_TRUE@ MAKEINFO = @MAKEINFO@ -MAKE_HTML = @MAKE_HTML@ -MAKE_PDF = @MAKE_PDF@ -MAKE_PS = @MAKE_PS@ -MAKE_TEXT = @MAKE_TEXT@ +MAN_SUBSTS = @MAN_SUBSTS@ MISC_MAN_DIR = @MISC_MAN_DIR@ MISC_MAN_SUFFIX = @MISC_MAN_SUFFIX@ NMEDIT = @NMEDIT@ @@ -144,19 +134,15 @@ PATH_SEPARATOR = @PATH_SEPARATOR@ PCIACCESS_CFLAGS = @PCIACCESS_CFLAGS@ PCIACCESS_LIBS = @PCIACCESS_LIBS@ PKG_CONFIG = @PKG_CONFIG@ -PS2PDF = @PS2PDF@ RANLIB = @RANLIB@ SED = @SED@ SET_MAKE = @SET_MAKE@ SHELL = @SHELL@ STRIP = @STRIP@ VERSION = @VERSION@ -VIDEO_DEBUG_FALSE = @VIDEO_DEBUG_FALSE@ -VIDEO_DEBUG_TRUE = @VIDEO_DEBUG_TRUE@ -XEXT_CFLAGS = @XEXT_CFLAGS@ -XEXT_LIBS = @XEXT_LIBS@ XORG_CFLAGS = @XORG_CFLAGS@ XORG_LIBS = @XORG_LIBS@ +XORG_MAN_PAGE = @XORG_MAN_PAGE@ XVMCLIB_CFLAGS = @XVMCLIB_CFLAGS@ XVMCLIB_LIBS = @XVMCLIB_LIBS@ XVMC_FALSE = @XVMC_FALSE@ diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_affine.g6i b/driver/xf86-video-intel/src/render_program/exa_wm_affine.g6i new file mode 100644 index 000000000..9ac21d5cd --- /dev/null +++ b/driver/xf86-video-intel/src/render_program/exa_wm_affine.g6i @@ -0,0 +1,35 @@ +/* + * Copyright © 2010-2011 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ + +/* + * Fragment to compute src u/v values + */ + +/* U */ +pln (8) ul<1>F a0_a_x bl { align1 }; /* pixel 0-7 */ +pln (8) uh<1>F a0_a_x bh { align1 }; /* pixel 8-15 */ + +/* V */ +pln (8) vl<1>F a0_a_y bl { align1 }; /* pixel 0-7 */ +pln (8) vh<1>F a0_a_y bh { align1 }; /* pixel 8-15 */ diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_ca.g6b b/driver/xf86-video-intel/src/render_program/exa_wm_ca.g6b new file mode 100644 index 000000000..521a5b64a --- /dev/null +++ b/driver/xf86-video-intel/src/render_program/exa_wm_ca.g6b @@ -0,0 +1,4 @@ + { 0x00800041, 0x21c077bd, 0x008d01c0, 0x008d02c0 }, + { 0x00800041, 0x220077bd, 0x008d0200, 0x008d0300 }, + { 0x00800041, 0x224077bd, 0x008d0240, 0x008d0340 }, + { 0x00800041, 0x228077bd, 0x008d0280, 0x008d0380 }, diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_ca_srcalpha.g6b b/driver/xf86-video-intel/src/render_program/exa_wm_ca_srcalpha.g6b new file mode 100644 index 000000000..d5ab7e42a --- /dev/null +++ b/driver/xf86-video-intel/src/render_program/exa_wm_ca_srcalpha.g6b @@ -0,0 +1,4 @@ + { 0x00800041, 0x21c077bd, 0x008d02c0, 0x008d0280 }, + { 0x00800041, 0x220077bd, 0x008d0300, 0x008d0280 }, + { 0x00800041, 0x224077bd, 0x008d0340, 0x008d0280 }, + { 0x00800041, 0x228077bd, 0x008d0380, 0x008d0280 }, diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_mask_affine.g6a b/driver/xf86-video-intel/src/render_program/exa_wm_mask_affine.g6a new file mode 100644 index 000000000..04ad2a237 --- /dev/null +++ b/driver/xf86-video-intel/src/render_program/exa_wm_mask_affine.g6a @@ -0,0 +1,41 @@ +/* + * Copyright © 2010 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ + +/* + * Fragment to compute src u/v values + */ +include(`exa_wm.g4i') + +define(`ul', `mask_u') +define(`uh', `m9') +define(`vl', `mask_v') +define(`vh', `m11') + +define(`bl', `g2.0<8,8,1>F') +define(`bh', `g4.0<8,8,1>F') + +define(`a0_a_x',`g8.0<0,1,0>F') +define(`a0_a_y',`g8.16<0,1,0>F') + +include(`exa_wm_affine.g6i') diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_mask_affine.g6b b/driver/xf86-video-intel/src/render_program/exa_wm_mask_affine.g6b new file mode 100644 index 000000000..e4bef29e9 --- /dev/null +++ b/driver/xf86-video-intel/src/render_program/exa_wm_mask_affine.g6b @@ -0,0 +1,4 @@ + { 0x0060005a, 0x210077be, 0x00000100, 0x008d0040 }, + { 0x0060005a, 0x212077be, 0x00000100, 0x008d0080 }, + { 0x0060005a, 0x214077be, 0x00000110, 0x008d0040 }, + { 0x0060005a, 0x216077be, 0x00000110, 0x008d0080 }, diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_mask_affine.g7a b/driver/xf86-video-intel/src/render_program/exa_wm_mask_affine.g7a new file mode 100644 index 000000000..42770802b --- /dev/null +++ b/driver/xf86-video-intel/src/render_program/exa_wm_mask_affine.g7a @@ -0,0 +1,41 @@ +/* + * Copyright © 2010 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ + +/* + * Fragment to compute src u/v values + */ +include(`exa_wm.g4i') + +define(`ul', `g72') +define(`uh', `g73') +define(`vl', `g74') +define(`vh', `g75') + +define(`bl', `g2.0<8,8,1>F') +define(`bh', `g4.0<8,8,1>F') + +define(`a0_a_x',`g8.0<0,1,0>F') +define(`a0_a_y',`g8.16<0,1,0>F') + +include(`exa_wm_affine.g6i') diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_mask_affine.g7b b/driver/xf86-video-intel/src/render_program/exa_wm_mask_affine.g7b new file mode 100644 index 000000000..8d72599d8 --- /dev/null +++ b/driver/xf86-video-intel/src/render_program/exa_wm_mask_affine.g7b @@ -0,0 +1,4 @@ + { 0x0060005a, 0x290077bd, 0x00000100, 0x008d0040 }, + { 0x0060005a, 0x292077bd, 0x00000100, 0x008d0080 }, + { 0x0060005a, 0x294077bd, 0x00000110, 0x008d0040 }, + { 0x0060005a, 0x296077bd, 0x00000110, 0x008d0080 }, diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_mask_projective.g6a b/driver/xf86-video-intel/src/render_program/exa_wm_mask_projective.g6a new file mode 100644 index 000000000..378c27746 --- /dev/null +++ b/driver/xf86-video-intel/src/render_program/exa_wm_mask_projective.g6a @@ -0,0 +1,63 @@ +/* + * Copyright © 2010 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ + +/* + * Fragment to compute src u/v values + */ +include(`exa_wm.g4i') + +define(`u', `mask_u') +define(`ul', `mask_u') +define(`uh', `m9') +define(`v', `mask_v') +define(`vl', `mask_v') +define(`vh', `m11') +define(`w', `mask_w') +define(`wl', `mask_w_0') +define(`wh', `mask_w_1') + +define(`bl', `g2.0<8,8,1>F') +define(`bh', `g4.0<8,8,1>F') + +define(`a0_a_x',`g8.0<0,1,0>F') +define(`a0_a_y',`g8.16<0,1,0>F') +define(`a0_a_z',`g9.0<0,1,0>F') + +/* W */ +pln (8) temp_x_0<1>F a0_a_z bl { align1 }; /* pixel 0-7 */ +pln (8) temp_x_1<1>F a0_a_z bh { align1 }; /* pixel 8-15 */ +math (8) wl<1>F temp_x_0<8,8,1>F null inv { align1 }; +math (8) wh<1>F temp_x_1<8,8,1>F null inv { align1 }; + +/* U */ +pln (8) temp_x_0<1>F a0_a_x bl { align1 }; /* pixel 0-7 */ +pln (8) temp_x_1<1>F a0_a_x bh { align1 }; /* pixel 8-15 */ +mul (8) ul<1>F temp_x_0<8,8,1>F wl<8,8,1>F { align1 }; +mul (8) uh<1>F temp_x_1<8,8,1>F wh<8,8,1>F { align1 }; + +/* V */ +pln (8) temp_x_0<1>F a0_a_y bl { align1 }; /* pixel 0-7 */ +pln (8) temp_x_1<1>F a0_a_y bh { align1 }; /* pixel 8-15 */ +mul (8) vl<1>F temp_x_0<8,8,1>F wl<8,8,1>F { align1 }; +mul (8) vh<1>F temp_x_1<8,8,1>F wh<8,8,1>F { align1 }; diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_mask_projective.g6b b/driver/xf86-video-intel/src/render_program/exa_wm_mask_projective.g6b new file mode 100644 index 000000000..dddcb4bdc --- /dev/null +++ b/driver/xf86-video-intel/src/render_program/exa_wm_mask_projective.g6b @@ -0,0 +1,12 @@ + { 0x0060005a, 0x23c077bd, 0x00000120, 0x008d0040 }, + { 0x0060005a, 0x23e077bd, 0x00000120, 0x008d0080 }, + { 0x01600038, 0x218003bd, 0x008d03c0, 0x00000000 }, + { 0x01600038, 0x21a003bd, 0x008d03e0, 0x00000000 }, + { 0x0060005a, 0x23c077bd, 0x00000100, 0x008d0040 }, + { 0x0060005a, 0x23e077bd, 0x00000100, 0x008d0080 }, + { 0x00600041, 0x210077be, 0x008d03c0, 0x008d0180 }, + { 0x00600041, 0x212077be, 0x008d03e0, 0x008d01a0 }, + { 0x0060005a, 0x23c077bd, 0x00000110, 0x008d0040 }, + { 0x0060005a, 0x23e077bd, 0x00000110, 0x008d0080 }, + { 0x00600041, 0x214077be, 0x008d03c0, 0x008d0180 }, + { 0x00600041, 0x216077be, 0x008d03e0, 0x008d01a0 }, diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_mask_projective.g7a b/driver/xf86-video-intel/src/render_program/exa_wm_mask_projective.g7a new file mode 100644 index 000000000..ba4158f88 --- /dev/null +++ b/driver/xf86-video-intel/src/render_program/exa_wm_mask_projective.g7a @@ -0,0 +1,63 @@ +/* + * Copyright © 2010 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ + +/* + * Fragment to compute src u/v values + */ +include(`exa_wm.g4i') + +define(`u', `g72') +define(`ul', `g72') +define(`uh', `g73') +define(`v', `g74') +define(`vl', `g74') +define(`vh', `g75') +define(`w', `mask_w') +define(`wl', `mask_w_0') +define(`wh', `mask_w_1') + +define(`bl', `g2.0<8,8,1>F') +define(`bh', `g4.0<8,8,1>F') + +define(`a0_a_x',`g8.0<0,1,0>F') +define(`a0_a_y',`g8.16<0,1,0>F') +define(`a0_a_z',`g9.0<0,1,0>F') + +/* W */ +pln (8) temp_x_0<1>F a0_a_z bl { align1 }; /* pixel 0-7 */ +pln (8) temp_x_1<1>F a0_a_z bh { align1 }; /* pixel 8-15 */ +math (8) wl<1>F temp_x_0<8,8,1>F null inv { align1 }; +math (8) wh<1>F temp_x_1<8,8,1>F null inv { align1 }; + +/* U */ +pln (8) temp_x_0<1>F a0_a_x bl { align1 }; /* pixel 0-7 */ +pln (8) temp_x_1<1>F a0_a_x bh { align1 }; /* pixel 8-15 */ +mul (8) ul<1>F temp_x_0<8,8,1>F wl<8,8,1>F { align1 }; +mul (8) uh<1>F temp_x_1<8,8,1>F wh<8,8,1>F { align1 }; + +/* V */ +pln (8) temp_x_0<1>F a0_a_y bl { align1 }; /* pixel 0-7 */ +pln (8) temp_x_1<1>F a0_a_y bh { align1 }; /* pixel 8-15 */ +mul (8) vl<1>F temp_x_0<8,8,1>F wl<8,8,1>F { align1 }; +mul (8) vh<1>F temp_x_1<8,8,1>F wh<8,8,1>F { align1 }; diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_mask_projective.g7b b/driver/xf86-video-intel/src/render_program/exa_wm_mask_projective.g7b new file mode 100644 index 000000000..a2e9267bf --- /dev/null +++ b/driver/xf86-video-intel/src/render_program/exa_wm_mask_projective.g7b @@ -0,0 +1,12 @@ + { 0x0060005a, 0x23c077bd, 0x00000120, 0x008d0040 }, + { 0x0060005a, 0x23e077bd, 0x00000120, 0x008d0080 }, + { 0x01600038, 0x218003bd, 0x008d03c0, 0x00000000 }, + { 0x01600038, 0x21a003bd, 0x008d03e0, 0x00000000 }, + { 0x0060005a, 0x23c077bd, 0x00000100, 0x008d0040 }, + { 0x0060005a, 0x23e077bd, 0x00000100, 0x008d0080 }, + { 0x00600041, 0x290077bd, 0x008d03c0, 0x008d0180 }, + { 0x00600041, 0x292077bd, 0x008d03e0, 0x008d01a0 }, + { 0x0060005a, 0x23c077bd, 0x00000110, 0x008d0040 }, + { 0x0060005a, 0x23e077bd, 0x00000110, 0x008d0080 }, + { 0x00600041, 0x294077bd, 0x008d03c0, 0x008d0180 }, + { 0x00600041, 0x296077bd, 0x008d03e0, 0x008d01a0 }, diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_mask_sample_a.g4a b/driver/xf86-video-intel/src/render_program/exa_wm_mask_sample_a.g4a index bbb19d7a7..b1c75af1e 100644 --- a/driver/xf86-video-intel/src/render_program/exa_wm_mask_sample_a.g4a +++ b/driver/xf86-video-intel/src/render_program/exa_wm_mask_sample_a.g4a @@ -36,12 +36,13 @@ include(`exa_wm.g4i') /* load only alpha */ mov (1) g0.8<1>UD 0x00007000UD { align1 mask_disable }; +mov (8) mask_msg<1>UD g0<8,8,1>UD { align1 }; /* copy to msg start reg*/ /* mask_msg will be copied with g0, as it contains send desc */ /* emit sampler 'send' cmd */ send (16) mask_msg_ind /* msg reg index */ mask_sample_a_01<1>UW /* readback */ - g0<8,8,1>UW /* copy to msg start reg*/ + null sampler (2,1,F) /* sampler message description, (binding_table,sampler_index,datatype) /* here(src->dst) we should use src_sampler and src_surface */ mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */ diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_mask_sample_a.g4b b/driver/xf86-video-intel/src/render_program/exa_wm_mask_sample_a.g4b index 018bd36a9..7db47ca45 100644 --- a/driver/xf86-video-intel/src/render_program/exa_wm_mask_sample_a.g4b +++ b/driver/xf86-video-intel/src/render_program/exa_wm_mask_sample_a.g4b @@ -1,2 +1,3 @@ { 0x00000201, 0x20080061, 0x00000000, 0x00007000 }, - { 0x07800031, 0x23801d29, 0x008d0000, 0x02520102 }, + { 0x00600001, 0x20e00022, 0x008d0000, 0x00000000 }, + { 0x07800031, 0x23801c09, 0x00000000, 0x02520102 }, diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_mask_sample_a.g4b.gen5 b/driver/xf86-video-intel/src/render_program/exa_wm_mask_sample_a.g4b.gen5 index d9740acb5..472c2bbe8 100644 --- a/driver/xf86-video-intel/src/render_program/exa_wm_mask_sample_a.g4b.gen5 +++ b/driver/xf86-video-intel/src/render_program/exa_wm_mask_sample_a.g4b.gen5 @@ -1,2 +1,3 @@ { 0x00000201, 0x20080061, 0x00000000, 0x00007000 }, - { 0x07800031, 0x23801d29, 0x208d0000, 0x0a2a0102 }, + { 0x00600001, 0x20e00022, 0x008d0000, 0x00000000 }, + { 0x07800031, 0x23801c09, 0x20000000, 0x0a2a0102 }, diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_mask_sample_a.g6b b/driver/xf86-video-intel/src/render_program/exa_wm_mask_sample_a.g6b new file mode 100644 index 000000000..6d1eae937 --- /dev/null +++ b/driver/xf86-video-intel/src/render_program/exa_wm_mask_sample_a.g6b @@ -0,0 +1,3 @@ + { 0x00000201, 0x20080061, 0x00000000, 0x00007000 }, + { 0x00600001, 0x20e00022, 0x008d0000, 0x00000000 }, + { 0x02800031, 0x23801cc9, 0x000000e0, 0x0a2a0102 }, diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_mask_sample_a.g7a b/driver/xf86-video-intel/src/render_program/exa_wm_mask_sample_a.g7a new file mode 100644 index 000000000..a0d38e1ce --- /dev/null +++ b/driver/xf86-video-intel/src/render_program/exa_wm_mask_sample_a.g7a @@ -0,0 +1,49 @@ +/* + * Copyright © 2006 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Wang Zhenyu <zhenyu.z.wang@intel.com> + * Keith Packard <keithp@keithp.com> + */ + +/* Sample the mask surface */ + +include(`exa_wm.g4i') + +/* prepare sampler read back gX register, which would be written back to output */ + +/* use simd16 sampler, param 0 is u, param 1 is v. */ +/* 'payload' loading, assuming tex coord start from g4 */ + +/* load only alpha */ +mov (1) g0.8<1>UD 0x00007000UD { align1 mask_disable }; +mov (8) g71<1>UD g0<8,8,1>UD { align1 }; /* copy to msg start reg*/ + +/* g71 will be copied with g0, as it contains send desc */ +/* emit sampler 'send' cmd */ +send (16) 71 /* msg reg index */ + mask_sample_a_01<1>UW /* readback */ + null + sampler (2,1,F) /* sampler message description, (binding_table,sampler_index,datatype) + /* here(src->dst) we should use src_sampler and src_surface */ + mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */ + diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_mask_sample_a.g7b b/driver/xf86-video-intel/src/render_program/exa_wm_mask_sample_a.g7b new file mode 100644 index 000000000..fa36a59e7 --- /dev/null +++ b/driver/xf86-video-intel/src/render_program/exa_wm_mask_sample_a.g7b @@ -0,0 +1,3 @@ + { 0x00000201, 0x20080061, 0x00000000, 0x00007000 }, + { 0x00600001, 0x28e00021, 0x008d0000, 0x00000000 }, + { 0x02800031, 0x23801ca9, 0x000008e0, 0x0a2c0102 }, diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_mask_sample_argb.g4a b/driver/xf86-video-intel/src/render_program/exa_wm_mask_sample_argb.g4a index def4cfe44..78bfc92a1 100644 --- a/driver/xf86-video-intel/src/render_program/exa_wm_mask_sample_argb.g4a +++ b/driver/xf86-video-intel/src/render_program/exa_wm_mask_sample_argb.g4a @@ -36,12 +36,13 @@ include(`exa_wm.g4i') /* load argb */ mov (1) g0.8<1>UD 0x00000000UD { align1 mask_disable }; +mov (8) mask_msg<1>UD g0<8,8,1>UD { align1 }; /* copy to msg start reg*/ /* mask_msg will be copied with g0, as it contains send desc */ /* emit sampler 'send' cmd */ send (16) mask_msg_ind /* msg reg index */ mask_sample_base<1>UW /* readback */ - g0<8,8,1>UW /* copy to msg start reg*/ + null sampler (2,1,F) /* sampler message description, (binding_table,sampler_index,datatype) /* here(src->dst) we should use src_sampler and src_surface */ mlen 5 rlen 8 { align1 }; /* required message len 5, readback len 8 */ diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_mask_sample_argb.g4b b/driver/xf86-video-intel/src/render_program/exa_wm_mask_sample_argb.g4b index b159cbaa8..9026ee2a2 100644 --- a/driver/xf86-video-intel/src/render_program/exa_wm_mask_sample_argb.g4b +++ b/driver/xf86-video-intel/src/render_program/exa_wm_mask_sample_argb.g4b @@ -1,2 +1,3 @@ { 0x00000201, 0x20080061, 0x00000000, 0x00000000 }, - { 0x07800031, 0x22c01d29, 0x008d0000, 0x02580102 }, + { 0x00600001, 0x20e00022, 0x008d0000, 0x00000000 }, + { 0x07800031, 0x22c01c09, 0x00000000, 0x02580102 }, diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_mask_sample_argb.g4b.gen5 b/driver/xf86-video-intel/src/render_program/exa_wm_mask_sample_argb.g4b.gen5 index f0a6dddf8..cb112d56f 100644 --- a/driver/xf86-video-intel/src/render_program/exa_wm_mask_sample_argb.g4b.gen5 +++ b/driver/xf86-video-intel/src/render_program/exa_wm_mask_sample_argb.g4b.gen5 @@ -1,2 +1,3 @@ { 0x00000201, 0x20080061, 0x00000000, 0x00000000 }, - { 0x07800031, 0x22c01d29, 0x208d0000, 0x0a8a0102 }, + { 0x00600001, 0x20e00022, 0x008d0000, 0x00000000 }, + { 0x07800031, 0x22c01c09, 0x20000000, 0x0a8a0102 }, diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_mask_sample_argb.g6b b/driver/xf86-video-intel/src/render_program/exa_wm_mask_sample_argb.g6b new file mode 100644 index 000000000..e5630bd18 --- /dev/null +++ b/driver/xf86-video-intel/src/render_program/exa_wm_mask_sample_argb.g6b @@ -0,0 +1,3 @@ + { 0x00000201, 0x20080061, 0x00000000, 0x00000000 }, + { 0x00600001, 0x20e00022, 0x008d0000, 0x00000000 }, + { 0x02800031, 0x22c01cc9, 0x000000e0, 0x0a8a0102 }, diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_mask_sample_argb.g7a b/driver/xf86-video-intel/src/render_program/exa_wm_mask_sample_argb.g7a new file mode 100644 index 000000000..984b62229 --- /dev/null +++ b/driver/xf86-video-intel/src/render_program/exa_wm_mask_sample_argb.g7a @@ -0,0 +1,49 @@ +/* + * Copyright © 2006 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Wang Zhenyu <zhenyu.z.wang@intel.com> + * Keith Packard <keithp@keithp.com> + */ + +/* Sample the mask surface */ + +include(`exa_wm.g4i') + +/* prepare sampler read back gX register, which would be written back to output */ + +/* use simd16 sampler, param 0 is u, param 1 is v. */ +/* 'payload' loading, assuming tex coord start from g4 */ + +/* load argb */ +mov (1) g0.8<1>UD 0x00000000UD { align1 mask_disable }; +mov (8) g71<1>UD g0<8,8,1>UD { align1 }; /* copy to msg start reg*/ + +/* g71 will be copied with g0, as it contains send desc */ +/* emit sampler 'send' cmd */ +send (16) 71 /* msg reg index */ + mask_sample_base<1>UW /* readback */ + null + sampler (2,1,F) /* sampler message description, (binding_table,sampler_index,datatype) + /* here(src->dst) we should use src_sampler and src_surface */ + mlen 5 rlen 8 { align1 }; /* required message len 5, readback len 8 */ + diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_mask_sample_argb.g7b b/driver/xf86-video-intel/src/render_program/exa_wm_mask_sample_argb.g7b new file mode 100644 index 000000000..01edf7d58 --- /dev/null +++ b/driver/xf86-video-intel/src/render_program/exa_wm_mask_sample_argb.g7b @@ -0,0 +1,3 @@ + { 0x00000201, 0x20080061, 0x00000000, 0x00000000 }, + { 0x00600001, 0x28e00021, 0x008d0000, 0x00000000 }, + { 0x02800031, 0x22c01ca9, 0x000008e0, 0x0a8c0102 }, diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_noca.g6b b/driver/xf86-video-intel/src/render_program/exa_wm_noca.g6b new file mode 100644 index 000000000..e77ea2dd2 --- /dev/null +++ b/driver/xf86-video-intel/src/render_program/exa_wm_noca.g6b @@ -0,0 +1,4 @@ + { 0x00800041, 0x21c077bd, 0x008d01c0, 0x008d0380 }, + { 0x00800041, 0x220077bd, 0x008d0200, 0x008d0380 }, + { 0x00800041, 0x224077bd, 0x008d0240, 0x008d0380 }, + { 0x00800041, 0x228077bd, 0x008d0280, 0x008d0380 }, diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_sample_planar.g4i b/driver/xf86-video-intel/src/render_program/exa_wm_sample_planar.g4i new file mode 100644 index 000000000..5452420a2 --- /dev/null +++ b/driver/xf86-video-intel/src/render_program/exa_wm_sample_planar.g4i @@ -0,0 +1,64 @@ +/* + * Copyright © 2006 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Wang Zhenyu <zhenyu.z.wang@intel.com> + * Keith Packard <keithp@keithp.com> + */ + +/* Sample the src surface in planar format */ + +/* prepare sampler read back gX register, which would be written back to output */ + +/* use simd16 sampler, param 0 is u, param 1 is v. */ +/* 'payload' loading, assuming tex coord start from g4 */ + +/* load r */ +mov (1) g0.8<1>UD 0x0000e000UD { align1 mask_disable }; + +/* src_msg will be copied with g0, as it contains send desc */ +/* emit sampler 'send' cmd */ + +/* sample Y */ +mov (8) src_msg<1>UD g0<8,8,1>UD { align1 }; /* copy to msg start reg*/ +send (16) src_msg_ind /* msg reg index */ + src_sample_g<1>UW /* readback */ + null + sampler (1,0,F) /* sampler message description, (binding_table,sampler_index,datatype) + /* here(src->dst) we should use src_sampler and src_surface */ + mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */ + +/* sample U (Cr) */ +send (16) src_msg_ind /* msg reg index */ + src_sample_r<1>UW /* readback */ + null + sampler (3,0,F) /* sampler message description, (binding_table,sampler_index,datatype) + /* here(src->dst) we should use src_sampler and src_surface */ + mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */ + +/* sample V (Cb) */ +send (16) src_msg_ind /* msg reg index */ + src_sample_b<1>UW /* readback */ + null + sampler (5,0,F) /* sampler message description, (binding_table,sampler_index,datatype) + /* here(src->dst) we should use src_sampler and src_surface */ + mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */ diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_src_affine.g6a b/driver/xf86-video-intel/src/render_program/exa_wm_src_affine.g6a new file mode 100644 index 000000000..38623bf4e --- /dev/null +++ b/driver/xf86-video-intel/src/render_program/exa_wm_src_affine.g6a @@ -0,0 +1,41 @@ +/* + * Copyright © 2010 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ + +/* + * Fragment to compute src u/v values + */ +include(`exa_wm.g4i') + +define(`ul', `src_u') +define(`uh', `m3') +define(`vl', `src_v') +define(`vh', `m5') + +define(`bl', `g2.0<8,8,1>F') +define(`bh', `g4.0<8,8,1>F') + +define(`a0_a_x',`g6.0<0,1,0>F') +define(`a0_a_y',`g6.16<0,1,0>F') + +include(`exa_wm_affine.g6i') diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_src_affine.g6b b/driver/xf86-video-intel/src/render_program/exa_wm_src_affine.g6b new file mode 100644 index 000000000..7035e6a5c --- /dev/null +++ b/driver/xf86-video-intel/src/render_program/exa_wm_src_affine.g6b @@ -0,0 +1,4 @@ + { 0x0060005a, 0x204077be, 0x000000c0, 0x008d0040 }, + { 0x0060005a, 0x206077be, 0x000000c0, 0x008d0080 }, + { 0x0060005a, 0x208077be, 0x000000d0, 0x008d0040 }, + { 0x0060005a, 0x20a077be, 0x000000d0, 0x008d0080 }, diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_src_affine.g7a b/driver/xf86-video-intel/src/render_program/exa_wm_src_affine.g7a new file mode 100644 index 000000000..cf24b2f12 --- /dev/null +++ b/driver/xf86-video-intel/src/render_program/exa_wm_src_affine.g7a @@ -0,0 +1,41 @@ +/* + * Copyright © 2010 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ + +/* + * Fragment to compute src u/v values + */ +include(`exa_wm.g4i') + +define(`ul', `g66') +define(`uh', `g67') +define(`vl', `g68') +define(`vh', `g69') + +define(`bl', `g2.0<8,8,1>F') +define(`bh', `g4.0<8,8,1>F') + +define(`a0_a_x',`g6.0<0,1,0>F') +define(`a0_a_y',`g6.16<0,1,0>F') + +include(`exa_wm_affine.g6i') diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_src_affine.g7b b/driver/xf86-video-intel/src/render_program/exa_wm_src_affine.g7b new file mode 100644 index 000000000..f545fba1e --- /dev/null +++ b/driver/xf86-video-intel/src/render_program/exa_wm_src_affine.g7b @@ -0,0 +1,4 @@ + { 0x0060005a, 0x284077bd, 0x000000c0, 0x008d0040 }, + { 0x0060005a, 0x286077bd, 0x000000c0, 0x008d0080 }, + { 0x0060005a, 0x288077bd, 0x000000d0, 0x008d0040 }, + { 0x0060005a, 0x28a077bd, 0x000000d0, 0x008d0080 }, diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_src_projective.g6a b/driver/xf86-video-intel/src/render_program/exa_wm_src_projective.g6a new file mode 100644 index 000000000..af08effaa --- /dev/null +++ b/driver/xf86-video-intel/src/render_program/exa_wm_src_projective.g6a @@ -0,0 +1,63 @@ +/* + * Copyright © 2010 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ + +/* + * Fragment to compute src u/v values + */ +include(`exa_wm.g4i') + +define(`u', `src_u') +define(`ul', `src_u') +define(`uh', `m3') +define(`v', `src_v') +define(`vl', `src_v') +define(`vh', `m5') +define(`w', `src_w') +define(`wl', `src_w_0') +define(`wh', `src_w_1') + +define(`bl', `g2.0<8,8,1>F') +define(`bh', `g4.0<8,8,1>F') + +define(`a0_a_x',`g6.0<0,1,0>F') +define(`a0_a_y',`g6.16<0,1,0>F') +define(`a0_a_z',`g7.0<0,1,0>F') + +/* W */ +pln (8) temp_x_0<1>F a0_a_z bl { align1 }; /* pixel 0-7 */ +pln (8) temp_x_1<1>F a0_a_z bh { align1 }; /* pixel 8-15 */ +math (8) wl<1>F temp_x_0<8,8,1>F null inv { align1 }; +math (8) wh<1>F temp_x_1<8,8,1>F null inv { align1 }; + +/* U */ +pln (8) temp_x_0<1>F a0_a_x bl { align1 }; /* pixel 0-7 */ +pln (8) temp_x_1<1>F a0_a_x bh { align1 }; /* pixel 8-15 */ +mul (8) ul<1>F temp_x_0<8,8,1>F wl<8,8,1>F { align1 }; +mul (8) uh<1>F temp_x_1<8,8,1>F wh<8,8,1>F { align1 }; + +/* V */ +pln (8) temp_x_0<1>F a0_a_y bl { align1 }; /* pixel 0-7 */ +pln (8) temp_x_1<1>F a0_a_y bh { align1 }; /* pixel 8-15 */ +mul (8) vl<1>F temp_x_0<8,8,1>F wl<8,8,1>F { align1 }; +mul (8) vh<1>F temp_x_1<8,8,1>F wh<8,8,1>F { align1 }; diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_src_projective.g6b b/driver/xf86-video-intel/src/render_program/exa_wm_src_projective.g6b new file mode 100644 index 000000000..8e39bffa8 --- /dev/null +++ b/driver/xf86-video-intel/src/render_program/exa_wm_src_projective.g6b @@ -0,0 +1,12 @@ + { 0x0060005a, 0x23c077bd, 0x000000e0, 0x008d0040 }, + { 0x0060005a, 0x23e077bd, 0x000000e0, 0x008d0080 }, + { 0x01600038, 0x218003bd, 0x008d03c0, 0x00000000 }, + { 0x01600038, 0x21a003bd, 0x008d03e0, 0x00000000 }, + { 0x0060005a, 0x23c077bd, 0x000000c0, 0x008d0040 }, + { 0x0060005a, 0x23e077bd, 0x000000c0, 0x008d0080 }, + { 0x00600041, 0x204077be, 0x008d03c0, 0x008d0180 }, + { 0x00600041, 0x206077be, 0x008d03e0, 0x008d01a0 }, + { 0x0060005a, 0x23c077bd, 0x000000d0, 0x008d0040 }, + { 0x0060005a, 0x23e077bd, 0x000000d0, 0x008d0080 }, + { 0x00600041, 0x208077be, 0x008d03c0, 0x008d0180 }, + { 0x00600041, 0x20a077be, 0x008d03e0, 0x008d01a0 }, diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_src_projective.g7a b/driver/xf86-video-intel/src/render_program/exa_wm_src_projective.g7a new file mode 100644 index 000000000..9fd495ca3 --- /dev/null +++ b/driver/xf86-video-intel/src/render_program/exa_wm_src_projective.g7a @@ -0,0 +1,63 @@ +/* + * Copyright © 2010 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ + +/* + * Fragment to compute src u/v values + */ +include(`exa_wm.g4i') + +define(`u', `g66') +define(`ul', `g66') +define(`uh', `g67') +define(`v', `src_v') +define(`vl', `src_v') +define(`vh', `g69') +define(`w', `src_w') +define(`wl', `src_w_0') +define(`wh', `src_w_1') + +define(`bl', `g2.0<8,8,1>F') +define(`bh', `g4.0<8,8,1>F') + +define(`a0_a_x',`g6.0<0,1,0>F') +define(`a0_a_y',`g6.16<0,1,0>F') +define(`a0_a_z',`g7.0<0,1,0>F') + +/* W */ +pln (8) temp_x_0<1>F a0_a_z bl { align1 }; /* pixel 0-7 */ +pln (8) temp_x_1<1>F a0_a_z bh { align1 }; /* pixel 8-15 */ +math (8) wl<1>F temp_x_0<8,8,1>F null inv { align1 }; +math (8) wh<1>F temp_x_1<8,8,1>F null inv { align1 }; + +/* U */ +pln (8) temp_x_0<1>F a0_a_x bl { align1 }; /* pixel 0-7 */ +pln (8) temp_x_1<1>F a0_a_x bh { align1 }; /* pixel 8-15 */ +mul (8) ul<1>F temp_x_0<8,8,1>F wl<8,8,1>F { align1 }; +mul (8) uh<1>F temp_x_1<8,8,1>F wh<8,8,1>F { align1 }; + +/* V */ +pln (8) temp_x_0<1>F a0_a_y bl { align1 }; /* pixel 0-7 */ +pln (8) temp_x_1<1>F a0_a_y bh { align1 }; /* pixel 8-15 */ +mul (8) vl<1>F temp_x_0<8,8,1>F wl<8,8,1>F { align1 }; +mul (8) vh<1>F temp_x_1<8,8,1>F wh<8,8,1>F { align1 }; diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_src_projective.g7b b/driver/xf86-video-intel/src/render_program/exa_wm_src_projective.g7b new file mode 100644 index 000000000..73727ffd5 --- /dev/null +++ b/driver/xf86-video-intel/src/render_program/exa_wm_src_projective.g7b @@ -0,0 +1,12 @@ + { 0x0060005a, 0x23c077bd, 0x000000e0, 0x008d0040 }, + { 0x0060005a, 0x23e077bd, 0x000000e0, 0x008d0080 }, + { 0x01600038, 0x218003bd, 0x008d03c0, 0x00000000 }, + { 0x01600038, 0x21a003bd, 0x008d03e0, 0x00000000 }, + { 0x0060005a, 0x23c077bd, 0x000000c0, 0x008d0040 }, + { 0x0060005a, 0x23e077bd, 0x000000c0, 0x008d0080 }, + { 0x00600041, 0x284077bd, 0x008d03c0, 0x008d0180 }, + { 0x00600041, 0x286077bd, 0x008d03e0, 0x008d01a0 }, + { 0x0060005a, 0x23c077bd, 0x000000d0, 0x008d0040 }, + { 0x0060005a, 0x23e077bd, 0x000000d0, 0x008d0080 }, + { 0x00600041, 0x208077be, 0x008d03c0, 0x008d0180 }, + { 0x00600041, 0x28a077bd, 0x008d03e0, 0x008d01a0 }, diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_a.g4a b/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_a.g4a index 552aaeeb8..667bfb36f 100644 --- a/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_a.g4a +++ b/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_a.g4a @@ -36,12 +36,13 @@ include(`exa_wm.g4i') /* load alpha */ mov (1) g0.8<1>UD 0x00007000UD { align1 mask_disable }; +mov (8) src_msg<1>UD g0<8,8,1>UD { align1 }; /* copy to msg start reg*/ /* src_msg will be copied with g0, as it contains send desc */ /* emit sampler 'send' cmd */ send (16) src_msg_ind /* msg reg index */ src_sample_a_01<1>UW /* readback */ - g0<8,8,1>UW /* copy to msg start reg*/ + null sampler (1,0,F) /* sampler message description, (binding_table,sampler_index,datatype) /* here(src->dst) we should use src_sampler and src_surface */ mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */ diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_a.g4b b/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_a.g4b index ce8650a0a..5e5a11f9c 100644 --- a/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_a.g4b +++ b/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_a.g4b @@ -1,2 +1,3 @@ { 0x00000201, 0x20080061, 0x00000000, 0x00007000 }, - { 0x01800031, 0x22801d29, 0x008d0000, 0x02520001 }, + { 0x00600001, 0x20200022, 0x008d0000, 0x00000000 }, + { 0x01800031, 0x22801c09, 0x00000000, 0x02520001 }, diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_a.g4b.gen5 b/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_a.g4b.gen5 index 8cd411c23..0e4eebe23 100644 --- a/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_a.g4b.gen5 +++ b/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_a.g4b.gen5 @@ -1,2 +1,3 @@ { 0x00000201, 0x20080061, 0x00000000, 0x00007000 }, - { 0x01800031, 0x22801d29, 0x208d0000, 0x0a2a0001 }, + { 0x00600001, 0x20200022, 0x008d0000, 0x00000000 }, + { 0x01800031, 0x22801c09, 0x20000000, 0x0a2a0001 }, diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_a.g6b b/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_a.g6b new file mode 100644 index 000000000..0b4a955d0 --- /dev/null +++ b/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_a.g6b @@ -0,0 +1,3 @@ + { 0x00000201, 0x20080061, 0x00000000, 0x00007000 }, + { 0x00600001, 0x20200022, 0x008d0000, 0x00000000 }, + { 0x02800031, 0x22801cc9, 0x00000020, 0x0a2a0001 }, diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_a.g7a b/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_a.g7a new file mode 100644 index 000000000..d5d24fd9e --- /dev/null +++ b/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_a.g7a @@ -0,0 +1,48 @@ +/* + * Copyright © 2006 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Wang Zhenyu <zhenyu.z.wang@intel.com> + * Keith Packard <keithp@keithp.com> + */ + +/* Sample the src surface */ + +include(`exa_wm.g4i') + +/* prepare sampler read back gX register, which would be written back to output */ + +/* use simd16 sampler, param 0 is u, param 1 is v. */ +/* 'payload' loading, assuming tex coord start from g4 */ + +/* load alpha */ +mov (1) g0.8<1>UD 0x00007000UD { align1 mask_disable }; +mov (8) g65<1>UD g0<8,8,1>UD { align1 }; /* copy to msg start reg*/ + +/* g65 will be copied with g0, as it contains send desc */ +/* emit sampler 'send' cmd */ +send (16) 65 /* msg reg index */ + src_sample_a_01<1>UW /* readback */ + null + sampler (1,0,F) /* sampler message description, (binding_table,sampler_index,datatype) + /* here(src->dst) we should use src_sampler and src_surface */ + mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */ diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_a.g7b b/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_a.g7b new file mode 100644 index 000000000..73912b759 --- /dev/null +++ b/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_a.g7b @@ -0,0 +1,3 @@ + { 0x00000201, 0x20080061, 0x00000000, 0x00007000 }, + { 0x00600001, 0x28200021, 0x008d0000, 0x00000000 }, + { 0x02800031, 0x22801ca9, 0x00000820, 0x0a2c0001 }, diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_argb.g4a b/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_argb.g4a index c20f53f22..02119e317 100644 --- a/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_argb.g4a +++ b/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_argb.g4a @@ -29,19 +29,4 @@ include(`exa_wm.g4i') -/* prepare sampler read back gX register, which would be written back to output */ - -/* use simd16 sampler, param 0 is u, param 1 is v. */ -/* 'payload' loading, assuming tex coord start from g4 */ - -/* load argb */ -mov (1) g0.8<1>UD 0x00000000UD { align1 mask_disable }; - -/* src_msg will be copied with g0, as it contains send desc */ -/* emit sampler 'send' cmd */ -send (16) src_msg_ind /* msg reg index */ - src_sample_base<1>UW /* readback */ - g0<8,8,1>UW /* copy to msg start reg*/ - sampler (1,0,F) /* sampler message description, (binding_table,sampler_index,datatype) - /* here(src->dst) we should use src_sampler and src_surface */ - mlen 5 rlen 8 { align1 }; /* required message len 5, readback len 8 */ +include(`exa_wm_src_sample_argb.g4i') diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_argb.g4b b/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_argb.g4b index c5b927401..a15e40a05 100644 --- a/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_argb.g4b +++ b/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_argb.g4b @@ -1,2 +1,3 @@ { 0x00000201, 0x20080061, 0x00000000, 0x00000000 }, - { 0x01800031, 0x21c01d29, 0x008d0000, 0x02580001 }, + { 0x00600001, 0x20200022, 0x008d0000, 0x00000000 }, + { 0x01800031, 0x21c01c09, 0x00000000, 0x02580001 }, diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_argb.g4b.gen5 b/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_argb.g4b.gen5 index f8cb41efd..42039afff 100644 --- a/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_argb.g4b.gen5 +++ b/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_argb.g4b.gen5 @@ -1,2 +1,3 @@ { 0x00000201, 0x20080061, 0x00000000, 0x00000000 }, - { 0x01800031, 0x21c01d29, 0x208d0000, 0x0a8a0001 }, + { 0x00600001, 0x20200022, 0x008d0000, 0x00000000 }, + { 0x01800031, 0x21c01c09, 0x20000000, 0x0a8a0001 }, diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_argb.g4i b/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_argb.g4i new file mode 100644 index 000000000..62d5afc78 --- /dev/null +++ b/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_argb.g4i @@ -0,0 +1,44 @@ +/* + * Copyright © 2006 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Wang Zhenyu <zhenyu.z.wang@intel.com> + * Keith Packard <keithp@keithp.com> + */ + +/* prepare sampler read back gX register, which would be written back to output */ + +/* use simd16 sampler, param 0 is u, param 1 is v. */ +/* 'payload' loading, assuming tex coord start from g4 */ + +/* load argb */ +mov (1) g0.8<1>UD 0x00000000UD { align1 mask_disable }; +mov (8) src_msg<1>UD g0<8,8,1>UD { align1 }; /* copy to msg start reg*/ + +/* src_msg will be copied with g0, as it contains send desc */ +/* emit sampler 'send' cmd */ +send (16) src_msg_ind /* msg reg index */ + src_sample_base<1>UW /* readback */ + null + sampler (1,0,F) /* sampler message description, (binding_table,sampler_index,datatype) + /* here(src->dst) we should use src_sampler and src_surface */ + mlen 5 rlen 8 { align1 }; /* required message len 5, readback len 8 */ diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_argb.g6b b/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_argb.g6b new file mode 100644 index 000000000..8bfe84986 --- /dev/null +++ b/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_argb.g6b @@ -0,0 +1,3 @@ + { 0x00000201, 0x20080061, 0x00000000, 0x00000000 }, + { 0x00600001, 0x20200022, 0x008d0000, 0x00000000 }, + { 0x02800031, 0x21c01cc9, 0x00000020, 0x0a8a0001 }, diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_argb.g7a b/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_argb.g7a new file mode 100644 index 000000000..69f5ebc07 --- /dev/null +++ b/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_argb.g7a @@ -0,0 +1,38 @@ +/* + * Copyright © 2006 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Wang Zhenyu <zhenyu.z.wang@intel.com> + * Keith Packard <keithp@keithp.com> + */ + +/* Sample the src surface */ + +include(`exa_wm.g4i') + +undefine(`src_msg') +undefine(`src_msg_ind') + +define(`src_msg', `g65') +define(`src_msg_ind', `65') + +include(`exa_wm_src_sample_argb.g4i') diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_argb.g7b b/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_argb.g7b new file mode 100644 index 000000000..a282cf8ff --- /dev/null +++ b/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_argb.g7b @@ -0,0 +1,3 @@ + { 0x00000201, 0x20080061, 0x00000000, 0x00000000 }, + { 0x00600001, 0x28200021, 0x008d0000, 0x00000000 }, + { 0x02800031, 0x21c01ca9, 0x00000820, 0x0a8c0001 }, diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_planar.g4a b/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_planar.g4a index ad33350f5..59678f532 100644 --- a/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_planar.g4a +++ b/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_planar.g4a @@ -29,37 +29,4 @@ include(`exa_wm.g4i') -/* prepare sampler read back gX register, which would be written back to output */ - -/* use simd16 sampler, param 0 is u, param 1 is v. */ -/* 'payload' loading, assuming tex coord start from g4 */ - -/* load r */ -mov (1) g0.8<1>UD 0x0000e000UD { align1 mask_disable }; - -/* src_msg will be copied with g0, as it contains send desc */ -/* emit sampler 'send' cmd */ - -/* sample Y */ -send (16) src_msg_ind /* msg reg index */ - src_sample_g<1>UW /* readback */ - g0<8,8,1>UW /* copy to msg start reg*/ - sampler (1,0,F) /* sampler message description, (binding_table,sampler_index,datatype) - /* here(src->dst) we should use src_sampler and src_surface */ - mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */ - -/* sample U (Cr) */ -send (16) src_msg_ind /* msg reg index */ - src_sample_r<1>UW /* readback */ - g0<8,8,1>UW /* copy to msg start reg*/ - sampler (3,0,F) /* sampler message description, (binding_table,sampler_index,datatype) - /* here(src->dst) we should use src_sampler and src_surface */ - mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */ - -/* sample V (Cb) */ -send (16) src_msg_ind /* msg reg index */ - src_sample_b<1>UW /* readback */ - g0<8,8,1>UW /* copy to msg start reg*/ - sampler (5,0,F) /* sampler message description, (binding_table,sampler_index,datatype) - /* here(src->dst) we should use src_sampler and src_surface */ - mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */ +include(`exa_wm_sample_planar.g4i') diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_planar.g4b b/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_planar.g4b index 23e5e0d76..c8dc47d78 100644 --- a/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_planar.g4b +++ b/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_planar.g4b @@ -1,4 +1,5 @@ { 0x00000201, 0x20080061, 0x00000000, 0x0000e000 }, - { 0x01800031, 0x22001d29, 0x008d0000, 0x02520001 }, - { 0x01800031, 0x21c01d29, 0x008d0000, 0x02520003 }, - { 0x01800031, 0x22401d29, 0x008d0000, 0x02520005 }, + { 0x00600001, 0x20200022, 0x008d0000, 0x00000000 }, + { 0x01800031, 0x22001c09, 0x00000000, 0x02520001 }, + { 0x01800031, 0x21c01c09, 0x00000000, 0x02520003 }, + { 0x01800031, 0x22401c09, 0x00000000, 0x02520005 }, diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_planar.g4b.gen5 b/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_planar.g4b.gen5 index 71068d9f2..ce3670b9b 100644 --- a/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_planar.g4b.gen5 +++ b/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_planar.g4b.gen5 @@ -1,4 +1,5 @@ { 0x00000201, 0x20080061, 0x00000000, 0x0000e000 }, - { 0x01800031, 0x22001d29, 0x208d0000, 0x0a2a0001 }, - { 0x01800031, 0x21c01d29, 0x208d0000, 0x0a2a0003 }, - { 0x01800031, 0x22401d29, 0x208d0000, 0x0a2a0005 }, + { 0x00600001, 0x20200022, 0x008d0000, 0x00000000 }, + { 0x01800031, 0x22001c09, 0x20000000, 0x0a2a0001 }, + { 0x01800031, 0x21c01c09, 0x20000000, 0x0a2a0003 }, + { 0x01800031, 0x22401c09, 0x20000000, 0x0a2a0005 }, diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_planar.g6b b/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_planar.g6b new file mode 100644 index 000000000..0a22827e8 --- /dev/null +++ b/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_planar.g6b @@ -0,0 +1,5 @@ + { 0x00000201, 0x20080061, 0x00000000, 0x0000e000 }, + { 0x00600001, 0x20200022, 0x008d0000, 0x00000000 }, + { 0x02800031, 0x22001cc9, 0x00000020, 0x0a2a0001 }, + { 0x02800031, 0x21c01cc9, 0x00000020, 0x0a2a0003 }, + { 0x02800031, 0x22401cc9, 0x00000020, 0x0a2a0005 }, diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_planar.g7a b/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_planar.g7a new file mode 100644 index 000000000..53b12110f --- /dev/null +++ b/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_planar.g7a @@ -0,0 +1,38 @@ +/* + * Copyright © 2006 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Wang Zhenyu <zhenyu.z.wang@intel.com> + * Keith Packard <keithp@keithp.com> + */ + +/* Sample the src surface in planar format */ + +include(`exa_wm.g4i') + +undefine(`src_msg') +undefine(`src_msg_ind') + +define(`src_msg', `g65') +define(`src_msg_ind', `65') + +include(`exa_wm_sample_planar.g4i') diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_planar.g7b b/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_planar.g7b new file mode 100644 index 000000000..ddd6f3659 --- /dev/null +++ b/driver/xf86-video-intel/src/render_program/exa_wm_src_sample_planar.g7b @@ -0,0 +1,5 @@ + { 0x00000201, 0x20080061, 0x00000000, 0x0000e000 }, + { 0x00600001, 0x28200021, 0x008d0000, 0x00000000 }, + { 0x02800031, 0x22001ca9, 0x00000820, 0x0a2c0001 }, + { 0x02800031, 0x21c01ca9, 0x00000820, 0x0a2c0003 }, + { 0x02800031, 0x22401ca9, 0x00000820, 0x0a2c0005 }, diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_write.g6a b/driver/xf86-video-intel/src/render_program/exa_wm_write.g6a new file mode 100644 index 000000000..ed976b5cc --- /dev/null +++ b/driver/xf86-video-intel/src/render_program/exa_wm_write.g6a @@ -0,0 +1,41 @@ +/* + * Copyright © 2010 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ + +include(`exa_wm.g4i') + +/* + * Prepare data in m2-m3 for Red channel, m4-m5 for Green channel, + * m6-m7 for Blue and m8-m9 for Alpha channel + */ +define(`slot_r_00', `m2') +define(`slot_r_01', `m3') +define(`slot_g_00', `m4') +define(`slot_g_01', `m5') +define(`slot_b_00', `m6') +define(`slot_b_01', `m7') +define(`slot_a_00', `m8') +define(`slot_a_01', `m9') +define(`data_port_msg_2_ind', `2') + +include(`exa_wm_write.g6i') diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_write.g6b b/driver/xf86-video-intel/src/render_program/exa_wm_write.g6b new file mode 100644 index 000000000..3cb6bff38 --- /dev/null +++ b/driver/xf86-video-intel/src/render_program/exa_wm_write.g6b @@ -0,0 +1,17 @@ + { 0x00600001, 0x204003be, 0x008d01c0, 0x00000000 }, + { 0x00600001, 0x206003be, 0x008d01e0, 0x00000000 }, + { 0x00600001, 0x208003be, 0x008d0200, 0x00000000 }, + { 0x00600001, 0x20a003be, 0x008d0220, 0x00000000 }, + { 0x00600001, 0x20c003be, 0x008d0240, 0x00000000 }, + { 0x00600001, 0x20e003be, 0x008d0260, 0x00000000 }, + { 0x00600001, 0x210003be, 0x008d0280, 0x00000000 }, + { 0x00600001, 0x212003be, 0x008d02a0, 0x00000000 }, + { 0x05800031, 0x24001cc8, 0x00000040, 0x90019000 }, + { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, + { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, + { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, + { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, + { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, + { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, + { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, + { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_write.g6i b/driver/xf86-video-intel/src/render_program/exa_wm_write.g6i new file mode 100644 index 000000000..7be1db299 --- /dev/null +++ b/driver/xf86-video-intel/src/render_program/exa_wm_write.g6i @@ -0,0 +1,61 @@ +/* + * Copyright © 2010 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ + +mov (8) slot_r_00<1>F src_sample_r_01<8,8,1>F { align1 }; +mov (8) slot_r_01<1>F src_sample_r_23<8,8,1>F { align1 }; + +mov (8) slot_g_00<1>F src_sample_g_01<8,8,1>F { align1 }; +mov (8) slot_g_01<1>F src_sample_g_23<8,8,1>F { align1 }; + +mov (8) slot_b_00<1>F src_sample_b_01<8,8,1>F { align1 }; +mov (8) slot_b_01<1>F src_sample_b_23<8,8,1>F { align1 }; + +mov (8) slot_a_00<1>F src_sample_a_01<8,8,1>F { align1 }; +mov (8) slot_a_01<1>F src_sample_a_23<8,8,1>F { align1 }; + +/* write */ +send (16) + data_port_msg_2_ind + acc0<1>UW + null + write ( + 0, /* binding_table */ + 16, /* pixel scordboard clear, msg type simd16 single source */ + 12, /* render target write */ + 0, /* no write commit message */ + 0 /* headerless render target write */ + ) + mlen 8 + rlen 0 + { align1 EOT }; + +nop; +nop; +nop; +nop; +nop; +nop; +nop; +nop; + diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_write.g7a b/driver/xf86-video-intel/src/render_program/exa_wm_write.g7a new file mode 100644 index 000000000..d21f9b462 --- /dev/null +++ b/driver/xf86-video-intel/src/render_program/exa_wm_write.g7a @@ -0,0 +1,41 @@ +/* + * Copyright © 2010 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ + +include(`exa_wm.g4i') + +/* + * Prepare data in g66-g67 for Red channel, g68-g69 for Green channel, + * g70-g71 for Blue and g72-g73 for Alpha channel + */ +define(`slot_r_00', `g66') +define(`slot_r_01', `g67') +define(`slot_g_00', `g68') +define(`slot_g_01', `g69') +define(`slot_b_00', `g70') +define(`slot_b_01', `g71') +define(`slot_a_00', `g72') +define(`slot_a_01', `g73') +define(`data_port_msg_2_ind', `66') + +include(`exa_wm_write.g6i') diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_write.g7b b/driver/xf86-video-intel/src/render_program/exa_wm_write.g7b new file mode 100644 index 000000000..f31af5187 --- /dev/null +++ b/driver/xf86-video-intel/src/render_program/exa_wm_write.g7b @@ -0,0 +1,17 @@ + { 0x00600001, 0x284003bd, 0x008d01c0, 0x00000000 }, + { 0x00600001, 0x286003bd, 0x008d01e0, 0x00000000 }, + { 0x00600001, 0x288003bd, 0x008d0200, 0x00000000 }, + { 0x00600001, 0x28a003bd, 0x008d0220, 0x00000000 }, + { 0x00600001, 0x28c003bd, 0x008d0240, 0x00000000 }, + { 0x00600001, 0x28e003bd, 0x008d0260, 0x00000000 }, + { 0x00600001, 0x290003bd, 0x008d0280, 0x00000000 }, + { 0x00600001, 0x292003bd, 0x008d02a0, 0x00000000 }, + { 0x05800031, 0x24001ca8, 0x00000840, 0x90031000 }, + { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, + { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, + { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, + { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, + { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, + { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, + { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, + { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_yuv_rgb.g6b b/driver/xf86-video-intel/src/render_program/exa_wm_yuv_rgb.g6b new file mode 100644 index 000000000..01ec5e50a --- /dev/null +++ b/driver/xf86-video-intel/src/render_program/exa_wm_yuv_rgb.g6b @@ -0,0 +1,12 @@ + { 0x00800040, 0x23007fbd, 0x008d0200, 0xbd808081 }, + { 0x00800041, 0x23007fbd, 0x008d0300, 0x3f94fdf4 }, + { 0x00800040, 0x22c07fbd, 0x008d01c0, 0xbf008084 }, + { 0x00800040, 0x23407fbd, 0x008d0240, 0xbf008084 }, + { 0x00800001, 0x240003bc, 0x008d0300, 0x00000000 }, + { 0x80800048, 0x21c07fbd, 0x008d02c0, 0x3fcc49ba }, + { 0x00800001, 0x240003bc, 0x008d0300, 0x00000000 }, + { 0x00800048, 0x24007fbc, 0x008d02c0, 0xbf5020c5 }, + { 0x80800048, 0x22007fbd, 0x008d0340, 0xbec8b439 }, + { 0x00800001, 0x240003bc, 0x008d0300, 0x00000000 }, + { 0x80800048, 0x22407fbd, 0x008d0340, 0x40011687 }, + { 0x00800001, 0x228003fd, 0x00000000, 0x3f800000 }, diff --git a/driver/xf86-video-intel/src/render_program/exa_wm_yuv_rgb.g7b b/driver/xf86-video-intel/src/render_program/exa_wm_yuv_rgb.g7b new file mode 100644 index 000000000..01ec5e50a --- /dev/null +++ b/driver/xf86-video-intel/src/render_program/exa_wm_yuv_rgb.g7b @@ -0,0 +1,12 @@ + { 0x00800040, 0x23007fbd, 0x008d0200, 0xbd808081 }, + { 0x00800041, 0x23007fbd, 0x008d0300, 0x3f94fdf4 }, + { 0x00800040, 0x22c07fbd, 0x008d01c0, 0xbf008084 }, + { 0x00800040, 0x23407fbd, 0x008d0240, 0xbf008084 }, + { 0x00800001, 0x240003bc, 0x008d0300, 0x00000000 }, + { 0x80800048, 0x21c07fbd, 0x008d02c0, 0x3fcc49ba }, + { 0x00800001, 0x240003bc, 0x008d0300, 0x00000000 }, + { 0x00800048, 0x24007fbc, 0x008d02c0, 0xbf5020c5 }, + { 0x80800048, 0x22007fbd, 0x008d0340, 0xbec8b439 }, + { 0x00800001, 0x240003bc, 0x008d0300, 0x00000000 }, + { 0x80800048, 0x22407fbd, 0x008d0340, 0x40011687 }, + { 0x00800001, 0x228003fd, 0x00000000, 0x3f800000 }, diff --git a/driver/xf86-video-intel/src/sil164/Makefile.in b/driver/xf86-video-intel/src/sil164/Makefile.in index 14d711b8b..2200b050f 100644 --- a/driver/xf86-video-intel/src/sil164/Makefile.in +++ b/driver/xf86-video-intel/src/sil164/Makefile.in @@ -87,10 +87,6 @@ AUTOCONF = @AUTOCONF@ AUTOHEADER = @AUTOHEADER@ AUTOMAKE = @AUTOMAKE@ AWK = @AWK@ -BUILD_LINUXDOC_FALSE = @BUILD_LINUXDOC_FALSE@ -BUILD_LINUXDOC_TRUE = @BUILD_LINUXDOC_TRUE@ -BUILD_PDFDOC_FALSE = @BUILD_PDFDOC_FALSE@ -BUILD_PDFDOC_TRUE = @BUILD_PDFDOC_TRUE@ CC = @CC@ CCDEPMODE = @CCDEPMODE@ CFLAGS = @CFLAGS@ @@ -130,8 +126,6 @@ GEN4ASM_LIBS = @GEN4ASM_LIBS@ GREP = @GREP@ HAVE_GEN4ASM_FALSE = @HAVE_GEN4ASM_FALSE@ HAVE_GEN4ASM_TRUE = @HAVE_GEN4ASM_TRUE@ -HAVE_XEXTPROTO_71_FALSE = @HAVE_XEXTPROTO_71_FALSE@ -HAVE_XEXTPROTO_71_TRUE = @HAVE_XEXTPROTO_71_TRUE@ INSTALL_CMD = @INSTALL_CMD@ INSTALL_DATA = @INSTALL_DATA@ INSTALL_PROGRAM = @INSTALL_PROGRAM@ @@ -145,17 +139,13 @@ LIBS = @LIBS@ LIBTOOL = @LIBTOOL@ LIB_MAN_DIR = @LIB_MAN_DIR@ LIB_MAN_SUFFIX = @LIB_MAN_SUFFIX@ -LINUXDOC = @LINUXDOC@ LN_S = @LN_S@ LTLIBOBJS = @LTLIBOBJS@ MAINT = @MAINT@ MAINTAINER_MODE_FALSE = @MAINTAINER_MODE_FALSE@ MAINTAINER_MODE_TRUE = @MAINTAINER_MODE_TRUE@ MAKEINFO = @MAKEINFO@ -MAKE_HTML = @MAKE_HTML@ -MAKE_PDF = @MAKE_PDF@ -MAKE_PS = @MAKE_PS@ -MAKE_TEXT = @MAKE_TEXT@ +MAN_SUBSTS = @MAN_SUBSTS@ MISC_MAN_DIR = @MISC_MAN_DIR@ MISC_MAN_SUFFIX = @MISC_MAN_SUFFIX@ NMEDIT = @NMEDIT@ @@ -170,19 +160,15 @@ PATH_SEPARATOR = @PATH_SEPARATOR@ PCIACCESS_CFLAGS = @PCIACCESS_CFLAGS@ PCIACCESS_LIBS = @PCIACCESS_LIBS@ PKG_CONFIG = @PKG_CONFIG@ -PS2PDF = @PS2PDF@ RANLIB = @RANLIB@ SED = @SED@ SET_MAKE = @SET_MAKE@ SHELL = @SHELL@ STRIP = @STRIP@ VERSION = @VERSION@ -VIDEO_DEBUG_FALSE = @VIDEO_DEBUG_FALSE@ -VIDEO_DEBUG_TRUE = @VIDEO_DEBUG_TRUE@ -XEXT_CFLAGS = @XEXT_CFLAGS@ -XEXT_LIBS = @XEXT_LIBS@ XORG_CFLAGS = @XORG_CFLAGS@ XORG_LIBS = @XORG_LIBS@ +XORG_MAN_PAGE = @XORG_MAN_PAGE@ XVMCLIB_CFLAGS = @XVMCLIB_CFLAGS@ XVMCLIB_LIBS = @XVMCLIB_LIBS@ XVMC_FALSE = @XVMC_FALSE@ diff --git a/driver/xf86-video-intel/src/tfp410/Makefile.in b/driver/xf86-video-intel/src/tfp410/Makefile.in index 1a37cb799..3ca834042 100644 --- a/driver/xf86-video-intel/src/tfp410/Makefile.in +++ b/driver/xf86-video-intel/src/tfp410/Makefile.in @@ -87,10 +87,6 @@ AUTOCONF = @AUTOCONF@ AUTOHEADER = @AUTOHEADER@ AUTOMAKE = @AUTOMAKE@ AWK = @AWK@ -BUILD_LINUXDOC_FALSE = @BUILD_LINUXDOC_FALSE@ -BUILD_LINUXDOC_TRUE = @BUILD_LINUXDOC_TRUE@ -BUILD_PDFDOC_FALSE = @BUILD_PDFDOC_FALSE@ -BUILD_PDFDOC_TRUE = @BUILD_PDFDOC_TRUE@ CC = @CC@ CCDEPMODE = @CCDEPMODE@ CFLAGS = @CFLAGS@ @@ -130,8 +126,6 @@ GEN4ASM_LIBS = @GEN4ASM_LIBS@ GREP = @GREP@ HAVE_GEN4ASM_FALSE = @HAVE_GEN4ASM_FALSE@ HAVE_GEN4ASM_TRUE = @HAVE_GEN4ASM_TRUE@ -HAVE_XEXTPROTO_71_FALSE = @HAVE_XEXTPROTO_71_FALSE@ -HAVE_XEXTPROTO_71_TRUE = @HAVE_XEXTPROTO_71_TRUE@ INSTALL_CMD = @INSTALL_CMD@ INSTALL_DATA = @INSTALL_DATA@ INSTALL_PROGRAM = @INSTALL_PROGRAM@ @@ -145,17 +139,13 @@ LIBS = @LIBS@ LIBTOOL = @LIBTOOL@ LIB_MAN_DIR = @LIB_MAN_DIR@ LIB_MAN_SUFFIX = @LIB_MAN_SUFFIX@ -LINUXDOC = @LINUXDOC@ LN_S = @LN_S@ LTLIBOBJS = @LTLIBOBJS@ MAINT = @MAINT@ MAINTAINER_MODE_FALSE = @MAINTAINER_MODE_FALSE@ MAINTAINER_MODE_TRUE = @MAINTAINER_MODE_TRUE@ MAKEINFO = @MAKEINFO@ -MAKE_HTML = @MAKE_HTML@ -MAKE_PDF = @MAKE_PDF@ -MAKE_PS = @MAKE_PS@ -MAKE_TEXT = @MAKE_TEXT@ +MAN_SUBSTS = @MAN_SUBSTS@ MISC_MAN_DIR = @MISC_MAN_DIR@ MISC_MAN_SUFFIX = @MISC_MAN_SUFFIX@ NMEDIT = @NMEDIT@ @@ -170,19 +160,15 @@ PATH_SEPARATOR = @PATH_SEPARATOR@ PCIACCESS_CFLAGS = @PCIACCESS_CFLAGS@ PCIACCESS_LIBS = @PCIACCESS_LIBS@ PKG_CONFIG = @PKG_CONFIG@ -PS2PDF = @PS2PDF@ RANLIB = @RANLIB@ SED = @SED@ SET_MAKE = @SET_MAKE@ SHELL = @SHELL@ STRIP = @STRIP@ VERSION = @VERSION@ -VIDEO_DEBUG_FALSE = @VIDEO_DEBUG_FALSE@ -VIDEO_DEBUG_TRUE = @VIDEO_DEBUG_TRUE@ -XEXT_CFLAGS = @XEXT_CFLAGS@ -XEXT_LIBS = @XEXT_LIBS@ XORG_CFLAGS = @XORG_CFLAGS@ XORG_LIBS = @XORG_LIBS@ +XORG_MAN_PAGE = @XORG_MAN_PAGE@ XVMCLIB_CFLAGS = @XVMCLIB_CFLAGS@ XVMCLIB_LIBS = @XVMCLIB_LIBS@ XVMC_FALSE = @XVMC_FALSE@ diff --git a/driver/xf86-video-intel/src/xvmc/Makefile.am b/driver/xf86-video-intel/src/xvmc/Makefile.am index be8824b82..9473b7f29 100644 --- a/driver/xf86-video-intel/src/xvmc/Makefile.am +++ b/driver/xf86-video-intel/src/xvmc/Makefile.am @@ -1,17 +1,9 @@ if XVMC -lib_LTLIBRARIES=libI810XvMC.la libIntelXvMC.la +lib_LTLIBRARIES=libIntelXvMC.la endif SUBDIRS = shader -libI810XvMC_la_SOURCES = I810XvMC.c \ - I810XvMC.h - -libI810XvMC_la_CFLAGS = @CWARNFLAGS@ @XORG_CFLAGS@ @DRM_CFLAGS@ @DRI_CFLAGS@ \ - -I$(top_srcdir)/src -DTRUE=1 -DFALSE=0 -libI810XvMC_la_LDFLAGS = -version-number 1:0:0 -libI810XvMC_la_LIBADD = @DRI_LIBS@ @DRM_LIBS@ @XVMCLIB_LIBS@ - libIntelXvMC_la_SOURCES = intel_xvmc.c \ intel_xvmc.h \ intel_xvmc_dump.c \ @@ -26,7 +18,8 @@ libIntelXvMC_la_SOURCES = intel_xvmc.c \ intel_batchbuffer.c \ intel_batchbuffer.h -libIntelXvMC_la_CFLAGS = @XORG_CFLAGS@ @DRM_CFLAGS@ @DRI_CFLAGS@ \ +AM_CFLAGS = @XORG_CFLAGS@ @DRM_CFLAGS@ @DRI_CFLAGS@ \ @XVMCLIB_CFLAGS@ -I$(top_srcdir)/src -DTRUE=1 -DFALSE=0 + libIntelXvMC_la_LDFLAGS = -version-number 1:0:0 libIntelXvMC_la_LIBADD = @DRI_LIBS@ @DRM_LIBS@ @XVMCLIB_LIBS@ -lpthread -ldrm_intel diff --git a/driver/xf86-video-intel/src/xvmc/Makefile.in b/driver/xf86-video-intel/src/xvmc/Makefile.in index a4b2751a0..cfc75ab7d 100644 --- a/driver/xf86-video-intel/src/xvmc/Makefile.in +++ b/driver/xf86-video-intel/src/xvmc/Makefile.in @@ -54,16 +54,9 @@ am__strip_dir = `echo $$p | sed -e 's|^.*/||'`; am__installdirs = "$(DESTDIR)$(libdir)" libLTLIBRARIES_INSTALL = $(INSTALL) LTLIBRARIES = $(lib_LTLIBRARIES) -libI810XvMC_la_DEPENDENCIES = -am_libI810XvMC_la_OBJECTS = libI810XvMC_la-I810XvMC.lo -libI810XvMC_la_OBJECTS = $(am_libI810XvMC_la_OBJECTS) -@XVMC_TRUE@am_libI810XvMC_la_rpath = -rpath $(libdir) libIntelXvMC_la_DEPENDENCIES = -am_libIntelXvMC_la_OBJECTS = libIntelXvMC_la-intel_xvmc.lo \ - libIntelXvMC_la-intel_xvmc_dump.lo \ - libIntelXvMC_la-i915_xvmc.lo libIntelXvMC_la-i965_xvmc.lo \ - libIntelXvMC_la-xvmc_vld.lo \ - libIntelXvMC_la-intel_batchbuffer.lo +am_libIntelXvMC_la_OBJECTS = intel_xvmc.lo intel_xvmc_dump.lo \ + i915_xvmc.lo i965_xvmc.lo xvmc_vld.lo intel_batchbuffer.lo libIntelXvMC_la_OBJECTS = $(am_libIntelXvMC_la_OBJECTS) @XVMC_TRUE@am_libIntelXvMC_la_rpath = -rpath $(libdir) DEFAULT_INCLUDES = -I. -I$(srcdir) -I$(top_builddir) @@ -77,8 +70,8 @@ LTCOMPILE = $(LIBTOOL) --tag=CC --mode=compile $(CC) $(DEFS) \ CCLD = $(CC) LINK = $(LIBTOOL) --tag=CC --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \ $(AM_LDFLAGS) $(LDFLAGS) -o $@ -SOURCES = $(libI810XvMC_la_SOURCES) $(libIntelXvMC_la_SOURCES) -DIST_SOURCES = $(libI810XvMC_la_SOURCES) $(libIntelXvMC_la_SOURCES) +SOURCES = $(libIntelXvMC_la_SOURCES) +DIST_SOURCES = $(libIntelXvMC_la_SOURCES) RECURSIVE_TARGETS = all-recursive check-recursive dvi-recursive \ html-recursive info-recursive install-data-recursive \ install-exec-recursive install-info-recursive \ @@ -103,10 +96,6 @@ AUTOCONF = @AUTOCONF@ AUTOHEADER = @AUTOHEADER@ AUTOMAKE = @AUTOMAKE@ AWK = @AWK@ -BUILD_LINUXDOC_FALSE = @BUILD_LINUXDOC_FALSE@ -BUILD_LINUXDOC_TRUE = @BUILD_LINUXDOC_TRUE@ -BUILD_PDFDOC_FALSE = @BUILD_PDFDOC_FALSE@ -BUILD_PDFDOC_TRUE = @BUILD_PDFDOC_TRUE@ CC = @CC@ CCDEPMODE = @CCDEPMODE@ CFLAGS = @CFLAGS@ @@ -146,8 +135,6 @@ GEN4ASM_LIBS = @GEN4ASM_LIBS@ GREP = @GREP@ HAVE_GEN4ASM_FALSE = @HAVE_GEN4ASM_FALSE@ HAVE_GEN4ASM_TRUE = @HAVE_GEN4ASM_TRUE@ -HAVE_XEXTPROTO_71_FALSE = @HAVE_XEXTPROTO_71_FALSE@ -HAVE_XEXTPROTO_71_TRUE = @HAVE_XEXTPROTO_71_TRUE@ INSTALL_CMD = @INSTALL_CMD@ INSTALL_DATA = @INSTALL_DATA@ INSTALL_PROGRAM = @INSTALL_PROGRAM@ @@ -161,17 +148,13 @@ LIBS = @LIBS@ LIBTOOL = @LIBTOOL@ LIB_MAN_DIR = @LIB_MAN_DIR@ LIB_MAN_SUFFIX = @LIB_MAN_SUFFIX@ -LINUXDOC = @LINUXDOC@ LN_S = @LN_S@ LTLIBOBJS = @LTLIBOBJS@ MAINT = @MAINT@ MAINTAINER_MODE_FALSE = @MAINTAINER_MODE_FALSE@ MAINTAINER_MODE_TRUE = @MAINTAINER_MODE_TRUE@ MAKEINFO = @MAKEINFO@ -MAKE_HTML = @MAKE_HTML@ -MAKE_PDF = @MAKE_PDF@ -MAKE_PS = @MAKE_PS@ -MAKE_TEXT = @MAKE_TEXT@ +MAN_SUBSTS = @MAN_SUBSTS@ MISC_MAN_DIR = @MISC_MAN_DIR@ MISC_MAN_SUFFIX = @MISC_MAN_SUFFIX@ NMEDIT = @NMEDIT@ @@ -186,19 +169,15 @@ PATH_SEPARATOR = @PATH_SEPARATOR@ PCIACCESS_CFLAGS = @PCIACCESS_CFLAGS@ PCIACCESS_LIBS = @PCIACCESS_LIBS@ PKG_CONFIG = @PKG_CONFIG@ -PS2PDF = @PS2PDF@ RANLIB = @RANLIB@ SED = @SED@ SET_MAKE = @SET_MAKE@ SHELL = @SHELL@ STRIP = @STRIP@ VERSION = @VERSION@ -VIDEO_DEBUG_FALSE = @VIDEO_DEBUG_FALSE@ -VIDEO_DEBUG_TRUE = @VIDEO_DEBUG_TRUE@ -XEXT_CFLAGS = @XEXT_CFLAGS@ -XEXT_LIBS = @XEXT_LIBS@ XORG_CFLAGS = @XORG_CFLAGS@ XORG_LIBS = @XORG_LIBS@ +XORG_MAN_PAGE = @XORG_MAN_PAGE@ XVMCLIB_CFLAGS = @XVMCLIB_CFLAGS@ XVMCLIB_LIBS = @XVMCLIB_LIBS@ XVMC_FALSE = @XVMC_FALSE@ @@ -251,16 +230,8 @@ sbindir = @sbindir@ sharedstatedir = @sharedstatedir@ sysconfdir = @sysconfdir@ target_alias = @target_alias@ -@XVMC_TRUE@lib_LTLIBRARIES = libI810XvMC.la libIntelXvMC.la +@XVMC_TRUE@lib_LTLIBRARIES = libIntelXvMC.la SUBDIRS = shader -libI810XvMC_la_SOURCES = I810XvMC.c \ - I810XvMC.h - -libI810XvMC_la_CFLAGS = @CWARNFLAGS@ @XORG_CFLAGS@ @DRM_CFLAGS@ @DRI_CFLAGS@ \ - -I$(top_srcdir)/src -DTRUE=1 -DFALSE=0 - -libI810XvMC_la_LDFLAGS = -version-number 1:0:0 -libI810XvMC_la_LIBADD = @DRI_LIBS@ @DRM_LIBS@ @XVMCLIB_LIBS@ libIntelXvMC_la_SOURCES = intel_xvmc.c \ intel_xvmc.h \ intel_xvmc_dump.c \ @@ -275,7 +246,7 @@ libIntelXvMC_la_SOURCES = intel_xvmc.c \ intel_batchbuffer.c \ intel_batchbuffer.h -libIntelXvMC_la_CFLAGS = @XORG_CFLAGS@ @DRM_CFLAGS@ @DRI_CFLAGS@ \ +AM_CFLAGS = @XORG_CFLAGS@ @DRM_CFLAGS@ @DRI_CFLAGS@ \ @XVMCLIB_CFLAGS@ -I$(top_srcdir)/src -DTRUE=1 -DFALSE=0 libIntelXvMC_la_LDFLAGS = -version-number 1:0:0 @@ -340,8 +311,6 @@ clean-libLTLIBRARIES: echo "rm -f \"$${dir}/so_locations\""; \ rm -f "$${dir}/so_locations"; \ done -libI810XvMC.la: $(libI810XvMC_la_OBJECTS) $(libI810XvMC_la_DEPENDENCIES) - $(LINK) $(am_libI810XvMC_la_rpath) $(libI810XvMC_la_LDFLAGS) $(libI810XvMC_la_OBJECTS) $(libI810XvMC_la_LIBADD) $(LIBS) libIntelXvMC.la: $(libIntelXvMC_la_OBJECTS) $(libIntelXvMC_la_DEPENDENCIES) $(LINK) $(am_libIntelXvMC_la_rpath) $(libIntelXvMC_la_LDFLAGS) $(libIntelXvMC_la_OBJECTS) $(libIntelXvMC_la_LIBADD) $(LIBS) @@ -351,13 +320,12 @@ mostlyclean-compile: distclean-compile: -rm -f *.tab.c -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libI810XvMC_la-I810XvMC.Plo@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libIntelXvMC_la-i915_xvmc.Plo@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libIntelXvMC_la-i965_xvmc.Plo@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libIntelXvMC_la-intel_batchbuffer.Plo@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libIntelXvMC_la-intel_xvmc.Plo@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libIntelXvMC_la-intel_xvmc_dump.Plo@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libIntelXvMC_la-xvmc_vld.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i915_xvmc.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i965_xvmc.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/intel_batchbuffer.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/intel_xvmc.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/intel_xvmc_dump.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/xvmc_vld.Plo@am__quote@ .c.o: @am__fastdepCC_TRUE@ if $(COMPILE) -MT $@ -MD -MP -MF "$(DEPDIR)/$*.Tpo" -c -o $@ $<; \ @@ -380,55 +348,6 @@ distclean-compile: @AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ @am__fastdepCC_FALSE@ $(LTCOMPILE) -c -o $@ $< -libI810XvMC_la-I810XvMC.lo: I810XvMC.c -@am__fastdepCC_TRUE@ if $(LIBTOOL) --tag=CC --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(libI810XvMC_la_CFLAGS) $(CFLAGS) -MT libI810XvMC_la-I810XvMC.lo -MD -MP -MF "$(DEPDIR)/libI810XvMC_la-I810XvMC.Tpo" -c -o libI810XvMC_la-I810XvMC.lo `test -f 'I810XvMC.c' || echo '$(srcdir)/'`I810XvMC.c; \ -@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/libI810XvMC_la-I810XvMC.Tpo" "$(DEPDIR)/libI810XvMC_la-I810XvMC.Plo"; else rm -f "$(DEPDIR)/libI810XvMC_la-I810XvMC.Tpo"; exit 1; fi -@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='I810XvMC.c' object='libI810XvMC_la-I810XvMC.lo' libtool=yes @AMDEPBACKSLASH@ -@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ -@am__fastdepCC_FALSE@ $(LIBTOOL) --tag=CC --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(libI810XvMC_la_CFLAGS) $(CFLAGS) -c -o libI810XvMC_la-I810XvMC.lo `test -f 'I810XvMC.c' || echo '$(srcdir)/'`I810XvMC.c - -libIntelXvMC_la-intel_xvmc.lo: intel_xvmc.c -@am__fastdepCC_TRUE@ if $(LIBTOOL) --tag=CC --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(libIntelXvMC_la_CFLAGS) $(CFLAGS) -MT libIntelXvMC_la-intel_xvmc.lo -MD -MP -MF "$(DEPDIR)/libIntelXvMC_la-intel_xvmc.Tpo" -c -o libIntelXvMC_la-intel_xvmc.lo `test -f 'intel_xvmc.c' || echo '$(srcdir)/'`intel_xvmc.c; \ -@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/libIntelXvMC_la-intel_xvmc.Tpo" "$(DEPDIR)/libIntelXvMC_la-intel_xvmc.Plo"; else rm -f "$(DEPDIR)/libIntelXvMC_la-intel_xvmc.Tpo"; exit 1; fi -@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='intel_xvmc.c' object='libIntelXvMC_la-intel_xvmc.lo' libtool=yes @AMDEPBACKSLASH@ -@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ -@am__fastdepCC_FALSE@ $(LIBTOOL) --tag=CC --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(libIntelXvMC_la_CFLAGS) $(CFLAGS) -c -o libIntelXvMC_la-intel_xvmc.lo `test -f 'intel_xvmc.c' || echo '$(srcdir)/'`intel_xvmc.c - -libIntelXvMC_la-intel_xvmc_dump.lo: intel_xvmc_dump.c -@am__fastdepCC_TRUE@ if $(LIBTOOL) --tag=CC --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(libIntelXvMC_la_CFLAGS) $(CFLAGS) -MT libIntelXvMC_la-intel_xvmc_dump.lo -MD -MP -MF "$(DEPDIR)/libIntelXvMC_la-intel_xvmc_dump.Tpo" -c -o libIntelXvMC_la-intel_xvmc_dump.lo `test -f 'intel_xvmc_dump.c' || echo '$(srcdir)/'`intel_xvmc_dump.c; \ -@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/libIntelXvMC_la-intel_xvmc_dump.Tpo" "$(DEPDIR)/libIntelXvMC_la-intel_xvmc_dump.Plo"; else rm -f "$(DEPDIR)/libIntelXvMC_la-intel_xvmc_dump.Tpo"; exit 1; fi -@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='intel_xvmc_dump.c' object='libIntelXvMC_la-intel_xvmc_dump.lo' libtool=yes @AMDEPBACKSLASH@ -@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ -@am__fastdepCC_FALSE@ $(LIBTOOL) --tag=CC --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(libIntelXvMC_la_CFLAGS) $(CFLAGS) -c -o libIntelXvMC_la-intel_xvmc_dump.lo `test -f 'intel_xvmc_dump.c' || echo '$(srcdir)/'`intel_xvmc_dump.c - -libIntelXvMC_la-i915_xvmc.lo: i915_xvmc.c -@am__fastdepCC_TRUE@ if $(LIBTOOL) --tag=CC --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(libIntelXvMC_la_CFLAGS) $(CFLAGS) -MT libIntelXvMC_la-i915_xvmc.lo -MD -MP -MF "$(DEPDIR)/libIntelXvMC_la-i915_xvmc.Tpo" -c -o libIntelXvMC_la-i915_xvmc.lo `test -f 'i915_xvmc.c' || echo '$(srcdir)/'`i915_xvmc.c; \ -@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/libIntelXvMC_la-i915_xvmc.Tpo" "$(DEPDIR)/libIntelXvMC_la-i915_xvmc.Plo"; else rm -f "$(DEPDIR)/libIntelXvMC_la-i915_xvmc.Tpo"; exit 1; fi -@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='i915_xvmc.c' object='libIntelXvMC_la-i915_xvmc.lo' libtool=yes @AMDEPBACKSLASH@ -@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ -@am__fastdepCC_FALSE@ $(LIBTOOL) --tag=CC --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(libIntelXvMC_la_CFLAGS) $(CFLAGS) -c -o libIntelXvMC_la-i915_xvmc.lo `test -f 'i915_xvmc.c' || echo '$(srcdir)/'`i915_xvmc.c - -libIntelXvMC_la-i965_xvmc.lo: i965_xvmc.c -@am__fastdepCC_TRUE@ if $(LIBTOOL) --tag=CC --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(libIntelXvMC_la_CFLAGS) $(CFLAGS) -MT libIntelXvMC_la-i965_xvmc.lo -MD -MP -MF "$(DEPDIR)/libIntelXvMC_la-i965_xvmc.Tpo" -c -o libIntelXvMC_la-i965_xvmc.lo `test -f 'i965_xvmc.c' || echo '$(srcdir)/'`i965_xvmc.c; \ -@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/libIntelXvMC_la-i965_xvmc.Tpo" "$(DEPDIR)/libIntelXvMC_la-i965_xvmc.Plo"; else rm -f "$(DEPDIR)/libIntelXvMC_la-i965_xvmc.Tpo"; exit 1; fi -@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='i965_xvmc.c' object='libIntelXvMC_la-i965_xvmc.lo' libtool=yes @AMDEPBACKSLASH@ -@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ -@am__fastdepCC_FALSE@ $(LIBTOOL) --tag=CC --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(libIntelXvMC_la_CFLAGS) $(CFLAGS) -c -o libIntelXvMC_la-i965_xvmc.lo `test -f 'i965_xvmc.c' || echo '$(srcdir)/'`i965_xvmc.c - -libIntelXvMC_la-xvmc_vld.lo: xvmc_vld.c -@am__fastdepCC_TRUE@ if $(LIBTOOL) --tag=CC --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(libIntelXvMC_la_CFLAGS) $(CFLAGS) -MT libIntelXvMC_la-xvmc_vld.lo -MD -MP -MF "$(DEPDIR)/libIntelXvMC_la-xvmc_vld.Tpo" -c -o libIntelXvMC_la-xvmc_vld.lo `test -f 'xvmc_vld.c' || echo '$(srcdir)/'`xvmc_vld.c; \ -@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/libIntelXvMC_la-xvmc_vld.Tpo" "$(DEPDIR)/libIntelXvMC_la-xvmc_vld.Plo"; else rm -f "$(DEPDIR)/libIntelXvMC_la-xvmc_vld.Tpo"; exit 1; fi -@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='xvmc_vld.c' object='libIntelXvMC_la-xvmc_vld.lo' libtool=yes @AMDEPBACKSLASH@ -@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ -@am__fastdepCC_FALSE@ $(LIBTOOL) --tag=CC --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(libIntelXvMC_la_CFLAGS) $(CFLAGS) -c -o libIntelXvMC_la-xvmc_vld.lo `test -f 'xvmc_vld.c' || echo '$(srcdir)/'`xvmc_vld.c - -libIntelXvMC_la-intel_batchbuffer.lo: intel_batchbuffer.c -@am__fastdepCC_TRUE@ if $(LIBTOOL) --tag=CC --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(libIntelXvMC_la_CFLAGS) $(CFLAGS) -MT libIntelXvMC_la-intel_batchbuffer.lo -MD -MP -MF "$(DEPDIR)/libIntelXvMC_la-intel_batchbuffer.Tpo" -c -o libIntelXvMC_la-intel_batchbuffer.lo `test -f 'intel_batchbuffer.c' || echo '$(srcdir)/'`intel_batchbuffer.c; \ -@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/libIntelXvMC_la-intel_batchbuffer.Tpo" "$(DEPDIR)/libIntelXvMC_la-intel_batchbuffer.Plo"; else rm -f "$(DEPDIR)/libIntelXvMC_la-intel_batchbuffer.Tpo"; exit 1; fi -@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='intel_batchbuffer.c' object='libIntelXvMC_la-intel_batchbuffer.lo' libtool=yes @AMDEPBACKSLASH@ -@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ -@am__fastdepCC_FALSE@ $(LIBTOOL) --tag=CC --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(libIntelXvMC_la_CFLAGS) $(CFLAGS) -c -o libIntelXvMC_la-intel_batchbuffer.lo `test -f 'intel_batchbuffer.c' || echo '$(srcdir)/'`intel_batchbuffer.c - mostlyclean-libtool: -rm -f *.lo diff --git a/driver/xf86-video-intel/src/xvmc/i915_xvmc.c b/driver/xf86-video-intel/src/xvmc/i915_xvmc.c index 9ad8d01a3..fbd4555e8 100644 --- a/driver/xf86-video-intel/src/xvmc/i915_xvmc.c +++ b/driver/xf86-video-intel/src/xvmc/i915_xvmc.c @@ -31,7 +31,9 @@ #include "i915_structs.h" #include "i915_program.h" -#define STRIDE(w) (((w) + 0x3ff) & ~0x3ff) +#define ALIGN(i,m) (((i) + (m) - 1) & ~((m) - 1)) + +#define STRIDE(w) (ALIGN((w), 1024)) #define SIZE_Y420(w, h) (h * STRIDE(w)) #define SIZE_UV420(w, h) ((h >> 1) * STRIDE(w >> 1)) #define SIZE_YUV420(w, h) (SIZE_Y420(w,h) + SIZE_UV420(w,h) * 2) @@ -389,7 +391,6 @@ static void i915_mc_static_indirect_state_set(XvMCContext * context, i915XvMCContext *pI915XvMC = (i915XvMCContext *) context->privData; struct intel_xvmc_surface *intel_surf = dest->privData; struct i915_mc_static_indirect_state_buffer *buffer_info; - unsigned int w = dest->width; drm_intel_gem_bo_map_gtt(pI915XvMC->sis_bo); buffer_info = pI915XvMC->sis_bo->virtual; @@ -686,7 +687,7 @@ static void i915_mc_load_indirect_render_emit(XvMCContext * context) { i915XvMCContext *pI915XvMC = (i915XvMCContext *) context->privData; int mem_select; - uint32_t load_indirect, buffer_address; + uint32_t load_indirect; BATCH_LOCALS; BEGIN_BATCH(5); diff --git a/driver/xf86-video-intel/src/xvmc/i915_xvmc.h b/driver/xf86-video-intel/src/xvmc/i915_xvmc.h index 96dd3ce8c..852e3eabf 100644 --- a/driver/xf86-video-intel/src/xvmc/i915_xvmc.h +++ b/driver/xf86-video-intel/src/xvmc/i915_xvmc.h @@ -29,7 +29,7 @@ #define _I915XVMC_H #include "intel_xvmc.h" -#include "i830_hwmc.h" +#include "intel_hwmc.h" #define I915_SUBPIC_PALETTE_SIZE 16 #define MAX_SUBCONTEXT_LEN 1024 diff --git a/driver/xf86-video-intel/src/xvmc/i965_xvmc.c b/driver/xf86-video-intel/src/xvmc/i965_xvmc.c index 52b93e327..210cf7316 100644 --- a/driver/xf86-video-intel/src/xvmc/i965_xvmc.c +++ b/driver/xf86-video-intel/src/xvmc/i965_xvmc.c @@ -25,11 +25,12 @@ * */ #include "intel_xvmc.h" -#include "i810_reg.h" +#include "i830_reg.h" +#include "i965_reg.h" #include "brw_defines.h" #include "brw_structs.h" #include "intel_batchbuffer.h" -#include "i830_hwmc.h" +#include "intel_hwmc.h" #define BATCH_STRUCT(x) intelBatchbufferData(&x, sizeof(x), 0) #define URB_SIZE 256 /* XXX */ diff --git a/driver/xf86-video-intel/src/xvmc/intel_batchbuffer.c b/driver/xf86-video-intel/src/xvmc/intel_batchbuffer.c index 873cd4ac7..2b5526c50 100644 --- a/driver/xf86-video-intel/src/xvmc/intel_batchbuffer.c +++ b/driver/xf86-video-intel/src/xvmc/intel_batchbuffer.c @@ -49,41 +49,6 @@ #include "brw_structs.h" #define MI_BATCH_BUFFER_END (0xA << 23) #define BATCH_SIZE 8*1024 /* one bo is allocated each time, so the size can be small */ -static int intelEmitIrqLocked(void) -{ - drmI830IrqEmit ie; - int ret, seq; - - ie.irq_seq = &seq; - ret = drmCommandWriteRead(xvmc_driver->fd, DRM_I830_IRQ_EMIT, - &ie, sizeof(ie)); - - if (ret) { - fprintf(stderr, "%s: drmI830IrqEmit: %d\n", __FUNCTION__, ret); - exit(1); - } - - return seq; -} - -static void intelWaitIrq(int seq) -{ - int ret; - drmI830IrqWait iw; - - iw.irq_seq = seq; - - do { - ret = - drmCommandWrite(xvmc_driver->fd, DRM_I830_IRQ_WAIT, &iw, - sizeof(iw)); - } while (ret == -EAGAIN || ret == -EINTR); - - if (ret) { - fprintf(stderr, "%s: drmI830IrqWait: %d\n", __FUNCTION__, ret); - exit(1); - } -} static void i965_end_batch(void) { @@ -99,8 +64,6 @@ static void i965_end_batch(void) Bool intelInitBatchBuffer(void) { - int i; - if ((xvmc_driver->batch.buf = drm_intel_bo_alloc(xvmc_driver->bufmgr, "batch buffer", BATCH_SIZE, 0x1000)) == NULL) { diff --git a/driver/xf86-video-intel/src/xvmc/intel_batchbuffer.h b/driver/xf86-video-intel/src/xvmc/intel_batchbuffer.h index 6fa1c05b3..888abeb15 100644 --- a/driver/xf86-video-intel/src/xvmc/intel_batchbuffer.h +++ b/driver/xf86-video-intel/src/xvmc/intel_batchbuffer.h @@ -24,7 +24,7 @@ extern int VERBOSE; #define OUT_RELOC(bo,read_domains,write_domains,delta) \ do { \ - *(unsigned int *)batch_ptr = delta + bo->offset; \ + *(unsigned int *)batch_ptr = (delta) + bo->offset; \ intel_batch_emit_reloc(bo, read_domains, write_domains, delta, batch_ptr); \ batch_ptr += 4; \ } while (0) diff --git a/driver/xf86-video-intel/src/xvmc/intel_xvmc.c b/driver/xf86-video-intel/src/xvmc/intel_xvmc.c index 6cbec8076..1b969457b 100644 --- a/driver/xf86-video-intel/src/xvmc/intel_xvmc.c +++ b/driver/xf86-video-intel/src/xvmc/intel_xvmc.c @@ -105,8 +105,6 @@ unsigned int mb_bytes_420[] = { void LOCK_HARDWARE(drm_context_t ctx) { - char __ret = 0; - PPTHREAD_MUTEX_LOCK(); assert(!xvmc_driver->locked); @@ -218,11 +216,6 @@ _X_EXPORT Status XvMCCreateContext(Display * display, XvPortID port, int error_base; int event_base; int priv_count; - int isCapable; - int screen = DefaultScreen(display); - intel_xvmc_context_ptr intel_ctx; - int fd; - char *driverName = NULL, *deviceName = NULL; /* Verify Obvious things first */ if (!display || !context) @@ -482,7 +475,6 @@ _X_EXPORT Status XvMCCreateBlocks(Display * display, XvMCContext * context, unsigned int num_blocks, XvMCBlockArray * block) { - Status ret; if (!display || !context || !num_blocks || !block) return BadValue; @@ -505,7 +497,6 @@ _X_EXPORT Status XvMCCreateBlocks(Display * display, XvMCContext * context, */ _X_EXPORT Status XvMCDestroyBlocks(Display * display, XvMCBlockArray * block) { - Status ret; if (!display || !block) return BadValue; @@ -678,13 +669,10 @@ _X_EXPORT Status XvMCPutSurface(Display * display, XvMCSurface * surface, */ _X_EXPORT Status XvMCSyncSurface(Display * display, XvMCSurface * surface) { - Status ret; - int stat = 0; - if (!display || !surface) return XvMCBadSurface; - return ret; + return Success; } /* @@ -739,9 +727,6 @@ _X_EXPORT Status XvMCGetSurfaceStatus(Display * display, XvMCSurface * surface, */ _X_EXPORT Status XvMCHideSurface(Display * display, XvMCSurface * surface) { - int stat = 0; - Status ret; - if (!display || !surface) return XvMCBadSurface; @@ -1071,7 +1056,7 @@ _X_EXPORT Status XvMCLoadQMatrix(Display * display, XvMCContext * context, _X_EXPORT Status XvMCPutSlice(Display * display, XvMCContext * context, char *slice, int nbytes) { - if (xvmc_driver->put_slice(display, context, slice, nbytes)) { + if (xvmc_driver->put_slice(display, context, (unsigned char *) slice, nbytes)) { XVMC_ERR("PutSlice fail\n"); return BadValue; } @@ -1082,7 +1067,7 @@ _X_EXPORT Status XvMCPutSlice2(Display * display, XvMCContext * context, char *slice, int nbytes, int slice_code) { if (xvmc_driver->put_slice2 - (display, context, slice, nbytes, slice_code)) { + (display, context, (unsigned char *) slice, nbytes, slice_code)) { XVMC_ERR("PutSlice2 fail\n"); return BadValue; } diff --git a/driver/xf86-video-intel/src/xvmc/intel_xvmc.h b/driver/xf86-video-intel/src/xvmc/intel_xvmc.h index 90b623594..7fdfd0628 100644 --- a/driver/xf86-video-intel/src/xvmc/intel_xvmc.h +++ b/driver/xf86-video-intel/src/xvmc/intel_xvmc.h @@ -41,8 +41,7 @@ #include <stdint.h> #include <xf86drm.h> -#include "i830_common.h" -#include "i830_hwmc.h" +#include "intel_hwmc.h" #include <X11/X.h> #include <X11/Xlibint.h> #include <X11/Xutil.h> diff --git a/driver/xf86-video-intel/src/xvmc/intel_xvmc_dump.c b/driver/xf86-video-intel/src/xvmc/intel_xvmc_dump.c index 974bcbb0a..d22d311a4 100644 --- a/driver/xf86-video-intel/src/xvmc/intel_xvmc_dump.c +++ b/driver/xf86-video-intel/src/xvmc/intel_xvmc_dump.c @@ -38,7 +38,7 @@ void intel_xvmc_dump_open(void) if (xvmc_dump) return; - if (d = getenv("INTEL_XVMC_DUMP")) + if ((d = getenv("INTEL_XVMC_DUMP"))) xvmc_dump = 1; if (xvmc_dump) { diff --git a/driver/xf86-video-intel/src/xvmc/shader/Makefile.in b/driver/xf86-video-intel/src/xvmc/shader/Makefile.in index 0a8aca009..e057d6b6f 100644 --- a/driver/xf86-video-intel/src/xvmc/shader/Makefile.in +++ b/driver/xf86-video-intel/src/xvmc/shader/Makefile.in @@ -70,10 +70,6 @@ AUTOCONF = @AUTOCONF@ AUTOHEADER = @AUTOHEADER@ AUTOMAKE = @AUTOMAKE@ AWK = @AWK@ -BUILD_LINUXDOC_FALSE = @BUILD_LINUXDOC_FALSE@ -BUILD_LINUXDOC_TRUE = @BUILD_LINUXDOC_TRUE@ -BUILD_PDFDOC_FALSE = @BUILD_PDFDOC_FALSE@ -BUILD_PDFDOC_TRUE = @BUILD_PDFDOC_TRUE@ CC = @CC@ CCDEPMODE = @CCDEPMODE@ CFLAGS = @CFLAGS@ @@ -113,8 +109,6 @@ GEN4ASM_LIBS = @GEN4ASM_LIBS@ GREP = @GREP@ HAVE_GEN4ASM_FALSE = @HAVE_GEN4ASM_FALSE@ HAVE_GEN4ASM_TRUE = @HAVE_GEN4ASM_TRUE@ -HAVE_XEXTPROTO_71_FALSE = @HAVE_XEXTPROTO_71_FALSE@ -HAVE_XEXTPROTO_71_TRUE = @HAVE_XEXTPROTO_71_TRUE@ INSTALL_CMD = @INSTALL_CMD@ INSTALL_DATA = @INSTALL_DATA@ INSTALL_PROGRAM = @INSTALL_PROGRAM@ @@ -128,17 +122,13 @@ LIBS = @LIBS@ LIBTOOL = @LIBTOOL@ LIB_MAN_DIR = @LIB_MAN_DIR@ LIB_MAN_SUFFIX = @LIB_MAN_SUFFIX@ -LINUXDOC = @LINUXDOC@ LN_S = @LN_S@ LTLIBOBJS = @LTLIBOBJS@ MAINT = @MAINT@ MAINTAINER_MODE_FALSE = @MAINTAINER_MODE_FALSE@ MAINTAINER_MODE_TRUE = @MAINTAINER_MODE_TRUE@ MAKEINFO = @MAKEINFO@ -MAKE_HTML = @MAKE_HTML@ -MAKE_PDF = @MAKE_PDF@ -MAKE_PS = @MAKE_PS@ -MAKE_TEXT = @MAKE_TEXT@ +MAN_SUBSTS = @MAN_SUBSTS@ MISC_MAN_DIR = @MISC_MAN_DIR@ MISC_MAN_SUFFIX = @MISC_MAN_SUFFIX@ NMEDIT = @NMEDIT@ @@ -153,19 +143,15 @@ PATH_SEPARATOR = @PATH_SEPARATOR@ PCIACCESS_CFLAGS = @PCIACCESS_CFLAGS@ PCIACCESS_LIBS = @PCIACCESS_LIBS@ PKG_CONFIG = @PKG_CONFIG@ -PS2PDF = @PS2PDF@ RANLIB = @RANLIB@ SED = @SED@ SET_MAKE = @SET_MAKE@ SHELL = @SHELL@ STRIP = @STRIP@ VERSION = @VERSION@ -VIDEO_DEBUG_FALSE = @VIDEO_DEBUG_FALSE@ -VIDEO_DEBUG_TRUE = @VIDEO_DEBUG_TRUE@ -XEXT_CFLAGS = @XEXT_CFLAGS@ -XEXT_LIBS = @XEXT_LIBS@ XORG_CFLAGS = @XORG_CFLAGS@ XORG_LIBS = @XORG_LIBS@ +XORG_MAN_PAGE = @XORG_MAN_PAGE@ XVMCLIB_CFLAGS = @XVMCLIB_CFLAGS@ XVMCLIB_LIBS = @XVMCLIB_LIBS@ XVMC_FALSE = @XVMC_FALSE@ diff --git a/driver/xf86-video-intel/src/xvmc/shader/mc/Makefile.in b/driver/xf86-video-intel/src/xvmc/shader/mc/Makefile.in index 6e958f97d..f40933917 100644 --- a/driver/xf86-video-intel/src/xvmc/shader/mc/Makefile.in +++ b/driver/xf86-video-intel/src/xvmc/shader/mc/Makefile.in @@ -61,10 +61,6 @@ AUTOCONF = @AUTOCONF@ AUTOHEADER = @AUTOHEADER@ AUTOMAKE = @AUTOMAKE@ AWK = @AWK@ -BUILD_LINUXDOC_FALSE = @BUILD_LINUXDOC_FALSE@ -BUILD_LINUXDOC_TRUE = @BUILD_LINUXDOC_TRUE@ -BUILD_PDFDOC_FALSE = @BUILD_PDFDOC_FALSE@ -BUILD_PDFDOC_TRUE = @BUILD_PDFDOC_TRUE@ CC = @CC@ CCDEPMODE = @CCDEPMODE@ CFLAGS = @CFLAGS@ @@ -104,8 +100,6 @@ GEN4ASM_LIBS = @GEN4ASM_LIBS@ GREP = @GREP@ HAVE_GEN4ASM_FALSE = @HAVE_GEN4ASM_FALSE@ HAVE_GEN4ASM_TRUE = @HAVE_GEN4ASM_TRUE@ -HAVE_XEXTPROTO_71_FALSE = @HAVE_XEXTPROTO_71_FALSE@ -HAVE_XEXTPROTO_71_TRUE = @HAVE_XEXTPROTO_71_TRUE@ INSTALL_CMD = @INSTALL_CMD@ INSTALL_DATA = @INSTALL_DATA@ INSTALL_PROGRAM = @INSTALL_PROGRAM@ @@ -119,17 +113,13 @@ LIBS = @LIBS@ LIBTOOL = @LIBTOOL@ LIB_MAN_DIR = @LIB_MAN_DIR@ LIB_MAN_SUFFIX = @LIB_MAN_SUFFIX@ -LINUXDOC = @LINUXDOC@ LN_S = @LN_S@ LTLIBOBJS = @LTLIBOBJS@ MAINT = @MAINT@ MAINTAINER_MODE_FALSE = @MAINTAINER_MODE_FALSE@ MAINTAINER_MODE_TRUE = @MAINTAINER_MODE_TRUE@ MAKEINFO = @MAKEINFO@ -MAKE_HTML = @MAKE_HTML@ -MAKE_PDF = @MAKE_PDF@ -MAKE_PS = @MAKE_PS@ -MAKE_TEXT = @MAKE_TEXT@ +MAN_SUBSTS = @MAN_SUBSTS@ MISC_MAN_DIR = @MISC_MAN_DIR@ MISC_MAN_SUFFIX = @MISC_MAN_SUFFIX@ NMEDIT = @NMEDIT@ @@ -144,19 +134,15 @@ PATH_SEPARATOR = @PATH_SEPARATOR@ PCIACCESS_CFLAGS = @PCIACCESS_CFLAGS@ PCIACCESS_LIBS = @PCIACCESS_LIBS@ PKG_CONFIG = @PKG_CONFIG@ -PS2PDF = @PS2PDF@ RANLIB = @RANLIB@ SED = @SED@ SET_MAKE = @SET_MAKE@ SHELL = @SHELL@ STRIP = @STRIP@ VERSION = @VERSION@ -VIDEO_DEBUG_FALSE = @VIDEO_DEBUG_FALSE@ -VIDEO_DEBUG_TRUE = @VIDEO_DEBUG_TRUE@ -XEXT_CFLAGS = @XEXT_CFLAGS@ -XEXT_LIBS = @XEXT_LIBS@ XORG_CFLAGS = @XORG_CFLAGS@ XORG_LIBS = @XORG_LIBS@ +XORG_MAN_PAGE = @XORG_MAN_PAGE@ XVMCLIB_CFLAGS = @XVMCLIB_CFLAGS@ XVMCLIB_LIBS = @XVMCLIB_LIBS@ XVMC_FALSE = @XVMC_FALSE@ diff --git a/driver/xf86-video-intel/src/xvmc/shader/vld/Makefile.in b/driver/xf86-video-intel/src/xvmc/shader/vld/Makefile.in index 8cf7664b6..bf8e1b07a 100644 --- a/driver/xf86-video-intel/src/xvmc/shader/vld/Makefile.in +++ b/driver/xf86-video-intel/src/xvmc/shader/vld/Makefile.in @@ -61,10 +61,6 @@ AUTOCONF = @AUTOCONF@ AUTOHEADER = @AUTOHEADER@ AUTOMAKE = @AUTOMAKE@ AWK = @AWK@ -BUILD_LINUXDOC_FALSE = @BUILD_LINUXDOC_FALSE@ -BUILD_LINUXDOC_TRUE = @BUILD_LINUXDOC_TRUE@ -BUILD_PDFDOC_FALSE = @BUILD_PDFDOC_FALSE@ -BUILD_PDFDOC_TRUE = @BUILD_PDFDOC_TRUE@ CC = @CC@ CCDEPMODE = @CCDEPMODE@ CFLAGS = @CFLAGS@ @@ -104,8 +100,6 @@ GEN4ASM_LIBS = @GEN4ASM_LIBS@ GREP = @GREP@ HAVE_GEN4ASM_FALSE = @HAVE_GEN4ASM_FALSE@ HAVE_GEN4ASM_TRUE = @HAVE_GEN4ASM_TRUE@ -HAVE_XEXTPROTO_71_FALSE = @HAVE_XEXTPROTO_71_FALSE@ -HAVE_XEXTPROTO_71_TRUE = @HAVE_XEXTPROTO_71_TRUE@ INSTALL_CMD = @INSTALL_CMD@ INSTALL_DATA = @INSTALL_DATA@ INSTALL_PROGRAM = @INSTALL_PROGRAM@ @@ -119,17 +113,13 @@ LIBS = @LIBS@ LIBTOOL = @LIBTOOL@ LIB_MAN_DIR = @LIB_MAN_DIR@ LIB_MAN_SUFFIX = @LIB_MAN_SUFFIX@ -LINUXDOC = @LINUXDOC@ LN_S = @LN_S@ LTLIBOBJS = @LTLIBOBJS@ MAINT = @MAINT@ MAINTAINER_MODE_FALSE = @MAINTAINER_MODE_FALSE@ MAINTAINER_MODE_TRUE = @MAINTAINER_MODE_TRUE@ MAKEINFO = @MAKEINFO@ -MAKE_HTML = @MAKE_HTML@ -MAKE_PDF = @MAKE_PDF@ -MAKE_PS = @MAKE_PS@ -MAKE_TEXT = @MAKE_TEXT@ +MAN_SUBSTS = @MAN_SUBSTS@ MISC_MAN_DIR = @MISC_MAN_DIR@ MISC_MAN_SUFFIX = @MISC_MAN_SUFFIX@ NMEDIT = @NMEDIT@ @@ -144,19 +134,15 @@ PATH_SEPARATOR = @PATH_SEPARATOR@ PCIACCESS_CFLAGS = @PCIACCESS_CFLAGS@ PCIACCESS_LIBS = @PCIACCESS_LIBS@ PKG_CONFIG = @PKG_CONFIG@ -PS2PDF = @PS2PDF@ RANLIB = @RANLIB@ SED = @SED@ SET_MAKE = @SET_MAKE@ SHELL = @SHELL@ STRIP = @STRIP@ VERSION = @VERSION@ -VIDEO_DEBUG_FALSE = @VIDEO_DEBUG_FALSE@ -VIDEO_DEBUG_TRUE = @VIDEO_DEBUG_TRUE@ -XEXT_CFLAGS = @XEXT_CFLAGS@ -XEXT_LIBS = @XEXT_LIBS@ XORG_CFLAGS = @XORG_CFLAGS@ XORG_LIBS = @XORG_LIBS@ +XORG_MAN_PAGE = @XORG_MAN_PAGE@ XVMCLIB_CFLAGS = @XVMCLIB_CFLAGS@ XVMCLIB_LIBS = @XVMCLIB_LIBS@ XVMC_FALSE = @XVMC_FALSE@ diff --git a/driver/xf86-video-intel/src/xvmc/xvmc_vld.c b/driver/xf86-video-intel/src/xvmc/xvmc_vld.c index 9ef840b36..d72e105b0 100644 --- a/driver/xf86-video-intel/src/xvmc/xvmc_vld.c +++ b/driver/xf86-video-intel/src/xvmc/xvmc_vld.c @@ -24,8 +24,9 @@ * Zou Nan hai <nanhai.zou@intel.com> */ #include "intel_xvmc.h" -#include "i830_hwmc.h" -#include "i810_reg.h" +#include "intel_hwmc.h" +#include "i830_reg.h" +#include "i965_reg.h" #include "brw_defines.h" #include "brw_structs.h" @@ -784,7 +785,6 @@ static Status begin_surface(Display * display, XvMCContext * context, XvMCSurface * future, const XvMCMpegControl * control) { - struct i965_xvmc_contex *i965_ctx; struct intel_xvmc_surface *priv_target, *priv_past, *priv_future; intel_xvmc_context_ptr intel_ctx = context->privData; Status ret; diff --git a/driver/xf86-video-intel/uxa/Makefile.in b/driver/xf86-video-intel/uxa/Makefile.in index b50b9cb3f..16f2b4c8a 100644 --- a/driver/xf86-video-intel/uxa/Makefile.in +++ b/driver/xf86-video-intel/uxa/Makefile.in @@ -80,10 +80,6 @@ AUTOCONF = @AUTOCONF@ AUTOHEADER = @AUTOHEADER@ AUTOMAKE = @AUTOMAKE@ AWK = @AWK@ -BUILD_LINUXDOC_FALSE = @BUILD_LINUXDOC_FALSE@ -BUILD_LINUXDOC_TRUE = @BUILD_LINUXDOC_TRUE@ -BUILD_PDFDOC_FALSE = @BUILD_PDFDOC_FALSE@ -BUILD_PDFDOC_TRUE = @BUILD_PDFDOC_TRUE@ CC = @CC@ CCDEPMODE = @CCDEPMODE@ CFLAGS = @CFLAGS@ @@ -123,8 +119,6 @@ GEN4ASM_LIBS = @GEN4ASM_LIBS@ GREP = @GREP@ HAVE_GEN4ASM_FALSE = @HAVE_GEN4ASM_FALSE@ HAVE_GEN4ASM_TRUE = @HAVE_GEN4ASM_TRUE@ -HAVE_XEXTPROTO_71_FALSE = @HAVE_XEXTPROTO_71_FALSE@ -HAVE_XEXTPROTO_71_TRUE = @HAVE_XEXTPROTO_71_TRUE@ INSTALL_CMD = @INSTALL_CMD@ INSTALL_DATA = @INSTALL_DATA@ INSTALL_PROGRAM = @INSTALL_PROGRAM@ @@ -138,17 +132,13 @@ LIBS = @LIBS@ LIBTOOL = @LIBTOOL@ LIB_MAN_DIR = @LIB_MAN_DIR@ LIB_MAN_SUFFIX = @LIB_MAN_SUFFIX@ -LINUXDOC = @LINUXDOC@ LN_S = @LN_S@ LTLIBOBJS = @LTLIBOBJS@ MAINT = @MAINT@ MAINTAINER_MODE_FALSE = @MAINTAINER_MODE_FALSE@ MAINTAINER_MODE_TRUE = @MAINTAINER_MODE_TRUE@ MAKEINFO = @MAKEINFO@ -MAKE_HTML = @MAKE_HTML@ -MAKE_PDF = @MAKE_PDF@ -MAKE_PS = @MAKE_PS@ -MAKE_TEXT = @MAKE_TEXT@ +MAN_SUBSTS = @MAN_SUBSTS@ MISC_MAN_DIR = @MISC_MAN_DIR@ MISC_MAN_SUFFIX = @MISC_MAN_SUFFIX@ NMEDIT = @NMEDIT@ @@ -163,19 +153,15 @@ PATH_SEPARATOR = @PATH_SEPARATOR@ PCIACCESS_CFLAGS = @PCIACCESS_CFLAGS@ PCIACCESS_LIBS = @PCIACCESS_LIBS@ PKG_CONFIG = @PKG_CONFIG@ -PS2PDF = @PS2PDF@ RANLIB = @RANLIB@ SED = @SED@ SET_MAKE = @SET_MAKE@ SHELL = @SHELL@ STRIP = @STRIP@ VERSION = @VERSION@ -VIDEO_DEBUG_FALSE = @VIDEO_DEBUG_FALSE@ -VIDEO_DEBUG_TRUE = @VIDEO_DEBUG_TRUE@ -XEXT_CFLAGS = @XEXT_CFLAGS@ -XEXT_LIBS = @XEXT_LIBS@ XORG_CFLAGS = @XORG_CFLAGS@ XORG_LIBS = @XORG_LIBS@ +XORG_MAN_PAGE = @XORG_MAN_PAGE@ XVMCLIB_CFLAGS = @XVMCLIB_CFLAGS@ XVMCLIB_LIBS = @XVMCLIB_LIBS@ XVMC_FALSE = @XVMC_FALSE@ diff --git a/driver/xf86-video-intel/uxa/uxa-accel.c b/driver/xf86-video-intel/uxa/uxa-accel.c index 245738a65..301af2f4d 100644 --- a/driver/xf86-video-intel/uxa/uxa-accel.c +++ b/driver/xf86-video-intel/uxa/uxa-accel.c @@ -1,3 +1,4 @@ + /* * Copyright ® 2001 Keith Packard * @@ -36,24 +37,6 @@ #include "uxa.h" #include "mipict.h" -static CARD32 -format_for_depth(int depth) -{ - switch (depth) { - case 1: return PICT_a1; - case 4: return PICT_a4; - case 8: return PICT_a8; - case 15: return PICT_x1r5g5b5; - case 16: return PICT_r5g6b5; - default: - case 24: return PICT_x8r8g8b8; -#if 0 - case 30: return PICT_x2r10g10b10; -#endif - case 32: return PICT_a8r8g8b8; - } -} - static void uxa_fill_spans(DrawablePtr pDrawable, GCPtr pGC, int n, DDXPointPtr ppt, int *pwidth, int fSorted) @@ -61,19 +44,13 @@ uxa_fill_spans(DrawablePtr pDrawable, GCPtr pGC, int n, ScreenPtr screen = pDrawable->pScreen; uxa_screen_t *uxa_screen = uxa_get_screen(screen); RegionPtr pClip = fbGetCompositeClip(pGC); - PixmapPtr dst_pixmap, src_pixmap = NULL; - BoxPtr pextent, pbox; + PixmapPtr dst_pixmap; + BoxPtr pbox; int nbox; - int extentX1, extentX2, extentY1, extentY2; - int fullX1, fullX2, fullY1; - int partX1, partX2; + int x1, x2, y; int off_x, off_y; - xRenderColor color; - PictFormatPtr format; - PicturePtr dst, src; - int error; - if (uxa_screen->swappedOut) + if (uxa_screen->swappedOut || uxa_screen->force_fallback) goto fallback; if (pGC->fillStyle != FillSolid) @@ -83,125 +60,6 @@ uxa_fill_spans(DrawablePtr pDrawable, GCPtr pGC, int n, if (!dst_pixmap) goto fallback; - if (pGC->alu != GXcopy || pGC->planemask != FB_ALLONES) - goto solid; - - format = PictureMatchFormat(screen, - dst_pixmap->drawable.depth, - format_for_depth(dst_pixmap->drawable.depth)); - dst = CreatePicture(0, &dst_pixmap->drawable, format, 0, 0, serverClient, &error); - if (!dst) - goto solid; - - ValidatePicture(dst); - - uxa_get_rgba_from_pixel(pGC->fgPixel, - &color.red, - &color.green, - &color.blue, - &color.alpha, - format_for_depth(dst_pixmap->drawable.depth)); - src = CreateSolidPicture(0, &color, &error); - if (!src) { - FreePicture(dst, 0); - goto solid; - } - - if (!uxa_screen->info->check_composite(PictOpSrc, src, NULL, dst, 0, 0)) { - FreePicture(src, 0); - FreePicture(dst, 0); - goto solid; - } - - if (!uxa_screen->info->check_composite_texture || - !uxa_screen->info->check_composite_texture(screen, src)) { - PicturePtr solid; - int src_off_x, src_off_y; - - solid = uxa_acquire_solid(screen, src->pSourcePict); - FreePicture(src, 0); - - src = solid; - src_pixmap = uxa_get_offscreen_pixmap(src->pDrawable, - &src_off_x, &src_off_y); - if (!src_pixmap) { - FreePicture(src, 0); - FreePicture(dst, 0); - goto solid; - } - } - - if (!uxa_screen->info->prepare_composite(PictOpSrc, src, NULL, dst, src_pixmap, NULL, dst_pixmap)) { - FreePicture(src, 0); - FreePicture(dst, 0); - goto solid; - } - - pextent = REGION_EXTENTS(pGC->screen, pClip); - extentX1 = pextent->x1; - extentY1 = pextent->y1; - extentX2 = pextent->x2; - extentY2 = pextent->y2; - while (n--) { - fullX1 = ppt->x; - fullY1 = ppt->y; - fullX2 = fullX1 + (int)*pwidth; - ppt++; - pwidth++; - - if (fullY1 < extentY1 || extentY2 <= fullY1) - continue; - - if (fullX1 < extentX1) - fullX1 = extentX1; - - if (fullX2 > extentX2) - fullX2 = extentX2; - - if (fullX1 >= fullX2) - continue; - - nbox = REGION_NUM_RECTS(pClip); - if (nbox == 1) { - uxa_screen->info->composite(dst_pixmap, - 0, 0, 0, 0, - fullX1 + off_x, - fullY1 + off_y, - fullX2 - fullX1, 1); - } else { - pbox = REGION_RECTS(pClip); - while (nbox--) { - if (pbox->y1 > fullY1) - break; - - if (pbox->y1 <= fullY1) { - partX1 = pbox->x1; - if (partX1 < fullX1) - partX1 = fullX1; - - partX2 = pbox->x2; - if (partX2 > fullX2) - partX2 = fullX2; - - if (partX2 > partX1) { - uxa_screen->info->composite(dst_pixmap, - 0, 0, 0, 0, - partX1 + off_x, - fullY1 + off_y, - partX2 - partX1, 1); - } - } - pbox++; - } - } - } - - uxa_screen->info->done_composite(dst_pixmap); - FreePicture(src, 0); - FreePicture(dst, 0); - return; - -solid: if (uxa_screen->info->check_solid && !uxa_screen->info->check_solid(pDrawable, pGC->alu, pGC->planemask)) goto fallback; @@ -212,58 +70,32 @@ solid: pGC->fgPixel)) goto fallback; - pextent = REGION_EXTENTS(pGC->screen, pClip); - extentX1 = pextent->x1; - extentY1 = pextent->y1; - extentX2 = pextent->x2; - extentY2 = pextent->y2; while (n--) { - fullX1 = ppt->x; - fullY1 = ppt->y; - fullX2 = fullX1 + (int)*pwidth; + x1 = ppt->x; + y = ppt->y; + x2 = x1 + (int)*pwidth; ppt++; pwidth++; - if (fullY1 < extentY1 || extentY2 <= fullY1) - continue; + nbox = REGION_NUM_RECTS(pClip); + pbox = REGION_RECTS(pClip); + while (nbox--) { + if (pbox->y1 > y || pbox->y2 <= y) + continue; - if (fullX1 < extentX1) - fullX1 = extentX1; + if (x1 < pbox->x1) + x1 = pbox->x1; - if (fullX2 > extentX2) - fullX2 = extentX2; + if (x2 > pbox->x2) + x2 = pbox->x2; - if (fullX1 >= fullX2) - continue; + if (x2 <= x1) + continue; - nbox = REGION_NUM_RECTS(pClip); - if (nbox == 1) { (*uxa_screen->info->solid) (dst_pixmap, - fullX1 + off_x, - fullY1 + off_y, - fullX2 + off_x, - fullY1 + 1 + off_y); - } else { - pbox = REGION_RECTS(pClip); - while (nbox--) { - if (pbox->y1 <= fullY1 && fullY1 < pbox->y2) { - partX1 = pbox->x1; - if (partX1 < fullX1) - partX1 = fullX1; - partX2 = pbox->x2; - if (partX2 > fullX2) - partX2 = fullX2; - if (partX2 > partX1) { - (*uxa_screen->info-> - solid) (dst_pixmap, - partX1 + off_x, - fullY1 + off_y, - partX2 + off_x, - fullY1 + 1 + off_y); - } - } - pbox++; - } + x1 + off_x, y + off_y, + x2 + off_x, y + 1 + off_y); + pbox++; } } (*uxa_screen->info->done_solid) (dst_pixmap); @@ -290,16 +122,18 @@ uxa_do_put_image(DrawablePtr pDrawable, GCPtr pGC, int depth, int x, int y, if (format != ZPixmap || bpp < 8) return FALSE; - /* Only accelerate copies: no rop or planemask. */ - if (!UXA_PM_IS_SOLID(pDrawable, pGC->planemask) || pGC->alu != GXcopy) + if (uxa_screen->swappedOut || uxa_screen->force_fallback) return FALSE; - if (uxa_screen->swappedOut) + if (!uxa_screen->info->put_image) return FALSE; - pPix = uxa_get_offscreen_pixmap(pDrawable, &xoff, &yoff); + /* Only accelerate copies: no rop or planemask. */ + if (!UXA_PM_IS_SOLID(pDrawable, pGC->planemask) || pGC->alu != GXcopy) + return FALSE; - if (!pPix || !uxa_screen->info->put_image) + pPix = uxa_get_offscreen_pixmap(pDrawable, &xoff, &yoff); + if (!pPix) return FALSE; x += pDrawable->x; @@ -510,6 +344,9 @@ uxa_copy_n_to_n(DrawablePtr pSrcDrawable, int dst_off_x, dst_off_y; PixmapPtr pSrcPixmap, pDstPixmap; + if (uxa_screen->swappedOut || uxa_screen->force_fallback) + goto fallback; + pSrcPixmap = uxa_get_drawable_pixmap(pSrcDrawable); pDstPixmap = uxa_get_drawable_pixmap(pDstDrawable); if (!pSrcPixmap || !pDstPixmap) @@ -638,11 +475,13 @@ fallback: uxa_drawable_location(pSrcDrawable), uxa_drawable_location(pDstDrawable))); if (uxa_prepare_access(pDstDrawable, UXA_ACCESS_RW)) { - if (uxa_prepare_access(pSrcDrawable, UXA_ACCESS_RO)) { + if (pSrcDrawable == pDstDrawable || + uxa_prepare_access(pSrcDrawable, UXA_ACCESS_RO)) { fbCopyNtoN(pSrcDrawable, pDstDrawable, pGC, pbox, nbox, dx, dy, reverse, upsidedown, bitplane, closure); - uxa_finish_access(pSrcDrawable); + if (pSrcDrawable != pDstDrawable) + uxa_finish_access(pSrcDrawable); } uxa_finish_access(pDstDrawable); } @@ -654,7 +493,7 @@ uxa_copy_area(DrawablePtr pSrcDrawable, DrawablePtr pDstDrawable, GCPtr pGC, { uxa_screen_t *uxa_screen = uxa_get_screen(pDstDrawable->pScreen); - if (uxa_screen->swappedOut) { + if (uxa_screen->swappedOut || uxa_screen->force_fallback) { return uxa_check_copy_area(pSrcDrawable, pDstDrawable, pGC, srcx, srcy, width, height, dstx, dsty); @@ -828,10 +667,7 @@ uxa_poly_fill_rect(DrawablePtr pDrawable, RegionPtr pClip = fbGetCompositeClip(pGC); PixmapPtr pPixmap; register BoxPtr pbox; - BoxPtr pextent; - int extentX1, extentX2, extentY1, extentY2; int fullX1, fullX2, fullY1, fullY2; - int partX1, partX2, partY1, partY2; int xoff, yoff; int xorg, yorg; int n; @@ -844,7 +680,7 @@ uxa_poly_fill_rect(DrawablePtr pDrawable, if (!REGION_NUM_RECTS(pReg)) goto out; - if (uxa_screen->swappedOut) + if (uxa_screen->swappedOut || uxa_screen->force_fallback) goto fallback; pPixmap = uxa_get_offscreen_pixmap (pDrawable, &xoff, &yoff); @@ -893,11 +729,6 @@ fallback: xorg = pDrawable->x; yorg = pDrawable->y; - pextent = REGION_EXTENTS(pGC->pScreen, pClip); - extentX1 = pextent->x1; - extentY1 = pextent->y1; - extentX2 = pextent->x2; - extentY2 = pextent->y2; while (nrect--) { fullX1 = prect->x + xorg; fullY1 = prect->y + yorg; @@ -905,62 +736,37 @@ fallback: fullY2 = fullY1 + (int)prect->height; prect++; - if (fullX1 < extentX1) - fullX1 = extentX1; - - if (fullY1 < extentY1) - fullY1 = extentY1; - - if (fullX2 > extentX2) - fullX2 = extentX2; + n = REGION_NUM_RECTS(pClip); + pbox = REGION_RECTS(pClip); + /* + * clip the rectangle to each box in the clip region + * this is logically equivalent to calling Intersect(), + * but rectangles may overlap each other here. + */ + while (n--) { + int x1 = fullX1; + int x2 = fullX2; + int y1 = fullY1; + int y2 = fullY2; + + if (pbox->x1 > x1) + x1 = pbox->x1; + if (pbox->x2 < x2) + x2 = pbox->x2; + if (pbox->y1 > y1) + y1 = pbox->y1; + if (pbox->y2 < y2) + y2 = pbox->y2; + pbox++; - if (fullY2 > extentY2) - fullY2 = extentY2; + if (x1 >= x2 || y1 >= y2) + continue; - if ((fullX1 >= fullX2) || (fullY1 >= fullY2)) - continue; - n = REGION_NUM_RECTS(pClip); - if (n == 1) { (*uxa_screen->info->solid) (pPixmap, - fullX1 + xoff, - fullY1 + yoff, - fullX2 + xoff, - fullY2 + yoff); - } else { - pbox = REGION_RECTS(pClip); - /* - * clip the rectangle to each box in the clip region - * this is logically equivalent to calling Intersect(), - * but rectangles may overlap each other here. - */ - while (n--) { - partX1 = pbox->x1; - if (partX1 < fullX1) - partX1 = fullX1; - partY1 = pbox->y1; - if (partY1 < fullY1) - partY1 = fullY1; - partX2 = pbox->x2; - if (partX2 > fullX2) - partX2 = fullX2; - partY2 = pbox->y2; - if (partY2 > fullY2) - partY2 = fullY2; - - pbox++; - - if (partX1 < partX2 && partY1 < partY2) { - (*uxa_screen->info->solid) (pPixmap, - partX1 + - xoff, - partY1 + - yoff, - partX2 + - xoff, - partY2 + - yoff); - } - } + x1 + xoff, + y1 + yoff, + x2 + xoff, + y2 + yoff); } } (*uxa_screen->info->done_solid) (pPixmap); @@ -1029,7 +835,7 @@ uxa_fill_region_solid(DrawablePtr pDrawable, PixmapPtr pixmap; int xoff, yoff; int nbox; - BoxPtr pBox, extents; + BoxPtr pBox; Bool ret = FALSE; pixmap = uxa_get_offscreen_pixmap(pDrawable, &xoff, &yoff); @@ -1040,101 +846,21 @@ uxa_fill_region_solid(DrawablePtr pDrawable, nbox = REGION_NUM_RECTS(pRegion); pBox = REGION_RECTS(pRegion); - extents = REGION_EXTENTS(screen, pRegion); - - /* Using GEM, the relocation costs outweigh the advantages of the blitter */ - if (nbox == 1 || (alu != GXcopy && alu != GXclear) || planemask != FB_ALLONES) { -try_solid: - if (uxa_screen->info->check_solid && - !uxa_screen->info->check_solid(&pixmap->drawable, alu, planemask)) - goto err; - - if (!uxa_screen->info->prepare_solid(pixmap, alu, planemask, pixel)) - goto err; - while (nbox--) { - uxa_screen->info->solid(pixmap, - pBox->x1, pBox->y1, - pBox->x2, pBox->y2); - pBox++; - } - - uxa_screen->info->done_solid(pixmap); - } else { - PicturePtr dst, src; - PixmapPtr src_pixmap = NULL; - xRenderColor color; - int error; - - dst = CreatePicture(0, &pixmap->drawable, - PictureMatchFormat(screen, - pixmap->drawable.depth, - format_for_depth(pixmap->drawable.depth)), - 0, 0, serverClient, &error); - if (!dst) - goto err; - - ValidatePicture(dst); - - uxa_get_rgba_from_pixel(pixel, - &color.red, - &color.green, - &color.blue, - &color.alpha, - format_for_depth(pixmap->drawable.depth)); - src = CreateSolidPicture(0, &color, &error); - if (!src) { - FreePicture(dst, 0); - goto err; - } - - if (!uxa_screen->info->check_composite(PictOpSrc, src, NULL, dst, - extents->x2 - extents->x1, - extents->y2 - extents->y1)) { - FreePicture(src, 0); - FreePicture(dst, 0); - goto try_solid; - } - - if (!uxa_screen->info->check_composite_texture || - !uxa_screen->info->check_composite_texture(screen, src)) { - PicturePtr solid; - int src_off_x, src_off_y; - - solid = uxa_acquire_solid(screen, src->pSourcePict); - FreePicture(src, 0); - - src = solid; - src_pixmap = uxa_get_offscreen_pixmap(src->pDrawable, - &src_off_x, &src_off_y); - if (!src_pixmap) { - FreePicture(src, 0); - FreePicture(dst, 0); - goto err; - } - } - - if (!uxa_screen->info->prepare_composite(PictOpSrc, src, NULL, dst, src_pixmap, NULL, pixmap)) { - FreePicture(src, 0); - FreePicture(dst, 0); - goto err; - } + if (uxa_screen->info->check_solid && + !uxa_screen->info->check_solid(&pixmap->drawable, alu, planemask)) + goto err; - while (nbox--) { - uxa_screen->info->composite(pixmap, - 0, 0, 0, 0, - pBox->x1, - pBox->y1, - pBox->x2 - pBox->x1, - pBox->y2 - pBox->y1); - pBox++; - } + if (!uxa_screen->info->prepare_solid(pixmap, alu, planemask, pixel)) + goto err; - uxa_screen->info->done_composite(pixmap); - FreePicture(src, 0); - FreePicture(dst, 0); + while (nbox--) { + uxa_screen->info->solid(pixmap, + pBox->x1, pBox->y1, + pBox->x2, pBox->y2); + pBox++; } - + uxa_screen->info->done_solid(pixmap); ret = TRUE; err: @@ -1257,7 +983,7 @@ uxa_get_image(DrawablePtr pDrawable, int x, int y, int w, int h, Box.x2 = Box.x1 + w; Box.y2 = Box.y1 + h; - if (uxa_screen->swappedOut) + if (uxa_screen->swappedOut || uxa_screen->force_fallback) goto fallback; pPix = uxa_get_offscreen_pixmap(pDrawable, &xoff, &yoff); diff --git a/driver/xf86-video-intel/uxa/uxa-glyphs.c b/driver/xf86-video-intel/uxa/uxa-glyphs.c index 823cf82f7..6c9ea0d6c 100644 --- a/driver/xf86-video-intel/uxa/uxa-glyphs.c +++ b/driver/xf86-video-intel/uxa/uxa-glyphs.c @@ -111,6 +111,9 @@ static void uxa_unrealize_glyph_caches(ScreenPtr pScreen) uxa_screen_t *uxa_screen = uxa_get_screen(pScreen); int i; + if (!uxa_screen->glyph_cache_initialized) + return; + for (i = 0; i < UXA_NUM_GLYPH_CACHE_FORMATS; i++) { uxa_glyph_cache_t *cache = &uxa_screen->glyphCaches[i]; @@ -120,6 +123,7 @@ static void uxa_unrealize_glyph_caches(ScreenPtr pScreen) if (cache->glyphs) free(cache->glyphs); } + uxa_screen->glyph_cache_initialized = FALSE; } void uxa_glyphs_fini(ScreenPtr pScreen) @@ -145,6 +149,10 @@ static Bool uxa_realize_glyph_caches(ScreenPtr pScreen) }; int i; + if (uxa_screen->glyph_cache_initialized) + return TRUE; + + uxa_screen->glyph_cache_initialized = TRUE; memset(uxa_screen->glyphCaches, 0, sizeof(uxa_screen->glyphCaches)); for (i = 0; i < sizeof(formats)/sizeof(formats[0]); i++) { @@ -164,7 +172,12 @@ static Bool uxa_realize_glyph_caches(ScreenPtr pScreen) INTEL_CREATE_PIXMAP_TILING_X); if (!pixmap) goto bail; - assert (uxa_pixmap_is_offscreen(pixmap)); + if (!uxa_pixmap_is_offscreen(pixmap)) { + /* Presume shadow is in-effect */ + pScreen->DestroyPixmap(pixmap); + uxa_unrealize_glyph_caches(pScreen); + return TRUE; + } component_alpha = NeedsComponent(pPictFormat->format); picture = CreatePicture(0, &pixmap->drawable, pPictFormat, @@ -197,13 +210,6 @@ bail: Bool uxa_glyphs_init(ScreenPtr pScreen) { - /* We are trying to initialise per screen resources prior to the - * complete initialisation of the screen. So ensure the components - * that we depend upon are initialsed prior to our use. - */ - if (!CreateScratchPixmapsForScreen(pScreen->myNum)) - return FALSE; - #if HAS_DIXREGISTERPRIVATEKEY if (!dixRegisterPrivateKey(&uxa_glyph_key, PRIVATE_GLYPH, 0)) return FALSE; @@ -212,10 +218,11 @@ Bool uxa_glyphs_init(ScreenPtr pScreen) return FALSE; #endif - if (!uxa_realize_glyph_caches(pScreen)) - return FALSE; + /* Skip pixmap creation if we don't intend to use it. */ + if (uxa_get_screen(pScreen)->force_fallback) + return TRUE; - return TRUE; + return uxa_realize_glyph_caches(pScreen); } /* The most efficient thing to way to upload the glyph to the screen @@ -293,18 +300,19 @@ uxa_glyph_cache_upload_glyph(ScreenPtr screen, } void -uxa_glyph_unrealize(ScreenPtr pScreen, - GlyphPtr pGlyph) +uxa_glyph_unrealize(ScreenPtr screen, + GlyphPtr glyph) { struct uxa_glyph *priv; - priv = uxa_glyph_get_private(pGlyph); + /* Use Lookup in case we have not attached to this glyph. */ + priv = dixLookupPrivate(&glyph->devPrivates, &uxa_glyph_key); if (priv == NULL) return; priv->cache->glyphs[priv->pos] = NULL; - uxa_glyph_set_private(pGlyph, NULL); + uxa_glyph_set_private(glyph, NULL); free(priv); } @@ -780,9 +788,8 @@ uxa_glyphs_to_dst(CARD8 op, mask_pixmap = uxa_get_drawable_pixmap(this_atlas->pDrawable); - assert (uxa_pixmap_is_offscreen(mask_pixmap)); - - if (!uxa_screen->info->prepare_composite(op, + if (!uxa_pixmap_is_offscreen(mask_pixmap) || + !uxa_screen->info->prepare_composite(op, localSrc, this_atlas, pDst, src_pixmap, mask_pixmap, dst_pixmap)) return -1; @@ -930,6 +937,11 @@ uxa_glyphs_via_mask(CARD8 op, if (!pixmap) return 1; + if (!uxa_pixmap_is_offscreen(pixmap)) { + screen->DestroyPixmap(pixmap); + return -1; + } + uxa_clear_pixmap(screen, uxa_screen, pixmap); component_alpha = NeedsComponent(maskFormat->format); @@ -983,9 +995,8 @@ uxa_glyphs_via_mask(CARD8 op, src_pixmap = uxa_get_drawable_pixmap(this_atlas->pDrawable); - assert (uxa_pixmap_is_offscreen(src_pixmap)); - - if (!uxa_screen->info->prepare_composite(PictOpAdd, + if (!uxa_pixmap_is_offscreen(src_pixmap) || + !uxa_screen->info->prepare_composite(PictOpAdd, this_atlas, NULL, mask, src_pixmap, NULL, pixmap)) return -1; @@ -1022,6 +1033,19 @@ next_glyph: return 0; } +static Bool +is_solid(PicturePtr picture) +{ + if (picture->pSourcePict) { + SourcePict *source = picture->pSourcePict; + return source->type == SourcePictTypeSolidFill; + } else { + return (picture->repeat && + picture->pDrawable->width == 1 && + picture->pDrawable->height == 1); + } +} + void uxa_glyphs(CARD8 op, PicturePtr pSrc, @@ -1040,8 +1064,11 @@ uxa_glyphs(CARD8 op, if (!uxa_screen->info->prepare_composite || uxa_screen->swappedOut || + uxa_screen->force_fallback || !uxa_drawable_is_offscreen(pDst->pDrawable) || - pDst->alphaMap || pSrc->alphaMap) { + pDst->alphaMap || pSrc->alphaMap || + /* XXX we fail to handle (rare) non-solid sources correctly. */ + !is_solid(pSrc)) { fallback: uxa_check_glyphs(op, pSrc, pDst, maskFormat, xSrc, ySrc, nlist, list, glyphs); return; @@ -1122,6 +1149,11 @@ fallback: if (!pixmap) return; + if (!uxa_pixmap_is_offscreen(pixmap)) { + screen->DestroyPixmap(pixmap); + goto fallback; + } + gc = GetScratchGC(depth, screen); if (!gc) { screen->DestroyPixmap(pixmap); diff --git a/driver/xf86-video-intel/uxa/uxa-priv.h b/driver/xf86-video-intel/uxa/uxa-priv.h index 4b988f4e7..6b9a9c11f 100644 --- a/driver/xf86-video-intel/uxa/uxa-priv.h +++ b/driver/xf86-video-intel/uxa/uxa-priv.h @@ -39,7 +39,6 @@ #include "uxa.h" #include <X11/X.h> -#define NEED_EVENTS #include <X11/Xproto.h> #include "scrnintstr.h" #include "pixmapstr.h" @@ -133,12 +132,14 @@ typedef struct { #endif EnableDisableFBAccessProcPtr SavedEnableDisableFBAccess; + Bool force_fallback; Bool fallback_debug; Bool swappedOut; unsigned disableFbCount; unsigned offScreenCounter; uxa_glyph_cache_t glyphCaches[UXA_NUM_GLYPH_CACHE_FORMATS]; + Bool glyph_cache_initialized; PicturePtr solid_clear, solid_black, solid_white; uxa_solid_cache_t solid_cache[UXA_NUM_SOLID_CACHE]; @@ -324,9 +325,11 @@ uxa_check_composite(CARD8 op, /* uxa.c */ Bool uxa_prepare_access(DrawablePtr pDrawable, uxa_access_t access); - void uxa_finish_access(DrawablePtr pDrawable); +Bool uxa_picture_prepare_access(PicturePtr picture, int mode); +void uxa_picture_finish_access(PicturePtr picture); + void uxa_get_drawable_deltas(DrawablePtr pDrawable, PixmapPtr pPixmap, int *xp, int *yp); diff --git a/driver/xf86-video-intel/uxa/uxa-render.c b/driver/xf86-video-intel/uxa/uxa-render.c index 056b60a47..076152446 100644 --- a/driver/xf86-video-intel/uxa/uxa-render.c +++ b/driver/xf86-video-intel/uxa/uxa-render.c @@ -167,6 +167,10 @@ uxa_print_composite_fallback(const char *func, CARD8 op, if (! uxa_screen->fallback_debug) return; + /* Limit the noise if fallbacks are expected. */ + if (uxa_screen->force_fallback) + return; + uxa_composite_fallback_pict_desc(pSrc, srcdesc, 40); uxa_composite_fallback_pict_desc(pMask, maskdesc, 40); uxa_composite_fallback_pict_desc(pDst, dstdesc, 40); @@ -200,7 +204,10 @@ Bool uxa_op_reads_destination(CARD8 op) static Bool uxa_get_pixel_from_rgba(CARD32 * pixel, CARD16 red, - CARD16 green, CARD16 blue, CARD16 alpha, CARD32 format) + CARD16 green, + CARD16 blue, + CARD16 alpha, + CARD32 format) { int rbits, bbits, gbits, abits; int rshift, bshift, gshift, ashift; @@ -225,17 +232,24 @@ uxa_get_pixel_from_rgba(CARD32 * pixel, gshift = bbits; rshift = gshift + gbits; ashift = rshift + rbits; - } else { /* PICT_TYPE_ABGR */ + } else if (PICT_FORMAT_TYPE(format) == PICT_TYPE_ABGR) { rshift = 0; gshift = rbits; bshift = gshift + gbits; ashift = bshift + bbits; + } else if (PICT_FORMAT_TYPE(format) == PICT_TYPE_BGRA) { + ashift = 0; + rshift = abits; + gshift = rshift + rbits; + bshift = gshift + gbits; + } else { + return FALSE; } *pixel = 0; - *pixel |= (blue >> (16 - bbits)) << bshift; - *pixel |= (red >> (16 - rbits)) << rshift; + *pixel |= (blue >> (16 - bbits)) << bshift; *pixel |= (green >> (16 - gbits)) << gshift; + *pixel |= (red >> (16 - rbits)) << rshift; *pixel |= (alpha >> (16 - abits)) << ashift; return TRUE; @@ -245,7 +259,9 @@ Bool uxa_get_rgba_from_pixel(CARD32 pixel, CARD16 * red, CARD16 * green, - CARD16 * blue, CARD16 * alpha, CARD32 format) + CARD16 * blue, + CARD16 * alpha, + CARD32 format) { int rbits, bbits, gbits, abits; int rshift, bshift, gshift, ashift; @@ -267,6 +283,13 @@ uxa_get_rgba_from_pixel(CARD32 pixel, gshift = rbits; bshift = gshift + gbits; ashift = bshift + bbits; + } else if (PICT_FORMAT_TYPE(format) == PICT_TYPE_BGRA) { + ashift = 0; + rshift = abits; + if (abits == 0) + rshift = PICT_FORMAT_BPP(format) - (rbits+gbits+bbits); + gshift = rshift + rbits; + bshift = gshift + gbits; } else { return FALSE; } @@ -322,11 +345,13 @@ uxa_get_color_for_pixmap (PixmapPtr pixmap, *pixel = uxa_get_pixmap_first_pixel(pixmap); if (src_format != dst_format) { - if (!uxa_get_rgba_from_pixel(*pixel, &red, &green, &blue, &alpha, + if (!uxa_get_rgba_from_pixel(*pixel, + &red, &green, &blue, &alpha, src_format)) return FALSE; - if (!uxa_get_pixel_from_rgba(pixel, red, green, blue, alpha, + if (!uxa_get_pixel_from_rgba(pixel, + red, green, blue, alpha, dst_format)) return FALSE; } @@ -384,7 +409,23 @@ uxa_try_driver_solid_fill(PicturePtr pSrc, return -1; } - pixel = solid->color; + if (pDst->format == PICT_a8r8g8b8) { + pixel = solid->color; + } else if (pDst->format == PICT_x8r8g8b8) { + pixel = solid->color | 0xff000000; + } else { + CARD16 red, green, blue, alpha; + + if (!uxa_get_rgba_from_pixel(solid->color, + &red, &green, &blue, &alpha, + PICT_a8r8g8b8) || + !uxa_get_pixel_from_rgba(&pixel, + red, green, blue, alpha, + pDst->format)) { + REGION_UNINIT(pDst->pDrawable->pScreen, ®ion); + return -1; + } + } } if (!(*uxa_screen->info->prepare_solid) @@ -411,12 +452,12 @@ uxa_try_driver_solid_fill(PicturePtr pSrc, } static PicturePtr -uxa_picture_for_pixman_format(ScreenPtr pScreen, +uxa_picture_for_pixman_format(ScreenPtr screen, pixman_format_code_t format, int width, int height) { - PicturePtr pPicture; - PixmapPtr pPixmap; + PicturePtr picture; + PixmapPtr pixmap; int error; if (format == PIXMAN_a1) @@ -426,24 +467,29 @@ uxa_picture_for_pixman_format(ScreenPtr pScreen, if (PIXMAN_FORMAT_A(format) == 0) format = PIXMAN_a8r8g8b8; - pPixmap = (*pScreen->CreatePixmap)(pScreen, width, height, - PIXMAN_FORMAT_DEPTH(format), - UXA_CREATE_PIXMAP_FOR_MAP); - if (!pPixmap) + pixmap = screen->CreatePixmap(screen, width, height, + PIXMAN_FORMAT_DEPTH(format), + UXA_CREATE_PIXMAP_FOR_MAP); + if (!pixmap) return 0; - pPicture = CreatePicture(0, &pPixmap->drawable, - PictureMatchFormat(pScreen, - PIXMAN_FORMAT_DEPTH(format), - format), - 0, 0, serverClient, &error); - (*pScreen->DestroyPixmap) (pPixmap); - if (!pPicture) + if (!uxa_pixmap_is_offscreen(pixmap)) { + screen->DestroyPixmap(pixmap); + return 0; + } + + picture = CreatePicture(0, &pixmap->drawable, + PictureMatchFormat(screen, + PIXMAN_FORMAT_DEPTH(format), + format), + 0, 0, serverClient, &error); + screen->DestroyPixmap(pixmap); + if (!picture) return 0; - ValidatePicture(pPicture); + ValidatePicture(picture); - return pPicture; + return picture; } static PicturePtr @@ -514,10 +560,10 @@ uxa_picture_from_pixman_image(ScreenPtr screen, } ValidatePicture(src); - if (uxa_prepare_access(picture->pDrawable, UXA_ACCESS_RW)) { + if (uxa_picture_prepare_access(picture, UXA_ACCESS_RW)) { fbComposite(PictOpSrc, src, NULL, picture, 0, 0, 0, 0, 0, 0, width, height); - uxa_finish_access(picture->pDrawable); + uxa_picture_finish_access(picture); } FreePicture(src, 0); @@ -645,10 +691,10 @@ uxa_acquire_pattern(ScreenPtr pScreen, if (!pDst) return 0; - if (uxa_prepare_access(pDst->pDrawable, UXA_ACCESS_RW)) { + if (uxa_picture_prepare_access(pDst, UXA_ACCESS_RW)) { fbComposite(PictOpSrc, pSrc, NULL, pDst, x, y, 0, 0, 0, 0, width, height); - uxa_finish_access(pDst->pDrawable); + uxa_picture_finish_access(pDst); return pDst; } else { FreePicture(pDst, 0); @@ -702,14 +748,14 @@ uxa_render_picture(ScreenPtr screen, if (!picture) return 0; - if (uxa_prepare_access(picture->pDrawable, UXA_ACCESS_RW)) { - if (uxa_prepare_access(src->pDrawable, UXA_ACCESS_RO)) { + if (uxa_picture_prepare_access(picture, UXA_ACCESS_RW)) { + if (uxa_picture_prepare_access(src, UXA_ACCESS_RO)) { ret = 1; fbComposite(PictOpSrc, src, NULL, picture, x, y, 0, 0, 0, 0, width, height); - uxa_finish_access(src->pDrawable); + uxa_picture_finish_access(src); } - uxa_finish_access(picture->pDrawable); + uxa_picture_finish_access(picture); } if (!ret) { @@ -757,6 +803,8 @@ uxa_acquire_drawable(ScreenPtr pScreen, pDst = uxa_render_picture(pScreen, pSrc, pSrc->format | (BitsPerPixel(pSrc->pDrawable->depth) << 24), x, y, width, height); + if (!pDst) + return 0; goto done; } else { @@ -794,8 +842,10 @@ uxa_acquire_drawable(ScreenPtr pScreen, PictureMatchFormat(pScreen, depth, pSrc->format), 0, 0, serverClient, &error); pScreen->DestroyPixmap(pPixmap); - ValidatePicture(pDst); + if (!pDst) + return 0; + ValidatePicture(pDst); done: pDst->componentAlpha = pSrc->componentAlpha; *out_x = 0; @@ -945,11 +995,6 @@ uxa_solid_rects (CARD8 op, return; } - /* XXX xserver-1.8: CompositeRects is not tracked by Damage, so we must - * manually append the damaged regions ourselves. - */ - DamageRegionAppend(dst->pDrawable, ®ion); - pixman_region_translate(®ion, dst_x, dst_y); boxes = pixman_region_rectangles(®ion, &num_boxes); extents = pixman_region_extents (®ion); @@ -1013,6 +1058,8 @@ try_solid: int src_off_x, src_off_y; solid = uxa_acquire_solid(screen, src->pSourcePict); + if (!solid) + goto err_src; FreePicture(src, 0); src = solid; @@ -1039,6 +1086,12 @@ try_solid: FreePicture(src, 0); } + /* XXX xserver-1.8: CompositeRects is not tracked by Damage, so we must + * manually append the damaged regions ourselves. + */ + pixman_region_translate(®ion, -dst_x, -dst_y); + DamageRegionAppend(dst->pDrawable, ®ion); + pixman_region_fini(®ion); return; @@ -1469,17 +1522,15 @@ uxa_composite(CARD8 op, RegionRec region; int tx, ty; - if (uxa_screen->swappedOut) + if (uxa_screen->swappedOut || uxa_screen->force_fallback) goto fallback; if (!uxa_drawable_is_offscreen(pDst->pDrawable)) goto fallback; - if (pDst->alphaMap || pSrc->alphaMap || (pMask && pMask->alphaMap)) goto fallback; - /* Remove repeat in source if useless */ if (pSrc->pDrawable && pSrc->repeat && pSrc->filter != PictFilterConvolution && transform_is_integer_translation(pSrc->transform, &tx, &ty) && @@ -1705,6 +1756,90 @@ uxa_create_alpha_picture(ScreenPtr pScreen, return pPicture; } +static void +uxa_check_trapezoids(CARD8 op, PicturePtr src, PicturePtr dst, + PictFormatPtr maskFormat, INT16 xSrc, INT16 ySrc, + int ntrap, xTrapezoid * traps) +{ + ScreenPtr screen = dst->pDrawable->pScreen; + + if (maskFormat) { + PixmapPtr scratch = NULL; + PicturePtr mask; + INT16 xDst, yDst; + INT16 xRel, yRel; + BoxRec bounds; + int width, height; + pixman_image_t *image; + pixman_format_code_t format; + int error; + + xDst = traps[0].left.p1.x >> 16; + yDst = traps[0].left.p1.y >> 16; + + miTrapezoidBounds (ntrap, traps, &bounds); + if (bounds.y1 >= bounds.y2 || bounds.x1 >= bounds.x2) + return; + + width = bounds.x2 - bounds.x1; + height = bounds.y2 - bounds.y1; + + format = maskFormat->format | + (BitsPerPixel(maskFormat->depth) << 24); + image = + pixman_image_create_bits(format, width, height, NULL, 0); + if (!image) + return; + + for (; ntrap; ntrap--, traps++) + pixman_rasterize_trapezoid(image, + (pixman_trapezoid_t *) traps, + -bounds.x1, -bounds.y1); + + + scratch = GetScratchPixmapHeader(screen, width, height, + PIXMAN_FORMAT_DEPTH(format), + PIXMAN_FORMAT_BPP(format), + pixman_image_get_stride(image), + pixman_image_get_data(image)); + if (!scratch) { + pixman_image_unref(image); + return; + } + + mask = CreatePicture(0, &scratch->drawable, + PictureMatchFormat(screen, + PIXMAN_FORMAT_DEPTH(format), + format), + 0, 0, serverClient, &error); + if (!mask) { + FreeScratchPixmapHeader(scratch); + pixman_image_unref(image); + return; + } + + xRel = bounds.x1 + xSrc - xDst; + yRel = bounds.y1 + ySrc - yDst; + CompositePicture(op, src, mask, dst, + xRel, yRel, + 0, 0, + bounds.x1, bounds.y1, + width, height); + FreePicture(mask, 0); + + FreeScratchPixmapHeader(scratch); + pixman_image_unref(image); + } else { + if (dst->polyEdge == PolyEdgeSharp) + maskFormat = PictureMatchFormat(screen, 1, PICT_a1); + else + maskFormat = PictureMatchFormat(screen, 8, PICT_a8); + + for (; ntrap; ntrap--, traps++) + uxa_check_trapezoids(op, src, dst, maskFormat, xSrc, ySrc, 1, traps); + } +} + /** * uxa_trapezoids is essentially a copy of miTrapezoids that uses * uxa_create_alpha_picture instead of miCreateAlphaPicture. @@ -1724,9 +1859,15 @@ uxa_trapezoids(CARD8 op, PicturePtr src, PicturePtr dst, int ntrap, xTrapezoid * traps) { ScreenPtr screen = dst->pDrawable->pScreen; + uxa_screen_t *uxa_screen = uxa_get_screen(screen); BoxRec bounds; Bool direct; + if (uxa_screen->swappedOut || uxa_screen->force_fallback) { + uxa_check_trapezoids(op, src, dst, maskFormat, xSrc, ySrc, ntrap, traps); + return; + } + direct = op == PictOpAdd && miIsSolidAlpha(src); if (maskFormat || direct) { miTrapezoidBounds(ntrap, traps, &bounds); diff --git a/driver/xf86-video-intel/uxa/uxa-unaccel.c b/driver/xf86-video-intel/uxa/uxa-unaccel.c index 15be821a0..1d4b2c02e 100644 --- a/driver/xf86-video-intel/uxa/uxa-unaccel.c +++ b/driver/xf86-video-intel/uxa/uxa-unaccel.c @@ -67,6 +67,34 @@ void uxa_finish_access_gc(GCPtr pGC) uxa_finish_access(&pGC->stipple->drawable); } +Bool uxa_picture_prepare_access(PicturePtr picture, int mode) +{ + if (picture->pDrawable == NULL) + return TRUE; + + if (!uxa_prepare_access(picture->pDrawable, mode)) + return FALSE; + + if (picture->alphaMap && + !uxa_prepare_access(picture->alphaMap->pDrawable, mode)) { + uxa_finish_access(picture->pDrawable); + return FALSE; + } + + return TRUE; +} + +void uxa_picture_finish_access(PicturePtr picture) +{ + if (picture->pDrawable == NULL) + return; + + uxa_finish_access(picture->pDrawable); + if (picture->alphaMap) + uxa_finish_access(picture->alphaMap->pDrawable); +} + + char uxa_drawable_location(DrawablePtr pDrawable) { return uxa_drawable_is_offscreen(pDrawable) ? 's' : 'm'; @@ -362,24 +390,20 @@ uxa_check_composite(CARD8 op, UXA_FALLBACK(("from picts %p/%p to pict %p\n", pSrc, pMask, pDst)); - if (uxa_prepare_access(pDst->pDrawable, UXA_ACCESS_RW)) { - if (pSrc->pDrawable == NULL || - uxa_prepare_access(pSrc->pDrawable, UXA_ACCESS_RO)) { - if (!pMask || pMask->pDrawable == NULL || - uxa_prepare_access(pMask->pDrawable, UXA_ACCESS_RO)) - { + if (uxa_picture_prepare_access(pDst, UXA_ACCESS_RW)) { + if (uxa_picture_prepare_access(pSrc, UXA_ACCESS_RO)) { + if (!pMask || uxa_picture_prepare_access(pMask, UXA_ACCESS_RO)) { fbComposite(op, pSrc, pMask, pDst, xSrc, ySrc, xMask, yMask, xDst, yDst, width, height); - if (pMask && pMask->pDrawable != NULL) - uxa_finish_access(pMask->pDrawable); + if (pMask) + uxa_picture_finish_access(pMask); } - if (pSrc->pDrawable != NULL) - uxa_finish_access(pSrc->pDrawable); + uxa_picture_finish_access(pSrc); } - uxa_finish_access(pDst->pDrawable); + uxa_picture_finish_access(pDst); } } @@ -391,9 +415,9 @@ uxa_check_add_traps(PicturePtr pPicture, UXA_FALLBACK(("to pict %p (%c)\n", pPicture, uxa_drawable_location(pPicture->pDrawable))); - if (uxa_prepare_access(pPicture->pDrawable, UXA_ACCESS_RW)) { + if (uxa_picture_prepare_access(pPicture, UXA_ACCESS_RW)) { fbAddTraps(pPicture, x_off, y_off, ntrap, traps); - uxa_finish_access(pPicture->pDrawable); + uxa_picture_finish_access(pPicture); } } diff --git a/driver/xf86-video-intel/uxa/uxa.c b/driver/xf86-video-intel/uxa/uxa.c index 37546dc3a..856a0ce5b 100644 --- a/driver/xf86-video-intel/uxa/uxa.c +++ b/driver/xf86-video-intel/uxa/uxa.c @@ -1,7 +1,7 @@ /* - * Copyright © 2001 Keith Packard + * Copyright © 2001 Keith Packard * - * Partly based on code that is Copyright © The XFree86 Project Inc. + * Partly based on code that is Copyright © The XFree86 Project Inc. * * Permission to use, copy, modify, distribute, and sell this software and its * documentation for any purpose is hereby granted without fee, provided that @@ -164,11 +164,12 @@ void uxa_finish_access(DrawablePtr pDrawable) { ScreenPtr pScreen = pDrawable->pScreen; uxa_screen_t *uxa_screen = uxa_get_screen(pScreen); - PixmapPtr pPixmap = uxa_get_drawable_pixmap(pDrawable); + PixmapPtr pPixmap; if (uxa_screen->info->finish_access == NULL) return; + pPixmap = uxa_get_drawable_pixmap(pDrawable); if (!uxa_pixmap_is_offscreen(pPixmap)) return; @@ -354,6 +355,13 @@ void uxa_set_fallback_debug(ScreenPtr screen, Bool enable) uxa_screen->fallback_debug = enable; } +void uxa_set_force_fallback(ScreenPtr screen, Bool value) +{ + uxa_screen_t *uxa_screen = uxa_get_screen(screen); + + uxa_screen->force_fallback = value; +} + /** * uxa_close_screen() unwraps its wrapped screen functions and tears down UXA's * screen private, before calling down to the next CloseSccreen. @@ -378,6 +386,16 @@ static Bool uxa_close_screen(int i, ScreenPtr pScreen) uxa_glyphs_fini(pScreen); + if (pScreen->devPrivate) { + /* Destroy the pixmap created by miScreenInit() *before* + * chaining up as we finalize ourselves here and so this + * is the last chance we have of releasing our resources + * associated with the Pixmap. So do it first. + */ + (void) (*pScreen->DestroyPixmap) (pScreen->devPrivate); + pScreen->devPrivate = NULL; + } + pScreen->CreateGC = uxa_screen->SavedCreateGC; pScreen->CloseScreen = uxa_screen->SavedCloseScreen; pScreen->GetImage = uxa_screen->SavedGetImage; @@ -481,6 +499,8 @@ Bool uxa_driver_init(ScreenPtr screen, uxa_driver_t * uxa_driver) dixSetPrivate(&screen->devPrivates, &uxa_screen_index, uxa_screen); + uxa_screen->force_fallback = FALSE; + uxa_screen->solid_cache_size = 0; uxa_screen->solid_clear = 0; uxa_screen->solid_black = 0; diff --git a/driver/xf86-video-intel/uxa/uxa.h b/driver/xf86-video-intel/uxa/uxa.h index efadfdaaa..e001c53df 100644 --- a/driver/xf86-video-intel/uxa/uxa.h +++ b/driver/xf86-video-intel/uxa/uxa.h @@ -571,6 +571,7 @@ uxa_get_color_for_pixmap (PixmapPtr pixmap, CARD32 *pixel); void uxa_set_fallback_debug(ScreenPtr screen, Bool enable); +void uxa_set_force_fallback(ScreenPtr screen, Bool enable); /** * Returns TRUE if the given planemask covers all the significant bits in the |