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authorJonathan Gray <jsg@cvs.openbsd.org>2018-10-23 06:36:00 +0000
committerJonathan Gray <jsg@cvs.openbsd.org>2018-10-23 06:36:00 +0000
commitb65fcab046d3a1b6b6ac315720df220925c5322e (patch)
treeff73dcc383ac0799c655ff6194cda9dacb75dde9 /lib/mesa/src/compiler/glsl/ir_optimization.h
parent18d6381c51e253e4c41c62619f80d9ce745b95c8 (diff)
Merge Mesa 17.3.9
Mesa 18.x needs an ld with build-id for at least the intel code Mesa 18.2 assumes linux only memfd syscalls in intel code Tested by matthieu@, kettenis@ and myself on a variety of hardware and architectures. ok kettenis@
Diffstat (limited to 'lib/mesa/src/compiler/glsl/ir_optimization.h')
-rw-r--r--lib/mesa/src/compiler/glsl/ir_optimization.h39
1 files changed, 30 insertions, 9 deletions
diff --git a/lib/mesa/src/compiler/glsl/ir_optimization.h b/lib/mesa/src/compiler/glsl/ir_optimization.h
index 95af29544..f44ddcb05 100644
--- a/lib/mesa/src/compiler/glsl/ir_optimization.h
+++ b/lib/mesa/src/compiler/glsl/ir_optimization.h
@@ -21,13 +21,15 @@
* DEALINGS IN THE SOFTWARE.
*/
-
/**
* \file ir_optimization.h
*
* Prototypes for optimization passes to be called by the compiler and drivers.
*/
+#ifndef GLSL_IR_OPTIMIZATION_H
+#define GLSL_IR_OPTIMIZATION_H
+
/* Operations for lower_instructions() */
#define SUB_TO_ADD_NEG 0x01
#define FDIV_TO_MUL_RCP 0x02
@@ -51,6 +53,13 @@
#define IMUL_HIGH_TO_MUL 0x80000
#define DDIV_TO_MUL_RCP 0x100000
#define DIV_TO_MUL_RCP (FDIV_TO_MUL_RCP | DDIV_TO_MUL_RCP)
+#define SQRT_TO_ABS_SQRT 0x200000
+
+/* Opertaions for lower_64bit_integer_instructions() */
+#define MUL64 (1U << 0)
+#define SIGN64 (1U << 1)
+#define DIV64 (1U << 2)
+#define MOD64 (1U << 3)
/**
* \see class lower_packing_builtins_visitor
@@ -110,7 +119,8 @@ bool do_lower_texture_projection(exec_list *instructions);
bool do_if_simplification(exec_list *instructions);
bool opt_flatten_nested_if_blocks(exec_list *instructions);
bool do_discard_simplification(exec_list *instructions);
-bool lower_if_to_cond_assign(exec_list *instructions, unsigned max_depth = 0);
+bool lower_if_to_cond_assign(gl_shader_stage stage, exec_list *instructions,
+ unsigned max_depth = 0, unsigned min_branch_cost = 0);
bool do_mat_op_to_vec(exec_list *instructions);
bool do_minmax_prune(exec_list *instructions);
bool do_noop_swizzle(exec_list *instructions);
@@ -133,12 +143,15 @@ bool lower_clip_cull_distance(struct gl_shader_program *prog,
gl_linked_shader *shader);
void lower_output_reads(unsigned stage, exec_list *instructions);
bool lower_packing_builtins(exec_list *instructions, int op_mask);
-void lower_shared_reference(struct gl_linked_shader *shader,
- unsigned *shared_size);
+void lower_shared_reference(struct gl_context *ctx,
+ struct gl_shader_program *prog,
+ struct gl_linked_shader *shader);
void lower_ubo_reference(struct gl_linked_shader *shader,
- bool clamp_block_indices);
+ bool clamp_block_indices, bool use_std430_as_default);
void lower_packed_varyings(void *mem_ctx,
- unsigned locations_used, ir_variable_mode mode,
+ unsigned locations_used,
+ const uint8_t *components,
+ ir_variable_mode mode,
unsigned gs_input_vertices,
gl_linked_shader *shader,
bool disable_varying_packing, bool xfb_enabled);
@@ -153,11 +166,19 @@ void optimize_dead_builtin_variables(exec_list *instructions,
bool lower_tess_level(gl_linked_shader *shader);
bool lower_vertex_id(gl_linked_shader *shader);
+bool lower_cs_derived(gl_linked_shader *shader);
bool lower_blend_equation_advanced(gl_linked_shader *shader);
bool lower_subroutine(exec_list *instructions, struct _mesa_glsl_parse_state *state);
void propagate_invariance(exec_list *instructions);
-ir_rvalue *
-compare_index_block(exec_list *instructions, ir_variable *index,
- unsigned base, unsigned components, void *mem_ctx);
+namespace ir_builder { class ir_factory; };
+
+ir_variable *compare_index_block(ir_builder::ir_factory &body,
+ ir_variable *index,
+ unsigned base, unsigned components);
+
+bool lower_64bit_integer_instructions(exec_list *instructions,
+ unsigned what_to_lower);
+
+#endif /* GLSL_IR_OPTIMIZATION_H */