Merge Mesa 22.1.7

1 files changed, 36 insertions, 14 deletions

diff --git a/lib/mesa/src/gallium/drivers/radeonsi/si_pm4.c b/lib/mesa/src/gallium/drivers/radeonsi/si_pm4.c
index d4ea07692..6f671a90e 100644
--- a/lib/mesa/src/gallium/drivers/radeonsi/si_pm4.c
+++ b/lib/mesa/src/gallium/drivers/radeonsi/si_pm4.c
@@ -29,16 +29,21 @@
 
 static void si_pm4_cmd_begin(struct si_pm4_state *state, unsigned opcode)
 {
-   assert(state->ndw < SI_PM4_MAX_DW);
+   if (!state->max_dw)
+      state->max_dw = ARRAY_SIZE(state->pm4);
+   assert(state->ndw < state->max_dw);
+   assert(opcode <= 254);
    state->last_opcode = opcode;
    state->last_pm4 = state->ndw++;
 }
 
 void si_pm4_cmd_add(struct si_pm4_state *state, uint32_t dw)
 {
-   assert(state->ndw < SI_PM4_MAX_DW);
+   if (!state->max_dw)
+      state->max_dw = ARRAY_SIZE(state->pm4);
+   assert(state->ndw < state->max_dw);
    state->pm4[state->ndw++] = dw;
-   state->last_opcode = -1;
+   state->last_opcode = 255; /* invalid opcode */
 }
 
 static void si_pm4_cmd_end(struct si_pm4_state *state, bool predicate)
@@ -48,6 +53,27 @@ static void si_pm4_cmd_end(struct si_pm4_state *state, bool predicate)
    state->pm4[state->last_pm4] = PKT3(state->last_opcode, count, predicate);
 }
 
+static void si_pm4_set_reg_custom(struct si_pm4_state *state, unsigned reg, uint32_t val,
+                                  unsigned opcode, unsigned idx)
+{
+   reg >>= 2;
+
+   if (!state->max_dw)
+      state->max_dw = ARRAY_SIZE(state->pm4);
+
+   assert(state->ndw + 2 <= state->max_dw);
+
+   if (opcode != state->last_opcode || reg != (state->last_reg + 1)) {
+      si_pm4_cmd_begin(state, opcode);
+      state->pm4[state->ndw++] = reg | (idx << 28);
+   }
+
+   assert(reg <= UINT16_MAX);
+   state->last_reg = reg;
+   state->pm4[state->ndw++] = val;
+   si_pm4_cmd_end(state, false);
+}
+
 void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val)
 {
    unsigned opcode;
@@ -75,18 +101,14 @@ void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val)
       return;
    }
 
-   reg >>= 2;
-
-   assert(state->ndw + 2 <= SI_PM4_MAX_DW);
+   si_pm4_set_reg_custom(state, reg, val, opcode, 0);
+}
 
-   if (opcode != state->last_opcode || reg != (state->last_reg + 1)) {
-      si_pm4_cmd_begin(state, opcode);
-      state->pm4[state->ndw++] = reg;
-   }
+void si_pm4_set_reg_idx3(struct si_pm4_state *state, unsigned reg, uint32_t val)
+{
+   SI_CHECK_SHADOWED_REGS(reg, 1);
 
-   state->last_reg = reg;
-   state->pm4[state->ndw++] = val;
-   si_pm4_cmd_end(state, false);
+   si_pm4_set_reg_custom(state, reg - SI_SH_REG_OFFSET, val, PKT3_SET_SH_REG_INDEX, 3);
 }
 
 void si_pm4_clear_state(struct si_pm4_state *state)
@@ -119,7 +141,7 @@ void si_pm4_emit(struct si_context *sctx, struct si_pm4_state *state)
 
    if (state->is_shader) {
       radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, ((struct si_shader*)state)->bo,
-                                RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
+                                RADEON_USAGE_READ | RADEON_PRIO_SHADER_BINARY);
    }
 
    radeon_begin(cs);