Import Mesa 22.3.7

33 files changed, 322 insertions, 142 deletions

diff --git a/lib/mesa/src/gallium/drivers/crocus/crocus_context.c b/lib/mesa/src/gallium/drivers/crocus/crocus_context.c
index 903be3585..77ddb2e52 100644
--- a/lib/mesa/src/gallium/drivers/crocus/crocus_context.c
+++ b/lib/mesa/src/gallium/drivers/crocus/crocus_context.c
@@ -61,7 +61,7 @@ crocus_init_identifier_bo(struct crocus_context *ice)
 
    ice->workaround_bo->kflags |= EXEC_OBJECT_CAPTURE;
    ice->workaround_offset = ALIGN(
-      intel_debug_write_identifiers(bo_map, 4096, "Crocus") + 8, 8);
+      intel_debug_write_identifiers(bo_map, 4096, "Crocus"), 32);
 
    crocus_bo_unmap(ice->workaround_bo);
 
diff --git a/lib/mesa/src/gallium/drivers/crocus/crocus_resource.c b/lib/mesa/src/gallium/drivers/crocus/crocus_resource.c
index 7b4d50a66..789a04db1 100644
--- a/lib/mesa/src/gallium/drivers/crocus/crocus_resource.c
+++ b/lib/mesa/src/gallium/drivers/crocus/crocus_resource.c
@@ -189,11 +189,8 @@ crocus_resource_configure_main(const struct crocus_screen *screen,
 
       tiling_flags = 1 << res->mod_info->tiling;
    } else {
-      if (templ->bind & PIPE_BIND_RENDER_TARGET && devinfo->ver < 6) {
-         modifier = I915_FORMAT_MOD_X_TILED;
-         res->mod_info = isl_drm_modifier_get_info(modifier);
-         tiling_flags = 1 << res->mod_info->tiling;
-      }
+      if (templ->bind & PIPE_BIND_RENDER_TARGET && devinfo->ver < 6)
+         tiling_flags &= ISL_TILING_LINEAR_BIT | ISL_TILING_X_BIT;
       /* Use linear for staging buffers */
       if (templ->usage == PIPE_USAGE_STAGING ||
           templ->bind & (PIPE_BIND_LINEAR | PIPE_BIND_CURSOR) )
diff --git a/lib/mesa/src/gallium/drivers/d3d12/d3d12_video_dec_vp9.cpp b/lib/mesa/src/gallium/drivers/d3d12/d3d12_video_dec_vp9.cpp
index 26638d429..0e7c5b45c 100644
--- a/lib/mesa/src/gallium/drivers/d3d12/d3d12_video_dec_vp9.cpp
+++ b/lib/mesa/src/gallium/drivers/d3d12/d3d12_video_dec_vp9.cpp
@@ -310,7 +310,7 @@ d3d12_video_decoder_dxva_picparams_from_pipe_picparams_vp9(
          dxvaStructure.ref_frame_coded_width[i]  = pipe_vp9->ref[i]->width;
          dxvaStructure.ref_frame_coded_height[i] = pipe_vp9->ref[i]->height;
       } else
-         dxvaStructure.ref_frame_map[i].bPicEntry = DXVA_VP9_INVALID_PICTURE_INDEX;
+         dxvaStructure.ref_frame_map[i].bPicEntry = DXVA_VP9_INVALID_PICTURE_ENTRY;
    }
 
    /* DXVA spec The enums and indices for ref_frame_sign_bias[] are defined */
@@ -319,7 +319,7 @@ d3d12_video_decoder_dxva_picparams_from_pipe_picparams_vp9(
    const uint8_t signbias_alt_index = 3;
 
    /* AssociatedFlag When Index7Bits does not contain an index to a valid uncompressed surface, the value shall be set to 127, to indicate that the index is invalid. */
-   memset(&dxvaStructure.frame_refs[0], DXVA_VP9_INVALID_PICTURE_INDEX, sizeof(dxvaStructure.frame_refs));
+   memset(&dxvaStructure.frame_refs[0], DXVA_VP9_INVALID_PICTURE_ENTRY, sizeof(dxvaStructure.frame_refs));
 
    if (pipe_vp9->ref[pipe_vp9->picture_parameter.pic_fields.last_ref_frame]) {
       /* AssociatedFlag When Index7Bits does not contain an index to a valid uncompressed surface, the value shall be set to 127, to indicate that the index is invalid. */
@@ -348,10 +348,16 @@ d3d12_video_decoder_dxva_picparams_from_pipe_picparams_vp9(
    dxvaStructure.filter_level    = pipe_vp9->picture_parameter.filter_level;
    dxvaStructure.sharpness_level = pipe_vp9->picture_parameter.sharpness_level;
 
-   bool use_last_frame_mvs = !pipe_vp9->picture_parameter.pic_fields.error_resilient_mode && pipe_vp9->picture_parameter.pic_fields.show_frame;
+   bool use_prev_in_find_mv_refs =
+      !pipe_vp9->picture_parameter.pic_fields.error_resilient_mode &&
+      !(pipe_vp9->picture_parameter.pic_fields.frame_type == 0 /*KEY_FRAME*/ || pipe_vp9->picture_parameter.pic_fields.intra_only) &&
+      pipe_vp9->picture_parameter.pic_fields.prev_show_frame &&
+      pipe_vp9->picture_parameter.frame_width == pipe_vp9->picture_parameter.prev_frame_width &&
+      pipe_vp9->picture_parameter.frame_height == pipe_vp9->picture_parameter.prev_frame_height;
+
    dxvaStructure.wControlInfoFlags = (pipe_vp9->picture_parameter.mode_ref_delta_enabled  << 0) |
                            (pipe_vp9->picture_parameter.mode_ref_delta_update             << 1) |
-                           (use_last_frame_mvs                                            << 2) |
+                           (use_prev_in_find_mv_refs                                      << 2) |
                            (0                                                             << 3);
 
    for (uint32_t i = 0; i < 4; i++)
diff --git a/lib/mesa/src/gallium/drivers/d3d12/d3d12_video_dec_vp9.h b/lib/mesa/src/gallium/drivers/d3d12/d3d12_video_dec_vp9.h
index 322daf7bd..24aa032ef 100644
--- a/lib/mesa/src/gallium/drivers/d3d12/d3d12_video_dec_vp9.h
+++ b/lib/mesa/src/gallium/drivers/d3d12/d3d12_video_dec_vp9.h
@@ -27,7 +27,8 @@
 
 #include "d3d12_video_types.h"
 
-constexpr uint16_t DXVA_VP9_INVALID_PICTURE_INDEX = 0xFF;
+constexpr uint16_t DXVA_VP9_INVALID_PICTURE_INDEX = 0x7F;
+constexpr uint16_t DXVA_VP9_INVALID_PICTURE_ENTRY = 0xFF;
 
 #pragma pack(push, BeforeDXVApacking, 1)
 
diff --git a/lib/mesa/src/gallium/drivers/iris/iris_batch.c b/lib/mesa/src/gallium/drivers/iris/iris_batch.c
index ec32d88cc..d598fd701 100644
--- a/lib/mesa/src/gallium/drivers/iris/iris_batch.c
+++ b/lib/mesa/src/gallium/drivers/iris/iris_batch.c
@@ -1053,10 +1053,10 @@ _iris_batch_flush(struct iris_batch *batch, const char *file, int line)
 
    }
 
-   uint64_t start_ts = intel_ds_begin_submit(batch->ds);
-   uint64_t submission_id = batch->ds->submission_id;
+   uint64_t start_ts = intel_ds_begin_submit(&batch->ds);
+   uint64_t submission_id = batch->ds.submission_id;
    int ret = submit_batch(batch);
-   intel_ds_end_submit(batch->ds, start_ts);
+   intel_ds_end_submit(&batch->ds, start_ts);
 
    /* When batch submission fails, our end-of-batch syncobj remains
     * unsignalled, and in fact is not even considered submitted.
diff --git a/lib/mesa/src/gallium/drivers/iris/iris_batch.h b/lib/mesa/src/gallium/drivers/iris/iris_batch.h
index a1dfa6e63..437352a5a 100644
--- a/lib/mesa/src/gallium/drivers/iris/iris_batch.h
+++ b/lib/mesa/src/gallium/drivers/iris/iris_batch.h
@@ -197,7 +197,7 @@ struct iris_batch {
    struct u_trace trace;
 
    /** Batch wrapper structure for perfetto */
-   struct intel_ds_queue *ds;
+   struct intel_ds_queue ds;
 };
 
 void iris_init_batches(struct iris_context *ice, int priority);
diff --git a/lib/mesa/src/gallium/drivers/iris/iris_state.c b/lib/mesa/src/gallium/drivers/iris/iris_state.c
index b281393dc..30a0ba17e 100644
--- a/lib/mesa/src/gallium/drivers/iris/iris_state.c
+++ b/lib/mesa/src/gallium/drivers/iris/iris_state.c
@@ -2799,6 +2799,21 @@ iris_create_surface(struct pipe_context *ctx,
                                                &res->surf, view,
                                                &isl_surf, view, &offset_B,
                                                &tile_x_el, &tile_y_el);
+
+      /* On Broadwell, HALIGN and VALIGN are specified in pixels and are
+       * hard-coded to align to exactly the block size of the compressed
+       * texture. This means that, when reinterpreted as a non-compressed
+       * texture, the tile offsets may be anything.
+       *
+       * We need them to be multiples of 4 to be usable in RENDER_SURFACE_STATE,
+       * so force the state tracker to take fallback paths if they're not.
+       */
+#if GFX_VER == 8
+      if (tile_x_el % 4 != 0 || tile_y_el % 4 != 0) {
+         ok = false;
+      }
+#endif
+
       if (!ok) {
          free(surf);
          return NULL;
diff --git a/lib/mesa/src/gallium/drivers/iris/iris_utrace.c b/lib/mesa/src/gallium/drivers/iris/iris_utrace.c
index 7f49826d7..e66a56092 100644
--- a/lib/mesa/src/gallium/drivers/iris/iris_utrace.c
+++ b/lib/mesa/src/gallium/drivers/iris/iris_utrace.c
@@ -95,7 +95,7 @@ iris_utrace_delete_flush_data(struct u_trace_context *utctx,
 void iris_utrace_flush(struct iris_batch *batch, uint64_t submission_id)
 {
    struct intel_ds_flush_data *flush_data = malloc(sizeof(*flush_data));
-   intel_ds_flush_data_init(flush_data, batch->ds, submission_id);
+   intel_ds_flush_data_init(flush_data, &batch->ds, submission_id);
    u_trace_flush(&batch->trace, flush_data, false);
 }
 
@@ -122,9 +122,8 @@ void iris_utrace_init(struct iris_context *ice)
                              iris_utrace_delete_flush_data);
 
    for (int i = 0; i < IRIS_BATCH_COUNT; i++) {
-      ice->batches[i].ds =
-         intel_ds_device_add_queue(&ice->ds, "%s",
-                                   iris_batch_name_to_string(i));
+      intel_ds_device_init_queue(&ice->ds, &ice->batches[i].ds, "%s",
+                                 iris_batch_name_to_string(i));
    }
 }
 
diff --git a/lib/mesa/src/gallium/drivers/lima/lima_resource.c b/lib/mesa/src/gallium/drivers/lima/lima_resource.c
index 260212178..ad55fa5c8 100644
--- a/lib/mesa/src/gallium/drivers/lima/lima_resource.c
+++ b/lib/mesa/src/gallium/drivers/lima/lima_resource.c
@@ -59,7 +59,10 @@ lima_resource_create_scanout(struct pipe_screen *pscreen,
    struct lima_screen *screen = lima_screen(pscreen);
    struct renderonly_scanout *scanout;
    struct winsys_handle handle;
-   struct pipe_resource *pres;
+
+   struct lima_resource *res = CALLOC_STRUCT(lima_resource);
+   if (!res)
+      return NULL;
 
    struct pipe_resource scanout_templat = *templat;
    scanout_templat.width0 = width;
@@ -71,20 +74,31 @@ lima_resource_create_scanout(struct pipe_screen *pscreen,
    if (!scanout)
       return NULL;
 
+   res->base = *templat;
+   res->base.screen = pscreen;
+   pipe_reference_init(&res->base.reference, 1);
+   res->levels[0].offset = handle.offset;
+   res->levels[0].stride = handle.stride;
+
    assert(handle.type == WINSYS_HANDLE_TYPE_FD);
-   pres = pscreen->resource_from_handle(pscreen, templat, &handle,
-                                        PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE);
+   res->bo = lima_bo_import(screen, &handle);
+   if (!res->bo) {
+      FREE(res);
+      return NULL;
+   }
+
+   res->modifier_constant = true;
 
    close(handle.handle);
-   if (!pres) {
+   if (!res->bo) {
       renderonly_scanout_destroy(scanout, screen->ro);
+      FREE(res);
       return NULL;
    }
 
-   struct lima_resource *res = lima_resource(pres);
    res->scanout = scanout;
 
-   return pres;
+   return &res->base;
 }
 
 static uint32_t
diff --git a/lib/mesa/src/gallium/drivers/radeonsi/driinfo_radeonsi.h b/lib/mesa/src/gallium/drivers/radeonsi/driinfo_radeonsi.h
index e8a2b4674..7cfe86175 100644
--- a/lib/mesa/src/gallium/drivers/radeonsi/driinfo_radeonsi.h
+++ b/lib/mesa/src/gallium/drivers/radeonsi/driinfo_radeonsi.h
@@ -1,7 +1,6 @@
 // DriConf options specific to radeonsi
 DRI_CONF_SECTION_PERFORMANCE
 DRI_CONF_ADAPTIVE_SYNC(true)
-DRI_CONF_MESA_GLTHREAD(true)
 DRI_CONF_SECTION_END
 
 DRI_CONF_SECTION_DEBUG
diff --git a/lib/mesa/src/gallium/drivers/radeonsi/radeon_vcn_dec.c b/lib/mesa/src/gallium/drivers/radeonsi/radeon_vcn_dec.c
index 414a8d699..1c8038325 100644
--- a/lib/mesa/src/gallium/drivers/radeonsi/radeon_vcn_dec.c
+++ b/lib/mesa/src/gallium/drivers/radeonsi/radeon_vcn_dec.c
@@ -278,6 +278,20 @@ static rvcn_dec_message_avc_t get_h264_msg(struct radeon_decoder *dec,
       }
    }
 
+   /* if reference picture exists, however no reference picture found at the end
+      curr_pic_ref_frame_num == 0, which is not reasonable, should be corrected. */
+   if (result.used_for_reference_flags && (result.curr_pic_ref_frame_num == 0)) {
+      for (i = 0; i < ARRAY_SIZE(result.ref_frame_list); i++) {
+         result.ref_frame_list[i] = pic->ref[i] ?
+                (uintptr_t)vl_video_buffer_get_associated_data(pic->ref[i], &dec->base) : 0xff;
+         if (result.ref_frame_list[i] != 0xff) {
+            result.curr_pic_ref_frame_num++;
+            result.non_existing_frame_flags &= ~(1 << i);
+            break;
+         }
+      }
+   }
+
    for (i = 0; i < ARRAY_SIZE(result.ref_frame_list); i++) {
       if (result.ref_frame_list[i] != 0xff) {
          dec->h264_valid_ref_num[i]         = result.frame_num_list[i];
@@ -3160,7 +3174,8 @@ struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
    case CHIP_GFX1100:
    case CHIP_GFX1101:
    case CHIP_GFX1102:
-   case CHIP_GFX1103:
+   case CHIP_GFX1103_R1:
+   case CHIP_GFX1103_R2:
       dec->jpg.direct_reg = true;
       dec->addr_gfx_mode = RDECODE_ARRAY_MODE_ADDRLIB_SEL_GFX11;
       dec->av1_version = RDECODE_AV1_VER_1;
diff --git a/lib/mesa/src/gallium/drivers/radeonsi/si_sdma_copy_image.c b/lib/mesa/src/gallium/drivers/radeonsi/si_sdma_copy_image.c
index b1b408b8f..c5e8b9eed 100644
--- a/lib/mesa/src/gallium/drivers/radeonsi/si_sdma_copy_image.c
+++ b/lib/mesa/src/gallium/drivers/radeonsi/si_sdma_copy_image.c
@@ -139,7 +139,7 @@ bool si_sdma_v4_v5_copy_texture(struct si_context *sctx, struct si_texture *sdst
       radeon_emit(CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
                                   CIK_SDMA_COPY_SUB_OPCODE_LINEAR,
                                   (tmz ? 4 : 0)));
-      radeon_emit(bytes);
+      radeon_emit(bytes - 1);
       radeon_emit(0);
       radeon_emit(src_address);
       radeon_emit(src_address >> 32);
diff --git a/lib/mesa/src/gallium/drivers/radeonsi/si_shader_llvm_ps.c b/lib/mesa/src/gallium/drivers/radeonsi/si_shader_llvm_ps.c
index 218a3c2a3..9e717b926 100644
--- a/lib/mesa/src/gallium/drivers/radeonsi/si_shader_llvm_ps.c
+++ b/lib/mesa/src/gallium/drivers/radeonsi/si_shader_llvm_ps.c
@@ -570,7 +570,8 @@ static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
  * overriden by other states. (e.g. per-sample interpolation)
  * Interpolated colors are stored after the preloaded VGPRs.
  */
-void si_llvm_build_ps_prolog(struct si_shader_context *ctx, union si_shader_part_key *key)
+void si_llvm_build_ps_prolog(struct si_shader_context *ctx, union si_shader_part_key *key,
+                             bool separate_prolog)
 {
    LLVMValueRef ret, func;
    int num_returns, i, num_color_channels;
@@ -694,13 +695,13 @@ void si_llvm_build_ps_prolog(struct si_shader_context *ctx, union si_shader_part
 
       /* Read LINEAR_SAMPLE. */
       for (i = 0; i < 2; i++)
-         linear_sample[i] = LLVMGetParam(func, base + 6 + i);
+         linear_sample[i] = LLVMGetParam(func, base + (separate_prolog ? 6 : 9) + i);
       /* Overwrite LINEAR_CENTER. */
       for (i = 0; i < 2; i++)
-         ret = LLVMBuildInsertValue(ctx->ac.builder, ret, linear_sample[i], base + 8 + i, "");
+         ret = LLVMBuildInsertValue(ctx->ac.builder, ret, linear_sample[i], base + (separate_prolog ? 8 : 11) + i, "");
       /* Overwrite LINEAR_CENTROID. */
       for (i = 0; i < 2; i++)
-         ret = LLVMBuildInsertValue(ctx->ac.builder, ret, linear_sample[i], base + 10 + i, "");
+         ret = LLVMBuildInsertValue(ctx->ac.builder, ret, linear_sample[i], base + (separate_prolog ? 10 : 13) + i, "");
    }
 
    /* Force center interpolation. */
@@ -825,7 +826,8 @@ void si_llvm_build_ps_prolog(struct si_shader_context *ctx, union si_shader_part
  * Build the pixel shader epilog function. This handles everything that must be
  * emulated for pixel shader exports. (alpha-test, format conversions, etc)
  */
-void si_llvm_build_ps_epilog(struct si_shader_context *ctx, union si_shader_part_key *key)
+void si_llvm_build_ps_epilog(struct si_shader_context *ctx, union si_shader_part_key *key,
+                             UNUSED bool separate_epilog)
 {
    int i;
    struct si_ps_exports exp = {};
@@ -947,7 +949,7 @@ void si_llvm_build_monolithic_ps(struct si_shader_context *ctx, struct si_shader
    si_get_ps_prolog_key(shader, &prolog_key, false);
 
    if (si_need_ps_prolog(&prolog_key)) {
-      si_llvm_build_ps_prolog(ctx, &prolog_key);
+      si_llvm_build_ps_prolog(ctx, &prolog_key, false);
       parts[num_parts++] = ctx->main_fn;
    }
 
@@ -956,7 +958,7 @@ void si_llvm_build_monolithic_ps(struct si_shader_context *ctx, struct si_shader
 
    union si_shader_part_key epilog_key;
    si_get_ps_epilog_key(shader, &epilog_key);
-   si_llvm_build_ps_epilog(ctx, &epilog_key);
+   si_llvm_build_ps_epilog(ctx, &epilog_key, false);
    parts[num_parts++] = ctx->main_fn;
 
    si_build_wrapper_function(ctx, parts, num_parts, main_index, 0, main_arg_types, false);
diff --git a/lib/mesa/src/gallium/drivers/radeonsi/si_shader_llvm_tess.c b/lib/mesa/src/gallium/drivers/radeonsi/si_shader_llvm_tess.c
index 5a5665a51..03da1e3e7 100644
--- a/lib/mesa/src/gallium/drivers/radeonsi/si_shader_llvm_tess.c
+++ b/lib/mesa/src/gallium/drivers/radeonsi/si_shader_llvm_tess.c
@@ -602,7 +602,8 @@ void si_llvm_ls_build_end(struct si_shader_context *ctx)
  * Compile the TCS epilog function. This writes tesselation factors to memory
  * based on the output primitive type of the tesselator (determined by TES).
  */
-void si_llvm_build_tcs_epilog(struct si_shader_context *ctx, union si_shader_part_key *key)
+void si_llvm_build_tcs_epilog(struct si_shader_context *ctx, union si_shader_part_key *key,
+                              UNUSED bool separate_epilog)
 {
    memset(&ctx->args, 0, sizeof(ctx->args));
 
diff --git a/lib/mesa/src/gallium/drivers/radeonsi/si_shader_llvm_vs.c b/lib/mesa/src/gallium/drivers/radeonsi/si_shader_llvm_vs.c
index 950daf49f..ca6c4c6f8 100644
--- a/lib/mesa/src/gallium/drivers/radeonsi/si_shader_llvm_vs.c
+++ b/lib/mesa/src/gallium/drivers/radeonsi/si_shader_llvm_vs.c
@@ -923,7 +923,8 @@ void si_llvm_vs_build_end(struct si_shader_context *ctx)
  *   (InstanceID + StartInstance),
  *   (InstanceID / 2 + StartInstance)
  */
-void si_llvm_build_vs_prolog(struct si_shader_context *ctx, union si_shader_part_key *key)
+void si_llvm_build_vs_prolog(struct si_shader_context *ctx, union si_shader_part_key *key,
+                             UNUSED bool separate_prolog)
 {
    LLVMTypeRef *returns;
    LLVMValueRef ret, func;
diff --git a/lib/mesa/src/gallium/drivers/radeonsi/si_state_shaders.cpp b/lib/mesa/src/gallium/drivers/radeonsi/si_state_shaders.cpp
index 16012344a..b3c0f85a3 100644
--- a/lib/mesa/src/gallium/drivers/radeonsi/si_state_shaders.cpp
+++ b/lib/mesa/src/gallium/drivers/radeonsi/si_state_shaders.cpp
@@ -673,7 +673,7 @@ unsigned si_get_shader_prefetch_size(struct si_shader *shader)
    /* Return 0 for some A0 chips only. Other chips don't need it. */
    if ((shader->selector->screen->info.family == CHIP_GFX1100 ||
         shader->selector->screen->info.family == CHIP_GFX1102 ||
-        shader->selector->screen->info.family == CHIP_GFX1103) &&
+        shader->selector->screen->info.family == CHIP_GFX1103_R1) &&
        shader->selector->screen->info.chip_rev == 0)
       return 0;
 
@@ -1234,7 +1234,8 @@ static void gfx10_emit_shader_ngg_tail(struct si_context *sctx, struct si_shader
                        (sctx->gfx_level >= GFX10 ? radeon_set_sh_reg_idx3_func : radeon_set_sh_reg_func));
       ac_set_reg_cu_en(&sctx->gfx_cs, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
                        shader->ctx_reg.ngg.spi_shader_pgm_rsrc4_gs,
-                       C_00B204_CU_EN_GFX10, 16, &sctx->screen->info,
+                       sctx->gfx_level >= GFX11 ? C_00B204_CU_EN_GFX11 : C_00B204_CU_EN_GFX10, 16,
+                       &sctx->screen->info,
                        (void (*)(void*, unsigned, uint32_t))
                        (sctx->gfx_level >= GFX10 ? radeon_set_sh_reg_idx3_func : radeon_set_sh_reg_func));
       sctx->tracked_regs.reg_saved &= ~BITFIELD64_BIT(SI_TRACKED_SPI_SHADER_PGM_RSRC4_GS) &
diff --git a/lib/mesa/src/gallium/drivers/zink/VP_ZINK_requirements.json b/lib/mesa/src/gallium/drivers/zink/VP_ZINK_requirements.json
index f42f4c8d7..83d972b83 100644
--- a/lib/mesa/src/gallium/drivers/zink/VP_ZINK_requirements.json
+++ b/lib/mesa/src/gallium/drivers/zink/VP_ZINK_requirements.json
@@ -31,9 +31,15 @@
                 "VkPhysicalDeviceCustomBorderColorFeaturesEXT": {
                     "customBorderColorWithoutFormat": true
                 },
+                "VkPhysicalDeviceBorderColorSwizzleFeaturesEXT": {
+                    "borderColorSwizzleFromImage": true
+                },
                 "VkPhysicalDeviceLineRasterizationFeaturesEXT": {
                     "rectangularLines": true,
                     "bresenhamLines": true
+                },
+                "VkPhysicalDeviceProvokingVertexFeaturesEXT": {
+                    "provokingVertexLast": true
                 }
             },
             "properties": {
@@ -49,13 +55,22 @@
             "features": {
                 "VkPhysicalDeviceScalarBlockLayoutFeaturesEXT": {
                     "scalarBlockLayout": true
+                },
+                "VkPhysicalDeviceTimelineSemaphoreFeaturesKHR": {
+                    "timelineSemaphore": true
+                },
+                "VkPhysicalDeviceImagelessFramebufferFeatures": {
+                    "imagelessFramebuffer": true
                 }
             }
         },
         "gl21_baseline_vk12": {
             "features": {
                 "VkPhysicalDeviceVulkan12Features": {
-                    "scalarBlockLayout": true
+                    "scalarBlockLayout": true,
+                    "drawIndirectCount": true,
+                    "imagelessFramebuffer": true,
+                    "timelineSemaphore": true
                 }
             }
         },
@@ -72,6 +87,12 @@
             "features": {
                 "VkPhysicalDeviceFeatures": {
                     "independentBlend": true
+                },
+                "VkPhysicalDeviceTransformFeedbackFeaturesEXT": {
+                    "transformFeedback": true
+                },
+                "VkPhysicalDeviceConditionalRenderingFeaturesEXT": {
+                    "conditionalRendering": true
                 }
             }
         },
@@ -107,6 +128,9 @@
                 "VkPhysicalDeviceFeatures": {
                     "occlusionQueryPrecise": true,
                     "dualSrcBlend": true
+                },
+                "VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT": {
+                    "vertexAttributeInstanceRateDivisor": true
                 }
             }
         },
@@ -170,6 +194,9 @@
                     "shaderStorageImageWriteWithoutFormat": true,
                     "vertexPipelineStoresAndAtomics": true,
                     "fragmentStoresAndAtomics": true
+                },
+                "VkPhysicalDeviceImage2DViewOf3DFeaturesEXT": {
+                    "image2DViewOf3D": true
                 }
             }
         },
@@ -271,9 +298,6 @@
             }
         },
         "gl44_baseline": {
-            "extensions": {
-                "VK_KHR_sampler_mirror_clamp_to_edge": 1
-            },
             "formats": {
                 "VK_FORMAT_B10G11R11_UFLOAT_PACK32": {
                     "VkFormatProperties": {
@@ -284,6 +308,18 @@
                 }
             }
         },
+        "gl44_baseline_ext": {
+            "extensions": {
+                "VK_KHR_sampler_mirror_clamp_to_edge": 1
+            }
+        },
+        "gl44_baseline_vk12": {
+            "features": {
+                "VkPhysicalDeviceVulkan12Features": {
+                    "samplerMirrorClampToEdge": true
+                }
+            }
+        },
         "gl45_baseline": {
             "features": {
                 "VkPhysicalDeviceFeatures": {
@@ -698,7 +734,8 @@
                 "gl42_baseline",
                 [ "gl42_baseline_vk10", "gl42_baseline_vk12" ],
                 "gl43_baseline",
-                "gl44_baseline"
+                "gl44_baseline",
+                [ "gl44_baseline_ext", "gl44_baseline_vk12" ]
             ]
         },
         "VP_ZINK_gl45_baseline": {
@@ -720,6 +757,7 @@
                 [ "gl42_baseline_vk10", "gl42_baseline_vk12" ],
                 "gl43_baseline",
                 "gl44_baseline",
+                [ "gl44_baseline_ext", "gl44_baseline_vk12" ],
                 "gl45_baseline"
             ]
         },
@@ -742,6 +780,7 @@
                 [ "gl42_baseline_vk10", "gl42_baseline_vk12" ],
                 "gl43_baseline",
                 "gl44_baseline",
+                [ "gl44_baseline_ext", "gl44_baseline_vk12" ],
                 "gl45_baseline",
                 "gl46_baseline"
             ]
@@ -765,6 +804,7 @@
                 [ "gl42_baseline_vk10", "gl42_baseline_vk12" ],
                 "gl43_baseline",
                 "gl44_baseline",
+                [ "gl44_baseline_ext", "gl44_baseline_vk12" ],
                 "gl45_baseline",
                 "gl46_baseline",
                 "gl46_optimal",
diff --git a/lib/mesa/src/gallium/drivers/zink/ci/zink-lvp-fails.txt b/lib/mesa/src/gallium/drivers/zink/ci/zink-lvp-fails.txt
index e61edddab..54d5bbc7e 100644
--- a/lib/mesa/src/gallium/drivers/zink/ci/zink-lvp-fails.txt
+++ b/lib/mesa/src/gallium/drivers/zink/ci/zink-lvp-fails.txt
@@ -53,7 +53,6 @@ glx@glx_ext_import_context@imported context has same context id,Fail
 glx@glx_ext_import_context@make current- multi process,Fail
 glx@glx_ext_import_context@make current- single process,Fail
 glx@glx_ext_import_context@query context info,Fail
-shaders@glsl-fs-pointcoord,Fail
 shaders@point-vertex-id divisor,Fail
 shaders@point-vertex-id gl_instanceid,Fail
 shaders@point-vertex-id gl_instanceid divisor,Fail
@@ -92,9 +91,7 @@ spec@!opengl 2.0@gl-2.0-edgeflag-immediate,Fail
 spec@!opengl 2.1@pbo,Fail
 spec@!opengl 2.1@pbo@test_polygon_stip,Fail
 spec@!opengl 2.1@polygon-stipple-fs,Fail
-spec@!opengl es 2.0@glsl-fs-pointcoord,Fail
 spec@arb_depth_texture@depth-tex-modes,Fail
-spec@arb_framebuffer_object@fbo-gl_pointcoord,Fail
 spec@arb_gpu_shader_fp64@execution@arb_gpu_shader_fp64-tf-separate,Fail
 spec@arb_pipeline_statistics_query@arb_pipeline_statistics_query-frag,Fail
 spec@arb_point_sprite@arb_point_sprite-checkerboard,Fail
@@ -156,33 +153,6 @@ spec@ext_framebuffer_multisample@interpolation 4 centroid-disabled,Fail
 spec@ext_framebuffer_multisample@interpolation 4 centroid-edges,Fail
 spec@ext_framebuffer_multisample@interpolation 4 non-centroid-deriv-disabled,Fail
 spec@ext_framebuffer_multisample@interpolation 4 non-centroid-disabled,Fail
-spec@ext_image_dma_buf_import@ext_image_dma_buf_import-intel_external_sampler_only,Fail
-spec@ext_image_dma_buf_import@ext_image_dma_buf_import-invalid_attributes,Fail
-spec@ext_image_dma_buf_import@ext_image_dma_buf_import-invalid_hints,Fail
-spec@ext_image_dma_buf_import@ext_image_dma_buf_import-missing_attributes,Fail
-spec@ext_image_dma_buf_import@ext_image_dma_buf_import-ownership_transfer,Fail
-spec@ext_image_dma_buf_import@ext_image_dma_buf_import-refcount,Fail
-spec@ext_image_dma_buf_import@ext_image_dma_buf_import-reimport-bug,Fail
-spec@ext_image_dma_buf_import@ext_image_dma_buf_import-sample_argb8888,Fail
-spec@ext_image_dma_buf_import@ext_image_dma_buf_import-sample_ayuv,Fail
-spec@ext_image_dma_buf_import@ext_image_dma_buf_import-sample_nv12,Fail
-spec@ext_image_dma_buf_import@ext_image_dma_buf_import-sample_p010,Fail
-spec@ext_image_dma_buf_import@ext_image_dma_buf_import-sample_p012,Fail
-spec@ext_image_dma_buf_import@ext_image_dma_buf_import-sample_p016,Fail
-spec@ext_image_dma_buf_import@ext_image_dma_buf_import-sample_uyvy,Fail
-spec@ext_image_dma_buf_import@ext_image_dma_buf_import-sample_xrgb8888,Fail
-spec@ext_image_dma_buf_import@ext_image_dma_buf_import-sample_xyuv,Fail
-spec@ext_image_dma_buf_import@ext_image_dma_buf_import-sample_y210,Fail
-spec@ext_image_dma_buf_import@ext_image_dma_buf_import-sample_y212,Fail
-spec@ext_image_dma_buf_import@ext_image_dma_buf_import-sample_y216,Fail
-spec@ext_image_dma_buf_import@ext_image_dma_buf_import-sample_y410,Fail
-spec@ext_image_dma_buf_import@ext_image_dma_buf_import-sample_y412,Fail
-spec@ext_image_dma_buf_import@ext_image_dma_buf_import-sample_y416,Fail
-spec@ext_image_dma_buf_import@ext_image_dma_buf_import-sample_yuv420,Fail
-spec@ext_image_dma_buf_import@ext_image_dma_buf_import-sample_yuyv,Fail
-spec@ext_image_dma_buf_import@ext_image_dma_buf_import-sample_yvu420,Fail
-spec@ext_image_dma_buf_import@ext_image_dma_buf_import-transcode-nv12-as-r8-gr88,Fail
-spec@ext_image_dma_buf_import@ext_image_dma_buf_import-unsupported_format,Fail
 spec@ext_packed_float@query-rgba-signed-components,Fail
 spec@ext_texture_swizzle@depth_texture_mode_and_swizzle,Fail
 spec@intel_performance_query@intel_performance_query-issue_2235,Fail
diff --git a/lib/mesa/src/gallium/drivers/zink/ci/zink-radv-fails.txt b/lib/mesa/src/gallium/drivers/zink/ci/zink-radv-fails.txt
index 3fa433d8f..02c86646a 100644
--- a/lib/mesa/src/gallium/drivers/zink/ci/zink-radv-fails.txt
+++ b/lib/mesa/src/gallium/drivers/zink/ci/zink-radv-fails.txt
@@ -38,7 +38,6 @@ glx@glx-swap-pixmap-bad,Fail
 spec@arb_framebuffer_object@fbo-blit-scaled-linear,Fail
 
 
-shaders@glsl-fs-pointcoord,Fail
 shaders@point-vertex-id divisor,Fail
 shaders@point-vertex-id gl_instanceid divisor,Fail
 shaders@point-vertex-id gl_instanceid,Fail
@@ -59,7 +58,6 @@ spec@arb_fragment_program_shadow@txp-shadow2d,Fail
 spec@arb_fragment_program_shadow@txp-shadow2drect,Fail
 spec@arb_framebuffer_no_attachments@arb_framebuffer_no_attachments-query,Fail
 spec@arb_framebuffer_no_attachments@arb_framebuffer_no_attachments-query@MS8,Fail
-spec@arb_framebuffer_object@fbo-gl_pointcoord,Fail
 spec@arb_gpu_shader_fp64@execution@arb_gpu_shader_fp64-tf-separate,Fail
 spec@arb_gpu_shader_fp64@execution@conversion@frag-conversion-explicit-dmat2-mat2,Fail
 spec@arb_gpu_shader_fp64@execution@conversion@frag-conversion-explicit-dmat2x3-mat2x3,Fail
@@ -388,7 +386,6 @@ spec@!opengl 2.1@pbo,Fail
 spec@!opengl 2.1@pbo@test_polygon_stip,Fail
 spec@!opengl 2.1@polygon-stipple-fs,Fail
 spec@!opengl 3.0@clearbuffer-depth-cs-probe,Fail
-spec@!opengl es 2.0@glsl-fs-pointcoord,Fail
 spec@!opengl 1.0@rasterpos@glsl_vs_gs_linked,Fail
 spec@!opengl 1.0@rasterpos@glsl_vs_tes_linked,Fail
 
diff --git a/lib/mesa/src/gallium/drivers/zink/zink_blit.c b/lib/mesa/src/gallium/drivers/zink/zink_blit.c
index 135378f4d..df718afc7 100644
--- a/lib/mesa/src/gallium/drivers/zink/zink_blit.c
+++ b/lib/mesa/src/gallium/drivers/zink/zink_blit.c
@@ -128,7 +128,7 @@ blit_native(struct zink_context *ctx, const struct pipe_blit_info *info, bool *n
       return false;
 
    if (util_format_is_depth_or_stencil(info->dst.format) &&
-       info->dst.format != info->src.format)
+       (info->dst.format != info->src.format || info->filter == PIPE_TEX_FILTER_LINEAR))
       return false;
 
    /* vkCmdBlitImage must not be used for multisampled source or destination images. */
@@ -252,7 +252,8 @@ blit_native(struct zink_context *ctx, const struct pipe_blit_info *info, bool *n
    VKCTX(CmdBlitImage)(cmdbuf, src->obj->image, src->layout,
                   dst->obj->image, dst->layout,
                   1, &region,
-                  zink_filter(info->filter));
+                  /* VUID-vkCmdBlitImage-srcImage-00232: zs formats must use NEAREST filtering */
+                  util_format_is_depth_or_stencil(info->src.format) ? VK_FILTER_NEAREST : zink_filter(info->filter));
 
    return true;
 }
@@ -355,7 +356,7 @@ zink_blit(struct pipe_context *pctx,
       util_blitter_clear_depth_stencil(ctx->blitter, dst_view, PIPE_CLEAR_STENCIL,
                                        0, 0, info->dst.box.x, info->dst.box.y,
                                        info->dst.box.width, info->dst.box.height);
-      zink_blit_begin(ctx, ZINK_BLIT_SAVE_FB | ZINK_BLIT_SAVE_FS | ZINK_BLIT_SAVE_TEXTURES);
+      zink_blit_begin(ctx, ZINK_BLIT_SAVE_FB | ZINK_BLIT_SAVE_FS | ZINK_BLIT_SAVE_TEXTURES | ZINK_BLIT_SAVE_FS_CONST_BUF);
       util_blitter_stencil_fallback(ctx->blitter,
                                     info->dst.resource,
                                     info->dst.level,
@@ -390,8 +391,10 @@ zink_blit_begin(struct zink_context *ctx, enum zink_blit_flags flags)
    util_blitter_save_rasterizer(ctx->blitter, ctx->rast_state);
    util_blitter_save_so_targets(ctx->blitter, ctx->num_so_targets, ctx->so_targets);
 
-   if (flags & ZINK_BLIT_SAVE_FS) {
+   if (flags & ZINK_BLIT_SAVE_FS_CONST_BUF)
       util_blitter_save_fragment_constant_buffer_slot(ctx->blitter, ctx->ubos[MESA_SHADER_FRAGMENT]);
+
+   if (flags & ZINK_BLIT_SAVE_FS) {
       util_blitter_save_blend(ctx->blitter, ctx->gfx_pipeline_state.blend_state);
       util_blitter_save_depth_stencil_alpha(ctx->blitter, ctx->dsa_state);
       util_blitter_save_stencil_ref(ctx->blitter, &ctx->stencil_ref);
diff --git a/lib/mesa/src/gallium/drivers/zink/zink_bo.h b/lib/mesa/src/gallium/drivers/zink/zink_bo.h
index 42b1fc643..42e5ec225 100644
--- a/lib/mesa/src/gallium/drivers/zink/zink_bo.h
+++ b/lib/mesa/src/gallium/drivers/zink/zink_bo.h
@@ -30,7 +30,6 @@
 #include "zink_batch.h"
 
 #define VK_VIS_VRAM (VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT | VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT)
-#define VK_STAGING_RAM (VK_MEMORY_PROPERTY_HOST_COHERENT_BIT | VK_MEMORY_PROPERTY_HOST_CACHED_BIT)
 #define VK_LAZY_VRAM (VK_MEMORY_PROPERTY_LAZILY_ALLOCATED_BIT | VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT)
 
 
diff --git a/lib/mesa/src/gallium/drivers/zink/zink_clear.c b/lib/mesa/src/gallium/drivers/zink/zink_clear.c
index cfb66df3f..1db046757 100644
--- a/lib/mesa/src/gallium/drivers/zink/zink_clear.c
+++ b/lib/mesa/src/gallium/drivers/zink/zink_clear.c
@@ -455,8 +455,10 @@ zink_clear_texture(struct pipe_context *pctx,
       util_blitter_save_framebuffer(ctx->blitter, &ctx->fb_state);
       set_clear_fb(pctx, surf, NULL);
       ctx->blitting = true;
+      ctx->queries_disabled = true;
       pctx->clear(pctx, PIPE_CLEAR_COLOR0, &scissor, &color, 0, 0);
       util_blitter_restore_fb_state(ctx->blitter);
+      ctx->queries_disabled = false;
       ctx->blitting = false;
    } else {
       float depth = 0.0;
@@ -477,8 +479,10 @@ zink_clear_texture(struct pipe_context *pctx,
       util_blitter_save_framebuffer(ctx->blitter, &ctx->fb_state);
       ctx->blitting = true;
       set_clear_fb(pctx, NULL, surf);
+      ctx->queries_disabled = true;
       pctx->clear(pctx, flags, &scissor, NULL, depth, stencil);
       util_blitter_restore_fb_state(ctx->blitter);
+      ctx->queries_disabled = false;
       ctx->blitting = false;
    }
    /* this will never destroy the surface */
diff --git a/lib/mesa/src/gallium/drivers/zink/zink_compiler.c b/lib/mesa/src/gallium/drivers/zink/zink_compiler.c
index c59c4d5ae..a23212aa8 100644
--- a/lib/mesa/src/gallium/drivers/zink/zink_compiler.c
+++ b/lib/mesa/src/gallium/drivers/zink/zink_compiler.c
@@ -2207,6 +2207,32 @@ prune_io(nir_shader *nir)
    }
 }
 
+static bool
+invert_point_coord_instr(nir_builder *b, nir_instr *instr, void *data)
+{
+   if (instr->type != nir_instr_type_intrinsic)
+      return false;
+   nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
+   if (intr->intrinsic != nir_intrinsic_load_deref)
+      return false;
+   nir_variable *deref_var = nir_intrinsic_get_var(intr, 0);
+   if (deref_var->data.location != VARYING_SLOT_PNTC)
+      return false;
+   b->cursor = nir_after_instr(instr);
+   nir_ssa_def *def = nir_vec2(b, nir_channel(b, &intr->dest.ssa, 0),
+                                  nir_fsub(b, nir_imm_float(b, 1.0), nir_channel(b, &intr->dest.ssa, 1)));
+   nir_ssa_def_rewrite_uses_after(&intr->dest.ssa, def, def->parent_instr);
+   return true;
+}
+
+static bool
+invert_point_coord(nir_shader *nir)
+{
+   if (!(nir->info.inputs_read & BITFIELD64_BIT(VARYING_SLOT_PNTC)))
+      return false;
+   return nir_shader_instructions_pass(nir, invert_point_coord_instr, nir_metadata_dominance, NULL);
+}
+
 VkShaderModule
 zink_shader_compile(struct zink_screen *screen, struct zink_shader *zs, nir_shader *base_nir, const struct zink_shader_key *key)
 {
@@ -2283,10 +2309,10 @@ zink_shader_compile(struct zink_screen *screen, struct zink_shader *zs, nir_shad
          if (zink_fs_key(key)->force_dual_color_blend && nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_DATA1)) {
             NIR_PASS_V(nir, lower_dual_blend);
          }
-         if (zink_fs_key(key)->coord_replace_bits) {
-            NIR_PASS_V(nir, nir_lower_texcoord_replace, zink_fs_key(key)->coord_replace_bits,
-                     false, zink_fs_key(key)->coord_replace_yinvert);
-         }
+         if (zink_fs_key(key)->coord_replace_bits)
+            NIR_PASS_V(nir, nir_lower_texcoord_replace, zink_fs_key(key)->coord_replace_bits, false, false);
+         if (zink_fs_key(key)->point_coord_yinvert)
+            NIR_PASS_V(nir, invert_point_coord);
          if (zink_fs_key(key)->force_persample_interp || zink_fs_key(key)->fbfetch_ms) {
             nir_foreach_shader_in_variable(var, nir)
                var->data.sample = true;
@@ -3368,7 +3394,7 @@ struct zink_shader *
 zink_shader_create(struct zink_screen *screen, struct nir_shader *nir,
                    const struct pipe_stream_output_info *so_info)
 {
-   struct zink_shader *ret = CALLOC_STRUCT(zink_shader);
+   struct zink_shader *ret = rzalloc(NULL, struct zink_shader);
    bool have_psiz = false;
 
    ret->sinfo.have_vulkan_memory_model = screen->info.have_KHR_vulkan_memory_model;
@@ -3482,6 +3508,8 @@ zink_shader_create(struct zink_screen *screen, struct nir_shader *nir,
       ret->sinfo.sampler_mask = sampler_mask;
    }
 
+   unsigned ubo_binding_mask = 0;
+   unsigned ssbo_binding_mask = 0;
    foreach_list_typed_reverse_safe(nir_variable, var, node, &nir->variables) {
       if (_nir_shader_variable_has_mode(var, nir_var_uniform |
                                         nir_var_image |
@@ -3504,13 +3532,14 @@ zink_shader_create(struct zink_screen *screen, struct nir_shader *nir,
 
             if (!var->data.driver_location) {
                ret->has_uniforms = true;
-            } else {
+            } else if (!(ubo_binding_mask & BITFIELD_BIT(binding))) {
                ret->bindings[ztype][ret->num_bindings[ztype]].index = var->data.driver_location;
                ret->bindings[ztype][ret->num_bindings[ztype]].binding = binding;
                ret->bindings[ztype][ret->num_bindings[ztype]].type = vktype;
                ret->bindings[ztype][ret->num_bindings[ztype]].size = glsl_get_length(var->type);
                assert(ret->bindings[ztype][ret->num_bindings[ztype]].size);
                ret->num_bindings[ztype]++;
+               ubo_binding_mask |= BITFIELD_BIT(binding);
             }
          } else if (var->data.mode == nir_var_mem_ssbo) {
             ztype = ZINK_DESCRIPTOR_TYPE_SSBO;
@@ -3519,12 +3548,15 @@ zink_shader_create(struct zink_screen *screen, struct nir_shader *nir,
                                              VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
                                              var->data.driver_location,
                                              screen->compact_descriptors);
-            ret->bindings[ztype][ret->num_bindings[ztype]].index = var->data.driver_location;
-            ret->bindings[ztype][ret->num_bindings[ztype]].binding = var->data.binding;
-            ret->bindings[ztype][ret->num_bindings[ztype]].type = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER;
-            ret->bindings[ztype][ret->num_bindings[ztype]].size = glsl_get_length(var->type);
-            assert(ret->bindings[ztype][ret->num_bindings[ztype]].size);
-            ret->num_bindings[ztype]++;
+            if (!(ssbo_binding_mask & BITFIELD_BIT(var->data.binding))) {
+               ret->bindings[ztype][ret->num_bindings[ztype]].index = var->data.driver_location;
+               ret->bindings[ztype][ret->num_bindings[ztype]].binding = var->data.binding;
+               ret->bindings[ztype][ret->num_bindings[ztype]].type = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER;
+               ret->bindings[ztype][ret->num_bindings[ztype]].size = glsl_get_length(var->type);
+               assert(ret->bindings[ztype][ret->num_bindings[ztype]].size);
+               ret->num_bindings[ztype]++;
+               ssbo_binding_mask |= BITFIELD_BIT(var->data.binding);
+            }
          } else {
             assert(var->data.mode == nir_var_uniform ||
                    var->data.mode == nir_var_image);
@@ -3644,6 +3676,16 @@ zink_shader_free(struct zink_screen *screen, struct zink_shader *shader)
          prog->base.removed = true;
          simple_mtx_unlock(&prog->ctx->program_lock[idx]);
          util_queue_fence_wait(&prog->base.cache_fence);
+
+         for (unsigned r = 0; r < ARRAY_SIZE(prog->pipelines); r++) {
+            for (int i = 0; i < ARRAY_SIZE(prog->pipelines[0]); ++i) {
+               hash_table_foreach(&prog->pipelines[r][i], entry) {
+                  struct zink_gfx_pipeline_cache_entry *pc_entry = entry->data;
+
+                  util_queue_fence_wait(&pc_entry->fence);
+               }
+            }
+         }
       }
       if (stage != MESA_SHADER_TESS_CTRL || !shader->tcs.is_generated) {
          prog->shaders[stage] = NULL;
@@ -3663,7 +3705,7 @@ zink_shader_free(struct zink_screen *screen, struct zink_shader *shader)
    _mesa_set_destroy(shader->programs, NULL);
    ralloc_free(shader->nir);
    ralloc_free(shader->spirv);
-   FREE(shader);
+   ralloc_free(shader);
 }
 
 
@@ -3700,7 +3742,7 @@ void main()
 struct zink_shader *
 zink_shader_tcs_create(struct zink_screen *screen, struct zink_shader *vs, unsigned vertices_per_patch)
 {
-   struct zink_shader *ret = CALLOC_STRUCT(zink_shader);
+   struct zink_shader *ret = rzalloc(NULL, struct zink_shader);
    ret->hash = _mesa_hash_pointer(ret);
    ret->programs = _mesa_pointer_set_create(NULL);
    simple_mtx_init(&ret->lock, mtx_plain);
diff --git a/lib/mesa/src/gallium/drivers/zink/zink_context.c b/lib/mesa/src/gallium/drivers/zink/zink_context.c
index 0cbb0ccad..18bd412f1 100644
--- a/lib/mesa/src/gallium/drivers/zink/zink_context.c
+++ b/lib/mesa/src/gallium/drivers/zink/zink_context.c
@@ -99,6 +99,9 @@ zink_context_destroy(struct pipe_context *pctx)
    struct zink_context *ctx = zink_context(pctx);
    struct zink_screen *screen = zink_screen(pctx->screen);
 
+   struct pipe_framebuffer_state fb = {0};
+   pctx->set_framebuffer_state(pctx, &fb);
+
    if (util_queue_is_initialized(&screen->flush_queue))
       util_queue_finish(&screen->flush_queue);
    if (ctx->batch.state && !screen->device_lost) {
@@ -1442,8 +1445,9 @@ zink_set_constant_buffer(struct pipe_context *pctx,
 ALWAYS_INLINE static void
 unbind_descriptor_reads(struct zink_resource *res, gl_shader_stage pstage)
 {
-   if (!res->sampler_binds[pstage] && !res->image_binds[pstage])
-      res->barrier_access[pstage == MESA_SHADER_COMPUTE] &= ~VK_ACCESS_SHADER_READ_BIT;
+   bool is_compute = pstage == MESA_SHADER_COMPUTE;
+   if (!res->sampler_bind_count[is_compute] && !res->image_bind_count[is_compute])
+      res->barrier_access[is_compute] &= ~VK_ACCESS_SHADER_READ_BIT;
 }
 
 ALWAYS_INLINE static void
@@ -1520,7 +1524,8 @@ zink_set_shader_buffers(struct pipe_context *pctx,
          else
             new_res->obj->unordered_read = false;
       } else {
-         update = !!res;
+         if (res)
+            update = true;
          ssbo->buffer_offset = 0;
          ssbo->buffer_size = 0;
          if (res) {
@@ -1609,6 +1614,7 @@ unbind_shader_image(struct zink_context *ctx, gl_shader_stage stage, unsigned sl
       zink_buffer_view_reference(zink_screen(ctx->base.screen), &image_view->buffer_view, NULL);
    } else {
       unbind_descriptor_stage(res, stage);
+      unbind_descriptor_reads(res, stage);
       if (!res->image_bind_count[is_compute])
          check_for_layout_update(ctx, res, is_compute);
       zink_surface_reference(zink_screen(ctx->base.screen), &image_view->surface, NULL);
@@ -1737,8 +1743,11 @@ zink_set_shader_images(struct pipe_context *pctx,
                res->image_bind_count[p_stage == MESA_SHADER_COMPUTE]++;
                update_res_bind_count(ctx, res, p_stage == MESA_SHADER_COMPUTE, false);
                unbind_shader_image(ctx, p_stage, start_slot + i);
+               image_view->surface = surface;
+            } else {
+               /* create_image_surface will always increment ref */
+               zink_surface_reference(zink_screen(ctx->base.screen), &surface, NULL);
             }
-            image_view->surface = surface;
             finalize_image_bind(ctx, res, p_stage == MESA_SHADER_COMPUTE);
             zink_batch_resource_usage_set(&ctx->batch, res,
                                           zink_resource_access_is_write(access), false);
@@ -2890,7 +2899,8 @@ unbind_fb_surface(struct zink_context *ctx, struct pipe_surface *surf, unsigned
       check_resource_for_batch_ref(ctx, res);
       if (res->sampler_bind_count[0]) {
          update_res_sampler_layouts(ctx, res);
-         _mesa_set_add(ctx->need_barriers[0], res);
+         if (res->layout != VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL)
+            _mesa_set_add(ctx->need_barriers[0], res);
       }
    }
 }
@@ -3258,7 +3268,7 @@ pipeline_dst_stage(VkImageLayout layout)
 bool
 zink_resource_access_is_write(VkAccessFlags flags)
 {
-   return (flags & ALL_READ_ACCESS_FLAGS) != flags;
+   return (flags & ~ALL_READ_ACCESS_FLAGS) > 0;
 }
 
 bool
@@ -4632,6 +4642,7 @@ zink_context_replace_buffer_storage(struct pipe_context *pctx, struct pipe_resou
       zink_batch_reference_resource(&ctx->batch, d);
    /* don't be too creative */
    zink_resource_object_reference(screen, &d->obj, s->obj);
+   d->valid_buffer_range = s->valid_buffer_range;
    /* force counter buffer reset */
    d->so_valid = false;
    if (num_rebinds && rebind_buffer(ctx, d, rebind_mask, num_rebinds) < num_rebinds)
@@ -4682,6 +4693,13 @@ zink_get_dummy_pipe_surface(struct zink_context *ctx, int samples_index)
 {
    if (!ctx->dummy_surface[samples_index]) {
       ctx->dummy_surface[samples_index] = zink_surface_create_null(ctx, PIPE_TEXTURE_2D, 1024, 1024, BITFIELD_BIT(samples_index));
+      /* This is possibly used with imageLoad which according to GL spec must return 0 */
+      if (!samples_index) {
+         union pipe_color_union color = {0};
+         struct pipe_box box;
+         u_box_2d(0, 0, 1024, 1024, &box);
+         ctx->base.clear_texture(&ctx->base, ctx->dummy_surface[samples_index]->texture, 0, &box, &color);
+      }
    }
    return ctx->dummy_surface[samples_index];
 }
@@ -4850,6 +4868,8 @@ zink_context_create(struct pipe_screen *pscreen, void *priv, unsigned flags)
    }
    ctx->gfx_pipeline_state.rendering_info.sType = VK_STRUCTURE_TYPE_PIPELINE_RENDERING_CREATE_INFO;
    ctx->gfx_pipeline_state.rendering_info.pColorAttachmentFormats = ctx->gfx_pipeline_state.rendering_formats;
+   ctx->gfx_pipeline_state.feedback_loop = screen->driver_workarounds.always_feedback_loop;
+   ctx->gfx_pipeline_state.feedback_loop_zs = screen->driver_workarounds.always_feedback_loop_zs;
 
    const uint32_t data[] = {0};
    if (!is_copy_only) {
diff --git a/lib/mesa/src/gallium/drivers/zink/zink_descriptors.c b/lib/mesa/src/gallium/drivers/zink/zink_descriptors.c
index 6f5762b62..c19af2fe7 100644
--- a/lib/mesa/src/gallium/drivers/zink/zink_descriptors.c
+++ b/lib/mesa/src/gallium/drivers/zink/zink_descriptors.c
@@ -586,6 +586,8 @@ zink_descriptor_program_deinit(struct zink_screen *screen, struct zink_program *
          pg->dd.pool_key[i]->use_count--;
          pg->dd.pool_key[i] = NULL;
       }
+   }
+   for (unsigned i = 0; pg->num_dsl && i < ZINK_DESCRIPTOR_NON_BINDLESS_TYPES; i++) {
       if (pg->dd.templates[i]) {
          VKSCR(DestroyDescriptorUpdateTemplate)(screen->dev, pg->dd.templates[i], NULL);
          pg->dd.templates[i] = VK_NULL_HANDLE;
@@ -972,7 +974,7 @@ zink_descriptors_update(struct zink_context *ctx, bool is_compute)
    /* bindless descriptors are context-based and get updated elsewhere */
    if (pg->dd.bindless && unlikely(!ctx->dd.bindless_bound)) {
       VKCTX(CmdBindDescriptorSets)(ctx->batch.state->cmdbuf, is_compute ? VK_PIPELINE_BIND_POINT_COMPUTE : VK_PIPELINE_BIND_POINT_GRAPHICS,
-                                   pg->layout, ZINK_DESCRIPTOR_BINDLESS, 1, &ctx->dd.bindless_set,
+                                   pg->layout, screen->desc_set_id[ZINK_DESCRIPTOR_BINDLESS], 1, &ctx->dd.bindless_set,
                                    0, NULL);
       ctx->dd.bindless_bound = true;
    }
@@ -1009,11 +1011,11 @@ void
 zink_batch_descriptor_deinit(struct zink_screen *screen, struct zink_batch_state *bs)
 {
    for (unsigned i = 0; i < ZINK_DESCRIPTOR_BASE_TYPES; i++) {
-      while (util_dynarray_contains(&bs->dd.pools[i], struct zink_descriptor_pool_multi *)) {
-         struct zink_descriptor_pool_multi *mpool = util_dynarray_pop(&bs->dd.pools[i], struct zink_descriptor_pool_multi *);
-         if (mpool) {
-            deinit_multi_pool_overflow(screen, mpool);
-            multi_pool_destroy(screen, mpool);
+      for (unsigned j = 0; j < bs->dd.pools[i].capacity / sizeof(struct zink_descriptor_pool_multi *); j++) {
+         struct zink_descriptor_pool_multi **mppool = util_dynarray_element(&bs->dd.pools[i], struct zink_descriptor_pool_multi *, j);
+         if (mppool && *mppool) {
+            deinit_multi_pool_overflow(screen, *mppool);
+            multi_pool_destroy(screen, *mppool);
          }
       }
       util_dynarray_fini(&bs->dd.pools[i]);
diff --git a/lib/mesa/src/gallium/drivers/zink/zink_kopper.c b/lib/mesa/src/gallium/drivers/zink/zink_kopper.c
index 6070abb39..a67b7566a 100644
--- a/lib/mesa/src/gallium/drivers/zink/zink_kopper.c
+++ b/lib/mesa/src/gallium/drivers/zink/zink_kopper.c
@@ -297,7 +297,6 @@ kopper_CreateSwapchain(struct zink_screen *screen, struct kopper_displaytarget *
        *result = error;
        return NULL;
    }
-   cswap->max_acquires = cswap->scci.minImageCount - cdt->caps.minImageCount;
    cswap->last_present = UINT32_MAX;
 
    *result = VK_SUCCESS;
@@ -320,6 +319,7 @@ kopper_GetSwapchainImages(struct zink_screen *screen, struct kopper_swapchain *c
       for (unsigned i = 0; i < cswap->num_images; i++)
          cswap->images[i].image = images[i];
    }
+   cswap->max_acquires = cswap->num_images - cswap->scci.minImageCount + 1;
    return error;
 }
 
@@ -490,7 +490,7 @@ kopper_acquire(struct zink_screen *screen, struct zink_resource *res, uint64_t t
          res->obj->access_stage = 0;
       }
       if (timeout == UINT64_MAX && util_queue_is_initialized(&screen->flush_queue) &&
-          p_atomic_read_relaxed(&cdt->swapchain->num_acquires) > cdt->swapchain->max_acquires) {
+          p_atomic_read_relaxed(&cdt->swapchain->num_acquires) >= cdt->swapchain->max_acquires) {
          util_queue_fence_wait(&cdt->present_fence);
       }
       VkSemaphoreCreateInfo sci = {
diff --git a/lib/mesa/src/gallium/drivers/zink/zink_program.c b/lib/mesa/src/gallium/drivers/zink/zink_program.c
index 66e2161b0..1e742a31c 100644
--- a/lib/mesa/src/gallium/drivers/zink/zink_program.c
+++ b/lib/mesa/src/gallium/drivers/zink/zink_program.c
@@ -451,17 +451,37 @@ generate_gfx_program_modules_optimal(struct zink_context *ctx, struct zink_scree
 }
 
 static uint32_t
-hash_pipeline_lib(const void *key)
+hash_pipeline_lib_generated_tcs(const void *key)
 {
    return 1;
 }
 
+
 static bool
-equals_pipeline_lib_optimal(const void *a, const void *b)
+equals_pipeline_lib_generated_tcs(const void *a, const void *b)
 {
    return !memcmp(a, b, sizeof(uint32_t));
 }
 
+static uint32_t
+hash_pipeline_lib(const void *key)
+{
+   const struct zink_gfx_library_key *gkey = key;
+   /* remove generated tcs bits */
+   return zink_shader_key_optimal_no_tcs(gkey->optimal_key);
+}
+
+static bool
+equals_pipeline_lib(const void *a, const void *b)
+{
+   const struct zink_gfx_library_key *ak = a;
+   const struct zink_gfx_library_key *bk = b;
+   /* remove generated tcs bits */
+   uint32_t val_a = zink_shader_key_optimal_no_tcs(ak->optimal_key);
+   uint32_t val_b = zink_shader_key_optimal_no_tcs(bk->optimal_key);
+   return val_a == val_b;
+}
+
 uint32_t
 hash_gfx_input_dynamic(const void *key)
 {
@@ -866,20 +886,22 @@ zink_create_gfx_program(struct zink_context *ctx,
    prog->ctx = ctx;
 
    for (int i = 0; i < ZINK_GFX_SHADER_COUNT; ++i) {
-      util_dynarray_init(&prog->shader_cache[i][0][0], NULL);
-      util_dynarray_init(&prog->shader_cache[i][0][1], NULL);
-      util_dynarray_init(&prog->shader_cache[i][1][0], NULL);
-      util_dynarray_init(&prog->shader_cache[i][1][1], NULL);
+      util_dynarray_init(&prog->shader_cache[i][0][0], prog);
+      util_dynarray_init(&prog->shader_cache[i][0][1], prog);
+      util_dynarray_init(&prog->shader_cache[i][1][0], prog);
+      util_dynarray_init(&prog->shader_cache[i][1][1], prog);
       if (stages[i]) {
          prog->shaders[i] = stages[i];
          prog->stages_present |= BITFIELD_BIT(i);
       }
    }
+   bool generated_tcs = false;
    if (stages[MESA_SHADER_TESS_EVAL] && !stages[MESA_SHADER_TESS_CTRL]) {
       prog->shaders[MESA_SHADER_TESS_EVAL]->tes.generated =
       prog->shaders[MESA_SHADER_TESS_CTRL] =
         zink_shader_tcs_create(screen, stages[MESA_SHADER_VERTEX], vertices_per_patch);
       prog->stages_present |= BITFIELD_BIT(MESA_SHADER_TESS_CTRL);
+      generated_tcs = true;
    }
    prog->stages_remaining = prog->stages_present;
 
@@ -902,7 +924,10 @@ zink_create_gfx_program(struct zink_context *ctx,
       }
    }
 
-   _mesa_set_init(&prog->libs, prog, hash_pipeline_lib, equals_pipeline_lib_optimal);
+   if (generated_tcs)
+      _mesa_set_init(&prog->libs, prog, hash_pipeline_lib_generated_tcs, equals_pipeline_lib_generated_tcs);
+   else
+      _mesa_set_init(&prog->libs, prog, hash_pipeline_lib, equals_pipeline_lib);
 
    struct mesa_sha1 sctx;
    _mesa_sha1_init(&sctx);
@@ -986,8 +1011,8 @@ precompile_compute_job(void *data, void *gdata, int thread_index)
    assert(comp->module);
    comp->module->shader = zink_shader_compile(screen, comp->shader, comp->shader->nir, NULL);
    assert(comp->module->shader);
-   util_dynarray_init(&comp->shader_cache[0], NULL);
-   util_dynarray_init(&comp->shader_cache[1], NULL);
+   util_dynarray_init(&comp->shader_cache[0], comp);
+   util_dynarray_init(&comp->shader_cache[1], comp);
 
    struct blob blob = {0};
    blob_init(&blob);
@@ -1201,8 +1226,13 @@ zink_destroy_compute_program(struct zink_screen *screen,
 {
    deinit_program(screen, &comp->base);
 
-   if (comp->shader)
-      _mesa_set_remove_key(comp->shader->programs, comp);
+   assert(comp->shader);
+   assert(!comp->shader->spirv);
+
+   _mesa_set_destroy(comp->shader->programs, NULL);
+   ralloc_free(comp->shader->nir);
+   ralloc_free(comp->shader);
+
    destroy_shader_cache(screen, &comp->shader_cache[0]);
    destroy_shader_cache(screen, &comp->shader_cache[1]);
 
@@ -1600,6 +1630,7 @@ zink_create_pipeline_lib(struct zink_screen *screen, struct zink_gfx_program *pr
 {
    struct zink_gfx_library_key *gkey = rzalloc(prog, struct zink_gfx_library_key);
    gkey->optimal_key = state->optimal_key;
+   assert(gkey->optimal_key);
    memcpy(gkey->modules, prog->modules, sizeof(gkey->modules));
    gkey->pipeline = zink_create_gfx_pipeline_library(screen, prog);
    _mesa_set_add(&prog->libs, gkey);
@@ -1695,6 +1726,8 @@ precompile_job(void *data, void *gdata, int thread_index)
 
    struct zink_gfx_pipeline_state state = {0};
    state.shader_keys_optimal.key.vs_base.last_vertex_stage = true;
+   state.shader_keys_optimal.key.tcs.patch_vertices = 3; //random guess, generated tcs precompile is hard
+   state.optimal_key = state.shader_keys_optimal.key.val;
    generate_gfx_program_modules_optimal(NULL, screen, prog, &state);
    zink_screen_get_pipeline_cache(screen, &prog->base, true);
    zink_create_pipeline_lib(screen, prog, &state);
diff --git a/lib/mesa/src/gallium/drivers/zink/zink_program.h b/lib/mesa/src/gallium/drivers/zink/zink_program.h
index caa9c573d..12658458e 100644
--- a/lib/mesa/src/gallium/drivers/zink/zink_program.h
+++ b/lib/mesa/src/gallium/drivers/zink/zink_program.h
@@ -317,12 +317,12 @@ static inline void
 zink_set_fs_point_coord_key(struct zink_context *ctx)
 {
    const struct zink_fs_key *fs = zink_get_fs_key(ctx);
-   bool disable = ctx->gfx_pipeline_state.rast_prim != PIPE_PRIM_POINTS || !ctx->rast_state->base.sprite_coord_enable;
+   bool disable = ctx->gfx_pipeline_state.rast_prim != PIPE_PRIM_POINTS;
    uint8_t coord_replace_bits = disable ? 0 : ctx->rast_state->base.sprite_coord_enable;
-   bool coord_replace_yinvert = disable ? false : !!ctx->rast_state->base.sprite_coord_mode;
-   if (fs->coord_replace_bits != coord_replace_bits || fs->coord_replace_yinvert != coord_replace_yinvert) {
+   bool point_coord_yinvert = disable ? false : !!ctx->rast_state->base.sprite_coord_mode;
+   if (fs->coord_replace_bits != coord_replace_bits || fs->point_coord_yinvert != point_coord_yinvert) {
       zink_set_fs_key(ctx)->coord_replace_bits = coord_replace_bits;
-      zink_set_fs_key(ctx)->coord_replace_yinvert = coord_replace_yinvert;
+      zink_set_fs_key(ctx)->point_coord_yinvert = point_coord_yinvert;
    }
 }
 
diff --git a/lib/mesa/src/gallium/drivers/zink/zink_query.c b/lib/mesa/src/gallium/drivers/zink/zink_query.c
index 67ac1f915..e9dc921c2 100644
--- a/lib/mesa/src/gallium/drivers/zink/zink_query.c
+++ b/lib/mesa/src/gallium/drivers/zink/zink_query.c
@@ -1070,8 +1070,8 @@ zink_resume_queries(struct zink_context *ctx, struct zink_batch *batch)
 {
    struct zink_query *query, *next;
    LIST_FOR_EACH_ENTRY_SAFE(query, next, &ctx->suspended_queries, active_list) {
-      begin_query(ctx, batch, query);
       list_delinit(&query->active_list);
+      begin_query(ctx, batch, query);
    }
 }
 
diff --git a/lib/mesa/src/gallium/drivers/zink/zink_resource.c b/lib/mesa/src/gallium/drivers/zink/zink_resource.c
index eb7bb894c..56f445f63 100644
--- a/lib/mesa/src/gallium/drivers/zink/zink_resource.c
+++ b/lib/mesa/src/gallium/drivers/zink/zink_resource.c
@@ -105,6 +105,7 @@ zink_destroy_resource_object(struct zink_screen *screen, struct zink_resource_ob
       while (util_dynarray_contains(&obj->views, VkImageView))
          VKSCR(DestroyImageView)(screen->dev, util_dynarray_pop(&obj->views, VkImageView), NULL);
    }
+   util_dynarray_fini(&obj->views);
    if (obj->is_buffer) {
       VKSCR(DestroyBuffer)(screen->dev, obj->buffer, NULL);
       VKSCR(DestroyBuffer)(screen->dev, obj->storage_buffer, NULL);
@@ -190,6 +191,9 @@ create_bci(struct zink_screen *screen, const struct pipe_resource *templ, unsign
                 VK_BUFFER_USAGE_TRANSFORM_FEEDBACK_BUFFER_BIT_EXT |
                 VK_BUFFER_USAGE_TRANSFORM_FEEDBACK_COUNTER_BUFFER_BIT_EXT;
 
+   if (screen->info.have_KHR_buffer_device_address)
+      bci.usage |= VK_BUFFER_USAGE_SHADER_DEVICE_ADDRESS_BIT;
+
    if (bind & PIPE_BIND_SHADER_IMAGE)
       bci.usage |= VK_BUFFER_USAGE_STORAGE_TEXEL_BUFFER_BIT;
 
@@ -630,9 +634,12 @@ resource_object_create(struct zink_screen *screen, const struct pipe_resource *t
 #else
          external = VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_WIN32_BIT;
 #endif
-      } else {
+      } else if (screen->info.have_EXT_external_memory_dma_buf) {
          external = VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT;
          export_types |= VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT;
+      } else {
+         /* can't export anything, fail early */
+         return NULL;
       }
    }
 
@@ -672,6 +679,8 @@ resource_object_create(struct zink_screen *screen, const struct pipe_resource *t
          flags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT | VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT;
       obj->is_buffer = true;
       obj->transfer_dst = true;
+      obj->vkflags = bci.flags;
+      obj->vkusage = bci.usage;
    } else {
       bool winsys_modifier = (export_types & VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT) && whandle && whandle->modifier != DRM_FORMAT_MOD_INVALID;
       uint64_t mods[10];
@@ -1283,7 +1292,7 @@ add_resource_bind(struct zink_context *ctx, struct zink_resource *res, unsigned
    }
    struct zink_resource_object *new_obj = resource_object_create(screen, &res->base.b, NULL, &res->linear, res->modifiers, res->modifiers_count, NULL);
    if (!new_obj) {
-      debug_printf("new backing resource alloc failed!");
+      debug_printf("new backing resource alloc failed!\n");
       res->base.b.bind &= ~bind;
       return false;
    }
@@ -1293,11 +1302,6 @@ add_resource_bind(struct zink_context *ctx, struct zink_resource *res, unsigned
    res->layout = VK_IMAGE_LAYOUT_UNDEFINED;
    res->obj->access = 0;
    res->obj->access_stage = 0;
-   bool needs_unref = true;
-   if (zink_resource_has_usage(res)) {
-      zink_batch_reference_resource_move(&ctx->batch, res);
-      needs_unref = false;
-   }
    res->obj = new_obj;
    for (unsigned i = 0; i <= res->base.b.last_level; i++) {
       struct pipe_box box = {0, 0, 0,
@@ -1306,8 +1310,7 @@ add_resource_bind(struct zink_context *ctx, struct zink_resource *res, unsigned
       box.depth = util_num_layers(&res->base.b, i);
       ctx->base.resource_copy_region(&ctx->base, &res->base.b, i, 0, 0, 0, &staging.base.b, i, &box);
    }
-   if (needs_unref)
-      zink_resource_object_reference(screen, &old_obj, NULL);
+   zink_resource_object_reference(screen, &old_obj, NULL);
    return true;
 }
 
@@ -1638,7 +1641,7 @@ invalidate_buffer(struct zink_context *ctx, struct zink_resource *res)
 
    struct zink_resource_object *new_obj = resource_object_create(screen, &res->base.b, NULL, NULL, NULL, 0, NULL);
    if (!new_obj) {
-      debug_printf("new backing resource alloc failed!");
+      debug_printf("new backing resource alloc failed!\n");
       return false;
    }
    /* this ref must be transferred before rebind or else BOOM */
@@ -1864,9 +1867,7 @@ zink_buffer_map(struct pipe_context *pctx,
          goto success;
       usage |= PIPE_MAP_UNSYNCHRONIZED;
    } else if (!(usage & PIPE_MAP_UNSYNCHRONIZED) &&
-              (((usage & PIPE_MAP_READ) && !(usage & PIPE_MAP_PERSISTENT) &&
-               ((screen->info.mem_props.memoryTypes[res->obj->bo->base.placement].propertyFlags & VK_STAGING_RAM) != VK_STAGING_RAM)) ||
-              !res->obj->host_visible)) {
+              (((usage & PIPE_MAP_READ) && !(usage & PIPE_MAP_PERSISTENT) && res->base.b.usage != PIPE_USAGE_STAGING) || !res->obj->host_visible)) {
       assert(!(usage & (TC_TRANSFER_MAP_THREADED_UNSYNC | PIPE_MAP_THREAD_SAFE)));
       if (!res->obj->host_visible || !(usage & PIPE_MAP_ONCE)) {
 overwrite:
diff --git a/lib/mesa/src/gallium/drivers/zink/zink_screen.c b/lib/mesa/src/gallium/drivers/zink/zink_screen.c
index 452f48dd4..3427b68cd 100644
--- a/lib/mesa/src/gallium/drivers/zink/zink_screen.c
+++ b/lib/mesa/src/gallium/drivers/zink/zink_screen.c
@@ -879,8 +879,12 @@ zink_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_SPARSE_TEXTURE_FULL_ARRAY_CUBE_MIPMAPS:
       return screen->info.feats.features.sparseResidencyImage2D ? 1 : 0;
    case PIPE_CAP_QUERY_SPARSE_TEXTURE_RESIDENCY:
+      return screen->info.feats.features.sparseResidency2Samples &&
+             screen->info.feats.features.shaderResourceResidency ? 1 : 0;
    case PIPE_CAP_CLAMP_SPARSE_TEXTURE_LOD:
-      return screen->info.feats.features.sparseResidency2Samples ? 1 : 0;
+      return screen->info.feats.features.shaderResourceMinLod &&
+             screen->info.feats.features.sparseResidency2Samples &&
+             screen->info.feats.features.shaderResourceResidency ? 1 : 0;
 
    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
       return screen->info.props.limits.viewportSubPixelBits;
diff --git a/lib/mesa/src/gallium/drivers/zink/zink_shader_keys.h b/lib/mesa/src/gallium/drivers/zink/zink_shader_keys.h
index 295cbe3cf..fab6fb403 100644
--- a/lib/mesa/src/gallium/drivers/zink/zink_shader_keys.h
+++ b/lib/mesa/src/gallium/drivers/zink/zink_shader_keys.h
@@ -29,9 +29,9 @@
 #include "compiler/shader_info.h"
 
 struct zink_vs_key_base {
+   bool last_vertex_stage : 1;
    bool clip_halfz : 1;
    bool push_drawid : 1;
-   bool last_vertex_stage : 1;
    uint8_t pad : 5;
 };
 
@@ -57,7 +57,7 @@ struct zink_vs_key {
 };
 
 struct zink_fs_key {
-   bool coord_replace_yinvert : 1;
+   bool point_coord_yinvert : 1;
    bool samples : 1;
    bool force_dual_color_blend : 1;
    bool force_persample_interp : 1;
@@ -107,6 +107,19 @@ union zink_shader_key_optimal {
    uint32_t val;
 };
 
+/* the default key has only last_vertex_stage set*/
+#define ZINK_SHADER_KEY_OPTIMAL_DEFAULT (1<<0)
+/* Ignore patch_vertices bits that would only be used if we had to generate the missing TCS */
+static inline uint32_t
+zink_shader_key_optimal_no_tcs(uint32_t key)
+{
+   union zink_shader_key_optimal k;
+   k.val = key;
+   k.tcs_bits = 0;
+   return k.val;
+}
+#define ZINK_SHADER_KEY_OPTIMAL_IS_DEFAULT(key) (zink_shader_key_optimal_no_tcs(key) == ZINK_SHADER_KEY_OPTIMAL_DEFAULT)
+
 static inline const struct zink_fs_key *
 zink_fs_key(const struct zink_shader_key *key)
 {
diff --git a/lib/mesa/src/gallium/drivers/zink/zink_types.h b/lib/mesa/src/gallium/drivers/zink/zink_types.h
index 93ae9ac8c..b05ad12ed 100644
--- a/lib/mesa/src/gallium/drivers/zink/zink_types.h
+++ b/lib/mesa/src/gallium/drivers/zink/zink_types.h
@@ -128,6 +128,7 @@ enum zink_blit_flags {
    ZINK_BLIT_SAVE_FB = 1 << 2,
    ZINK_BLIT_SAVE_TEXTURES = 1 << 3,
    ZINK_BLIT_NO_COND_RENDER = 1 << 4,
+   ZINK_BLIT_SAVE_FS_CONST_BUF = 1 << 5,
 };
 
 /* descriptor types; also the ordering of the sets