Merge Mesa 21.3.8

7 files changed, 32 insertions, 7 deletions

diff --git a/lib/mesa/src/intel/compiler/brw_fs.cpp b/lib/mesa/src/intel/compiler/brw_fs.cpp
index 62181cb7c..bb6e1e338 100644
--- a/lib/mesa/src/intel/compiler/brw_fs.cpp
+++ b/lib/mesa/src/intel/compiler/brw_fs.cpp
@@ -8936,7 +8936,12 @@ fs_visitor::allocate_registers(bool allow_spilling)
    if (last_scratch > 0) {
       ASSERTED unsigned max_scratch_size = 2 * 1024 * 1024;
 
-      prog_data->total_scratch = brw_get_scratch_size(last_scratch);
+      /* Take the max of any previously compiled variant of the shader. In the
+       * case of bindless shaders with return parts, this will also take the
+       * max of all parts.
+       */
+      prog_data->total_scratch = MAX2(brw_get_scratch_size(last_scratch),
+                                      prog_data->total_scratch);
 
       if (stage == MESA_SHADER_COMPUTE || stage == MESA_SHADER_KERNEL) {
          if (devinfo->is_haswell) {
@@ -9721,6 +9726,7 @@ brw_compile_fs(const struct brw_compiler *compiler,
       INTEL_DEBUG(params->debug_flag ? params->debug_flag : DEBUG_WM);
 
    prog_data->base.stage = MESA_SHADER_FRAGMENT;
+   prog_data->base.total_scratch = 0;
 
    const struct intel_device_info *devinfo = compiler->devinfo;
    const unsigned max_subgroup_size = compiler->devinfo->ver >= 6 ? 32 : 16;
@@ -10110,6 +10116,7 @@ brw_compile_cs(const struct brw_compiler *compiler,
 
    prog_data->base.stage = MESA_SHADER_COMPUTE;
    prog_data->base.total_shared = nir->info.shared_size;
+   prog_data->base.total_scratch = 0;
 
    /* Generate code for all the possible SIMD variants. */
    bool generate_all;
@@ -10523,6 +10530,7 @@ brw_compile_bs(const struct brw_compiler *compiler, void *log_data,
    const bool debug_enabled = INTEL_DEBUG(DEBUG_RT);
 
    prog_data->base.stage = shader->info.stage;
+   prog_data->base.total_scratch = 0;
    prog_data->max_stack_size = 0;
 
    fs_generator g(compiler, log_data, mem_ctx, &prog_data->base,
diff --git a/lib/mesa/src/intel/compiler/brw_shader.h b/lib/mesa/src/intel/compiler/brw_shader.h
index 8d0c9c6b1..adf769a42 100644
--- a/lib/mesa/src/intel/compiler/brw_shader.h
+++ b/lib/mesa/src/intel/compiler/brw_shader.h
@@ -121,7 +121,7 @@ extern const char *const conditional_modifier[16];
 extern const char *const pred_ctrl_align16[16];
 
 /* Per-thread scratch space is a power-of-two multiple of 1KB. */
-static inline int
+static inline unsigned
 brw_get_scratch_size(int size)
 {
    return MAX2(1024, util_next_power_of_two(size));
diff --git a/lib/mesa/src/intel/compiler/brw_vec4.cpp b/lib/mesa/src/intel/compiler/brw_vec4.cpp
index 72165932c..52fdc67c8 100644
--- a/lib/mesa/src/intel/compiler/brw_vec4.cpp
+++ b/lib/mesa/src/intel/compiler/brw_vec4.cpp
@@ -2896,6 +2896,7 @@ brw_compile_vs(const struct brw_compiler *compiler,
       INTEL_DEBUG(params->debug_flag ? params->debug_flag : DEBUG_VS);
 
    prog_data->base.base.stage = MESA_SHADER_VERTEX;
+   prog_data->base.base.total_scratch = 0;
 
    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_VERTEX];
    brw_nir_apply_key(nir, compiler, &key->base, 8, is_scalar);
diff --git a/lib/mesa/src/intel/compiler/brw_vec4_gs_visitor.cpp b/lib/mesa/src/intel/compiler/brw_vec4_gs_visitor.cpp
index 1b55e9234..8032fa30b 100644
--- a/lib/mesa/src/intel/compiler/brw_vec4_gs_visitor.cpp
+++ b/lib/mesa/src/intel/compiler/brw_vec4_gs_visitor.cpp
@@ -600,6 +600,7 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
    const bool debug_enabled = INTEL_DEBUG(DEBUG_GS);
 
    prog_data->base.base.stage = MESA_SHADER_GEOMETRY;
+   prog_data->base.base.total_scratch = 0;
 
    /* The GLSL linker will have already matched up GS inputs and the outputs
     * of prior stages.  The driver does extend VS outputs in some cases, but
diff --git a/lib/mesa/src/intel/compiler/brw_vec4_tcs.cpp b/lib/mesa/src/intel/compiler/brw_vec4_tcs.cpp
index 167f8a353..ea212c9c4 100644
--- a/lib/mesa/src/intel/compiler/brw_vec4_tcs.cpp
+++ b/lib/mesa/src/intel/compiler/brw_vec4_tcs.cpp
@@ -372,6 +372,7 @@ brw_compile_tcs(const struct brw_compiler *compiler,
    const unsigned *assembly;
 
    vue_prog_data->base.stage = MESA_SHADER_TESS_CTRL;
+   prog_data->base.base.total_scratch = 0;
 
    nir->info.outputs_written = key->outputs_written;
    nir->info.patch_outputs_written = key->patch_outputs_written;
diff --git a/lib/mesa/src/intel/vulkan/anv_pipeline.c b/lib/mesa/src/intel/vulkan/anv_pipeline.c
index f86ce8ec0..fee7e04b3 100644
--- a/lib/mesa/src/intel/vulkan/anv_pipeline.c
+++ b/lib/mesa/src/intel/vulkan/anv_pipeline.c
@@ -233,6 +233,12 @@ anv_shader_compile_to_nir(struct anv_device *device,
     */
    NIR_PASS_V(nir, nir_lower_variable_initializers, ~0);
 
+   const nir_opt_access_options opt_access_options = {
+      .is_vulkan = true,
+      .infer_non_readable = true,
+   };
+   NIR_PASS_V(nir, nir_opt_access, &opt_access_options);
+
    /* Split member structs.  We do this before lower_io_to_temporaries so that
     * it doesn't lower system values to temporaries by accident.
     */
diff --git a/lib/mesa/src/intel/vulkan/genX_cmd_buffer.c b/lib/mesa/src/intel/vulkan/genX_cmd_buffer.c
index 8b249093b..cf7629f2f 100644
--- a/lib/mesa/src/intel/vulkan/genX_cmd_buffer.c
+++ b/lib/mesa/src/intel/vulkan/genX_cmd_buffer.c
@@ -1413,14 +1413,22 @@ transition_color_buffer(struct anv_cmd_buffer *cmd_buffer,
       anv_layout_to_aux_usage(devinfo, image, aspect, 0, initial_layout);
    enum isl_aux_usage final_aux_usage =
       anv_layout_to_aux_usage(devinfo, image, aspect, 0, final_layout);
+   enum anv_fast_clear_type initial_fast_clear =
+      anv_layout_to_fast_clear_type(devinfo, image, aspect, initial_layout);
+   enum anv_fast_clear_type final_fast_clear =
+      anv_layout_to_fast_clear_type(devinfo, image, aspect, final_layout);
 
    /* We must override the anv_layout_to_* functions because they are unaware of
     * acquire/release direction.
     */
    if (mod_acquire) {
       initial_aux_usage = isl_mod_info->aux_usage;
+      initial_fast_clear = isl_mod_info->supports_clear_color ?
+         initial_fast_clear : ANV_FAST_CLEAR_NONE;
    } else if (mod_release) {
       final_aux_usage = isl_mod_info->aux_usage;
+      final_fast_clear = isl_mod_info->supports_clear_color ?
+         final_fast_clear : ANV_FAST_CLEAR_NONE;
    }
 
    /* The current code assumes that there is no mixing of CCS_E and CCS_D.
@@ -1443,10 +1451,6 @@ transition_color_buffer(struct anv_cmd_buffer *cmd_buffer,
    /* If the initial layout supports more fast clear than the final layout
     * then we need at least a partial resolve.
     */
-   const enum anv_fast_clear_type initial_fast_clear =
-      anv_layout_to_fast_clear_type(devinfo, image, aspect, initial_layout);
-   const enum anv_fast_clear_type final_fast_clear =
-      anv_layout_to_fast_clear_type(devinfo, image, aspect, final_layout);
    if (final_fast_clear < initial_fast_clear)
       resolve_op = ISL_AUX_OP_PARTIAL_RESOLVE;
 
@@ -1822,7 +1826,7 @@ genX(BeginCommandBuffer)(
          const struct anv_image_view * const iview =
             anv_cmd_buffer_get_depth_stencil_view(cmd_buffer);
 
-         if (iview) {
+         if (iview && (iview->image->vk.aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
             VkImageLayout layout =
                 cmd_buffer->state.subpass->depth_stencil_attachment->layout;
 
@@ -4206,6 +4210,9 @@ void genX(CmdDrawIndirectByteCountEXT)(
 
    genX(cmd_buffer_flush_state)(cmd_buffer);
 
+   if (cmd_buffer->state.conditional_render_enabled)
+      genX(cmd_emit_conditional_render_predicate)(cmd_buffer);
+
    if (vs_prog_data->uses_firstvertex ||
        vs_prog_data->uses_baseinstance)
       emit_base_vertex_instance(cmd_buffer, firstVertex, firstInstance);
@@ -4240,6 +4247,7 @@ void genX(CmdDrawIndirectByteCountEXT)(
 
    anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE), prim) {
       prim.IndirectParameterEnable  = true;
+      prim.PredicateEnable          = cmd_buffer->state.conditional_render_enabled;
       prim.VertexAccessType         = SEQUENTIAL;
       prim.PrimitiveTopologyType    = cmd_buffer->state.gfx.primitive_topology;
    }