Import Mesa 17.3.9

1 files changed, 30 insertions, 36 deletions

diff --git a/lib/mesa/src/mesa/drivers/dri/i965/brw_pipe_control.h b/lib/mesa/src/mesa/drivers/dri/i965/brw_pipe_control.h
index 1aed53ee1..6e9a40487 100644
--- a/lib/mesa/src/mesa/drivers/dri/i965/brw_pipe_control.h
+++ b/lib/mesa/src/mesa/drivers/dri/i965/brw_pipe_control.h
@@ -25,45 +25,40 @@
 #define BRW_PIPE_CONTROL_DOT_H
 
 struct brw_context;
-struct intel_device_info;
+struct gen_device_info;
 struct brw_bo;
 
 /** @{
  *
  * PIPE_CONTROL operation, a combination MI_FLUSH and register write with
  * additional flushing control.
- *
- * The bits here are not the actual hardware values.  The actual values
- * shift around a bit per-generation, so we just have flags for each
- * potential operation, and use genxml to encode the actual packet.
  */
-enum pipe_control_flags
-{
-   PIPE_CONTROL_FLUSH_LLC                       = (1 << 1),
-   PIPE_CONTROL_LRI_POST_SYNC_OP                = (1 << 2),
-   PIPE_CONTROL_STORE_DATA_INDEX                = (1 << 3),
-   PIPE_CONTROL_CS_STALL                        = (1 << 4),
-   PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET     = (1 << 5),
-   PIPE_CONTROL_SYNC_GFDT                       = (1 << 6),
-   PIPE_CONTROL_TLB_INVALIDATE                  = (1 << 7),
-   PIPE_CONTROL_MEDIA_STATE_CLEAR               = (1 << 8),
-   PIPE_CONTROL_WRITE_IMMEDIATE                 = (1 << 9),
-   PIPE_CONTROL_WRITE_DEPTH_COUNT               = (1 << 10),
-   PIPE_CONTROL_WRITE_TIMESTAMP                 = (1 << 11),
-   PIPE_CONTROL_DEPTH_STALL                     = (1 << 12),
-   PIPE_CONTROL_RENDER_TARGET_FLUSH             = (1 << 13),
-   PIPE_CONTROL_INSTRUCTION_INVALIDATE          = (1 << 14),
-   PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE        = (1 << 15),
-   PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE = (1 << 16),
-   PIPE_CONTROL_NOTIFY_ENABLE                   = (1 << 17),
-   PIPE_CONTROL_FLUSH_ENABLE                    = (1 << 18),
-   PIPE_CONTROL_DATA_CACHE_FLUSH                = (1 << 19),
-   PIPE_CONTROL_VF_CACHE_INVALIDATE             = (1 << 20),
-   PIPE_CONTROL_CONST_CACHE_INVALIDATE          = (1 << 21),
-   PIPE_CONTROL_STATE_CACHE_INVALIDATE          = (1 << 22),
-   PIPE_CONTROL_STALL_AT_SCOREBOARD             = (1 << 23),
-   PIPE_CONTROL_DEPTH_CACHE_FLUSH               = (1 << 24),
-};
+#define _3DSTATE_PIPE_CONTROL		(CMD_3D | (3 << 27) | (2 << 24))
+#define PIPE_CONTROL_CS_STALL		(1 << 20)
+#define PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET	(1 << 19)
+#define PIPE_CONTROL_TLB_INVALIDATE	(1 << 18)
+#define PIPE_CONTROL_SYNC_GFDT		(1 << 17)
+#define PIPE_CONTROL_MEDIA_STATE_CLEAR	(1 << 16)
+#define PIPE_CONTROL_NO_WRITE		(0 << 14)
+#define PIPE_CONTROL_WRITE_IMMEDIATE	(1 << 14)
+#define PIPE_CONTROL_WRITE_DEPTH_COUNT	(2 << 14)
+#define PIPE_CONTROL_WRITE_TIMESTAMP	(3 << 14)
+#define PIPE_CONTROL_DEPTH_STALL	(1 << 13)
+#define PIPE_CONTROL_RENDER_TARGET_FLUSH (1 << 12)
+#define PIPE_CONTROL_INSTRUCTION_INVALIDATE (1 << 11)
+#define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE	(1 << 10) /* GM45+ only */
+#define PIPE_CONTROL_ISP_DIS		(1 << 9)
+#define PIPE_CONTROL_INTERRUPT_ENABLE	(1 << 8)
+#define PIPE_CONTROL_FLUSH_ENABLE	(1 << 7) /* Gen7+ only */
+/* GT */
+#define PIPE_CONTROL_DATA_CACHE_FLUSH   	(1 << 5)
+#define PIPE_CONTROL_VF_CACHE_INVALIDATE	(1 << 4)
+#define PIPE_CONTROL_CONST_CACHE_INVALIDATE	(1 << 3)
+#define PIPE_CONTROL_STATE_CACHE_INVALIDATE	(1 << 2)
+#define PIPE_CONTROL_STALL_AT_SCOREBOARD	(1 << 1)
+#define PIPE_CONTROL_DEPTH_CACHE_FLUSH		(1 << 0)
+#define PIPE_CONTROL_PPGTT_WRITE	(0 << 2)
+#define PIPE_CONTROL_GLOBAL_GTT_WRITE	(1 << 2)
 
 #define PIPE_CONTROL_CACHE_FLUSH_BITS \
    (PIPE_CONTROL_DEPTH_CACHE_FLUSH | PIPE_CONTROL_DATA_CACHE_FLUSH | \
@@ -77,7 +72,7 @@ enum pipe_control_flags
 /** @} */
 
 int brw_init_pipe_control(struct brw_context *brw,
-                          const struct intel_device_info *info);
+			  const struct gen_device_info *info);
 void brw_fini_pipe_control(struct brw_context *brw);
 
 void brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags);
@@ -88,8 +83,7 @@ void brw_emit_end_of_pipe_sync(struct brw_context *brw, uint32_t flags);
 void brw_emit_mi_flush(struct brw_context *brw);
 void brw_emit_post_sync_nonzero_flush(struct brw_context *brw);
 void brw_emit_depth_stall_flushes(struct brw_context *brw);
-void gfx7_emit_vs_workaround_flush(struct brw_context *brw);
-void gfx7_emit_cs_stall_flush(struct brw_context *brw);
-void gfx7_emit_isp_disable(struct brw_context *brw);
+void gen7_emit_vs_workaround_flush(struct brw_context *brw);
+void gen7_emit_cs_stall_flush(struct brw_context *brw);
 
 #endif