diff options
Diffstat (limited to 'lib/libdrm')
39 files changed, 1042 insertions, 181 deletions
diff --git a/lib/libdrm/README.rst b/lib/libdrm/README.rst index da995d0b3..746080319 100644 --- a/lib/libdrm/README.rst +++ b/lib/libdrm/README.rst @@ -13,6 +13,24 @@ but a new libdrm will always work with an older kernel. libdrm is a low-level library, typically used by graphics drivers such as the Mesa drivers, the X drivers, libva and similar projects. +Syncing with the Linux kernel headers +------------------------------------- + +The library should be regularly updated to match the recent changes in the +`include/uapi/drm/`. + +libdrm maintains a human-readable version for the token format modifier, with +the simpler ones being extracted automatically from `drm_fourcc.h` header file +with the help of a python script. This might not always possible, as some of +the vendors require decoding/extracting them programmatically. For that +reason one can enhance the current vendor functions to include/provide the +newly added token formats, or, in case there's no such decoding +function, to add one that performs the tasks of extracting them. + +For simpler format modifier tokens there's a script (gen_table_fourcc.py) that +creates a static table, by going over `drm_fourcc.h` header file. The script +could be further modified if it can't handle new (simpler) token format +modifiers instead of the generated static table. Compiling --------- diff --git a/lib/libdrm/amdgpu/amdgpu-symbols.txt b/lib/libdrm/amdgpu/amdgpu-symbols.txt index e3bafaabd..a2ed65274 100644 --- a/lib/libdrm/amdgpu/amdgpu-symbols.txt +++ b/lib/libdrm/amdgpu/amdgpu-symbols.txt @@ -66,6 +66,7 @@ amdgpu_query_hw_ip_count amdgpu_query_hw_ip_info amdgpu_query_info amdgpu_query_sensor_info +amdgpu_query_video_caps_info amdgpu_read_mm_registers amdgpu_va_range_alloc amdgpu_va_range_free diff --git a/lib/libdrm/amdgpu/amdgpu.h b/lib/libdrm/amdgpu/amdgpu.h index 188179c9c..b118dd487 100644 --- a/lib/libdrm/amdgpu/amdgpu.h +++ b/lib/libdrm/amdgpu/amdgpu.h @@ -1238,6 +1238,23 @@ int amdgpu_query_sensor_info(amdgpu_device_handle dev, unsigned sensor_type, unsigned size, void *value); /** + * Query information about video capabilities + * + * The return sizeof(struct drm_amdgpu_info_video_caps) + * + * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() + * \param caps_type - \c [in] AMDGPU_INFO_VIDEO_CAPS_DECODE(ENCODE) + * \param size - \c [in] Size of the returned value. + * \param value - \c [out] Pointer to the return value. + * + * \return 0 on success\n + * <0 - Negative POSIX Error code + * +*/ +int amdgpu_query_video_caps_info(amdgpu_device_handle dev, unsigned cap_type, + unsigned size, void *value); + +/** * Read a set of consecutive memory-mapped registers. * Not all registers are allowed to be read by userspace. * @@ -1263,6 +1280,7 @@ int amdgpu_read_mm_registers(amdgpu_device_handle dev, unsigned dword_offset, */ #define AMDGPU_VA_RANGE_32_BIT 0x1 #define AMDGPU_VA_RANGE_HIGH 0x2 +#define AMDGPU_VA_RANGE_REPLAYABLE 0x4 /** * Allocate virtual address range diff --git a/lib/libdrm/amdgpu/amdgpu_gpu_info.c b/lib/libdrm/amdgpu/amdgpu_gpu_info.c index 777087f27..9f8695ce3 100644 --- a/lib/libdrm/amdgpu/amdgpu_gpu_info.c +++ b/lib/libdrm/amdgpu/amdgpu_gpu_info.c @@ -331,3 +331,18 @@ drm_public int amdgpu_query_sensor_info(amdgpu_device_handle dev, unsigned senso return drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request, sizeof(struct drm_amdgpu_info)); } + +drm_public int amdgpu_query_video_caps_info(amdgpu_device_handle dev, unsigned cap_type, + unsigned size, void *value) +{ + struct drm_amdgpu_info request; + + memset(&request, 0, sizeof(request)); + request.return_pointer = (uintptr_t)value; + request.return_size = size; + request.query = AMDGPU_INFO_VIDEO_CAPS; + request.sensor_info.type = cap_type; + + return drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request, + sizeof(struct drm_amdgpu_info)); +} diff --git a/lib/libdrm/amdgpu/amdgpu_vamgr.c b/lib/libdrm/amdgpu/amdgpu_vamgr.c index d25d4216f..077a9fc85 100644 --- a/lib/libdrm/amdgpu/amdgpu_vamgr.c +++ b/lib/libdrm/amdgpu/amdgpu_vamgr.c @@ -69,65 +69,99 @@ drm_private void amdgpu_vamgr_deinit(struct amdgpu_bo_va_mgr *mgr) pthread_mutex_destroy(&mgr->bo_va_mutex); } -static drm_private uint64_t +static drm_private int +amdgpu_vamgr_subtract_hole(struct amdgpu_bo_va_hole *hole, uint64_t start_va, + uint64_t end_va) +{ + if (start_va > hole->offset && end_va - hole->offset < hole->size) { + struct amdgpu_bo_va_hole *n = calloc(1, sizeof(struct amdgpu_bo_va_hole)); + if (!n) + return -ENOMEM; + + n->size = start_va - hole->offset; + n->offset = hole->offset; + list_add(&n->list, &hole->list); + + hole->size -= (end_va - hole->offset); + hole->offset = end_va; + } else if (start_va > hole->offset) { + hole->size = start_va - hole->offset; + } else if (end_va - hole->offset < hole->size) { + hole->size -= (end_va - hole->offset); + hole->offset = end_va; + } else { + list_del(&hole->list); + free(hole); + } + + return 0; +} + +static drm_private int amdgpu_vamgr_find_va(struct amdgpu_bo_va_mgr *mgr, uint64_t size, - uint64_t alignment, uint64_t base_required) + uint64_t alignment, uint64_t base_required, + bool search_from_top, uint64_t *va_out) { struct amdgpu_bo_va_hole *hole, *n; - uint64_t offset = 0, waste = 0; + uint64_t offset = 0; + int ret; alignment = MAX2(alignment, mgr->va_alignment); size = ALIGN(size, mgr->va_alignment); if (base_required % alignment) - return AMDGPU_INVALID_VA_ADDRESS; + return -EINVAL; pthread_mutex_lock(&mgr->bo_va_mutex); - LIST_FOR_EACH_ENTRY_SAFE_REV(hole, n, &mgr->va_holes, list) { - if (base_required) { - if (hole->offset > base_required || - (hole->offset + hole->size) < (base_required + size)) - continue; - waste = base_required - hole->offset; - offset = base_required; - } else { - offset = hole->offset; - waste = offset % alignment; - waste = waste ? alignment - waste : 0; - offset += waste; - if (offset >= (hole->offset + hole->size)) { - continue; + if (!search_from_top) { + LIST_FOR_EACH_ENTRY_SAFE_REV(hole, n, &mgr->va_holes, list) { + if (base_required) { + if (hole->offset > base_required || + (hole->offset + hole->size) < (base_required + size)) + continue; + offset = base_required; + } else { + uint64_t waste = hole->offset % alignment; + waste = waste ? alignment - waste : 0; + offset = hole->offset + waste; + if (offset >= (hole->offset + hole->size) || + size > (hole->offset + hole->size) - offset) { + continue; + } } - } - if (!waste && hole->size == size) { - offset = hole->offset; - list_del(&hole->list); - free(hole); + ret = amdgpu_vamgr_subtract_hole(hole, offset, offset + size); pthread_mutex_unlock(&mgr->bo_va_mutex); - return offset; + *va_out = offset; + return ret; } - if ((hole->size - waste) > size) { - if (waste) { - n = calloc(1, sizeof(struct amdgpu_bo_va_hole)); - n->size = waste; - n->offset = hole->offset; - list_add(&n->list, &hole->list); + } else { + LIST_FOR_EACH_ENTRY_SAFE(hole, n, &mgr->va_holes, list) { + if (base_required) { + if (hole->offset > base_required || + (hole->offset + hole->size) < (base_required + size)) + continue; + offset = base_required; + } else { + if (size > hole->size) + continue; + + offset = hole->offset + hole->size - size; + offset -= offset % alignment; + if (offset < hole->offset) { + continue; + } } - hole->size -= (size + waste); - hole->offset += size + waste; - pthread_mutex_unlock(&mgr->bo_va_mutex); - return offset; - } - if ((hole->size - waste) == size) { - hole->size = waste; + + ret = amdgpu_vamgr_subtract_hole(hole, offset, offset + size); pthread_mutex_unlock(&mgr->bo_va_mutex); - return offset; + *va_out = offset; + return ret; } } pthread_mutex_unlock(&mgr->bo_va_mutex); - return AMDGPU_INVALID_VA_ADDRESS; + return -ENOMEM; } static drm_private void @@ -196,6 +230,8 @@ drm_public int amdgpu_va_range_alloc(amdgpu_device_handle dev, uint64_t flags) { struct amdgpu_bo_va_mgr *vamgr; + bool search_from_top = !!(flags & AMDGPU_VA_RANGE_REPLAYABLE); + int ret; /* Clear the flag when the high VA manager is not initialized */ if (flags & AMDGPU_VA_RANGE_HIGH && !dev->vamgr_high_32.va_max) @@ -216,21 +252,22 @@ drm_public int amdgpu_va_range_alloc(amdgpu_device_handle dev, va_base_alignment = MAX2(va_base_alignment, vamgr->va_alignment); size = ALIGN(size, vamgr->va_alignment); - *va_base_allocated = amdgpu_vamgr_find_va(vamgr, size, - va_base_alignment, va_base_required); + ret = amdgpu_vamgr_find_va(vamgr, size, + va_base_alignment, va_base_required, + search_from_top, va_base_allocated); - if (!(flags & AMDGPU_VA_RANGE_32_BIT) && - (*va_base_allocated == AMDGPU_INVALID_VA_ADDRESS)) { + if (!(flags & AMDGPU_VA_RANGE_32_BIT) && ret) { /* fallback to 32bit address */ if (flags & AMDGPU_VA_RANGE_HIGH) vamgr = &dev->vamgr_high_32; else vamgr = &dev->vamgr_32; - *va_base_allocated = amdgpu_vamgr_find_va(vamgr, size, - va_base_alignment, va_base_required); + ret = amdgpu_vamgr_find_va(vamgr, size, + va_base_alignment, va_base_required, + search_from_top, va_base_allocated); } - if (*va_base_allocated != AMDGPU_INVALID_VA_ADDRESS) { + if (!ret) { struct amdgpu_va* va; va = calloc(1, sizeof(struct amdgpu_va)); if(!va){ @@ -243,11 +280,9 @@ drm_public int amdgpu_va_range_alloc(amdgpu_device_handle dev, va->range = va_range_type; va->vamgr = vamgr; *va_range_handle = va; - } else { - return -EINVAL; } - return 0; + return ret; } drm_public int amdgpu_va_range_free(amdgpu_va_handle va_range_handle) diff --git a/lib/libdrm/amdgpu/meson.build b/lib/libdrm/amdgpu/meson.build index a1781f595..3301a10e8 100644 --- a/lib/libdrm/amdgpu/meson.build +++ b/lib/libdrm/amdgpu/meson.build @@ -21,7 +21,7 @@ datadir_amdgpu = join_paths(get_option('prefix'), get_option('datadir'), 'libdrm') -libdrm_amdgpu = shared_library( +libdrm_amdgpu = library( 'drm_amdgpu', [ files( @@ -36,7 +36,7 @@ libdrm_amdgpu = shared_library( ], include_directories : [inc_root, inc_drm], link_with : libdrm, - dependencies : [dep_pthread_stubs, dep_atomic_ops], + dependencies : [dep_pthread_stubs, dep_atomic_ops, dep_rt], version : '1.0.0', install : true, ) diff --git a/lib/libdrm/core-symbols.txt b/lib/libdrm/core-symbols.txt index 1ff4ecaaf..a79e62606 100644 --- a/lib/libdrm/core-symbols.txt +++ b/lib/libdrm/core-symbols.txt @@ -83,6 +83,7 @@ drmHashInsert drmHashLookup drmHashNext drmIoctl +drmIsKMS drmIsMaster drmMalloc drmMap @@ -195,3 +196,5 @@ drmUnmap drmUnmapBufs drmUpdateDrawableInfo drmWaitVBlank +drmGetFormatModifierName +drmGetFormatModifierVendor diff --git a/lib/libdrm/data/amdgpu.ids b/lib/libdrm/data/amdgpu.ids index d0de378db..cd6fa67ef 100644 --- a/lib/libdrm/data/amdgpu.ids +++ b/lib/libdrm/data/amdgpu.ids @@ -135,7 +135,9 @@ 67C2, 01, AMD Radeon (TM) Pro V7350x2 67C2, 02, AMD Radeon (TM) Pro V7300X 67C4, 00, AMD Radeon (TM) Pro WX 7100 Graphics +67C4, 80, AMD Radeon (TM) E9560/E9565 Graphics 67C7, 00, AMD Radeon (TM) Pro WX 5100 Graphics +67C7, 80, AMD Radeon (TM) Pro E9390 Graphics 67C0, 00, AMD Radeon (TM) Pro WX 7100 Graphics 67D0, 01, AMD Radeon (TM) Pro V7350x2 67D0, 02, AMD Radeon (TM) Pro V7300X @@ -254,6 +256,8 @@ 7300, CB, AMD Radeon (TM) R9 Fury Series 7300, CA, AMD Radeon (TM) R9 Fury Series 7312, 00, AMD Radeon Pro W5700 +731E, C6, AMD Radeon RX 5700XTB +731E, C7, AMD Radeon RX 5700B 731F, C0, AMD Radeon RX 5700 XT 50th Anniversary 731F, C1, AMD Radeon RX 5700 XT 731F, C2, AMD Radeon RX 5600M @@ -265,9 +269,19 @@ 7340, C1, Radeon RX 5500M 7340, C5, Radeon RX 5500 XT 7340, C7, Radeon RX 5500 +7340, C9, AMD Radeon RX 5500XTB 7340, CF, Radeon RX 5300 7341, 00, AMD Radeon Pro W5500 7347, 00, AMD Radeon Pro W5500M +73A3, 00, AMD Radeon PRO W6800 +73AF, C0, AMD Radeon RX 6900 XT +73BF, C0, AMD Radeon RX 6900 XT +73BF, C1, AMD Radeon RX 6800 XT +73BF, C3, AMD Radeon RX 6800 +73DF, C1, AMD Radeon RX 6700 XT +73DF, C5, AMD Radeon RX 6700 XT +73E1, 00, AMD Radeon PRO W6600M +73E3, 00, AMD Radeon PRO W6600 9874, C4, AMD Radeon R7 Graphics 9874, C5, AMD Radeon R6 Graphics 9874, C6, AMD Radeon R6 Graphics diff --git a/lib/libdrm/etnaviv/meson.build b/lib/libdrm/etnaviv/meson.build index 6040cf632..8b82ed079 100644 --- a/lib/libdrm/etnaviv/meson.build +++ b/lib/libdrm/etnaviv/meson.build @@ -19,7 +19,7 @@ # SOFTWARE. -libdrm_etnaviv = shared_library( +libdrm_etnaviv = library( 'drm_etnaviv', [ files( diff --git a/lib/libdrm/exynos/meson.build b/lib/libdrm/exynos/meson.build index 40d66fc1a..7d1edfeab 100644 --- a/lib/libdrm/exynos/meson.build +++ b/lib/libdrm/exynos/meson.build @@ -18,7 +18,7 @@ # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE # SOFTWARE. -libdrm_exynos = shared_library( +libdrm_exynos = library( 'drm_exynos', [files('exynos_drm.c', 'exynos_fimg2d.c'), config_file], c_args : libdrm_c_args, diff --git a/lib/libdrm/freedreno/meson.build b/lib/libdrm/freedreno/meson.build index 63b84fc94..49e665939 100644 --- a/lib/libdrm/freedreno/meson.build +++ b/lib/libdrm/freedreno/meson.build @@ -39,7 +39,7 @@ if with_freedreno_kgsl ) endif -libdrm_freedreno = shared_library( +libdrm_freedreno = library( 'drm_freedreno', [files_freedreno, config_file], c_args : libdrm_c_args, diff --git a/lib/libdrm/gen_table_fourcc.py b/lib/libdrm/gen_table_fourcc.py new file mode 100644 index 000000000..4e8bc4096 --- /dev/null +++ b/lib/libdrm/gen_table_fourcc.py @@ -0,0 +1,84 @@ +#!/usr/bin/env python3 + +# Copyright 2021 Collabora, Ltd. +# +# Permission is hereby granted, free of charge, to any person obtaining +# a copy of this software and associated documentation files (the +# "Software"), to deal in the Software without restriction, including +# without limitation the rights to use, copy, modify, merge, publish, +# distribute, sublicense, and/or sell copies of the Software, and to +# permit persons to whom the Software is furnished to do so, subject to +# the following conditions: +# +# The above copyright notice and this permission notice (including the +# next paragraph) shall be included in all copies or substantial +# portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +# BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN +# ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. + +# Helper script that reads drm_fourcc.h and writes a static table with the +# simpler format token modifiers + +import sys +import re + +filename = sys.argv[1] +towrite = sys.argv[2] + +fm_re = { + 'intel': r'^#define I915_FORMAT_MOD_(\w+)', + 'others': r'^#define DRM_FORMAT_MOD_((?:ARM|SAMSUNG|QCOM|VIVANTE|NVIDIA|BROADCOM|ALLWINNER)\w+)\s', + 'vendors': r'^#define DRM_FORMAT_MOD_VENDOR_(\w+)' +} + +def print_fm_intel(f, f_mod): + f.write(' {{ DRM_MODIFIER_INTEL({}, {}) }},\n'.format(f_mod, f_mod)) + +# generic write func +def print_fm(f, vendor, mod, f_name): + f.write(' {{ DRM_MODIFIER({}, {}, {}) }},\n'.format(vendor, mod, f_name)) + +with open(filename, "r") as f: + data = f.read() + for k, v in fm_re.items(): + fm_re[k] = re.findall(v, data, flags=re.M) + +with open(towrite, "w") as f: + f.write('''\ +/* AUTOMATICALLY GENERATED by gen_table_fourcc.py. You should modify + that script instead of adding here entries manually! */ +static const struct drmFormatModifierInfo drm_format_modifier_table[] = { +''') + f.write(' { DRM_MODIFIER_INVALID(NONE, INVALID_MODIFIER) },\n') + f.write(' { DRM_MODIFIER_LINEAR(NONE, LINEAR) },\n') + + for entry in fm_re['intel']: + print_fm_intel(f, entry) + + for entry in fm_re['others']: + (vendor, mod) = entry.split('_', 1) + if vendor == 'ARM' and (mod == 'TYPE_AFBC' or mod == 'TYPE_MISC'): + continue + print_fm(f, vendor, mod, mod) + + f.write('''\ +}; +''') + + f.write('''\ +static const struct drmFormatModifierVendorInfo drm_format_modifier_vendor_table[] = { +''') + + for entry in fm_re['vendors']: + f.write(" {{ DRM_FORMAT_MOD_VENDOR_{}, \"{}\" }},\n".format(entry, entry)) + + f.write('''\ +}; +''') diff --git a/lib/libdrm/include/drm/amdgpu_drm.h b/lib/libdrm/include/drm/amdgpu_drm.h index 4e873dcbe..728566542 100644 --- a/lib/libdrm/include/drm/amdgpu_drm.h +++ b/lib/libdrm/include/drm/amdgpu_drm.h @@ -502,15 +502,15 @@ struct drm_amdgpu_gem_op { #define AMDGPU_VM_MTYPE_MASK (0xf << 5) /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) -/* Use NC MTYPE instead of default MTYPE */ +/* Use Non Coherent MTYPE instead of default MTYPE */ #define AMDGPU_VM_MTYPE_NC (1 << 5) -/* Use WC MTYPE instead of default MTYPE */ +/* Use Write Combine MTYPE instead of default MTYPE */ #define AMDGPU_VM_MTYPE_WC (2 << 5) -/* Use CC MTYPE instead of default MTYPE */ +/* Use Cache Coherent MTYPE instead of default MTYPE */ #define AMDGPU_VM_MTYPE_CC (3 << 5) -/* Use UC MTYPE instead of default MTYPE */ +/* Use UnCached MTYPE instead of default MTYPE */ #define AMDGPU_VM_MTYPE_UC (4 << 5) -/* Use RW MTYPE instead of default MTYPE */ +/* Use Read Write MTYPE instead of default MTYPE */ #define AMDGPU_VM_MTYPE_RW (5 << 5) struct drm_amdgpu_gem_va { @@ -667,12 +667,13 @@ struct drm_amdgpu_cs_chunk_data { }; }; -/** +/* * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU * */ #define AMDGPU_IDS_FLAGS_FUSION 0x1 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 +#define AMDGPU_IDS_FLAGS_TMZ 0x4 /* indicate if acceleration can be working */ #define AMDGPU_INFO_ACCEL_WORKING 0x00 @@ -723,6 +724,8 @@ struct drm_amdgpu_cs_chunk_data { #define AMDGPU_INFO_FW_TA 0x13 /* Subquery id: Query DMCUB firmware version */ #define AMDGPU_INFO_FW_DMCUB 0x14 + /* Subquery id: Query TOC firmware version */ + #define AMDGPU_INFO_FW_TOC 0x15 /* number of bytes moved for TTM migration */ #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f @@ -779,6 +782,12 @@ struct drm_amdgpu_cs_chunk_data { #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F /* query ras mask of enabled features*/ #define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20 +/* query video encode/decode caps */ +#define AMDGPU_INFO_VIDEO_CAPS 0x21 + /* Subquery id: Decode */ + #define AMDGPU_INFO_VIDEO_CAPS_DECODE 0 + /* Subquery id: Encode */ + #define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1 /* RAS MASK: UMC (VRAM) */ #define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0) @@ -875,6 +884,10 @@ struct drm_amdgpu_info { struct { __u32 type; } sensor_info; + + struct { + __u32 type; + } video_cap; }; }; @@ -945,6 +958,7 @@ struct drm_amdgpu_info_firmware { #define AMDGPU_VRAM_TYPE_DDR3 7 #define AMDGPU_VRAM_TYPE_DDR4 8 #define AMDGPU_VRAM_TYPE_GDDR6 9 +#define AMDGPU_VRAM_TYPE_DDR5 10 struct drm_amdgpu_info_device { /** PCI Device ID */ @@ -1070,6 +1084,30 @@ struct drm_amdgpu_info_vce_clock_table { __u32 pad; }; +/* query video encode/decode caps */ +#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2 0 +#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4 1 +#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1 2 +#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC 3 +#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC 4 +#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG 5 +#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9 6 +#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1 7 +#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT 8 + +struct drm_amdgpu_info_video_codec_info { + __u32 valid; + __u32 max_width; + __u32 max_height; + __u32 max_pixels_per_frame; + __u32 max_level; + __u32 pad; +}; + +struct drm_amdgpu_info_video_caps { + struct drm_amdgpu_info_video_codec_info codec_info[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT]; +}; + /* * Supported GPU families */ @@ -1082,6 +1120,7 @@ struct drm_amdgpu_info_vce_clock_table { #define AMDGPU_FAMILY_AI 141 /* Vega10 */ #define AMDGPU_FAMILY_RV 142 /* Raven */ #define AMDGPU_FAMILY_NV 143 /* Navi10 */ +#define AMDGPU_FAMILY_VGH 144 /* Van Gogh */ #if defined(__cplusplus) } diff --git a/lib/libdrm/intel/intel_chipset.c b/lib/libdrm/intel/intel_chipset.c index 439db3e55..f0da6d81c 100644 --- a/lib/libdrm/intel/intel_chipset.c +++ b/lib/libdrm/intel/intel_chipset.c @@ -35,9 +35,12 @@ static const struct pci_device { uint16_t gen; } pciids[] = { /* Keep ids sorted by gen; latest gen first */ + INTEL_ADLP_IDS(12), + INTEL_ADLS_IDS(12), INTEL_RKL_IDS(12), INTEL_DG1_IDS(12), INTEL_TGL_12_IDS(12), + INTEL_JSL_IDS(11), INTEL_EHL_IDS(11), INTEL_ICL_11_IDS(11), INTEL_CNL_IDS(10), diff --git a/lib/libdrm/intel/meson.build b/lib/libdrm/intel/meson.build index 4d3f1ebda..5fa06c286 100644 --- a/lib/libdrm/intel/meson.build +++ b/lib/libdrm/intel/meson.build @@ -18,7 +18,7 @@ # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE # SOFTWARE. -libdrm_intel = shared_library( +libdrm_intel = library( 'drm_intel', [ files( diff --git a/lib/libdrm/libkms/meson.build b/lib/libdrm/libkms/meson.build index 216be4df4..8d17bb2ef 100644 --- a/lib/libdrm/libkms/meson.build +++ b/lib/libdrm/libkms/meson.build @@ -41,7 +41,7 @@ if with_exynos libkms_include += include_directories('../exynos') endif -libkms = shared_library( +libkms = library( 'kms', [files_libkms, config_file], c_args : libdrm_c_args, diff --git a/lib/libdrm/meson.build b/lib/libdrm/meson.build index a4d8d7074..288106bdd 100644 --- a/lib/libdrm/meson.build +++ b/lib/libdrm/meson.build @@ -21,9 +21,9 @@ project( 'libdrm', ['c'], - version : '2.4.104', + version : '2.4.107', license : 'MIT', - meson_version : '>= 0.43', + meson_version : '>= 0.46', default_options : ['buildtype=debugoptimized', 'c_std=gnu99'], ) @@ -51,6 +51,11 @@ prog_nm = find_program('nm') intel_atomics = false lib_atomics = false +python3 = import('python').find_installation() +format_mod_static_table = custom_target('format_mod_static_table', + output : 'generated_static_table_fourcc.h', input: 'include/drm/drm_fourcc.h', + command : [python3, files('gen_table_fourcc.py'), '@INPUT@', '@OUTPUT@']) + dep_atomic_ops = dependency('atomic_ops', required : false) if cc.links(''' int atomic_add(int *i) { return __sync_add_and_fetch (i, 1); } @@ -261,7 +266,7 @@ else endif with_man_pages = get_option('man-pages') -prog_rst2man = find_program('rst2man', required: with_man_pages == 'true') +prog_rst2man = find_program('rst2man', 'rst2man.py', required: with_man_pages == 'true') with_man_pages = with_man_pages != 'false' and prog_rst2man.found() config.set10('HAVE_VISIBILITY', @@ -294,13 +299,13 @@ add_project_arguments('-include', '@0@'.format(config_file), language : 'c') inc_root = include_directories('.') inc_drm = include_directories('include/drm') -libdrm = shared_library( +libdrm = library( 'drm', [files( 'xf86drm.c', 'xf86drmHash.c', 'xf86drmRandom.c', 'xf86drmSL.c', 'xf86drmMode.c' ), - config_file, + config_file, format_mod_static_table ], c_args : libdrm_c_args, dependencies : [dep_valgrind, dep_rt, dep_m], diff --git a/lib/libdrm/nouveau/meson.build b/lib/libdrm/nouveau/meson.build index 9bd58fca5..af45336c6 100644 --- a/lib/libdrm/nouveau/meson.build +++ b/lib/libdrm/nouveau/meson.build @@ -19,7 +19,7 @@ # SOFTWARE. -libdrm_nouveau = shared_library( +libdrm_nouveau = library( 'drm_nouveau', [files( 'nouveau.c', 'pushbuf.c', 'bufctx.c', 'abi16.c'), config_file], c_args : libdrm_c_args, diff --git a/lib/libdrm/nouveau/nouveau.c b/lib/libdrm/nouveau/nouveau.c index f18d1426b..9fa940a93 100644 --- a/lib/libdrm/nouveau/nouveau.c +++ b/lib/libdrm/nouveau/nouveau.c @@ -46,19 +46,35 @@ #include "nvif/ioctl.h" #include "nvif/unpack.h" -#ifdef DEBUG +drm_private FILE *nouveau_out = NULL; drm_private uint32_t nouveau_debug = 0; static void -debug_init(char *args) +debug_init(void) { - if (args) { - int n = strtol(args, NULL, 0); + static bool once = false; + char *debug, *out; + + if (once) + return; + once = true; + + debug = getenv("NOUVEAU_LIBDRM_DEBUG"); + if (debug) { + int n = strtol(debug, NULL, 0); if (n >= 0) nouveau_debug = n; + + } + + nouveau_out = stderr; + out = getenv("NOUVEAU_LIBDRM_OUT"); + if (out) { + FILE *fout = fopen(out, "w"); + if (fout) + nouveau_out = fout; } } -#endif static int nouveau_object_ioctl(struct nouveau_object *obj, void *data, uint32_t size) @@ -327,9 +343,7 @@ nouveau_drm_new(int fd, struct nouveau_drm **pdrm) struct nouveau_drm *drm; drmVersionPtr ver; -#ifdef DEBUG - debug_init(getenv("NOUVEAU_LIBDRM_DEBUG")); -#endif + debug_init(); if (!(drm = calloc(1, sizeof(*drm)))) return -ENOMEM; diff --git a/lib/libdrm/nouveau/pushbuf.c b/lib/libdrm/nouveau/pushbuf.c index e5f73f0d7..10ff3f57f 100644 --- a/lib/libdrm/nouveau/pushbuf.c +++ b/lib/libdrm/nouveau/pushbuf.c @@ -292,11 +292,14 @@ pushbuf_dump(struct nouveau_pushbuf_krec *krec, int krec_id, int chid) kref = krec->buffer + kpsh->bo_index; bo = (void *)(unsigned long)kref->user_priv; bgn = (uint32_t *)((char *)bo->map + kpsh->offset); - end = bgn + (kpsh->length /4); + end = bgn + ((kpsh->length & 0x7fffff) /4); - err("ch%d: psh %08x %010llx %010llx\n", chid, kpsh->bo_index, + err("ch%d: psh %s%08x %010llx %010llx\n", chid, + bo->map ? "" : "(unmapped) ", kpsh->bo_index, (unsigned long long)kpsh->offset, (unsigned long long)(kpsh->offset + kpsh->length)); + if (!bo->map) + continue; while (bgn < end) err("\t0x%08x\n", *bgn++); } @@ -336,6 +339,8 @@ pushbuf_submit(struct nouveau_pushbuf *push, struct nouveau_object *chan) req.suffix0 = nvpb->suffix0; req.suffix1 = nvpb->suffix1; req.vram_available = 0; /* for valgrind */ + if (dbg_on(1)) + req.vram_available |= NOUVEAU_GEM_PUSHBUF_SYNC; req.gart_available = 0; if (dbg_on(0)) diff --git a/lib/libdrm/omap/meson.build b/lib/libdrm/omap/meson.build index 53330b61b..bfd59f057 100644 --- a/lib/libdrm/omap/meson.build +++ b/lib/libdrm/omap/meson.build @@ -18,7 +18,7 @@ # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE # SOFTWARE. -libdrm_omap = shared_library( +libdrm_omap = library( 'drm_omap', [files('omap_drm.c'), config_file], include_directories : [inc_root, inc_drm], diff --git a/lib/libdrm/radeon/meson.build b/lib/libdrm/radeon/meson.build index ca128329c..31fe9cd09 100644 --- a/lib/libdrm/radeon/meson.build +++ b/lib/libdrm/radeon/meson.build @@ -19,7 +19,7 @@ # SOFTWARE. -libdrm_radeon = shared_library( +libdrm_radeon = library( 'drm_radeon', [ files( diff --git a/lib/libdrm/tegra/meson.build b/lib/libdrm/tegra/meson.build index 88613b9cd..edddf72bc 100644 --- a/lib/libdrm/tegra/meson.build +++ b/lib/libdrm/tegra/meson.build @@ -18,7 +18,7 @@ # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE # SOFTWARE. -libdrm_tegra = shared_library( +libdrm_tegra = library( 'drm_tegra', [files('tegra.c'), config_file], include_directories : [inc_root, inc_drm], diff --git a/lib/libdrm/tests/amdgpu/amdgpu_test.c b/lib/libdrm/tests/amdgpu/amdgpu_test.c index 8c867678b..c4224c910 100644 --- a/lib/libdrm/tests/amdgpu/amdgpu_test.c +++ b/lib/libdrm/tests/amdgpu/amdgpu_test.c @@ -37,6 +37,18 @@ #include <sys/time.h> #include <stdarg.h> #include <stdint.h> +#ifdef __linux__ +#include <linux/limits.h> +#elif __FreeBSD__ +/* SPECNAMELEN in FreeBSD is defined here: */ +#include <sys/param.h> +#endif +#ifdef MAJOR_IN_MKDEV +#include <sys/mkdev.h> +#endif +#ifdef MAJOR_IN_SYSMACROS +#include <sys/sysmacros.h> +#endif #include "drm.h" #include "xf86drmMode.h" @@ -59,6 +71,7 @@ #define RAS_TESTS_STR "RAS Tests" #define SYNCOBJ_TIMELINE_TESTS_STR "SYNCOBJ TIMELINE Tests" #define SECURITY_TESTS_STR "Security Tests" +#define HOTUNPLUG_TESTS_STR "Hotunplug Tests" /** * Open handles for amdgpu devices @@ -137,6 +150,12 @@ static CU_SuiteInfo suites[] = { .pCleanupFunc = suite_security_tests_clean, .pTests = security_tests, }, + { + .pName = HOTUNPLUG_TESTS_STR, + .pInitFunc = suite_hotunplug_tests_init, + .pCleanupFunc = suite_hotunplug_tests_clean, + .pTests = hotunplug_tests, + }, CU_SUITE_INFO_NULL, }; @@ -198,6 +217,10 @@ static Suites_Active_Status suites_active_stat[] = { .pName = SECURITY_TESTS_STR, .pActive = suite_security_tests_enable, }, + { + .pName = HOTUNPLUG_TESTS_STR, + .pActive = suite_hotunplug_tests_enable, + }, }; @@ -339,12 +362,13 @@ static int amdgpu_open_devices(int open_render_node) /* Close AMD devices. */ -static void amdgpu_close_devices() +void amdgpu_close_devices() { int i; for (i = 0; i < MAX_CARDS_SUPPORTED; i++) - if (drm_amdgpu[i] >=0) + if (drm_amdgpu[i] >=0) { close(drm_amdgpu[i]); + } } /* Print AMD devices information */ @@ -430,7 +454,8 @@ static void amdgpu_disable_suites() { amdgpu_device_handle device_handle; uint32_t major_version, minor_version, family_id; - int i; + drmDevicePtr devices[MAX_CARDS_SUPPORTED]; + int i, drm_count; int size = sizeof(suites_active_stat) / sizeof(suites_active_stat[0]); if (amdgpu_device_initialize(drm_amdgpu[0], &major_version, @@ -442,6 +467,8 @@ static void amdgpu_disable_suites() if (amdgpu_device_deinitialize(device_handle)) return; + drm_count = drmGetDevices2(0, devices, MAX_CARDS_SUPPORTED); + /* Set active status for suites based on their policies */ for (i = 0; i < size; ++i) if (amdgpu_set_suite_active(suites_active_stat[i].pName, @@ -496,9 +523,6 @@ static void amdgpu_disable_suites() "gfx ring slow bad draw test (set amdgpu.lockup_timeout=50)", CU_FALSE)) fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); - if (amdgpu_set_test_active(BO_TESTS_STR, "Metadata", CU_FALSE)) - fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); - if (amdgpu_set_test_active(BASIC_TESTS_STR, "bo eviction Test", CU_FALSE)) fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); @@ -524,6 +548,84 @@ static void amdgpu_disable_suites() //if (family_id < AMDGPU_FAMILY_AI || family_id > AMDGPU_FAMILY_RV) if (amdgpu_set_test_active(BASIC_TESTS_STR, "GPU reset Test", CU_FALSE)) fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); + + /* You need at least 2 devices for this */ + if (drm_count < 2) + if (amdgpu_set_test_active(HOTUNPLUG_TESTS_STR, "Unplug with exported fence", CU_FALSE)) + fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); +} + +int test_device_index; + +int amdgpu_open_device_on_test_index(int render_node) +{ + int i; + + if (amdgpu_open_devices(open_render_node) <= 0) { + perror("Cannot open AMDGPU device"); + return -1; + } + + if (test_device_index >= 0) { + /* Most tests run on device of drm_amdgpu[0]. + * Swap the chosen device to drm_amdgpu[0]. + */ + i = drm_amdgpu[0]; + drm_amdgpu[0] = drm_amdgpu[test_device_index]; + drm_amdgpu[test_device_index] = i; + } + + return 0; + + +} + + +static bool amdgpu_node_is_drm(int maj, int min) +{ +#ifdef __linux__ + char path[64]; + struct stat sbuf; + + snprintf(path, sizeof(path), "/sys/dev/char/%d:%d/device/drm", + maj, min); + return stat(path, &sbuf) == 0; +#elif defined(__FreeBSD__) + char name[SPECNAMELEN]; + + if (!devname_r(makedev(maj, min), S_IFCHR, name, sizeof(name))) + return 0; + /* Handle drm/ and dri/ as both are present in different FreeBSD version + * FreeBSD on amd64/i386/powerpc external kernel modules create node in + * in /dev/drm/ and links in /dev/dri while a WIP in kernel driver creates + * only device nodes in /dev/dri/ */ + return (!strncmp(name, "drm/", 4) || !strncmp(name, "dri/", 4)); +#else + return maj == DRM_MAJOR; +#endif +} + +char *amdgpu_get_device_from_fd(int fd) +{ +#ifdef __linux__ + struct stat sbuf; + char path[PATH_MAX + 1]; + unsigned int maj, min; + + if (fstat(fd, &sbuf)) + return NULL; + + maj = major(sbuf.st_rdev); + min = minor(sbuf.st_rdev); + + if (!amdgpu_node_is_drm(maj, min) || !S_ISCHR(sbuf.st_mode)) + return NULL; + + snprintf(path, sizeof(path), "/sys/dev/char/%d:%d/device", maj, min); + return strdup(path); +#else + return NULL; +#endif } /* The main() function for setting up and running the tests. @@ -541,7 +643,6 @@ int main(int argc, char **argv) int display_devices = 0;/* By default not to display devices' info */ CU_pSuite pSuite = NULL; CU_pTest pTest = NULL; - int test_device_index; int display_list = 0; int force_run = 0; diff --git a/lib/libdrm/tests/amdgpu/amdgpu_test.h b/lib/libdrm/tests/amdgpu/amdgpu_test.h index 98cec6989..cc12756d1 100644 --- a/lib/libdrm/tests/amdgpu/amdgpu_test.h +++ b/lib/libdrm/tests/amdgpu/amdgpu_test.h @@ -273,6 +273,29 @@ amdgpu_command_submission_write_linear_helper_with_secure(amdgpu_device_handle unsigned ip_type, bool secure); + + +/** + * Initialize hotunplug test suite + */ +int suite_hotunplug_tests_init(); + +/** + * Deinitialize hotunplug test suite + */ +int suite_hotunplug_tests_clean(); + +/** + * Decide if the suite is enabled by default or not. + */ +CU_BOOL suite_hotunplug_tests_enable(void); + +/** + * Tests in uvd enc test suite + */ +extern CU_TestInfo hotunplug_tests[]; + + /** * Helper functions */ @@ -449,13 +472,18 @@ static inline CU_ErrorCode amdgpu_set_test_active(const char *suite_name, return r; } -static inline bool asic_is_arcturus(uint32_t asic_id) + +static inline bool asic_is_gfx_pipe_removed(uint32_t family_id, uint32_t chip_id, uint32_t chip_rev) { - switch(asic_id) { - /* Arcturus asic DID */ - case 0x738C: - case 0x7388: - case 0x738E: + + if (family_id != AMDGPU_FAMILY_AI) + return false; + + switch (chip_id - chip_rev) { + /* Arcturus */ + case 0x32: + /* Aldebaran */ + case 0x3c: return true; default: return false; @@ -471,4 +499,8 @@ void amdgpu_test_exec_cs_helper_raw(amdgpu_device_handle device_handle, struct amdgpu_cs_request *ibs_request, bool secure); +void amdgpu_close_devices(); +int amdgpu_open_device_on_test_index(int render_node); +char *amdgpu_get_device_from_fd(int fd); + #endif /* #ifdef _AMDGPU_TEST_H_ */ diff --git a/lib/libdrm/tests/amdgpu/basic_tests.c b/lib/libdrm/tests/amdgpu/basic_tests.c index dc9ed947d..0180f9ce6 100644 --- a/lib/libdrm/tests/amdgpu/basic_tests.c +++ b/lib/libdrm/tests/amdgpu/basic_tests.c @@ -46,6 +46,8 @@ static amdgpu_device_handle device_handle; static uint32_t major_version; static uint32_t minor_version; static uint32_t family_id; +static uint32_t chip_id; +static uint32_t chip_rev; static void amdgpu_query_info_test(void); static void amdgpu_command_submission_gfx(void); @@ -341,9 +343,10 @@ enum cs_type { }; static const uint32_t bufferclear_cs_shader_gfx9[] = { - 0xD1FD0000, 0x04010C08, 0x7E020204, 0x7E040205, - 0x7E060206, 0x7E080207, 0xE01C2000, 0x80000100, - 0xBF810000 + 0x260000ff, 0x000003ff, 0xd1fd0000, 0x04010c08, + 0x7e020280, 0x7e040204, 0x7e060205, 0x7e080206, + 0x7e0a0207, 0xe01c2000, 0x80000200, 0xbf8c0000, + 0xbf810000 }; static const uint32_t bufferclear_cs_shader_registers_gfx9[][2] = { @@ -357,8 +360,9 @@ static const uint32_t bufferclear_cs_shader_registers_gfx9[][2] = { static const uint32_t bufferclear_cs_shader_registers_num_gfx9 = 5; static const uint32_t buffercopy_cs_shader_gfx9[] = { - 0xD1FD0000, 0x04010C08, 0xE00C2000, 0x80000100, - 0xBF8C0F70, 0xE01C2000, 0x80010100, 0xBF810000 + 0x260000ff, 0x000003ff, 0xd1fd0000, 0x04010c08, + 0x7e020280, 0xe00c2000, 0x80000200, 0xbf8c0f70, + 0xe01c2000, 0x80010200, 0xbf810000 }; static const uint32_t preamblecache_gfx9[] = { @@ -617,19 +621,21 @@ int amdgpu_bo_alloc_and_map_raw(amdgpu_device_handle dev, unsigned size, CU_BOOL suite_basic_tests_enable(void) { - uint32_t asic_id; if (amdgpu_device_initialize(drm_amdgpu[0], &major_version, &minor_version, &device_handle)) return CU_FALSE; - asic_id = device_handle->info.asic_id; + + family_id = device_handle->info.family_id; + chip_id = device_handle->info.chip_external_rev; + chip_rev = device_handle->info.chip_rev; if (amdgpu_device_deinitialize(device_handle)) return CU_FALSE; - /* disable gfx engine basic test cases for Arturus due to no CPG */ - if (asic_is_arcturus(asic_id)) { + /* disable gfx engine basic test cases for some asics have no CPG */ + if (asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) { if (amdgpu_set_test_active("Basic Tests", "Command submission Test (GFX)", CU_FALSE)) @@ -1066,6 +1072,14 @@ static void amdgpu_semaphore_test(void) amdgpu_bo_list_handle bo_list[2]; amdgpu_va_handle va_handle[2]; int r, i; + struct amdgpu_gpu_info gpu_info = {0}; + unsigned gc_ip_type; + + r = amdgpu_query_gpu_info(device_handle, &gpu_info); + CU_ASSERT_EQUAL(r, 0); + + gc_ip_type = (asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) ? + AMDGPU_HW_IP_COMPUTE : AMDGPU_HW_IP_GFX; if (family_id == AMDGPU_FAMILY_SI) { sdma_nop = SDMA_PACKET_SI(SDMA_NOP_SI, 0, 0, 0, 0); @@ -1108,14 +1122,14 @@ static void amdgpu_semaphore_test(void) r = amdgpu_cs_signal_semaphore(context_handle[0], AMDGPU_HW_IP_DMA, 0, 0, sem); CU_ASSERT_EQUAL(r, 0); - r = amdgpu_cs_wait_semaphore(context_handle[0], AMDGPU_HW_IP_GFX, 0, 0, sem); + r = amdgpu_cs_wait_semaphore(context_handle[0], gc_ip_type, 0, 0, sem); CU_ASSERT_EQUAL(r, 0); ptr = ib_result_cpu[1]; ptr[0] = gfx_nop; ib_info[1].ib_mc_address = ib_result_mc_address[1]; ib_info[1].size = 1; - ibs_request[1].ip_type = AMDGPU_HW_IP_GFX; + ibs_request[1].ip_type = gc_ip_type; ibs_request[1].number_of_ibs = 1; ibs_request[1].ibs = &ib_info[1]; ibs_request[1].resources = bo_list[1]; @@ -1125,7 +1139,7 @@ static void amdgpu_semaphore_test(void) CU_ASSERT_EQUAL(r, 0); fence_status.context = context_handle[0]; - fence_status.ip_type = AMDGPU_HW_IP_GFX; + fence_status.ip_type = gc_ip_type; fence_status.ip_instance = 0; fence_status.fence = ibs_request[1].seq_no; r = amdgpu_cs_query_fence_status(&fence_status, @@ -1139,24 +1153,24 @@ static void amdgpu_semaphore_test(void) ib_info[0].ib_mc_address = ib_result_mc_address[0]; ib_info[0].size = 1; - ibs_request[0].ip_type = AMDGPU_HW_IP_GFX; + ibs_request[0].ip_type = gc_ip_type; ibs_request[0].number_of_ibs = 1; ibs_request[0].ibs = &ib_info[0]; ibs_request[0].resources = bo_list[0]; ibs_request[0].fence_info.handle = NULL; r = amdgpu_cs_submit(context_handle[0], 0,&ibs_request[0], 1); CU_ASSERT_EQUAL(r, 0); - r = amdgpu_cs_signal_semaphore(context_handle[0], AMDGPU_HW_IP_GFX, 0, 0, sem); + r = amdgpu_cs_signal_semaphore(context_handle[0], gc_ip_type, 0, 0, sem); CU_ASSERT_EQUAL(r, 0); - r = amdgpu_cs_wait_semaphore(context_handle[1], AMDGPU_HW_IP_GFX, 0, 0, sem); + r = amdgpu_cs_wait_semaphore(context_handle[1], gc_ip_type, 0, 0, sem); CU_ASSERT_EQUAL(r, 0); ptr = ib_result_cpu[1]; ptr[0] = gfx_nop; ib_info[1].ib_mc_address = ib_result_mc_address[1]; ib_info[1].size = 1; - ibs_request[1].ip_type = AMDGPU_HW_IP_GFX; + ibs_request[1].ip_type = gc_ip_type; ibs_request[1].number_of_ibs = 1; ibs_request[1].ibs = &ib_info[1]; ibs_request[1].resources = bo_list[1]; @@ -1166,7 +1180,7 @@ static void amdgpu_semaphore_test(void) CU_ASSERT_EQUAL(r, 0); fence_status.context = context_handle[1]; - fence_status.ip_type = AMDGPU_HW_IP_GFX; + fence_status.ip_type = gc_ip_type; fence_status.ip_instance = 0; fence_status.fence = ibs_request[1].seq_no; r = amdgpu_cs_query_fence_status(&fence_status, diff --git a/lib/libdrm/tests/amdgpu/bo_tests.c b/lib/libdrm/tests/amdgpu/bo_tests.c index 4c11665a7..8fc7fe26c 100644 --- a/lib/libdrm/tests/amdgpu/bo_tests.c +++ b/lib/libdrm/tests/amdgpu/bo_tests.c @@ -168,7 +168,7 @@ static void amdgpu_bo_metadata(void) struct amdgpu_bo_info info = {0}; int r; - meta.size_metadata = 1; + meta.size_metadata = 4; meta.umd_metadata[0] = 0xdeadbeef; r = amdgpu_bo_set_metadata(buffer_handle, &meta); @@ -177,7 +177,7 @@ static void amdgpu_bo_metadata(void) r = amdgpu_bo_query_info(buffer_handle, &info); CU_ASSERT_EQUAL(r, 0); - CU_ASSERT_EQUAL(info.metadata.size_metadata, 1); + CU_ASSERT_EQUAL(info.metadata.size_metadata, 4); CU_ASSERT_EQUAL(info.metadata.umd_metadata[0], 0xdeadbeef); } diff --git a/lib/libdrm/tests/amdgpu/cs_tests.c b/lib/libdrm/tests/amdgpu/cs_tests.c index 10124c159..f5096781e 100644 --- a/lib/libdrm/tests/amdgpu/cs_tests.c +++ b/lib/libdrm/tests/amdgpu/cs_tests.c @@ -64,21 +64,20 @@ CU_TestInfo cs_tests[] = { CU_BOOL suite_cs_tests_enable(void) { - uint32_t asic_id; - if (amdgpu_device_initialize(drm_amdgpu[0], &major_version, &minor_version, &device_handle)) return CU_FALSE; family_id = device_handle->info.family_id; - asic_id = device_handle->info.asic_id; + chip_id = device_handle->info.chip_external_rev; + chip_rev = device_handle->info.chip_rev; if (amdgpu_device_deinitialize(device_handle)) return CU_FALSE; if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI || - asic_is_arcturus(asic_id)) { + asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) { printf("\n\nThe ASIC NOT support UVD, suite disabled\n"); return CU_FALSE; } diff --git a/lib/libdrm/tests/amdgpu/deadlock_tests.c b/lib/libdrm/tests/amdgpu/deadlock_tests.c index 248cc339a..07a39446b 100644 --- a/lib/libdrm/tests/amdgpu/deadlock_tests.c +++ b/lib/libdrm/tests/amdgpu/deadlock_tests.c @@ -106,6 +106,10 @@ static uint32_t minor_version; static pthread_t stress_thread; static uint32_t *ptr; +static uint32_t family_id; +static uint32_t chip_rev; +static uint32_t chip_id; + int use_uc_mtype = 0; static void amdgpu_deadlock_helper(unsigned ip_type); @@ -124,25 +128,27 @@ static void amdgpu_draw_hang_slow_gfx(void); CU_BOOL suite_deadlock_tests_enable(void) { CU_BOOL enable = CU_TRUE; - uint32_t asic_id; if (amdgpu_device_initialize(drm_amdgpu[0], &major_version, &minor_version, &device_handle)) return CU_FALSE; + family_id = device_handle->info.family_id; + chip_id = device_handle->info.chip_external_rev; + chip_rev = device_handle->info.chip_rev; + /* * Only enable for ASICs supporting GPU reset and for which it's enabled * by default (currently GFX8/9 dGPUS) */ - if (device_handle->info.family_id != AMDGPU_FAMILY_VI && - device_handle->info.family_id != AMDGPU_FAMILY_AI && - device_handle->info.family_id != AMDGPU_FAMILY_CI) { + if (family_id != AMDGPU_FAMILY_VI && + family_id != AMDGPU_FAMILY_AI && + family_id != AMDGPU_FAMILY_CI) { printf("\n\nGPU reset is not enabled for the ASIC, deadlock suite disabled\n"); enable = CU_FALSE; } - asic_id = device_handle->info.asic_id; - if (asic_is_arcturus(asic_id)) { + if (asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) { if (amdgpu_set_test_active("Deadlock Tests", "gfx ring block test (set amdgpu.lockup_timeout=50)", CU_FALSE)) diff --git a/lib/libdrm/tests/amdgpu/hotunplug_tests.c b/lib/libdrm/tests/amdgpu/hotunplug_tests.c new file mode 100644 index 000000000..23ea1407e --- /dev/null +++ b/lib/libdrm/tests/amdgpu/hotunplug_tests.c @@ -0,0 +1,445 @@ +/* + * Copyright 2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * +*/ + +#include <stdlib.h> +#include <unistd.h> +#include <sys/types.h> +#include <sys/stat.h> +#include <fcntl.h> +#if HAVE_ALLOCA_H +# include <alloca.h> +#endif + +#include "CUnit/Basic.h" + +#include "amdgpu_test.h" +#include "amdgpu_drm.h" +#include "amdgpu_internal.h" +#include "xf86drm.h" +#include <pthread.h> + +#define GFX_COMPUTE_NOP 0xffff1000 + +static amdgpu_device_handle device_handle; +static uint32_t major_version; +static uint32_t minor_version; +static char *sysfs_remove = NULL; +static bool do_cs; + +CU_BOOL suite_hotunplug_tests_enable(void) +{ + CU_BOOL enable = CU_TRUE; + drmDevicePtr device; + + if (drmGetDevice2(drm_amdgpu[0], DRM_DEVICE_GET_PCI_REVISION, &device)) { + printf("\n\nGPU Failed to get DRM device PCI info!\n"); + return CU_FALSE; + } + + if (device->bustype != DRM_BUS_PCI) { + printf("\n\nGPU device is not on PCI bus!\n"); + amdgpu_device_deinitialize(device_handle); + return CU_FALSE; + } + + /* Disable until the hot-unplug support in kernel gets into drm-next */ + if (major_version < 0xff) + enable = false; + + if (amdgpu_device_initialize(drm_amdgpu[0], &major_version, + &minor_version, &device_handle)) + return CU_FALSE; + + /* TODO Once DRM version for unplug feature ready compare here agains it*/ + + if (amdgpu_device_deinitialize(device_handle)) + return CU_FALSE; + + return enable; +} + +int suite_hotunplug_tests_init(void) +{ + /* We need to open/close device at each test manually */ + amdgpu_close_devices(); + + return CUE_SUCCESS; +} + +int suite_hotunplug_tests_clean(void) +{ + + + return CUE_SUCCESS; +} + +static int amdgpu_hotunplug_trigger(const char *pathname) +{ + int fd, len; + + fd = open(pathname, O_WRONLY); + if (fd < 0) + return -errno; + + len = write(fd, "1", 1); + close(fd); + + return len; +} + +static int amdgpu_hotunplug_setup_test() +{ + int r; + char *tmp_str; + + if (amdgpu_open_device_on_test_index(open_render_node) < 0) { + printf("\n\n Failed to reopen device file!\n"); + return CUE_SINIT_FAILED; + + + + } + + r = amdgpu_device_initialize(drm_amdgpu[0], &major_version, + &minor_version, &device_handle); + + if (r) { + if ((r == -EACCES) && (errno == EACCES)) + printf("\n\nError:%s. " + "Hint:Try to run this test program as root.", + strerror(errno)); + return CUE_SINIT_FAILED; + } + + tmp_str = amdgpu_get_device_from_fd(drm_amdgpu[0]); + if (!tmp_str){ + printf("\n\n Device path not found!\n"); + return CUE_SINIT_FAILED; + } + + sysfs_remove = realloc(tmp_str, strlen(tmp_str) * 2); + strcat(sysfs_remove, "/remove"); + + return 0; +} + +static int amdgpu_hotunplug_teardown_test() +{ + if (amdgpu_device_deinitialize(device_handle)) + return CUE_SCLEAN_FAILED; + + amdgpu_close_devices(); + + if (sysfs_remove) + free(sysfs_remove); + + return 0; +} + +static inline int amdgpu_hotunplug_remove() +{ + return amdgpu_hotunplug_trigger(sysfs_remove); +} + +static inline int amdgpu_hotunplug_rescan() +{ + return amdgpu_hotunplug_trigger("/sys/bus/pci/rescan"); +} + +static int amdgpu_cs_sync(amdgpu_context_handle context, + unsigned int ip_type, + int ring, + unsigned int seqno) +{ + struct amdgpu_cs_fence fence = { + .context = context, + .ip_type = ip_type, + .ring = ring, + .fence = seqno, + }; + uint32_t expired; + + return amdgpu_cs_query_fence_status(&fence, + AMDGPU_TIMEOUT_INFINITE, + 0, &expired); +} + +static void *amdgpu_nop_cs() +{ + amdgpu_bo_handle ib_result_handle; + void *ib_result_cpu; + uint64_t ib_result_mc_address; + uint32_t *ptr; + int i, r; + amdgpu_bo_list_handle bo_list; + amdgpu_va_handle va_handle; + amdgpu_context_handle context; + struct amdgpu_cs_request ibs_request; + struct amdgpu_cs_ib_info ib_info; + + r = amdgpu_cs_ctx_create(device_handle, &context); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096, + AMDGPU_GEM_DOMAIN_GTT, 0, + &ib_result_handle, &ib_result_cpu, + &ib_result_mc_address, &va_handle); + CU_ASSERT_EQUAL(r, 0); + + ptr = ib_result_cpu; + for (i = 0; i < 16; ++i) + ptr[i] = GFX_COMPUTE_NOP; + + r = amdgpu_bo_list_create(device_handle, 1, &ib_result_handle, NULL, &bo_list); + CU_ASSERT_EQUAL(r, 0); + + memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info)); + ib_info.ib_mc_address = ib_result_mc_address; + ib_info.size = 16; + + memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request)); + ibs_request.ip_type = AMDGPU_HW_IP_GFX; + ibs_request.ring = 0; + ibs_request.number_of_ibs = 1; + ibs_request.ibs = &ib_info; + ibs_request.resources = bo_list; + + while (do_cs) + amdgpu_cs_submit(context, 0, &ibs_request, 1); + + amdgpu_cs_sync(context, AMDGPU_HW_IP_GFX, 0, ibs_request.seq_no); + amdgpu_bo_list_destroy(bo_list); + amdgpu_bo_unmap_and_free(ib_result_handle, va_handle, + ib_result_mc_address, 4096); + + amdgpu_cs_ctx_free(context); + + return (void *)0; +} + +static pthread_t* amdgpu_create_cs_thread() +{ + int r; + pthread_t *thread = malloc(sizeof(*thread)); + if (!thread) + return NULL; + + do_cs = true; + + r = pthread_create(thread, NULL, amdgpu_nop_cs, NULL); + CU_ASSERT_EQUAL(r, 0); + + /* Give thread enough time to start*/ + usleep(100000); + return thread; +} + +static void amdgpu_destroy_cs_thread(pthread_t *thread) +{ + void *status; + + do_cs = false; + + pthread_join(*thread, &status); + CU_ASSERT_EQUAL(status, 0); + + free(thread); +} + + +static void amdgpu_hotunplug_test(bool with_cs) +{ + int r; + pthread_t *thread = NULL; + + r = amdgpu_hotunplug_setup_test(); + CU_ASSERT_EQUAL(r , 0); + + if (with_cs) { + thread = amdgpu_create_cs_thread(); + CU_ASSERT_NOT_EQUAL(thread, NULL); + } + + r = amdgpu_hotunplug_remove(); + CU_ASSERT_EQUAL(r > 0, 1); + + if (with_cs) + amdgpu_destroy_cs_thread(thread); + + r = amdgpu_hotunplug_teardown_test(); + CU_ASSERT_EQUAL(r , 0); + + r = amdgpu_hotunplug_rescan(); + CU_ASSERT_EQUAL(r > 0, 1); +} + +static void amdgpu_hotunplug_simple(void) +{ + amdgpu_hotunplug_test(false); +} + +static void amdgpu_hotunplug_with_cs(void) +{ + amdgpu_hotunplug_test(true); +} + +static void amdgpu_hotunplug_with_exported_bo(void) +{ + int r; + uint32_t dma_buf_fd; + unsigned int *ptr; + amdgpu_bo_handle bo_handle; + + struct amdgpu_bo_alloc_request request = { + .alloc_size = 4096, + .phys_alignment = 4096, + .preferred_heap = AMDGPU_GEM_DOMAIN_GTT, + .flags = 0, + }; + + r = amdgpu_hotunplug_setup_test(); + CU_ASSERT_EQUAL(r , 0); + + amdgpu_bo_alloc(device_handle, &request, &bo_handle); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_export(bo_handle, amdgpu_bo_handle_type_dma_buf_fd, &dma_buf_fd); + CU_ASSERT_EQUAL(r, 0); + + ptr = mmap(NULL, 4096, PROT_READ | PROT_WRITE, MAP_SHARED, dma_buf_fd, 0); + CU_ASSERT_NOT_EQUAL(ptr, MAP_FAILED); + + r = amdgpu_hotunplug_remove(); + CU_ASSERT_EQUAL(r > 0, 1); + + amdgpu_bo_free(bo_handle); + + r = amdgpu_hotunplug_teardown_test(); + CU_ASSERT_EQUAL(r , 0); + + *ptr = 0xdeafbeef; + + munmap(ptr, 4096); + close (dma_buf_fd); + + r = amdgpu_hotunplug_rescan(); + CU_ASSERT_EQUAL(r > 0, 1); +} + +static void amdgpu_hotunplug_with_exported_fence(void) +{ + amdgpu_bo_handle ib_result_handle; + void *ib_result_cpu; + uint64_t ib_result_mc_address; + uint32_t *ptr, sync_obj_handle, sync_obj_handle2; + int i, r; + amdgpu_bo_list_handle bo_list; + amdgpu_va_handle va_handle; + uint32_t major2, minor2; + amdgpu_device_handle device2; + amdgpu_context_handle context; + struct amdgpu_cs_request ibs_request; + struct amdgpu_cs_ib_info ib_info; + struct amdgpu_cs_fence fence_status = {0}; + int shared_fd; + + r = amdgpu_hotunplug_setup_test(); + CU_ASSERT_EQUAL(r , 0); + + r = amdgpu_device_initialize(drm_amdgpu[1], &major2, &minor2, &device2); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_cs_ctx_create(device_handle, &context); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096, + AMDGPU_GEM_DOMAIN_GTT, 0, + &ib_result_handle, &ib_result_cpu, + &ib_result_mc_address, &va_handle); + CU_ASSERT_EQUAL(r, 0); + + ptr = ib_result_cpu; + for (i = 0; i < 16; ++i) + ptr[i] = GFX_COMPUTE_NOP; + + r = amdgpu_bo_list_create(device_handle, 1, &ib_result_handle, NULL, &bo_list); + CU_ASSERT_EQUAL(r, 0); + + memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info)); + ib_info.ib_mc_address = ib_result_mc_address; + ib_info.size = 16; + + memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request)); + ibs_request.ip_type = AMDGPU_HW_IP_GFX; + ibs_request.ring = 0; + ibs_request.number_of_ibs = 1; + ibs_request.ibs = &ib_info; + ibs_request.resources = bo_list; + + CU_ASSERT_EQUAL(amdgpu_cs_submit(context, 0, &ibs_request, 1), 0); + + fence_status.context = context; + fence_status.ip_type = AMDGPU_HW_IP_GFX; + fence_status.ip_instance = 0; + fence_status.fence = ibs_request.seq_no; + + CU_ASSERT_EQUAL(amdgpu_cs_fence_to_handle(device_handle, &fence_status, + AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ, + &sync_obj_handle), + 0); + + CU_ASSERT_EQUAL(amdgpu_cs_export_syncobj(device_handle, sync_obj_handle, &shared_fd), 0); + + CU_ASSERT_EQUAL(amdgpu_cs_import_syncobj(device2, shared_fd, &sync_obj_handle2), 0); + + CU_ASSERT_EQUAL(amdgpu_cs_destroy_syncobj(device_handle, sync_obj_handle), 0); + + CU_ASSERT_EQUAL(amdgpu_bo_list_destroy(bo_list), 0); + CU_ASSERT_EQUAL(amdgpu_bo_unmap_and_free(ib_result_handle, va_handle, + ib_result_mc_address, 4096), 0); + CU_ASSERT_EQUAL(amdgpu_cs_ctx_free(context), 0); + + r = amdgpu_hotunplug_remove(); + CU_ASSERT_EQUAL(r > 0, 1); + + CU_ASSERT_EQUAL(amdgpu_cs_syncobj_wait(device2, &sync_obj_handle2, 1, 100000000, 0, NULL), 0); + + CU_ASSERT_EQUAL(amdgpu_cs_destroy_syncobj(device2, sync_obj_handle2), 0); + + amdgpu_device_deinitialize(device2); + + r = amdgpu_hotunplug_teardown_test(); + CU_ASSERT_EQUAL(r , 0); + + r = amdgpu_hotunplug_rescan(); + CU_ASSERT_EQUAL(r > 0, 1); +} + + +CU_TestInfo hotunplug_tests[] = { + { "Unplug card and rescan the bus to plug it back", amdgpu_hotunplug_simple }, + { "Same as first test but with command submission", amdgpu_hotunplug_with_cs }, + { "Unplug with exported bo", amdgpu_hotunplug_with_exported_bo }, + { "Unplug with exported fence", amdgpu_hotunplug_with_exported_fence }, + CU_TEST_INFO_NULL, +}; diff --git a/lib/libdrm/tests/amdgpu/meson.build b/lib/libdrm/tests/amdgpu/meson.build index eb16a50c1..e6e308122 100644 --- a/lib/libdrm/tests/amdgpu/meson.build +++ b/lib/libdrm/tests/amdgpu/meson.build @@ -25,6 +25,7 @@ if dep_cunit.found() 'amdgpu_test.c', 'basic_tests.c', 'bo_tests.c', 'cs_tests.c', 'vce_tests.c', 'uvd_enc_tests.c', 'vcn_tests.c', 'deadlock_tests.c', 'vm_tests.c', 'ras_tests.c', 'syncobj_tests.c', 'security_tests.c', + 'hotunplug_tests.c' ), dependencies : [dep_cunit, dep_threads, dep_atomic_ops], include_directories : [inc_root, inc_drm, include_directories('../../amdgpu')], diff --git a/lib/libdrm/tests/amdgpu/security_tests.c b/lib/libdrm/tests/amdgpu/security_tests.c index eed695a38..f0eb57a7b 100644 --- a/lib/libdrm/tests/amdgpu/security_tests.c +++ b/lib/libdrm/tests/amdgpu/security_tests.c @@ -432,7 +432,8 @@ CU_BOOL suite_security_tests_enable(void) &minor_version, &device_handle)) return CU_FALSE; - if (device_handle->info.family_id != AMDGPU_FAMILY_RV) { + + if (!(device_handle->dev_info.ids_flags & AMDGPU_IDS_FLAGS_TMZ)) { printf("\n\nDon't support TMZ (trust memory zone), security suite disabled\n"); enable = CU_FALSE; } diff --git a/lib/libdrm/tests/amdgpu/syncobj_tests.c b/lib/libdrm/tests/amdgpu/syncobj_tests.c index 3a7b38eb1..690bea018 100644 --- a/lib/libdrm/tests/amdgpu/syncobj_tests.c +++ b/lib/libdrm/tests/amdgpu/syncobj_tests.c @@ -33,6 +33,10 @@ static amdgpu_device_handle device_handle; static uint32_t major_version; static uint32_t minor_version; +static uint32_t family_id; +static uint32_t chip_id; +static uint32_t chip_rev; + static void amdgpu_syncobj_timeline_test(void); CU_BOOL suite_syncobj_timeline_tests_enable(void) @@ -100,6 +104,18 @@ static int syncobj_command_submission_helper(uint32_t syncobj_handle, bool int i, r; uint64_t seq_no; static uint32_t *ptr; + struct amdgpu_gpu_info gpu_info = {0}; + unsigned gc_ip_type; + + r = amdgpu_query_gpu_info(device_handle, &gpu_info); + CU_ASSERT_EQUAL(r, 0); + + family_id = device_handle->info.family_id; + chip_id = device_handle->info.chip_external_rev; + chip_rev = device_handle->info.chip_rev; + + gc_ip_type = (asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) ? + AMDGPU_HW_IP_COMPUTE : AMDGPU_HW_IP_GFX; r = amdgpu_cs_ctx_create(device_handle, &context_handle); CU_ASSERT_EQUAL(r, 0); @@ -125,11 +141,11 @@ static int syncobj_command_submission_helper(uint32_t syncobj_handle, bool chunk_data.ib_data._pad = 0; chunk_data.ib_data.va_start = ib_result_mc_address; chunk_data.ib_data.ib_bytes = 16 * 4; - chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX : + chunk_data.ib_data.ip_type = wait_or_signal ? gc_ip_type : AMDGPU_HW_IP_DMA; chunk_data.ib_data.ip_instance = 0; chunk_data.ib_data.ring = 0; - chunk_data.ib_data.flags = 0; + chunk_data.ib_data.flags = AMDGPU_IB_FLAG_EMIT_MEM_SYNC; chunks[1].chunk_id = wait_or_signal ? AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT : @@ -151,7 +167,7 @@ static int syncobj_command_submission_helper(uint32_t syncobj_handle, bool memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence)); fence_status.context = context_handle; - fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX: + fence_status.ip_type = wait_or_signal ? gc_ip_type : AMDGPU_HW_IP_DMA; fence_status.ip_instance = 0; fence_status.ring = 0; diff --git a/lib/libdrm/tests/amdgpu/vce_tests.c b/lib/libdrm/tests/amdgpu/vce_tests.c index 5434e4445..4e925cae2 100644 --- a/lib/libdrm/tests/amdgpu/vce_tests.c +++ b/lib/libdrm/tests/amdgpu/vce_tests.c @@ -116,7 +116,7 @@ CU_BOOL suite_vce_tests_enable(void) return CU_FALSE; if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI || - asic_is_arcturus(asic_id)) { + asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) { printf("\n\nThe ASIC NOT support VCE, suite disabled\n"); return CU_FALSE; } diff --git a/lib/libdrm/tests/amdgpu/vcn_tests.c b/lib/libdrm/tests/amdgpu/vcn_tests.c index 3a4588623..628b4910f 100644 --- a/lib/libdrm/tests/amdgpu/vcn_tests.c +++ b/lib/libdrm/tests/amdgpu/vcn_tests.c @@ -102,8 +102,6 @@ CU_BOOL suite_vcn_tests_enable(void) return CU_FALSE; family_id = device_handle->info.family_id; - chip_rev = device_handle->info.chip_rev; - chip_id = device_handle->info.chip_external_rev; asic_id = device_handle->info.asic_id; chip_rev = device_handle->info.chip_rev; chip_id = device_handle->info.chip_external_rev; @@ -116,7 +114,7 @@ CU_BOOL suite_vcn_tests_enable(void) if (r != 0 || !info.available_rings || (family_id < AMDGPU_FAMILY_RV && (family_id == AMDGPU_FAMILY_AI && - chip_id != (chip_rev + 0x32)))) { /* Arcturus */ + (chip_id - chip_rev) < 0x32))) { /* Arcturus */ printf("\n\nThe ASIC NOT support VCN, suite disabled\n"); return CU_FALSE; } @@ -142,7 +140,9 @@ CU_BOOL suite_vcn_tests_enable(void) reg.cntl = 0x81c6; } } else if (family_id == AMDGPU_FAMILY_NV) { - if (chip_id == (chip_rev + 0x28)) { + if (chip_id == (chip_rev + 0x28) || + chip_id == (chip_rev + 0x32) || + chip_id == (chip_rev + 0x3c)) { reg.data0 = 0x10; reg.data1 = 0x11; reg.cmd = 0xf; diff --git a/lib/libdrm/tests/amdgpu/vm_tests.c b/lib/libdrm/tests/amdgpu/vm_tests.c index 95011ea06..b94999c54 100644 --- a/lib/libdrm/tests/amdgpu/vm_tests.c +++ b/lib/libdrm/tests/amdgpu/vm_tests.c @@ -30,6 +30,9 @@ static amdgpu_device_handle device_handle; static uint32_t major_version; static uint32_t minor_version; +static uint32_t family_id; +static uint32_t chip_id; +static uint32_t chip_rev; static void amdgpu_vmid_reserve_test(void); static void amdgpu_vm_unaligned_map(void); @@ -110,7 +113,11 @@ static void amdgpu_vmid_reserve_test(void) r = amdgpu_query_gpu_info(device_handle, &gpu_info); CU_ASSERT_EQUAL(r, 0); - gc_ip_type = (asic_is_arcturus(gpu_info.asic_id)) ? + family_id = device_handle->info.family_id; + chip_id = device_handle->info.chip_external_rev; + chip_rev = device_handle->info.chip_rev; + + gc_ip_type = (asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) ? AMDGPU_HW_IP_COMPUTE : AMDGPU_HW_IP_GFX; r = amdgpu_cs_ctx_create(device_handle, &context_handle); diff --git a/lib/libdrm/tests/modetest/modetest.c b/lib/libdrm/tests/modetest/modetest.c index fc75383a4..2c83bd030 100644 --- a/lib/libdrm/tests/modetest/modetest.c +++ b/lib/libdrm/tests/modetest/modetest.c @@ -265,52 +265,37 @@ static void dump_blob(struct device *dev, uint32_t blob_id) static const char *modifier_to_string(uint64_t modifier) { - switch (modifier) { - case DRM_FORMAT_MOD_INVALID: - return "INVALID"; - case DRM_FORMAT_MOD_LINEAR: - return "LINEAR"; - case I915_FORMAT_MOD_X_TILED: - return "X_TILED"; - case I915_FORMAT_MOD_Y_TILED: - return "Y_TILED"; - case I915_FORMAT_MOD_Yf_TILED: - return "Yf_TILED"; - case I915_FORMAT_MOD_Y_TILED_CCS: - return "Y_TILED_CCS"; - case I915_FORMAT_MOD_Yf_TILED_CCS: - return "Yf_TILED_CCS"; - case DRM_FORMAT_MOD_SAMSUNG_64_32_TILE: - return "SAMSUNG_64_32_TILE"; - case DRM_FORMAT_MOD_VIVANTE_TILED: - return "VIVANTE_TILED"; - case DRM_FORMAT_MOD_VIVANTE_SUPER_TILED: - return "VIVANTE_SUPER_TILED"; - case DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED: - return "VIVANTE_SPLIT_TILED"; - case DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED: - return "VIVANTE_SPLIT_SUPER_TILED"; - case DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED: - return "NVIDIA_TEGRA_TILED"; - case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0): - return "NVIDIA_16BX2_BLOCK(0)"; - case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1): - return "NVIDIA_16BX2_BLOCK(1)"; - case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2): - return "NVIDIA_16BX2_BLOCK(2)"; - case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3): - return "NVIDIA_16BX2_BLOCK(3)"; - case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4): - return "NVIDIA_16BX2_BLOCK(4)"; - case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5): - return "NVIDIA_16BX2_BLOCK(5)"; - case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED: - return "MOD_BROADCOM_VC4_T_TILED"; - case DRM_FORMAT_MOD_QCOM_COMPRESSED: - return "QCOM_COMPRESSED"; - default: - return "(UNKNOWN MODIFIER)"; + static char mod_string[4096]; + + char *modifier_name = drmGetFormatModifierName(modifier); + char *vendor_name = drmGetFormatModifierVendor(modifier); + memset(mod_string, 0x00, sizeof(mod_string)); + + if (!modifier_name) { + if (vendor_name) + snprintf(mod_string, sizeof(mod_string), "%s_%s", + vendor_name, "UNKNOWN_MODIFIER"); + else + snprintf(mod_string, sizeof(mod_string), "%s_%s", + "UNKNOWN_VENDOR", "UNKNOWN_MODIFIER"); + /* safe, as free is no-op for NULL */ + free(vendor_name); + return mod_string; } + + if (modifier == DRM_FORMAT_MOD_LINEAR) { + snprintf(mod_string, sizeof(mod_string), "%s", modifier_name); + free(modifier_name); + free(vendor_name); + return mod_string; + } + + snprintf(mod_string, sizeof(mod_string), "%s_%s", + vendor_name, modifier_name); + + free(modifier_name); + free(vendor_name); + return mod_string; } static void dump_in_formats(struct device *dev, uint32_t blob_id) diff --git a/lib/libdrm/tests/util/kms.c b/lib/libdrm/tests/util/kms.c index 08b48fe58..39a93866a 100644 --- a/lib/libdrm/tests/util/kms.c +++ b/lib/libdrm/tests/util/kms.c @@ -149,6 +149,7 @@ static const char * const modules[] = { "armada-drm", "komeda", "imx-dcss", + "mxsfb-drm", }; int util_open(const char *device, const char *module) diff --git a/lib/libdrm/tests/util/pattern.c b/lib/libdrm/tests/util/pattern.c index bf1797d40..158c0b160 100644 --- a/lib/libdrm/tests/util/pattern.c +++ b/lib/libdrm/tests/util/pattern.c @@ -985,7 +985,6 @@ static void fill_tiles_rgb16fp(const struct util_format_info *info, void *mem, unsigned int stride) { const struct util_rgb_info *rgb = &info->rgb; - void *mem_base = mem; unsigned int x, y; /* TODO: Give this actual fp16 precision */ @@ -1113,7 +1112,7 @@ static void fill_gradient_rgb32(const struct util_rgb_info *rgb, unsigned int width, unsigned int height, unsigned int stride) { - int i, j; + unsigned int i, j; for (i = 0; i < height / 2; i++) { uint32_t *row = mem; @@ -1141,7 +1140,7 @@ static void fill_gradient_rgb16fp(const struct util_rgb_info *rgb, unsigned int width, unsigned int height, unsigned int stride) { - int i, j; + unsigned int i, j; for (i = 0; i < height / 2; i++) { uint64_t *row = mem; |