diff options
Diffstat (limited to 'lib/mesa/src/gallium/drivers/etnaviv')
49 files changed, 1467 insertions, 3136 deletions
diff --git a/lib/mesa/src/gallium/drivers/etnaviv/Automake.inc b/lib/mesa/src/gallium/drivers/etnaviv/Automake.inc deleted file mode 100644 index f9b39567e..000000000 --- a/lib/mesa/src/gallium/drivers/etnaviv/Automake.inc +++ /dev/null @@ -1,11 +0,0 @@ -if HAVE_GALLIUM_ETNAVIV - -TARGET_DRIVERS += etnaviv -TARGET_CPPFLAGS += -DGALLIUM_ETNAVIV -TARGET_LIB_DEPS += \ - $(top_builddir)/src/gallium/winsys/etnaviv/drm/libetnavivdrm.la \ - $(top_builddir)/src/gallium/drivers/etnaviv/libetnaviv.la \ - $(ETNAVIV_LIBS) \ - $(LIBDRM_LIBS) - -endif diff --git a/lib/mesa/src/gallium/drivers/etnaviv/Makefile.am b/lib/mesa/src/gallium/drivers/etnaviv/Makefile.am deleted file mode 100644 index 81ef3c9f3..000000000 --- a/lib/mesa/src/gallium/drivers/etnaviv/Makefile.am +++ /dev/null @@ -1,46 +0,0 @@ -# Copyright © 2013 W.J. van der Laan -# -# Permission is hereby granted, free of charge, to any person obtaining a -# copy of this software and associated documentation files (the "Software"), -# to deal in the Software without restriction, including without limitation -# the rights to use, copy, modify, merge, publish, distribute, sublicense, -# and/or sell copies of the Software, and to permit persons to whom the -# Software is furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice (including the next -# paragraph) shall be included in all copies or substantial portions of the -# Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -# HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER -# DEALINGS IN THE SOFTWARE. - -include Makefile.sources -include $(top_srcdir)/src/gallium/Automake.inc - -noinst_LTLIBRARIES = libetnaviv.la - -AM_CPPFLAGS = \ - $(GALLIUM_DRIVER_CFLAGS) \ - $(ETNAVIV_CFLAGS) - -libetnaviv_la_SOURCES = $(C_SOURCES) - -noinst_PROGRAMS = etnaviv_compiler - -etnaviv_compiler_SOURCES = \ - etnaviv_compiler_cmdline.c - -etnaviv_compiler_LDADD = \ - libetnaviv.la \ - $(top_builddir)/src/gallium/auxiliary/libgallium.la \ - $(top_builddir)/src/util/libmesautil.la \ - $(GALLIUM_COMMON_LIB_DEPS) \ - $(ETNAVIV_LIBS) - -EXTRA_DIST = meson.build diff --git a/lib/mesa/src/gallium/drivers/etnaviv/Makefile.in b/lib/mesa/src/gallium/drivers/etnaviv/Makefile.in deleted file mode 100644 index f8d5909b0..000000000 --- a/lib/mesa/src/gallium/drivers/etnaviv/Makefile.in +++ /dev/null @@ -1,1016 +0,0 @@ -# Makefile.in generated by automake 1.12.6 from Makefile.am. -# @configure_input@ - -# Copyright (C) 1994-2012 Free Software Foundation, Inc. - -# This Makefile.in is free software; the Free Software Foundation -# gives unlimited permission to copy and/or distribute it, -# with or without modifications, as long as this notice is preserved. - -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY, to the extent permitted by law; without -# even the implied warranty of MERCHANTABILITY or FITNESS FOR A -# PARTICULAR PURPOSE. - -@SET_MAKE@ - -# Copyright © 2013 W.J. van der Laan -# -# Permission is hereby granted, free of charge, to any person obtaining a -# copy of this software and associated documentation files (the "Software"), -# to deal in the Software without restriction, including without limitation -# the rights to use, copy, modify, merge, publish, distribute, sublicense, -# and/or sell copies of the Software, and to permit persons to whom the -# Software is furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice (including the next -# paragraph) shall be included in all copies or substantial portions of the -# Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -# HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER -# DEALINGS IN THE SOFTWARE. - - -VPATH = @srcdir@ -am__make_dryrun = \ - { \ - am__dry=no; \ - case $$MAKEFLAGS in \ - *\\[\ \ ]*) \ - echo 'am--echo: ; @echo "AM" OK' | $(MAKE) -f - 2>/dev/null \ - | grep '^AM OK$$' >/dev/null || am__dry=yes;; \ - *) \ - for am__flg in $$MAKEFLAGS; do \ - case $$am__flg in \ - *=*|--*) ;; \ - *n*) am__dry=yes; break;; \ - esac; \ - done;; \ - esac; \ - test $$am__dry = yes; \ - } -pkgdatadir = $(datadir)/@PACKAGE@ -pkgincludedir = $(includedir)/@PACKAGE@ -pkglibdir = $(libdir)/@PACKAGE@ -pkglibexecdir = $(libexecdir)/@PACKAGE@ -am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd -install_sh_DATA = $(install_sh) -c -m 644 -install_sh_PROGRAM = $(install_sh) -c -install_sh_SCRIPT = $(install_sh) -c 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-# Otherwise a system limit (for SysV at least) may be exceeded. -.NOEXPORT: diff --git a/lib/mesa/src/gallium/drivers/etnaviv/Makefile.sources b/lib/mesa/src/gallium/drivers/etnaviv/Makefile.sources index ec7ef8438..e74f7efe9 100644 --- a/lib/mesa/src/gallium/drivers/etnaviv/Makefile.sources +++ b/lib/mesa/src/gallium/drivers/etnaviv/Makefile.sources @@ -34,14 +34,16 @@ C_SOURCES := \ etnaviv_format.c \ etnaviv_format.h \ etnaviv_internal.h \ + etnaviv_perfmon.c \ + etnaviv_perfmon.h \ etnaviv_query.c \ etnaviv_query.h \ - etnaviv_query_hw.c \ - etnaviv_query_hw.h \ + etnaviv_query_acc_occlusion.c \ + etnaviv_query_acc_perfmon.c \ + etnaviv_query_acc.c \ + etnaviv_query_acc.h \ etnaviv_query_sw.c \ etnaviv_query_sw.h \ - etnaviv_query_pm.c \ - etnaviv_query_pm.h \ etnaviv_rasterizer.c \ etnaviv_rasterizer.h \ etnaviv_resource.c \ @@ -58,6 +60,8 @@ C_SOURCES := \ etnaviv_surface.h \ etnaviv_texture.c \ etnaviv_texture.h \ + etnaviv_texture_desc.c \ + etnaviv_texture_desc.h \ etnaviv_texture_state.c \ etnaviv_texture_state.h \ etnaviv_tiling.c \ diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_asm.h b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_asm.h index e91e08a20..03e18a7b4 100644 --- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_asm.h +++ b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_asm.h @@ -29,6 +29,7 @@ #include <stdint.h> #include <stdbool.h> +#include "util/u_math.h" #include "hw/isa.xml.h" /* Size of an instruction in 32-bit words */ @@ -145,6 +146,21 @@ etna_immediate_src(unsigned type, uint32_t bits) }; } +static inline struct etna_inst_src +etna_immediate_float(float x) +{ + uint32_t bits = fui(x); + assert((bits & 0xfff) == 0); /* 12 lsb cut off */ + return etna_immediate_src(0, bits >> 12); +} + +static inline struct etna_inst_src +etna_immediate_int(int x) +{ + assert(x >= -0x80000 && x < 0x80000); /* 20-bit signed int */ + return etna_immediate_src(1, x); +} + /** * Build vivante instruction from structure with * opcode, cond, sat, dst_use, dst_amode, diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_blend.c b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_blend.c index 1f57499e4..b9a7c0373 100644 --- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_blend.c +++ b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_blend.c @@ -123,7 +123,7 @@ etna_update_blend(struct etna_context *ctx) uint32_t colormask; if (pfb->cbufs[0] && - translate_rs_format_rb_swap(pfb->cbufs[0]->format)) { + translate_pe_format_rb_swap(pfb->cbufs[0]->format)) { colormask = rt0->colormask & (PIPE_MASK_A | PIPE_MASK_G); if (rt0->colormask & PIPE_MASK_R) colormask |= PIPE_MASK_B; @@ -164,7 +164,7 @@ etna_update_blend_color(struct etna_context *ctx) { struct pipe_framebuffer_state *pfb = &ctx->framebuffer_s; struct compiled_blend_color *cs = &ctx->blend_color; - bool rb_swap = (pfb->cbufs[0] && translate_rs_format_rb_swap(pfb->cbufs[0]->format)); + bool rb_swap = (pfb->cbufs[0] && translate_pe_format_rb_swap(pfb->cbufs[0]->format)); cs->PE_ALPHA_BLEND_COLOR = VIVS_PE_ALPHA_BLEND_COLOR_R(etna_cfloat_to_uint8(cs->color[rb_swap ? 2 : 0])) | diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_clear_blit.c b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_clear_blit.c index df12e609a..7b0da00c6 100644 --- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_clear_blit.c +++ b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_clear_blit.c @@ -48,12 +48,14 @@ void etna_blit_save_state(struct etna_context *ctx) { + util_blitter_save_fragment_constant_buffer_slot(ctx->blitter, + ctx->constant_buffer[PIPE_SHADER_FRAGMENT].cb); util_blitter_save_vertex_buffer_slot(ctx->blitter, ctx->vertex_buffer.vb); util_blitter_save_vertex_elements(ctx->blitter, ctx->vertex_elements); util_blitter_save_vertex_shader(ctx->blitter, ctx->shader.bind_vs); util_blitter_save_rasterizer(ctx->blitter, ctx->rasterizer); util_blitter_save_viewport(ctx->blitter, &ctx->viewport_s); - util_blitter_save_scissor(ctx->blitter, &ctx->scissor_s); + util_blitter_save_scissor(ctx->blitter, &ctx->scissor); util_blitter_save_fragment_shader(ctx->blitter, ctx->shader.bind_fs); util_blitter_save_blend(ctx->blitter, ctx->blend); util_blitter_save_depth_stencil_alpha(ctx->blitter, ctx->zsa); @@ -66,15 +68,57 @@ etna_blit_save_state(struct etna_context *ctx) ctx->num_fragment_sampler_views, ctx->sampler_view); } -uint32_t -etna_clear_blit_pack_rgba(enum pipe_format format, const float *rgba) +uint64_t +etna_clear_blit_pack_rgba(enum pipe_format format, const union pipe_color_union *color) { union util_color uc; - util_pack_color(rgba, format, &uc); - if (util_format_get_blocksize(format) == 2) - return uc.ui[0] << 16 | (uc.ui[0] & 0xffff); - else - return uc.ui[0]; + + if (util_format_is_pure_uint(format)) { + util_format_write_4ui(format, color->ui, 0, &uc, 0, 0, 0, 1, 1); + } else if (util_format_is_pure_sint(format)) { + util_format_write_4i(format, color->i, 0, &uc, 0, 0, 0, 1, 1); + } else { + util_pack_color(color->f, format, &uc); + } + + switch (util_format_get_blocksize(format)) { + case 1: + uc.ui[0] = uc.ui[0] << 8 | (uc.ui[0] & 0xff); + case 2: + uc.ui[0] = uc.ui[0] << 16 | (uc.ui[0] & 0xffff); + case 4: + uc.ui[1] = uc.ui[0]; + default: + return (uint64_t) uc.ui[1] << 32 | uc.ui[0]; + } +} + +static void +etna_blit(struct pipe_context *pctx, const struct pipe_blit_info *blit_info) +{ + struct etna_context *ctx = etna_context(pctx); + struct pipe_blit_info info = *blit_info; + + if (ctx->blit(pctx, &info)) + return; + + if (util_try_blit_via_copy_region(pctx, &info)) + return; + + if (info.mask & PIPE_MASK_S) { + DBG("cannot blit stencil, skipping"); + info.mask &= ~PIPE_MASK_S; + } + + if (!util_blitter_is_blit_supported(ctx->blitter, &info)) { + DBG("blit unsupported %s -> %s", + util_format_short_name(info.src.resource->format), + util_format_short_name(info.dst.resource->format)); + return; + } + + etna_blit_save_state(ctx); + util_blitter_blit(ctx->blitter, &info); } static void @@ -114,9 +158,6 @@ etna_resource_copy_region(struct pipe_context *pctx, struct pipe_resource *dst, { struct etna_context *ctx = etna_context(pctx); - /* The resource must be of the same format. */ - assert(src->format == dst->format); - /* XXX we can use the RS as a literal copy engine here * the only complexity is tiling; the size of the boxes needs to be aligned * to the tile size @@ -141,10 +182,10 @@ etna_flush_resource(struct pipe_context *pctx, struct pipe_resource *prsc) { struct etna_resource *rsc = etna_resource(prsc); - if (rsc->external) { - if (etna_resource_older(etna_resource(rsc->external), rsc)) { - etna_copy_resource(pctx, rsc->external, prsc, 0, 0); - etna_resource(rsc->external)->seqno = rsc->seqno; + if (rsc->render) { + if (etna_resource_older(rsc, etna_resource(rsc->render))) { + etna_copy_resource(pctx, prsc, rsc->render, 0, 0); + rsc->seqno = etna_resource(rsc->render)->seqno; } } else if (etna_resource_needs_flush(rsc)) { etna_copy_resource(pctx, prsc, prsc, 0, 0); @@ -223,13 +264,15 @@ void etna_clear_blit_init(struct pipe_context *pctx) { struct etna_context *ctx = etna_context(pctx); + struct etna_screen *screen = ctx->screen; + pctx->blit = etna_blit; pctx->clear_render_target = etna_clear_render_target; pctx->clear_depth_stencil = etna_clear_depth_stencil; pctx->resource_copy_region = etna_resource_copy_region; pctx->flush_resource = etna_flush_resource; - if (ctx->specs.use_blt) + if (screen->specs.use_blt) etna_clear_blit_blt_init(pctx); else etna_clear_blit_rs_init(pctx); diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_clear_blit.h b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_clear_blit.h index 05a7b64a9..2249a5b12 100644 --- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_clear_blit.h +++ b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_clear_blit.h @@ -36,7 +36,7 @@ struct etna_surface; void etna_rs_gen_clear_surface(struct etna_context *ctx, struct etna_surface *surf, - uint32_t clear_value); + uint64_t clear_value); void etna_copy_resource(struct pipe_context *pctx, struct pipe_resource *dst, @@ -50,8 +50,8 @@ etna_copy_resource_box(struct pipe_context *pctx, struct pipe_resource *dst, void etna_blit_save_state(struct etna_context *ctx); -uint32_t -etna_clear_blit_pack_rgba(enum pipe_format format, const float *rgba); +uint64_t +etna_clear_blit_pack_rgba(enum pipe_format format, const union pipe_color_union *color); void etna_clear_blit_init(struct pipe_context *pctx); diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_context.c b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_context.c index 6919d1367..34698ce56 100644 --- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_context.c +++ b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_context.c @@ -34,7 +34,7 @@ #include "etnaviv_emit.h" #include "etnaviv_fence.h" #include "etnaviv_query.h" -#include "etnaviv_query_hw.h" +#include "etnaviv_query_acc.h" #include "etnaviv_rasterizer.h" #include "etnaviv_resource.h" #include "etnaviv_screen.h" @@ -48,6 +48,7 @@ #include "pipe/p_context.h" #include "pipe/p_state.h" +#include "util/hash_table.h" #include "util/u_blitter.h" #include "util/u_helpers.h" #include "util/u_memory.h" @@ -56,11 +57,74 @@ #include "hw/common.xml.h" +static inline void +etna_emit_nop_with_data(struct etna_cmd_stream *stream, uint32_t value) +{ + etna_cmd_stream_emit(stream, VIV_FE_NOP_HEADER_OP_NOP); + etna_cmd_stream_emit(stream, value); +} + +static void +etna_emit_string_marker(struct pipe_context *pctx, const char *string, int len) +{ + struct etna_context *ctx = etna_context(pctx); + struct etna_cmd_stream *stream = ctx->stream; + const uint32_t *buf = (const void *)string; + + etna_cmd_stream_reserve(stream, len * 2); + + while (len >= 4) { + etna_emit_nop_with_data(stream, *buf); + buf++; + len -= 4; + } + + /* copy remainder bytes without reading past end of input string */ + if (len > 0) { + uint32_t w = 0; + memcpy(&w, buf, len); + etna_emit_nop_with_data(stream, w); + } +} + static void etna_context_destroy(struct pipe_context *pctx) { struct etna_context *ctx = etna_context(pctx); + mtx_lock(&ctx->lock); + if (ctx->used_resources_read) { + + /* + * There should be no resources tracked in the context when it's being + * destroyed. Be sure there are none to avoid memory leaks on buggy + * programs. + */ + set_foreach(ctx->used_resources_read, entry) { + struct etna_resource *rsc = (struct etna_resource *)entry->key; + + _mesa_set_remove_key(rsc->pending_ctx, ctx); + } + _mesa_set_destroy(ctx->used_resources_read, NULL); + + } + if (ctx->used_resources_write) { + + /* + * There should be no resources tracked in the context when it's being + * destroyed. Be sure there are none to avoid memory leaks on buggy + * programs. + */ + set_foreach(ctx->used_resources_write, entry) { + struct etna_resource *rsc = (struct etna_resource *)entry->key; + + _mesa_set_remove_key(rsc->pending_ctx, ctx); + } + _mesa_set_destroy(ctx->used_resources_write, NULL); + + } + mtx_unlock(&ctx->lock); + if (ctx->dummy_rt) etna_bo_del(ctx->dummy_rt); @@ -83,6 +147,8 @@ etna_context_destroy(struct pipe_context *pctx) if (ctx->in_fence_fd != -1) close(ctx->in_fence_fd); + mtx_destroy(&ctx->lock); + FREE(pctx); } @@ -152,6 +218,7 @@ static void etna_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info) { struct etna_context *ctx = etna_context(pctx); + struct etna_screen *screen = ctx->screen; struct pipe_framebuffer_state *pfb = &ctx->framebuffer_s; uint32_t draw_mode; unsigned i; @@ -190,7 +257,7 @@ etna_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info) if (info->index_size) { indexbuf = info->has_user_indices ? NULL : info->index.resource; if (info->has_user_indices && - !util_upload_index_buffer(pctx, info, &indexbuf, &index_offset)) { + !util_upload_index_buffer(pctx, info, &indexbuf, &index_offset, 4)) { BUG("Index buffer upload failed."); return; } @@ -214,9 +281,12 @@ etna_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info) } ctx->dirty |= ETNA_DIRTY_INDEX_BUFFER; - struct etna_shader_key key = {}; + struct etna_shader_key key = { + .front_ccw = ctx->rasterizer->front_ccw, + }; + if (pfb->cbufs[0]) - key.frag_rb_swap = !!translate_rs_format_rb_swap(pfb->cbufs[0]->format); + key.frag_rb_swap = !!translate_pe_format_rb_swap(pfb->cbufs[0]->format); if (!etna_get_vs(ctx, key) || !etna_get_fs(ctx, key)) { BUG("compiled shaders are not okay"); @@ -227,6 +297,8 @@ etna_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info) if (!etna_state_update(ctx)) return; + mtx_lock(&ctx->lock); + /* * Figure out the buffers/features we need: */ @@ -247,11 +319,14 @@ etna_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info) } /* Mark constant buffers as being read */ - resource_read(ctx, ctx->constant_buffer[PIPE_SHADER_VERTEX].buffer); - resource_read(ctx, ctx->constant_buffer[PIPE_SHADER_FRAGMENT].buffer); + foreach_bit(i, ctx->constant_buffer[PIPE_SHADER_VERTEX].enabled_mask) + resource_read(ctx, ctx->constant_buffer[PIPE_SHADER_VERTEX].cb[i].buffer); + + foreach_bit(i, ctx->constant_buffer[PIPE_SHADER_FRAGMENT].enabled_mask) + resource_read(ctx, ctx->constant_buffer[PIPE_SHADER_FRAGMENT].cb[i].buffer); /* Mark VBOs as being read */ - for (i = 0; i < ctx->vertex_buffer.count; i++) { + foreach_bit(i, ctx->vertex_buffer.enabled_mask) { assert(!ctx->vertex_buffer.vb[i].is_user_buffer); resource_read(ctx, ctx->vertex_buffer.vb[i].buffer.resource); } @@ -260,14 +335,19 @@ etna_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info) resource_read(ctx, indexbuf); /* Mark textures as being read */ - for (i = 0; i < PIPE_MAX_SAMPLERS; i++) - if (ctx->sampler_view[i]) - resource_read(ctx, ctx->sampler_view[i]->texture); - - list_for_each_entry(struct etna_hw_query, hq, &ctx->active_hw_queries, node) - resource_written(ctx, hq->prsc); + for (i = 0; i < PIPE_MAX_SAMPLERS; i++) { + if (ctx->sampler_view[i]) { + resource_read(ctx, ctx->sampler_view[i]->texture); + + /* if texture was modified since the last update, + * we need to clear the texture cache and possibly + * resolve/update ts + */ + etna_update_sampler_source(ctx->sampler_view[i], i); + } + } - ctx->stats.prims_emitted += u_reduced_prims_for_vertices(info->mode, info->count); + ctx->stats.prims_generated += u_reduced_prims_for_vertices(info->mode, info->count); ctx->stats.draw_calls++; /* Update state for this draw operation */ @@ -276,9 +356,9 @@ etna_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info) /* First, sync state, then emit DRAW_PRIMITIVES or DRAW_INDEXED_PRIMITIVES */ etna_emit_state(ctx); - if (ctx->specs.halti >= 2) { + if (screen->specs.halti >= 2) { /* On HALTI2+ (GC3000 and higher) only use instanced drawing commands, as the blob does */ - etna_draw_instanced(ctx->stream, info->index_size, draw_mode, 1, + etna_draw_instanced(ctx->stream, info->index_size, draw_mode, info->instance_count, info->count, info->index_size ? info->index_bias : info->start); } else { if (info->index_size) @@ -293,6 +373,7 @@ etna_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info) * draw op has caused the hang. */ etna_stall(ctx->stream, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE); } + mtx_unlock(&ctx->lock); if (DBG_ENABLED(ETNA_DBG_FLUSH_ALL)) pctx->flush(pctx, NULL, 0); @@ -306,35 +387,9 @@ etna_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info) } static void -etna_flush(struct pipe_context *pctx, struct pipe_fence_handle **fence, - enum pipe_flush_flags flags) -{ - struct etna_context *ctx = etna_context(pctx); - struct etna_screen *screen = ctx->screen; - int out_fence_fd = -1; - - mtx_lock(&screen->lock); - - list_for_each_entry(struct etna_hw_query, hq, &ctx->active_hw_queries, node) - etna_hw_query_suspend(hq, ctx); - - etna_cmd_stream_flush2(ctx->stream, ctx->in_fence_fd, - (flags & PIPE_FLUSH_FENCE_FD) ? &out_fence_fd : - NULL); - - list_for_each_entry(struct etna_hw_query, hq, &ctx->active_hw_queries, node) - etna_hw_query_resume(hq, ctx); - - if (fence) - *fence = etna_fence_create(pctx, out_fence_fd); - - mtx_unlock(&screen->lock); -} - -static void -etna_cmd_stream_reset_notify(struct etna_cmd_stream *stream, void *priv) +etna_reset_gpu_state(struct etna_context *ctx) { - struct etna_context *ctx = priv; + struct etna_cmd_stream *stream = ctx->stream; struct etna_screen *screen = ctx->screen; etna_set_state(stream, VIVS_GL_API_MODE, VIVS_GL_API_MODE_OPENGL); @@ -348,57 +403,125 @@ etna_cmd_stream_reset_notify(struct etna_cmd_stream *stream, void *priv) etna_set_state(stream, VIVS_PA_VIEWPORT_UNK00A84, fui(8192.0)); etna_set_state(stream, VIVS_PA_ZFARCLIPPING, 0x00000000); etna_set_state(stream, VIVS_RA_HDEPTH_CONTROL, 0x00007000); - etna_set_state(stream, VIVS_PE_STENCIL_CONFIG_EXT2, 0x00000000); etna_set_state(stream, VIVS_PS_CONTROL_EXT, 0x00000000); /* There is no HALTI0 specific state */ - if (ctx->specs.halti >= 1) { /* Only on HALTI1+ */ + if (screen->specs.halti >= 1) { /* Only on HALTI1+ */ etna_set_state(stream, VIVS_VS_HALTI1_UNK00884, 0x00000808); } - if (ctx->specs.halti >= 2) { /* Only on HALTI2+ */ + if (screen->specs.halti >= 2) { /* Only on HALTI2+ */ etna_set_state(stream, VIVS_RA_UNK00E0C, 0x00000000); } - if (ctx->specs.halti >= 3) { /* Only on HALTI3+ */ + if (screen->specs.halti >= 3) { /* Only on HALTI3+ */ etna_set_state(stream, VIVS_PS_HALTI3_UNK0103C, 0x76543210); } - if (ctx->specs.halti >= 4) { /* Only on HALTI4+ */ + if (screen->specs.halti >= 4) { /* Only on HALTI4+ */ etna_set_state(stream, VIVS_PS_MSAA_CONFIG, 0x6fffffff & 0xf70fffff & 0xfff6ffff & 0xffff6fff & 0xfffff6ff & 0xffffff7f); etna_set_state(stream, VIVS_PE_HALTI4_UNK014C0, 0x00000000); } - if (ctx->specs.halti >= 5) { /* Only on HALTI5+ */ + if (screen->specs.halti >= 5) { /* Only on HALTI5+ */ etna_set_state(stream, VIVS_NTE_DESCRIPTOR_UNK14C40, 0x00000001); etna_set_state(stream, VIVS_FE_HALTI5_UNK007D8, 0x00000002); - etna_set_state(stream, VIVS_FE_HALTI5_ID_CONFIG, 0x00000000); etna_set_state(stream, VIVS_PS_SAMPLER_BASE, 0x00000000); etna_set_state(stream, VIVS_VS_SAMPLER_BASE, 0x00000020); etna_set_state(stream, VIVS_SH_CONFIG, VIVS_SH_CONFIG_RTNE_ROUNDING); } else { /* Only on pre-HALTI5 */ - etna_set_state(stream, VIVS_GL_UNK03834, 0x00000000); etna_set_state(stream, VIVS_GL_UNK03838, 0x00000000); etna_set_state(stream, VIVS_GL_UNK03854, 0x00000000); } - if (!ctx->specs.use_blt) { + if (!screen->specs.use_blt) { /* Enable SINGLE_BUFFER for resolve, if supported */ - etna_set_state(stream, VIVS_RS_SINGLE_BUFFER, COND(ctx->specs.single_buffer, VIVS_RS_SINGLE_BUFFER_ENABLE)); + etna_set_state(stream, VIVS_RS_SINGLE_BUFFER, COND(screen->specs.single_buffer, VIVS_RS_SINGLE_BUFFER_ENABLE)); + } + + if (screen->specs.halti >= 5) { + /* TXDESC cache flush - do this once at the beginning, as texture + * descriptors are only written by the CPU once, then patched by the kernel + * before command stream submission. It does not need flushing if the + * referenced image data changes. + */ + etna_set_state(stream, VIVS_NTE_DESCRIPTOR_FLUSH, 0); + etna_set_state(stream, VIVS_GL_FLUSH_CACHE, + VIVS_GL_FLUSH_CACHE_DESCRIPTOR_UNK12 | + VIVS_GL_FLUSH_CACHE_DESCRIPTOR_UNK13); + + /* Icache invalidate (should do this on shader change?) */ + etna_set_state(stream, VIVS_VS_ICACHE_INVALIDATE, + VIVS_VS_ICACHE_INVALIDATE_UNK0 | VIVS_VS_ICACHE_INVALIDATE_UNK1 | + VIVS_VS_ICACHE_INVALIDATE_UNK2 | VIVS_VS_ICACHE_INVALIDATE_UNK3 | + VIVS_VS_ICACHE_INVALIDATE_UNK4); } ctx->dirty = ~0L; ctx->dirty_sampler_views = ~0L; +} + +static void +etna_flush(struct pipe_context *pctx, struct pipe_fence_handle **fence, + enum pipe_flush_flags flags) +{ + struct etna_context *ctx = etna_context(pctx); + int out_fence_fd = -1; + + mtx_lock(&ctx->lock); + + list_for_each_entry(struct etna_acc_query, aq, &ctx->active_acc_queries, node) + etna_acc_query_suspend(aq, ctx); + + etna_cmd_stream_flush(ctx->stream, ctx->in_fence_fd, + (flags & PIPE_FLUSH_FENCE_FD) ? &out_fence_fd : NULL); + + list_for_each_entry(struct etna_acc_query, aq, &ctx->active_acc_queries, node) + etna_acc_query_resume(aq, ctx); + + if (fence) + *fence = etna_fence_create(pctx, out_fence_fd); /* - * Go through all _resources_ associated with this _screen_, pending - * in this _context_ and mark them as not pending in this _context_ - * anymore, since they were just flushed. - */ - mtx_lock(&screen->lock); - set_foreach(screen->used_resources, entry) { + * Go through all _resources_ pending in this _context_ and mark them as + * not pending in this _context_ anymore, since they were just flushed. + */ + set_foreach(ctx->used_resources_read, entry) { + struct etna_resource *rsc = (struct etna_resource *)entry->key; + struct pipe_resource *referenced = &rsc->base; + + _mesa_set_remove_key(rsc->pending_ctx, ctx); + + /* if resource has no pending ctx's reset its status */ + if (_mesa_set_next_entry(rsc->pending_ctx, NULL) == NULL) + rsc->status &= ~ETNA_PENDING_READ; + + pipe_resource_reference(&referenced, NULL); + } + _mesa_set_clear(ctx->used_resources_read, NULL); + + set_foreach(ctx->used_resources_write, entry) { struct etna_resource *rsc = (struct etna_resource *)entry->key; + struct pipe_resource *referenced = &rsc->base; _mesa_set_remove_key(rsc->pending_ctx, ctx); + + /* if resource has no pending ctx's reset its status */ + if (_mesa_set_next_entry(rsc->pending_ctx, NULL) == NULL) + rsc->status &= ~ETNA_PENDING_WRITE; + + pipe_resource_reference(&referenced, NULL); } - mtx_unlock(&screen->lock); + _mesa_set_clear(ctx->used_resources_write, NULL); + + etna_reset_gpu_state(ctx); + mtx_unlock(&ctx->lock); +} + +static void +etna_context_force_flush(struct etna_cmd_stream *stream, void *priv) +{ + struct pipe_context *pctx = priv; + + pctx->flush(pctx, NULL, 0); + } static void @@ -432,18 +555,30 @@ etna_context_create(struct pipe_screen *pscreen, void *priv, unsigned flags) pctx->const_uploader = pctx->stream_uploader; screen = etna_screen(pscreen); - ctx->stream = etna_cmd_stream_new(screen->pipe, 0x2000, &etna_cmd_stream_reset_notify, ctx); + ctx->stream = etna_cmd_stream_new(screen->pipe, 0x2000, + &etna_context_force_flush, pctx); if (ctx->stream == NULL) goto fail; + ctx->used_resources_read = _mesa_set_create(NULL, _mesa_hash_pointer, + _mesa_key_pointer_equal); + if (!ctx->used_resources_read) + goto fail; + + ctx->used_resources_write = _mesa_set_create(NULL, _mesa_hash_pointer, + _mesa_key_pointer_equal); + if (!ctx->used_resources_write) + goto fail; + + mtx_init(&ctx->lock, mtx_recursive); + /* context ctxate setup */ - ctx->specs = screen->specs; ctx->screen = screen; /* need some sane default in case state tracker doesn't set some state: */ ctx->sample_mask = 0xffff; /* Set sensible defaults for state */ - etna_cmd_stream_reset_notify(ctx->stream, ctx); + etna_reset_gpu_state(ctx); ctx->in_fence_fd = -1; @@ -453,6 +588,7 @@ etna_context_create(struct pipe_screen *pscreen, void *priv, unsigned flags) pctx->set_debug_callback = etna_set_debug_callback; pctx->create_fence_fd = etna_create_fence_fd; pctx->fence_server_sync = etna_fence_server_sync; + pctx->emit_string_marker = etna_emit_string_marker; /* creation of compile states */ pctx->create_blend_state = etna_blend_state_create; @@ -476,9 +612,15 @@ etna_context_create(struct pipe_screen *pscreen, void *priv, unsigned flags) 1 << PIPE_PRIM_LINES | 1 << PIPE_PRIM_LINE_STRIP | 1 << PIPE_PRIM_TRIANGLES | - 1 << PIPE_PRIM_TRIANGLE_STRIP | 1 << PIPE_PRIM_TRIANGLE_FAN; + /* TODO: The bug relates only to indexed draws, but here we signal + * that there is no support for triangle strips at all. This should + * be refined. + */ + if (VIV_FEATURE(ctx->screen, chipMinorFeatures2, BUG_FIXES8)) + ctx->prim_hwsupport |= 1 << PIPE_PRIM_TRIANGLE_STRIP; + if (VIV_FEATURE(ctx->screen, chipMinorFeatures2, LINE_LOOP)) ctx->prim_hwsupport |= 1 << PIPE_PRIM_LINE_LOOP; @@ -487,7 +629,7 @@ etna_context_create(struct pipe_screen *pscreen, void *priv, unsigned flags) goto fail; slab_create_child(&ctx->transfer_pool, &screen->transfer_pool); - list_inithead(&ctx->active_hw_queries); + list_inithead(&ctx->active_acc_queries); /* create dummy RT buffer, used when rendering with no color buffer */ ctx->dummy_rt = etna_bo_new(ctx->screen->dev, 64 * 64 * 4, @@ -499,6 +641,20 @@ etna_context_create(struct pipe_screen *pscreen, void *priv, unsigned flags) ctx->dummy_rt_reloc.offset = 0; ctx->dummy_rt_reloc.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE; + if (screen->specs.halti >= 5) { + /* Create an empty dummy texture descriptor */ + ctx->dummy_desc_bo = etna_bo_new(ctx->screen->dev, 0x100, DRM_ETNA_GEM_CACHE_WC); + if (!ctx->dummy_desc_bo) + goto fail; + uint32_t *buf = etna_bo_map(ctx->dummy_desc_bo); + etna_bo_cpu_prep(ctx->dummy_desc_bo, DRM_ETNA_PREP_WRITE); + memset(buf, 0, 0x100); + etna_bo_cpu_fini(ctx->dummy_desc_bo); + ctx->DUMMY_DESC_ADDR.bo = ctx->dummy_desc_bo; + ctx->DUMMY_DESC_ADDR.offset = 0; + ctx->DUMMY_DESC_ADDR.flags = ETNA_RELOC_READ; + } + return pctx; fail: diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_context.h b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_context.h index 81d4d963e..dd6af3d93 100644 --- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_context.h +++ b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_context.h @@ -73,6 +73,11 @@ struct etna_transfer { void *mapped; }; +struct etna_constbuf_state { + struct pipe_constant_buffer cb[ETNA_MAX_CONST_BUF]; + uint32_t enabled_mask; +}; + struct etna_vertexbuf_state { struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS]; struct compiled_set_vertex_buffer cvb[PIPE_MAX_ATTRIBS]; @@ -92,7 +97,7 @@ enum etna_immediate_contents { ETNA_IMMEDIATE_TEXRECT_SCALE_X, ETNA_IMMEDIATE_TEXRECT_SCALE_Y, ETNA_IMMEDIATE_UBO0_ADDR, - ETNA_IMMEDIATE_UBOMAX_ADDR = ETNA_IMMEDIATE_UBO0_ADDR + 255, + ETNA_IMMEDIATE_UBOMAX_ADDR = ETNA_IMMEDIATE_UBO0_ADDR + ETNA_MAX_CONST_BUF - 1, }; struct etna_shader_uniform_info { @@ -108,8 +113,9 @@ struct etna_context { void (*emit_texture_state)(struct etna_context *pctx); /* Get sampler TS pointer for sampler view */ struct etna_sampler_ts *(*ts_for_sampler_view)(struct pipe_sampler_view *pview); + /* GPU-specific blit implementation */ + bool (*blit)(struct pipe_context *pipe, const struct pipe_blit_info *info); - struct etna_specs specs; struct etna_screen *screen; struct etna_cmd_stream *stream; @@ -134,6 +140,7 @@ struct etna_context { ETNA_DIRTY_TS = (1 << 17), ETNA_DIRTY_TEXTURE_CACHES = (1 << 18), ETNA_DIRTY_DERIVE_TS = (1 << 19), + ETNA_DIRTY_SCISSOR_CLIP = (1 << 20), } dirty; uint32_t prim_hwsupport; @@ -152,19 +159,19 @@ struct etna_context { struct pipe_depth_stencil_alpha_state *zsa; struct compiled_vertex_elements_state *vertex_elements; struct compiled_shader_state shader_state; + struct pipe_scissor_state clipping; /* to simplify the emit process we store pre compiled state objects, * which got 'compiled' during state change. */ struct compiled_blend_color blend_color; struct compiled_stencil_ref stencil_ref; struct compiled_framebuffer_state framebuffer; - struct compiled_scissor_state scissor; struct compiled_viewport_state viewport; unsigned num_fragment_sampler_views; uint32_t active_sampler_views; uint32_t dirty_sampler_views; struct pipe_sampler_view *sampler_view[PIPE_MAX_SAMPLERS]; - struct pipe_constant_buffer constant_buffer[PIPE_SHADER_TYPES]; + struct etna_constbuf_state constant_buffer[PIPE_SHADER_TYPES]; struct etna_vertexbuf_state vertex_buffer; struct etna_index_buffer index_buffer; struct etna_shader_state shader; @@ -173,11 +180,11 @@ struct etna_context { struct pipe_framebuffer_state framebuffer_s; struct pipe_stencil_ref stencil_ref_s; struct pipe_viewport_state viewport_s; - struct pipe_scissor_state scissor_s; + struct pipe_scissor_state scissor; /* stats/counters */ struct { - uint64_t prims_emitted; + uint64_t prims_generated; uint64_t draw_calls; uint64_t rs_operations; } stats; @@ -185,11 +192,21 @@ struct etna_context { struct pipe_debug_callback debug; int in_fence_fd; - /* list of active hardware queries */ - struct list_head active_hw_queries; + /* list of accumulated HW queries */ + struct list_head active_acc_queries; struct etna_bo *dummy_rt; struct etna_reloc dummy_rt_reloc; + + /* Dummy texture descriptor (if needed) */ + struct etna_bo *dummy_desc_bo; + struct etna_reloc DUMMY_DESC_ADDR; + + /* set of resources used by currently-unsubmitted renders */ + struct set *used_resources_read; + struct set *used_resources_write; + + mtx_t lock; }; static inline struct etna_context * diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_debug.h b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_debug.h index 7676e5adc..79e6ebaed 100644 --- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_debug.h +++ b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_debug.h @@ -54,6 +54,7 @@ #define ETNA_DBG_SHADERDB 0x800000 /* dump program compile information */ #define ETNA_DBG_NO_SINGLEBUF 0x1000000 /* disable single buffer feature */ #define ETNA_DBG_NIR 0x2000000 /* use new NIR compiler */ +#define ETNA_DBG_DEQP 0x4000000 /* Hacks to run dEQP GLES3 tests */ extern int etna_mesa_debug; /* set in etna_screen.c from ETNA_DEBUG */ diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_disasm.c b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_disasm.c index 45db5bbbb..56d94e27f 100644 --- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_disasm.c +++ b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_disasm.c @@ -508,6 +508,8 @@ static const struct opc_info { OPC(STORE), OPC(IMULLO0), OPC(IMULHI0), + OPC(IMADLO0), + OPC(IMADHI0), OPC(LEADZERO), OPC(LSHIFT), OPC(RSHIFT), @@ -518,6 +520,7 @@ static const struct opc_info { OPC(NOT), OPC(DP2), OPC(DIV), + OPC(IABS), }; static void diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_emit.c b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_emit.c index 2e373ecc2..cb55b2eb4 100644 --- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_emit.c +++ b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_emit.c @@ -132,6 +132,7 @@ emit_halti5_only_state(struct etna_context *ctx, int vs_output_count) etna_coalesce_start(stream, &coalesce); if (unlikely(dirty & (ETNA_DIRTY_SHADER))) { /* Magic states (load balancing, inter-unit sync, buffers) */ + /*007C4*/ EMIT_STATE(FE_HALTI5_ID_CONFIG, ctx->shader_state.FE_HALTI5_ID_CONFIG); /*00870*/ EMIT_STATE(VS_HALTI5_OUTPUT_COUNT, vs_output_count | ((vs_output_count * 0x10) << 8)); /*008A0*/ EMIT_STATE(VS_HALTI5_UNK008A0, 0x0001000e | ((0x110/vs_output_count) << 20)); for (int x = 0; x < 4; ++x) { @@ -144,9 +145,11 @@ emit_halti5_only_state(struct etna_context *ctx, int vs_output_count) } } if (unlikely(dirty & (ETNA_DIRTY_SHADER))) { - /*00A90*/ EMIT_STATE(PA_VARYING_NUM_COMPONENTS(0), ctx->shader_state.GL_VARYING_NUM_COMPONENTS); + /*00A90*/ EMIT_STATE(PA_VARYING_NUM_COMPONENTS(0), ctx->shader_state.GL_VARYING_NUM_COMPONENTS[0]); + /*00A94*/ EMIT_STATE(PA_VARYING_NUM_COMPONENTS(1), ctx->shader_state.GL_VARYING_NUM_COMPONENTS[1]); /*00AA8*/ EMIT_STATE(PA_VS_OUTPUT_COUNT, vs_output_count); - /*01080*/ EMIT_STATE(PS_VARYING_NUM_COMPONENTS(0), ctx->shader_state.GL_VARYING_NUM_COMPONENTS); + /*01080*/ EMIT_STATE(PS_VARYING_NUM_COMPONENTS(0), ctx->shader_state.GL_VARYING_NUM_COMPONENTS[0]); + /*01084*/ EMIT_STATE(PS_VARYING_NUM_COMPONENTS(1), ctx->shader_state.GL_VARYING_NUM_COMPONENTS[1]); /*03888*/ EMIT_STATE(GL_HALTI5_SH_SPECIALS, ctx->shader_state.GL_HALTI5_SH_SPECIALS); } etna_coalesce_end(stream, &coalesce); @@ -198,10 +201,11 @@ emit_pre_halti5_state(struct etna_context *ctx) /*01018*/ EMIT_STATE(PS_START_PC, ctx->shader_state.PS_START_PC); } if (unlikely(dirty & (ETNA_DIRTY_SHADER))) { - /*03820*/ EMIT_STATE(GL_VARYING_NUM_COMPONENTS, ctx->shader_state.GL_VARYING_NUM_COMPONENTS); + /*03820*/ EMIT_STATE(GL_VARYING_NUM_COMPONENTS, ctx->shader_state.GL_VARYING_NUM_COMPONENTS[0]); for (int x = 0; x < 2; ++x) { /*03828*/ EMIT_STATE(GL_VARYING_COMPONENT_USE(x), ctx->shader_state.GL_VARYING_COMPONENT_USE[x]); } + /*03834*/ EMIT_STATE(GL_VARYING_NUM_COMPONENTS2, ctx->shader_state.GL_VARYING_NUM_COMPONENTS[1]); } etna_coalesce_end(stream, &coalesce); } @@ -214,6 +218,9 @@ void etna_emit_state(struct etna_context *ctx) { struct etna_cmd_stream *stream = ctx->stream; + struct etna_screen *screen = ctx->screen; + unsigned ccw = ctx->rasterizer->front_ccw; + /* Pre-reserve the command buffer space which we are likely to need. * This must cover all the state emitted below, and the following @@ -247,7 +254,7 @@ etna_emit_state(struct etna_context *ctx) * a) the number of vertex elements written matters: so write only active ones * b) the vertex element states must all be written: do not skip entries that stay the same */ if (dirty & (ETNA_DIRTY_VERTEX_ELEMENTS)) { - if (ctx->specs.halti >= 5) { + if (screen->specs.halti >= 5) { /*17800*/ etna_set_state_multi(stream, VIVS_NFE_GENERIC_ATTRIB_CONFIG0(0), ctx->vertex_elements->num_elements, ctx->vertex_elements->NFE_GENERIC_ATTRIB_CONFIG0); @@ -262,7 +269,7 @@ etna_emit_state(struct etna_context *ctx) /*00600*/ etna_set_state_multi(stream, VIVS_FE_VERTEX_ELEMENT_CONFIG(0), ctx->vertex_elements->num_elements, ctx->vertex_elements->FE_VERTEX_ELEMENT_CONFIG); - if (ctx->specs.halti >= 2) { + if (screen->specs.halti >= 2) { /*00780*/ etna_set_state_multi(stream, VIVS_FE_GENERIC_ATTRIB_SCALE(0), ctx->vertex_elements->num_elements, ctx->vertex_elements->NFE_GENERIC_ATTRIB_SCALE); @@ -316,7 +323,7 @@ etna_emit_state(struct etna_context *ctx) /*00674*/ EMIT_STATE(FE_PRIMITIVE_RESTART_INDEX, ctx->index_buffer.FE_PRIMITIVE_RESTART_INDEX); } if (likely(dirty & (ETNA_DIRTY_VERTEX_BUFFERS))) { - if (ctx->specs.halti >= 2) { /* HALTI2+: NFE_VERTEX_STREAMS */ + if (screen->specs.halti >= 2) { /* HALTI2+: NFE_VERTEX_STREAMS */ for (int x = 0; x < ctx->vertex_buffer.count; ++x) { /*14600*/ EMIT_STATE_RELOC(NFE_VERTEX_STREAMS_BASE_ADDR(x), &ctx->vertex_buffer.cvb[x].FE_VERTEX_STREAM_BASE_ADDR); } @@ -325,12 +332,7 @@ etna_emit_state(struct etna_context *ctx) /*14640*/ EMIT_STATE(NFE_VERTEX_STREAMS_CONTROL(x), ctx->vertex_buffer.cvb[x].FE_VERTEX_STREAM_CONTROL); } } - for (int x = 0; x < ctx->vertex_buffer.count; ++x) { - if (ctx->vertex_buffer.cvb[x].FE_VERTEX_STREAM_BASE_ADDR.bo) { - /*14680*/ EMIT_STATE(NFE_VERTEX_STREAMS_VERTEX_DIVISOR(x), ctx->vertex_buffer.cvb[x].FE_VERTEX_STREAM_UNK14680); - } - } - } else if(ctx->specs.stream_count > 1) { /* hw w/ multiple vertex streams */ + } else if(screen->specs.stream_count > 1) { /* hw w/ multiple vertex streams */ for (int x = 0; x < ctx->vertex_buffer.count; ++x) { /*00680*/ EMIT_STATE_RELOC(FE_VERTEX_STREAMS_BASE_ADDR(x), &ctx->vertex_buffer.cvb[x].FE_VERTEX_STREAM_BASE_ADDR); } @@ -344,6 +346,13 @@ etna_emit_state(struct etna_context *ctx) /*00650*/ EMIT_STATE(FE_VERTEX_STREAM_CONTROL, ctx->vertex_buffer.cvb[0].FE_VERTEX_STREAM_CONTROL); } } + /* gallium has instance divisor as part of elements state */ + if ((dirty & (ETNA_DIRTY_VERTEX_ELEMENTS)) && screen->specs.halti >= 2) { + for (int x = 0; x < ctx->vertex_elements->num_buffers; ++x) { + /*14680*/ EMIT_STATE(NFE_VERTEX_STREAMS_VERTEX_DIVISOR(x), ctx->vertex_elements->NFE_VERTEX_STREAMS_VERTEX_DIVISOR[x]); + } + } + if (unlikely(dirty & (ETNA_DIRTY_SHADER | ETNA_DIRTY_RASTERIZER))) { /*00804*/ EMIT_STATE(VS_OUTPUT_COUNT, vs_output_count); @@ -382,33 +391,11 @@ etna_emit_state(struct etna_context *ctx) /*00A38*/ EMIT_STATE(PA_WIDE_LINE_WIDTH0, rasterizer->PA_LINE_WIDTH); /*00A3C*/ EMIT_STATE(PA_WIDE_LINE_WIDTH1, rasterizer->PA_LINE_WIDTH); } - if (unlikely(dirty & (ETNA_DIRTY_SCISSOR | ETNA_DIRTY_FRAMEBUFFER | - ETNA_DIRTY_RASTERIZER | ETNA_DIRTY_VIEWPORT))) { - /* this is a bit of a mess: rasterizer.scissor determines whether to use - * only the framebuffer scissor, or specific scissor state, and the - * viewport clips too so the logic spans four CSOs */ - struct etna_rasterizer_state *rasterizer = etna_rasterizer_state(ctx->rasterizer); - - uint32_t scissor_left = - MAX2(ctx->framebuffer.SE_SCISSOR_LEFT, ctx->viewport.SE_SCISSOR_LEFT); - uint32_t scissor_top = - MAX2(ctx->framebuffer.SE_SCISSOR_TOP, ctx->viewport.SE_SCISSOR_TOP); - uint32_t scissor_right = - MIN2(ctx->framebuffer.SE_SCISSOR_RIGHT, ctx->viewport.SE_SCISSOR_RIGHT); - uint32_t scissor_bottom = - MIN2(ctx->framebuffer.SE_SCISSOR_BOTTOM, ctx->viewport.SE_SCISSOR_BOTTOM); - - if (rasterizer->scissor) { - scissor_left = MAX2(ctx->scissor.SE_SCISSOR_LEFT, scissor_left); - scissor_top = MAX2(ctx->scissor.SE_SCISSOR_TOP, scissor_top); - scissor_right = MIN2(ctx->scissor.SE_SCISSOR_RIGHT, scissor_right); - scissor_bottom = MIN2(ctx->scissor.SE_SCISSOR_BOTTOM, scissor_bottom); - } - - /*00C00*/ EMIT_STATE_FIXP(SE_SCISSOR_LEFT, scissor_left); - /*00C04*/ EMIT_STATE_FIXP(SE_SCISSOR_TOP, scissor_top); - /*00C08*/ EMIT_STATE_FIXP(SE_SCISSOR_RIGHT, scissor_right); - /*00C0C*/ EMIT_STATE_FIXP(SE_SCISSOR_BOTTOM, scissor_bottom); + if (unlikely(dirty & (ETNA_DIRTY_SCISSOR_CLIP))) { + /*00C00*/ EMIT_STATE_FIXP(SE_SCISSOR_LEFT, ctx->clipping.minx << 16); + /*00C04*/ EMIT_STATE_FIXP(SE_SCISSOR_TOP, ctx->clipping.miny << 16); + /*00C08*/ EMIT_STATE_FIXP(SE_SCISSOR_RIGHT, (ctx->clipping.maxx << 16) + ETNA_SE_SCISSOR_MARGIN_RIGHT); + /*00C0C*/ EMIT_STATE_FIXP(SE_SCISSOR_BOTTOM, (ctx->clipping.maxy << 16) + ETNA_SE_SCISSOR_MARGIN_BOTTOM); } if (unlikely(dirty & (ETNA_DIRTY_RASTERIZER))) { struct etna_rasterizer_state *rasterizer = etna_rasterizer_state(ctx->rasterizer); @@ -417,22 +404,9 @@ etna_emit_state(struct etna_context *ctx) /*00C14*/ EMIT_STATE(SE_DEPTH_BIAS, rasterizer->SE_DEPTH_BIAS); /*00C18*/ EMIT_STATE(SE_CONFIG, rasterizer->SE_CONFIG); } - if (unlikely(dirty & (ETNA_DIRTY_SCISSOR | ETNA_DIRTY_FRAMEBUFFER | - ETNA_DIRTY_RASTERIZER | ETNA_DIRTY_VIEWPORT))) { - struct etna_rasterizer_state *rasterizer = etna_rasterizer_state(ctx->rasterizer); - - uint32_t clip_right = - MIN2(ctx->framebuffer.SE_CLIP_RIGHT, ctx->viewport.SE_CLIP_RIGHT); - uint32_t clip_bottom = - MIN2(ctx->framebuffer.SE_CLIP_BOTTOM, ctx->viewport.SE_CLIP_BOTTOM); - - if (rasterizer->scissor) { - clip_right = MIN2(ctx->scissor.SE_CLIP_RIGHT, clip_right); - clip_bottom = MIN2(ctx->scissor.SE_CLIP_BOTTOM, clip_bottom); - } - - /*00C20*/ EMIT_STATE_FIXP(SE_CLIP_RIGHT, clip_right); - /*00C24*/ EMIT_STATE_FIXP(SE_CLIP_BOTTOM, clip_bottom); + if (unlikely(dirty & (ETNA_DIRTY_SCISSOR_CLIP))) { + /*00C20*/ EMIT_STATE_FIXP(SE_CLIP_RIGHT, (ctx->clipping.maxx << 16) + ETNA_SE_CLIP_MARGIN_RIGHT); + /*00C24*/ EMIT_STATE_FIXP(SE_CLIP_BOTTOM, (ctx->clipping.maxy << 16) + ETNA_SE_CLIP_MARGIN_BOTTOM); } if (unlikely(dirty & (ETNA_DIRTY_SHADER))) { /*00E00*/ EMIT_STATE(RA_CONTROL, ctx->shader_state.RA_CONTROL); @@ -447,11 +421,13 @@ etna_emit_state(struct etna_context *ctx) ctx->framebuffer.msaa_mode ? ctx->shader_state.PS_TEMP_REGISTER_CONTROL_MSAA : ctx->shader_state.PS_TEMP_REGISTER_CONTROL); - /*01010*/ EMIT_STATE(PS_CONTROL, ctx->shader_state.PS_CONTROL); + /*01010*/ EMIT_STATE(PS_CONTROL, ctx->framebuffer.PS_CONTROL); + /*01030*/ EMIT_STATE(PS_CONTROL_EXT, ctx->framebuffer.PS_CONTROL_EXT); } - if (unlikely(dirty & (ETNA_DIRTY_ZSA | ETNA_DIRTY_FRAMEBUFFER))) { - uint32_t val = etna_zsa_state(ctx->zsa)->PE_DEPTH_CONFIG; - /*01400*/ EMIT_STATE(PE_DEPTH_CONFIG, val | ctx->framebuffer.PE_DEPTH_CONFIG); + if (unlikely(dirty & (ETNA_DIRTY_ZSA | ETNA_DIRTY_FRAMEBUFFER | ETNA_DIRTY_SHADER))) { + /*01400*/ EMIT_STATE(PE_DEPTH_CONFIG, (etna_zsa_state(ctx->zsa)->PE_DEPTH_CONFIG | + ctx->framebuffer.PE_DEPTH_CONFIG) & + ctx->shader_state.PE_DEPTH_CONFIG); } if (unlikely(dirty & (ETNA_DIRTY_VIEWPORT))) { /*01404*/ EMIT_STATE(PE_DEPTH_NEAR, ctx->viewport.PE_DEPTH_NEAR); @@ -460,19 +436,20 @@ etna_emit_state(struct etna_context *ctx) if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER))) { /*0140C*/ EMIT_STATE(PE_DEPTH_NORMALIZE, ctx->framebuffer.PE_DEPTH_NORMALIZE); - if (ctx->specs.pixel_pipes == 1) { + if (screen->specs.pixel_pipes == 1) { /*01410*/ EMIT_STATE_RELOC(PE_DEPTH_ADDR, &ctx->framebuffer.PE_DEPTH_ADDR); } /*01414*/ EMIT_STATE(PE_DEPTH_STRIDE, ctx->framebuffer.PE_DEPTH_STRIDE); } - if (unlikely(dirty & (ETNA_DIRTY_ZSA))) { - uint32_t val = etna_zsa_state(ctx->zsa)->PE_STENCIL_OP; + + if (unlikely(dirty & (ETNA_DIRTY_ZSA | ETNA_DIRTY_RASTERIZER))) { + uint32_t val = etna_zsa_state(ctx->zsa)->PE_STENCIL_OP[ccw]; /*01418*/ EMIT_STATE(PE_STENCIL_OP, val); } - if (unlikely(dirty & (ETNA_DIRTY_ZSA | ETNA_DIRTY_STENCIL_REF))) { - uint32_t val = etna_zsa_state(ctx->zsa)->PE_STENCIL_CONFIG; - /*0141C*/ EMIT_STATE(PE_STENCIL_CONFIG, val | ctx->stencil_ref.PE_STENCIL_CONFIG); + if (unlikely(dirty & (ETNA_DIRTY_ZSA | ETNA_DIRTY_STENCIL_REF | ETNA_DIRTY_RASTERIZER))) { + uint32_t val = etna_zsa_state(ctx->zsa)->PE_STENCIL_CONFIG[ccw]; + /*0141C*/ EMIT_STATE(PE_STENCIL_CONFIG, val | ctx->stencil_ref.PE_STENCIL_CONFIG[ccw]); } if (unlikely(dirty & (ETNA_DIRTY_ZSA))) { uint32_t val = etna_zsa_state(ctx->zsa)->PE_ALPHA_OP; @@ -496,11 +473,11 @@ etna_emit_state(struct etna_context *ctx) /*0142C*/ EMIT_STATE(PE_COLOR_FORMAT, val); } if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER))) { - if (ctx->specs.pixel_pipes == 1) { + if (screen->specs.pixel_pipes == 1) { /*01430*/ EMIT_STATE_RELOC(PE_COLOR_ADDR, &ctx->framebuffer.PE_COLOR_ADDR); /*01434*/ EMIT_STATE(PE_COLOR_STRIDE, ctx->framebuffer.PE_COLOR_STRIDE); /*01454*/ EMIT_STATE(PE_HDEPTH_CONTROL, ctx->framebuffer.PE_HDEPTH_CONTROL); - } else if (ctx->specs.pixel_pipes == 2) { + } else if (screen->specs.pixel_pipes == 2) { /*01434*/ EMIT_STATE(PE_COLOR_STRIDE, ctx->framebuffer.PE_COLOR_STRIDE); /*01454*/ EMIT_STATE(PE_HDEPTH_CONTROL, ctx->framebuffer.PE_HDEPTH_CONTROL); /*01460*/ EMIT_STATE_RELOC(PE_PIPE_COLOR_ADDR(0), &ctx->framebuffer.PE_PIPE_COLOR_ADDR[0]); @@ -511,8 +488,9 @@ etna_emit_state(struct etna_context *ctx) abort(); } } - if (unlikely(dirty & (ETNA_DIRTY_STENCIL_REF))) { - /*014A0*/ EMIT_STATE(PE_STENCIL_CONFIG_EXT, ctx->stencil_ref.PE_STENCIL_CONFIG_EXT); + if (unlikely(dirty & (ETNA_DIRTY_STENCIL_REF | ETNA_DIRTY_RASTERIZER | ETNA_DIRTY_ZSA))) { + uint32_t val = etna_zsa_state(ctx->zsa)->PE_STENCIL_CONFIG_EXT; + /*014A0*/ EMIT_STATE(PE_STENCIL_CONFIG_EXT, val | ctx->stencil_ref.PE_STENCIL_CONFIG_EXT[ccw]); } if (unlikely(dirty & (ETNA_DIRTY_BLEND | ETNA_DIRTY_FRAMEBUFFER))) { struct etna_blend_state *blend = etna_blend_state(ctx->blend); @@ -524,11 +502,15 @@ etna_emit_state(struct etna_context *ctx) /*014A8*/ EMIT_STATE(PE_DITHER(x), blend->PE_DITHER[x]); } } - if (unlikely(dirty & (ETNA_DIRTY_BLEND_COLOR))) { + if (unlikely(dirty & (ETNA_DIRTY_BLEND_COLOR)) && + VIV_FEATURE(screen, chipMinorFeatures1, HALF_FLOAT)) { /*014B0*/ EMIT_STATE(PE_ALPHA_COLOR_EXT0, ctx->blend_color.PE_ALPHA_COLOR_EXT0); /*014B4*/ EMIT_STATE(PE_ALPHA_COLOR_EXT1, ctx->blend_color.PE_ALPHA_COLOR_EXT1); } - if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER)) && ctx->specs.halti >= 3) + if (unlikely(dirty & (ETNA_DIRTY_ZSA | ETNA_DIRTY_RASTERIZER))) { + /*014B8*/ EMIT_STATE(PE_STENCIL_CONFIG_EXT2, etna_zsa_state(ctx->zsa)->PE_STENCIL_CONFIG_EXT2[ccw]); + } + if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER)) && screen->specs.halti >= 3) /*014BC*/ EMIT_STATE(PE_MEM_CONFIG, ctx->framebuffer.PE_MEM_CONFIG); if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER | ETNA_DIRTY_TS))) { /*01654*/ EMIT_STATE(TS_MEM_CONFIG, ctx->framebuffer.TS_MEM_CONFIG); @@ -538,6 +520,7 @@ etna_emit_state(struct etna_context *ctx) /*01664*/ EMIT_STATE_RELOC(TS_DEPTH_STATUS_BASE, &ctx->framebuffer.TS_DEPTH_STATUS_BASE); /*01668*/ EMIT_STATE_RELOC(TS_DEPTH_SURFACE_BASE, &ctx->framebuffer.TS_DEPTH_SURFACE_BASE); /*0166C*/ EMIT_STATE(TS_DEPTH_CLEAR_VALUE, ctx->framebuffer.TS_DEPTH_CLEAR_VALUE); + /*016BC*/ EMIT_STATE(TS_COLOR_CLEAR_VALUE_EXT, ctx->framebuffer.TS_COLOR_CLEAR_VALUE_EXT); } if (unlikely(dirty & (ETNA_DIRTY_SHADER))) { /*0381C*/ EMIT_STATE(GL_VARYING_TOTAL_COMPONENTS, ctx->shader_state.GL_VARYING_TOTAL_COMPONENTS); @@ -546,7 +529,7 @@ etna_emit_state(struct etna_context *ctx) /* end only EMIT_STATE */ /* Emit strongly architecture-specific state */ - if (ctx->specs.halti >= 5) + if (screen->specs.halti >= 5) emit_halti5_only_state(ctx, vs_output_count); else emit_pre_halti5_state(ctx); @@ -560,7 +543,7 @@ etna_emit_state(struct etna_context *ctx) * I summise that this is because the "new" locations at 0xc000 are not * properly protected against updates as other states seem to be. Hence, * we detect the "new" vertex shader instruction offset to apply this. */ - if (ctx->dirty & (ETNA_DIRTY_SHADER | ETNA_DIRTY_CONSTBUF) && ctx->specs.vs_offset > 0x4000) + if (ctx->dirty & (ETNA_DIRTY_SHADER | ETNA_DIRTY_CONSTBUF) && screen->specs.vs_offset > 0x4000) etna_stall(ctx->stream, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE); /* We need to update the uniform cache only if one of the following bits are @@ -577,7 +560,7 @@ etna_emit_state(struct etna_context *ctx) ETNA_DIRTY_SHADER | ETNA_DIRTY_CONSTBUF; /**** Large dynamically-sized state ****/ - bool do_uniform_flush = ctx->specs.halti < 5; + bool do_uniform_flush = screen->specs.halti < 5; if (dirty & (ETNA_DIRTY_SHADER)) { /* Special case: a new shader was loaded; simply re-load all uniforms and * shader code at once */ @@ -589,7 +572,7 @@ etna_emit_state(struct etna_context *ctx) state can legitimately be programmed multiple times. */ - if (ctx->specs.halti >= 5) { /* ICACHE (HALTI5) */ + if (screen->specs.halti >= 5) { /* ICACHE (HALTI5) */ assert(ctx->shader_state.VS_INST_ADDR.bo && ctx->shader_state.PS_INST_ADDR.bo); /* Set icache (VS) */ etna_set_state(stream, VIVS_VS_NEWRANGE_LOW, 0); @@ -611,7 +594,7 @@ etna_emit_state(struct etna_context *ctx) } else if (ctx->shader_state.VS_INST_ADDR.bo || ctx->shader_state.PS_INST_ADDR.bo) { /* ICACHE (pre-HALTI5) */ - assert(ctx->specs.has_icache && ctx->specs.has_shader_range_registers); + assert(screen->specs.has_icache && screen->specs.has_shader_range_registers); /* Set icache (VS) */ etna_set_state(stream, VIVS_VS_RANGE, (ctx->shader_state.vs_inst_mem_size / 4 - 1) << 16); etna_set_state(stream, VIVS_VS_ICACHE_CONTROL, @@ -630,40 +613,40 @@ etna_emit_state(struct etna_context *ctx) } else { /* Upload shader directly, first flushing and disabling icache if * supported on this hw */ - if (ctx->specs.has_icache) { + if (screen->specs.has_icache) { etna_set_state(stream, VIVS_VS_ICACHE_CONTROL, VIVS_VS_ICACHE_CONTROL_FLUSH_PS | VIVS_VS_ICACHE_CONTROL_FLUSH_VS); } - if (ctx->specs.has_shader_range_registers) { + if (screen->specs.has_shader_range_registers) { etna_set_state(stream, VIVS_VS_RANGE, (ctx->shader_state.vs_inst_mem_size / 4 - 1) << 16); etna_set_state(stream, VIVS_PS_RANGE, ((ctx->shader_state.ps_inst_mem_size / 4 - 1 + 0x100) << 16) | 0x100); } - etna_set_state_multi(stream, ctx->specs.vs_offset, + etna_set_state_multi(stream, screen->specs.vs_offset, ctx->shader_state.vs_inst_mem_size, ctx->shader_state.VS_INST_MEM); - etna_set_state_multi(stream, ctx->specs.ps_offset, + etna_set_state_multi(stream, screen->specs.ps_offset, ctx->shader_state.ps_inst_mem_size, ctx->shader_state.PS_INST_MEM); } - if (ctx->specs.has_unified_uniforms) { + if (screen->specs.has_unified_uniforms) { etna_set_state(stream, VIVS_VS_UNIFORM_BASE, 0); - etna_set_state(stream, VIVS_PS_UNIFORM_BASE, ctx->specs.max_vs_uniforms); + etna_set_state(stream, VIVS_PS_UNIFORM_BASE, screen->specs.max_vs_uniforms); } if (do_uniform_flush) etna_set_state(stream, VIVS_VS_UNIFORM_CACHE, VIVS_VS_UNIFORM_CACHE_FLUSH); - etna_uniforms_write(ctx, ctx->shader.vs, &ctx->constant_buffer[PIPE_SHADER_VERTEX]); + etna_uniforms_write(ctx, ctx->shader.vs, ctx->constant_buffer[PIPE_SHADER_VERTEX].cb); if (do_uniform_flush) etna_set_state(stream, VIVS_VS_UNIFORM_CACHE, VIVS_VS_UNIFORM_CACHE_FLUSH | VIVS_VS_UNIFORM_CACHE_PS); - etna_uniforms_write(ctx, ctx->shader.fs, &ctx->constant_buffer[PIPE_SHADER_FRAGMENT]); + etna_uniforms_write(ctx, ctx->shader.fs, ctx->constant_buffer[PIPE_SHADER_FRAGMENT].cb); - if (ctx->specs.halti >= 5) { + if (screen->specs.halti >= 5) { /* HALTI5 needs to be prompted to pre-fetch shaders */ etna_set_state(stream, VIVS_VS_ICACHE_PREFETCH, 0x00000000); etna_set_state(stream, VIVS_PS_ICACHE_PREFETCH, 0x00000000); @@ -675,14 +658,14 @@ etna_emit_state(struct etna_context *ctx) etna_set_state(stream, VIVS_VS_UNIFORM_CACHE, VIVS_VS_UNIFORM_CACHE_FLUSH); if (dirty & (uniform_dirty_bits | ctx->shader.vs->uniforms_dirty_bits)) - etna_uniforms_write(ctx, ctx->shader.vs, &ctx->constant_buffer[PIPE_SHADER_VERTEX]); + etna_uniforms_write(ctx, ctx->shader.vs, ctx->constant_buffer[PIPE_SHADER_VERTEX].cb); /* ideally this cache would only be flushed if there are PS uniform changes */ if (do_uniform_flush) etna_set_state(stream, VIVS_VS_UNIFORM_CACHE, VIVS_VS_UNIFORM_CACHE_FLUSH | VIVS_VS_UNIFORM_CACHE_PS); if (dirty & (uniform_dirty_bits | ctx->shader.fs->uniforms_dirty_bits)) - etna_uniforms_write(ctx, ctx->shader.fs, &ctx->constant_buffer[PIPE_SHADER_FRAGMENT]); + etna_uniforms_write(ctx, ctx->shader.fs, ctx->constant_buffer[PIPE_SHADER_FRAGMENT].cb); } /**** End of state update ****/ #undef EMIT_STATE diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_emit.h b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_emit.h index b4670eeb8..6018af91d 100644 --- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_emit.h +++ b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_emit.h @@ -32,7 +32,6 @@ #include "hw/cmdstream.xml.h" struct etna_context; -struct compiled_rs_state; struct etna_coalesce { uint32_t start; diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_fence.c b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_fence.c index c0684bccf..b2400b6ac 100644 --- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_fence.c +++ b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_fence.c @@ -88,7 +88,8 @@ etna_fence_server_sync(struct pipe_context *pctx, { struct etna_context *ctx = etna_context(pctx); - sync_accumulate("etnaviv", &ctx->in_fence_fd, pfence->fence_fd); + if (pfence->fence_fd != -1) + sync_accumulate("etnaviv", &ctx->in_fence_fd, pfence->fence_fd); } static int diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_format.c b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_format.c index de3121e56..97df90e06 100644 --- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_format.c +++ b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_format.c @@ -39,47 +39,37 @@ struct etna_format { unsigned vtx; unsigned tex; - unsigned rs; + unsigned pe; bool present; - const unsigned char tex_swiz[4]; }; -#define RS_FORMAT_NONE ~0 +#define PE_FORMAT_NONE ~0 -#define RS_FORMAT_MASK 0xf -#define RS_FORMAT(x) ((x) & RS_FORMAT_MASK) -#define RS_FORMAT_RB_SWAP 0x10 +#define PE_FORMAT_MASK 0x7f +#define PE_FORMAT(x) ((x) & PE_FORMAT_MASK) +#define PE_FORMAT_RB_SWAP 0x80 -#define RS_FORMAT_X8B8G8R8 (RS_FORMAT_X8R8G8B8 | RS_FORMAT_RB_SWAP) -#define RS_FORMAT_A8B8G8R8 (RS_FORMAT_A8R8G8B8 | RS_FORMAT_RB_SWAP) +#define PE_FORMAT_X8B8G8R8 (PE_FORMAT_X8R8G8B8 | PE_FORMAT_RB_SWAP) +#define PE_FORMAT_A8B8G8R8 (PE_FORMAT_A8R8G8B8 | PE_FORMAT_RB_SWAP) #define TS_SAMPLER_FORMAT_NONE ETNA_NO_MATCH -#define SWIZ(x,y,z,w) { \ - PIPE_SWIZZLE_##x, \ - PIPE_SWIZZLE_##y, \ - PIPE_SWIZZLE_##z, \ - PIPE_SWIZZLE_##w \ -} - /* vertex + texture */ -#define VT(pipe, vtxfmt, texfmt, texswiz, rsfmt) \ +#define VT(pipe, vtxfmt, texfmt, rsfmt) \ [PIPE_FORMAT_##pipe] = { \ .vtx = FE_DATA_TYPE_##vtxfmt, \ .tex = TEXTURE_FORMAT_##texfmt, \ - .rs = RS_FORMAT_##rsfmt, \ + .pe = PE_FORMAT_##rsfmt, \ .present = 1, \ - .tex_swiz = texswiz, \ } /* texture-only */ -#define _T(pipe, fmt, swiz, rsfmt) \ +#define _T(pipe, fmt, rsfmt) \ [PIPE_FORMAT_##pipe] = { \ .vtx = ETNA_NO_MATCH, \ .tex = TEXTURE_FORMAT_##fmt, \ - .rs = RS_FORMAT_##rsfmt, \ + .pe = PE_FORMAT_##rsfmt, \ .present = 1, \ - .tex_swiz = swiz, \ } /* vertex-only */ @@ -87,103 +77,107 @@ struct etna_format { [PIPE_FORMAT_##pipe] = { \ .vtx = FE_DATA_TYPE_##fmt, \ .tex = ETNA_NO_MATCH, \ - .rs = RS_FORMAT_##rsfmt, \ + .pe = PE_FORMAT_##rsfmt, \ .present = 1, \ } static struct etna_format formats[PIPE_FORMAT_COUNT] = { /* 8-bit */ - VT(R8_UNORM, UNSIGNED_BYTE, L8, SWIZ(X, 0, 0, 1), NONE), - V_(R8_SNORM, BYTE, NONE), - V_(R8_UINT, UNSIGNED_BYTE, NONE), - V_(R8_SINT, BYTE, NONE), + VT(R8_UNORM, UNSIGNED_BYTE, L8, R8), + VT(R8_SNORM, BYTE, EXT_R8_SNORM | EXT_FORMAT, NONE), + VT(R8_UINT, BYTE_I, EXT_R8I | EXT_FORMAT, R8I), + VT(R8_SINT, BYTE_I, EXT_R8I | EXT_FORMAT, R8I), V_(R8_USCALED, UNSIGNED_BYTE, NONE), V_(R8_SSCALED, BYTE, NONE), - _T(A8_UNORM, A8, SWIZ(X, Y, Z, W), NONE), - _T(L8_UNORM, L8, SWIZ(X, Y, Z, W), NONE), - _T(I8_UNORM, I8, SWIZ(X, Y, Z, W), NONE), + _T(A8_UNORM, A8, NONE), + _T(L8_UNORM, L8, NONE), + _T(I8_UNORM, I8, NONE), /* 16-bit */ V_(R16_UNORM, UNSIGNED_SHORT, NONE), V_(R16_SNORM, SHORT, NONE), - V_(R16_UINT, UNSIGNED_SHORT, NONE), - V_(R16_SINT, SHORT, NONE), + VT(R16_UINT, SHORT_I, EXT_R16I | EXT_FORMAT, R16I), + VT(R16_SINT, SHORT_I, EXT_R16I | EXT_FORMAT, R16I), V_(R16_USCALED, UNSIGNED_SHORT, NONE), V_(R16_SSCALED, SHORT, NONE), - V_(R16_FLOAT, HALF_FLOAT, NONE), + VT(R16_FLOAT, HALF_FLOAT, EXT_R16F | EXT_FORMAT, R16F), - _T(B4G4R4A4_UNORM, A4R4G4B4, SWIZ(X, Y, Z, W), A4R4G4B4), - _T(B4G4R4X4_UNORM, X4R4G4B4, SWIZ(X, Y, Z, W), X4R4G4B4), + _T(B4G4R4A4_UNORM, A4R4G4B4, A4R4G4B4), + _T(B4G4R4X4_UNORM, X4R4G4B4, X4R4G4B4), - _T(L8A8_UNORM, A8L8, SWIZ(X, Y, Z, W), NONE), + _T(L8A8_UNORM, A8L8, NONE), - _T(Z16_UNORM, D16, SWIZ(X, Y, Z, W), A4R4G4B4), - _T(B5G6R5_UNORM, R5G6B5, SWIZ(X, Y, Z, W), R5G6B5), - _T(B5G5R5A1_UNORM, A1R5G5B5, SWIZ(X, Y, Z, W), A1R5G5B5), - _T(B5G5R5X1_UNORM, X1R5G5B5, SWIZ(X, Y, Z, W), X1R5G5B5), + _T(Z16_UNORM, D16, NONE), + _T(B5G6R5_UNORM, R5G6B5, R5G6B5), + _T(B5G5R5A1_UNORM, A1R5G5B5, A1R5G5B5), + _T(B5G5R5X1_UNORM, X1R5G5B5, X1R5G5B5), - VT(R8G8_UNORM, UNSIGNED_BYTE, EXT_G8R8 | EXT_FORMAT, SWIZ(X, Y, 0, 1), NONE), - V_(R8G8_SNORM, BYTE, NONE), - V_(R8G8_UINT, UNSIGNED_BYTE, NONE), - V_(R8G8_SINT, BYTE, NONE), + VT(R8G8_UNORM, UNSIGNED_BYTE, EXT_G8R8 | EXT_FORMAT, G8R8), + VT(R8G8_SNORM, BYTE, EXT_G8R8_SNORM | EXT_FORMAT, NONE), + VT(R8G8_UINT, BYTE_I, EXT_G8R8I | EXT_FORMAT, G8R8I), + VT(R8G8_SINT, BYTE_I, EXT_G8R8I | EXT_FORMAT, G8R8I), V_(R8G8_USCALED, UNSIGNED_BYTE, NONE), V_(R8G8_SSCALED, BYTE, NONE), /* 24-bit */ V_(R8G8B8_UNORM, UNSIGNED_BYTE, NONE), V_(R8G8B8_SNORM, BYTE, NONE), - V_(R8G8B8_UINT, UNSIGNED_BYTE, NONE), - V_(R8G8B8_SINT, BYTE, NONE), + V_(R8G8B8_UINT, BYTE_I, NONE), + V_(R8G8B8_SINT, BYTE_I, NONE), V_(R8G8B8_USCALED, UNSIGNED_BYTE, NONE), V_(R8G8B8_SSCALED, BYTE, NONE), /* 32-bit */ V_(R32_UNORM, UNSIGNED_INT, NONE), V_(R32_SNORM, INT, NONE), - V_(R32_SINT, INT, NONE), - V_(R32_UINT, UNSIGNED_INT, NONE), + VT(R32_SINT, FLOAT, EXT_R32F | EXT_FORMAT, R32F), + VT(R32_UINT, FLOAT, EXT_R32F | EXT_FORMAT, R32F), V_(R32_USCALED, UNSIGNED_INT, NONE), V_(R32_SSCALED, INT, NONE), - V_(R32_FLOAT, FLOAT, NONE), + VT(R32_FLOAT, FLOAT, EXT_R32F | EXT_FORMAT, R32F), V_(R32_FIXED, FIXED, NONE), V_(R16G16_UNORM, UNSIGNED_SHORT, NONE), V_(R16G16_SNORM, SHORT, NONE), - V_(R16G16_UINT, UNSIGNED_SHORT, NONE), - V_(R16G16_SINT, SHORT, NONE), + VT(R16G16_UINT, SHORT_I, EXT_G16R16I | EXT_FORMAT, G16R16I), + VT(R16G16_SINT, SHORT_I, EXT_G16R16I | EXT_FORMAT, G16R16I), V_(R16G16_USCALED, UNSIGNED_SHORT, NONE), V_(R16G16_SSCALED, SHORT, NONE), - V_(R16G16_FLOAT, HALF_FLOAT, NONE), + VT(R16G16_FLOAT, HALF_FLOAT, EXT_G16R16F | EXT_FORMAT, G16R16F), V_(A8B8G8R8_UNORM, UNSIGNED_BYTE, NONE), - VT(R8G8B8A8_UNORM, UNSIGNED_BYTE, A8B8G8R8, SWIZ(X, Y, Z, W), A8B8G8R8), - V_(R8G8B8A8_SNORM, BYTE, A8B8G8R8), - _T(R8G8B8X8_UNORM, X8B8G8R8, SWIZ(X, Y, Z, W), X8B8G8R8), - V_(R8G8B8A8_UINT, UNSIGNED_BYTE, A8B8G8R8), - V_(R8G8B8A8_SINT, BYTE, A8B8G8R8), + VT(R8G8B8A8_UNORM, UNSIGNED_BYTE, A8B8G8R8, A8B8G8R8), + VT(R8G8B8A8_SNORM, BYTE, EXT_A8B8G8R8_SNORM | EXT_FORMAT, NONE), + _T(R8G8B8X8_UNORM, X8B8G8R8, X8B8G8R8), + _T(R8G8B8X8_SNORM, EXT_X8B8G8R8_SNORM | EXT_FORMAT, NONE), + VT(R8G8B8A8_UINT, BYTE_I, EXT_A8B8G8R8I | EXT_FORMAT, A8B8G8R8I), + VT(R8G8B8A8_SINT, BYTE_I, EXT_A8B8G8R8I | EXT_FORMAT, A8B8G8R8I), V_(R8G8B8A8_USCALED, UNSIGNED_BYTE, A8B8G8R8), V_(R8G8B8A8_SSCALED, BYTE, A8B8G8R8), - _T(B8G8R8A8_UNORM, A8R8G8B8, SWIZ(X, Y, Z, W), A8R8G8B8), - _T(B8G8R8X8_UNORM, X8R8G8B8, SWIZ(X, Y, Z, W), X8R8G8B8), - _T(B8G8R8A8_SRGB, A8R8G8B8, SWIZ(X, Y, Z, W), A8R8G8B8), - _T(B8G8R8X8_SRGB, X8R8G8B8, SWIZ(X, Y, Z, W), X8R8G8B8), + _T(B8G8R8A8_UNORM, A8R8G8B8, A8R8G8B8), + _T(B8G8R8X8_UNORM, X8R8G8B8, X8R8G8B8), - V_(R10G10B10A2_UNORM, UNSIGNED_INT_10_10_10_2, NONE), - V_(R10G10B10A2_SNORM, INT_10_10_10_2, NONE), - V_(R10G10B10A2_USCALED, UNSIGNED_INT_10_10_10_2, NONE), - V_(R10G10B10A2_SSCALED, INT_10_10_10_2, NONE), + VT(R10G10B10A2_UNORM, UNSIGNED_INT_2_10_10_10_REV, EXT_A2B10G10R10 | EXT_FORMAT, A2B10G10R10), + _T(R10G10B10X2_UNORM, EXT_A2B10G10R10 | EXT_FORMAT, A2B10G10R10), + V_(R10G10B10A2_SNORM, INT_2_10_10_10_REV, NONE), + _T(R10G10B10A2_UINT, EXT_A2B10G10R10UI | EXT_FORMAT, A2B10G10R10UI), + V_(R10G10B10A2_USCALED, UNSIGNED_INT_2_10_10_10_REV, NONE), + V_(R10G10B10A2_SSCALED, INT_2_10_10_10_REV, NONE), - _T(X8Z24_UNORM, D24X8, SWIZ(X, Y, Z, W), A8R8G8B8), - _T(S8_UINT_Z24_UNORM, D24X8, SWIZ(X, Y, Z, W), A8R8G8B8), + _T(X8Z24_UNORM, D24X8, NONE), + _T(S8_UINT_Z24_UNORM, D24X8, NONE), + + _T(R9G9B9E5_FLOAT, E5B9G9R9, NONE), + _T(R11G11B10_FLOAT, EXT_B10G11R11F | EXT_FORMAT, B10G11R11F), /* 48-bit */ V_(R16G16B16_UNORM, UNSIGNED_SHORT, NONE), V_(R16G16B16_SNORM, SHORT, NONE), - V_(R16G16B16_UINT, UNSIGNED_SHORT, NONE), - V_(R16G16B16_SINT, SHORT, NONE), + V_(R16G16B16_UINT, SHORT_I, NONE), + V_(R16G16B16_SINT, SHORT_I, NONE), V_(R16G16B16_USCALED, UNSIGNED_SHORT, NONE), V_(R16G16B16_SSCALED, SHORT, NONE), V_(R16G16B16_FLOAT, HALF_FLOAT, NONE), @@ -191,26 +185,26 @@ static struct etna_format formats[PIPE_FORMAT_COUNT] = { /* 64-bit */ V_(R16G16B16A16_UNORM, UNSIGNED_SHORT, NONE), V_(R16G16B16A16_SNORM, SHORT, NONE), - V_(R16G16B16A16_UINT, UNSIGNED_SHORT, NONE), - V_(R16G16B16A16_SINT, SHORT, NONE), + VT(R16G16B16A16_UINT, SHORT_I, EXT_A16B16G16R16I | EXT_FORMAT, A16B16G16R16I), + VT(R16G16B16A16_SINT, SHORT_I, EXT_A16B16G16R16I | EXT_FORMAT, A16B16G16R16I), V_(R16G16B16A16_USCALED, UNSIGNED_SHORT, NONE), V_(R16G16B16A16_SSCALED, SHORT, NONE), - V_(R16G16B16A16_FLOAT, HALF_FLOAT, NONE), + VT(R16G16B16A16_FLOAT, HALF_FLOAT, EXT_A16B16G16R16F | EXT_FORMAT, A16B16G16R16F), V_(R32G32_UNORM, UNSIGNED_INT, NONE), V_(R32G32_SNORM, INT, NONE), - V_(R32G32_UINT, UNSIGNED_INT, NONE), - V_(R32G32_SINT, INT, NONE), + VT(R32G32_UINT, FLOAT, EXT_G32R32F | EXT_FORMAT, G32R32F), + VT(R32G32_SINT, FLOAT, EXT_G32R32F | EXT_FORMAT, G32R32F), V_(R32G32_USCALED, UNSIGNED_INT, NONE), V_(R32G32_SSCALED, INT, NONE), - V_(R32G32_FLOAT, FLOAT, NONE), + VT(R32G32_FLOAT, FLOAT, EXT_G32R32F | EXT_FORMAT, G32R32F), V_(R32G32_FIXED, FIXED, NONE), /* 96-bit */ V_(R32G32B32_UNORM, UNSIGNED_INT, NONE), V_(R32G32B32_SNORM, INT, NONE), - V_(R32G32B32_UINT, UNSIGNED_INT, NONE), - V_(R32G32B32_SINT, INT, NONE), + V_(R32G32B32_UINT, FLOAT, NONE), + V_(R32G32B32_SINT, FLOAT, NONE), V_(R32G32B32_USCALED, UNSIGNED_INT, NONE), V_(R32G32B32_SSCALED, INT, NONE), V_(R32G32B32_FLOAT, FLOAT, NONE), @@ -219,73 +213,54 @@ static struct etna_format formats[PIPE_FORMAT_COUNT] = { /* 128-bit */ V_(R32G32B32A32_UNORM, UNSIGNED_INT, NONE), V_(R32G32B32A32_SNORM, INT, NONE), - V_(R32G32B32A32_UINT, UNSIGNED_INT, NONE), - V_(R32G32B32A32_SINT, INT, NONE), + V_(R32G32B32A32_UINT, FLOAT, NONE), + V_(R32G32B32A32_SINT, FLOAT, NONE), V_(R32G32B32A32_USCALED, UNSIGNED_INT, NONE), V_(R32G32B32A32_SSCALED, INT, NONE), V_(R32G32B32A32_FLOAT, FLOAT, NONE), V_(R32G32B32A32_FIXED, FIXED, NONE), /* compressed */ - _T(ETC1_RGB8, ETC1, SWIZ(X, Y, Z, W), NONE), - - _T(DXT1_RGB, DXT1, SWIZ(X, Y, Z, W), NONE), - _T(DXT1_SRGBA,DXT1, SWIZ(X, Y, Z, W), NONE), - _T(DXT1_RGBA, DXT1, SWIZ(X, Y, Z, W), NONE), - _T(DXT3_SRGBA,DXT2_DXT3, SWIZ(X, Y, Z, W), NONE), - _T(DXT3_RGBA, DXT2_DXT3, SWIZ(X, Y, Z, W), NONE), - _T(DXT5_SRGBA,DXT4_DXT5, SWIZ(X, Y, Z, W), NONE), - _T(DXT5_RGBA, DXT4_DXT5, SWIZ(X, Y, Z, W), NONE), - - _T(ETC2_RGB8, EXT_NONE | EXT_FORMAT, SWIZ(X, Y, Z, W), NONE), /* Extd. format NONE doubles as ETC2_RGB8 */ - _T(ETC2_SRGB8, EXT_NONE | EXT_FORMAT, SWIZ(X, Y, Z, W), NONE), - _T(ETC2_RGB8A1, EXT_RGB8_PUNCHTHROUGH_ALPHA1_ETC2 | EXT_FORMAT, SWIZ(X, Y, Z, W), NONE), - _T(ETC2_SRGB8A1, EXT_RGB8_PUNCHTHROUGH_ALPHA1_ETC2 | EXT_FORMAT, SWIZ(X, Y, Z, W), NONE), - _T(ETC2_RGBA8, EXT_RGBA8_ETC2_EAC | EXT_FORMAT, SWIZ(X, Y, Z, W), NONE), - _T(ETC2_SRGBA8, EXT_RGBA8_ETC2_EAC | EXT_FORMAT, SWIZ(X, Y, Z, W), NONE), - _T(ETC2_R11_UNORM, EXT_R11_EAC | EXT_FORMAT, SWIZ(X, Y, Z, W), NONE), - _T(ETC2_R11_SNORM, EXT_SIGNED_R11_EAC | EXT_FORMAT, SWIZ(X, Y, Z, W), NONE), - _T(ETC2_RG11_UNORM, EXT_RG11_EAC | EXT_FORMAT, SWIZ(X, Y, Z, W), NONE), - _T(ETC2_RG11_SNORM, EXT_SIGNED_RG11_EAC | EXT_FORMAT, SWIZ(X, Y, Z, W), NONE), - - _T(ASTC_4x4, ASTC_RGBA_4x4 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE), - _T(ASTC_5x4, ASTC_RGBA_5x4 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE), - _T(ASTC_5x5, ASTC_RGBA_5x5 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE), - _T(ASTC_6x5, ASTC_RGBA_6x5 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE), - _T(ASTC_6x6, ASTC_RGBA_6x6 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE), - _T(ASTC_8x5, ASTC_RGBA_8x5 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE), - _T(ASTC_8x6, ASTC_RGBA_8x6 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE), - _T(ASTC_8x8, ASTC_RGBA_8x8 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE), - _T(ASTC_10x5, ASTC_RGBA_10x5 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE), - _T(ASTC_10x6, ASTC_RGBA_10x6 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE), - _T(ASTC_10x8, ASTC_RGBA_10x8 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE), - _T(ASTC_10x10, ASTC_RGBA_10x10 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE), - _T(ASTC_12x10, ASTC_RGBA_12x10 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE), - _T(ASTC_12x12, ASTC_RGBA_12x12 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE), - - _T(ASTC_4x4_SRGB, ASTC_RGBA_4x4 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE), - _T(ASTC_5x4_SRGB, ASTC_RGBA_5x4 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE), - _T(ASTC_5x5_SRGB, ASTC_RGBA_5x5 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE), - _T(ASTC_6x5_SRGB, ASTC_RGBA_6x5 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE), - _T(ASTC_6x6_SRGB, ASTC_RGBA_6x6 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE), - _T(ASTC_8x5_SRGB, ASTC_RGBA_8x5 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE), - _T(ASTC_8x6_SRGB, ASTC_RGBA_8x6 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE), - _T(ASTC_8x8_SRGB, ASTC_RGBA_8x8 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE), - _T(ASTC_10x5_SRGB, ASTC_RGBA_10x5 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE), - _T(ASTC_10x6_SRGB, ASTC_RGBA_10x6 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE), - _T(ASTC_10x8_SRGB, ASTC_RGBA_10x8 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE), - _T(ASTC_10x10_SRGB, ASTC_RGBA_10x10 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE), - _T(ASTC_12x10_SRGB, ASTC_RGBA_12x10 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE), - _T(ASTC_12x12_SRGB, ASTC_RGBA_12x12 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE), + _T(ETC1_RGB8, ETC1, NONE), + + _T(DXT1_RGB, DXT1, NONE), + _T(DXT1_RGBA, DXT1, NONE), + _T(DXT3_RGBA, DXT2_DXT3, NONE), + _T(DXT5_RGBA, DXT4_DXT5, NONE), + + _T(ETC2_RGB8, EXT_NONE | EXT_FORMAT, NONE), /* Extd. format NONE doubles as ETC2_RGB8 */ + _T(ETC2_RGB8A1, EXT_RGB8_PUNCHTHROUGH_ALPHA1_ETC2 | EXT_FORMAT, NONE), + _T(ETC2_RGBA8, EXT_RGBA8_ETC2_EAC | EXT_FORMAT, NONE), + _T(ETC2_R11_UNORM, EXT_R11_EAC | EXT_FORMAT, NONE), + _T(ETC2_R11_SNORM, EXT_SIGNED_R11_EAC | EXT_FORMAT, NONE), + _T(ETC2_RG11_UNORM, EXT_RG11_EAC | EXT_FORMAT, NONE), + _T(ETC2_RG11_SNORM, EXT_SIGNED_RG11_EAC | EXT_FORMAT, NONE), + + _T(ASTC_4x4, ASTC_RGBA_4x4 | ASTC_FORMAT, NONE), + _T(ASTC_5x4, ASTC_RGBA_5x4 | ASTC_FORMAT, NONE), + _T(ASTC_5x5, ASTC_RGBA_5x5 | ASTC_FORMAT, NONE), + _T(ASTC_6x5, ASTC_RGBA_6x5 | ASTC_FORMAT, NONE), + _T(ASTC_6x6, ASTC_RGBA_6x6 | ASTC_FORMAT, NONE), + _T(ASTC_8x5, ASTC_RGBA_8x5 | ASTC_FORMAT, NONE), + _T(ASTC_8x6, ASTC_RGBA_8x6 | ASTC_FORMAT, NONE), + _T(ASTC_8x8, ASTC_RGBA_8x8 | ASTC_FORMAT, NONE), + _T(ASTC_10x5, ASTC_RGBA_10x5 | ASTC_FORMAT, NONE), + _T(ASTC_10x6, ASTC_RGBA_10x6 | ASTC_FORMAT, NONE), + _T(ASTC_10x8, ASTC_RGBA_10x8 | ASTC_FORMAT, NONE), + _T(ASTC_10x10, ASTC_RGBA_10x10 | ASTC_FORMAT, NONE), + _T(ASTC_12x10, ASTC_RGBA_12x10 | ASTC_FORMAT, NONE), + _T(ASTC_12x12, ASTC_RGBA_12x12 | ASTC_FORMAT, NONE), /* YUV */ - _T(YUYV, YUY2, SWIZ(X, Y, Z, W), YUY2), - _T(UYVY, UYVY, SWIZ(X, Y, Z, W), NONE), + _T(YUYV, YUY2, YUY2), + _T(UYVY, UYVY, NONE), }; uint32_t translate_texture_format(enum pipe_format fmt) { + fmt = util_format_linear(fmt); + if (!formats[fmt].present) return ETNA_NO_MATCH; @@ -293,15 +268,51 @@ translate_texture_format(enum pipe_format fmt) } bool -texture_format_needs_swiz(enum pipe_format fmt) +texture_use_int_filter(const struct pipe_sampler_view *sv, + const struct pipe_sampler_state *ss, + bool tex_desc) { - static const unsigned char def[4] = SWIZ(X, Y, Z, W); - bool swiz = false; + switch (sv->target) { + case PIPE_TEXTURE_1D_ARRAY: + case PIPE_TEXTURE_2D_ARRAY: + if (tex_desc) + break; + case PIPE_TEXTURE_3D: + return false; + default: + break; + } - if (formats[fmt].present) - swiz = !!memcmp(def, formats[fmt].tex_swiz, sizeof(formats[fmt].tex_swiz)); + /* only unorm formats can use int filter */ + if (!util_format_is_unorm(sv->format)) + return false; + + if (util_format_is_srgb(sv->format)) + return false; + + if (util_format_description(sv->format)->layout == UTIL_FORMAT_LAYOUT_ASTC) + return false; + + if (ss->max_anisotropy > 1) + return false; + + switch (sv->format) { + /* apparently D16 can't use int filter but D24 can */ + case PIPE_FORMAT_Z16_UNORM: + case PIPE_FORMAT_R10G10B10A2_UNORM: + case PIPE_FORMAT_R10G10B10X2_UNORM: + case PIPE_FORMAT_ETC2_R11_UNORM: + case PIPE_FORMAT_ETC2_RG11_UNORM: + return false; + default: + return true; + } +} - return swiz; +bool +texture_format_needs_swiz(enum pipe_format fmt) +{ + return util_format_linear(fmt) == PIPE_FORMAT_R8_UNORM; } uint32_t @@ -310,10 +321,15 @@ get_texture_swiz(enum pipe_format fmt, unsigned swizzle_r, { unsigned char swiz[4] = { swizzle_r, swizzle_g, swizzle_b, swizzle_a, - }, rswiz[4]; - - assert(formats[fmt].present); - util_format_compose_swizzles(formats[fmt].tex_swiz, swiz, rswiz); + }; + + if (util_format_linear(fmt) == PIPE_FORMAT_R8_UNORM) { + /* R8 is emulated with L8, needs yz channels set to zero */ + for (unsigned i = 0; i < 4; i++) { + if (swiz[i] == PIPE_SWIZZLE_Y || swiz[i] == PIPE_SWIZZLE_Z) + swiz[i] = PIPE_SWIZZLE_0; + } + } /* PIPE_SWIZZLE_ maps 1:1 to TEXTURE_SWIZZLE_ */ STATIC_ASSERT(PIPE_SWIZZLE_X == TEXTURE_SWIZZLE_RED); @@ -323,30 +339,33 @@ get_texture_swiz(enum pipe_format fmt, unsigned swizzle_r, STATIC_ASSERT(PIPE_SWIZZLE_0 == TEXTURE_SWIZZLE_ZERO); STATIC_ASSERT(PIPE_SWIZZLE_1 == TEXTURE_SWIZZLE_ONE); - return VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_R(rswiz[0]) | - VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_G(rswiz[1]) | - VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_B(rswiz[2]) | - VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A(rswiz[3]); + return VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_R(swiz[0]) | + VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_G(swiz[1]) | + VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_B(swiz[2]) | + VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A(swiz[3]); } uint32_t -translate_rs_format(enum pipe_format fmt) +translate_pe_format(enum pipe_format fmt) { + fmt = util_format_linear(fmt); + if (!formats[fmt].present) return ETNA_NO_MATCH; - if (formats[fmt].rs == ETNA_NO_MATCH) + if (formats[fmt].pe == ETNA_NO_MATCH) return ETNA_NO_MATCH; - return RS_FORMAT(formats[fmt].rs); + return PE_FORMAT(formats[fmt].pe); } int -translate_rs_format_rb_swap(enum pipe_format fmt) +translate_pe_format_rb_swap(enum pipe_format fmt) { + fmt = util_format_linear(fmt); assert(formats[fmt].present); - return formats[fmt].rs & RS_FORMAT_RB_SWAP; + return formats[fmt].pe & PE_FORMAT_RB_SWAP; } /* Return type flags for vertex element format */ diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_format.h b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_format.h index 1672d67b9..0aaa4ad6e 100644 --- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_format.h +++ b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_format.h @@ -27,7 +27,8 @@ #ifndef ETNAVIV_FORMAT_H_ #define ETNAVIV_FORMAT_H_ -#include "util/u_format.h" +#include "util/format/u_format.h" +#include "pipe/p_state.h" #include <stdint.h> #define ETNA_NO_MATCH (~0) @@ -38,6 +39,11 @@ uint32_t translate_texture_format(enum pipe_format fmt); bool +texture_use_int_filter(const struct pipe_sampler_view *sv, + const struct pipe_sampler_state *ss, + bool tex_desc); + +bool texture_format_needs_swiz(enum pipe_format fmt); uint32_t @@ -45,10 +51,10 @@ get_texture_swiz(enum pipe_format fmt, unsigned swizzle_r, unsigned swizzle_g, unsigned swizzle_b, unsigned swizzle_a); uint32_t -translate_rs_format(enum pipe_format fmt); +translate_pe_format(enum pipe_format fmt); int -translate_rs_format_rb_swap(enum pipe_format fmt); +translate_pe_format_rb_swap(enum pipe_format fmt); uint32_t translate_vertex_format_type(enum pipe_format fmt); diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_internal.h b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_internal.h index 1f70a1cf2..dc5f3f2b9 100644 --- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_internal.h +++ b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_internal.h @@ -34,10 +34,11 @@ #include "drm/etnaviv_drmif.h" #define ETNA_NUM_INPUTS (16) -#define ETNA_NUM_VARYINGS 8 +#define ETNA_NUM_VARYINGS 16 #define ETNA_NUM_LOD (14) #define ETNA_NUM_LAYERS (6) #define ETNA_MAX_UNIFORMS (256) +#define ETNA_MAX_CONST_BUF 16 #define ETNA_MAX_PIXELPIPES 2 /* All RS operations must have width%16 = 0 */ @@ -90,6 +91,8 @@ struct etna_specs { unsigned use_blt : 1; /* can use any kind of wrapping mode on npot textures */ unsigned npot_tex_any_wrap : 1; + /* supports seamless cube map */ + unsigned seamless_cube_map : 1; /* number of bits per TS tile */ unsigned bits_per_tile; /* clear value for TS (dependent on bits_per_tile) */ @@ -152,18 +155,8 @@ struct compiled_blend_color { /* Compiled pipe_stencil_ref */ struct compiled_stencil_ref { - uint32_t PE_STENCIL_CONFIG; - uint32_t PE_STENCIL_CONFIG_EXT; -}; - -/* Compiled pipe_scissor_state */ -struct compiled_scissor_state { - uint32_t SE_SCISSOR_LEFT; - uint32_t SE_SCISSOR_TOP; - uint32_t SE_SCISSOR_RIGHT; - uint32_t SE_SCISSOR_BOTTOM; - uint32_t SE_CLIP_RIGHT; - uint32_t SE_CLIP_BOTTOM; + uint32_t PE_STENCIL_CONFIG[2]; + uint32_t PE_STENCIL_CONFIG_EXT[2]; }; /* Compiled pipe_viewport_state */ @@ -178,8 +171,6 @@ struct compiled_viewport_state { uint32_t SE_SCISSOR_TOP; uint32_t SE_SCISSOR_RIGHT; uint32_t SE_SCISSOR_BOTTOM; - uint32_t SE_CLIP_RIGHT; - uint32_t SE_CLIP_BOTTOM; uint32_t PE_DEPTH_NEAR; uint32_t PE_DEPTH_FAR; }; @@ -198,12 +189,6 @@ struct compiled_framebuffer_state { struct etna_reloc PE_PIPE_COLOR_ADDR[ETNA_MAX_PIXELPIPES]; uint32_t PE_COLOR_STRIDE; uint32_t PE_MEM_CONFIG; - uint32_t SE_SCISSOR_LEFT; - uint32_t SE_SCISSOR_TOP; - uint32_t SE_SCISSOR_RIGHT; - uint32_t SE_SCISSOR_BOTTOM; - uint32_t SE_CLIP_RIGHT; - uint32_t SE_CLIP_BOTTOM; uint32_t RA_MULTISAMPLE_UNK00E04; uint32_t RA_MULTISAMPLE_UNK00E10[VIVS_RA_MULTISAMPLE_UNK00E10__LEN]; uint32_t RA_CENTROID_TABLE[VIVS_RA_CENTROID_TABLE__LEN]; @@ -212,9 +197,12 @@ struct compiled_framebuffer_state { struct etna_reloc TS_DEPTH_STATUS_BASE; struct etna_reloc TS_DEPTH_SURFACE_BASE; uint32_t TS_COLOR_CLEAR_VALUE; + uint32_t TS_COLOR_CLEAR_VALUE_EXT; struct etna_reloc TS_COLOR_STATUS_BASE; struct etna_reloc TS_COLOR_SURFACE_BASE; uint32_t PE_LOGIC_OP; + uint32_t PS_CONTROL; + uint32_t PS_CONTROL_EXT; bool msaa_mode; /* adds input (and possible temp) to PS */ }; @@ -225,12 +213,13 @@ struct compiled_vertex_elements_state { uint32_t NFE_GENERIC_ATTRIB_CONFIG0[VIVS_NFE_GENERIC_ATTRIB__LEN]; uint32_t NFE_GENERIC_ATTRIB_SCALE[VIVS_NFE_GENERIC_ATTRIB__LEN]; uint32_t NFE_GENERIC_ATTRIB_CONFIG1[VIVS_NFE_GENERIC_ATTRIB__LEN]; + unsigned num_buffers; + uint32_t NFE_VERTEX_STREAMS_VERTEX_DIVISOR[VIVS_NFE_VERTEX_STREAMS__LEN]; }; /* Compiled context->set_vertex_buffer result */ struct compiled_set_vertex_buffer { uint32_t FE_VERTEX_STREAM_CONTROL; - uint32_t FE_VERTEX_STREAM_UNK14680; struct etna_reloc FE_VERTEX_STREAM_BASE_ADDR; }; @@ -255,12 +244,13 @@ struct compiled_shader_state { uint32_t PS_INPUT_COUNT_MSAA; /* Adds an input */ uint32_t PS_TEMP_REGISTER_CONTROL; uint32_t PS_TEMP_REGISTER_CONTROL_MSAA; /* Adds a temporary if needed to make space for extra input */ - uint32_t PS_CONTROL; uint32_t PS_START_PC; + uint32_t PE_DEPTH_CONFIG; uint32_t GL_VARYING_TOTAL_COMPONENTS; - uint32_t GL_VARYING_NUM_COMPONENTS; + uint32_t GL_VARYING_NUM_COMPONENTS[2]; uint32_t GL_VARYING_COMPONENT_USE[2]; uint32_t GL_HALTI5_SH_SPECIALS; + uint32_t FE_HALTI5_ID_CONFIG; unsigned vs_inst_mem_size; unsigned ps_inst_mem_size; uint32_t *VS_INST_MEM; diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_query.c b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_query.c index 89e016d01..01ec3bebc 100644 --- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_query.c +++ b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_query.c @@ -29,10 +29,10 @@ #include "util/u_inlines.h" #include "etnaviv_context.h" +#include "etnaviv_perfmon.h" #include "etnaviv_query.h" -#include "etnaviv_query_hw.h" +#include "etnaviv_query_acc.h" #include "etnaviv_query_sw.h" -#include "etnaviv_query_pm.h" static struct pipe_query * etna_create_query(struct pipe_context *pctx, unsigned query_type, @@ -43,9 +43,7 @@ etna_create_query(struct pipe_context *pctx, unsigned query_type, q = etna_sw_create_query(ctx, query_type); if (!q) - q = etna_hw_create_query(ctx, query_type); - if (!q) - q = etna_pm_create_query(ctx, query_type); + q = etna_acc_create_query(ctx, query_type); return (struct pipe_query *)q; } @@ -62,15 +60,10 @@ static bool etna_begin_query(struct pipe_context *pctx, struct pipe_query *pq) { struct etna_query *q = etna_query(pq); - bool ret; - - if (q->active) - return false; - ret = q->funcs->begin_query(etna_context(pctx), q); - q->active = ret; + q->funcs->begin_query(etna_context(pctx), q); - return ret; + return true; } static bool @@ -78,11 +71,7 @@ etna_end_query(struct pipe_context *pctx, struct pipe_query *pq) { struct etna_query *q = etna_query(pq); - if (!q->active) - return false; - q->funcs->end_query(etna_context(pctx), q); - q->active = false; return true; } @@ -93,9 +82,6 @@ etna_get_query_result(struct pipe_context *pctx, struct pipe_query *pq, { struct etna_query *q = etna_query(pq); - if (q->active) - return false; - util_query_clear_result(result, q->type); return q->funcs->get_query_result(etna_context(pctx), q, wait, result); @@ -139,11 +125,11 @@ etna_set_active_query_state(struct pipe_context *pctx, bool enable) struct etna_context *ctx = etna_context(pctx); if (enable) { - list_for_each_entry(struct etna_hw_query, hq, &ctx->active_hw_queries, node) - etna_hw_query_resume(hq, ctx); + list_for_each_entry(struct etna_acc_query, aq, &ctx->active_acc_queries, node) + etna_acc_query_resume(aq, ctx); } else { - list_for_each_entry(struct etna_hw_query, hq, &ctx->active_hw_queries, node) - etna_hw_query_suspend(hq, ctx); + list_for_each_entry(struct etna_acc_query, aq, &ctx->active_acc_queries, node) + etna_acc_query_suspend(aq, ctx); } } diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_query.h b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_query.h index f1aa14990..c3c5911f7 100644 --- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_query.h +++ b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_query.h @@ -35,7 +35,7 @@ struct etna_query; struct etna_query_funcs { void (*destroy_query)(struct etna_context *ctx, struct etna_query *q); - bool (*begin_query)(struct etna_context *ctx, struct etna_query *q); + void (*begin_query)(struct etna_context *ctx, struct etna_query *q); void (*end_query)(struct etna_context *ctx, struct etna_query *q); bool (*get_query_result)(struct etna_context *ctx, struct etna_query *q, bool wait, union pipe_query_result *result); @@ -43,7 +43,6 @@ struct etna_query_funcs { struct etna_query { const struct etna_query_funcs *funcs; - bool active; unsigned type; }; diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_query_hw.c b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_query_hw.c deleted file mode 100644 index 0f3cd7257..000000000 --- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_query_hw.c +++ /dev/null @@ -1,263 +0,0 @@ -/* - * Copyright (c) 2017 Etnaviv Project - * Copyright (C) 2017 Zodiac Inflight Innovations - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sub license, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * Rob Clark <robclark@freedesktop.org> - * Christian Gmeiner <christian.gmeiner@gmail.com> - */ - -#include "util/u_inlines.h" -#include "util/u_memory.h" - -#include "etnaviv_context.h" -#include "etnaviv_debug.h" -#include "etnaviv_emit.h" -#include "etnaviv_query_hw.h" -#include "etnaviv_screen.h" - -/* - * Occlusion Query: - * - * OCCLUSION_COUNTER and OCCLUSION_PREDICATE differ only in how they - * interpret results - */ - -static void -occlusion_start(struct etna_hw_query *hq, struct etna_context *ctx) -{ - struct etna_resource *rsc = etna_resource(hq->prsc); - struct etna_reloc r = { - .bo = rsc->bo, - .flags = ETNA_RELOC_WRITE - }; - - if (hq->samples > 63) { - hq->samples = 63; - BUG("samples overflow"); - } - - r.offset = hq->samples * 8; /* 64bit value */ - - etna_set_state_reloc(ctx->stream, VIVS_GL_OCCLUSION_QUERY_ADDR, &r); -} - -static void -occlusion_stop(struct etna_hw_query *hq, struct etna_context *ctx) -{ - /* 0x1DF5E76 is the value used by blob - but any random value will work */ - etna_set_state(ctx->stream, VIVS_GL_OCCLUSION_QUERY_CONTROL, 0x1DF5E76); -} - -static void -occlusion_suspend(struct etna_hw_query *hq, struct etna_context *ctx) -{ - occlusion_stop(hq, ctx); -} - -static void -occlusion_resume(struct etna_hw_query *hq, struct etna_context *ctx) -{ - hq->samples++; - occlusion_start(hq, ctx); -} - -static void -occlusion_result(struct etna_hw_query *hq, void *buf, - union pipe_query_result *result) -{ - uint64_t sum = 0; - uint64_t *ptr = (uint64_t *)buf; - - for (unsigned i = 0; i <= hq->samples; i++) - sum += *(ptr + i); - - if (hq->base.type == PIPE_QUERY_OCCLUSION_COUNTER) - result->u64 = sum; - else - result->b = !!sum; -} - -static void -etna_hw_destroy_query(struct etna_context *ctx, struct etna_query *q) -{ - struct etna_hw_query *hq = etna_hw_query(q); - - pipe_resource_reference(&hq->prsc, NULL); - list_del(&hq->node); - - FREE(hq); -} - -static const struct etna_hw_sample_provider occlusion_provider = { - .start = occlusion_start, - .stop = occlusion_stop, - .suspend = occlusion_suspend, - .resume = occlusion_resume, - .result = occlusion_result, -}; - -static void -realloc_query_bo(struct etna_context *ctx, struct etna_hw_query *hq) -{ - struct etna_resource *rsc; - void *map; - - pipe_resource_reference(&hq->prsc, NULL); - - /* allocate resource with space for 64 * 64bit values */ - hq->prsc = pipe_buffer_create(&ctx->screen->base, PIPE_BIND_QUERY_BUFFER, - 0, 0x1000); - - /* don't assume the buffer is zero-initialized */ - rsc = etna_resource(hq->prsc); - - etna_bo_cpu_prep(rsc->bo, DRM_ETNA_PREP_WRITE); - - map = etna_bo_map(rsc->bo); - memset(map, 0, 0x1000); - etna_bo_cpu_fini(rsc->bo); -} - -static boolean -etna_hw_begin_query(struct etna_context *ctx, struct etna_query *q) -{ - struct etna_hw_query *hq = etna_hw_query(q); - const struct etna_hw_sample_provider *p = hq->provider; - - /* ->begin_query() discards previous results, so realloc bo */ - realloc_query_bo(ctx, hq); - - p->start(hq, ctx); - - /* add to active list */ - assert(list_empty(&hq->node)); - list_addtail(&hq->node, &ctx->active_hw_queries); - - return true; -} - -static void -etna_hw_end_query(struct etna_context *ctx, struct etna_query *q) -{ - struct etna_hw_query *hq = etna_hw_query(q); - const struct etna_hw_sample_provider *p = hq->provider; - - p->stop(hq, ctx); - - /* remove from active list */ - list_delinit(&hq->node); -} - -static boolean -etna_hw_get_query_result(struct etna_context *ctx, struct etna_query *q, - boolean wait, union pipe_query_result *result) -{ - struct etna_hw_query *hq = etna_hw_query(q); - struct etna_resource *rsc = etna_resource(hq->prsc); - const struct etna_hw_sample_provider *p = hq->provider; - - assert(LIST_IS_EMPTY(&hq->node)); - - if (!wait) { - int ret; - - if (rsc->status & ETNA_PENDING_WRITE) { - /* piglit spec@arb_occlusion_query@occlusion_query_conform - * test, and silly apps perhaps, get stuck in a loop trying - * to get query result forever with wait==false.. we don't - * wait to flush unnecessarily but we also don't want to - * spin forever. - */ - if (hq->no_wait_cnt++ > 5) - ctx->base.flush(&ctx->base, NULL, 0); - return false; - } - - ret = etna_bo_cpu_prep(rsc->bo, DRM_ETNA_PREP_READ | DRM_ETNA_PREP_NOSYNC); - if (ret) - return false; - - etna_bo_cpu_fini(rsc->bo); - } - - /* flush that GPU executes all query related actions */ - ctx->base.flush(&ctx->base, NULL, 0); - - /* get the result */ - etna_bo_cpu_prep(rsc->bo, DRM_ETNA_PREP_READ); - - void *ptr = etna_bo_map(rsc->bo); - p->result(hq, ptr, result); - - etna_bo_cpu_fini(rsc->bo); - - return true; -} - -static const struct etna_query_funcs hw_query_funcs = { - .destroy_query = etna_hw_destroy_query, - .begin_query = etna_hw_begin_query, - .end_query = etna_hw_end_query, - .get_query_result = etna_hw_get_query_result, -}; - -static inline const struct etna_hw_sample_provider * -query_sample_provider(unsigned query_type) -{ - switch (query_type) { - case PIPE_QUERY_OCCLUSION_COUNTER: - /* fallthrough */ - case PIPE_QUERY_OCCLUSION_PREDICATE: - /* fallthrough */ - case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE: - return &occlusion_provider; - default: - return NULL; - } -} - -struct etna_query * -etna_hw_create_query(struct etna_context *ctx, unsigned query_type) -{ - struct etna_hw_query *hq; - struct etna_query *q; - const struct etna_hw_sample_provider *p; - - p = query_sample_provider(query_type); - if (!p) - return NULL; - - hq = CALLOC_STRUCT(etna_hw_query); - if (!hq) - return NULL; - - hq->provider = p; - - list_inithead(&hq->node); - - q = &hq->base; - q->funcs = &hw_query_funcs; - q->type = query_type; - - return q; -} diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_query_hw.h b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_query_hw.h deleted file mode 100644 index 73f3c851e..000000000 --- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_query_hw.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Copyright (c) 2017 Etnaviv Project - * Copyright (C) 2017 Zodiac Inflight Innovations - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sub license, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * Rob Clark <robclark@freedesktop.org> - * Christian Gmeiner <christian.gmeiner@gmail.com> - */ - -#ifndef H_ETNAVIV_QUERY_HW -#define H_ETNAVIV_QUERY_HW - -#include "etnaviv_query.h" - -struct etna_hw_query; - -struct etna_hw_sample_provider { - void (*start)(struct etna_hw_query *hq, struct etna_context *ctx); - void (*stop)(struct etna_hw_query *hq, struct etna_context *ctx); - void (*suspend)(struct etna_hw_query *hq, struct etna_context *ctx); - void (*resume)(struct etna_hw_query *hq, struct etna_context *ctx); - - void (*result)(struct etna_hw_query *hq, void *buf, - union pipe_query_result *result); -}; - -struct etna_hw_query { - struct etna_query base; - - struct pipe_resource *prsc; - unsigned samples; /* number of samples stored in resource */ - unsigned no_wait_cnt; /* see etna_hw_get_query_result() */ - struct list_head node; /* list-node in ctx->active_hw_queries */ - - const struct etna_hw_sample_provider *provider; -}; - -static inline struct etna_hw_query * -etna_hw_query(struct etna_query *q) -{ - return (struct etna_hw_query *)q; -} - -struct etna_query * -etna_hw_create_query(struct etna_context *ctx, unsigned query_type); - -static inline void -etna_hw_query_suspend(struct etna_hw_query *hq, struct etna_context *ctx) -{ - const struct etna_hw_sample_provider *p = hq->provider; - - if (!hq->base.active) - return; - - p->suspend(hq, ctx); -} - -static inline void -etna_hw_query_resume(struct etna_hw_query *hq, struct etna_context *ctx) -{ - const struct etna_hw_sample_provider *p = hq->provider; - - if (!hq->base.active) - return; - - p->resume(hq, ctx); -} - -#endif diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_query_pm.c b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_query_pm.c deleted file mode 100644 index ade0b9790..000000000 --- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_query_pm.c +++ /dev/null @@ -1,678 +0,0 @@ -/* - * Copyright (c) 2017 Etnaviv Project - * Copyright (C) 2017 Zodiac Inflight Innovations - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sub license, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * Christian Gmeiner <christian.gmeiner@gmail.com> - */ - -#include "util/u_inlines.h" -#include "util/u_memory.h" - -#include "etnaviv_context.h" -#include "etnaviv_query_pm.h" -#include "etnaviv_screen.h" - -struct etna_perfmon_source -{ - const char *domain; - const char *signal; -}; - -struct etna_perfmon_config -{ - const char *name; - unsigned type; - unsigned group_id; - const struct etna_perfmon_source *source; -}; - -static const char *group_names[] = { - [ETNA_QUERY_HI_GROUP_ID] = "HI", - [ETNA_QUERY_PE_GROUP_ID] = "PE", - [ETNA_QUERY_SH_GROUP_ID] = "SH", - [ETNA_QUERY_PA_GROUP_ID] = "PA", - [ETNA_QUERY_SE_GROUP_ID] = "SE", - [ETNA_QUERY_RA_GROUP_ID] = "RA", - [ETNA_QUERY_TX_GROUP_ID] = "TX", - [ETNA_QUERY_MC_GROUP_ID] = "MC", -}; - -static const struct etna_perfmon_config query_config[] = { - { - .name = "hi-total-cycles", - .type = ETNA_QUERY_HI_TOTAL_CYCLES, - .group_id = ETNA_QUERY_HI_GROUP_ID, - .source = (const struct etna_perfmon_source[]) { - { "HI", "TOTAL_CYCLES" } - } - }, - { - .name = "hi-idle-cycles", - .type = ETNA_QUERY_HI_IDLE_CYCLES, - .group_id = ETNA_QUERY_HI_GROUP_ID, - .source = (const struct etna_perfmon_source[]) { - { "HI", "IDLE_CYCLES" } - } - }, - { - .name = "hi-axi-cycles-read-request-stalled", - .type = ETNA_QUERY_HI_AXI_CYCLES_READ_REQUEST_STALLED, - .group_id = ETNA_QUERY_HI_GROUP_ID, - .source = (const struct etna_perfmon_source[]) { - { "HI", "AXI_CYCLES_READ_REQUEST_STALLED" } - } - }, - { - .name = "hi-axi-cycles-write-request-stalled", - .type = ETNA_QUERY_HI_AXI_CYCLES_WRITE_REQUEST_STALLED, - .group_id = ETNA_QUERY_HI_GROUP_ID, - .source = (const struct etna_perfmon_source[]) { - { "HI", "AXI_CYCLES_WRITE_REQUEST_STALLED" } - } - }, - { - .name = "hi-axi-cycles-write-data-stalled", - .type = ETNA_QUERY_HI_AXI_CYCLES_WRITE_DATA_STALLED, - .group_id = ETNA_QUERY_HI_GROUP_ID, - .source = (const struct etna_perfmon_source[]) { - { "HI", "AXI_CYCLES_WRITE_DATA_STALLED" } - } - }, - { - .name = "pe-pixel-count-killed-by-color-pipe", - .type = ETNA_QUERY_PE_PIXEL_COUNT_KILLED_BY_COLOR_PIPE, - .group_id = ETNA_QUERY_PE_GROUP_ID, - .source = (const struct etna_perfmon_source[]) { - { "PE", "PIXEL_COUNT_KILLED_BY_COLOR_PIPE" } - } - }, - { - .name = "pe-pixel-count-killed-by-depth-pipe", - .type = ETNA_QUERY_PE_PIXEL_COUNT_KILLED_BY_DEPTH_PIPE, - .group_id = ETNA_QUERY_PE_GROUP_ID, - .source = (const struct etna_perfmon_source[]) { - { "PE", "PIXEL_COUNT_KILLED_BY_DEPTH_PIPE" } - } - }, - { - .name = "pe-pixel-count-drawn-by-color-pipe", - .type = ETNA_QUERY_PE_PIXEL_COUNT_DRAWN_BY_COLOR_PIPE, - .group_id = ETNA_QUERY_PE_GROUP_ID, - .source = (const struct etna_perfmon_source[]) { - { "PE", "PIXEL_COUNT_DRAWN_BY_COLOR_PIPE" } - } - }, - { - .name = "pe-pixel-count-drawn-by-depth-pipe", - .type = ETNA_QUERY_PE_PIXEL_COUNT_DRAWN_BY_DEPTH_PIPE, - .group_id = ETNA_QUERY_PE_GROUP_ID, - .source = (const struct etna_perfmon_source[]) { - { "PE", "PIXEL_COUNT_DRAWN_BY_DEPTH_PIPE" } - } - }, - { - .name = "sh-shader-cycles", - .type = ETNA_QUERY_SH_SHADER_CYCLES, - .group_id = ETNA_QUERY_SH_GROUP_ID, - .source = (const struct etna_perfmon_source[]) { - { "SH", "SHADER_CYCLES" } - } - }, - { - .name = "sh-ps-inst-counter", - .type = ETNA_QUERY_SH_PS_INST_COUNTER, - .group_id = ETNA_QUERY_SH_GROUP_ID, - .source = (const struct etna_perfmon_source[]) { - { "SH", "PS_INST_COUNTER" } - } - }, - { - .name = "sh-rendered-pixel-counter", - .type = ETNA_QUERY_SH_RENDERED_PIXEL_COUNTER, - .group_id = ETNA_QUERY_SH_GROUP_ID, - .source = (const struct etna_perfmon_source[]) { - { "SH", "RENDERED_PIXEL_COUNTER" } - } - }, - { - .name = "sh-vs-inst-counter", - .type = ETNA_QUERY_SH_VS_INST_COUNTER, - .group_id = ETNA_QUERY_SH_GROUP_ID, - .source = (const struct etna_perfmon_source[]) { - { "SH", "VS_INST_COUNTER" } - } - }, - { - .name = "sh-rendered-vertice-counter", - .type = ETNA_QUERY_SH_RENDERED_VERTICE_COUNTER, - .group_id = ETNA_QUERY_SH_GROUP_ID, - .source = (const struct etna_perfmon_source[]) { - { "SH", "RENDERED_VERTICE_COUNTER" } - } - }, - { - .name = "sh-vtx-branch-inst-counter", - .type = ETNA_QUERY_SH_RENDERED_VERTICE_COUNTER, - .group_id = ETNA_QUERY_SH_GROUP_ID, - .source = (const struct etna_perfmon_source[]) { - { "SH", "VTX_BRANCH_INST_COUNTER" } - } - }, - { - .name = "sh-vtx-texld-inst-counter", - .type = ETNA_QUERY_SH_RENDERED_VERTICE_COUNTER, - .group_id = ETNA_QUERY_SH_GROUP_ID, - .source = (const struct etna_perfmon_source[]) { - { "SH", "VTX_TEXLD_INST_COUNTER" } - } - }, - { - .name = "sh-plx-branch-inst-counter", - .type = ETNA_QUERY_SH_RENDERED_VERTICE_COUNTER, - .group_id = ETNA_QUERY_SH_GROUP_ID, - .source = (const struct etna_perfmon_source[]) { - { "SH", "PXL_BRANCH_INST_COUNTER" } - } - }, - { - .name = "sh-plx-texld-inst-counter", - .type = ETNA_QUERY_SH_RENDERED_VERTICE_COUNTER, - .group_id = ETNA_QUERY_SH_GROUP_ID, - .source = (const struct etna_perfmon_source[]) { - { "SH", "PXL_TEXLD_INST_COUNTER" } - } - }, - { - .name = "pa-input-vtx-counter", - .type = ETNA_QUERY_PA_INPUT_VTX_COUNTER, - .group_id = ETNA_QUERY_PA_GROUP_ID, - .source = (const struct etna_perfmon_source[]) { - { "PA", "INPUT_VTX_COUNTER" } - } - }, - { - .name = "pa-input-prim-counter", - .type = ETNA_QUERY_PA_INPUT_PRIM_COUNTER, - .group_id = ETNA_QUERY_PA_GROUP_ID, - .source = (const struct etna_perfmon_source[]) { - { "PA", "INPUT_PRIM_COUNTER" } - } - }, - { - .name = "pa-output-prim-counter", - .type = ETNA_QUERY_PA_OUTPUT_PRIM_COUNTER, - .group_id = ETNA_QUERY_PA_GROUP_ID, - .source = (const struct etna_perfmon_source[]) { - { "PA", "OUTPUT_PRIM_COUNTER" } - } - }, - { - .name = "pa-depth-clipped-counter", - .type = ETNA_QUERY_PA_DEPTH_CLIPPED_COUNTER, - .group_id = ETNA_QUERY_PA_GROUP_ID, - .source = (const struct etna_perfmon_source[]) { - { "PA", "DEPTH_CLIPPED_COUNTER" } - } - }, - { - .name = "pa-trivial-rejected-counter", - .type = ETNA_QUERY_PA_TRIVIAL_REJECTED_COUNTER, - .group_id = ETNA_QUERY_PA_GROUP_ID, - .source = (const struct etna_perfmon_source[]) { - { "PA", "TRIVIAL_REJECTED_COUNTER" } - } - }, - { - .name = "pa-culled-counter", - .type = ETNA_QUERY_PA_CULLED_COUNTER, - .group_id = ETNA_QUERY_PA_GROUP_ID, - .source = (const struct etna_perfmon_source[]) { - { "PA", "CULLED_COUNTER" } - } - }, - { - .name = "se-culled-triangle-count", - .type = ETNA_QUERY_SE_CULLED_TRIANGLE_COUNT, - .group_id = ETNA_QUERY_SE_GROUP_ID, - .source = (const struct etna_perfmon_source[]) { - { "SE", "CULLED_TRIANGLE_COUNT" } - } - }, - { - .name = "se-culled-lines-count", - .type = ETNA_QUERY_SE_CULLED_LINES_COUNT, - .group_id = ETNA_QUERY_SE_GROUP_ID, - .source = (const struct etna_perfmon_source[]) { - { "SE", "CULLED_LINES_COUNT" } - } - }, - { - .name = "ra-valid-pixel-count", - .type = ETNA_QUERY_RA_VALID_PIXEL_COUNT, - .group_id = ETNA_QUERY_RA_GROUP_ID, - .source = (const struct etna_perfmon_source[]) { - { "RA", "VALID_PIXEL_COUNT" } - } - }, - { - .name = "ra-total-quad-count", - .type = ETNA_QUERY_RA_TOTAL_QUAD_COUNT, - .group_id = ETNA_QUERY_RA_GROUP_ID, - .source = (const struct etna_perfmon_source[]) { - { "RA", "TOTAL_QUAD_COUNT" } - } - }, - { - .name = "ra-valid-quad-count-after-early-z", - .type = ETNA_QUERY_RA_VALID_QUAD_COUNT_AFTER_EARLY_Z, - .group_id = ETNA_QUERY_RA_GROUP_ID, - .source = (const struct etna_perfmon_source[]) { - { "RA", "VALID_QUAD_COUNT_AFTER_EARLY_Z" } - } - }, - { - .name = "ra-total-primitive-count", - .type = ETNA_QUERY_RA_TOTAL_PRIMITIVE_COUNT, - .group_id = ETNA_QUERY_RA_GROUP_ID, - .source = (const struct etna_perfmon_source[]) { - { "RA", "TOTAL_PRIMITIVE_COUNT" } - } - }, - { - .name = "ra-pipe-cache-miss-counter", - .type = ETNA_QUERY_RA_PIPE_CACHE_MISS_COUNTER, - .group_id = ETNA_QUERY_RA_GROUP_ID, - .source = (const struct etna_perfmon_source[]) { - { "RA", "PIPE_CACHE_MISS_COUNTER" } - } - }, - { - .name = "ra-prefetch-cache-miss-counter", - .type = ETNA_QUERY_RA_PREFETCH_CACHE_MISS_COUNTER, - .group_id = ETNA_QUERY_RA_GROUP_ID, - .source = (const struct etna_perfmon_source[]) { - { "RA", "PREFETCH_CACHE_MISS_COUNTER" } - } - }, - { - .name = "ra-pculled-quad-count", - .type = ETNA_QUERY_RA_CULLED_QUAD_COUNT, - .group_id = ETNA_QUERY_RA_GROUP_ID, - .source = (const struct etna_perfmon_source[]) { - { "RA", "CULLED_QUAD_COUNT" } - } - }, - { - .name = "tx-total-bilinear-requests", - .type = ETNA_QUERY_TX_TOTAL_BILINEAR_REQUESTS, - .group_id = ETNA_QUERY_TX_GROUP_ID, - .source = (const struct etna_perfmon_source[]) { - { "TX", "TOTAL_BILINEAR_REQUESTS" } - } - }, - { - .name = "tx-total-trilinear-requests", - .type = ETNA_QUERY_TX_TOTAL_TRILINEAR_REQUESTS, - .group_id = ETNA_QUERY_TX_GROUP_ID, - .source = (const struct etna_perfmon_source[]) { - { "TX", "TOTAL_TRILINEAR_REQUESTS" } - } - }, - { - .name = "tx-total-discarded-texture-requests", - .type = ETNA_QUERY_TX_TOTAL_DISCARDED_TEXTURE_REQUESTS, - .group_id = ETNA_QUERY_TX_GROUP_ID, - .source = (const struct etna_perfmon_source[]) { - { "TX", "TOTAL_DISCARDED_TEXTURE_REQUESTS" } - } - }, - { - .name = "tx-total-texture-requests", - .type = ETNA_QUERY_TX_TOTAL_TEXTURE_REQUESTS, - .group_id = ETNA_QUERY_TX_GROUP_ID, - .source = (const struct etna_perfmon_source[]) { - { "TX", "TOTAL_TEXTURE_REQUESTS" } - } - }, - { - .name = "tx-mem-read-count", - .type = ETNA_QUERY_TX_MEM_READ_COUNT, - .group_id = ETNA_QUERY_TX_GROUP_ID, - .source = (const struct etna_perfmon_source[]) { - { "TX", "MEM_READ_COUNT" } - } - }, - { - .name = "tx-mem-read-in-8b-count", - .type = ETNA_QUERY_TX_MEM_READ_IN_8B_COUNT, - .group_id = ETNA_QUERY_TX_GROUP_ID, - .source = (const struct etna_perfmon_source[]) { - { "TX", "MEM_READ_IN_8B_COUNT" } - } - }, - { - .name = "tx-cache-miss-count", - .type = ETNA_QUERY_TX_CACHE_MISS_COUNT, - .group_id = ETNA_QUERY_TX_GROUP_ID, - .source = (const struct etna_perfmon_source[]) { - { "TX", "CACHE_MISS_COUNT" } - } - }, - { - .name = "tx-cache-hit-texel-count", - .type = ETNA_QUERY_TX_CACHE_HIT_TEXEL_COUNT, - .group_id = ETNA_QUERY_TX_GROUP_ID, - .source = (const struct etna_perfmon_source[]) { - { "TX", "CACHE_HIT_TEXEL_COUNT" } - } - }, - { - .name = "tx-cache-miss-texel-count", - .type = ETNA_QUERY_TX_CACHE_MISS_TEXEL_COUNT, - .group_id = ETNA_QUERY_TX_GROUP_ID, - .source = (const struct etna_perfmon_source[]) { - { "TX", "CACHE_MISS_TEXEL_COUNT" } - } - }, - { - .name = "mc-total-read-req-8b-from-pipeline", - .type = ETNA_QUERY_MC_TOTAL_READ_REQ_8B_FROM_PIPELINE, - .group_id = ETNA_QUERY_MC_GROUP_ID, - .source = (const struct etna_perfmon_source[]) { - { "MC", "TOTAL_READ_REQ_8B_FROM_PIPELINE" } - } - }, - { - .name = "mc-total-read-req-8b-from-ip", - .type = ETNA_QUERY_MC_TOTAL_READ_REQ_8B_FROM_IP, - .group_id = ETNA_QUERY_MC_GROUP_ID, - .source = (const struct etna_perfmon_source[]) { - { "MC", "TOTAL_READ_REQ_8B_FROM_IP" } - } - }, - { - .name = "mc-total-write-req-8b-from-pipeline", - .type = ETNA_QUERY_MC_TOTAL_WRITE_REQ_8B_FROM_PIPELINE, - .group_id = ETNA_QUERY_MC_GROUP_ID, - .source = (const struct etna_perfmon_source[]) { - { "MC", "TOTAL_WRITE_REQ_8B_FROM_PIPELINE" } - } - } -}; - -static const struct etna_perfmon_config * -etna_pm_query_config(unsigned type) -{ - for (unsigned i = 0; i < ARRAY_SIZE(query_config); i++) - if (query_config[i].type == type) - return &query_config[i]; - - return NULL; -} - -static struct etna_perfmon_signal * -etna_pm_query_signal(struct etna_perfmon *perfmon, - const struct etna_perfmon_source *source) -{ - struct etna_perfmon_domain *domain; - - domain = etna_perfmon_get_dom_by_name(perfmon, source->domain); - if (!domain) - return NULL; - - return etna_perfmon_get_sig_by_name(domain, source->signal); -} - -static inline bool -etna_pm_cfg_supported(struct etna_perfmon *perfmon, - const struct etna_perfmon_config *cfg) -{ - struct etna_perfmon_signal *signal = etna_pm_query_signal(perfmon, cfg->source); - - return !!signal; -} - -static inline void -etna_pm_add_signal(struct etna_pm_query *pq, struct etna_perfmon *perfmon, - const struct etna_perfmon_config *cfg) -{ - struct etna_perfmon_signal *signal = etna_pm_query_signal(perfmon, cfg->source); - - pq->signal = signal; -} - -static bool -realloc_query_bo(struct etna_context *ctx, struct etna_pm_query *pq) -{ - if (pq->bo) - etna_bo_del(pq->bo); - - pq->bo = etna_bo_new(ctx->screen->dev, 64, DRM_ETNA_GEM_CACHE_WC); - if (unlikely(!pq->bo)) - return false; - - pq->data = etna_bo_map(pq->bo); - - return true; -} - -static void -etna_pm_query_get(struct etna_cmd_stream *stream, struct etna_query *q, - unsigned flags) -{ - struct etna_pm_query *pq = etna_pm_query(q); - unsigned offset; - assert(flags); - - if (flags == ETNA_PM_PROCESS_PRE) - offset = 2; - else - offset = 3; - - struct etna_perf p = { - .flags = flags, - .sequence = pq->sequence, - .bo = pq->bo, - .signal = pq->signal, - .offset = offset - }; - - etna_cmd_stream_perf(stream, &p); -} - -static inline void -etna_pm_query_update(struct etna_query *q) -{ - struct etna_pm_query *pq = etna_pm_query(q); - - if (pq->data[0] == pq->sequence) - pq->ready = true; -} - -static void -etna_pm_destroy_query(struct etna_context *ctx, struct etna_query *q) -{ - struct etna_pm_query *pq = etna_pm_query(q); - - etna_bo_del(pq->bo); - FREE(pq); -} - -static boolean -etna_pm_begin_query(struct etna_context *ctx, struct etna_query *q) -{ - struct etna_pm_query *pq = etna_pm_query(q); - - pq->ready = false; - pq->sequence++; - - etna_pm_query_get(ctx->stream, q, ETNA_PM_PROCESS_PRE); - - return true; -} - -static void -etna_pm_end_query(struct etna_context *ctx, struct etna_query *q) -{ - etna_pm_query_get(ctx->stream, q, ETNA_PM_PROCESS_POST); -} - -static boolean -etna_pm_get_query_result(struct etna_context *ctx, struct etna_query *q, - boolean wait, union pipe_query_result *result) -{ - struct etna_pm_query *pq = etna_pm_query(q); - - etna_pm_query_update(q); - - if (!pq->ready) { - if (!wait) - return false; - - if (!etna_bo_cpu_prep(pq->bo, DRM_ETNA_PREP_READ)) - return false; - - pq->ready = true; - etna_bo_cpu_fini(pq->bo); - } - - result->u32 = pq->data[2] - pq->data[1]; - - return true; -} - -static const struct etna_query_funcs hw_query_funcs = { - .destroy_query = etna_pm_destroy_query, - .begin_query = etna_pm_begin_query, - .end_query = etna_pm_end_query, - .get_query_result = etna_pm_get_query_result, -}; - -struct etna_query * -etna_pm_create_query(struct etna_context *ctx, unsigned query_type) -{ - struct etna_perfmon *perfmon = ctx->screen->perfmon; - const struct etna_perfmon_config *cfg; - struct etna_pm_query *pq; - struct etna_query *q; - - cfg = etna_pm_query_config(query_type); - if (!cfg) - return NULL; - - if (!etna_pm_cfg_supported(perfmon, cfg)) - return NULL; - - pq = CALLOC_STRUCT(etna_pm_query); - if (!pq) - return NULL; - - if (!realloc_query_bo(ctx, pq)) { - FREE(pq); - return NULL; - } - - q = &pq->base; - q->funcs = &hw_query_funcs; - q->type = query_type; - - etna_pm_add_signal(pq, perfmon, cfg); - - return q; -} - -void -etna_pm_query_setup(struct etna_screen *screen) -{ - screen->perfmon = etna_perfmon_create(screen->pipe); - - if (!screen->perfmon) - return; - - for (unsigned i = 0; i < ARRAY_SIZE(query_config); i++) { - const struct etna_perfmon_config *cfg = &query_config[i]; - - if (!etna_pm_cfg_supported(screen->perfmon, cfg)) - continue; - - util_dynarray_append(&screen->supported_pm_queries, unsigned, i); - } -} - -int -etna_pm_get_driver_query_info(struct pipe_screen *pscreen, unsigned index, - struct pipe_driver_query_info *info) -{ - const struct etna_screen *screen = etna_screen(pscreen); - const unsigned num = screen->supported_pm_queries.size / sizeof(unsigned); - unsigned i; - - if (!info) - return num; - - if (index >= num) - return 0; - - i = *util_dynarray_element(&screen->supported_pm_queries, unsigned, index); - assert(i < ARRAY_SIZE(query_config)); - - info->name = query_config[i].name; - info->query_type = query_config[i].type; - info->group_id = query_config[i].group_id; - - return 1; -} - -static -unsigned query_count(unsigned group) -{ - unsigned count = 0; - - for (unsigned i = 0; i < ARRAY_SIZE(query_config); i++) - if (query_config[i].group_id == group) - count++; - - assert(count); - - return count; -} - -int -etna_pm_get_driver_query_group_info(struct pipe_screen *pscreen, - unsigned index, - struct pipe_driver_query_group_info *info) -{ - if (!info) - return ARRAY_SIZE(group_names); - - if (index >= ARRAY_SIZE(group_names)) - return 0; - - unsigned count = query_count(index); - - info->name = group_names[index]; - info->max_active_queries = count; - info->num_queries = count; - - return 1; -} diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_query_pm.h b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_query_pm.h deleted file mode 100644 index e80310cab..000000000 --- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_query_pm.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright (c) 2017 Etnaviv Project - * Copyright (C) 2017 Zodiac Inflight Innovations - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sub license, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * Rob Clark <robclark@freedesktop.org> - * Christian Gmeiner <christian.gmeiner@gmail.com> - */ - -#ifndef H_ETNAVIV_QUERY_PM -#define H_ETNAVIV_QUERY_PM - -#include "etnaviv_query.h" - -struct etna_screen; - -#define ETNA_QUERY_HI_GROUP_ID 1 -#define ETNA_QUERY_PE_GROUP_ID 2 -#define ETNA_QUERY_SH_GROUP_ID 3 -#define ETNA_QUERY_PA_GROUP_ID 4 -#define ETNA_QUERY_SE_GROUP_ID 5 -#define ETNA_QUERY_RA_GROUP_ID 6 -#define ETNA_QUERY_TX_GROUP_ID 7 -#define ETNA_QUERY_MC_GROUP_ID 8 - -#define ETNA_QUERY_HI_TOTAL_CYCLES (ETNA_PM_QUERY_BASE + 0) -#define ETNA_QUERY_HI_IDLE_CYCLES (ETNA_PM_QUERY_BASE + 1) -#define ETNA_QUERY_HI_AXI_CYCLES_READ_REQUEST_STALLED (ETNA_PM_QUERY_BASE + 2) -#define ETNA_QUERY_HI_AXI_CYCLES_WRITE_REQUEST_STALLED (ETNA_PM_QUERY_BASE + 3) -#define ETNA_QUERY_HI_AXI_CYCLES_WRITE_DATA_STALLED (ETNA_PM_QUERY_BASE + 4) - -#define ETNA_QUERY_PE_PIXEL_COUNT_KILLED_BY_COLOR_PIPE (ETNA_PM_QUERY_BASE + 5) -#define ETNA_QUERY_PE_PIXEL_COUNT_KILLED_BY_DEPTH_PIPE (ETNA_PM_QUERY_BASE + 6) -#define ETNA_QUERY_PE_PIXEL_COUNT_DRAWN_BY_COLOR_PIPE (ETNA_PM_QUERY_BASE + 7) -#define ETNA_QUERY_PE_PIXEL_COUNT_DRAWN_BY_DEPTH_PIPE (ETNA_PM_QUERY_BASE + 8) -#define ETNA_QUERY_PE_PIXELS_RENDERED_2D (ETNA_PM_QUERY_BASE + 9) - -#define ETNA_QUERY_SH_SHADER_CYCLES (ETNA_PM_QUERY_BASE + 10) -#define ETNA_QUERY_SH_PS_INST_COUNTER (ETNA_PM_QUERY_BASE + 11) -#define ETNA_QUERY_SH_RENDERED_PIXEL_COUNTER (ETNA_PM_QUERY_BASE + 12) -#define ETNA_QUERY_SH_VS_INST_COUNTER (ETNA_PM_QUERY_BASE + 13) -#define ETNA_QUERY_SH_RENDERED_VERTICE_COUNTER (ETNA_PM_QUERY_BASE + 14) -#define ETNA_QUERY_SH_VTX_BRANCH_INST_COUNTER (ETNA_PM_QUERY_BASE + 15) -#define ETNA_QUERY_SH_VTX_TEXLD_INST_COUNTER (ETNA_PM_QUERY_BASE + 16) -#define ETNA_QUERY_SH_PXL_BRANCH_INST_COUNTER (ETNA_PM_QUERY_BASE + 17) -#define ETNA_QUERY_SH_PXL_TEXLD_INST_COUNTER (ETNA_PM_QUERY_BASE + 18) - -#define ETNA_QUERY_PA_INPUT_VTX_COUNTER (ETNA_PM_QUERY_BASE + 19) -#define ETNA_QUERY_PA_INPUT_PRIM_COUNTER (ETNA_PM_QUERY_BASE + 20) -#define ETNA_QUERY_PA_OUTPUT_PRIM_COUNTER (ETNA_PM_QUERY_BASE + 21) -#define ETNA_QUERY_PA_DEPTH_CLIPPED_COUNTER (ETNA_PM_QUERY_BASE + 22) -#define ETNA_QUERY_PA_TRIVIAL_REJECTED_COUNTER (ETNA_PM_QUERY_BASE + 23) -#define ETNA_QUERY_PA_CULLED_COUNTER (ETNA_PM_QUERY_BASE + 24) - -#define ETNA_QUERY_SE_CULLED_TRIANGLE_COUNT (ETNA_PM_QUERY_BASE + 25) -#define ETNA_QUERY_SE_CULLED_LINES_COUNT (ETNA_PM_QUERY_BASE + 26) - -#define ETNA_QUERY_RA_VALID_PIXEL_COUNT (ETNA_PM_QUERY_BASE + 27) -#define ETNA_QUERY_RA_TOTAL_QUAD_COUNT (ETNA_PM_QUERY_BASE + 28) -#define ETNA_QUERY_RA_VALID_QUAD_COUNT_AFTER_EARLY_Z (ETNA_PM_QUERY_BASE + 29) -#define ETNA_QUERY_RA_TOTAL_PRIMITIVE_COUNT (ETNA_PM_QUERY_BASE + 30) -#define ETNA_QUERY_RA_PIPE_CACHE_MISS_COUNTER (ETNA_PM_QUERY_BASE + 31) -#define ETNA_QUERY_RA_PREFETCH_CACHE_MISS_COUNTER (ETNA_PM_QUERY_BASE + 32) -#define ETNA_QUERY_RA_CULLED_QUAD_COUNT (ETNA_PM_QUERY_BASE + 33) - -#define ETNA_QUERY_TX_TOTAL_BILINEAR_REQUESTS (ETNA_PM_QUERY_BASE + 34) -#define ETNA_QUERY_TX_TOTAL_TRILINEAR_REQUESTS (ETNA_PM_QUERY_BASE + 35) -#define ETNA_QUERY_TX_TOTAL_DISCARDED_TEXTURE_REQUESTS (ETNA_PM_QUERY_BASE + 36) -#define ETNA_QUERY_TX_TOTAL_TEXTURE_REQUESTS (ETNA_PM_QUERY_BASE + 37) -#define ETNA_QUERY_TX_MEM_READ_COUNT (ETNA_PM_QUERY_BASE + 38) -#define ETNA_QUERY_TX_MEM_READ_IN_8B_COUNT (ETNA_PM_QUERY_BASE + 39) -#define ETNA_QUERY_TX_CACHE_MISS_COUNT (ETNA_PM_QUERY_BASE + 40) -#define ETNA_QUERY_TX_CACHE_HIT_TEXEL_COUNT (ETNA_PM_QUERY_BASE + 41) -#define ETNA_QUERY_TX_CACHE_MISS_TEXEL_COUNT (ETNA_PM_QUERY_BASE + 42) - -#define ETNA_QUERY_MC_TOTAL_READ_REQ_8B_FROM_PIPELINE (ETNA_PM_QUERY_BASE + 43) -#define ETNA_QUERY_MC_TOTAL_READ_REQ_8B_FROM_IP (ETNA_PM_QUERY_BASE + 44) -#define ETNA_QUERY_MC_TOTAL_WRITE_REQ_8B_FROM_PIPELINE (ETNA_PM_QUERY_BASE + 45) - -struct etna_pm_query { - struct etna_query base; - struct etna_perfmon_signal *signal; - struct etna_bo *bo; - uint32_t *data; - uint32_t sequence; - bool ready; -}; - -static inline struct etna_pm_query * -etna_pm_query(struct etna_query *q) -{ - return (struct etna_pm_query *)q; -} - -void -etna_pm_query_setup(struct etna_screen *screen); - -struct etna_query * -etna_pm_create_query(struct etna_context *ctx, unsigned query_type); - -int -etna_pm_get_driver_query_info(struct pipe_screen *pscreen, unsigned index, - struct pipe_driver_query_info *info); - -int -etna_pm_get_driver_query_group_info(struct pipe_screen *pscreen, - unsigned index, - struct pipe_driver_query_group_info *info); - -#endif diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_query_sw.c b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_query_sw.c index b9fc1cca2..6bcd04d82 100644 --- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_query_sw.c +++ b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_query_sw.c @@ -45,8 +45,8 @@ static uint64_t read_counter(struct etna_context *ctx, unsigned type) { switch (type) { - case PIPE_QUERY_PRIMITIVES_EMITTED: - return ctx->stats.prims_emitted; + case PIPE_QUERY_PRIMITIVES_GENERATED: + return ctx->stats.prims_generated; case ETNA_QUERY_DRAW_CALLS: return ctx->stats.draw_calls; case ETNA_QUERY_RS_OPERATIONS: @@ -56,14 +56,12 @@ read_counter(struct etna_context *ctx, unsigned type) return 0; } -static bool +static void etna_sw_begin_query(struct etna_context *ctx, struct etna_query *q) { struct etna_sw_query *sq = etna_sw_query(q); sq->begin_value = read_counter(ctx, q->type); - - return true; } static void @@ -99,7 +97,7 @@ etna_sw_create_query(struct etna_context *ctx, unsigned query_type) struct etna_query *q; switch (query_type) { - case PIPE_QUERY_PRIMITIVES_EMITTED: + case PIPE_QUERY_PRIMITIVES_GENERATED: case ETNA_QUERY_DRAW_CALLS: case ETNA_QUERY_RS_OPERATIONS: break; @@ -119,7 +117,7 @@ etna_sw_create_query(struct etna_context *ctx, unsigned query_type) } static const struct pipe_driver_query_info list[] = { - {"prims-emitted", PIPE_QUERY_PRIMITIVES_EMITTED, { 0 }}, + {"prims-generated", PIPE_QUERY_PRIMITIVES_GENERATED, { 0 }}, {"draw-calls", ETNA_QUERY_DRAW_CALLS, { 0 }}, {"rs-operations", ETNA_QUERY_RS_OPERATIONS, { 0 }}, }; diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_resource.c b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_resource.c index 124618ea4..4a992b5f6 100644 --- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_resource.c +++ b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_resource.c @@ -145,7 +145,7 @@ etna_screen_can_create_resource(struct pipe_screen *pscreen, const struct pipe_resource *templat) { struct etna_screen *screen = etna_screen(pscreen); - if (!translate_samples_to_xyscale(templat->nr_samples, NULL, NULL, NULL)) + if (!translate_samples_to_xyscale(templat->nr_samples, NULL, NULL)) return false; /* templat->bind is not set here, so we must use the minimum sizes */ @@ -204,8 +204,7 @@ static bool is_rs_align(struct etna_screen *screen, /* Create a new resource object, using the given template info */ struct pipe_resource * etna_resource_alloc(struct pipe_screen *pscreen, unsigned layout, - enum etna_resource_addressing_mode mode, uint64_t modifier, - const struct pipe_resource *templat) + uint64_t modifier, const struct pipe_resource *templat) { struct etna_screen *screen = etna_screen(pscreen); struct etna_resource *rsc; @@ -230,7 +229,7 @@ etna_resource_alloc(struct pipe_screen *pscreen, unsigned layout, } int msaa_xscale = 1, msaa_yscale = 1; - if (!translate_samples_to_xyscale(nr_samples, &msaa_xscale, &msaa_yscale, NULL)) { + if (!translate_samples_to_xyscale(nr_samples, &msaa_xscale, &msaa_yscale)) { /* Number of samples not supported */ return NULL; } @@ -299,9 +298,9 @@ etna_resource_alloc(struct pipe_screen *pscreen, unsigned layout, rsc->base.nr_samples = nr_samples; rsc->layout = layout; rsc->halign = halign; - rsc->addressing_mode = mode; pipe_reference_init(&rsc->base.reference, 1); + util_range_init(&rsc->valid_buffer_range); size = setup_miptree(rsc, paddingX, paddingY, msaa_xscale, msaa_yscale); @@ -339,58 +338,38 @@ etna_resource_create(struct pipe_screen *pscreen, const struct pipe_resource *templat) { struct etna_screen *screen = etna_screen(pscreen); - - /* Figure out what tiling and address mode to use -- for now, assume that - * texture cannot be linear. there is a capability LINEAR_TEXTURE_SUPPORT - * (supported on gc880 and gc2000 at least), but not sure how it works. - * Buffers always have LINEAR layout. + unsigned layout = ETNA_LAYOUT_TILED; + + /* At this point we don't know if the resource will be used as a texture, + * render target, or both, because gallium sets the bits whenever possible + * This matters because on some GPUs (GC2000) there is no tiling that is + * compatible with both TE and PE. + * + * We expect that depth/stencil buffers will always be used by PE (rendering), + * and any other non-scanout resource will be used as a texture at some point, + * So allocate a render-compatible base buffer for scanout/depthstencil buffers, + * and a texture-compatible base buffer in other cases + * */ - unsigned layout = ETNA_LAYOUT_LINEAR; - enum etna_resource_addressing_mode mode = ETNA_ADDRESSING_MODE_TILED; - - if (etna_resource_sampler_only(templat)) { - /* The buffer is only used for texturing, so create something - * directly compatible with the sampler. Such a buffer can - * never be rendered to. */ - layout = ETNA_LAYOUT_TILED; - - if (util_format_is_compressed(templat->format)) - layout = ETNA_LAYOUT_LINEAR; - } else if (templat->target != PIPE_BUFFER) { - bool want_multitiled = false; - bool want_supertiled = screen->specs.can_supertile; - - /* When this GPU supports single-buffer rendering, don't ever enable - * multi-tiling. This replicates the blob behavior on GC3000. - */ - if (!screen->specs.single_buffer) - want_multitiled = screen->specs.pixel_pipes > 1; - - /* Keep single byte blocksized resources as tiled, since we - * are unable to use the RS blit to de-tile them. However, - * if they're used as a render target or depth/stencil, they - * must be multi-tiled for GPUs with multiple pixel pipes. - * Ignore depth/stencil here, but it is an error for a render - * target. - */ - if (util_format_get_blocksize(templat->format) == 1 && - !(templat->bind & PIPE_BIND_DEPTH_STENCIL)) { - assert(!(templat->bind & PIPE_BIND_RENDER_TARGET && want_multitiled)); - want_multitiled = want_supertiled = false; - } - - layout = ETNA_LAYOUT_BIT_TILE; - if (want_multitiled) + if (templat->bind & (PIPE_BIND_SCANOUT | PIPE_BIND_DEPTH_STENCIL)) { + if (screen->specs.pixel_pipes > 1 && !screen->specs.single_buffer) layout |= ETNA_LAYOUT_BIT_MULTI; - if (want_supertiled) + if (screen->specs.can_supertile) layout |= ETNA_LAYOUT_BIT_SUPER; + } else if (VIV_FEATURE(screen, chipMinorFeatures2, SUPERTILED_TEXTURE) && + etna_resource_hw_tileable(screen->specs.use_blt, templat)) { + layout |= ETNA_LAYOUT_BIT_SUPER; } - if (templat->target == PIPE_TEXTURE_3D) + if ((templat->bind & PIPE_BIND_LINEAR) || /* linear base requested */ + templat->target == PIPE_BUFFER || /* buffer always linear */ + /* compressed textures don't use tiling, they have their own "tiles" */ + util_format_is_compressed(templat->format)) { layout = ETNA_LAYOUT_LINEAR; + } /* modifier is only used for scanout surfaces, so safe to use LINEAR here */ - return etna_resource_alloc(pscreen, layout, mode, DRM_FORMAT_MOD_LINEAR, templat); + return etna_resource_alloc(pscreen, layout, DRM_FORMAT_MOD_LINEAR, templat); } enum modifier_priority { @@ -470,31 +449,22 @@ etna_resource_create_modifiers(struct pipe_screen *pscreen, */ tmpl.bind |= PIPE_BIND_SCANOUT; - return etna_resource_alloc(pscreen, modifier_to_layout(modifier), - ETNA_ADDRESSING_MODE_TILED, modifier, &tmpl); + return etna_resource_alloc(pscreen, modifier_to_layout(modifier), modifier, &tmpl); } static void etna_resource_changed(struct pipe_screen *pscreen, struct pipe_resource *prsc) { - struct etna_resource *res = etna_resource(prsc); - - if (res->external) - etna_resource(res->external)->seqno++; - else - res->seqno++; + etna_resource(prsc)->seqno++; } static void etna_resource_destroy(struct pipe_screen *pscreen, struct pipe_resource *prsc) { - struct etna_screen *screen = etna_screen(pscreen); struct etna_resource *rsc = etna_resource(prsc); - mtx_lock(&screen->lock); - _mesa_set_remove_key(screen->used_resources, rsc); + assert(!_mesa_set_next_entry(rsc->pending_ctx, NULL)); _mesa_set_destroy(rsc->pending_ctx, NULL); - mtx_unlock(&screen->lock); if (rsc->bo) etna_bo_del(rsc->bo); @@ -505,8 +475,10 @@ etna_resource_destroy(struct pipe_screen *pscreen, struct pipe_resource *prsc) if (rsc->scanout) renderonly_scanout_destroy(rsc->scanout, etna_screen(pscreen)->ro); + util_range_destroy(&rsc->valid_buffer_range); + pipe_resource_reference(&rsc->texture, NULL); - pipe_resource_reference(&rsc->external, NULL); + pipe_resource_reference(&rsc->render, NULL); for (unsigned i = 0; i < ETNA_NUM_LOD; i++) FREE(rsc->levels[i].patch_offsets); @@ -523,7 +495,6 @@ etna_resource_from_handle(struct pipe_screen *pscreen, struct etna_resource *rsc; struct etna_resource_level *level; struct pipe_resource *prsc; - struct pipe_resource *ptiled = NULL; DBG("target=%d, format=%s, %ux%ux%u, array_size=%u, last_level=%u, " "nr_samples=%u, usage=%u, bind=%x, flags=%x", @@ -541,6 +512,7 @@ etna_resource_from_handle(struct pipe_screen *pscreen, *prsc = *tmpl; pipe_reference_init(&prsc->reference, 1); + util_range_init(&rsc->valid_buffer_range); prsc->screen = pscreen; rsc->bo = etna_screen_bo_from_handle(pscreen, handle, &level->stride); @@ -550,8 +522,6 @@ etna_resource_from_handle(struct pipe_screen *pscreen, rsc->seqno = 1; rsc->layout = modifier_to_layout(handle->modifier); rsc->halign = TEXTURE_HALIGN_FOUR; - rsc->addressing_mode = ETNA_ADDRESSING_MODE_TILED; - level->width = tmpl->width0; level->height = tmpl->height0; @@ -594,35 +564,10 @@ etna_resource_from_handle(struct pipe_screen *pscreen, if (!rsc->pending_ctx) goto fail; - if (rsc->layout == ETNA_LAYOUT_LINEAR) { - /* - * Both sampler and pixel pipes can't handle linear, create a compatible - * base resource, where we can attach the imported buffer as an external - * resource. - */ - struct pipe_resource tiled_templat = *tmpl; - - /* - * Remove BIND_SCANOUT to avoid recursion, as etna_resource_create uses - * this function to import the scanout buffer and get a tiled resource. - */ - tiled_templat.bind &= ~PIPE_BIND_SCANOUT; - - ptiled = etna_resource_create(pscreen, &tiled_templat); - if (!ptiled) - goto fail; - - etna_resource(ptiled)->external = prsc; - - return ptiled; - } - return prsc; fail: etna_resource_destroy(pscreen, prsc); - if (ptiled) - etna_resource_destroy(pscreen, ptiled); return NULL; } @@ -637,13 +582,6 @@ etna_resource_get_handle(struct pipe_screen *pscreen, /* Scanout is always attached to the base resource */ struct renderonly_scanout *scanout = rsc->scanout; - /* - * External resources are preferred, so a import->export chain of - * render/sampler incompatible buffers yield the same handle. - */ - if (rsc->external) - rsc = etna_resource(rsc->external); - handle->stride = rsc->levels[0].stride; handle->offset = rsc->levels[0].offset; handle->modifier = layout_to_modifier(rsc->layout); @@ -665,51 +603,80 @@ etna_resource_get_handle(struct pipe_screen *pscreen, } } +enum etna_resource_status +etna_resource_get_status(struct etna_context *ctx, struct etna_resource *rsc) +{ + enum etna_resource_status newstatus = 0; + + set_foreach(rsc->pending_ctx, entry) { + struct etna_context *extctx = (struct etna_context *)entry->key; + + set_foreach(extctx->used_resources_read, entry2) { + struct etna_resource *rsc2 = (struct etna_resource *)entry2->key; + if (ctx == extctx || rsc2 != rsc) + continue; + + newstatus |= ETNA_PENDING_READ; + } + + set_foreach(extctx->used_resources_write, entry2) { + struct etna_resource *rsc2 = (struct etna_resource *)entry2->key; + if (ctx == extctx || rsc2 != rsc) + continue; + + newstatus |= ETNA_PENDING_WRITE; + } + } + + return newstatus; +} + void etna_resource_used(struct etna_context *ctx, struct pipe_resource *prsc, enum etna_resource_status status) { - struct etna_screen *screen = ctx->screen; + struct pipe_resource *referenced = NULL; struct etna_resource *rsc; if (!prsc) return; + mtx_lock(&ctx->lock); + rsc = etna_resource(prsc); - mtx_lock(&screen->lock); + set_foreach(rsc->pending_ctx, entry) { + struct etna_context *extctx = (struct etna_context *)entry->key; + struct pipe_context *pctx = &extctx->base; - /* - * if we are pending read or write by any other context or - * if reading a resource pending a write, then - * flush all the contexts to maintain coherency - */ - if (((status & ETNA_PENDING_WRITE) && rsc->status) || - ((status & ETNA_PENDING_READ) && (rsc->status & ETNA_PENDING_WRITE))) { - set_foreach(rsc->pending_ctx, entry) { - struct etna_context *extctx = (struct etna_context *)entry->key; - struct pipe_context *pctx = &extctx->base; + set_foreach(extctx->used_resources_read, entry2) { + struct etna_resource *rsc2 = (struct etna_resource *)entry2->key; + if (ctx == extctx || rsc2 != rsc) + continue; - if (extctx == ctx) + if (status & ETNA_PENDING_WRITE) + pctx->flush(pctx, NULL, 0); + } + + set_foreach(extctx->used_resources_write, entry2) { + struct etna_resource *rsc2 = (struct etna_resource *)entry2->key; + if (ctx == extctx || rsc2 != rsc) continue; pctx->flush(pctx, NULL, 0); - /* It's safe to clear the status here. If we need to flush it means - * either another context had the resource in exclusive (write) use, - * or we transition the resource to exclusive use in our context. - * In both cases the new status accurately reflects the resource use - * after the flush. - */ - rsc->status = 0; } } - rsc->status |= status; + rsc->status = status; - _mesa_set_add(screen->used_resources, rsc); - _mesa_set_add(rsc->pending_ctx, ctx); + if (!_mesa_set_search(rsc->pending_ctx, ctx)) { + pipe_resource_reference(&referenced, prsc); + _mesa_set_add((status & ETNA_PENDING_READ) ? + ctx->used_resources_read : ctx->used_resources_write, rsc); + _mesa_set_add(rsc->pending_ctx, ctx); + } - mtx_unlock(&screen->lock); + mtx_unlock(&ctx->lock); } bool diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_resource.h b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_resource.h index 90e04f515..1da0315ab 100644 --- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_resource.h +++ b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_resource.h @@ -30,9 +30,11 @@ #include "etnaviv_internal.h" #include "etnaviv_tiling.h" #include "pipe/p_state.h" +#include "util/format/u_format.h" #include "util/list.h" #include "util/set.h" #include "util/u_helpers.h" +#include "util/u_range.h" struct etna_context; struct pipe_screen; @@ -50,7 +52,7 @@ struct etna_resource_level { uint32_t ts_offset; uint32_t ts_layer_stride; uint32_t ts_size; - uint32_t clear_value; /* clear value of resource level (mainly for TS) */ + uint64_t clear_value; /* clear value of resource level (mainly for TS) */ bool ts_valid; uint8_t ts_mode; int8_t ts_compress_fmt; /* COLOR_COMPRESSION_FORMAT_* (-1 = disable) */ @@ -60,11 +62,6 @@ struct etna_resource_level { struct util_dynarray *patch_offsets; }; -enum etna_resource_addressing_mode { - ETNA_ADDRESSING_MODE_TILED = 0, - ETNA_ADDRESSING_MODE_LINEAR, -}; - /* status of queued up but not flushed reads and write operations. * In _transfer_map() we need to know if queued up rendering needs * to be flushed to preserve the order of cpu and gpu access. */ @@ -82,7 +79,6 @@ struct etna_resource { /* only lod 0 used for non-texture buffers */ /* Layout for surface (tiled, multitiled, split tiled, ...) */ enum etna_surface_layout layout; - enum etna_resource_addressing_mode addressing_mode; /* Horizontal alignment for texture unit (TEXTURE_HALIGN_*) */ unsigned halign; struct etna_bo *bo; /* Surface video memory */ @@ -90,13 +86,13 @@ struct etna_resource { struct etna_resource_level levels[ETNA_NUM_LOD]; - /* When we are rendering to a texture, we need a differently tiled resource */ + /* buffer range that has been initialized */ + struct util_range valid_buffer_range; + + /* for when TE doesn't support the base layout */ struct pipe_resource *texture; - /* - * If imported resources have an render/sampler incompatible tiling, we keep - * them as an external resource, which is blitted as needed. - */ - struct pipe_resource *external; + /* for when PE doesn't support the base layout */ + struct pipe_resource *render; enum etna_resource_status status; @@ -137,12 +133,26 @@ etna_resource_sampler_only(const struct pipe_resource *pres) PIPE_BIND_SAMPLER_VIEW; } +static inline bool +etna_resource_hw_tileable(bool use_blt, const struct pipe_resource *pres) +{ + if (use_blt) + return true; + + /* RS can only tile 16bpp or 32bpp formats */ + return util_format_get_blocksize(pres->format) == 2 || + util_format_get_blocksize(pres->format) == 4; +} + static inline struct etna_resource * etna_resource(struct pipe_resource *p) { return (struct etna_resource *)p; } +enum etna_resource_status +etna_resource_get_status(struct etna_context *ctx, struct etna_resource *rsc); + void etna_resource_used(struct etna_context *ctx, struct pipe_resource *prsc, enum etna_resource_status status); @@ -169,8 +179,7 @@ etna_screen_resource_alloc_ts(struct pipe_screen *pscreen, struct pipe_resource * etna_resource_alloc(struct pipe_screen *pscreen, unsigned layout, - enum etna_resource_addressing_mode mode, uint64_t modifier, - const struct pipe_resource *templat); + uint64_t modifier, const struct pipe_resource *templat); void etna_resource_screen_init(struct pipe_screen *pscreen); diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_rs.c b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_rs.c index 0ac9b67f5..bcd11e05a 100644 --- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_rs.c +++ b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_rs.c @@ -50,10 +50,27 @@ #include <assert.h> +/* return a RS "compatible" format for use when copying */ +static uint32_t +etna_compatible_rs_format(enum pipe_format fmt) +{ + /* YUYV and UYVY are blocksize 4, but 2 bytes per pixel */ + if (fmt == PIPE_FORMAT_YUYV || fmt == PIPE_FORMAT_UYVY) + return RS_FORMAT_A4R4G4B4; + + switch (util_format_get_blocksize(fmt)) { + case 2: return RS_FORMAT_A4R4G4B4; + case 4: return RS_FORMAT_A8R8G8B8; + default: return ETNA_NO_MATCH; + } +} + void etna_compile_rs_state(struct etna_context *ctx, struct compiled_rs_state *cs, const struct rs_state *rs) { + struct etna_screen *screen = ctx->screen; + memset(cs, 0, sizeof(*cs)); /* TILED and SUPERTILED layout have their strides multiplied with 4 in RS */ @@ -89,7 +106,7 @@ etna_compile_rs_state(struct etna_context *ctx, struct compiled_rs_state *cs, * destination buffer respectively. This will be overridden below as * necessary for the multi-pipe, multi-tiled case. */ - for (unsigned pipe = 0; pipe < ctx->specs.pixel_pipes; ++pipe) { + for (unsigned pipe = 0; pipe < screen->specs.pixel_pipes; ++pipe) { cs->source[pipe].bo = rs->source; cs->source[pipe].offset = rs->source_offset; cs->source[pipe].flags = ETNA_RELOC_READ; @@ -116,7 +133,7 @@ etna_compile_rs_state(struct etna_context *ctx, struct compiled_rs_state *cs, VIVS_RS_WINDOW_SIZE_HEIGHT(rs->height); /* use dual pipe mode when required */ - if (!ctx->specs.single_buffer && ctx->specs.pixel_pipes == 2 && !(rs->height & 7)) { + if (!screen->specs.single_buffer && screen->specs.pixel_pipes == 2 && !(rs->height & 7)) { cs->RS_WINDOW_SIZE = VIVS_RS_WINDOW_SIZE_WIDTH(rs->width) | VIVS_RS_WINDOW_SIZE_HEIGHT(rs->height / 2); cs->RS_PIPE_OFFSET[1] = VIVS_RS_PIPE_OFFSET_X(0) | VIVS_RS_PIPE_OFFSET_Y(rs->height / 2); @@ -135,7 +152,7 @@ etna_compile_rs_state(struct etna_context *ctx, struct compiled_rs_state *cs, /* If source the same as destination, and the hardware supports this, * do an in-place resolve to fill in unrendered tiles. */ - if (ctx->specs.single_buffer && rs->source == rs->dest && + if (screen->specs.single_buffer && rs->source == rs->dest && rs->source_offset == rs->dest_offset && rs->source_format == rs->dest_format && rs->source_tiling == rs->dest_tiling && @@ -250,8 +267,9 @@ etna_submit_rs_state(struct etna_context *ctx, /* Generate clear command for a surface (non-fast clear case) */ void etna_rs_gen_clear_surface(struct etna_context *ctx, struct etna_surface *surf, - uint32_t clear_value) + uint64_t clear_value) { + struct etna_screen *screen = ctx->screen; struct etna_resource *dst = etna_resource(surf->base.texture); uint32_t format; @@ -263,7 +281,7 @@ etna_rs_gen_clear_surface(struct etna_context *ctx, struct etna_surface *surf, format = RS_FORMAT_A8R8G8B8; break; case 64: - assert(ctx->specs.halti >= 2); + assert(screen->specs.halti >= 2); format = RS_FORMAT_64BPP_CLEAR; break; default: @@ -286,7 +304,7 @@ etna_rs_gen_clear_surface(struct etna_context *ctx, struct etna_surface *surf, .dither = {0xffffffff, 0xffffffff}, .width = surf->surf.padded_width, /* These must be padded to 16x4 if !LINEAR, otherwise RS will hang */ .height = surf->surf.padded_height, - .clear_value = {clear_value}, + .clear_value = {clear_value, clear_value >> 32, clear_value, clear_value >> 32}, .clear_mode = VIVS_RS_CLEAR_CONTROL_MODE_ENABLED1, .clear_bits = 0xffff }); @@ -298,10 +316,11 @@ etna_blit_clear_color_rs(struct pipe_context *pctx, struct pipe_surface *dst, { struct etna_context *ctx = etna_context(pctx); struct etna_surface *surf = etna_surface(dst); - uint32_t new_clear_value = etna_clear_blit_pack_rgba(surf->base.format, color->f); + uint64_t new_clear_value = etna_clear_blit_pack_rgba(surf->base.format, color); if (surf->surf.ts_size) { /* TS: use precompiled clear command */ ctx->framebuffer.TS_COLOR_CLEAR_VALUE = new_clear_value; + ctx->framebuffer.TS_COLOR_CLEAR_VALUE_EXT = new_clear_value >> 32; if (VIV_FEATURE(ctx->screen, chipMinorFeatures1, AUTO_DISABLE)) { /* Set number of color tiles to be filled */ @@ -388,10 +407,11 @@ etna_blit_clear_zs_rs(struct pipe_context *pctx, struct pipe_surface *dst, } static void -etna_clear_rs(struct pipe_context *pctx, unsigned buffers, +etna_clear_rs(struct pipe_context *pctx, unsigned buffers, const struct pipe_scissor_state *scissor_state, const union pipe_color_union *color, double depth, unsigned stencil) { struct etna_context *ctx = etna_context(pctx); + mtx_lock(&ctx->lock); /* Flush color and depth cache before clearing anything. * This is especially important when coming from another surface, as @@ -437,6 +457,7 @@ etna_clear_rs(struct pipe_context *pctx, unsigned buffers, etna_blit_clear_zs_rs(pctx, ctx->framebuffer_s.zsbuf, buffers, depth, stencil); etna_stall(ctx->stream, SYNC_RECIPIENT_RA, SYNC_RECIPIENT_PE); + mtx_unlock(&ctx->lock); } static bool @@ -519,11 +540,12 @@ etna_get_rs_alignment_mask(const struct etna_context *ctx, const enum etna_surface_layout layout, unsigned int *width_mask, unsigned int *height_mask) { + struct etna_screen *screen = ctx->screen; unsigned int h_align, w_align; if (layout & ETNA_LAYOUT_BIT_SUPER) { w_align = 64; - h_align = 64 * ctx->specs.pixel_pipes; + h_align = 64 * screen->specs.pixel_pipes; } else { w_align = ETNA_RS_WIDTH_MASK + 1; h_align = ETNA_RS_HEIGHT_MASK + 1; @@ -533,6 +555,30 @@ etna_get_rs_alignment_mask(const struct etna_context *ctx, *height_mask = h_align -1; } +static bool msaa_config(const struct pipe_resource *src, + const struct pipe_resource *dst, + int *msaa_xscale, + int *msaa_yscale) +{ + int src_xscale = 1, src_yscale = 1; + int dst_xscale = 1, dst_yscale = 1; + + assert(src->nr_samples <= 4); + assert(dst->nr_samples <= 4); + + translate_samples_to_xyscale(src->nr_samples, &src_xscale, &src_yscale); + translate_samples_to_xyscale(dst->nr_samples, &dst_xscale, &dst_yscale); + + /* RS does not support upscaling */ + if ((src_xscale < dst_xscale) || (src_yscale < dst_yscale)) + return false; + + *msaa_xscale = src_xscale - dst_xscale + 1; + *msaa_yscale = src_yscale - dst_yscale + 1; + + return true; +} + static bool etna_try_rs_blit(struct pipe_context *pctx, const struct pipe_blit_info *blit_info) @@ -547,8 +593,10 @@ etna_try_rs_blit(struct pipe_context *pctx, assert(blit_info->src.level <= src->base.last_level); assert(blit_info->dst.level <= dst->base.last_level); - if (!translate_samples_to_xyscale(src->base.nr_samples, &msaa_xscale, &msaa_yscale, NULL)) + if (!msaa_config(&src->base, &dst->base, &msaa_xscale, &msaa_yscale)) { + DBG("upsampling not supported"); return false; + } /* The width/height are in pixels; they do not change as a result of * multi-sampling. So, when blitting from a 4x multisampled surface @@ -569,18 +617,19 @@ etna_try_rs_blit(struct pipe_context *pctx, return false; } - unsigned src_format = blit_info->src.format; - unsigned dst_format = blit_info->dst.format; + /* Only support same format (used tiling/detiling) blits for now. + * TODO: figure out which different-format blits are possible and test them + * - fail if swizzle needed + * - avoid trying to convert between float/int formats? + */ + if (blit_info->src.format != blit_info->dst.format) + return false; - /* for a copy with same dst/src format, we can use a different format */ - if (translate_rs_format(src_format) == ETNA_NO_MATCH && - src_format == dst_format) { - src_format = dst_format = etna_compatible_rs_format(src_format); - } + uint32_t format = etna_compatible_rs_format(blit_info->dst.format); + if (format == ETNA_NO_MATCH) + return false; - if (translate_rs_format(src_format) == ETNA_NO_MATCH || - translate_rs_format(dst_format) == ETNA_NO_MATCH || - blit_info->scissor_enable || + if (blit_info->scissor_enable || blit_info->dst.box.depth != blit_info->src.box.depth || blit_info->dst.box.depth != 1) { return false; @@ -647,6 +696,8 @@ etna_try_rs_blit(struct pipe_context *pctx, width & (w_align - 1) || height & (h_align - 1)) goto manual; + mtx_lock(&ctx->lock); + /* Always flush color and depth cache together before resolving. This works * around artifacts that appear in some cases when scanning out a texture * directly after it has been rendered to, such as rendering an animated web @@ -696,6 +747,7 @@ etna_try_rs_blit(struct pipe_context *pctx, etna_set_state_reloc(ctx->stream, VIVS_TS_COLOR_SURFACE_BASE, &reloc); etna_set_state(ctx->stream, VIVS_TS_COLOR_CLEAR_VALUE, src_lev->clear_value); + etna_set_state(ctx->stream, VIVS_TS_COLOR_CLEAR_VALUE_EXT, src_lev->clear_value >> 32); source_ts_valid = true; } else { @@ -705,7 +757,7 @@ etna_try_rs_blit(struct pipe_context *pctx, /* Kick off RS here */ etna_compile_rs_state(ctx, ©_to_screen, &(struct rs_state) { - .source_format = translate_rs_format(src_format), + .source_format = format, .source_tiling = src->layout, .source = src->bo, .source_offset = src_offset, @@ -714,7 +766,7 @@ etna_try_rs_blit(struct pipe_context *pctx, .source_padded_height = src_lev->padded_height, .source_ts_valid = source_ts_valid, .source_ts_compressed = src_lev->ts_compress_fmt >= 0, - .dest_format = translate_rs_format(dst_format), + .dest_format = format, .dest_tiling = dst->layout, .dest = dst->bo, .dest_offset = dst_offset, @@ -736,6 +788,7 @@ etna_try_rs_blit(struct pipe_context *pctx, dst->seqno++; dst_lev->ts_valid = false; ctx->dirty |= ETNA_DIRTY_DERIVE_TS; + mtx_unlock(&ctx->lock); return true; @@ -750,7 +803,7 @@ manual: return false; } -static void +static bool etna_blit_rs(struct pipe_context *pctx, const struct pipe_blit_info *blit_info) { /* This is a more extended version of resource_copy_region */ @@ -767,43 +820,24 @@ etna_blit_rs(struct pipe_context *pctx, const struct pipe_blit_info *blit_info) * * For the rest, fall back to util_blitter * XXX this goes wrong when source surface is supertiled. */ - struct etna_context *ctx = etna_context(pctx); - struct pipe_blit_info info = *blit_info; - if (info.src.resource->nr_samples > 1 && - info.dst.resource->nr_samples <= 1 && - !util_format_is_depth_or_stencil(info.src.resource->format) && - !util_format_is_pure_integer(info.src.resource->format)) { + if (blit_info->src.resource->nr_samples > 1 && + blit_info->dst.resource->nr_samples <= 1 && + !util_format_is_depth_or_stencil(blit_info->src.resource->format) && + !util_format_is_pure_integer(blit_info->src.resource->format)) { DBG("color resolve unimplemented"); - return; - } - - if (etna_try_rs_blit(pctx, blit_info)) - return; - - if (util_try_blit_via_copy_region(pctx, blit_info)) - return; - - if (info.mask & PIPE_MASK_S) { - DBG("cannot blit stencil, skipping"); - info.mask &= ~PIPE_MASK_S; - } - - if (!util_blitter_is_blit_supported(ctx->blitter, &info)) { - DBG("blit unsupported %s -> %s", - util_format_short_name(info.src.resource->format), - util_format_short_name(info.dst.resource->format)); - return; + return false; } - etna_blit_save_state(ctx); - util_blitter_blit(ctx->blitter, &info); + return etna_try_rs_blit(pctx, blit_info); } void etna_clear_blit_rs_init(struct pipe_context *pctx) { + struct etna_context *ctx = etna_context(pctx); + DBG("etnaviv: Using RS blit engine"); pctx->clear = etna_clear_rs; - pctx->blit = etna_blit_rs; + ctx->blit = etna_blit_rs; } diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_screen.c b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_screen.c index c1cc56bc3..6b3566884 100644 --- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_screen.c +++ b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_screen.c @@ -73,6 +73,7 @@ static const struct debug_named_value debug_options[] = { {"shaderdb", ETNA_DBG_SHADERDB, "Enable shaderdb output"}, {"no_singlebuffer",ETNA_DBG_NO_SINGLEBUF, "Disable single buffer feature"}, {"nir", ETNA_DBG_NIR, "use new NIR compiler"}, + {"deqp", ETNA_DBG_DEQP, "Hacks to run dEQP GLES3 tests"}, /* needs MESA_GLES_VERSION_OVERRIDE=3.0 */ DEBUG_NAMED_VALUE_END }; @@ -84,9 +85,6 @@ etna_screen_destroy(struct pipe_screen *pscreen) { struct etna_screen *screen = etna_screen(pscreen); - _mesa_set_destroy(screen->used_resources, NULL); - mtx_destroy(&screen->lock); - if (screen->perfmon) etna_perfmon_del(screen->perfmon); @@ -136,7 +134,6 @@ etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) switch (param) { /* Supported features (boolean caps). */ - case PIPE_CAP_ANISOTROPIC_FILTER: case PIPE_CAP_POINT_SPRITE: case PIPE_CAP_BLEND_EQUATION_SEPARATE: case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: @@ -152,6 +149,9 @@ etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_TGSI_TEXCOORD: case PIPE_CAP_VERTEX_COLOR_UNCLAMPED: case PIPE_CAP_MIXED_COLOR_DEPTH_BITS: + case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES: + case PIPE_CAP_STRING_MARKER: + case PIPE_CAP_SHAREABLE_SHADERS: return 1; case PIPE_CAP_NATIVE_FENCE_FD: return screen->drm_version >= ETNA_DRM_VERSION_FENCE_FD; @@ -171,6 +171,7 @@ etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) return true; /* VIV_FEATURE(priv->dev, chipMinorFeatures1, NON_POWER_OF_TWO); */ + case PIPE_CAP_ANISOTROPIC_FILTER: case PIPE_CAP_TEXTURE_SWIZZLE: case PIPE_CAP_PRIMITIVE_RESTART: return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0); @@ -182,6 +183,8 @@ etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) return 0; /* Stream output. */ + case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS: + return DBG_ENABLED(ETNA_DBG_DEQP) ? 4 : 0; case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS: case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS: return 0; @@ -190,8 +193,15 @@ etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) return 128; case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET: return 255; + case PIPE_CAP_MAX_VERTEX_BUFFERS: + return screen->specs.stream_count; + case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: + return VIV_FEATURE(screen, chipMinorFeatures4, HALTI2); + /* Texturing. */ + case PIPE_CAP_TEXTURE_SHADOW_MAP: + return DBG_ENABLED(ETNA_DBG_NIR) && screen->specs.halti >= 2; case PIPE_CAP_MAX_TEXTURE_2D_SIZE: case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: /* TODO: verify */ return screen->specs.max_texture_size; @@ -210,7 +220,7 @@ etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_MAX_TEXEL_OFFSET: return 7; case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: - return VIV_FEATURE(screen, chipMinorFeatures2, SEAMLESS_CUBE_MAP); + return screen->specs.seamless_cube_map; /* Timer queries. */ case PIPE_CAP_OCCLUSION_QUERY: @@ -221,6 +231,22 @@ etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) /* Preferences */ case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER: return 0; + case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET: { + /* etnaviv is being run on systems as small as 256MB total RAM so + * we need to provide a sane value for such a device. Limit the + * memory budget to min(~3% of pyhiscal memory, 64MB). + * + * a simple divison by 32 provides the numbers we want. + * 256MB / 32 = 8MB + * 2048MB / 32 = 64MB + */ + uint64_t system_memory; + + if (!os_get_total_physical_memory(&system_memory)) + system_memory = (uint64_t)4096 << 20; + + return MIN2(system_memory / 32, 64 * 1024 * 1024); + } case PIPE_CAP_MAX_VARYINGS: return screen->specs.max_varyings; @@ -272,6 +298,10 @@ etna_screen_get_shader_param(struct pipe_screen *pscreen, enum pipe_shader_cap param) { struct etna_screen *screen = etna_screen(pscreen); + bool ubo_enable = screen->specs.halti >= 2 && DBG_ENABLED(ETNA_DBG_NIR); + + if (DBG_ENABLED(ETNA_DBG_DEQP)) + ubo_enable = true; switch (shader) { case PIPE_SHADER_FRAGMENT: @@ -307,7 +337,7 @@ etna_screen_get_shader_param(struct pipe_screen *pscreen, case PIPE_SHADER_CAP_MAX_TEMPS: return 64; /* Max native temporaries. */ case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: - return 1; + return ubo_enable ? ETNA_MAX_CONST_BUF : 1; case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: return 1; case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: @@ -319,10 +349,11 @@ etna_screen_get_shader_param(struct pipe_screen *pscreen, return 0; case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED: return VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG); - case PIPE_SHADER_CAP_INTEGERS: case PIPE_SHADER_CAP_INT64_ATOMICS: case PIPE_SHADER_CAP_FP16: return 0; + case PIPE_SHADER_CAP_INTEGERS: + return DBG_ENABLED(ETNA_DBG_NIR) && screen->specs.halti >= 2; case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS: return shader == PIPE_SHADER_FRAGMENT @@ -331,6 +362,8 @@ etna_screen_get_shader_param(struct pipe_screen *pscreen, case PIPE_SHADER_CAP_PREFERRED_IR: return DBG_ENABLED(ETNA_DBG_NIR) ? PIPE_SHADER_IR_NIR : PIPE_SHADER_IR_TGSI; case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: + if (ubo_enable) + return 16384; /* 16384 so state tracker enables UBOs */ return shader == PIPE_SHADER_FRAGMENT ? screen->specs.max_ps_uniforms * sizeof(float[4]) : screen->specs.max_vs_uniforms * sizeof(float[4]); @@ -350,7 +383,6 @@ etna_screen_get_shader_param(struct pipe_screen *pscreen, case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS: - case PIPE_SHADER_CAP_SCALAR_ISA: return 0; } @@ -403,6 +435,14 @@ gpu_supports_texture_format(struct etna_screen *screen, uint32_t fmt, supported = screen->specs.tex_astc; } + if (util_format_is_snorm(format)) + supported = VIV_FEATURE(screen, chipMinorFeatures2, HALTI1); + + if (format != PIPE_FORMAT_S8_UINT_Z24_UNORM && + (util_format_is_pure_integer(format) || util_format_is_float(format))) + supported = VIV_FEATURE(screen, chipMinorFeatures4, HALTI2); + + if (!supported) return false; @@ -413,6 +453,54 @@ gpu_supports_texture_format(struct etna_screen *screen, uint32_t fmt, } static bool +gpu_supports_render_format(struct etna_screen *screen, enum pipe_format format, + unsigned sample_count) +{ + const uint32_t fmt = translate_pe_format(format); + + if (fmt == ETNA_NO_MATCH) + return false; + + /* MSAA is broken */ + if (sample_count > 1) + return false; + + if (format == PIPE_FORMAT_R8_UNORM) + return VIV_FEATURE(screen, chipMinorFeatures5, HALTI5); + + /* figure out 8bpp RS clear to enable these formats */ + if (format == PIPE_FORMAT_R8_SINT || format == PIPE_FORMAT_R8_UINT) + return VIV_FEATURE(screen, chipMinorFeatures5, HALTI5); + + if (util_format_is_srgb(format)) + return VIV_FEATURE(screen, chipMinorFeatures5, HALTI3); + + if (util_format_is_pure_integer(format) || util_format_is_float(format)) + return VIV_FEATURE(screen, chipMinorFeatures4, HALTI2); + + if (format == PIPE_FORMAT_R8G8_UNORM) + return VIV_FEATURE(screen, chipMinorFeatures4, HALTI2); + + /* any other extended format is HALTI0 (only R10G10B10A2?) */ + if (fmt >= PE_FORMAT_R16F) + return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0); + + return true; +} + +static bool +gpu_supports_vertex_format(struct etna_screen *screen, enum pipe_format format) +{ + if (translate_vertex_format_type(format) == ETNA_NO_MATCH) + return false; + + if (util_format_is_pure_integer(format)) + return VIV_FEATURE(screen, chipMinorFeatures4, HALTI2); + + return true; +} + +static bool etna_screen_is_format_supported(struct pipe_screen *pscreen, enum pipe_format format, enum pipe_texture_target target, @@ -430,19 +518,8 @@ etna_screen_is_format_supported(struct pipe_screen *pscreen, return false; if (usage & PIPE_BIND_RENDER_TARGET) { - /* if render target, must be RS-supported format */ - if (translate_rs_format(format) != ETNA_NO_MATCH) { - /* Validate MSAA; number of samples must be allowed, and render target - * must have MSAA'able format. */ - if (sample_count > 1) { - if (translate_samples_to_xyscale(sample_count, NULL, NULL, NULL) && - translate_ts_format(format) != ETNA_NO_MATCH) { - allowed |= PIPE_BIND_RENDER_TARGET; - } - } else { - allowed |= PIPE_BIND_RENDER_TARGET; - } - } + if (gpu_supports_render_format(screen, format, sample_count)) + allowed |= PIPE_BIND_RENDER_TARGET; } if (usage & PIPE_BIND_DEPTH_STENCIL) { @@ -461,7 +538,7 @@ etna_screen_is_format_supported(struct pipe_screen *pscreen, } if (usage & PIPE_BIND_VERTEX_BUFFER) { - if (translate_vertex_format_type(format) != ETNA_NO_MATCH) + if (gpu_supports_vertex_format(screen, format)) allowed |= PIPE_BIND_VERTEX_BUFFER; } @@ -618,6 +695,12 @@ etna_get_specs(struct etna_screen *screen) } screen->specs.num_constants = val; + if (etna_gpu_get_param(screen->gpu, ETNA_GPU_NUM_VARYINGS, &val)) { + DBG("could not get ETNA_GPU_NUM_VARYINGS"); + goto fail; + } + screen->specs.max_varyings = MAX2(val, ETNA_NUM_VARYINGS); + /* Figure out gross GPU architecture. See rnndb/common.xml for a specific * description of the differences. */ if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI5)) @@ -653,6 +736,10 @@ etna_get_specs(struct etna_screen *screen) screen->specs.vertex_sampler_offset = 8; screen->specs.fragment_sampler_count = 8; screen->specs.vertex_sampler_count = 4; + + if (screen->model == 0x400) + screen->specs.vertex_sampler_count = 0; + screen->specs.vs_need_z_div = screen->model < 0x1000 && screen->model != 0x880; screen->specs.has_sin_cos_sqrt = @@ -669,6 +756,9 @@ etna_get_specs(struct etna_screen *screen) VIV_FEATURE(screen, chipMinorFeatures4, HALTI2); screen->specs.v4_compression = VIV_FEATURE(screen, chipMinorFeatures6, V4_COMPRESSION); + screen->specs.seamless_cube_map = + (screen->model != 0x880) && /* Seamless cubemap is broken on GC880? */ + VIV_FEATURE(screen, chipMinorFeatures2, SEAMLESS_CUBE_MAP); if (screen->specs.halti >= 5) { /* GC7000 - this core must load shaders from memory. */ @@ -705,22 +795,14 @@ etna_get_specs(struct etna_screen *screen) } if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0)) { - screen->specs.max_varyings = 12; screen->specs.vertex_max_elements = 16; } else { - screen->specs.max_varyings = 8; /* Etna_viv documentation seems confused over the correct value * here so choose the lower to be safe: HALTI0 says 16 i.s.o. * 10, but VERTEX_ELEMENT_CONFIG register says 16 i.s.o. 12. */ screen->specs.vertex_max_elements = 10; } - /* Etna_viv documentation does not indicate where varyings above 8 are - * stored. Moreover, if we are passed more than 8 varyings, we will - * walk off the end of some arrays. Limit the maximum number of varyings. */ - if (screen->specs.max_varyings > ETNA_NUM_VARYINGS) - screen->specs.max_varyings = ETNA_NUM_VARYINGS; - etna_determine_uniform_limits(screen); if (screen->specs.halti >= 5) { @@ -752,7 +834,8 @@ etna_get_specs(struct etna_screen *screen) if (screen->specs.single_buffer) DBG("etnaviv: Single buffer mode enabled with %d pixel pipes", screen->specs.pixel_pipes); - screen->specs.tex_astc = VIV_FEATURE(screen, chipMinorFeatures4, TEXTURE_ASTC); + screen->specs.tex_astc = VIV_FEATURE(screen, chipMinorFeatures4, TEXTURE_ASTC) && + !VIV_FEATURE(screen, chipMinorFeatures6, NO_ASTC); screen->specs.use_blt = VIV_FEATURE(screen, chipMinorFeatures5, BLT_ENGINE); @@ -897,6 +980,11 @@ etna_screen_create(struct etna_device *dev, struct etna_gpu *gpu, if (!etna_get_specs(screen)) goto fail; + if (screen->specs.halti >= 5 && !etnaviv_device_softpin_capable(dev)) { + DBG("halti5 requires softpin"); + goto fail; + } + screen->options = (nir_shader_compiler_options) { .lower_fpow = true, .lower_sub = true, @@ -954,16 +1042,8 @@ etna_screen_create(struct etna_device *dev, struct etna_gpu *gpu, if (screen->drm_version >= ETNA_DRM_VERSION_PERFMON) etna_pm_query_setup(screen); - mtx_init(&screen->lock, mtx_recursive); - screen->used_resources = _mesa_set_create(NULL, _mesa_hash_pointer, - _mesa_key_pointer_equal); - if (!screen->used_resources) - goto fail2; - return pscreen; -fail2: - mtx_destroy(&screen->lock); fail: etna_screen_destroy(pscreen); return NULL; diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_screen.h b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_screen.h index 99e2cc20a..1bdae5a16 100644 --- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_screen.h +++ b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_screen.h @@ -29,7 +29,7 @@ #define H_ETNAVIV_SCREEN #include "etnaviv_internal.h" -#include "etnaviv_query_pm.h" +#include "etnaviv_perfmon.h" #include "os/os_thread.h" #include "pipe/p_screen.h" @@ -85,10 +85,6 @@ struct etna_screen { uint32_t drm_version; - /* set of resources used by currently-unsubmitted renders */ - mtx_t lock; - struct set *used_resources; - nir_shader_compiler_options options; }; diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_shader.c b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_shader.c index a5310ddde..3ac619ac9 100644 --- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_shader.c +++ b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_shader.c @@ -151,6 +151,10 @@ etna_link_shaders(struct etna_context *ctx, struct compiled_shader_state *cs, cs->VS_OUTPUT_COUNT_PSIZE = cs->VS_OUTPUT_COUNT; } + /* if fragment shader doesn't read pointcoord, disable it */ + if (link.pcoord_varying_comp_ofs == -1) + cs->PA_CONFIG &= ~VIVS_PA_CONFIG_POINT_SPRITE_ENABLE; + cs->VS_LOAD_BALANCING = vs->vs_load_balancing; cs->VS_START_PC = 0; @@ -161,7 +165,6 @@ etna_link_shaders(struct etna_context *ctx, struct compiled_shader_state *cs, VIVS_PS_INPUT_COUNT_UNK8(fs->input_count_unk8); cs->PS_TEMP_REGISTER_CONTROL = VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS(MAX2(fs->num_temps, link.num_varyings + 1)); - cs->PS_CONTROL = VIVS_PS_CONTROL_SATURATE_RT0; /* XXX when can we set BYPASS? */ cs->PS_START_PC = 0; /* Precompute PS_INPUT_COUNT and TEMP_REGISTER_CONTROL in the case of MSAA @@ -187,7 +190,8 @@ etna_link_shaders(struct etna_context *ctx, struct compiled_shader_state *cs, cs->GL_VARYING_TOTAL_COMPONENTS = VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM(align(total_components, 2)); - cs->GL_VARYING_NUM_COMPONENTS = num_components[0]; + cs->GL_VARYING_NUM_COMPONENTS[0] = num_components[0]; + cs->GL_VARYING_NUM_COMPONENTS[1] = num_components[1]; cs->GL_VARYING_COMPONENT_USE[0] = component_use[0]; cs->GL_VARYING_COMPONENT_USE[1] = component_use[1]; @@ -199,6 +203,9 @@ etna_link_shaders(struct etna_context *ctx, struct compiled_shader_state *cs, VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN((link.pcoord_varying_comp_ofs != -1) ? link.pcoord_varying_comp_ofs : 0x7f); + /* mask out early Z bit when frag depth is written */ + cs->PE_DEPTH_CONFIG = ~COND(fs->ps_depth_out_reg >= 0, VIVS_PE_DEPTH_CONFIG_EARLY_Z); + /* reference instruction memory */ cs->vs_inst_mem_size = vs->code_size; cs->VS_INST_MEM = vs->code; @@ -206,7 +213,7 @@ etna_link_shaders(struct etna_context *ctx, struct compiled_shader_state *cs, cs->ps_inst_mem_size = fs->code_size; cs->PS_INST_MEM = fs->code; - if (vs->needs_icache | fs->needs_icache) { + if (vs->needs_icache || fs->needs_icache) { /* If either of the shaders needs ICACHE, we use it for both. It is * either switched on or off for the entire shader processor. */ @@ -278,6 +285,20 @@ etna_shader_update_vs_inputs(struct compiled_shader_state *cs, etna_bitarray_set(vs_input, 8, idx, cur_temp++); } + if (vs->vs_id_in_reg >= 0) { + cs->VS_INPUT_COUNT = VIVS_VS_INPUT_COUNT_COUNT(num_vs_inputs + 1) | + VIVS_VS_INPUT_COUNT_UNK8(vs->input_count_unk8) | + VIVS_VS_INPUT_COUNT_ID_ENABLE; + + etna_bitarray_set(vs_input, 8, num_vs_inputs, vs->vs_id_in_reg); + + cs->FE_HALTI5_ID_CONFIG = + VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_ENABLE | + VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_ENABLE | + VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_REG(vs->vs_id_in_reg * 4) | + VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_REG(vs->vs_id_in_reg * 4 + 1); + } + for (int idx = 0; idx < ARRAY_SIZE(cs->VS_INPUT); ++idx) cs->VS_INPUT[idx] = vs_input[idx]; @@ -303,15 +324,12 @@ dump_shader_info(struct etna_shader_variant *v, struct pipe_debug_callback *debu if (!unlikely(etna_mesa_debug & ETNA_DBG_SHADERDB)) return; - pipe_debug_message(debug, SHADER_INFO, "\n" - "SHADER-DB: %s prog %d/%d: %u instructions %u temps\n" - "SHADER-DB: %s prog %d/%d: %u immediates %u loops\n", + pipe_debug_message(debug, SHADER_INFO, + "%s shader: %u instructions, %u temps, " + "%u immediates, %u loops", etna_shader_stage(v), - v->shader->id, v->id, v->code_size, v->num_temps, - etna_shader_stage(v), - v->shader->id, v->id, v->uniforms.imm_count, v->num_loops); } @@ -376,6 +394,7 @@ etna_create_shader_state(struct pipe_context *pctx, const struct pipe_shader_state *pss) { struct etna_context *ctx = etna_context(pctx); + struct etna_screen *screen = ctx->screen; struct etna_shader *shader = CALLOC_STRUCT(etna_shader); if (!shader) @@ -383,7 +402,7 @@ etna_create_shader_state(struct pipe_context *pctx, static uint32_t id; shader->id = id++; - shader->specs = &ctx->specs; + shader->specs = &screen->specs; if (DBG_ENABLED(ETNA_DBG_NIR)) shader->nir = (pss->type == PIPE_SHADER_IR_NIR) ? pss->ir.nir : diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_shader.h b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_shader.h index 3c5b6e65d..528603a55 100644 --- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_shader.h +++ b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_shader.h @@ -43,6 +43,8 @@ struct etna_shader_key /* do we need to swap rb in frag color? */ unsigned frag_rb_swap : 1; + /* do we need to invert front facing value? */ + unsigned front_ccw : 1; }; uint32_t global; }; diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_state.c b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_state.c index 84fc9f88a..5559cc54f 100644 --- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_state.c +++ b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_state.c @@ -33,6 +33,8 @@ #include "etnaviv_clear_blit.h" #include "etnaviv_context.h" #include "etnaviv_format.h" +#include "etnaviv_rasterizer.h" +#include "etnaviv_screen.h" #include "etnaviv_shader.h" #include "etnaviv_surface.h" #include "etnaviv_translate.h" @@ -52,10 +54,12 @@ etna_set_stencil_ref(struct pipe_context *pctx, const struct pipe_stencil_ref *s ctx->stencil_ref_s = *sr; - cs->PE_STENCIL_CONFIG = VIVS_PE_STENCIL_CONFIG_REF_FRONT(sr->ref_value[0]); - /* rest of bits weaved in from depth_stencil_alpha */ - cs->PE_STENCIL_CONFIG_EXT = - VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK(sr->ref_value[0]); + for (unsigned i = 0; i < 2; i++) { + cs->PE_STENCIL_CONFIG[i] = + VIVS_PE_STENCIL_CONFIG_REF_FRONT(sr->ref_value[i]); + cs->PE_STENCIL_CONFIG_EXT[i] = + VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK(sr->ref_value[!i]); + } ctx->dirty |= ETNA_DIRTY_STENCIL_REF; } @@ -80,48 +84,53 @@ etna_set_constant_buffer(struct pipe_context *pctx, const struct pipe_constant_buffer *cb) { struct etna_context *ctx = etna_context(pctx); + struct etna_constbuf_state *so = &ctx->constant_buffer[shader]; - if (unlikely(index > 0)) { - DBG("Unhandled buffer index %i", index); - return; - } + assert(index < ETNA_MAX_CONST_BUF); - - util_copy_constant_buffer(&ctx->constant_buffer[shader], cb); + util_copy_constant_buffer(&so->cb[index], cb); /* Note that the state tracker can unbind constant buffers by * passing NULL here. */ - if (unlikely(!cb || (!cb->buffer && !cb->user_buffer))) + if (unlikely(!cb || (!cb->buffer && !cb->user_buffer))) { + so->enabled_mask &= ~(1 << index); return; + } - /* there is no support for ARB_uniform_buffer_object */ - assert(cb->buffer == NULL && cb->user_buffer != NULL); + assert(index != 0 || cb->user_buffer != NULL); if (!cb->buffer) { - struct pipe_constant_buffer *cb = &ctx->constant_buffer[shader]; + struct pipe_constant_buffer *cb = &so->cb[index]; u_upload_data(pctx->const_uploader, 0, cb->buffer_size, 16, cb->user_buffer, &cb->buffer_offset, &cb->buffer); } + so->enabled_mask |= 1 << index; ctx->dirty |= ETNA_DIRTY_CONSTBUF; } static void -etna_update_render_resource(struct pipe_context *pctx, struct pipe_resource *pres) +etna_update_render_resource(struct pipe_context *pctx, struct etna_resource *base) { - struct etna_resource *res = etna_resource(pres); + struct etna_resource *to = base, *from = base; - if (res->texture && etna_resource_older(res, etna_resource(res->texture))) { - /* The render buffer is older than the texture buffer. Copy it over. */ - etna_copy_resource(pctx, pres, res->texture, 0, pres->last_level); - res->seqno = etna_resource(res->texture)->seqno; + if (base->texture && etna_resource_newer(etna_resource(base->texture), base)) + from = etna_resource(base->texture); + + if (base->render) + to = etna_resource(base->render); + + if ((to != from) && etna_resource_older(to, from)) { + etna_copy_resource(pctx, &to->base, &from->base, 0, base->base.last_level); + to->seqno = from->seqno; } } static void etna_set_framebuffer_state(struct pipe_context *pctx, - const struct pipe_framebuffer_state *sv) + const struct pipe_framebuffer_state *fb) { struct etna_context *ctx = etna_context(pctx); + struct etna_screen *screen = ctx->screen; struct compiled_framebuffer_state *cs = &ctx->framebuffer; int nr_samples_color = -1; int nr_samples_depth = -1; @@ -129,21 +138,28 @@ etna_set_framebuffer_state(struct pipe_context *pctx, /* Set up TS as well. Warning: this state is used by both the RS and PE */ uint32_t ts_mem_config = 0; uint32_t pe_mem_config = 0; + uint32_t pe_logic_op = 0; - if (sv->nr_cbufs > 0) { /* at least one color buffer? */ - struct etna_surface *cbuf = etna_surface(sv->cbufs[0]); + if (fb->nr_cbufs > 0) { /* at least one color buffer? */ + struct etna_surface *cbuf = etna_surface(fb->cbufs[0]); struct etna_resource *res = etna_resource(cbuf->base.texture); bool color_supertiled = (res->layout & ETNA_LAYOUT_BIT_SUPER) != 0; + uint32_t fmt = translate_pe_format(cbuf->base.format); assert(res->layout & ETNA_LAYOUT_BIT_TILE); /* Cannot render to linear surfaces */ - etna_update_render_resource(pctx, cbuf->base.texture); + etna_update_render_resource(pctx, etna_resource(cbuf->prsc)); - cs->PE_COLOR_FORMAT = - VIVS_PE_COLOR_FORMAT_FORMAT(translate_rs_format(cbuf->base.format)) | + if (fmt >= PE_FORMAT_R16F) + cs->PE_COLOR_FORMAT = VIVS_PE_COLOR_FORMAT_FORMAT_EXT(fmt) | + VIVS_PE_COLOR_FORMAT_FORMAT_MASK; + else + cs->PE_COLOR_FORMAT = VIVS_PE_COLOR_FORMAT_FORMAT(fmt); + + cs->PE_COLOR_FORMAT |= VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK | VIVS_PE_COLOR_FORMAT_OVERWRITE | COND(color_supertiled, VIVS_PE_COLOR_FORMAT_SUPER_TILED) | - COND(color_supertiled && ctx->specs.halti >= 5, VIVS_PE_COLOR_FORMAT_SUPER_TILED_NEW); + COND(color_supertiled && screen->specs.halti >= 5, VIVS_PE_COLOR_FORMAT_SUPER_TILED_NEW); /* VIVS_PE_COLOR_FORMAT_COMPONENTS() and * VIVS_PE_COLOR_FORMAT_OVERWRITE comes from blend_state * but only if we set the bits above. */ @@ -159,13 +175,13 @@ etna_set_framebuffer_state(struct pipe_context *pctx, cbuf->surf.offset, cbuf->surf.stride * 4); } - if (ctx->specs.pixel_pipes == 1) { + if (screen->specs.pixel_pipes == 1) { cs->PE_COLOR_ADDR = cbuf->reloc[0]; cs->PE_COLOR_ADDR.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE; } else { /* Rendered textures must always be multi-tiled, or single-buffer mode must be supported */ - assert((res->layout & ETNA_LAYOUT_BIT_MULTI) || ctx->specs.single_buffer); - for (int i = 0; i < ctx->specs.pixel_pipes; i++) { + assert((res->layout & ETNA_LAYOUT_BIT_MULTI) || screen->specs.single_buffer); + for (int i = 0; i < screen->specs.pixel_pipes; i++) { cs->PE_PIPE_COLOR_ADDR[i] = cbuf->reloc[i]; cs->PE_PIPE_COLOR_ADDR[i].flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE; } @@ -174,6 +190,7 @@ etna_set_framebuffer_state(struct pipe_context *pctx, if (cbuf->surf.ts_size) { cs->TS_COLOR_CLEAR_VALUE = cbuf->level->clear_value; + cs->TS_COLOR_CLEAR_VALUE_EXT = cbuf->level->clear_value >> 32; cs->TS_COLOR_STATUS_BASE = cbuf->ts_reloc; cs->TS_COLOR_STATUS_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE; @@ -185,7 +202,7 @@ etna_set_framebuffer_state(struct pipe_context *pctx, if (cbuf->level->ts_compress_fmt >= 0) { /* overwrite bit breaks v1/v2 compression */ - if (!ctx->specs.v4_compression) + if (!screen->specs.v4_compression) cs->PE_COLOR_FORMAT &= ~VIVS_PE_COLOR_FORMAT_OVERWRITE; ts_mem_config |= @@ -195,6 +212,13 @@ etna_set_framebuffer_state(struct pipe_context *pctx, } nr_samples_color = cbuf->base.texture->nr_samples; + + if (util_format_is_srgb(cbuf->base.format)) + pe_logic_op |= VIVS_PE_LOGIC_OP_SRGB; + + cs->PS_CONTROL = COND(util_format_is_unorm(cbuf->base.format), VIVS_PS_CONTROL_SATURATE_RT0); + cs->PS_CONTROL_EXT = + VIVS_PS_CONTROL_EXT_OUTPUT_MODE0(translate_output_mode(cbuf->base.format, screen->specs.halti >= 5)); } else { /* Clearing VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK and * VIVS_PE_COLOR_FORMAT_OVERWRITE prevents us from overwriting the @@ -205,15 +229,15 @@ etna_set_framebuffer_state(struct pipe_context *pctx, cs->TS_COLOR_SURFACE_BASE.bo = NULL; cs->PE_COLOR_ADDR = ctx->dummy_rt_reloc; - for (int i = 0; i < ctx->specs.pixel_pipes; i++) + for (int i = 0; i < screen->specs.pixel_pipes; i++) cs->PE_PIPE_COLOR_ADDR[i] = ctx->dummy_rt_reloc; } - if (sv->zsbuf != NULL) { - struct etna_surface *zsbuf = etna_surface(sv->zsbuf); + if (fb->zsbuf != NULL) { + struct etna_surface *zsbuf = etna_surface(fb->zsbuf); struct etna_resource *res = etna_resource(zsbuf->base.texture); - etna_update_render_resource(pctx, zsbuf->base.texture); + etna_update_render_resource(pctx, etna_resource(zsbuf->prsc)); assert(res->layout &ETNA_LAYOUT_BIT_TILE); /* Cannot render to linear surfaces */ @@ -227,16 +251,16 @@ etna_set_framebuffer_state(struct pipe_context *pctx, COND(depth_supertiled, VIVS_PE_DEPTH_CONFIG_SUPER_TILED) | VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_Z | VIVS_PE_DEPTH_CONFIG_UNK18 | /* something to do with clipping? */ - COND(ctx->specs.halti >= 5, VIVS_PE_DEPTH_CONFIG_DISABLE_ZS) /* Needs to be enabled on GC7000, otherwise depth writes hang w/ TS - apparently it does something else now */ + COND(screen->specs.halti >= 5, VIVS_PE_DEPTH_CONFIG_DISABLE_ZS) /* Needs to be enabled on GC7000, otherwise depth writes hang w/ TS - apparently it does something else now */ ; /* VIVS_PE_DEPTH_CONFIG_ONLY_DEPTH */ /* merged with depth_stencil_alpha */ - if (ctx->specs.pixel_pipes == 1) { + if (screen->specs.pixel_pipes == 1) { cs->PE_DEPTH_ADDR = zsbuf->reloc[0]; cs->PE_DEPTH_ADDR.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE; } else { - for (int i = 0; i < ctx->specs.pixel_pipes; i++) { + for (int i = 0; i < screen->specs.pixel_pipes; i++) { cs->PE_PIPE_DEPTH_ADDR[i] = zsbuf->reloc[i]; cs->PE_PIPE_DEPTH_ADDR[i].flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE; } @@ -325,25 +349,19 @@ etna_set_framebuffer_state(struct pipe_context *pctx, break; } - /* Scissor setup */ - cs->SE_SCISSOR_LEFT = 0; /* affected by rasterizer and scissor state as well */ - cs->SE_SCISSOR_TOP = 0; - cs->SE_SCISSOR_RIGHT = (sv->width << 16) + ETNA_SE_SCISSOR_MARGIN_RIGHT; - cs->SE_SCISSOR_BOTTOM = (sv->height << 16) + ETNA_SE_SCISSOR_MARGIN_BOTTOM; - cs->SE_CLIP_RIGHT = (sv->width << 16) + ETNA_SE_CLIP_MARGIN_RIGHT; - cs->SE_CLIP_BOTTOM = (sv->height << 16) + ETNA_SE_CLIP_MARGIN_BOTTOM; - cs->TS_MEM_CONFIG = ts_mem_config; cs->PE_MEM_CONFIG = pe_mem_config; /* Single buffer setup. There is only one switch for this, not a separate * one per color buffer / depth buffer. To keep the logic simple always use * single buffer when this feature is available. + * note: the blob will use 2 in some situations, figure out why? */ - cs->PE_LOGIC_OP = VIVS_PE_LOGIC_OP_SINGLE_BUFFER(ctx->specs.single_buffer ? 3 : 0); + pe_logic_op |= VIVS_PE_LOGIC_OP_SINGLE_BUFFER(screen->specs.single_buffer ? 3 : 0); + cs->PE_LOGIC_OP = pe_logic_op; /* keep copy of original structure */ - util_copy_framebuffer_state(&ctx->framebuffer_s, sv); + util_copy_framebuffer_state(&ctx->framebuffer_s, fb); ctx->dirty |= ETNA_DIRTY_FRAMEBUFFER | ETNA_DIRTY_DERIVE_TS; } @@ -359,19 +377,10 @@ etna_set_scissor_states(struct pipe_context *pctx, unsigned start_slot, unsigned num_scissors, const struct pipe_scissor_state *ss) { struct etna_context *ctx = etna_context(pctx); - struct compiled_scissor_state *cs = &ctx->scissor; assert(ss->minx <= ss->maxx); assert(ss->miny <= ss->maxy); - /* note that this state is only used when rasterizer_state->scissor is on */ - ctx->scissor_s = *ss; - cs->SE_SCISSOR_LEFT = (ss->minx << 16); - cs->SE_SCISSOR_TOP = (ss->miny << 16); - cs->SE_SCISSOR_RIGHT = (ss->maxx << 16) + ETNA_SE_SCISSOR_MARGIN_RIGHT; - cs->SE_SCISSOR_BOTTOM = (ss->maxy << 16) + ETNA_SE_SCISSOR_MARGIN_BOTTOM; - cs->SE_CLIP_RIGHT = (ss->maxx << 16) + ETNA_SE_CLIP_MARGIN_RIGHT; - cs->SE_CLIP_BOTTOM = (ss->maxy << 16) + ETNA_SE_CLIP_MARGIN_BOTTOM; - + ctx->scissor = *ss; ctx->dirty |= ETNA_DIRTY_SCISSOR; } @@ -406,14 +415,10 @@ etna_set_viewport_states(struct pipe_context *pctx, unsigned start_slot, /* Compute scissor rectangle (fixp) from viewport. * Make sure left is always < right and top always < bottom. */ - cs->SE_SCISSOR_LEFT = etna_f32_to_fixp16(MAX2(vs->translate[0] - fabsf(vs->scale[0]), 0.0f)); - cs->SE_SCISSOR_TOP = etna_f32_to_fixp16(MAX2(vs->translate[1] - fabsf(vs->scale[1]), 0.0f)); - uint32_t right_fixp = etna_f32_to_fixp16(MAX2(vs->translate[0] + fabsf(vs->scale[0]), 0.0f)); - uint32_t bottom_fixp = etna_f32_to_fixp16(MAX2(vs->translate[1] + fabsf(vs->scale[1]), 0.0f)); - cs->SE_SCISSOR_RIGHT = right_fixp + ETNA_SE_SCISSOR_MARGIN_RIGHT; - cs->SE_SCISSOR_BOTTOM = bottom_fixp + ETNA_SE_SCISSOR_MARGIN_BOTTOM; - cs->SE_CLIP_RIGHT = right_fixp + ETNA_SE_CLIP_MARGIN_RIGHT; - cs->SE_CLIP_BOTTOM = bottom_fixp + ETNA_SE_CLIP_MARGIN_BOTTOM; + cs->SE_SCISSOR_LEFT = MAX2(vs->translate[0] - fabsf(vs->scale[0]), 0.0f); + cs->SE_SCISSOR_TOP = MAX2(vs->translate[1] - fabsf(vs->scale[1]), 0.0f); + cs->SE_SCISSOR_RIGHT = ceilf(MAX2(vs->translate[0] + fabsf(vs->scale[0]), 0.0f)); + cs->SE_SCISSOR_BOTTOM = ceilf(MAX2(vs->translate[1] + fabsf(vs->scale[1]), 0.0f)); cs->PE_DEPTH_NEAR = fui(0.0); /* not affected if depth mode is Z (as in GL) */ cs->PE_DEPTH_FAR = fui(1.0); @@ -505,43 +510,29 @@ etna_vertex_elements_state_create(struct pipe_context *pctx, unsigned num_elements, const struct pipe_vertex_element *elements) { struct etna_context *ctx = etna_context(pctx); + struct etna_screen *screen = ctx->screen; struct compiled_vertex_elements_state *cs = CALLOC_STRUCT(compiled_vertex_elements_state); if (!cs) return NULL; - if (num_elements > ctx->specs.vertex_max_elements) { + if (num_elements > screen->specs.vertex_max_elements) { BUG("number of elements (%u) exceeds chip maximum (%u)", num_elements, - ctx->specs.vertex_max_elements); + screen->specs.vertex_max_elements); return NULL; } /* XXX could minimize number of consecutive stretches here by sorting, and * permuting the inputs in shader or does Mesa do this already? */ - /* Check that vertex element binding is compatible with hardware; thus - * elements[idx].vertex_buffer_index are < stream_count. If not, the binding - * uses more streams than is supported, and u_vbuf should have done some - * reorganization for compatibility. */ - - /* TODO: does mesa this for us? */ - bool incompatible = false; - for (unsigned idx = 0; idx < num_elements; ++idx) { - if (elements[idx].vertex_buffer_index >= ctx->specs.stream_count || elements[idx].instance_divisor > 0) - incompatible = true; - } - cs->num_elements = num_elements; - if (incompatible || num_elements == 0) { - DBG("Error: zero vertex elements, or more vertex buffers used than supported"); - FREE(cs); - return NULL; - } unsigned start_offset = 0; /* start of current consecutive stretch */ bool nonconsecutive = true; /* previous value of nonconsecutive */ + uint32_t buffer_mask = 0; /* mask of buffer_idx already seen */ for (unsigned idx = 0; idx < num_elements; ++idx) { + unsigned buffer_idx = elements[idx].vertex_buffer_index; unsigned element_size = util_format_get_blocksize(elements[idx].src_format); unsigned end_offset = elements[idx].src_offset + element_size; uint32_t format_type, normalize; @@ -549,12 +540,15 @@ etna_vertex_elements_state_create(struct pipe_context *pctx, if (nonconsecutive) start_offset = elements[idx].src_offset; + /* guaranteed by PIPE_CAP_MAX_VERTEX_BUFFERS */ + assert(buffer_idx < screen->specs.stream_count); + /* maximum vertex size is 256 bytes */ - assert(element_size != 0 && end_offset <= 256); + assert(element_size != 0 && (end_offset - start_offset) < 256); /* check whether next element is consecutive to this one */ nonconsecutive = (idx == (num_elements - 1)) || - elements[idx + 1].vertex_buffer_index != elements[idx].vertex_buffer_index || + elements[idx + 1].vertex_buffer_index != buffer_idx || end_offset != elements[idx + 1].src_offset; format_type = translate_vertex_format_type(elements[idx].src_format); @@ -563,13 +557,13 @@ etna_vertex_elements_state_create(struct pipe_context *pctx, assert(format_type != ETNA_NO_MATCH); assert(normalize != ETNA_NO_MATCH); - if (ctx->specs.halti < 5) { + if (screen->specs.halti < 5) { cs->FE_VERTEX_ELEMENT_CONFIG[idx] = COND(nonconsecutive, VIVS_FE_VERTEX_ELEMENT_CONFIG_NONCONSECUTIVE) | format_type | VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM(util_format_get_nr_components(elements[idx].src_format)) | normalize | VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN(ENDIAN_MODE_NO_SWAP) | - VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM(elements[idx].vertex_buffer_index) | + VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM(buffer_idx) | VIVS_FE_VERTEX_ELEMENT_CONFIG_START(elements[idx].src_offset) | VIVS_FE_VERTEX_ELEMENT_CONFIG_END(end_offset - start_offset); } else { /* HALTI5 spread vertex attrib config over two registers */ @@ -577,13 +571,26 @@ etna_vertex_elements_state_create(struct pipe_context *pctx, format_type | VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM(util_format_get_nr_components(elements[idx].src_format)) | normalize | VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN(ENDIAN_MODE_NO_SWAP) | - VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM(elements[idx].vertex_buffer_index) | + VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM(buffer_idx) | VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START(elements[idx].src_offset); cs->NFE_GENERIC_ATTRIB_CONFIG1[idx] = COND(nonconsecutive, VIVS_NFE_GENERIC_ATTRIB_CONFIG1_NONCONSECUTIVE) | VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END(end_offset - start_offset); } - cs->NFE_GENERIC_ATTRIB_SCALE[idx] = 0x3f800000; /* 1 for integer, 1.0 for float */ + + if (util_format_is_pure_integer(elements[idx].src_format)) + cs->NFE_GENERIC_ATTRIB_SCALE[idx] = 1; + else + cs->NFE_GENERIC_ATTRIB_SCALE[idx] = fui(1.0f); + + /* instance_divisor is part of elements state but should be the same for all buffers */ + if (buffer_mask & 1 << buffer_idx) + assert(cs->NFE_VERTEX_STREAMS_VERTEX_DIVISOR[buffer_idx] == elements[idx].instance_divisor); + else + cs->NFE_VERTEX_STREAMS_VERTEX_DIVISOR[buffer_idx] = elements[idx].instance_divisor; + + buffer_mask |= 1 << buffer_idx; + cs->num_buffers = MAX2(cs->num_buffers, buffer_idx + 1); } return cs; @@ -640,6 +647,36 @@ etna_update_ts_config(struct etna_context *ctx) return true; } +static bool +etna_update_clipping(struct etna_context *ctx) +{ + const struct etna_rasterizer_state *rasterizer = etna_rasterizer_state(ctx->rasterizer); + const struct pipe_framebuffer_state *fb = &ctx->framebuffer_s; + + /* clip framebuffer against viewport */ + uint32_t scissor_left = ctx->viewport.SE_SCISSOR_LEFT; + uint32_t scissor_top = ctx->viewport.SE_SCISSOR_TOP; + uint32_t scissor_right = MIN2(fb->width, ctx->viewport.SE_SCISSOR_RIGHT); + uint32_t scissor_bottom = MIN2(fb->height, ctx->viewport.SE_SCISSOR_BOTTOM); + + /* clip against scissor */ + if (rasterizer->scissor) { + scissor_left = MAX2(ctx->scissor.minx, scissor_left); + scissor_top = MAX2(ctx->scissor.miny, scissor_top); + scissor_right = MIN2(ctx->scissor.maxx, scissor_right); + scissor_bottom = MIN2(ctx->scissor.maxy, scissor_bottom); + } + + ctx->clipping.minx = scissor_left; + ctx->clipping.miny = scissor_top; + ctx->clipping.maxx = scissor_right; + ctx->clipping.maxy = scissor_bottom; + + ctx->dirty |= ETNA_DIRTY_SCISSOR_CLIP; + + return true; +} + struct etna_state_updater { bool (*update)(struct etna_context *ctx); uint32_t dirty; @@ -660,6 +697,10 @@ static const struct etna_state_updater etna_state_updates[] = { }, { etna_update_ts_config, ETNA_DIRTY_DERIVE_TS, + }, + { + etna_update_clipping, ETNA_DIRTY_SCISSOR | ETNA_DIRTY_FRAMEBUFFER | + ETNA_DIRTY_RASTERIZER | ETNA_DIRTY_VIEWPORT, } }; diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_surface.c b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_surface.c index 442957380..c78973bdb 100644 --- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_surface.c +++ b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_surface.c @@ -37,12 +37,49 @@ #include "hw/common.xml.h" +#include "drm-uapi/drm_fourcc.h" + +static struct etna_resource * +etna_render_handle_incompatible(struct pipe_context *pctx, struct pipe_resource *prsc) +{ + struct etna_context *ctx = etna_context(pctx); + struct etna_screen *screen = ctx->screen; + struct etna_resource *res = etna_resource(prsc); + bool need_multitiled = screen->specs.pixel_pipes > 1 && !screen->specs.single_buffer; + bool want_supertiled = screen->specs.can_supertile; + + /* Resource is compatible if it is tiled and has multi tiling when required + * TODO: LINEAR_PE feature means render to linear is possible ? + */ + if (res->layout != ETNA_LAYOUT_LINEAR && + (!need_multitiled || (res->layout & ETNA_LAYOUT_BIT_MULTI))) + return res; + + if (!res->render) { + struct pipe_resource templat = *prsc; + unsigned layout = ETNA_LAYOUT_TILED; + if (need_multitiled) + layout |= ETNA_LAYOUT_BIT_MULTI; + if (want_supertiled) + layout |= ETNA_LAYOUT_BIT_SUPER; + + templat.bind &= (PIPE_BIND_DEPTH_STENCIL | PIPE_BIND_RENDER_TARGET | + PIPE_BIND_BLENDABLE); + res->render = + etna_resource_alloc(pctx->screen, layout, + DRM_FORMAT_MOD_LINEAR, &templat); + assert(res->render); + } + return etna_resource(res->render); +} + static struct pipe_surface * etna_create_surface(struct pipe_context *pctx, struct pipe_resource *prsc, const struct pipe_surface *templat) { struct etna_context *ctx = etna_context(pctx); - struct etna_resource *rsc = etna_resource(prsc); + struct etna_screen *screen = ctx->screen; + struct etna_resource *rsc = etna_render_handle_incompatible(pctx, prsc); struct etna_surface *surf = CALLOC_STRUCT(etna_surface); if (!surf) @@ -57,6 +94,7 @@ etna_create_surface(struct pipe_context *pctx, struct pipe_resource *prsc, pipe_reference_init(&surf->base.reference, 1); pipe_resource_reference(&surf->base.texture, &rsc->base); + pipe_resource_reference(&surf->prsc, prsc); /* Allocate a TS for the resource if there isn't one yet, * and it is allowed by the hw (width is a multiple of 16). @@ -64,16 +102,18 @@ etna_create_surface(struct pipe_context *pctx, struct pipe_resource *prsc, * indicate the tile status module bypasses the memory * offset and MMU. */ - if (VIV_FEATURE(ctx->screen, chipFeatures, FAST_CLEAR) && - VIV_FEATURE(ctx->screen, chipMinorFeatures0, MC20) && + if (VIV_FEATURE(screen, chipFeatures, FAST_CLEAR) && + VIV_FEATURE(screen, chipMinorFeatures0, MC20) && !rsc->ts_bo && + /* needs to be RS/BLT compatible for transfer_map/unmap */ (rsc->levels[level].padded_width & ETNA_RS_WIDTH_MASK) == 0 && - (rsc->levels[level].padded_height & ETNA_RS_HEIGHT_MASK) == 0) { + (rsc->levels[level].padded_height & ETNA_RS_HEIGHT_MASK) == 0 && + etna_resource_hw_tileable(screen->specs.use_blt, prsc)) { etna_screen_resource_alloc_ts(pctx->screen, rsc); } surf->base.texture = &rsc->base; - surf->base.format = rsc->base.format; + surf->base.format = templat->format; surf->base.width = rsc->levels[level].width; surf->base.height = rsc->levels[level].height; surf->base.writable = templat->writable; /* what is this for anyway */ @@ -91,7 +131,7 @@ etna_create_surface(struct pipe_context *pctx, struct pipe_resource *prsc, struct etna_resource_level *lev = &rsc->levels[level]; /* Setup template relocations for this surface */ - for (unsigned pipe = 0; pipe < ctx->specs.pixel_pipes; ++pipe) { + for (unsigned pipe = 0; pipe < screen->specs.pixel_pipes; ++pipe) { surf->reloc[pipe].bo = rsc->bo; surf->reloc[pipe].offset = surf->surf.offset; surf->reloc[pipe].flags = 0; @@ -116,7 +156,7 @@ etna_create_surface(struct pipe_context *pctx, struct pipe_resource *prsc, surf->ts_reloc.offset = surf->surf.ts_offset; surf->ts_reloc.flags = 0; - if (!ctx->specs.use_blt) { + if (!screen->specs.use_blt) { /* This (ab)uses the RS as a plain buffer memset(). * Currently uses a fixed row size of 64 bytes. Some benchmarking with * different sizes may be in order. */ @@ -131,13 +171,13 @@ etna_create_surface(struct pipe_context *pctx, struct pipe_resource *prsc, .dither = {0xffffffff, 0xffffffff}, .width = 16, .height = etna_align_up(surf->surf.ts_size / 0x40, 4), - .clear_value = {ctx->specs.ts_clear_value}, + .clear_value = {screen->specs.ts_clear_value}, .clear_mode = VIVS_RS_CLEAR_CONTROL_MODE_ENABLED1, .clear_bits = 0xffff }); } } else { - if (!ctx->specs.use_blt) + if (!screen->specs.use_blt) etna_rs_gen_clear_surface(ctx, surf, surf->level->clear_value); } @@ -148,6 +188,7 @@ static void etna_surface_destroy(struct pipe_context *pctx, struct pipe_surface *psurf) { pipe_resource_reference(&psurf->texture, NULL); + pipe_resource_reference(&etna_surface(psurf)->prsc, NULL); FREE(psurf); } diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_surface.h b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_surface.h index e8cfd209a..fef85f521 100644 --- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_surface.h +++ b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_surface.h @@ -41,6 +41,8 @@ struct etna_surface { struct etna_resource_level *level; struct etna_reloc reloc[ETNA_MAX_PIXELPIPES]; struct etna_reloc ts_reloc; + /* keep pointer to original resource (for when a render compatible resource is used) */ + struct pipe_resource *prsc; }; static inline struct etna_surface * diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_texture.c b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_texture.c index 59a0d122d..e358f70ac 100644 --- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_texture.c +++ b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_texture.c @@ -32,6 +32,7 @@ #include "etnaviv_context.h" #include "etnaviv_emit.h" #include "etnaviv_format.h" +#include "etnaviv_texture_desc.h" #include "etnaviv_texture_state.h" #include "etnaviv_translate.h" #include "util/u_inlines.h" @@ -46,6 +47,7 @@ etna_bind_sampler_states(struct pipe_context *pctx, enum pipe_shader_type shader { /* bind fragment sampler */ struct etna_context *ctx = etna_context(pctx); + struct etna_screen *screen = ctx->screen; int offset; switch (shader) { @@ -54,7 +56,7 @@ etna_bind_sampler_states(struct pipe_context *pctx, enum pipe_shader_type shader ctx->num_fragment_samplers = num_samplers; break; case PIPE_SHADER_VERTEX: - offset = ctx->specs.vertex_sampler_offset; + offset = screen->specs.vertex_sampler_offset; break; default: assert(!"Invalid shader"); @@ -73,31 +75,40 @@ etna_bind_sampler_states(struct pipe_context *pctx, enum pipe_shader_type shader ctx->dirty |= ETNA_DIRTY_SAMPLERS; } -static void +static bool etna_configure_sampler_ts(struct etna_sampler_ts *sts, struct pipe_sampler_view *pview, bool enable) { + bool dirty = (sts->enable != enable); + assert(sts); sts->enable = enable; - if (enable) { - struct etna_resource *rsc = etna_resource(pview->texture); - struct etna_resource_level *lev = &rsc->levels[0]; - assert(rsc->ts_bo && lev->ts_valid); - - sts->mode = lev->ts_mode; - sts->TS_SAMPLER_CONFIG = - VIVS_TS_SAMPLER_CONFIG_ENABLE | - COND(lev->ts_compress_fmt >= 0, VIVS_TS_SAMPLER_CONFIG_COMPRESSION) | - VIVS_TS_SAMPLER_CONFIG_COMPRESSION_FORMAT(lev->ts_compress_fmt); - sts->TS_SAMPLER_CLEAR_VALUE = lev->clear_value; - sts->TS_SAMPLER_CLEAR_VALUE2 = lev->clear_value; /* To handle 64-bit formats this needs a different value */ - sts->TS_SAMPLER_STATUS_BASE.bo = rsc->ts_bo; - sts->TS_SAMPLER_STATUS_BASE.offset = lev->ts_offset; - sts->TS_SAMPLER_STATUS_BASE.flags = ETNA_RELOC_READ; - } else { + + if (!enable) { sts->TS_SAMPLER_CONFIG = 0; sts->TS_SAMPLER_STATUS_BASE.bo = NULL; + return dirty; } - /* n.b.: relies on caller to mark ETNA_DIRTY_SAMPLER_VIEWS */ + + struct etna_resource *rsc = etna_resource(pview->texture); + struct etna_resource_level *lev = &rsc->levels[0]; + + if (lev->clear_value != sts->TS_SAMPLER_CLEAR_VALUE) + dirty = true; + + assert(rsc->ts_bo && lev->ts_valid); + + sts->mode = lev->ts_mode; + sts->TS_SAMPLER_CONFIG = + VIVS_TS_SAMPLER_CONFIG_ENABLE | + COND(lev->ts_compress_fmt >= 0, VIVS_TS_SAMPLER_CONFIG_COMPRESSION) | + VIVS_TS_SAMPLER_CONFIG_COMPRESSION_FORMAT(lev->ts_compress_fmt); + sts->TS_SAMPLER_CLEAR_VALUE = lev->clear_value; + sts->TS_SAMPLER_CLEAR_VALUE2 = lev->clear_value >> 32; + sts->TS_SAMPLER_STATUS_BASE.bo = rsc->ts_bo; + sts->TS_SAMPLER_STATUS_BASE.offset = lev->ts_offset; + sts->TS_SAMPLER_STATUS_BASE.flags = ETNA_RELOC_READ; + + return dirty; } /* Return true if the GPU can use sampler TS with this sampler view. @@ -121,6 +132,7 @@ etna_can_use_sampler_ts(struct pipe_sampler_view *view, int num) */ struct etna_resource *rsc = etna_resource(view->texture); struct etna_screen *screen = etna_screen(rsc->base.screen); + return VIV_FEATURE(screen, chipMinorFeatures2, TEXTURE_TILED_READ) && num < VIVS_TS_SAMPLER__LEN && rsc->base.target != PIPE_BUFFER && @@ -129,7 +141,7 @@ etna_can_use_sampler_ts(struct pipe_sampler_view *view, int num) rsc->levels[0].ts_valid; } -static void +void etna_update_sampler_source(struct pipe_sampler_view *view, int num) { struct etna_resource *base = etna_resource(view->texture); @@ -137,8 +149,8 @@ etna_update_sampler_source(struct pipe_sampler_view *view, int num) struct etna_context *ctx = etna_context(view->context); bool enable_sampler_ts = false; - if (base->external && etna_resource_newer(etna_resource(base->external), base)) - from = etna_resource(base->external); + if (base->render && etna_resource_newer(etna_resource(base->render), base)) + from = etna_resource(base->render); if (base->texture) to = etna_resource(base->texture); @@ -147,6 +159,7 @@ etna_update_sampler_source(struct pipe_sampler_view *view, int num) etna_copy_resource(view->context, &to->base, &from->base, 0, view->texture->last_level); to->seqno = from->seqno; + ctx->dirty |= ETNA_DIRTY_TEXTURE_CACHES; } else if ((to == from) && etna_resource_needs_flush(to)) { if (ctx->ts_for_sampler_view && etna_can_use_sampler_ts(view, num)) { enable_sampler_ts = true; @@ -156,10 +169,16 @@ etna_update_sampler_source(struct pipe_sampler_view *view, int num) etna_copy_resource(view->context, &to->base, &from->base, 0, view->texture->last_level); to->flush_seqno = from->seqno; + ctx->dirty |= ETNA_DIRTY_TEXTURE_CACHES; } + } else if ((to == from) && (to->flush_seqno < from->seqno)) { + to->flush_seqno = from->seqno; + ctx->dirty |= ETNA_DIRTY_TEXTURE_CACHES; } - if (ctx->ts_for_sampler_view) { - etna_configure_sampler_ts(ctx->ts_for_sampler_view(view), view, enable_sampler_ts); + if (ctx->ts_for_sampler_view && + etna_configure_sampler_ts(ctx->ts_for_sampler_view(view), view, enable_sampler_ts)) { + ctx->dirty |= ETNA_DIRTY_SAMPLER_VIEWS | ETNA_DIRTY_TEXTURE_CACHES; + ctx->dirty_sampler_views |= (1 << num); } } @@ -207,7 +226,6 @@ etna_texture_handle_incompatible(struct pipe_context *pctx, struct pipe_resource PIPE_BIND_BLENDABLE); res->texture = etna_resource_alloc(pctx->screen, ETNA_LAYOUT_TILED, - ETNA_ADDRESSING_MODE_TILED, DRM_FORMAT_MOD_LINEAR, &templat); } @@ -249,8 +267,9 @@ static inline void etna_fragtex_set_sampler_views(struct etna_context *ctx, unsigned nr, struct pipe_sampler_view **views) { + struct etna_screen *screen = ctx->screen; unsigned start = 0; - unsigned end = start + ctx->specs.fragment_sampler_count; + unsigned end = start + screen->specs.fragment_sampler_count; set_sampler_views(ctx, start, end, nr, views); ctx->num_fragment_sampler_views = nr; @@ -261,8 +280,9 @@ static inline void etna_vertex_set_sampler_views(struct etna_context *ctx, unsigned nr, struct pipe_sampler_view **views) { - unsigned start = ctx->specs.vertex_sampler_offset; - unsigned end = start + ctx->specs.vertex_sampler_count; + struct etna_screen *screen = ctx->screen; + unsigned start = screen->specs.vertex_sampler_offset; + unsigned end = start + screen->specs.vertex_sampler_count; set_sampler_views(ctx, start, end, nr, views); } @@ -277,11 +297,6 @@ etna_set_sampler_views(struct pipe_context *pctx, enum pipe_shader_type shader, ctx->dirty |= ETNA_DIRTY_SAMPLER_VIEWS | ETNA_DIRTY_TEXTURE_CACHES; - for (unsigned idx = 0; idx < num_views; ++idx) { - if (views[idx]) - etna_update_sampler_source(views[idx], idx); - } - switch (shader) { case PIPE_SHADER_FRAGMENT: etna_fragtex_set_sampler_views(ctx, num_views, views); @@ -299,7 +314,9 @@ etna_texture_barrier(struct pipe_context *pctx, unsigned flags) struct etna_context *ctx = etna_context(pctx); /* clear color and texture cache to make sure that texture unit reads * what has been written */ + mtx_lock(&ctx->lock); etna_set_state(ctx->stream, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_TEXTURE); + mtx_unlock(&ctx->lock); } uint32_t @@ -311,8 +328,15 @@ active_samplers_bits(struct etna_context *ctx) void etna_texture_init(struct pipe_context *pctx) { + struct etna_context *ctx = etna_context(pctx); + struct etna_screen *screen = ctx->screen; + pctx->bind_sampler_states = etna_bind_sampler_states; pctx->set_sampler_views = etna_set_sampler_views; pctx->texture_barrier = etna_texture_barrier; - etna_texture_state_init(pctx); + + if (screen->specs.halti >= 5) + etna_texture_desc_init(pctx); + else + etna_texture_state_init(pctx); } diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_texture.h b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_texture.h index e982ee551..e2e9d2b51 100644 --- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_texture.h +++ b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_texture.h @@ -61,4 +61,8 @@ etna_texture_handle_incompatible(struct pipe_context *pctx, struct pipe_resource uint32_t active_samplers_bits(struct etna_context *ctx); +/* update TS / cache for a sampler if required */ +void +etna_update_sampler_source(struct pipe_sampler_view *view, int num); + #endif diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_tiling.c b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_tiling.c index f4f85c1d6..113b39cc9 100644 --- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_tiling.c +++ b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_tiling.c @@ -68,7 +68,9 @@ etna_texture_tile(void *dest, void *src, unsigned basex, unsigned basey, unsigned dst_stride, unsigned width, unsigned height, unsigned src_stride, unsigned elmtsize) { - if (elmtsize == 4) { + if (elmtsize == 8) { + DO_TILE(uint64_t) + } else if (elmtsize == 4) { DO_TILE(uint32_t) } else if (elmtsize == 2) { DO_TILE(uint16_t) @@ -84,7 +86,9 @@ etna_texture_untile(void *dest, void *src, unsigned basex, unsigned basey, unsigned src_stride, unsigned width, unsigned height, unsigned dst_stride, unsigned elmtsize) { - if (elmtsize == 4) { + if (elmtsize == 8) { + DO_UNTILE(uint64_t) + } else if (elmtsize == 4) { DO_UNTILE(uint32_t); } else if (elmtsize == 2) { DO_UNTILE(uint16_t); diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_transfer.c b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_transfer.c index de2d6ed9b..0d0324ec0 100644 --- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_transfer.c +++ b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_transfer.c @@ -35,7 +35,7 @@ #include "pipe/p_format.h" #include "pipe/p_screen.h" #include "pipe/p_state.h" -#include "util/u_format.h" +#include "util/format/u_format.h" #include "util/u_inlines.h" #include "util/u_memory.h" #include "util/u_surface.h" @@ -174,6 +174,14 @@ etna_transfer_unmap(struct pipe_context *pctx, struct pipe_transfer *ptrans) if (!trans->rsc && !(ptrans->usage & PIPE_TRANSFER_UNSYNCHRONIZED)) etna_bo_cpu_fini(rsc->bo); + if ((ptrans->resource->target == PIPE_BUFFER) && + (ptrans->usage & PIPE_TRANSFER_WRITE)) { + util_range_add(&rsc->base, + &rsc->valid_buffer_range, + ptrans->box.x, + ptrans->box.x + ptrans->box.width); + } + pipe_resource_reference(&trans->rsc, NULL); pipe_resource_reference(&ptrans->resource, NULL); slab_free(&ctx->transfer_pool, trans); @@ -187,6 +195,7 @@ etna_transfer_map(struct pipe_context *pctx, struct pipe_resource *prsc, struct pipe_transfer **out_transfer) { struct etna_context *ctx = etna_context(pctx); + struct etna_screen *screen = ctx->screen; struct etna_resource *rsc = etna_resource(prsc); struct etna_transfer *trans; struct pipe_transfer *ptrans; @@ -199,13 +208,16 @@ etna_transfer_map(struct pipe_context *pctx, struct pipe_resource *prsc, /* slab_alloc() doesn't zero */ memset(trans, 0, sizeof(*trans)); - ptrans = &trans->base; - pipe_resource_reference(&ptrans->resource, prsc); - ptrans->level = level; - ptrans->usage = usage; - ptrans->box = *box; - - assert(level <= prsc->last_level); + /* + * Upgrade to UNSYNCHRONIZED if target is PIPE_BUFFER and range is uninitialized. + */ + if ((usage & PIPE_TRANSFER_WRITE) && + (prsc->target == PIPE_BUFFER) && + !util_ranges_intersect(&rsc->valid_buffer_range, + box->x, + box->x + box->width)) { + usage |= PIPE_TRANSFER_UNSYNCHRONIZED; + } /* Upgrade DISCARD_RANGE to WHOLE_RESOURCE if the whole resource is * being mapped. If we add buffer reallocation to avoid CPU/GPU sync this @@ -221,6 +233,25 @@ etna_transfer_map(struct pipe_context *pctx, struct pipe_resource *prsc, usage |= PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE; } + ptrans = &trans->base; + pipe_resource_reference(&ptrans->resource, prsc); + ptrans->level = level; + ptrans->usage = usage; + ptrans->box = *box; + + assert(level <= prsc->last_level); + + /* This one is a little tricky: if we have a separate render resource, which + * is newer than the base resource we want the transfer to target this one, + * to get the most up-to-date content, but only if we don't have a texture + * target of the same age, as transfering in/out of the texture target is + * generally preferred for the reasons listed below */ + if (rsc->render && etna_resource_newer(etna_resource(rsc->render), rsc) && + (!rsc->texture || etna_resource_newer(etna_resource(rsc->render), + etna_resource(rsc->texture)))) { + rsc = etna_resource(rsc->render); + } + if (rsc->texture && !etna_resource_newer(rsc, etna_resource(rsc->texture))) { /* We have a texture resource which is the same age or newer than the * render resource. Use the texture resource, which avoids bouncing @@ -228,7 +259,7 @@ etna_transfer_map(struct pipe_context *pctx, struct pipe_resource *prsc, rsc = etna_resource(rsc->texture); } else if (rsc->ts_bo || (rsc->layout != ETNA_LAYOUT_LINEAR && - util_format_get_blocksize(format) > 1 && + etna_resource_hw_tileable(screen->specs.use_blt, prsc) && /* HALIGN 4 resources are incompatible with the resolve engine, * so fall back to using software to detile this resource. */ rsc->halign != TEXTURE_HALIGN_FOUR)) { @@ -254,14 +285,13 @@ etna_transfer_map(struct pipe_context *pctx, struct pipe_resource *prsc, templ.bind = PIPE_BIND_RENDER_TARGET; trans->rsc = etna_resource_alloc(pctx->screen, ETNA_LAYOUT_LINEAR, - ETNA_ADDRESSING_MODE_TILED, DRM_FORMAT_MOD_LINEAR, - &templ); + DRM_FORMAT_MOD_LINEAR, &templ); if (!trans->rsc) { slab_free(&ctx->transfer_pool, trans); return NULL; } - if (!ctx->specs.use_blt) { + if (!screen->specs.use_blt) { /* Need to align the transfer region to satisfy RS restrictions, as we * really want to hit the RS blit path here. */ @@ -284,7 +314,7 @@ etna_transfer_map(struct pipe_context *pctx, struct pipe_resource *prsc, } if (!(usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE)) - etna_copy_resource_box(pctx, trans->rsc, prsc, level, &ptrans->box); + etna_copy_resource_box(pctx, trans->rsc, &rsc->base, level, &ptrans->box); /* Switch to using the temporary resource instead */ rsc = etna_resource(trans->rsc); @@ -347,7 +377,6 @@ etna_transfer_map(struct pipe_context *pctx, struct pipe_resource *prsc, * transfers without a temporary resource. */ if (trans->rsc || !(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) { - struct etna_screen *screen = ctx->screen; uint32_t prep_flags = 0; /* @@ -356,7 +385,7 @@ etna_transfer_map(struct pipe_context *pctx, struct pipe_resource *prsc, * current GPU usage (reads must wait for GPU writes, writes must have * exclusive access to the buffer). */ - mtx_lock(&screen->lock); + mtx_lock(&ctx->lock); if ((trans->rsc && (etna_resource(trans->rsc)->status & ETNA_PENDING_WRITE)) || (!trans->rsc && @@ -370,7 +399,7 @@ etna_transfer_map(struct pipe_context *pctx, struct pipe_resource *prsc, } } - mtx_unlock(&screen->lock); + mtx_unlock(&ctx->lock); if (usage & PIPE_TRANSFER_READ) prep_flags |= DRM_ETNA_PREP_READ; @@ -462,10 +491,16 @@ fail_prep: static void etna_transfer_flush_region(struct pipe_context *pctx, - struct pipe_transfer *transfer, + struct pipe_transfer *ptrans, const struct pipe_box *box) { - /* NOOP for now */ + struct etna_resource *rsc = etna_resource(ptrans->resource); + + if (ptrans->resource->target == PIPE_BUFFER) + util_range_add(&rsc->base, + &rsc->valid_buffer_range, + ptrans->box.x + box->x, + ptrans->box.x + box->x + box->width); } void diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_translate.h b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_translate.h index fd48c60a1..0638bfd5d 100644 --- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_translate.h +++ b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_translate.h @@ -36,7 +36,7 @@ #include "hw/state.xml.h" #include "hw/state_3d.xml.h" -#include "util/u_format.h" +#include "util/format/u_format.h" #include "util/u_math.h" /* Returned when there is no match of pipe value to etna value */ @@ -227,35 +227,16 @@ translate_texture_filter(unsigned filter) return TEXTURE_FILTER_NEAREST; case PIPE_TEX_FILTER_LINEAR: return TEXTURE_FILTER_LINEAR; - /* What about anisotropic? */ default: DBG("Unhandled texture filter: %i", filter); return ETNA_NO_MATCH; } } -/* return a RS "compatible" format for use when copying */ -static inline enum pipe_format -etna_compatible_rs_format(enum pipe_format fmt) -{ - /* YUYV and UYVY are blocksize 4, but 2 bytes per pixel */ - if (fmt == PIPE_FORMAT_YUYV || fmt == PIPE_FORMAT_UYVY) - return PIPE_FORMAT_B4G4R4A4_UNORM; - - switch (util_format_get_blocksize(fmt)) { - case 2: - return PIPE_FORMAT_B4G4R4A4_UNORM; - case 4: - return PIPE_FORMAT_B8G8R8A8_UNORM; - default: - return fmt; - } -} - static inline int translate_rb_src_dst_swap(enum pipe_format src, enum pipe_format dst) { - return translate_rs_format_rb_swap(src) ^ translate_rs_format_rb_swap(dst); + return translate_pe_format_rb_swap(src) ^ translate_pe_format_rb_swap(dst); } static inline uint32_t @@ -320,11 +301,33 @@ translate_vertex_format_normalize(enum pipe_format fmt) /* assumes that normalization of channel 0 holds for all channels; * this holds for all vertex formats that we support */ return desc->channel[0].normalized - ? VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_ON + ? VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_SIGN_EXTEND : VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_OFF; } static inline uint32_t +translate_output_mode(enum pipe_format fmt, bool halti5) +{ + const unsigned bits = + util_format_get_component_bits(fmt, UTIL_FORMAT_COLORSPACE_RGB, 0); + + if (bits == 32) + return COLOR_OUTPUT_MODE_UIF32; + + if (!util_format_is_pure_integer(fmt)) + return COLOR_OUTPUT_MODE_NORMAL; + + /* generic integer output mode pre-halti5 (?) */ + if (bits == 10 || !halti5) + return COLOR_OUTPUT_MODE_A2B10G10R10UI; + + if (util_format_is_pure_sint(fmt)) + return bits == 8 ? COLOR_OUTPUT_MODE_I8 : COLOR_OUTPUT_MODE_I16; + + return bits == 8 ? COLOR_OUTPUT_MODE_U8 : COLOR_OUTPUT_MODE_U16; +} + +static inline uint32_t translate_index_size(unsigned index_size) { switch (index_size) { @@ -435,32 +438,26 @@ translate_clear_depth_stencil(enum pipe_format format, float depth, return clear_value; } -/* Convert MSAA number of samples to x and y scaling factor and - * VIVS_GL_MULTI_SAMPLE_CONFIG value. +/* Convert MSAA number of samples to x and y scaling factor. * Return true if supported and false otherwise. */ static inline bool -translate_samples_to_xyscale(int num_samples, int *xscale_out, int *yscale_out, - uint32_t *config_out) +translate_samples_to_xyscale(int num_samples, int *xscale_out, int *yscale_out) { int xscale, yscale; - uint32_t config; switch (num_samples) { case 0: case 1: xscale = 1; yscale = 1; - config = VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_NONE; break; case 2: xscale = 2; yscale = 1; - config = VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_2X; break; case 4: xscale = 2; yscale = 2; - config = VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_4X; break; default: return false; @@ -470,8 +467,6 @@ translate_samples_to_xyscale(int num_samples, int *xscale_out, int *yscale_out, *xscale_out = xscale; if (yscale_out) *yscale_out = yscale; - if (config_out) - *config_out = config; return true; } @@ -497,4 +492,29 @@ translate_texture_target(unsigned target) } } +static inline uint32_t +translate_texture_compare(enum pipe_compare_func compare_func) +{ + switch (compare_func) { + case PIPE_FUNC_NEVER: + return TEXTURE_COMPARE_FUNC_NEVER; + case PIPE_FUNC_LESS: + return TEXTURE_COMPARE_FUNC_LESS; + case PIPE_FUNC_EQUAL: + return TEXTURE_COMPARE_FUNC_EQUAL; + case PIPE_FUNC_LEQUAL: + return TEXTURE_COMPARE_FUNC_LEQUAL; + case PIPE_FUNC_GREATER: + return TEXTURE_COMPARE_FUNC_GREATER; + case PIPE_FUNC_NOTEQUAL: + return TEXTURE_COMPARE_FUNC_NOTEQUAL; + case PIPE_FUNC_GEQUAL: + return TEXTURE_COMPARE_FUNC_GEQUAL; + case PIPE_FUNC_ALWAYS: + return TEXTURE_COMPARE_FUNC_ALWAYS; + default: + unreachable("Invalid compare func"); + } +} + #endif diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_uniforms.c b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_uniforms.c index 22dbd6dba..06e1a6b35 100644 --- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_uniforms.c +++ b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_uniforms.c @@ -36,10 +36,12 @@ static unsigned get_const_idx(const struct etna_context *ctx, bool frag, unsigned samp_id) { + struct etna_screen *screen = ctx->screen; + if (frag) return samp_id; - return samp_id + ctx->specs.vertex_sampler_offset; + return samp_id + screen->specs.vertex_sampler_offset; } static uint32_t @@ -63,10 +65,12 @@ etna_uniforms_write(const struct etna_context *ctx, const struct etna_shader_variant *sobj, struct pipe_constant_buffer *cb) { + struct etna_screen *screen = ctx->screen; struct etna_cmd_stream *stream = ctx->stream; const struct etna_shader_uniform_info *uinfo = &sobj->uniforms; bool frag = (sobj == ctx->shader.fs); - uint32_t base = frag ? ctx->specs.ps_uniforms_offset : ctx->specs.vs_uniforms_offset; + uint32_t base = frag ? screen->specs.ps_uniforms_offset : screen->specs.vs_uniforms_offset; + unsigned idx; if (!uinfo->imm_count) return; @@ -94,11 +98,11 @@ etna_uniforms_write(const struct etna_context *ctx, break; case ETNA_IMMEDIATE_UBO0_ADDR ... ETNA_IMMEDIATE_UBOMAX_ADDR: - assert(uinfo->imm_contents[i] == ETNA_IMMEDIATE_UBO0_ADDR); + idx = uinfo->imm_contents[i] - ETNA_IMMEDIATE_UBO0_ADDR; etna_cmd_stream_reloc(stream, &(struct etna_reloc) { - .bo = etna_resource(cb->buffer)->bo, + .bo = etna_resource(cb[idx].buffer)->bo, .flags = ETNA_RELOC_READ, - .offset = cb->buffer_offset + val, + .offset = cb[idx].buffer_offset + val, }); break; diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_util.h b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_util.h index 62f62548d..d5b4dc963 100644 --- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_util.h +++ b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_util.h @@ -30,6 +30,9 @@ /* for conditionally setting boolean flag(s): */ #define COND(bool, val) ((bool) ? (val) : 0) +#define foreach_bit(b, mask) \ + for (uint32_t _m = (mask); _m && ({(b) = u_bit_scan(&_m); 1;});) + /* align to a value divisable by granularity >= value, works only for powers of two */ static inline uint32_t etna_align_up(uint32_t value, uint32_t granularity) @@ -37,12 +40,6 @@ etna_align_up(uint32_t value, uint32_t granularity) return (value + (granularity - 1)) & (~(granularity - 1)); } -static inline uint32_t -etna_bits_ones(unsigned num) -{ - return (1 << num) - 1; -} - /* clamped float [0.0 .. 1.0] -> [0 .. 255] */ static inline uint8_t etna_cfloat_to_uint8(float f) @@ -85,6 +82,19 @@ etna_float_to_fixp55(float f) return (int32_t)(f * 32.0f + 0.5f); } +/* float to fixp 8.8 */ +static inline uint32_t +etna_float_to_fixp88(float f) +{ + if (f >= (32767.0 - 1.0f) / 256.0f) + return 32767; + + if (f < -16.0f) + return 32768; + + return (int32_t)(f * 256.0f + 0.5f); +} + /* texture size to log2 in fixp 5.5 format */ static inline uint32_t etna_log2_fixp55(unsigned width) @@ -92,6 +102,13 @@ etna_log2_fixp55(unsigned width) return etna_float_to_fixp55(logf((float)width) * RCPLOG2); } +/* texture size to log2 in fixp 8.8 format */ +static inline uint32_t +etna_log2_fixp88(unsigned width) +{ + return etna_float_to_fixp88(logf((float)width) * RCPLOG2); +} + /* float to fixp 16.16 */ static inline uint32_t etna_f32_to_fixp16(float f) diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_zsa.c b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_zsa.c index 4e72cd2ff..0684ab77a 100644 --- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_zsa.c +++ b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_zsa.c @@ -29,6 +29,7 @@ #include "etnaviv_context.h" #include "etnaviv_screen.h" #include "etnaviv_translate.h" +#include "util/u_half.h" #include "util/u_memory.h" #include "hw/common.xml.h" @@ -38,6 +39,7 @@ etna_zsa_state_create(struct pipe_context *pctx, const struct pipe_depth_stencil_alpha_state *so) { struct etna_context *ctx = etna_context(pctx); + struct etna_screen *screen = ctx->screen; struct etna_zsa_state *cs = CALLOC_STRUCT(etna_zsa_state); if (!cs) @@ -92,6 +94,15 @@ etna_zsa_state_create(struct pipe_context *pctx, if (so->depth.enabled == false || so->depth.func == PIPE_FUNC_ALWAYS) early_z = false; + /* calculate extra_reference value */ + uint32_t extra_reference = 0; + + if (VIV_FEATURE(screen, chipMinorFeatures1, HALF_FLOAT)) + extra_reference = util_float_to_half(CLAMP(so->alpha.ref_value, 0.0f, 1.0f)); + + cs->PE_STENCIL_CONFIG_EXT = + VIVS_PE_STENCIL_CONFIG_EXT_EXTRA_ALPHA_REF(extra_reference); + /* compare funcs have 1 to 1 mapping */ cs->PE_DEPTH_CONFIG = VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC(so->depth.enabled ? so->depth.func @@ -99,26 +110,32 @@ etna_zsa_state_create(struct pipe_context *pctx, COND(so->depth.writemask, VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE) | COND(early_z, VIVS_PE_DEPTH_CONFIG_EARLY_Z) | /* this bit changed meaning with HALTI5: */ - COND(disable_zs && ctx->specs.halti < 5, VIVS_PE_DEPTH_CONFIG_DISABLE_ZS); + COND(disable_zs && screen->specs.halti < 5, VIVS_PE_DEPTH_CONFIG_DISABLE_ZS); cs->PE_ALPHA_OP = COND(so->alpha.enabled, VIVS_PE_ALPHA_OP_ALPHA_TEST) | VIVS_PE_ALPHA_OP_ALPHA_FUNC(so->alpha.func) | VIVS_PE_ALPHA_OP_ALPHA_REF(etna_cfloat_to_uint8(so->alpha.ref_value)); - cs->PE_STENCIL_OP = - VIVS_PE_STENCIL_OP_FUNC_FRONT(so->stencil[0].func) | - VIVS_PE_STENCIL_OP_FUNC_BACK(so->stencil[1].func) | - VIVS_PE_STENCIL_OP_FAIL_FRONT(translate_stencil_op(so->stencil[0].fail_op)) | - VIVS_PE_STENCIL_OP_FAIL_BACK(translate_stencil_op(so->stencil[1].fail_op)) | - VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT(translate_stencil_op(so->stencil[0].zfail_op)) | - VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK(translate_stencil_op(so->stencil[1].zfail_op)) | - VIVS_PE_STENCIL_OP_PASS_FRONT(translate_stencil_op(so->stencil[0].zpass_op)) | - VIVS_PE_STENCIL_OP_PASS_BACK(translate_stencil_op(so->stencil[1].zpass_op)); - cs->PE_STENCIL_CONFIG = - translate_stencil_mode(so->stencil[0].enabled, so->stencil[1].enabled) | - VIVS_PE_STENCIL_CONFIG_MASK_FRONT(so->stencil[0].valuemask) | - VIVS_PE_STENCIL_CONFIG_WRITE_MASK_FRONT(so->stencil[0].writemask); - /* XXX back masks in VIVS_PE_DEPTH_CONFIG_EXT? */ - /* XXX VIVS_PE_STENCIL_CONFIG_REF_FRONT comes from pipe_stencil_ref */ + + for (unsigned i = 0; i < 2; i++) { + const struct pipe_stencil_state *stencil_front = (so->stencil[1].enabled && so->stencil[1].valuemask) ? &so->stencil[i] : &so->stencil[0]; + const struct pipe_stencil_state *stencil_back = (so->stencil[1].enabled && so->stencil[1].valuemask) ? &so->stencil[!i] : &so->stencil[0]; + cs->PE_STENCIL_OP[i] = + VIVS_PE_STENCIL_OP_FUNC_FRONT(stencil_front->func) | + VIVS_PE_STENCIL_OP_FUNC_BACK(stencil_back->func) | + VIVS_PE_STENCIL_OP_FAIL_FRONT(translate_stencil_op(stencil_front->fail_op)) | + VIVS_PE_STENCIL_OP_FAIL_BACK(translate_stencil_op(stencil_back->fail_op)) | + VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT(translate_stencil_op(stencil_front->zfail_op)) | + VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK(translate_stencil_op(stencil_back->zfail_op)) | + VIVS_PE_STENCIL_OP_PASS_FRONT(translate_stencil_op(stencil_front->zpass_op)) | + VIVS_PE_STENCIL_OP_PASS_BACK(translate_stencil_op(stencil_back->zpass_op)); + cs->PE_STENCIL_CONFIG[i] = + translate_stencil_mode(so->stencil[0].enabled, so->stencil[0].enabled) | + VIVS_PE_STENCIL_CONFIG_MASK_FRONT(stencil_front->valuemask) | + VIVS_PE_STENCIL_CONFIG_WRITE_MASK_FRONT(stencil_front->writemask); + cs->PE_STENCIL_CONFIG_EXT2[i] = + VIVS_PE_STENCIL_CONFIG_EXT2_MASK_BACK(stencil_back->valuemask) | + VIVS_PE_STENCIL_CONFIG_EXT2_WRITE_MASK_BACK(stencil_back->writemask); + } /* XXX does alpha/stencil test affect PE_COLOR_FORMAT_OVERWRITE? */ return cs; diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_zsa.h b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_zsa.h index 953a6a78b..061a5f46b 100644 --- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_zsa.h +++ b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_zsa.h @@ -35,8 +35,11 @@ struct etna_zsa_state { uint32_t PE_DEPTH_CONFIG; uint32_t PE_ALPHA_OP; - uint32_t PE_STENCIL_OP; - uint32_t PE_STENCIL_CONFIG; + uint32_t PE_STENCIL_OP[2]; + uint32_t PE_STENCIL_CONFIG[2]; + uint32_t PE_STENCIL_CONFIG_EXT; + uint32_t PE_STENCIL_CONFIG_EXT2[2]; + }; static inline struct etna_zsa_state * diff --git a/lib/mesa/src/gallium/drivers/etnaviv/hw/cmdstream.xml.h b/lib/mesa/src/gallium/drivers/etnaviv/hw/cmdstream.xml.h index 002b94b03..bfab93869 100644 --- a/lib/mesa/src/gallium/drivers/etnaviv/hw/cmdstream.xml.h +++ b/lib/mesa/src/gallium/drivers/etnaviv/hw/cmdstream.xml.h @@ -8,9 +8,9 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng git clone git://0x04.net/rules-ng-ng The rules-ng-ng source files this header was generated from are: -- cmdstream.xml ( 16930 bytes, from 2019-01-07 09:52:31) -- copyright.xml ( 1597 bytes, from 2019-01-07 09:52:31) -- common.xml ( 35468 bytes, from 2019-01-07 09:52:31) +- cmdstream.xml ( 16930 bytes, from 2019-01-04 11:37:39) +- copyright.xml ( 1597 bytes, from 2018-02-10 13:09:26) +- common.xml ( 35468 bytes, from 2020-01-04 20:02:31) Copyright (C) 2012-2019 by the following authors: - Wladimir J. van der Laan <laanwj@gmail.com> diff --git a/lib/mesa/src/gallium/drivers/etnaviv/hw/common.xml.h b/lib/mesa/src/gallium/drivers/etnaviv/hw/common.xml.h index 81e855bd3..44c458541 100644 --- a/lib/mesa/src/gallium/drivers/etnaviv/hw/common.xml.h +++ b/lib/mesa/src/gallium/drivers/etnaviv/hw/common.xml.h @@ -8,12 +8,12 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng git clone git://0x04.net/rules-ng-ng The rules-ng-ng source files this header was generated from are: -- texdesc_3d.xml ( 3183 bytes, from 2019-01-07 09:52:31) -- copyright.xml ( 1597 bytes, from 2019-01-07 09:52:31) -- common.xml ( 35468 bytes, from 2019-01-07 09:52:31) -- common_3d.xml ( 14322 bytes, from 2019-08-19 14:35:07) +- texdesc_3d.xml ( 3183 bytes, from 2018-02-10 13:09:26) +- copyright.xml ( 1597 bytes, from 2018-02-10 13:09:26) +- common.xml ( 35468 bytes, from 2020-01-04 20:02:31) +- common_3d.xml ( 15058 bytes, from 2020-04-17 16:31:50) -Copyright (C) 2012-2019 by the following authors: +Copyright (C) 2012-2020 by the following authors: - Wladimir J. van der Laan <laanwj@gmail.com> - Christian Gmeiner <christian.gmeiner@gmail.com> - Lucas Stach <l.stach@pengutronix.de> diff --git a/lib/mesa/src/gallium/drivers/etnaviv/hw/isa.xml.h b/lib/mesa/src/gallium/drivers/etnaviv/hw/isa.xml.h index b5bf753c0..b75e6e393 100644 --- a/lib/mesa/src/gallium/drivers/etnaviv/hw/isa.xml.h +++ b/lib/mesa/src/gallium/drivers/etnaviv/hw/isa.xml.h @@ -8,10 +8,10 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng git clone git://0x04.net/rules-ng-ng The rules-ng-ng source files this header was generated from are: -- isa.xml ( 38205 bytes, from 2019-08-19 14:35:07) -- copyright.xml ( 1597 bytes, from 2019-01-07 09:52:31) +- isa.xml ( 38205 bytes, from 2020-01-10 14:36:29) +- copyright.xml ( 1597 bytes, from 2018-02-10 13:09:26) -Copyright (C) 2012-2019 by the following authors: +Copyright (C) 2012-2020 by the following authors: - Wladimir J. van der Laan <laanwj@gmail.com> - Christian Gmeiner <christian.gmeiner@gmail.com> - Lucas Stach <l.stach@pengutronix.de> diff --git a/lib/mesa/src/gallium/drivers/etnaviv/hw/state.xml.h b/lib/mesa/src/gallium/drivers/etnaviv/hw/state.xml.h index d29627999..20cccfc7d 100644 --- a/lib/mesa/src/gallium/drivers/etnaviv/hw/state.xml.h +++ b/lib/mesa/src/gallium/drivers/etnaviv/hw/state.xml.h @@ -8,17 +8,17 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng git clone git://0x04.net/rules-ng-ng The rules-ng-ng source files this header was generated from are: -- state.xml ( 26666 bytes, from 2019-08-19 14:35:07) -- common.xml ( 35468 bytes, from 2019-01-07 09:52:31) -- common_3d.xml ( 14322 bytes, from 2019-08-19 14:35:07) -- state_hi.xml ( 30232 bytes, from 2019-01-07 09:52:31) -- copyright.xml ( 1597 bytes, from 2019-01-07 09:52:31) -- state_2d.xml ( 51552 bytes, from 2019-01-07 09:52:31) -- state_3d.xml ( 83505 bytes, from 2019-08-19 14:46:17) -- state_blt.xml ( 14252 bytes, from 2019-08-19 14:35:07) -- state_vg.xml ( 5975 bytes, from 2019-01-07 09:52:31) - -Copyright (C) 2012-2019 by the following authors: +- state.xml ( 26877 bytes, from 2020-02-14 10:19:56) +- common.xml ( 35468 bytes, from 2020-01-04 20:02:31) +- common_3d.xml ( 15058 bytes, from 2020-04-17 16:31:50) +- state_hi.xml ( 34851 bytes, from 2020-04-17 16:25:34) +- copyright.xml ( 1597 bytes, from 2018-02-10 13:09:26) +- state_2d.xml ( 51552 bytes, from 2018-02-10 13:09:26) +- state_3d.xml ( 83771 bytes, from 2020-04-17 17:15:55) +- state_blt.xml ( 14252 bytes, from 2020-01-10 14:36:29) +- state_vg.xml ( 5975 bytes, from 2018-02-10 13:09:26) + +Copyright (C) 2012-2020 by the following authors: - Wladimir J. van der Laan <laanwj@gmail.com> - Christian Gmeiner <christian.gmeiner@gmail.com> - Lucas Stach <l.stach@pengutronix.de> @@ -379,7 +379,7 @@ DEALINGS IN THE SOFTWARE. #define VIVS_GL_OCCLUSION_QUERY_CONTROL 0x00003830 -#define VIVS_GL_UNK03834 0x00003834 +#define VIVS_GL_VARYING_NUM_COMPONENTS2 0x00003834 #define VIVS_GL_UNK03838 0x00003838 diff --git a/lib/mesa/src/gallium/drivers/etnaviv/hw/state_3d.xml.h b/lib/mesa/src/gallium/drivers/etnaviv/hw/state_3d.xml.h index 222a3aa54..7c0c60767 100644 --- a/lib/mesa/src/gallium/drivers/etnaviv/hw/state_3d.xml.h +++ b/lib/mesa/src/gallium/drivers/etnaviv/hw/state_3d.xml.h @@ -8,17 +8,17 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng git clone git://0x04.net/rules-ng-ng The rules-ng-ng source files this header was generated from are: -- state.xml ( 26666 bytes, from 2019-08-19 14:35:07) -- common.xml ( 35468 bytes, from 2019-01-07 09:52:31) -- common_3d.xml ( 14322 bytes, from 2019-08-19 14:35:07) -- state_hi.xml ( 30232 bytes, from 2019-01-07 09:52:31) -- copyright.xml ( 1597 bytes, from 2019-01-07 09:52:31) -- state_2d.xml ( 51552 bytes, from 2019-01-07 09:52:31) -- state_3d.xml ( 83505 bytes, from 2019-08-19 14:46:17) -- state_blt.xml ( 14252 bytes, from 2019-08-19 14:35:07) -- state_vg.xml ( 5975 bytes, from 2019-01-07 09:52:31) - -Copyright (C) 2012-2019 by the following authors: +- state.xml ( 26877 bytes, from 2020-02-14 10:19:56) +- common.xml ( 35468 bytes, from 2020-01-04 20:02:31) +- common_3d.xml ( 15058 bytes, from 2020-04-17 16:31:50) +- state_hi.xml ( 34851 bytes, from 2020-04-17 16:25:34) +- copyright.xml ( 1597 bytes, from 2018-02-10 13:09:26) +- state_2d.xml ( 51552 bytes, from 2018-02-10 13:09:26) +- state_3d.xml ( 83771 bytes, from 2020-04-17 17:15:55) +- state_blt.xml ( 14252 bytes, from 2020-01-10 14:36:29) +- state_vg.xml ( 5975 bytes, from 2018-02-10 13:09:26) + +Copyright (C) 2012-2020 by the following authors: - Wladimir J. van der Laan <laanwj@gmail.com> - Christian Gmeiner <christian.gmeiner@gmail.com> - Lucas Stach <l.stach@pengutronix.de> @@ -167,6 +167,7 @@ DEALINGS IN THE SOFTWARE. #define VIVS_VS_INPUT_COUNT_UNK8__MASK 0x00001f00 #define VIVS_VS_INPUT_COUNT_UNK8__SHIFT 8 #define VIVS_VS_INPUT_COUNT_UNK8(x) (((x) << VIVS_VS_INPUT_COUNT_UNK8__SHIFT) & VIVS_VS_INPUT_COUNT_UNK8__MASK) +#define VIVS_VS_INPUT_COUNT_ID_ENABLE 0x80000000 #define VIVS_VS_TEMP_REGISTER_CONTROL 0x0000080c #define VIVS_VS_TEMP_REGISTER_CONTROL_NUM_TEMPS__MASK 0x0000003f @@ -1024,9 +1025,9 @@ DEALINGS IN THE SOFTWARE. #define VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK(x) (((x) << VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK__SHIFT) & VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK__MASK) #define VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK_MASK 0x00000100 #define VIVS_PE_STENCIL_CONFIG_EXT_UNK16_MASK 0x00000200 -#define VIVS_PE_STENCIL_CONFIG_EXT_UNK16__MASK 0xffff0000 -#define VIVS_PE_STENCIL_CONFIG_EXT_UNK16__SHIFT 16 -#define VIVS_PE_STENCIL_CONFIG_EXT_UNK16(x) (((x) << VIVS_PE_STENCIL_CONFIG_EXT_UNK16__SHIFT) & VIVS_PE_STENCIL_CONFIG_EXT_UNK16__MASK) +#define VIVS_PE_STENCIL_CONFIG_EXT_EXTRA_ALPHA_REF__MASK 0xffff0000 +#define VIVS_PE_STENCIL_CONFIG_EXT_EXTRA_ALPHA_REF__SHIFT 16 +#define VIVS_PE_STENCIL_CONFIG_EXT_EXTRA_ALPHA_REF(x) (((x) << VIVS_PE_STENCIL_CONFIG_EXT_EXTRA_ALPHA_REF__SHIFT) & VIVS_PE_STENCIL_CONFIG_EXT_EXTRA_ALPHA_REF__MASK) #define VIVS_PE_LOGIC_OP 0x000014a4 #define VIVS_PE_LOGIC_OP_OP__MASK 0x0000000f @@ -1233,6 +1234,7 @@ DEALINGS IN THE SOFTWARE. #define VIVS_RS_SOURCE_STRIDE_STRIDE__MASK 0x0003ffff #define VIVS_RS_SOURCE_STRIDE_STRIDE__SHIFT 0 #define VIVS_RS_SOURCE_STRIDE_STRIDE(x) (((x) << VIVS_RS_SOURCE_STRIDE_STRIDE__SHIFT) & VIVS_RS_SOURCE_STRIDE_STRIDE__MASK) +#define VIVS_RS_SOURCE_STRIDE_UNK29 0x20000000 #define VIVS_RS_SOURCE_STRIDE_MULTI 0x40000000 #define VIVS_RS_SOURCE_STRIDE_TILING 0x80000000 @@ -1476,7 +1478,7 @@ DEALINGS IN THE SOFTWARE. #define VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT__SHIFT 10 #define VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT(x) (((x) << VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT__SHIFT) & VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT__MASK) #define VIVS_TE_SAMPLER_LOG_SIZE_ASTC 0x10000000 -#define VIVS_TE_SAMPLER_LOG_SIZE_RGB 0x20000000 +#define VIVS_TE_SAMPLER_LOG_SIZE_INT_FILTER 0x20000000 #define VIVS_TE_SAMPLER_LOG_SIZE_SRGB 0x80000000 #define VIVS_TE_SAMPLER_LOD_CONFIG(i0) (0x000020c0 + 0x4*(i0)) @@ -1536,6 +1538,27 @@ DEALINGS IN THE SOFTWARE. #define VIVS_TE_SAMPLER_UNK02240(i0) (0x00002240 + 0x4*(i0)) +#define VIVS_TE_SAMPLER_ASTC0(i0) (0x00002280 + 0x4*(i0)) +#define VIVS_TE_SAMPLER_ASTC0_ASTC_FORMAT__MASK 0x0000000f +#define VIVS_TE_SAMPLER_ASTC0_ASTC_FORMAT__SHIFT 0 +#define VIVS_TE_SAMPLER_ASTC0_ASTC_FORMAT(x) (((x) << VIVS_TE_SAMPLER_ASTC0_ASTC_FORMAT__SHIFT) & VIVS_TE_SAMPLER_ASTC0_ASTC_FORMAT__MASK) +#define VIVS_TE_SAMPLER_ASTC0_ASTC_SRGB 0x00000010 +#define VIVS_TE_SAMPLER_ASTC0_UNK8__MASK 0x0000ff00 +#define VIVS_TE_SAMPLER_ASTC0_UNK8__SHIFT 8 +#define VIVS_TE_SAMPLER_ASTC0_UNK8(x) (((x) << VIVS_TE_SAMPLER_ASTC0_UNK8__SHIFT) & VIVS_TE_SAMPLER_ASTC0_UNK8__MASK) +#define VIVS_TE_SAMPLER_ASTC0_UNK16__MASK 0x00ff0000 +#define VIVS_TE_SAMPLER_ASTC0_UNK16__SHIFT 16 +#define VIVS_TE_SAMPLER_ASTC0_UNK16(x) (((x) << VIVS_TE_SAMPLER_ASTC0_UNK16__SHIFT) & VIVS_TE_SAMPLER_ASTC0_UNK16__MASK) +#define VIVS_TE_SAMPLER_ASTC0_UNK24__MASK 0xff000000 +#define VIVS_TE_SAMPLER_ASTC0_UNK24__SHIFT 24 +#define VIVS_TE_SAMPLER_ASTC0_UNK24(x) (((x) << VIVS_TE_SAMPLER_ASTC0_UNK24__SHIFT) & VIVS_TE_SAMPLER_ASTC0_UNK24__MASK) + +#define VIVS_TE_SAMPLER_ASTC1(i0) (0x00002300 + 0x4*(i0)) + +#define VIVS_TE_SAMPLER_ASTC2(i0) (0x00002380 + 0x4*(i0)) + +#define VIVS_TE_SAMPLER_ASTC3(i0) (0x00002340 + 0x4*(i0)) + #define VIVS_TE_SAMPLER_LOD_ADDR(i0, i1) (0x00002400 + 0x4*(i0) + 0x40*(i1)) #define VIVS_TE_SAMPLER_LOD_ADDR__ESIZE 0x00000040 #define VIVS_TE_SAMPLER_LOD_ADDR__LEN 0x0000000e @@ -1599,7 +1622,7 @@ DEALINGS IN THE SOFTWARE. #define VIVS_NTE_SAMPLER_LOG_SIZE_HEIGHT__SHIFT 10 #define VIVS_NTE_SAMPLER_LOG_SIZE_HEIGHT(x) (((x) << VIVS_NTE_SAMPLER_LOG_SIZE_HEIGHT__SHIFT) & VIVS_NTE_SAMPLER_LOG_SIZE_HEIGHT__MASK) #define VIVS_NTE_SAMPLER_LOG_SIZE_ASTC 0x10000000 -#define VIVS_NTE_SAMPLER_LOG_SIZE_RGB 0x20000000 +#define VIVS_NTE_SAMPLER_LOG_SIZE_INT_FILTER 0x20000000 #define VIVS_NTE_SAMPLER_LOG_SIZE_SRGB 0x80000000 #define VIVS_NTE_SAMPLER_LOD_CONFIG(i0) (0x00010180 + 0x4*(i0)) @@ -1616,7 +1639,9 @@ DEALINGS IN THE SOFTWARE. #define VIVS_NTE_SAMPLER_UNK10200(i0) (0x00010200 + 0x4*(i0)) -#define VIVS_NTE_SAMPLER_UNK10280(i0) (0x00010280 + 0x4*(i0)) +#define VIVS_NTE_SAMPLER_LINEAR_STRIDE(i0, i1) (0x00010280 + 0x4*(i0) + 0x4*(i1)) +#define VIVS_NTE_SAMPLER_LINEAR_STRIDE__ESIZE 0x00000004 +#define VIVS_NTE_SAMPLER_LINEAR_STRIDE__LEN 0x00000020 #define VIVS_NTE_SAMPLER_3D_CONFIG(i0) (0x00010300 + 0x4*(i0)) #define VIVS_NTE_SAMPLER_3D_CONFIG_DEPTH__MASK 0x00003fff @@ -1678,16 +1703,20 @@ DEALINGS IN THE SOFTWARE. #define VIVS_NTE_SAMPLER_ASTC2(i0) (0x00010600 + 0x4*(i0)) -#define VIVS_NTE_SAMPLER_ASTC3(i0) (0x00010600 + 0x4*(i0)) +#define VIVS_NTE_SAMPLER_ASTC3(i0) (0x00010680 + 0x4*(i0)) #define VIVS_NTE_SAMPLER_BASELOD(i0) (0x00010700 + 0x4*(i0)) -#define VIVS_NTE_SAMPLER_BASELOD_UNK23 0x00800000 #define VIVS_NTE_SAMPLER_BASELOD_BASELOD__MASK 0x0000000f #define VIVS_NTE_SAMPLER_BASELOD_BASELOD__SHIFT 0 #define VIVS_NTE_SAMPLER_BASELOD_BASELOD(x) (((x) << VIVS_NTE_SAMPLER_BASELOD_BASELOD__SHIFT) & VIVS_NTE_SAMPLER_BASELOD_BASELOD__MASK) #define VIVS_NTE_SAMPLER_BASELOD_MAXLOD__MASK 0x00000f00 #define VIVS_NTE_SAMPLER_BASELOD_MAXLOD__SHIFT 8 #define VIVS_NTE_SAMPLER_BASELOD_MAXLOD(x) (((x) << VIVS_NTE_SAMPLER_BASELOD_MAXLOD__SHIFT) & VIVS_NTE_SAMPLER_BASELOD_MAXLOD__MASK) +#define VIVS_NTE_SAMPLER_BASELOD_COMPARE_ENABLE 0x00010000 +#define VIVS_NTE_SAMPLER_BASELOD_COMPARE_FUNC__MASK 0x00700000 +#define VIVS_NTE_SAMPLER_BASELOD_COMPARE_FUNC__SHIFT 20 +#define VIVS_NTE_SAMPLER_BASELOD_COMPARE_FUNC(x) (((x) << VIVS_NTE_SAMPLER_BASELOD_COMPARE_FUNC__SHIFT) & VIVS_NTE_SAMPLER_BASELOD_COMPARE_FUNC__MASK) +#define VIVS_NTE_SAMPLER_BASELOD_BASELOD_ENABLE 0x00800000 #define VIVS_NTE_SAMPLER_UNK10780(i0) (0x00010780 + 0x4*(i0)) @@ -1766,7 +1795,7 @@ DEALINGS IN THE SOFTWARE. #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_MIRROR(i0) (0x00016600 + 0x4*(i0)) -#define VIVS_NTE_DESCRIPTOR_UNK17400_MIRROR(i0) (0x00016800 + 0x4*(i0)) +#define VIVS_NTE_DESCRIPTOR_SAMP_ANISOTROPY_MIRROR(i0) (0x00016800 + 0x4*(i0)) #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0(i0) (0x00016c00 + 0x4*(i0)) #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_UWRAP__MASK 0x00000007 @@ -1790,17 +1819,10 @@ DEALINGS IN THE SOFTWARE. #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_COMPARE_ENABLE 0x00020000 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_COMPARE_FUNC__MASK 0x001c0000 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_COMPARE_FUNC__SHIFT 18 -#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_COMPARE_FUNC_LE 0x00000000 -#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_COMPARE_FUNC_GE 0x00040000 -#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_COMPARE_FUNC_LT 0x00080000 -#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_COMPARE_FUNC_GT 0x000c0000 -#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_COMPARE_FUNC_EQ 0x00100000 -#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_COMPARE_FUNC_NE 0x00140000 -#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_COMPARE_FUNC_ALWAYS 0x00180000 -#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_COMPARE_FUNC_NEVER 0x001c0000 +#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_COMPARE_FUNC(x) (((x) << VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_COMPARE_FUNC__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_COMPARE_FUNC__MASK) #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_UNK21 0x00200000 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_UNK22 0x00400000 -#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_RGB 0x00800000 +#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_INT_FILTER 0x00800000 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1(i0) (0x00016e00 + 0x4*(i0)) #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_UNK1 0x00000002 @@ -1824,7 +1846,7 @@ DEALINGS IN THE SOFTWARE. #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_BIAS(x) (((x) << VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_BIAS__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_BIAS__MASK) #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_ENABLE 0x00010000 -#define VIVS_NTE_DESCRIPTOR_UNK17400(i0) (0x00017400 + 0x4*(i0)) +#define VIVS_NTE_DESCRIPTOR_SAMP_ANISOTROPY(i0) (0x00017400 + 0x4*(i0)) #define VIVS_SH 0x00000000 |