diff options
Diffstat (limited to 'lib/mesa/src/panfrost/bifrost/ISA.xml')
| -rw-r--r-- | lib/mesa/src/panfrost/bifrost/ISA.xml | 1193 |
1 files changed, 53 insertions, 1140 deletions
diff --git a/lib/mesa/src/panfrost/bifrost/ISA.xml b/lib/mesa/src/panfrost/bifrost/ISA.xml index f1e908331..b5965fd3c 100644 --- a/lib/mesa/src/panfrost/bifrost/ISA.xml +++ b/lib/mesa/src/panfrost/bifrost/ISA.xml @@ -1986,7 +1986,7 @@ <src start="0" mask="0xfb"/> </ins> - <ins name="*NOP" mask="0x7fffff" exact="0x701963" dests="0"/> + <ins name="*NOP.i32" mask="0x7fffff" exact="0x701963"/> <ins name="*POPCOUNT.i32" mask="0x7ffff8" exact="0x73c6d8"> <src start="0" mask="0xfb"/> @@ -2036,7 +2036,6 @@ <opt>not</opt> <opt>none</opt> </mod> - <mod name="arithmetic" opt="arithmetic" size="1" start="1" pseudo="true"/> </ins> <ins name="*RSHIFT_AND.v2i16"> @@ -2057,7 +2056,6 @@ <opt>not</opt> <opt>none</opt> </mod> - <mod name="arithmetic" opt="arithmetic" size="1" start="1" pseudo="true"/> <encoding mask="0x7f3800" exact="0x300800"> <or> <eq left="lanes2" right="#b00"/> @@ -2091,7 +2089,6 @@ <src start="0" mask="0xfb"/> <src start="3" mask="0xfb"/> <src start="6"/> - <mod name="arithmetic" opt="arithmetic" size="1" start="1" pseudo="true"/> <mod name="lanes2" size="3" default="b0123"> <opt>b0123</opt> <opt>b0000</opt> @@ -2147,7 +2144,6 @@ <opt>not</opt> <opt>none</opt> </mod> - <mod name="arithmetic" opt="arithmetic" size="1" start="1" pseudo="true"/> <mod name="not_result" start="15" size="1" opt="not"/> </ins> @@ -2169,7 +2165,6 @@ <opt>none</opt> </mod> <mod name="not_result" start="15" size="1" opt="not"/> - <mod name="arithmetic" opt="arithmetic" size="1" start="1" pseudo="true"/> <encoding mask="0x7f3800" exact="0x302800"> <or> <eq left="lanes2" right="#b00"/> @@ -2215,7 +2210,6 @@ <opt>none</opt> </mod> <mod name="not_result" start="15" size="1" opt="not"/> - <mod name="arithmetic" opt="arithmetic" size="1" start="1" pseudo="true"/> <encoding mask="0x7f3800" exact="0x302000"> <neq left="lanes2" right="#b0123"/> <derived start="9" size="2"> @@ -2241,7 +2235,6 @@ <opt>b3</opt> </mod> <mod name="not_result" start="13" size="1" opt="not"/> - <mod name="arithmetic" opt="arithmetic" size="1" start="1" pseudo="true"/> </ins> <ins name="*RSHIFT_XOR.v2i16"> @@ -2258,7 +2251,6 @@ <opt>b02</opt> </mod> <mod name="not_result" start="13" size="1" opt="not"/> - <mod name="arithmetic" opt="arithmetic" size="1" start="1" pseudo="true"/> <encoding mask="0x7fd800" exact="0x320800"> <or> <eq left="lanes2" right="#b00"/> @@ -2300,7 +2292,6 @@ <opt>b3333</opt> </mod> <mod name="not_result" start="13" size="1" opt="not"/> - <mod name="arithmetic" opt="arithmetic" size="1" start="1" pseudo="true"/> <encoding mask="0x7fd800" exact="0x320000"> <neq left="lanes2" right="#b0123"/> <derived start="9" size="2"> @@ -2429,7 +2420,6 @@ <opt>rtz</opt> <opt>rtna</opt> </mod> - <mod name="ftz" start="9" size="1" opt="ftz" pseudo="true"/> <derived start="6" size="1"> <and> <eq left="abs0" right="#none"/> @@ -2496,9 +2486,6 @@ <ins name="+ATEST" staging="w=1" mask="0xfff00" exact="0xc8f00" message="atest" table="true"> <src start="0" mask="0xf7"/> <src start="3" mask="0xf7"/> - <!-- ATEST parameter datum. Implicitly encoded into the tuple on Bifrost. - Real source on Valhall. --> - <src start="6" pseudo="true"/> <mod name="widen1" start="6" size="2"> <reserved/> <opt>none</opt> @@ -2533,22 +2520,8 @@ <src start="0"/> <src start="3" mask="0xf7"/> <src start="6" mask="0xf7"/> - <!-- pseudo source for a dual source blend input --> - <src start="9" pseudo="true"/> <!-- not actually encoded, but used for IR --> <immediate name="sr_count" size="4" pseudo="true"/> - <immediate name="sr_count_2" size="4" pseudo="true"/> - <mod name="register_format" size="4" pseudo="true"> - <opt>f16</opt> - <opt>f32</opt> - <opt>s32</opt> - <opt>u32</opt> - <opt>s16</opt> - <opt>u16</opt> - <opt>f64</opt> - <opt>i64</opt> - <opt>auto</opt> - </mod> </ins> <ins name="+BRANCH.f16" mask="0xf8000" exact="0x68000" last="true" dests="0"> @@ -3716,12 +3689,12 @@ <src start="6" mask="0xf7"/> </ins> - <ins name="+CLPER_OLD.i32" mask="0xfffc0" exact="0x3f0c0"> + <ins name="+CLPER_V6.i32" mask="0xfffc0" exact="0x3f0c0"> <src start="0" mask="0x7"/> <src start="3"/> </ins> - <ins name="+CLPER.i32" mask="0xfc000" exact="0x7c000"> + <ins name="+CLPER_V7.i32" mask="0xfc000" exact="0x7c000"> <src start="0" mask="0x7"/> <src start="3"/> <mod name="lane_op" start="6" size="2"> @@ -3734,7 +3707,6 @@ <opt>subgroup2</opt> <opt>subgroup4</opt> <opt>subgroup8</opt> - <opt pseudo="true">subgroup16</opt> <!-- Only on Valhall --> </mod> <mod name="inactive_result" start="10" size="4"> <opt>zero</opt> @@ -3874,7 +3846,6 @@ <opt>h0</opt> <opt>h1</opt> </mod> - <mod name="ftz" start="9" size="1" opt="ftz" pseudo="true"/> </ins> <ins name="+F16_TO_S32"> @@ -6195,7 +6166,7 @@ <src start="6" mask="0xf7"/> </ins> - <ins name="+KABOOM" mask="0xffff8" exact="0xd7858" message="job" dests="0"> + <ins name="+KABOOM" mask="0xffff8" exact="0xd7858" unused="true" message="job_management"> <src start="0"/> </ins> @@ -6381,7 +6352,7 @@ </mod> </ins> - <ins name="+LD_TILE" staging="w=format" mask="0xff800" exact="0xcb000" message="tile"> + <ins name="+LD_TILE" staging="w=vecsize" mask="0xff800" exact="0xcb000" message="tile"> <src start="0"/> <src start="3"/> <src start="6" mask="0xf7"/> @@ -6391,15 +6362,9 @@ <opt>v3</opt> <opt>v4</opt> </mod> - <mod name="register_format" size="3" pseudo="true"> - <opt>f32</opt> - <opt>f16</opt> - <opt>u32</opt> - <opt>s32</opt> - </mod> </ins> - <ins name="+LD_VAR" staging="w=format" message="varying"> + <ins name="+LD_VAR" staging="w=vecsize" message="varying"> <src start="0"/> <src start="3"/> <mod name="vecsize" start="8" size="2"> @@ -7105,7 +7070,6 @@ <reserved/> <opt>tl</opt> </mod> - <immediate name="byte_offset" size="16" pseudo="true"/> </ins> <ins name="+LOAD.i16" staging="w=1" message="load"> @@ -7121,7 +7085,7 @@ <reserved/> <opt>tl</opt> </mod> - <mod name="lane_dest" size="2" default="h0"> + <mod name="lane0" size="2" default="h0"> <opt>h0</opt> <opt>h1</opt> <opt>w0</opt> @@ -7136,19 +7100,19 @@ <and> <eq left="extend" right="#none"/> <or> - <eq left="lane_dest" right="#h0"/> - <eq left="lane_dest" right="#h1"/> + <eq left="lane0" right="#h0"/> + <eq left="lane0" right="#h1"/> </or> </and> <derived start="9" size="1"> - <eq left="lane_dest" right="#h0"/> - <eq left="lane_dest" right="#h1"/> + <eq left="lane0" right="#h0"/> + <eq left="lane0" right="#h1"/> </derived> </encoding> <encoding mask="0xffc00" exact="0x63000"> <and> <neq left="extend" right="#none"/> - <eq left="lane_dest" right="#w0"/> + <eq left="lane0" right="#w0"/> </and> <derived start="9" size="1"> <eq left="extend" right="#sext"/> @@ -7158,14 +7122,13 @@ <encoding mask="0xffc00" exact="0x61800"> <and> <neq left="extend" right="#none"/> - <eq left="lane_dest" right="#d0"/> + <eq left="lane0" right="#d0"/> </and> <derived start="9" size="1"> <eq left="extend" right="#sext"/> <eq left="extend" right="#zext"/> </derived> </encoding> - <immediate name="byte_offset" size="16" pseudo="true"/> </ins> <ins name="+LOAD.i24" staging="w=1" mask="0xffe00" exact="0x65000" message="load"> @@ -7181,7 +7144,6 @@ <reserved/> <opt>tl</opt> </mod> - <immediate name="byte_offset" size="16" pseudo="true"/> </ins> <ins name="+LOAD.i32" staging="w=1" message="load"> @@ -7197,7 +7159,7 @@ <reserved/> <opt>tl</opt> </mod> - <mod name="lane_dest" size="1" opt="d0"/> + <mod name="lane0" size="1" opt="d0"/> <mod name="extend" size="2"> <opt>none</opt> <opt>sext</opt> @@ -7206,20 +7168,19 @@ <encoding mask="0xffe00" exact="0x60c00"> <and> <eq left="extend" right="#none"/> - <eq left="lane_dest" right="#none"/> + <eq left="lane0" right="#none"/> </and> </encoding> <encoding mask="0xffc00" exact="0x61c00"> <and> <neq left="extend" right="#none"/> - <eq left="lane_dest" right="#d0"/> + <eq left="lane0" right="#d0"/> </and> <derived start="9" size="1"> <eq left="extend" right="#sext"/> <eq left="extend" right="#zext"/> </derived> </encoding> - <immediate name="byte_offset" size="16" pseudo="true"/> </ins> <ins name="+LOAD.i48" staging="w=2" mask="0xffe00" exact="0x65200" message="load"> @@ -7235,7 +7196,6 @@ <reserved/> <opt>tl</opt> </mod> - <immediate name="byte_offset" size="16" pseudo="true"/> </ins> <ins name="+LOAD.i64" staging="w=2" mask="0xffe00" exact="0x60e00" message="load"> @@ -7251,7 +7211,6 @@ <reserved/> <opt>tl</opt> </mod> - <immediate name="byte_offset" size="16" pseudo="true"/> </ins> <ins name="+LOAD.i8" staging="w=1" message="load"> @@ -7267,7 +7226,7 @@ <reserved/> <opt>tl</opt> </mod> - <mod name="lane_dest" size="3" default="b0"> + <mod name="lane0" size="3" default="b0"> <opt>b0</opt> <opt>b1</opt> <opt>b2</opt> @@ -7286,25 +7245,25 @@ <and> <eq left="extend" right="#none"/> <or> - <eq left="lane_dest" right="#b0"/> - <eq left="lane_dest" right="#b1"/> - <eq left="lane_dest" right="#b2"/> - <eq left="lane_dest" right="#b3"/> + <eq left="lane0" right="#b0"/> + <eq left="lane0" right="#b1"/> + <eq left="lane0" right="#b2"/> + <eq left="lane0" right="#b3"/> </or> </and> <derived start="9" size="2"> - <eq left="lane_dest" right="#b0"/> - <eq left="lane_dest" right="#b1"/> - <eq left="lane_dest" right="#b2"/> - <eq left="lane_dest" right="#b3"/> + <eq left="lane0" right="#b0"/> + <eq left="lane0" right="#b1"/> + <eq left="lane0" right="#b2"/> + <eq left="lane0" right="#b3"/> </derived> </encoding> <encoding mask="0xff800" exact="0x63800"> <and> <neq left="extend" right="#none"/> <or> - <eq left="lane_dest" right="#h0"/> - <eq left="lane_dest" right="#h1"/> + <eq left="lane0" right="#h0"/> + <eq left="lane0" right="#h1"/> </or> </and> <derived start="9" size="1"> @@ -7312,14 +7271,14 @@ <eq left="extend" right="#zext"/> </derived> <derived start="10" size="1"> - <eq left="lane_dest" right="#h0"/> - <eq left="lane_dest" right="#h1"/> + <eq left="lane0" right="#h0"/> + <eq left="lane0" right="#h1"/> </derived> </encoding> <encoding mask="0xffc00" exact="0x63400"> <and> <neq left="extend" right="#none"/> - <eq left="lane_dest" right="#w0"/> + <eq left="lane0" right="#w0"/> </and> <derived start="9" size="1"> <eq left="extend" right="#sext"/> @@ -7329,14 +7288,13 @@ <encoding mask="0xffc00" exact="0x61400"> <and> <neq left="extend" right="#none"/> - <eq left="lane_dest" right="#d0"/> + <eq left="lane0" right="#d0"/> </and> <derived start="9" size="1"> <eq left="extend" right="#sext"/> <eq left="extend" right="#zext"/> </derived> </encoding> - <immediate name="byte_offset" size="16" pseudo="true"/> </ins> <ins name="+LOAD.i96" staging="w=3" mask="0xffe00" exact="0x65400" message="load"> @@ -7352,7 +7310,6 @@ <reserved/> <opt>tl</opt> </mod> - <immediate name="byte_offset" size="16" pseudo="true"/> </ins> <ins name="+LOGB.f32" mask="0xfffe0" exact="0x3d9a0"> @@ -7438,7 +7395,7 @@ </mod> </ins> - <ins name="+NOP" mask="0xfffff" exact="0x3d964" dests="0"/> + <ins name="+NOP.i32" mask="0xfffff" exact="0x3d964"/> <ins name="+QUIET.f32" mask="0xffff8" exact="0x3d970"> <src start="0"/> @@ -7562,12 +7519,11 @@ <opt>none</opt> <opt>wls</opt> <opt>stream</opt> - <opt pseudo="true">pos</opt> - <opt pseudo="true">vary</opt> + <reserved/> + <reserved/> <reserved/> <opt>tl</opt> </mod> - <immediate name="byte_offset" size="16" pseudo="true"/> </ins> <ins name="+STORE.i16" staging="r=1" mask="0xffe00" exact="0x62800" message="store" dests="0"> @@ -7578,12 +7534,11 @@ <opt>none</opt> <opt>wls</opt> <opt>stream</opt> - <opt pseudo="true">pos</opt> - <opt pseudo="true">vary</opt> + <reserved/> + <reserved/> <reserved/> <opt>tl</opt> </mod> - <immediate name="byte_offset" size="16" pseudo="true"/> </ins> <ins name="+STORE.i24" staging="r=1" mask="0xffe00" exact="0x65800" message="store" dests="0"> @@ -7594,12 +7549,11 @@ <opt>none</opt> <opt>wls</opt> <opt>stream</opt> - <opt pseudo="true">pos</opt> - <opt pseudo="true">vary</opt> + <reserved/> + <reserved/> <reserved/> <opt>tl</opt> </mod> - <immediate name="byte_offset" size="16" pseudo="true"/> </ins> <ins name="+STORE.i32" staging="r=1" mask="0xffe00" exact="0x62c00" message="store" dests="0"> @@ -7610,12 +7564,11 @@ <opt>none</opt> <opt>wls</opt> <opt>stream</opt> - <opt pseudo="true">pos</opt> - <opt pseudo="true">vary</opt> + <reserved/> + <reserved/> <reserved/> <opt>tl</opt> </mod> - <immediate name="byte_offset" size="16" pseudo="true"/> </ins> <ins name="+STORE.i48" staging="r=2" mask="0xffe00" exact="0x65a00" message="store" dests="0"> @@ -7626,12 +7579,11 @@ <opt>none</opt> <opt>wls</opt> <opt>stream</opt> - <opt pseudo="true">pos</opt> - <opt pseudo="true">vary</opt> + <reserved/> + <reserved/> <reserved/> <opt>tl</opt> </mod> - <immediate name="byte_offset" size="16" pseudo="true"/> </ins> <ins name="+STORE.i64" staging="r=2" mask="0xffe00" exact="0x62e00" message="store" dests="0"> @@ -7642,12 +7594,11 @@ <opt>none</opt> <opt>wls</opt> <opt>stream</opt> - <opt pseudo="true">pos</opt> - <opt pseudo="true">vary</opt> + <reserved/> + <reserved/> <reserved/> <opt>tl</opt> </mod> - <immediate name="byte_offset" size="16" pseudo="true"/> </ins> <ins name="+STORE.i8" staging="r=1" mask="0xffe00" exact="0x62000" message="store" dests="0"> @@ -7658,12 +7609,11 @@ <opt>none</opt> <opt>wls</opt> <opt>stream</opt> - <opt pseudo="true">pos</opt> - <opt pseudo="true">vary</opt> + <reserved/> + <reserved/> <reserved/> <opt>tl</opt> </mod> - <immediate name="byte_offset" size="16" pseudo="true"/> </ins> <ins name="+STORE.i96" staging="r=3" mask="0xffe00" exact="0x65c00" message="store" dests="0"> @@ -7674,12 +7624,11 @@ <opt>none</opt> <opt>wls</opt> <opt>stream</opt> - <opt pseudo="true">pos</opt> - <opt pseudo="true">vary</opt> + <reserved/> + <reserved/> <reserved/> <opt>tl</opt> </mod> - <immediate name="byte_offset" size="16" pseudo="true"/> </ins> <ins name="+ST_CVT" staging="r=format" mask="0xff800" exact="0xc9800" message="store" dests="0"> @@ -7704,7 +7653,7 @@ </mod> </ins> - <ins name="+ST_TILE" staging="r=format" mask="0xff800" exact="0xcb800" message="tile" dests="0"> + <ins name="+ST_TILE" staging="r=vecsize" mask="0xff800" exact="0xcb800" message="tile" dests="0"> <src start="0"/> <src start="3"/> <src start="6" mask="0xf7"/> @@ -7714,12 +7663,6 @@ <opt>v3</opt> <opt>v4</opt> </mod> - <mod name="register_format" size="3" pseudo="true"> - <opt>f32</opt> - <opt>f16</opt> - <opt>u32</opt> - <opt>s32</opt> - </mod> </ins> <ins name="+SWZ.v2i16" mask="0xfffc8" exact="0x3d948"> @@ -7753,27 +7696,6 @@ <mod name="skip" start="9" size="1" opt="skip"/> <!-- not actually encoded, but used for IR --> <immediate name="sr_count" size="4" pseudo="true"/> - <immediate name="sr_count_2" size="4" pseudo="true"/> - <mod name="lod_mode" start="13" size="1" default="zero_lod" pseudo="true"> - <opt>computed_lod</opt> - <opt>zero_lod</opt> - </mod> - </ins> - - <!-- Pseudo instruction representing dual texturing on Bifrost. Lowered to - TEXC after register allocation, when the second destination register can - be combined with the texture operation descriptor. --> - <ins name="+TEXC_DUAL" staging="rw=sr_count" pseudo="true" message="tex" dests="2"> - <src start="0"/> - <src start="3"/> - <src start="6" mask="0xf7"/> - <mod name="skip" start="9" size="1" opt="skip"/> - <immediate name="sr_count" size="4" pseudo="true"/> - <immediate name="sr_count_2" size="4" pseudo="true"/> - <mod name="lod_mode" start="13" size="1" default="zero_lod" pseudo="true"> - <opt>computed_lod</opt> - <opt>zero_lod</opt> - </mod> </ins> <ins name="+TEXS_2D.f16" staging="w=2" mask="0xfc000" exact="0xd8000" message="tex"> @@ -7959,7 +7881,6 @@ <opt>rtz</opt> <opt>rtna</opt> </mod> - <mod name="ftz" start="9" size="1" opt="ftz" pseudo="true"/> <derived start="6" size="1"> <and> <eq left="abs0" right="#none"/> @@ -8261,11 +8182,11 @@ <mod name="preserve_null" size="1" opt="preserve_null"/> </ins> - <!-- Scheduler lowered to *ATOM_C.i32/+ATOM_CX. Real Valhall instructions. --> - <ins name="+ATOM_RETURN.i32" pseudo="true" staging="rw=sr_count" message="atomic"> + <!-- Scheduler lowered to *ATOM_C.i32/+ATOM_CX --> + <ins name="+PATOM_C.i32" pseudo="true" staging="rw=sr_count" message="atomic"> <src start="0"/> <src start="3"/> - <mod name="atom_opc" start="9" size="5"> + <mod name="atom_opc" start="9" size="4"> <reserved/> <reserved/> <opt>aadd</opt> @@ -8281,14 +8202,10 @@ <opt>aand</opt> <opt>aor</opt> <opt>axor</opt> - <opt>axchg</opt> <!-- For Valhall --> - <opt>acmpxchg</opt> <!-- For Valhall --> </mod> - <!-- not actually encoded, but used for IR --> - <immediate name="sr_count" size="4" pseudo="true"/> </ins> - <ins name="+ATOM1_RETURN.i32" pseudo="true" staging="w=sr_count" message="atomic"> + <ins name="+PATOM_C1.i32" pseudo="true" staging="w=sr_count" message="atomic"> <src start="0"/> <src start="3"/> <mod name="atom_opc" start="6" size="3"> @@ -8298,32 +8215,6 @@ <opt>asmax1</opt> <opt>aor1</opt> </mod> - <!-- not actually encoded, but used for IR --> - <immediate name="sr_count" size="4" pseudo="true"/> - </ins> - - <ins name="+ATOM.i32" pseudo="true" staging="r=sr_count" message="atomic"> - <src start="0"/> - <src start="3"/> - <mod name="atom_opc" start="9" size="4"> - <reserved/> - <reserved/> - <opt>aadd</opt> - <reserved/> - <reserved/> - <reserved/> - <reserved/> - <reserved/> - <opt>asmin</opt> - <opt>asmax</opt> - <opt>aumin</opt> - <opt>aumax</opt> - <opt>aand</opt> - <opt>aor</opt> - <opt>axor</opt> - </mod> - <!-- not actually encoded, but used for IR --> - <immediate name="sr_count" size="4" pseudo="true"/> </ins> <!-- *CUBEFACE1/+CUBEFACE2 pair, two destinations, scheduler lowered --> @@ -8336,982 +8227,4 @@ <mod name="neg2" size="1" opt="neg"/> </ins> - <ins name="+IADD_IMM.i32" pseudo="true"> - <src start="0"/> - <immediate name="index" size="32"/> - </ins> - - <ins name="+IADD_IMM.v2i16" pseudo="true"> - <src start="0"/> - <immediate name="index" size="32"/> - </ins> - - <ins name="+IADD_IMM.v4i8" pseudo="true"> - <src start="0"/> - <immediate name="index" size="32"/> - </ins> - - <ins name="+FADD_IMM.f32" pseudo="true"> - <src start="0"/> - <immediate name="index" size="32"/> - </ins> - - <ins name="+FADD_IMM.v2f16" pseudo="true"> - <src start="0"/> - <immediate name="index" size="32"/> - </ins> - - <ins name="*FABSNEG.f32" pseudo="true"> - <src start="0" mask="0xfb"/> - <mod name="neg0" start="7" size="1" opt="neg"/> - <mod name="abs0" start="12" size="1" opt="abs"/> - <mod name="widen0" size="2"> - <opt>none</opt> - <opt>h0</opt> - <opt>h1</opt> - </mod> - </ins> - - <ins name="*FABSNEG.v2f16" pseudo="true"> - <src start="0" mask="0xfb"/> - <mod name="abs0" size="1" opt="abs"/> - <mod name="neg0" start="7" size="1" opt="neg"/> - <mod name="swz0" start="9" size="2" default="h01"> - <opt>h00</opt> - <opt>h10</opt> - <opt>h01</opt> - <opt>h11</opt> - </mod> - </ins> - - <ins name="*FCLAMP.f32" pseudo="true"> - <src start="0" mask="0xfb"/> - <mod name="clamp" start="15" size="2"> - <opt>none</opt> - <opt>clamp_0_inf</opt> - <opt>clamp_m1_1</opt> - <opt>clamp_0_1</opt> - </mod> - </ins> - - <ins name="*FCLAMP.v2f16" pseudo="true"> - <src start="0" mask="0xfb"/> - <mod name="clamp" start="15" size="2"> - <opt>none</opt> - <opt>clamp_0_inf</opt> - <opt>clamp_m1_1</opt> - <opt>clamp_0_1</opt> - </mod> - </ins> - - <ins name="+DISCARD.b32" pseudo="true" dests="0"> - <src start="0"/> - <mod name="widen0" size="2"> - <opt>none</opt> - <opt>h0</opt> - <opt>h1</opt> - </mod> - </ins> - - <ins name="+TEX_SINGLE" staging="rw=sr_count" message="tex" pseudo="true"> - <src start="0"/> - <src start="1"/> - <immediate name="sr_count" size="4" pseudo="true"/> - <mod name="texel_offset" start="9" size="1" opt="texel_offset"/> - <mod name="skip" start="9" size="1" opt="skip"/> - <mod name="shadow" start="9" size="1" opt="shadow"/> - <mod name="array_enable" start="9" size="1" opt="array_enable"/> - <mod name="dimension" start="9" size="2"> - <opt>1d</opt> - <opt>2d</opt> - <opt>3d</opt> - <opt>cube</opt> - </mod> - <mod name="write_mask" start="9" size="4"> - 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