diff options
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/libdrm/Makefile.inc | 4 | ||||
| -rw-r--r-- | lib/libdrm/intel/intel_aub.h | 76 | ||||
| -rw-r--r-- | lib/libdrm/intel/intel_bufmgr.h | 3 | ||||
| -rw-r--r-- | lib/libdrm/intel/intel_bufmgr_gem.c | 27 | ||||
| -rw-r--r-- | lib/libdrm/intel/intel_chipset.h | 101 | ||||
| -rw-r--r-- | lib/libdrm/intel/shlib_version | 2 | ||||
| -rw-r--r-- | lib/libdrm/radeon/r600_pci_ids.h | 26 | ||||
| -rw-r--r-- | lib/libdrm/radeon/radeon_surface.c | 3 | ||||
| -rw-r--r-- | lib/libdrm/shlib_version | 2 | ||||
| -rw-r--r-- | lib/libdrm/xf86drmMode.c | 15 | ||||
| -rw-r--r-- | lib/libdrm/xf86drmMode.h | 1 |
11 files changed, 206 insertions, 54 deletions
diff --git a/lib/libdrm/Makefile.inc b/lib/libdrm/Makefile.inc index 47e70466e..ef3a4f56f 100644 --- a/lib/libdrm/Makefile.inc +++ b/lib/libdrm/Makefile.inc @@ -1,6 +1,6 @@ -# $OpenBSD: Makefile.inc,v 1.6 2013/06/20 09:55:30 jsg Exp $ +# $OpenBSD: Makefile.inc,v 1.7 2013/07/08 09:10:05 jsg Exp $ -PACKAGE_VERSION= 2.4.45 +PACKAGE_VERSION= 2.4.46 NOPROFILE= diff --git a/lib/libdrm/intel/intel_aub.h b/lib/libdrm/intel/intel_aub.h index a36fd53a5..5f0aba8e6 100644 --- a/lib/libdrm/intel/intel_aub.h +++ b/lib/libdrm/intel/intel_aub.h @@ -93,29 +93,59 @@ #define AUB_TRACE_MEMTYPE_GTT_ENTRY (4 << 16) /* DW2 */ -// operation = TRACE_DATA_WRITE, Type = TRACE_DATA_WRITE_GENERAL_STATE -#define AUB_TRACE_GENERAL_STATE_MASK 0x000000ff - -#define AUB_TRACE_VS_STATE 0x00000001 -#define AUB_TRACE_GS_STATE 0x00000002 -#define AUB_TRACE_CL_STATE 0x00000003 -#define AUB_TRACE_SF_STATE 0x00000004 -#define AUB_TRACE_WM_STATE 0x00000005 -#define AUB_TRACE_CC_STATE 0x00000006 -#define AUB_TRACE_CL_VP 0x00000007 -#define AUB_TRACE_SF_VP 0x00000008 -#define AUB_TRACE_CC_VP 0x00000009 -#define AUB_TRACE_SAMPLER_STATE 0x0000000a -#define AUB_TRACE_KERNEL 0x0000000b -#define AUB_TRACE_SCRATCH 0x0000000c -#define AUB_TRACE_SDC 0x0000000d -#define AUB_TRACE_BLEND_STATE 0x00000016 -#define AUB_TRACE_DEPTH_STENCIL_STATE 0x00000017 - -// operation = TRACE_DATA_WRITE, Type = TRACE_DATA_WRITE_SURFACE_STATE -#define AUB_TRACE_SURFACE_STATE_MASK 0x00000ff00 -#define AUB_TRACE_BINDING_TABLE 0x000000100 -#define AUB_TRACE_SURFACE_STATE 0x000000200 + +/** + * aub_state_struct_type enum values are encoded with the top 16 bits + * representing the type to be delivered to the .aub file, and the bottom 16 + * bits representing the subtype. This macro performs the encoding. + */ +#define ENCODE_SS_TYPE(type, subtype) (((type) << 16) | (subtype)) + +enum aub_state_struct_type { + AUB_TRACE_VS_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 1), + AUB_TRACE_GS_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 2), + AUB_TRACE_CLIP_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 3), + AUB_TRACE_SF_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 4), + AUB_TRACE_WM_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 5), + AUB_TRACE_CC_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 6), + AUB_TRACE_CLIP_VP_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 7), + AUB_TRACE_SF_VP_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 8), + AUB_TRACE_CC_VP_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0x9), + AUB_TRACE_SAMPLER_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0xa), + AUB_TRACE_KERNEL_INSTRUCTIONS = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0xb), + AUB_TRACE_SCRATCH_SPACE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0xc), + AUB_TRACE_SAMPLER_DEFAULT_COLOR = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0xd), + + AUB_TRACE_SCISSOR_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0x15), + AUB_TRACE_BLEND_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0x16), + AUB_TRACE_DEPTH_STENCIL_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0x17), + + AUB_TRACE_VERTEX_BUFFER = ENCODE_SS_TYPE(AUB_TRACE_TYPE_VERTEX_BUFFER, 0), + AUB_TRACE_BINDING_TABLE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE, 0x100), + AUB_TRACE_SURFACE_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE, 0x200), + AUB_TRACE_VS_CONSTANTS = ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER, 0), + AUB_TRACE_WM_CONSTANTS = ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER, 1), +}; + +#undef ENCODE_SS_TYPE + +/** + * Decode a aub_state_struct_type value to determine the type that should be + * stored in the .aub file. + */ +static inline uint32_t AUB_TRACE_TYPE(enum aub_state_struct_type ss_type) +{ + return (ss_type & 0xFFFF0000) >> 16; +} + +/** + * Decode a state_struct_type value to determine the subtype that should be + * stored in the .aub file. + */ +static inline uint32_t AUB_TRACE_SUBTYPE(enum aub_state_struct_type ss_type) +{ + return ss_type & 0xFFFF; +} /* DW3: address */ /* DW4: len */ diff --git a/lib/libdrm/intel/intel_bufmgr.h b/lib/libdrm/intel/intel_bufmgr.h index 8d7f2390d..15f818e75 100644 --- a/lib/libdrm/intel/intel_bufmgr.h +++ b/lib/libdrm/intel/intel_bufmgr.h @@ -171,6 +171,9 @@ int drm_intel_gem_bo_get_reloc_count(drm_intel_bo *bo); void drm_intel_gem_bo_clear_relocs(drm_intel_bo *bo, int start); void drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable); +void +drm_intel_bufmgr_gem_set_aub_filename(drm_intel_bufmgr *bufmgr, + const char *filename); void drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable); void drm_intel_gem_bo_aub_dump_bmp(drm_intel_bo *bo, int x1, int y1, int width, int height, diff --git a/lib/libdrm/intel/intel_bufmgr_gem.c b/lib/libdrm/intel/intel_bufmgr_gem.c index 4df3cf4d7..0a42b719b 100644 --- a/lib/libdrm/intel/intel_bufmgr_gem.c +++ b/lib/libdrm/intel/intel_bufmgr_gem.c @@ -130,6 +130,7 @@ typedef struct _drm_intel_bufmgr_gem { unsigned int has_vebox : 1; bool fenced_relocs; + char *aub_filename; FILE *aub_file; uint32_t aub_offset; } drm_intel_bufmgr_gem; @@ -1580,6 +1581,7 @@ drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr) free(bufmgr_gem->exec_objects); #endif free(bufmgr_gem->exec_bos); + free(bufmgr_gem->aub_filename); pthread_mutex_destroy(&bufmgr_gem->lock); @@ -2879,6 +2881,23 @@ drm_intel_bufmgr_gem_get_devid(drm_intel_bufmgr *bufmgr) } /** + * Sets the AUB filename. + * + * This function has to be called before drm_intel_bufmgr_gem_set_aub_dump() + * for it to have any effect. + */ +void +drm_intel_bufmgr_gem_set_aub_filename(drm_intel_bufmgr *bufmgr, + const char *filename) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr; + + free(bufmgr_gem->aub_filename); + if (filename) + bufmgr_gem->aub_filename = strdup(filename); +} + +/** * Sets up AUB dumping. * * This is a trace file format that can be used with the simulator. @@ -2893,18 +2912,24 @@ drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable) int entry = 0x200003; int i; int gtt_size = 0x10000; + const char *filename; if (!enable) { if (bufmgr_gem->aub_file) { fclose(bufmgr_gem->aub_file); bufmgr_gem->aub_file = NULL; } + return; } if (geteuid() != getuid()) return; - bufmgr_gem->aub_file = fopen("intel.aub", "w+"); + if (bufmgr_gem->aub_filename) + filename = bufmgr_gem->aub_filename; + else + filename = "intel.aub"; + bufmgr_gem->aub_file = fopen(filename, "w+"); if (!bufmgr_gem->aub_file) return; diff --git a/lib/libdrm/intel/intel_chipset.h b/lib/libdrm/intel/intel_chipset.h index 5aea3f2b0..aeb439eb4 100644 --- a/lib/libdrm/intel/intel_chipset.h +++ b/lib/libdrm/intel/intel_chipset.h @@ -90,40 +90,64 @@ #define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */ #define PCI_CHIP_HASWELL_GT2 0x0412 -#define PCI_CHIP_HASWELL_GT2_PLUS 0x0422 +#define PCI_CHIP_HASWELL_GT3 0x0422 #define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */ #define PCI_CHIP_HASWELL_M_GT2 0x0416 -#define PCI_CHIP_HASWELL_M_GT2_PLUS 0x0426 +#define PCI_CHIP_HASWELL_M_GT3 0x0426 #define PCI_CHIP_HASWELL_S_GT1 0x040A /* Server */ #define PCI_CHIP_HASWELL_S_GT2 0x041A -#define PCI_CHIP_HASWELL_S_GT2_PLUS 0x042A +#define PCI_CHIP_HASWELL_S_GT3 0x042A +#define PCI_CHIP_HASWELL_B_GT1 0x040B /* Reserved */ +#define PCI_CHIP_HASWELL_B_GT2 0x041B +#define PCI_CHIP_HASWELL_B_GT3 0x042B +#define PCI_CHIP_HASWELL_E_GT1 0x040E /* Reserved */ +#define PCI_CHIP_HASWELL_E_GT2 0x041E +#define PCI_CHIP_HASWELL_E_GT3 0x042E #define PCI_CHIP_HASWELL_SDV_GT1 0x0C02 /* Desktop */ #define PCI_CHIP_HASWELL_SDV_GT2 0x0C12 -#define PCI_CHIP_HASWELL_SDV_GT2_PLUS 0x0C22 +#define PCI_CHIP_HASWELL_SDV_GT3 0x0C22 #define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06 /* Mobile */ #define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16 -#define PCI_CHIP_HASWELL_SDV_M_GT2_PLUS 0x0C26 +#define PCI_CHIP_HASWELL_SDV_M_GT3 0x0C26 #define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A /* Server */ #define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A -#define PCI_CHIP_HASWELL_SDV_S_GT2_PLUS 0x0C2A +#define PCI_CHIP_HASWELL_SDV_S_GT3 0x0C2A +#define PCI_CHIP_HASWELL_SDV_B_GT1 0x0C0B /* Reserved */ +#define PCI_CHIP_HASWELL_SDV_B_GT2 0x0C1B +#define PCI_CHIP_HASWELL_SDV_B_GT3 0x0C2B +#define PCI_CHIP_HASWELL_SDV_E_GT1 0x0C0E /* Reserved */ +#define PCI_CHIP_HASWELL_SDV_E_GT2 0x0C1E +#define PCI_CHIP_HASWELL_SDV_E_GT3 0x0C2E #define PCI_CHIP_HASWELL_ULT_GT1 0x0A02 /* Desktop */ #define PCI_CHIP_HASWELL_ULT_GT2 0x0A12 -#define PCI_CHIP_HASWELL_ULT_GT2_PLUS 0x0A22 +#define PCI_CHIP_HASWELL_ULT_GT3 0x0A22 #define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 /* Mobile */ #define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16 -#define PCI_CHIP_HASWELL_ULT_M_GT2_PLUS 0x0A26 +#define PCI_CHIP_HASWELL_ULT_M_GT3 0x0A26 #define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */ #define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A -#define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A +#define PCI_CHIP_HASWELL_ULT_S_GT3 0x0A2A +#define PCI_CHIP_HASWELL_ULT_B_GT1 0x0A0B /* Reserved */ +#define PCI_CHIP_HASWELL_ULT_B_GT2 0x0A1B +#define PCI_CHIP_HASWELL_ULT_B_GT3 0x0A2B +#define PCI_CHIP_HASWELL_ULT_E_GT1 0x0A0E /* Reserved */ +#define PCI_CHIP_HASWELL_ULT_E_GT2 0x0A1E +#define PCI_CHIP_HASWELL_ULT_E_GT3 0x0A2E #define PCI_CHIP_HASWELL_CRW_GT1 0x0D02 /* Desktop */ #define PCI_CHIP_HASWELL_CRW_GT2 0x0D12 -#define PCI_CHIP_HASWELL_CRW_GT2_PLUS 0x0D22 +#define PCI_CHIP_HASWELL_CRW_GT3 0x0D22 #define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D06 /* Mobile */ #define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D16 -#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D26 +#define PCI_CHIP_HASWELL_CRW_M_GT3 0x0D26 #define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A /* Server */ #define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A -#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D2A +#define PCI_CHIP_HASWELL_CRW_S_GT3 0x0D2A +#define PCI_CHIP_HASWELL_CRW_B_GT1 0x0D0B /* Reserved */ +#define PCI_CHIP_HASWELL_CRW_B_GT2 0x0D1B +#define PCI_CHIP_HASWELL_CRW_B_GT3 0x0D2B +#define PCI_CHIP_HASWELL_CRW_E_GT1 0x0D0E /* Reserved */ +#define PCI_CHIP_HASWELL_CRW_E_GT2 0x0D1E +#define PCI_CHIP_HASWELL_CRW_E_GT3 0x0D2E #define PCI_CHIP_VALLEYVIEW_PO 0x0f30 /* VLV PO board */ #define PCI_CHIP_VALLEYVIEW_1 0x0f31 @@ -210,42 +234,67 @@ #define IS_HSW_GT1(devid) ((devid) == PCI_CHIP_HASWELL_GT1 || \ (devid) == PCI_CHIP_HASWELL_M_GT1 || \ (devid) == PCI_CHIP_HASWELL_S_GT1 || \ + (devid) == PCI_CHIP_HASWELL_B_GT1 || \ + (devid) == PCI_CHIP_HASWELL_E_GT1 || \ (devid) == PCI_CHIP_HASWELL_SDV_GT1 || \ (devid) == PCI_CHIP_HASWELL_SDV_M_GT1 || \ (devid) == PCI_CHIP_HASWELL_SDV_S_GT1 || \ + (devid) == PCI_CHIP_HASWELL_SDV_B_GT1 || \ + (devid) == PCI_CHIP_HASWELL_SDV_E_GT1 || \ (devid) == PCI_CHIP_HASWELL_ULT_GT1 || \ (devid) == PCI_CHIP_HASWELL_ULT_M_GT1 || \ (devid) == PCI_CHIP_HASWELL_ULT_S_GT1 || \ + (devid) == PCI_CHIP_HASWELL_ULT_B_GT1 || \ + (devid) == PCI_CHIP_HASWELL_ULT_E_GT1 || \ (devid) == PCI_CHIP_HASWELL_CRW_GT1 || \ (devid) == PCI_CHIP_HASWELL_CRW_M_GT1 || \ - (devid) == PCI_CHIP_HASWELL_CRW_S_GT1) + (devid) == PCI_CHIP_HASWELL_CRW_S_GT1 || \ + (devid) == PCI_CHIP_HASWELL_CRW_B_GT1 || \ + (devid) == PCI_CHIP_HASWELL_CRW_E_GT1) #define IS_HSW_GT2(devid) ((devid) == PCI_CHIP_HASWELL_GT2 || \ (devid) == PCI_CHIP_HASWELL_M_GT2 || \ (devid) == PCI_CHIP_HASWELL_S_GT2 || \ + (devid) == PCI_CHIP_HASWELL_B_GT2 || \ + (devid) == PCI_CHIP_HASWELL_E_GT2 || \ (devid) == PCI_CHIP_HASWELL_SDV_GT2 || \ (devid) == PCI_CHIP_HASWELL_SDV_M_GT2 || \ (devid) == PCI_CHIP_HASWELL_SDV_S_GT2 || \ + (devid) == PCI_CHIP_HASWELL_SDV_B_GT2 || \ + (devid) == PCI_CHIP_HASWELL_SDV_E_GT2 || \ (devid) == PCI_CHIP_HASWELL_ULT_GT2 || \ (devid) == PCI_CHIP_HASWELL_ULT_M_GT2 || \ (devid) == PCI_CHIP_HASWELL_ULT_S_GT2 || \ + (devid) == PCI_CHIP_HASWELL_ULT_B_GT2 || \ + (devid) == PCI_CHIP_HASWELL_ULT_E_GT2 || \ (devid) == PCI_CHIP_HASWELL_CRW_GT2 || \ (devid) == PCI_CHIP_HASWELL_CRW_M_GT2 || \ (devid) == PCI_CHIP_HASWELL_CRW_S_GT2 || \ - (devid) == PCI_CHIP_HASWELL_GT2_PLUS || \ - (devid) == PCI_CHIP_HASWELL_M_GT2_PLUS || \ - (devid) == PCI_CHIP_HASWELL_S_GT2_PLUS || \ - (devid) == PCI_CHIP_HASWELL_SDV_GT2_PLUS || \ - (devid) == PCI_CHIP_HASWELL_SDV_M_GT2_PLUS || \ - (devid) == PCI_CHIP_HASWELL_SDV_S_GT2_PLUS || \ - (devid) == PCI_CHIP_HASWELL_ULT_GT2_PLUS || \ - (devid) == PCI_CHIP_HASWELL_ULT_M_GT2_PLUS || \ - (devid) == PCI_CHIP_HASWELL_ULT_S_GT2_PLUS || \ - (devid) == PCI_CHIP_HASWELL_CRW_GT2_PLUS || \ - (devid) == PCI_CHIP_HASWELL_CRW_M_GT2_PLUS || \ - (devid) == PCI_CHIP_HASWELL_CRW_S_GT2_PLUS) + (devid) == PCI_CHIP_HASWELL_CRW_B_GT2 || \ + (devid) == PCI_CHIP_HASWELL_CRW_E_GT2) +#define IS_HSW_GT3(devid) ((devid) == PCI_CHIP_HASWELL_GT3 || \ + (devid) == PCI_CHIP_HASWELL_M_GT3 || \ + (devid) == PCI_CHIP_HASWELL_S_GT3 || \ + (devid) == PCI_CHIP_HASWELL_B_GT3 || \ + (devid) == PCI_CHIP_HASWELL_E_GT3 || \ + (devid) == PCI_CHIP_HASWELL_SDV_GT3 || \ + (devid) == PCI_CHIP_HASWELL_SDV_M_GT3 || \ + (devid) == PCI_CHIP_HASWELL_SDV_S_GT3 || \ + (devid) == PCI_CHIP_HASWELL_SDV_B_GT3 || \ + (devid) == PCI_CHIP_HASWELL_SDV_E_GT3 || \ + (devid) == PCI_CHIP_HASWELL_ULT_GT3 || \ + (devid) == PCI_CHIP_HASWELL_ULT_M_GT3 || \ + (devid) == PCI_CHIP_HASWELL_ULT_S_GT3 || \ + (devid) == PCI_CHIP_HASWELL_ULT_B_GT3 || \ + (devid) == PCI_CHIP_HASWELL_ULT_E_GT3 || \ + (devid) == PCI_CHIP_HASWELL_CRW_GT3 || \ + (devid) == PCI_CHIP_HASWELL_CRW_M_GT3 || \ + (devid) == PCI_CHIP_HASWELL_CRW_S_GT3 || \ + (devid) == PCI_CHIP_HASWELL_CRW_B_GT3 || \ + (devid) == PCI_CHIP_HASWELL_CRW_E_GT3) #define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \ - IS_HSW_GT2(devid)) + IS_HSW_GT2(devid) || \ + IS_HSW_GT3(devid)) #define IS_9XX(dev) (IS_GEN3(dev) || \ IS_GEN4(dev) || \ diff --git a/lib/libdrm/intel/shlib_version b/lib/libdrm/intel/shlib_version index ba5a3fee5..b363be444 100644 --- a/lib/libdrm/intel/shlib_version +++ b/lib/libdrm/intel/shlib_version @@ -1,2 +1,2 @@ major=2 -minor=2 +minor=3 diff --git a/lib/libdrm/radeon/r600_pci_ids.h b/lib/libdrm/radeon/r600_pci_ids.h index 01c900f1a..fbadb8271 100644 --- a/lib/libdrm/radeon/r600_pci_ids.h +++ b/lib/libdrm/radeon/r600_pci_ids.h @@ -398,3 +398,29 @@ CHIPSET(0x6664, HAINAN_6664, HAINAN) CHIPSET(0x6665, HAINAN_6665, HAINAN) CHIPSET(0x6667, HAINAN_6667, HAINAN) CHIPSET(0x666F, HAINAN_666F, HAINAN) + +CHIPSET(0x6640, BONAIRE_6640, BONAIRE) +CHIPSET(0x6641, BONAIRE_6641, BONAIRE) +CHIPSET(0x6649, BONAIRE_6649, BONAIRE) +CHIPSET(0x6650, BONAIRE_6650, BONAIRE) +CHIPSET(0x6651, BONAIRE_6651, BONAIRE) +CHIPSET(0x6658, BONAIRE_6658, BONAIRE) +CHIPSET(0x665C, BONAIRE_665C, BONAIRE) +CHIPSET(0x665D, BONAIRE_665D, BONAIRE) + +CHIPSET(0x9830, KABINI_9830, KABINI) +CHIPSET(0x9831, KABINI_9831, KABINI) +CHIPSET(0x9832, KABINI_9832, KABINI) +CHIPSET(0x9833, KABINI_9833, KABINI) +CHIPSET(0x9834, KABINI_9834, KABINI) +CHIPSET(0x9835, KABINI_9835, KABINI) +CHIPSET(0x9836, KABINI_9836, KABINI) +CHIPSET(0x9837, KABINI_9837, KABINI) +CHIPSET(0x9838, KABINI_9838, KABINI) +CHIPSET(0x9839, KABINI_9839, KABINI) +CHIPSET(0x983A, KABINI_983A, KABINI) +CHIPSET(0x983B, KABINI_983B, KABINI) +CHIPSET(0x983C, KABINI_983C, KABINI) +CHIPSET(0x983D, KABINI_983D, KABINI) +CHIPSET(0x983E, KABINI_983E, KABINI) +CHIPSET(0x983F, KABINI_983F, KABINI) diff --git a/lib/libdrm/radeon/radeon_surface.c b/lib/libdrm/radeon/radeon_surface.c index a74064c46..818e26a9d 100644 --- a/lib/libdrm/radeon/radeon_surface.c +++ b/lib/libdrm/radeon/radeon_surface.c @@ -74,6 +74,9 @@ enum radeon_family { CHIP_VERDE, CHIP_OLAND, CHIP_HAINAN, + CHIP_BONAIRE, + CHIP_KAVERI, + CHIP_KABINI, CHIP_LAST, }; diff --git a/lib/libdrm/shlib_version b/lib/libdrm/shlib_version index 83a67c373..b25072f4e 100644 --- a/lib/libdrm/shlib_version +++ b/lib/libdrm/shlib_version @@ -1,2 +1,2 @@ major=3 -minor=2 +minor=3 diff --git a/lib/libdrm/xf86drmMode.c b/lib/libdrm/xf86drmMode.c index c2b777abe..27b2f155a 100644 --- a/lib/libdrm/xf86drmMode.c +++ b/lib/libdrm/xf86drmMode.c @@ -400,6 +400,21 @@ int drmModeSetCursor(int fd, uint32_t crtcId, uint32_t bo_handle, uint32_t width return DRM_IOCTL(fd, DRM_IOCTL_MODE_CURSOR, &arg); } +int drmModeSetCursor2(int fd, uint32_t crtcId, uint32_t bo_handle, uint32_t width, uint32_t height, int32_t hot_x, int32_t hot_y) +{ + struct drm_mode_cursor2 arg; + + arg.flags = DRM_MODE_CURSOR_BO; + arg.crtc_id = crtcId; + arg.width = width; + arg.height = height; + arg.handle = bo_handle; + arg.hot_x = hot_x; + arg.hot_y = hot_y; + + return DRM_IOCTL(fd, DRM_IOCTL_MODE_CURSOR2, &arg); +} + int drmModeMoveCursor(int fd, uint32_t crtcId, int x, int y) { struct drm_mode_cursor arg; diff --git a/lib/libdrm/xf86drmMode.h b/lib/libdrm/xf86drmMode.h index 8e4003405..f8a817cd5 100644 --- a/lib/libdrm/xf86drmMode.h +++ b/lib/libdrm/xf86drmMode.h @@ -378,6 +378,7 @@ int drmModeSetCrtc(int fd, uint32_t crtcId, uint32_t bufferId, */ int drmModeSetCursor(int fd, uint32_t crtcId, uint32_t bo_handle, uint32_t width, uint32_t height); +int drmModeSetCursor2(int fd, uint32_t crtcId, uint32_t bo_handle, uint32_t width, uint32_t height, int32_t hot_x, int32_t hot_y); /** * Move the cursor on crtc */ |