From d6d2a2060930919a1a41a7d7d8dfc9836c78445c Mon Sep 17 00:00:00 2001
From: Jonathan Gray <jsg@cvs.openbsd.org>
Date: Wed, 9 Jul 2014 20:35:21 +0000
Subject: Import Mesa 10.2.3

---
 .../drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp  |  2 +-
 .../nouveau/codegen/nv50_ir_lowering_nv50.cpp      | 10 ----
 .../nouveau/codegen/nv50_ir_lowering_nvc0.cpp      | 42 +++++------------
 .../drivers/nouveau/codegen/nv50_ir_peephole.cpp   |  4 --
 .../gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp | 15 +-----
 .../nouveau/codegen/nv50_ir_target_nv50.cpp        |  2 +-
 .../nouveau/codegen/nv50_ir_target_nvc0.cpp        |  2 +-
 .../drivers/nouveau/codegen/nv50_ir_util.cpp       |  8 ++--
 .../gallium/drivers/nouveau/codegen/nv50_ir_util.h |  1 -
 .../gallium/drivers/nouveau/nouveau_vp3_video.h    |  2 -
 .../gallium/drivers/nouveau/nouveau_vp3_video_vp.c | 46 +++---------------
 .../src/gallium/drivers/nouveau/nv50/nv50_state.c  |  7 +--
 .../drivers/nouveau/nv50/nv50_state_validate.c     |  8 ++--
 .../gallium/drivers/nouveau/nv50/nv50_surface.c    | 16 +++----
 .../gallium/drivers/nouveau/nv50/nv50_transfer.c   |  2 -
 .../src/gallium/drivers/nouveau/nv50/nv84_video.c  | 15 +++---
 .../gallium/drivers/nouveau/nv50/nv84_video_bsp.c  |  5 --
 .../gallium/drivers/nouveau/nv50/nv98_video_bsp.c  | 39 +--------------
 .../gallium/drivers/nouveau/nv50/nv98_video_vp.c   |  1 +
 .../gallium/drivers/nouveau/nvc0/nvc0_miptree.c    |  1 +
 .../gallium/drivers/nouveau/nvc0/nvc0_program.c    |  2 +-
 .../src/gallium/drivers/nouveau/nvc0/nvc0_video.c  | 10 ++--
 .../gallium/drivers/nouveau/nvc0/nvc0_video_bsp.c  | 47 +-----------------
 .../gallium/drivers/nouveau/nvc0/nvc0_video_vp.c   |  1 +
 .../src/gallium/drivers/radeon/r600_pipe_common.c  | 55 ++++++----------------
 .../src/gallium/drivers/radeon/r600_pipe_common.h  |  1 -
 dist/Mesa/src/gallium/drivers/radeon/r600_query.c  | 28 -----------
 .../Mesa/src/gallium/drivers/radeon/r600_texture.c |  9 ++--
 dist/Mesa/src/gallium/drivers/radeonsi/si_blit.c   |  9 +---
 .../Mesa/src/gallium/drivers/radeonsi/si_compute.c |  6 +--
 .../src/gallium/drivers/radeonsi/si_descriptors.c  |  6 +--
 dist/Mesa/src/gallium/drivers/radeonsi/si_dma.c    |  3 +-
 .../src/gallium/drivers/radeonsi/si_hw_context.c   |  2 +-
 dist/Mesa/src/gallium/drivers/radeonsi/si_pipe.h   |  2 +-
 dist/Mesa/src/gallium/drivers/radeonsi/si_shader.c | 12 ++---
 .../state_trackers/clover/core/timestamp.cpp       |  1 -
 dist/Mesa/src/mesa/drivers/common/meta_blit.c      |  4 +-
 .../src/mesa/drivers/common/meta_generate_mipmap.c | 12 -----
 .../src/mesa/drivers/dri/i965/gen8_surface_state.c | 54 +++------------------
 39 files changed, 100 insertions(+), 392 deletions(-)

(limited to 'dist/Mesa/src')

diff --git a/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp b/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
index 200fe1ff0..2ba3c1c8e 100644
--- a/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+++ b/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -2504,7 +2504,7 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
       break;
    case TGSI_OPCODE_TXB2:
    case TGSI_OPCODE_TXL2:
-      handleTEX(dst0, 2, 2, 0x10, 0x0f, 0x00, 0x00);
+      handleTEX(dst0, 2, 2, 0x10, 0x11, 0x00, 0x00);
       break;
    case TGSI_OPCODE_SAMPLE:
    case TGSI_OPCODE_SAMPLE_B:
diff --git a/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp b/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp
index e28342484..ed06def24 100644
--- a/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp
+++ b/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp
@@ -797,16 +797,6 @@ NV50LoweringPreSSA::handleTXB(TexInstruction *i)
    const CondCode cc[4] = { CC_EQU, CC_S, CC_C, CC_O };
    int l, d;
 
-   // We can't actually apply bias *and* do a compare for a cube
-   // texture. Since the compare has to be done before the filtering, just
-   // drop the bias on the floor.
-   if (i->tex.target == TEX_TARGET_CUBE_SHADOW) {
-      i->op = OP_TEX;
-      i->setSrc(3, i->getSrc(4));
-      i->setSrc(4, NULL);
-      return handleTEX(i);
-   }
-
    handleTEX(i);
    Value *bias = i->getSrc(i->tex.target.getArgCount());
    if (bias->isUniform())
diff --git a/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index 793393dd1..0b439ddf3 100644
--- a/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -26,7 +26,6 @@
 #include "codegen/nv50_ir_target_nvc0.h"
 
 #include <limits>
-#include <tr1/unordered_set>
 
 namespace nv50_ir {
 
@@ -149,8 +148,7 @@ private:
    bool insertTextureBarriers(Function *);
    inline bool insnDominatedBy(const Instruction *, const Instruction *) const;
    void findFirstUses(const Instruction *tex, const Instruction *def,
-                      std::list<TexUse>&,
-                      std::tr1::unordered_set<const Instruction *>&);
+                      std::list<TexUse>&);
    void findOverwritingDefs(const Instruction *tex, Instruction *insn,
                             const BasicBlock *term,
                             std::list<TexUse>&);
@@ -232,29 +230,15 @@ NVC0LegalizePostRA::findOverwritingDefs(const Instruction *texi,
 }
 
 void
-NVC0LegalizePostRA::findFirstUses(
-      const Instruction *texi,
-      const Instruction *insn,
-      std::list<TexUse> &uses,
-      std::tr1::unordered_set<const Instruction *>& visited)
+NVC0LegalizePostRA::findFirstUses(const Instruction *texi,
+                                  const Instruction *insn,
+                                  std::list<TexUse> &uses)
 {
    for (int d = 0; insn->defExists(d); ++d) {
       Value *v = insn->getDef(d);
       for (Value::UseIterator u = v->uses.begin(); u != v->uses.end(); ++u) {
          Instruction *usei = (*u)->getInsn();
 
-         // NOTE: In case of a loop that overwrites a value but never uses
-         // it, it can happen that we have a cycle of uses that consists only
-         // of phis and no-op moves and will thus cause an infinite loop here
-         // since these are not considered actual uses.
-         // The most obvious (and perhaps the only) way to prevent this is to
-         // remember which instructions we've already visited.
-
-         if (visited.find(usei) != visited.end())
-            continue;
-
-         visited.insert(usei);
-
          if (usei->op == OP_PHI || usei->op == OP_UNION) {
             // need a barrier before WAW cases
             for (int s = 0; usei->srcExists(s); ++s) {
@@ -269,11 +253,11 @@ NVC0LegalizePostRA::findFirstUses(
              usei->op == OP_PHI ||
              usei->op == OP_UNION) {
             // these uses don't manifest in the machine code
-            findFirstUses(texi, usei, uses, visited);
+            findFirstUses(texi, usei, uses);
          } else
          if (usei->op == OP_MOV && usei->getDef(0)->equals(usei->getSrc(0)) &&
              usei->subOp != NV50_IR_SUBOP_MOV_FINAL) {
-            findFirstUses(texi, usei, uses, visited);
+            findFirstUses(texi, usei, uses);
          } else {
             addTexUse(uses, usei, insn);
          }
@@ -329,10 +313,8 @@ NVC0LegalizePostRA::insertTextureBarriers(Function *fn)
    uses = new std::list<TexUse>[texes.size()];
    if (!uses)
       return false;
-   for (size_t i = 0; i < texes.size(); ++i) {
-      std::tr1::unordered_set<const Instruction *> visited;
-      findFirstUses(texes[i], texes[i], uses[i], visited);
-   }
+   for (size_t i = 0; i < texes.size(); ++i)
+      findFirstUses(texes[i], texes[i], uses[i]);
 
    // determine the barrier level at each use
    for (size_t i = 0; i < texes.size(); ++i) {
@@ -832,7 +814,6 @@ NVC0LoweringPass::handleManualTXD(TexInstruction *i)
    Value *zero = bld.loadImm(bld.getSSA(), 0);
    int l, c;
    const int dim = i->tex.target.getDim();
-   const int array = i->tex.target.isArray();
 
    i->op = OP_TEX; // no need to clone dPdx/dPdy later
 
@@ -843,7 +824,7 @@ NVC0LoweringPass::handleManualTXD(TexInstruction *i)
    for (l = 0; l < 4; ++l) {
       // mov coordinates from lane l to all lanes
       for (c = 0; c < dim; ++c)
-         bld.mkQuadop(0x00, crd[c], l, i->getSrc(c + array), zero);
+         bld.mkQuadop(0x00, crd[c], l, i->getSrc(c), zero);
       // add dPdx from lane l to lanes dx
       for (c = 0; c < dim; ++c)
          bld.mkQuadop(qOps[l][0], crd[c], l, i->dPdx[c].get(), crd[c]);
@@ -853,7 +834,7 @@ NVC0LoweringPass::handleManualTXD(TexInstruction *i)
       // texture
       bld.insert(tex = cloneForward(func, i));
       for (c = 0; c < dim; ++c)
-         tex->setSrc(c + array, crd[c]);
+         tex->setSrc(c, crd[c]);
       // save results
       for (c = 0; i->defExists(c); ++c) {
          Instruction *mov;
@@ -889,8 +870,7 @@ NVC0LoweringPass::handleTXD(TexInstruction *txd)
    if (dim > 2 ||
        txd->tex.target.isCube() ||
        arg > 4 ||
-       txd->tex.target.isShadow() ||
-       txd->tex.useOffsets)
+       txd->tex.target.isShadow())
       return handleManualTXD(txd);
 
    for (int c = 0; c < dim; ++c) {
diff --git a/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp b/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
index d51306e08..6e5b66c3b 100644
--- a/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
+++ b/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -560,10 +560,6 @@ ConstantFolding::expr(Instruction *i,
       ImmediateValue src0;
       if (i->src(0).getImmediate(src0))
          expr(i, src0, *i->getSrc(1)->asImm());
-      if (i->saturate && !prog->getTarget()->isSatSupported(i)) {
-         bld.setPosition(i, false);
-         i->setSrc(1, bld.loadImm(NULL, res.data.u32));
-      }
    } else {
       i->op = i->saturate ? OP_SAT : OP_MOV; /* SAT handled by unary() */
    }
diff --git a/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp b/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
index 814e353e5..b28408144 100644
--- a/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
+++ b/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
@@ -25,7 +25,6 @@
 
 #include <stack>
 #include <limits>
-#include <tr1/unordered_set>
 
 namespace nv50_ir {
 
@@ -1545,11 +1544,6 @@ SpillCodeInserter::run(const std::list<ValuePair>& lst)
       LValue *lval = it->first->asLValue();
       Symbol *mem = it->second ? it->second->asSym() : NULL;
 
-      // Keep track of which instructions to delete later. Deleting them
-      // inside the loop is unsafe since a single instruction may have
-      // multiple destinations that all need to be spilled (like OP_SPLIT).
-      std::tr1::unordered_set<Instruction *> to_del;
-
       for (Value::DefIterator d = lval->defs.begin(); d != lval->defs.end();
            ++d) {
          Value *slot = mem ?
@@ -1582,7 +1576,7 @@ SpillCodeInserter::run(const std::list<ValuePair>& lst)
             d = lval->defs.erase(d);
             --d;
             if (slot->reg.file == FILE_MEMORY_LOCAL)
-               to_del.insert(defi);
+               delete_Instruction(func->getProgram(), defi);
             else
                defi->setDef(0, slot);
          } else {
@@ -1590,9 +1584,6 @@ SpillCodeInserter::run(const std::list<ValuePair>& lst)
          }
       }
 
-      for (std::tr1::unordered_set<Instruction *>::const_iterator it = to_del.begin();
-           it != to_del.end(); ++it)
-         delete_Instruction(func->getProgram(), *it);
    }
 
    // TODO: We're not trying to reuse old slots in a potential next iteration.
@@ -1663,10 +1654,6 @@ RegAlloc::execFunc()
            ret && i <= func->loopNestingBound;
            sequence = func->cfg.nextSequence(), ++i)
          ret = buildLiveSets(BasicBlock::get(func->cfg.getRoot()));
-      // reset marker
-      for (ArrayList::Iterator bi = func->allBBlocks.iterator();
-           !bi.end(); bi.next())
-         BasicBlock::get(bi)->liveSet.marker = false;
       if (!ret)
          break;
       func->orderInstructions(this->insns);
diff --git a/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp b/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp
index ee2869c77..c844fa4d3 100644
--- a/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp
+++ b/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp
@@ -448,7 +448,7 @@ TargetNV50::isModSupported(const Instruction *insn, int s, Modifier mod) const
          return false;
       }
    }
-   if (s >= 3)
+   if (s > 3)
       return false;
    return (mod & Modifier(opInfo[insn->op].srcMods[s])) == mod;
 }
diff --git a/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp b/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
index fdff17c7d..395d5b5c5 100644
--- a/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
+++ b/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
@@ -417,7 +417,7 @@ TargetNVC0::isModSupported(const Instruction *insn, int s, Modifier mod) const
          return false;
       }
    }
-   if (s >= 3)
+   if (s > 3)
       return false;
    return (mod & Modifier(opInfo[insn->op].srcMods[s])) == mod;
 }
diff --git a/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_util.cpp b/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_util.cpp
index d26acb304..895977710 100644
--- a/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_util.cpp
+++ b/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_util.cpp
@@ -254,9 +254,7 @@ bool BitSet::resize(unsigned int nBits)
       return false;
    }
    if (n > p)
-      memset(&data[p], 0, (n - p) * 4);
-   if (nBits < size && (nBits % 32))
-      data[(nBits + 31) / 32 - 1] &= (1 << (nBits % 32)) - 1;
+      memset(&data[4 * p + 4], 0, (n - p) * 4);
 
    size = nBits;
    return true;
@@ -276,8 +274,8 @@ bool BitSet::allocate(unsigned int nBits, bool zero)
    if (zero)
       memset(data, 0, (size + 7) / 8);
    else
-   if (size % 32) // clear unused bits (e.g. for popCount)
-      data[(size + 31) / 32 - 1] &= (1 << (size % 32)) - 1;
+   if (nBits)
+      data[(size + 31) / 32 - 1] = 0; // clear unused bits (e.g. for popCount)
 
    return data;
 }
diff --git a/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_util.h b/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_util.h
index fa2c4804a..a4ea9d981 100644
--- a/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_util.h
+++ b/dist/Mesa/src/gallium/drivers/nouveau/codegen/nv50_ir_util.h
@@ -484,7 +484,6 @@ public:
          FREE(data);
    }
 
-   // allocate will keep old data iff size is unchanged
    bool allocate(unsigned int nBits, bool zero);
    bool resize(unsigned int nBits); // keep old data, zero additional bits
 
diff --git a/dist/Mesa/src/gallium/drivers/nouveau/nouveau_vp3_video.h b/dist/Mesa/src/gallium/drivers/nouveau/nouveau_vp3_video.h
index 279a1ce18..5c1af7104 100644
--- a/dist/Mesa/src/gallium/drivers/nouveau/nouveau_vp3_video.h
+++ b/dist/Mesa/src/gallium/drivers/nouveau/nouveau_vp3_video.h
@@ -39,8 +39,6 @@ struct nouveau_vp3_video_buffer {
 #define VP_OFFSET 0x200
 #define COMM_OFFSET 0x500
 
-#define NOUVEAU_VP3_BSP_RESERVED_SIZE 0x700
-
 #define NOUVEAU_VP3_DEBUG_FENCE 0
 
 #if NOUVEAU_VP3_DEBUG_FENCE
diff --git a/dist/Mesa/src/gallium/drivers/nouveau/nouveau_vp3_video_vp.c b/dist/Mesa/src/gallium/drivers/nouveau/nouveau_vp3_video_vp.c
index 25283b799..1dcb99c1b 100644
--- a/dist/Mesa/src/gallium/drivers/nouveau/nouveau_vp3_video_vp.c
+++ b/dist/Mesa/src/gallium/drivers/nouveau/nouveau_vp3_video_vp.c
@@ -78,10 +78,10 @@ struct mpeg4_picparm_vp {
 	uint8_t top_field_first; // bool, written to vuc
 
 	uint8_t pad4[3]; // 59, 5a, 5b, contains garbage on blob
+	uint32_t pad5[0x10]; // 5c...9c non-inclusive, but WHY?
 
-	uint32_t intra[0x10]; // 5c
-	uint32_t non_intra[0x10]; // 9c
-	uint32_t pad5[0x10]; // bc what does this do?
+	uint32_t intra[0x10]; // 9c
+	uint32_t non_intra[0x10]; // bc
 	// udc..uff pad?
 };
 
@@ -196,15 +196,11 @@ nouveau_vp3_handle_references(struct nouveau_vp3_decoder *dec, struct nouveau_vp
    /* Try to find a real empty spot first, there should be one..
     */
    for (i = 0; i < dec->base.max_references + 1; ++i) {
-      if (dec->refs[i].vidbuf == target) {
+      if (dec->refs[i].last_used != seq) {
          empty_spot = i;
          break;
-      } else if (!dec->refs[i].last_used) {
-         empty_spot = i;
-      } else if (empty_spot == ~0U && dec->refs[i].last_used != seq)
-         empty_spot = i;
+      }
    }
-
    assert(empty_spot < dec->base.max_references+1);
    dec->refs[empty_spot].last_used = seq;
 //   debug_printf("Kicked %p to add %p to slot %i\n", dec->refs[empty_spot].vidbuf, target, empty_spot);
@@ -271,6 +267,7 @@ nouveau_vp3_fill_picparm_mpeg4_vp(struct nouveau_vp3_decoder *dec,
 {
    struct mpeg4_picparm_vp pic_vp_stub = {}, *pic_vp = &pic_vp_stub;
    uint32_t ring, ret = 0x01014; // !async_shutdown << 16 | watchdog << 12 | irq_record << 4 | unk;
+   assert(!(dec->base.width & 0xf));
    *is_ref = desc->vop_coding_type <= 1;
 
    pic_vp->width = dec->base.width;
@@ -466,45 +463,14 @@ void nouveau_vp3_vp_caps(struct nouveau_vp3_decoder *dec, union pipe_desc desc,
    case PIPE_VIDEO_FORMAT_MPEG12:
       *caps = nouveau_vp3_fill_picparm_mpeg12_vp(dec, desc.mpeg12, refs, is_ref, vp);
       nouveau_vp3_handle_references(dec, refs, dec->fence_seq, target);
-      switch (desc.mpeg12->picture_structure) {
-      case PIPE_MPEG12_PICTURE_STRUCTURE_FIELD_TOP:
-         dec->refs[target->valid_ref].decoded_top = 1;
-         break;
-      case PIPE_MPEG12_PICTURE_STRUCTURE_FIELD_BOTTOM:
-         dec->refs[target->valid_ref].decoded_bottom = 1;
-         break;
-      default:
-         dec->refs[target->valid_ref].decoded_top = 1;
-         dec->refs[target->valid_ref].decoded_bottom = 1;
-         break;
-      }
       return;
    case PIPE_VIDEO_FORMAT_MPEG4:
       *caps = nouveau_vp3_fill_picparm_mpeg4_vp(dec, desc.mpeg4, refs, is_ref, vp);
       nouveau_vp3_handle_references(dec, refs, dec->fence_seq, target);
-      // XXX: Correct?
-      if (!desc.mpeg4->interlaced) {
-         dec->refs[target->valid_ref].decoded_top = 1;
-         dec->refs[target->valid_ref].decoded_bottom = 1;
-      } else if (desc.mpeg4->top_field_first) {
-         if (!dec->refs[target->valid_ref].decoded_top)
-            dec->refs[target->valid_ref].decoded_top = 1;
-         else
-            dec->refs[target->valid_ref].decoded_bottom = 1;
-      } else {
-         if (!dec->refs[target->valid_ref].decoded_bottom)
-            dec->refs[target->valid_ref].decoded_bottom = 1;
-         else
-            dec->refs[target->valid_ref].decoded_top = 1;
-      }
       return;
    case PIPE_VIDEO_FORMAT_VC1: {
       *caps = nouveau_vp3_fill_picparm_vc1_vp(dec, desc.vc1, refs, is_ref, vp);
       nouveau_vp3_handle_references(dec, refs, dec->fence_seq, target);
-      if (desc.vc1->frame_coding_mode == 3)
-         debug_printf("Field-Interlaced possibly incorrectly handled\n");
-      dec->refs[target->valid_ref].decoded_top = 1;
-      dec->refs[target->valid_ref].decoded_bottom = 1;
       return;
    }
    case PIPE_VIDEO_FORMAT_MPEG4_AVC: {
diff --git a/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv50_state.c b/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv50_state.c
index c140d6e73..d0bc7ff1a 100644
--- a/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv50_state.c
+++ b/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv50_state.c
@@ -585,12 +585,9 @@ nv50_stage_sampler_states_bind(struct nv50_context *nv50, int s,
          nv50_screen_tsc_unlock(nv50->screen, old);
    }
    assert(nv50->num_samplers[s] <= PIPE_MAX_SAMPLERS);
-   for (; i < nv50->num_samplers[s]; ++i) {
-      if (nv50->samplers[s][i]) {
+   for (; i < nv50->num_samplers[s]; ++i)
+      if (nv50->samplers[s][i])
          nv50_screen_tsc_unlock(nv50->screen, nv50->samplers[s][i]);
-         nv50->samplers[s][i] = NULL;
-      }
-   }
 
    nv50->num_samplers[s] = nr;
 
diff --git a/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c b/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c
index 4f2758af4..1dcb961ce 100644
--- a/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c
+++ b/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c
@@ -54,8 +54,8 @@ nv50_validate_fb(struct nv50_context *nv50)
       assert(mt->layout_3d || !array_mode || array_size == 1);
 
       BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(i)), 5);
-      PUSH_DATAh(push, mt->base.address + sf->offset);
-      PUSH_DATA (push, mt->base.address + sf->offset);
+      PUSH_DATAh(push, bo->offset + sf->offset);
+      PUSH_DATA (push, bo->offset + sf->offset);
       PUSH_DATA (push, nv50_format_table[sf->base.format].rt);
       if (likely(nouveau_bo_memtype(bo))) {
          PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
@@ -97,8 +97,8 @@ nv50_validate_fb(struct nv50_context *nv50)
       int unk = mt->base.base.target == PIPE_TEXTURE_3D || sf->depth == 1;
 
       BEGIN_NV04(push, NV50_3D(ZETA_ADDRESS_HIGH), 5);
-      PUSH_DATAh(push, mt->base.address + sf->offset);
-      PUSH_DATA (push, mt->base.address + sf->offset);
+      PUSH_DATAh(push, bo->offset + sf->offset);
+      PUSH_DATA (push, bo->offset + sf->offset);
       PUSH_DATA (push, nv50_format_table[fb->zsbuf->format].rt);
       PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
       PUSH_DATA (push, mt->layer_stride >> 2);
diff --git a/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv50_surface.c b/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv50_surface.c
index 8ec4a5fc1..600f4f93b 100644
--- a/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv50_surface.c
+++ b/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv50_surface.c
@@ -114,8 +114,8 @@ nv50_2d_texture_set(struct nouveau_pushbuf *push, int dst,
       PUSH_DATA (push, mt->level[level].pitch);
       PUSH_DATA (push, width);
       PUSH_DATA (push, height);
-      PUSH_DATAh(push, mt->base.address + offset);
-      PUSH_DATA (push, mt->base.address + offset);
+      PUSH_DATAh(push, bo->offset + offset);
+      PUSH_DATA (push, bo->offset + offset);
    } else {
       BEGIN_NV04(push, SUBC_2D(mthd), 5);
       PUSH_DATA (push, format);
@@ -126,8 +126,8 @@ nv50_2d_texture_set(struct nouveau_pushbuf *push, int dst,
       BEGIN_NV04(push, SUBC_2D(mthd + 0x18), 4);
       PUSH_DATA (push, width);
       PUSH_DATA (push, height);
-      PUSH_DATAh(push, mt->base.address + offset);
-      PUSH_DATA (push, mt->base.address + offset);
+      PUSH_DATAh(push, bo->offset + offset);
+      PUSH_DATA (push, bo->offset + offset);
    }
 
 #if 0
@@ -299,8 +299,8 @@ nv50_clear_render_target(struct pipe_context *pipe,
    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
    PUSH_DATA (push, 1);
    BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(0)), 5);
-   PUSH_DATAh(push, mt->base.address + sf->offset);
-   PUSH_DATA (push, mt->base.address + sf->offset);
+   PUSH_DATAh(push, bo->offset + sf->offset);
+   PUSH_DATA (push, bo->offset + sf->offset);
    PUSH_DATA (push, nv50_format_table[dst->format].rt);
    PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
    PUSH_DATA (push, mt->layer_stride >> 2);
@@ -381,8 +381,8 @@ nv50_clear_depth_stencil(struct pipe_context *pipe,
    nv50->scissors_dirty |= 1;
 
    BEGIN_NV04(push, NV50_3D(ZETA_ADDRESS_HIGH), 5);
-   PUSH_DATAh(push, mt->base.address + sf->offset);
-   PUSH_DATA (push, mt->base.address + sf->offset);
+   PUSH_DATAh(push, bo->offset + sf->offset);
+   PUSH_DATA (push, bo->offset + sf->offset);
    PUSH_DATA (push, nv50_format_table[dst->format].rt);
    PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
    PUSH_DATA (push, mt->layer_stride >> 2);
diff --git a/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv50_transfer.c b/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv50_transfer.c
index fc6b24aac..f71605281 100644
--- a/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv50_transfer.c
+++ b/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv50_transfer.c
@@ -24,8 +24,6 @@ nv50_m2mf_rect_setup(struct nv50_m2mf_rect *rect,
    rect->bo = mt->base.bo;
    rect->domain = mt->base.domain;
    rect->base = mt->level[l].offset;
-   if (mt->base.bo->offset != mt->base.address)
-      rect->base += mt->base.address - mt->base.bo->offset;
    rect->pitch = mt->level[l].pitch;
    if (util_format_is_plain(res->format)) {
       rect->width = w << mt->ms_x;
diff --git a/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv84_video.c b/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv84_video.c
index b42de20f7..a39f572f7 100644
--- a/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv84_video.c
+++ b/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv84_video.c
@@ -482,14 +482,12 @@ nv84_create_decoder(struct pipe_context *context,
       mip.level[0].pitch = surf.width * 4;
       mip.base.domain = NOUVEAU_BO_VRAM;
       mip.base.bo = dec->mbring;
-      mip.base.address = dec->mbring->offset;
       context->clear_render_target(context, &surf.base, &color, 0, 0, 64, 4760);
       surf.offset = dec->vpring->size / 2 - 0x1000;
       surf.width = 1024;
       surf.height = 1;
       mip.level[0].pitch = surf.width * 4;
       mip.base.bo = dec->vpring;
-      mip.base.address = dec->vpring->offset;
       context->clear_render_target(context, &surf.base, &color, 0, 0, 1024, 1);
       surf.offset = dec->vpring->size - 0x1000;
       context->clear_render_target(context, &surf.base, &color, 0, 0, 1024, 1);
@@ -685,14 +683,17 @@ nv84_video_buffer_create(struct pipe_context *pipe,
                       bo_size, &cfg, &buffer->full))
       goto error;
 
-   nouveau_bo_ref(buffer->interlaced, &mt0->base.bo);
+   mt0->base.bo = buffer->interlaced;
    mt0->base.domain = NOUVEAU_BO_VRAM;
-   mt0->base.address = buffer->interlaced->offset;
+   mt0->base.offset = 0;
+   mt0->base.address = buffer->interlaced->offset + mt0->base.offset;
+   nouveau_bo_ref(buffer->interlaced, &empty);
 
-   nouveau_bo_ref(buffer->interlaced, &mt1->base.bo);
+   mt1->base.bo = buffer->interlaced;
    mt1->base.domain = NOUVEAU_BO_VRAM;
-   mt1->base.offset = mt0->total_size;
-   mt1->base.address = buffer->interlaced->offset + mt0->total_size;
+   mt1->base.offset = mt0->layer_stride * 2;
+   mt1->base.address = buffer->interlaced->offset + mt1->base.offset;
+   nouveau_bo_ref(buffer->interlaced, &empty);
 
    memset(&sv_templ, 0, sizeof(sv_templ));
    for (component = 0, i = 0; i < 2; ++i ) {
diff --git a/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv84_video_bsp.c b/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv84_video_bsp.c
index 1a520d2df..de923e486 100644
--- a/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv84_video_bsp.c
+++ b/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv84_video_bsp.c
@@ -67,15 +67,10 @@ struct iparm {
          uint32_t field_is_ref; // 04 // bit0: top, bit1: bottom
          uint8_t is_long_term; // 08
          uint8_t non_existing; // 09
-         uint8_t u0a; // 0a
-         uint8_t u0b; // 0b
          uint32_t frame_idx; // 0c
          uint32_t field_order_cnt[2]; // 10
          uint32_t mvidx; // 18
          uint8_t field_pic_flag; // 1c
-         uint8_t u1d; // 1d
-         uint8_t u1e; // 1e
-         uint8_t u1f; // 1f
          // 20
       } refs[0x10]; // 1e0
    } ipicparm; // 150
diff --git a/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv98_video_bsp.c b/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv98_video_bsp.c
index 6058c2213..97d4119b6 100644
--- a/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv98_video_bsp.c
+++ b/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv98_video_bsp.c
@@ -42,8 +42,8 @@ nv98_decoder_bsp(struct nouveau_vp3_decoder *dec, union pipe_desc desc,
    struct nouveau_pushbuf *push = dec->pushbuf[0];
    enum pipe_video_format codec = u_reduce_video_profile(dec->base.profile);
    uint32_t bsp_addr, comm_addr, inter_addr;
-   uint32_t slice_size, bucket_size, ring_size, bsp_size;
-   uint32_t caps, i;
+   uint32_t slice_size, bucket_size, ring_size;
+   uint32_t caps;
    int ret;
    struct nouveau_bo *bsp_bo = dec->bsp_bo[comm_seq % NOUVEAU_VP3_VIDEO_QDEPTH];
    struct nouveau_bo *inter_bo = dec->inter_bo[comm_seq & 1];
@@ -65,41 +65,6 @@ nv98_decoder_bsp(struct nouveau_vp3_decoder *dec, union pipe_desc desc,
    fence_extra = 4;
 #endif
 
-   bsp_size = NOUVEAU_VP3_BSP_RESERVED_SIZE;
-   for (i = 0; i < num_buffers; i++)
-      bsp_size += num_bytes[i];
-   bsp_size += 256; /* the 4 end markers */
-
-   if (!bsp_bo || bsp_size > bsp_bo->size) {
-      struct nouveau_bo *tmp_bo = NULL;
-
-      /* round up to the nearest mb */
-      bsp_size += (1 << 20) - 1;
-      bsp_size &= ~((1 << 20) - 1);
-
-      ret = nouveau_bo_new(dec->bitplane_bo->device, NOUVEAU_BO_VRAM, 0, bsp_size, NULL, &tmp_bo);
-      if (ret) {
-         debug_printf("reallocating bsp %u -> %u failed with %i\n",
-                      bsp_bo ? (unsigned)bsp_bo->size : 0, bsp_size, ret);
-         return -1;
-      }
-      nouveau_bo_ref(NULL, &bsp_bo);
-      bo_refs[0].bo = dec->bsp_bo[comm_seq % NOUVEAU_VP3_VIDEO_QDEPTH] = bsp_bo = tmp_bo;
-   }
-
-   if (!inter_bo || bsp_bo->size * 4 > inter_bo->size) {
-      struct nouveau_bo *tmp_bo = NULL;
-
-      ret = nouveau_bo_new(dec->bitplane_bo->device, NOUVEAU_BO_VRAM, 0, bsp_bo->size * 4, NULL, &tmp_bo);
-      if (ret) {
-         debug_printf("reallocating inter %u -> %u failed with %i\n",
-                      inter_bo ? (unsigned)inter_bo->size : 0, (unsigned)bsp_bo->size * 4, ret);
-         return -1;
-      }
-      nouveau_bo_ref(NULL, &inter_bo);
-      bo_refs[1].bo = dec->inter_bo[comm_seq & 1] = inter_bo = tmp_bo;
-   }
-
    ret = nouveau_bo_map(bsp_bo, NOUVEAU_BO_WR, dec->client);
    if (ret) {
       debug_printf("map failed: %i %s\n", ret, strerror(-ret));
diff --git a/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv98_video_vp.c b/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv98_video_vp.c
index e74abe286..9cdb40ba0 100644
--- a/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv98_video_vp.c
+++ b/dist/Mesa/src/gallium/drivers/nouveau/nv50/nv98_video_vp.c
@@ -59,6 +59,7 @@ static void dump_comm_vp(struct nouveau_vp3_decoder *dec, struct comm *comm, u32
 static void
 nv98_decoder_kick_ref(struct nouveau_vp3_decoder *dec, struct nouveau_vp3_video_buffer *target)
 {
+   dec->refs[target->valid_ref].vidbuf = NULL;
    dec->refs[target->valid_ref].last_used = 0;
 //   debug_printf("Unreffed %p\n", target);
 }
diff --git a/dist/Mesa/src/gallium/drivers/nouveau/nvc0/nvc0_miptree.c b/dist/Mesa/src/gallium/drivers/nouveau/nvc0/nvc0_miptree.c
index d602aedcb..79c9390b7 100644
--- a/dist/Mesa/src/gallium/drivers/nouveau/nvc0/nvc0_miptree.c
+++ b/dist/Mesa/src/gallium/drivers/nouveau/nvc0/nvc0_miptree.c
@@ -261,6 +261,7 @@ nvc0_miptree_create(struct pipe_screen *pscreen,
 
    if (pt->usage == PIPE_USAGE_STAGING) {
       switch (pt->target) {
+      case PIPE_TEXTURE_1D:
       case PIPE_TEXTURE_2D:
       case PIPE_TEXTURE_RECT:
          if (pt->last_level == 0 &&
diff --git a/dist/Mesa/src/gallium/drivers/nouveau/nvc0/nvc0_program.c b/dist/Mesa/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
index 92580f76b..394e4a313 100644
--- a/dist/Mesa/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
+++ b/dist/Mesa/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
@@ -626,7 +626,7 @@ nvc0_program_translate(struct nvc0_program *prog, uint16_t chipset)
    if (info->bin.tlsSpace) {
       assert(info->bin.tlsSpace < (1 << 24));
       prog->hdr[0] |= 1 << 26;
-      prog->hdr[1] |= align(info->bin.tlsSpace, 0x10); /* l[] size */
+      prog->hdr[1] |= info->bin.tlsSpace; /* l[] size */
       prog->need_tls = TRUE;
    }
    /* TODO: factor 2 only needed where joinat/precont is used,
diff --git a/dist/Mesa/src/gallium/drivers/nouveau/nvc0/nvc0_video.c b/dist/Mesa/src/gallium/drivers/nouveau/nvc0/nvc0_video.c
index 48ffac1b7..5871f590e 100644
--- a/dist/Mesa/src/gallium/drivers/nouveau/nvc0/nvc0_video.c
+++ b/dist/Mesa/src/gallium/drivers/nouveau/nvc0/nvc0_video.c
@@ -173,12 +173,16 @@ nvc0_create_decoder(struct pipe_context *context,
       ret = nouveau_bo_new(screen->device, NOUVEAU_BO_VRAM,
                            0x100, 4 << 20, &cfg, &dec->inter_bo[0]);
    if (!ret) {
-      ret = nouveau_bo_new(screen->device, NOUVEAU_BO_VRAM,
-                           0x100, dec->inter_bo[0]->size, &cfg,
-                           &dec->inter_bo[1]);
+      if (!kepler)
+         nouveau_bo_ref(dec->inter_bo[0], &dec->inter_bo[1]);
+      else
+         ret = nouveau_bo_new(screen->device, NOUVEAU_BO_VRAM,
+                              0x100, dec->inter_bo[0]->size, &cfg,
+                              &dec->inter_bo[1]);
    }
    if (ret)
       goto fail;
+
    switch (u_reduce_video_profile(templ->profile)) {
    case PIPE_VIDEO_FORMAT_MPEG12: {
       codec = 1;
diff --git a/dist/Mesa/src/gallium/drivers/nouveau/nvc0/nvc0_video_bsp.c b/dist/Mesa/src/gallium/drivers/nouveau/nvc0/nvc0_video_bsp.c
index 9139bc1c9..40696fa77 100644
--- a/dist/Mesa/src/gallium/drivers/nouveau/nvc0/nvc0_video_bsp.c
+++ b/dist/Mesa/src/gallium/drivers/nouveau/nvc0/nvc0_video_bsp.c
@@ -42,8 +42,8 @@ nvc0_decoder_bsp(struct nouveau_vp3_decoder *dec, union pipe_desc desc,
    struct nouveau_pushbuf *push = dec->pushbuf[0];
    enum pipe_video_format codec = u_reduce_video_profile(dec->base.profile);
    uint32_t bsp_addr, comm_addr, inter_addr;
-   uint32_t slice_size, bucket_size, ring_size, bsp_size;
-   uint32_t caps, i;
+   uint32_t slice_size, bucket_size, ring_size;
+   uint32_t caps;
    int ret;
    struct nouveau_bo *bsp_bo = dec->bsp_bo[comm_seq % NOUVEAU_VP3_VIDEO_QDEPTH];
    struct nouveau_bo *inter_bo = dec->inter_bo[comm_seq & 1];
@@ -65,49 +65,6 @@ nvc0_decoder_bsp(struct nouveau_vp3_decoder *dec, union pipe_desc desc,
    fence_extra = 4;
 #endif
 
-   bsp_size = NOUVEAU_VP3_BSP_RESERVED_SIZE;
-   for (i = 0; i < num_buffers; i++)
-      bsp_size += num_bytes[i];
-   bsp_size += 256; /* the 4 end markers */
-
-   if (!bsp_bo || bsp_size > bsp_bo->size) {
-      union nouveau_bo_config cfg;
-      struct nouveau_bo *tmp_bo = NULL;
-
-      cfg.nvc0.tile_mode = 0x10;
-      cfg.nvc0.memtype = 0xfe;
-
-      /* round up to the nearest mb */
-      bsp_size += (1 << 20) - 1;
-      bsp_size &= ~((1 << 20) - 1);
-
-      ret = nouveau_bo_new(dec->bitplane_bo->device, NOUVEAU_BO_VRAM, 0, bsp_size, &cfg, &tmp_bo);
-      if (ret) {
-         debug_printf("reallocating bsp %u -> %u failed with %i\n",
-                      bsp_bo ? (unsigned)bsp_bo->size : 0, bsp_size, ret);
-         return -1;
-      }
-      nouveau_bo_ref(NULL, &bsp_bo);
-      bo_refs[0].bo = dec->bsp_bo[comm_seq % NOUVEAU_VP3_VIDEO_QDEPTH] = bsp_bo = tmp_bo;
-   }
-
-   if (!inter_bo || bsp_bo->size * 4 > inter_bo->size) {
-      union nouveau_bo_config cfg;
-      struct nouveau_bo *tmp_bo = NULL;
-
-      cfg.nvc0.tile_mode = 0x10;
-      cfg.nvc0.memtype = 0xfe;
-
-      ret = nouveau_bo_new(dec->bitplane_bo->device, NOUVEAU_BO_VRAM, 0, bsp_bo->size * 4, &cfg, &tmp_bo);
-      if (ret) {
-         debug_printf("reallocating inter %u -> %u failed with %i\n",
-                      inter_bo ? (unsigned)inter_bo->size : 0, (unsigned)bsp_bo->size * 4, ret);
-         return -1;
-      }
-      nouveau_bo_ref(NULL, &inter_bo);
-      bo_refs[1].bo = dec->inter_bo[comm_seq & 1] = inter_bo = tmp_bo;
-   }
-
    ret = nouveau_bo_map(bsp_bo, NOUVEAU_BO_WR, dec->client);
    if (ret) {
       debug_printf("map failed: %i %s\n", ret, strerror(-ret));
diff --git a/dist/Mesa/src/gallium/drivers/nouveau/nvc0/nvc0_video_vp.c b/dist/Mesa/src/gallium/drivers/nouveau/nvc0/nvc0_video_vp.c
index 33c73750d..07170a0e4 100644
--- a/dist/Mesa/src/gallium/drivers/nouveau/nvc0/nvc0_video_vp.c
+++ b/dist/Mesa/src/gallium/drivers/nouveau/nvc0/nvc0_video_vp.c
@@ -59,6 +59,7 @@ static void dump_comm_vp(struct nouveau_vp3_decoder *dec, struct comm *comm, u32
 static void
 nvc0_decoder_kick_ref(struct nouveau_vp3_decoder *dec, struct nouveau_vp3_video_buffer *target)
 {
+   dec->refs[target->valid_ref].vidbuf = NULL;
    dec->refs[target->valid_ref].last_used = 0;
 //   debug_printf("Unreffed %p\n", target);
 }
diff --git a/dist/Mesa/src/gallium/drivers/radeon/r600_pipe_common.c b/dist/Mesa/src/gallium/drivers/radeon/r600_pipe_common.c
index 4c9d2961f..70c4d1ade 100644
--- a/dist/Mesa/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/dist/Mesa/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -142,13 +142,7 @@ bool r600_common_context_init(struct r600_common_context *rctx,
 	rctx->ws = rscreen->ws;
 	rctx->family = rscreen->family;
 	rctx->chip_class = rscreen->chip_class;
-
-	if (rscreen->family == CHIP_HAWAII)
-		rctx->max_db = 16;
-	else if (rscreen->chip_class >= EVERGREEN)
-		rctx->max_db = 8;
-	else
-		rctx->max_db = 4;
+	rctx->max_db = rscreen->chip_class >= EVERGREEN ? 8 : 4;
 
 	rctx->b.transfer_map = u_transfer_map_vtbl;
 	rctx->b.transfer_flush_region = u_default_transfer_flush_region;
@@ -437,20 +431,7 @@ static int r600_get_compute_param(struct pipe_screen *screen,
 	//TODO: select these params by asic
 	switch (param) {
 	case PIPE_COMPUTE_CAP_IR_TARGET: {
-		const char *gpu;
-		switch(rscreen->family) {
-		/* Clang < 3.6 is missing Hainan in its list of
-		 * GPUs, so we need to use the name of a similar GPU.
-		 */
-#if HAVE_LLVM < 0x0306
-		case CHIP_HAINAN:
-			gpu = "oland";
-			break;
-#endif
-		default:
-			gpu = r600_get_llvm_processor_name(rscreen->family);
-			break;
-		}
+		const char *gpu = r600_get_llvm_processor_name(rscreen->family);
 		if (ret) {
 			sprintf(ret, "%s-r600--", gpu);
 		}
@@ -491,21 +472,13 @@ static int r600_get_compute_param(struct pipe_screen *screen,
 	case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 		if (ret) {
 			uint64_t *max_global_size = ret;
-			uint64_t max_mem_alloc_size;
-
-			r600_get_compute_param(screen,
-				PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
-				&max_mem_alloc_size);
-
-			/* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
-			 * 1/4 of the MAX_GLOBAL_SIZE.  Since the
-			 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
-			 * make sure we never report more than
-			 * 4 * MAX_MEM_ALLOC_SIZE.
-			 */
-			*max_global_size = MIN2(4 * max_mem_alloc_size,
-				rscreen->info.gart_size +
-				rscreen->info.vram_size);
+			/* XXX: This is what the proprietary driver reports, we
+			 * may want to use a different value. */
+			/* XXX: Not sure what to put here for SI. */
+			if (rscreen->chip_class >= SI)
+				*max_global_size = 2000000000;
+			else
+				*max_global_size = 201326592;
 		}
 		return sizeof(uint64_t);
 
@@ -529,11 +502,13 @@ static int r600_get_compute_param(struct pipe_screen *screen,
 		if (ret) {
 			uint64_t max_global_size;
 			uint64_t *max_mem_alloc_size = ret;
-
-			/* XXX: The limit in older kernels is 256 MB.  We
-			 * should add a query here for newer kernels.
+			r600_get_compute_param(screen, PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE, &max_global_size);
+			/* OpenCL requres this value be at least
+			 * max(MAX_GLOBAL_SIZE / 4, 128 * 1024 *1024)
+			 * I'm really not sure what value to report here, but
+			 * MAX_GLOBAL_SIZE / 4 seems resonable.
 			 */
-			*max_mem_alloc_size = 256 * 1024 * 1024;
+			*max_mem_alloc_size = max_global_size / 4;
 		}
 		return sizeof(uint64_t);
 
diff --git a/dist/Mesa/src/gallium/drivers/radeon/r600_pipe_common.h b/dist/Mesa/src/gallium/drivers/radeon/r600_pipe_common.h
index e7f410dd7..bbfcdf957 100644
--- a/dist/Mesa/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/dist/Mesa/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -72,7 +72,6 @@
 #define R600_CONTEXT_WAIT_3D_IDLE		(1 << 17)
 #define R600_CONTEXT_WAIT_CP_DMA_IDLE		(1 << 18)
 #define R600_CONTEXT_VGT_FLUSH			(1 << 19)
-#define R600_CONTEXT_VGT_STREAMOUT_SYNC		(1 << 20)
 
 /* Debug flags. */
 /* logging */
diff --git a/dist/Mesa/src/gallium/drivers/radeon/r600_query.c b/dist/Mesa/src/gallium/drivers/radeon/r600_query.c
index 2fc68e7fe..38889fdf2 100644
--- a/dist/Mesa/src/gallium/drivers/radeon/r600_query.c
+++ b/dist/Mesa/src/gallium/drivers/radeon/r600_query.c
@@ -786,40 +786,12 @@ void r600_suspend_nontimer_queries(struct r600_common_context *ctx)
 	assert(ctx->num_cs_dw_nontimer_queries_suspend == 0);
 }
 
-static unsigned r600_queries_num_cs_dw_for_resuming(struct r600_common_context *ctx)
-{
-	struct r600_query *query;
-	unsigned num_dw = 0;
-
-	LIST_FOR_EACH_ENTRY(query, &ctx->active_nontimer_queries, list) {
-		/* begin + end */
-		num_dw += query->num_cs_dw * 2;
-
-		/* Workaround for the fact that
-		 * num_cs_dw_nontimer_queries_suspend is incremented for every
-		 * resumed query, which raises the bar in need_cs_space for
-		 * queries about to be resumed.
-		 */
-		num_dw += query->num_cs_dw;
-	}
-	/* primitives generated query */
-	num_dw += ctx->streamout.enable_atom.num_dw;
-	/* guess for ZPASS enable or PERFECT_ZPASS_COUNT enable updates */
-	num_dw += 13;
-
-	return num_dw;
-}
-
 void r600_resume_nontimer_queries(struct r600_common_context *ctx)
 {
 	struct r600_query *query;
 
 	assert(ctx->num_cs_dw_nontimer_queries_suspend == 0);
 
-	/* Check CS space here. Resuming must not be interrupted by flushes. */
-	ctx->need_gfx_cs_space(&ctx->b,
-			       r600_queries_num_cs_dw_for_resuming(ctx), TRUE);
-
 	LIST_FOR_EACH_ENTRY(query, &ctx->active_nontimer_queries, list) {
 		r600_emit_query_begin(ctx, query);
 	}
diff --git a/dist/Mesa/src/gallium/drivers/radeon/r600_texture.c b/dist/Mesa/src/gallium/drivers/radeon/r600_texture.c
index 9a46c53f3..3a37465b1 100644
--- a/dist/Mesa/src/gallium/drivers/radeon/r600_texture.c
+++ b/dist/Mesa/src/gallium/drivers/radeon/r600_texture.c
@@ -380,8 +380,7 @@ void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
 
 	out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
 	out->alignment = MAX2(256, base_align);
-	out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
-		    align(slice_bytes, base_align);
+	out->size = rtex->surface.array_size * align(slice_bytes, base_align);
 }
 
 static void si_texture_get_cmask_info(struct r600_common_screen *rscreen,
@@ -428,8 +427,7 @@ static void si_texture_get_cmask_info(struct r600_common_screen *rscreen,
 		out->slice_tile_max -= 1;
 
 	out->alignment = MAX2(256, base_align);
-	out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
-		    align(slice_bytes, base_align);
+	out->size = rtex->surface.array_size * align(slice_bytes, base_align);
 }
 
 static void r600_texture_allocate_cmask(struct r600_common_screen *rscreen,
@@ -525,8 +523,7 @@ static unsigned si_texture_htile_alloc_size(struct r600_common_screen *rscreen,
 	pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
 	base_align = num_pipes * pipe_interleave_bytes;
 
-	return (util_max_layer(&rtex->resource.b.b, 0) + 1) *
-		align(slice_bytes, base_align);
+	return rtex->surface.array_size * align(slice_bytes, base_align);
 }
 
 static unsigned r600_texture_htile_alloc_size(struct r600_common_screen *rscreen,
diff --git a/dist/Mesa/src/gallium/drivers/radeonsi/si_blit.c b/dist/Mesa/src/gallium/drivers/radeonsi/si_blit.c
index dced3d0e7..1dfff49d1 100644
--- a/dist/Mesa/src/gallium/drivers/radeonsi/si_blit.c
+++ b/dist/Mesa/src/gallium/drivers/radeonsi/si_blit.c
@@ -60,16 +60,9 @@ static void si_blitter_begin(struct pipe_context *ctx, enum si_blitter_op op)
 	util_blitter_save_geometry_shader(sctx->blitter, sctx->gs_shader);
 	util_blitter_save_vertex_shader(sctx->blitter, sctx->vs_shader);
 	util_blitter_save_vertex_elements(sctx->blitter, sctx->vertex_elements);
-	if (sctx->queued.named.sample_mask) {
-		util_blitter_save_sample_mask(sctx->blitter,
-					      sctx->queued.named.sample_mask->sample_mask);
-	}
 	if (sctx->queued.named.viewport) {
 		util_blitter_save_viewport(sctx->blitter, &sctx->queued.named.viewport->viewport);
 	}
-	if (sctx->queued.named.scissor) {
-		util_blitter_save_scissor(sctx->blitter, &sctx->queued.named.scissor->scissor);
-	}
 	util_blitter_save_vertex_buffer_slot(sctx->blitter, sctx->vertex_buffer);
 	util_blitter_save_so_targets(sctx->blitter, sctx->b.streamout.num_targets,
 				     (struct pipe_stream_output_target**)sctx->b.streamout.targets);
@@ -742,7 +735,7 @@ static void si_flush_resource(struct pipe_context *ctx,
 
 	if (!rtex->is_depth && rtex->cmask.size) {
 		si_blit_decompress_color(ctx, rtex, 0, res->last_level,
-					 0, util_max_layer(res, 0));
+					 0, res->array_size - 1);
 	}
 }
 
diff --git a/dist/Mesa/src/gallium/drivers/radeonsi/si_compute.c b/dist/Mesa/src/gallium/drivers/radeonsi/si_compute.c
index 691e52a45..c0637f6f7 100644
--- a/dist/Mesa/src/gallium/drivers/radeonsi/si_compute.c
+++ b/dist/Mesa/src/gallium/drivers/radeonsi/si_compute.c
@@ -100,7 +100,7 @@ static void si_set_global_binding(
 
 	if (!resources) {
 		for (i = first; i < first + n; i++) {
-			pipe_resource_reference(&program->global_buffers[i], NULL);
+			program->global_buffers[i] = NULL;
 		}
 		return;
 	}
@@ -108,7 +108,7 @@ static void si_set_global_binding(
 	for (i = first; i < first + n; i++) {
 		uint64_t va;
 		uint32_t offset;
-		pipe_resource_reference(&program->global_buffers[i], resources[i]);
+		program->global_buffers[i] = resources[i];
 		va = r600_resource_va(ctx->screen, resources[i]);
 		offset = util_le32_to_cpu(*handles[i]);
 		va += offset;
@@ -288,8 +288,8 @@ static void si_launch_grid(
 	}
 #endif
 
+	FREE(pm4);
 	FREE(kernel_args);
-	si_pm4_free_state(sctx, pm4, ~0);
 }
 
 
diff --git a/dist/Mesa/src/gallium/drivers/radeonsi/si_descriptors.c b/dist/Mesa/src/gallium/drivers/radeonsi/si_descriptors.c
index 38ad0778c..77bc03432 100644
--- a/dist/Mesa/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/dist/Mesa/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -987,9 +987,9 @@ void si_init_all_descriptors(struct si_context *sctx)
 
 		si_init_sampler_views(sctx, &sctx->samplers[i].views, i);
 
-		sctx->atoms.s.const_buffers[i] = &sctx->const_buffers[i].desc.atom;
-		sctx->atoms.s.rw_buffers[i] = &sctx->rw_buffers[i].desc.atom;
-		sctx->atoms.s.sampler_views[i] = &sctx->samplers[i].views.desc.atom;
+		sctx->atoms.const_buffers[i] = &sctx->const_buffers[i].desc.atom;
+		sctx->atoms.rw_buffers[i] = &sctx->rw_buffers[i].desc.atom;
+		sctx->atoms.sampler_views[i] = &sctx->samplers[i].views.desc.atom;
 	}
 
 
diff --git a/dist/Mesa/src/gallium/drivers/radeonsi/si_dma.c b/dist/Mesa/src/gallium/drivers/radeonsi/si_dma.c
index 26f1e1b63..dc8c609b8 100644
--- a/dist/Mesa/src/gallium/drivers/radeonsi/si_dma.c
+++ b/dist/Mesa/src/gallium/drivers/radeonsi/si_dma.c
@@ -91,13 +91,12 @@ static void si_dma_copy_buffer(struct si_context *ctx,
 	}
 	ncopy = (size / max_csize) + !!(size % max_csize);
 
-	r600_need_dma_space(&ctx->b, ncopy * 5);
-
 	r600_context_bo_reloc(&ctx->b, &ctx->b.rings.dma, rsrc, RADEON_USAGE_READ,
 			      RADEON_PRIO_MIN);
 	r600_context_bo_reloc(&ctx->b, &ctx->b.rings.dma, rdst, RADEON_USAGE_WRITE,
 			      RADEON_PRIO_MIN);
 
+	r600_need_dma_space(&ctx->b, ncopy * 5);
 	for (i = 0; i < ncopy; i++) {
 		csize = size < max_csize ? size : max_csize;
 		cs->buf[cs->cdw++] = SI_DMA_PACKET(SI_DMA_PACKET_COPY, sub_cmd, csize);
diff --git a/dist/Mesa/src/gallium/drivers/radeonsi/si_hw_context.c b/dist/Mesa/src/gallium/drivers/radeonsi/si_hw_context.c
index d2a1dbe42..383157b7d 100644
--- a/dist/Mesa/src/gallium/drivers/radeonsi/si_hw_context.c
+++ b/dist/Mesa/src/gallium/drivers/radeonsi/si_hw_context.c
@@ -63,7 +63,7 @@ void si_need_cs_space(struct si_context *ctx, unsigned num_dw,
 	}
 
 	/* Count in framebuffer cache flushes at the end of CS. */
-	num_dw += ctx->atoms.s.cache_flush->num_dw;
+	num_dw += ctx->atoms.cache_flush->num_dw;
 
 #if SI_TRACE_CS
 	if (ctx->screen->b.trace_bo) {
diff --git a/dist/Mesa/src/gallium/drivers/radeonsi/si_pipe.h b/dist/Mesa/src/gallium/drivers/radeonsi/si_pipe.h
index de424778a..4a5f29177 100644
--- a/dist/Mesa/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/dist/Mesa/src/gallium/drivers/radeonsi/si_pipe.h
@@ -114,7 +114,7 @@ struct si_context {
 			struct r600_atom *streamout_begin;
 			struct r600_atom *streamout_enable; /* must be after streamout_begin */
 			struct r600_atom *framebuffer;
-		} s;
+		};
 		struct r600_atom *array[0];
 	} atoms;
 
diff --git a/dist/Mesa/src/gallium/drivers/radeonsi/si_shader.c b/dist/Mesa/src/gallium/drivers/radeonsi/si_shader.c
index 6b6a5caab..0d070d3ce 100644
--- a/dist/Mesa/src/gallium/drivers/radeonsi/si_shader.c
+++ b/dist/Mesa/src/gallium/drivers/radeonsi/si_shader.c
@@ -1539,8 +1539,9 @@ static void tex_fetch_args(
 	/* Pack LOD bias value */
 	if (opcode == TGSI_OPCODE_TXB)
 		address[count++] = coords[3];
-	if (opcode == TGSI_OPCODE_TXB2)
-		address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
+
+	if (target == TGSI_TEXTURE_CUBE || target == TGSI_TEXTURE_SHADOWCUBE)
+		radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
 
 	/* Pack depth comparison value */
 	switch (target) {
@@ -1557,9 +1558,6 @@ static void tex_fetch_args(
 		address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
 	}
 
-	if (target == TGSI_TEXTURE_CUBE || target == TGSI_TEXTURE_SHADOWCUBE)
-		radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
-
 	/* Pack user derivatives */
 	if (opcode == TGSI_OPCODE_TXD) {
 		for (chan = 0; chan < 2; chan++) {
@@ -2499,7 +2497,6 @@ int si_pipe_shader_create(
 
 	bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
 	bld_base->op_actions[TGSI_OPCODE_TXB] = txb_action;
-	bld_base->op_actions[TGSI_OPCODE_TXB2] = txb_action;
 #if HAVE_LLVM >= 0x0304
 	bld_base->op_actions[TGSI_OPCODE_TXD] = txd_action;
 #endif
@@ -2616,8 +2613,5 @@ out:
 
 void si_pipe_shader_destroy(struct pipe_context *ctx, struct si_pipe_shader *shader)
 {
-	if (shader->gs_copy_shader)
-		si_pipe_shader_destroy(ctx, shader->gs_copy_shader);
-
 	r600_resource_reference(&shader->bo, NULL);
 }
diff --git a/dist/Mesa/src/gallium/state_trackers/clover/core/timestamp.cpp b/dist/Mesa/src/gallium/state_trackers/clover/core/timestamp.cpp
index 18950130e..f168d61b6 100644
--- a/dist/Mesa/src/gallium/state_trackers/clover/core/timestamp.cpp
+++ b/dist/Mesa/src/gallium/state_trackers/clover/core/timestamp.cpp
@@ -30,7 +30,6 @@ using namespace clover;
 timestamp::query::query(command_queue &q) :
    q(q),
    _query(q.pipe->create_query(q.pipe, PIPE_QUERY_TIMESTAMP)) {
-   q.pipe->end_query(q.pipe, _query);
 }
 
 timestamp::query::query(query &&other) :
diff --git a/dist/Mesa/src/mesa/drivers/common/meta_blit.c b/dist/Mesa/src/mesa/drivers/common/meta_blit.c
index 0de830c15..58492e061 100644
--- a/dist/Mesa/src/mesa/drivers/common/meta_blit.c
+++ b/dist/Mesa/src/mesa/drivers/common/meta_blit.c
@@ -325,12 +325,10 @@ setup_glsl_blit_framebuffer(struct gl_context *ctx,
                             struct gl_renderbuffer *src_rb,
                             GLenum target)
 {
-   unsigned texcoord_size;
-
    /* target = GL_TEXTURE_RECTANGLE is not supported in GLES 3.0 */
    assert(_mesa_is_desktop_gl(ctx) || target == GL_TEXTURE_2D);
 
-   texcoord_size = 2 + (src_rb->Depth > 1 ? 1 : 0);
+   unsigned texcoord_size = 2 + (src_rb->Depth > 1 ? 1 : 0);
 
    _mesa_meta_setup_vertex_objects(&blit->VAO, &blit->VBO, true,
                                    2, texcoord_size, 0);
diff --git a/dist/Mesa/src/mesa/drivers/common/meta_generate_mipmap.c b/dist/Mesa/src/mesa/drivers/common/meta_generate_mipmap.c
index 4b1718df9..d12806c3d 100644
--- a/dist/Mesa/src/mesa/drivers/common/meta_generate_mipmap.c
+++ b/dist/Mesa/src/mesa/drivers/common/meta_generate_mipmap.c
@@ -43,7 +43,6 @@
 #include "main/varray.h"
 #include "main/viewport.h"
 #include "drivers/common/meta.h"
-#include "program/prog_instruction.h"
 
 
 /**
@@ -169,8 +168,6 @@ _mesa_meta_GenerateMipmap(struct gl_context *ctx, GLenum target,
    GLenum faceTarget;
    GLuint dstLevel;
    GLuint samplerSave;
-   GLint swizzle[4];
-   GLboolean swizzleSaved = GL_FALSE;
 
    if (fallback_required(ctx, target, texObj)) {
       _mesa_generate_mipmap(ctx, target, texObj);
@@ -234,13 +231,6 @@ _mesa_meta_GenerateMipmap(struct gl_context *ctx, GLenum target,
 
    _mesa_TexParameteri(target, GL_GENERATE_MIPMAP, GL_FALSE);
 
-   if (texObj->_Swizzle != SWIZZLE_NOOP) {
-      static const GLint swizzleNoop[4] = { GL_RED, GL_GREEN, GL_BLUE, GL_ALPHA };
-      memcpy(swizzle, texObj->Swizzle, sizeof(swizzle));
-      swizzleSaved = GL_TRUE;
-      _mesa_TexParameteriv(target, GL_TEXTURE_SWIZZLE_RGBA, swizzleNoop);
-   }
-
    /* Silence valgrind warnings about reading uninitialized stack. */
    memset(verts, 0, sizeof(verts));
 
@@ -357,6 +347,4 @@ _mesa_meta_GenerateMipmap(struct gl_context *ctx, GLenum target,
    _mesa_TexParameteri(target, GL_TEXTURE_MAX_LEVEL, maxLevelSave);
    if (genMipmapSave)
       _mesa_TexParameteri(target, GL_GENERATE_MIPMAP, genMipmapSave);
-   if (swizzleSaved)
-      _mesa_TexParameteriv(target, GL_TEXTURE_SWIZZLE_RGBA, swizzle);
 }
diff --git a/dist/Mesa/src/mesa/drivers/dri/i965/gen8_surface_state.c b/dist/Mesa/src/mesa/drivers/dri/i965/gen8_surface_state.c
index 72983f54f..80ac4f3ed 100644
--- a/dist/Mesa/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/dist/Mesa/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -134,8 +134,6 @@ gen8_update_texture_surface(struct gl_context *ctx,
    struct intel_mipmap_tree *mt = intelObj->mt;
    struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
    struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
-   struct intel_mipmap_tree *aux_mt = NULL;
-   uint32_t aux_mode = 0;
    mesa_format format = intelObj->_Format;
 
    if (tObj->Target == GL_TEXTURE_BUFFER) {
@@ -157,11 +155,6 @@ gen8_update_texture_surface(struct gl_context *ctx,
       pitch = mt->pitch;
    }
 
-   if (mt->mcs_mt) {
-      aux_mt = mt->mcs_mt;
-      aux_mode = GEN8_SURFACE_AUX_MODE_MCS;
-   }
-
    /* If this is a view with restricted NumLayers, then our effective depth
     * is not just the miptree depth.
     */
@@ -204,13 +197,7 @@ gen8_update_texture_surface(struct gl_context *ctx,
                        GEN7_SURFACE_MIN_LOD) |
              (intelObj->_MaxLevel - tObj->BaseLevel); /* mip count */
 
-   if (aux_mt) {
-      surf[6] = SET_FIELD(mt->qpitch / 4, GEN8_SURFACE_AUX_QPITCH) |
-                SET_FIELD((aux_mt->pitch / 128) - 1, GEN8_SURFACE_AUX_PITCH) |
-                aux_mode;
-   } else {
-      surf[6] = 0;
-   }
+   surf[6] = 0;
 
    /* Handling GL_ALPHA as a surface format override breaks 1.30+ style
     * texturing functions that return a float, as our code generation always
@@ -232,15 +219,8 @@ gen8_update_texture_surface(struct gl_context *ctx,
 
    *((uint64_t *) &surf[8]) = mt->bo->offset64 + mt->offset; /* reloc */
 
-   if (aux_mt) {
-      *((uint64_t *) &surf[10]) = aux_mt->bo->offset64;
-      drm_intel_bo_emit_reloc(brw->batch.bo, *surf_offset + 10 * 4,
-                              aux_mt->bo, 0,
-                              I915_GEM_DOMAIN_SAMPLER, 0);
-   } else {
-      surf[10] = 0;
-      surf[11] = 0;
-   }
+   surf[10] = 0;
+   surf[11] = 0;
    surf[12] = 0;
 
    /* Emit relocation to surface contents */
@@ -306,8 +286,6 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
    struct gl_context *ctx = &brw->ctx;
    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
    struct intel_mipmap_tree *mt = irb->mt;
-   struct intel_mipmap_tree *aux_mt = NULL;
-   uint32_t aux_mode = 0;
    unsigned width = mt->logical_width0;
    unsigned height = mt->logical_height0;
    unsigned pitch = mt->pitch;
@@ -360,11 +338,6 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
                        __FUNCTION__, _mesa_get_format_name(rb_format));
    }
 
-   if (mt->mcs_mt) {
-      aux_mt = mt->mcs_mt;
-      aux_mode = GEN8_SURFACE_AUX_MODE_MCS;
-   }
-
    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 13 * 4, 64,
                                     &brw->wm.base.surf_offset[surf_index]);
 
@@ -391,13 +364,7 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
 
    surf[5] = irb->mt_level - irb->mt->first_level;
 
-   if (aux_mt) {
-      surf[6] = SET_FIELD(mt->qpitch / 4, GEN8_SURFACE_AUX_QPITCH) |
-                SET_FIELD((aux_mt->pitch / 128) - 1, GEN8_SURFACE_AUX_PITCH) |
-                aux_mode;
-   } else {
-      surf[6] = 0;
-   }
+   surf[6] = 0; /* Nothing of relevance. */
 
    surf[7] = mt->fast_clear_color_value |
              SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
@@ -407,16 +374,9 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
 
    *((uint64_t *) &surf[8]) = mt->bo->offset64; /* reloc */
 
-   if (aux_mt) {
-      *((uint64_t *) &surf[10]) = aux_mt->bo->offset64;
-      drm_intel_bo_emit_reloc(brw->batch.bo,
-                              brw->wm.base.surf_offset[surf_index] + 10 * 4,
-                              aux_mt->bo, 0,
-                              I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
-   } else {
-      surf[10] = 0;
-      surf[11] = 0;
-   }
+   /* Nothing of relevance. */
+   surf[10] = 0;
+   surf[11] = 0;
    surf[12] = 0;
 
    drm_intel_bo_emit_reloc(brw->batch.bo,
-- 
cgit v1.2.3