1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
|
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include <string.h>
#include "radeon.h"
#include "radeon_reg.h"
#include "radeon_macros.h"
#include "radeon_probe.h"
#include <X11/extensions/Xv.h>
#include "radeon_video.h"
#include "xf86.h"
#include "atipciids.h"
#include "generic_bus.h"
#include "theatre_reg.h"
#define VIP_NAME "RADEON VIP BUS"
#define VIP_TYPE "ATI VIP BUS"
/* Status defines */
#define VIP_BUSY 0
#define VIP_IDLE 1
#define VIP_RESET 2
static Bool RADEONVIP_ioctl(GENERIC_BUS_Ptr b, long ioctl, long arg1, char *arg2)
{
long count;
switch(ioctl){
case GB_IOCTL_GET_NAME:
count=strlen(VIP_NAME)+1;
if(count>arg1)return FALSE;
memcpy(arg2,VIP_NAME,count);
return TRUE;
case GB_IOCTL_GET_TYPE:
count=strlen(VIP_TYPE)+1;
if(count>arg1)return FALSE;
memcpy(arg2,VIP_TYPE,count);
return TRUE;
default:
return FALSE;
}
}
static uint32_t RADEONVIP_idle(GENERIC_BUS_Ptr b)
{
ScrnInfoPtr pScrn = b->pScrn;
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
uint32_t timeout;
RADEONWaitForIdleMMIO(pScrn);
timeout = INREG(RADEON_VIPH_TIMEOUT_STAT);
if(timeout & RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_STAT) /* lockup ?? */
{
RADEONWaitForFifo(pScrn, 2);
OUTREG(RADEON_VIPH_TIMEOUT_STAT, (timeout & 0xffffff00) | RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_AK);
RADEONWaitForIdleMMIO(pScrn);
return (INREG(RADEON_VIPH_CONTROL) & 0x2000) ? VIP_BUSY : VIP_RESET;
}
RADEONWaitForIdleMMIO(pScrn);
return (INREG(RADEON_VIPH_CONTROL) & 0x2000) ? VIP_BUSY : VIP_IDLE ;
}
static uint32_t RADEONVIP_fifo_idle(GENERIC_BUS_Ptr b, uint8_t channel)
{
ScrnInfoPtr pScrn = b->pScrn;
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
uint32_t timeout;
RADEONWaitForIdleMMIO(pScrn);
timeout = INREG(VIPH_TIMEOUT_STAT);
if((timeout & 0x0000000f) & channel) /* lockup ?? */
{
xf86DrvMsg(b->pScrn->scrnIndex, X_INFO, "RADEON_fifo_idle\n");
RADEONWaitForFifo(pScrn, 2);
OUTREG(VIPH_TIMEOUT_STAT, (timeout & 0xfffffff0) | channel);
RADEONWaitForIdleMMIO(pScrn);
return (INREG(VIPH_CONTROL) & 0x2000) ? VIP_BUSY : VIP_RESET;
}
RADEONWaitForIdleMMIO(pScrn);
return (INREG(VIPH_CONTROL) & 0x2000) ? VIP_BUSY : VIP_IDLE ;
}
/* address format:
((device & 0x3)<<14) | (fifo << 12) | (addr)
*/
#define VIP_WAIT_FOR_IDLE() { \
int i2ctries = 0; \
while (i2ctries < 10) { \
status = RADEONVIP_idle(b); \
if (status==VIP_BUSY) \
{ \
usleep(1000); \
i2ctries++; \
} else break; \
} \
}
static Bool RADEONVIP_read(GENERIC_BUS_Ptr b, uint32_t address, uint32_t count, uint8_t *buffer)
{
ScrnInfoPtr pScrn = b->pScrn;
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
uint32_t status,tmp;
if((count!=1) && (count!=2) && (count!=4))
{
xf86DrvMsg(pScrn->scrnIndex,X_ERROR,"Attempt to access VIP bus with non-stadard transaction length\n");
return FALSE;
}
RADEONWaitForFifo(pScrn, 2);
OUTREG(RADEON_VIPH_REG_ADDR, address | 0x2000);
write_mem_barrier();
VIP_WAIT_FOR_IDLE();
if(VIP_IDLE != status) return FALSE;
/*
disable RADEON_VIPH_REGR_DIS to enable VIP cycle.
The LSB of RADEON_VIPH_TIMEOUT_STAT are set to 0
because 1 would have acknowledged various VIP
interrupts unexpectedly
*/
RADEONWaitForIdleMMIO(pScrn);
OUTREG(RADEON_VIPH_TIMEOUT_STAT, INREG(RADEON_VIPH_TIMEOUT_STAT) & (0xffffff00 & ~RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS) );
write_mem_barrier();
/*
the value returned here is garbage. The read merely initiates
a register cycle
*/
RADEONWaitForIdleMMIO(pScrn);
INREG(RADEON_VIPH_REG_DATA);
VIP_WAIT_FOR_IDLE();
if(VIP_IDLE != status) return FALSE;
/*
set RADEON_VIPH_REGR_DIS so that the read won't take too long.
*/
RADEONWaitForIdleMMIO(pScrn);
tmp=INREG(RADEON_VIPH_TIMEOUT_STAT);
OUTREG(RADEON_VIPH_TIMEOUT_STAT, (tmp & 0xffffff00) | RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS);
write_mem_barrier();
RADEONWaitForIdleMMIO(pScrn);
switch(count){
case 1:
*buffer=(uint8_t)(INREG(RADEON_VIPH_REG_DATA) & 0xff);
break;
case 2:
*(uint16_t *)buffer=(uint16_t) (INREG(RADEON_VIPH_REG_DATA) & 0xffff);
break;
case 4:
*(uint32_t *)buffer=(uint32_t) ( INREG(RADEON_VIPH_REG_DATA) & 0xffffffff);
break;
}
VIP_WAIT_FOR_IDLE();
if(VIP_IDLE != status) return FALSE;
/*
so that reading RADEON_VIPH_REG_DATA would not trigger unnecessary vip cycles.
*/
OUTREG(RADEON_VIPH_TIMEOUT_STAT, (INREG(RADEON_VIPH_TIMEOUT_STAT) & 0xffffff00) | RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS);
write_mem_barrier();
return TRUE;
}
static Bool RADEONVIP_fifo_read(GENERIC_BUS_Ptr b, uint32_t address, uint32_t count, uint8_t *buffer)
{
ScrnInfoPtr pScrn = b->pScrn;
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
uint32_t status,tmp;
if(count!=1)
{
xf86DrvMsg(pScrn->scrnIndex,X_ERROR,"Attempt to access VIP bus with non-stadard transaction length\n");
return FALSE;
}
RADEONWaitForFifo(pScrn, 2);
OUTREG(VIPH_REG_ADDR, address | 0x3000);
write_mem_barrier();
while(VIP_BUSY == (status = RADEONVIP_fifo_idle(b, 0xff)));
if(VIP_IDLE != status) return FALSE;
/*
disable VIPH_REGR_DIS to enable VIP cycle.
The LSB of VIPH_TIMEOUT_STAT are set to 0
because 1 would have acknowledged various VIP
interrupts unexpectedly
*/
RADEONWaitForIdleMMIO(pScrn);
OUTREG(VIPH_TIMEOUT_STAT, INREG(VIPH_TIMEOUT_STAT) & (0xffffff00 & ~VIPH_TIMEOUT_STAT__VIPH_REGR_DIS) );
write_mem_barrier();
/*
the value returned here is garbage. The read merely initiates
a register cycle
*/
RADEONWaitForIdleMMIO(pScrn);
INREG(VIPH_REG_DATA);
while(VIP_BUSY == (status = RADEONVIP_fifo_idle(b, 0xff)));
if(VIP_IDLE != status) return FALSE;
/*
set VIPH_REGR_DIS so that the read won't take too long.
*/
RADEONWaitForIdleMMIO(pScrn);
tmp=INREG(VIPH_TIMEOUT_STAT);
OUTREG(VIPH_TIMEOUT_STAT, (tmp & 0xffffff00) | VIPH_TIMEOUT_STAT__VIPH_REGR_DIS);
write_mem_barrier();
RADEONWaitForIdleMMIO(pScrn);
switch(count){
case 1:
*buffer=(uint8_t)(INREG(VIPH_REG_DATA) & 0xff);
break;
case 2:
*(uint16_t *)buffer=(uint16_t) (INREG(VIPH_REG_DATA) & 0xffff);
break;
case 4:
*(uint32_t *)buffer=(uint32_t) ( INREG(VIPH_REG_DATA) & 0xffffffff);
break;
}
while(VIP_BUSY == (status = RADEONVIP_fifo_idle(b, 0xff)));
if(VIP_IDLE != status) return FALSE;
/*
so that reading VIPH_REG_DATA would not trigger unnecessary vip cycles.
*/
OUTREG(VIPH_TIMEOUT_STAT, (INREG(VIPH_TIMEOUT_STAT) & 0xffffff00) | VIPH_TIMEOUT_STAT__VIPH_REGR_DIS);
write_mem_barrier();
return TRUE;
}
static Bool RADEONVIP_write(GENERIC_BUS_Ptr b, uint32_t address, uint32_t count, uint8_t *buffer)
{
ScrnInfoPtr pScrn = b->pScrn;
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
uint32_t status;
if((count!=4))
{
xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Attempt to access VIP bus with non-stadard transaction length\n");
return FALSE;
}
RADEONWaitForFifo(pScrn, 2);
OUTREG(RADEON_VIPH_REG_ADDR, address & (~0x2000));
while(VIP_BUSY == (status = RADEONVIP_idle(b)));
if(VIP_IDLE != status) return FALSE;
RADEONWaitForFifo(pScrn, 2);
switch(count){
case 4:
OUTREG(RADEON_VIPH_REG_DATA, *(uint32_t *)buffer);
break;
}
write_mem_barrier();
while(VIP_BUSY == (status = RADEONVIP_idle(b)));
if(VIP_IDLE != status) return FALSE;
return TRUE;
}
static Bool RADEONVIP_fifo_write(GENERIC_BUS_Ptr b, uint32_t address, uint32_t count, uint8_t *buffer)
{
ScrnInfoPtr pScrn = b->pScrn;
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
uint32_t status;
uint32_t i;
RADEONWaitForFifo(pScrn, 2);
OUTREG(VIPH_REG_ADDR, (address & (~0x2000)) | 0x1000);
while(VIP_BUSY == (status = RADEONVIP_fifo_idle(b, 0x0f)));
if(VIP_IDLE != status){
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "cannot write %x to VIPH_REG_ADDR\n", (unsigned int)address);
return FALSE;
}
RADEONWaitForFifo(pScrn, 2);
for (i = 0; i < count; i+=4)
{
OUTREG(VIPH_REG_DATA, *(uint32_t*)(buffer + i));
write_mem_barrier();
while(VIP_BUSY == (status = RADEONVIP_fifo_idle(b, 0x0f)));
if(VIP_IDLE != status)
{
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "cannot write to VIPH_REG_DATA\n");
return FALSE;
}
}
return TRUE;
}
void RADEONVIP_reset(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
RADEONWaitForIdleMMIO(pScrn);
switch(info->ChipFamily){
case CHIP_FAMILY_RV250:
case CHIP_FAMILY_RV350:
case CHIP_FAMILY_R350:
case CHIP_FAMILY_R300:
OUTREG(RADEON_VIPH_CONTROL, 0x003F0009); /* slowest, timeout in 16 phases */
OUTREG(RADEON_VIPH_TIMEOUT_STAT, (INREG(RADEON_VIPH_TIMEOUT_STAT) & 0xFFFFFF00) | RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS);
OUTREG(RADEON_VIPH_DV_LAT, 0x444400FF); /* set timeslice */
OUTREG(RADEON_VIPH_BM_CHUNK, 0x0);
OUTREG(RADEON_TEST_DEBUG_CNTL, INREG(RADEON_TEST_DEBUG_CNTL) & (~RADEON_TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN));
break;
case CHIP_FAMILY_RV380:
OUTREG(RADEON_VIPH_CONTROL, 0x003F000D); /* slowest, timeout in 16 phases */
OUTREG(RADEON_VIPH_TIMEOUT_STAT, (INREG(RADEON_VIPH_TIMEOUT_STAT) & 0xFFFFFF00) | RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS);
OUTREG(RADEON_VIPH_DV_LAT, 0x444400FF); /* set timeslice */
OUTREG(RADEON_VIPH_BM_CHUNK, 0x0);
OUTREG(RADEON_TEST_DEBUG_CNTL, INREG(RADEON_TEST_DEBUG_CNTL) & (~RADEON_TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN));
break;
default:
OUTREG(RADEON_VIPH_CONTROL, 0x003F0004); /* slowest, timeout in 16 phases */
OUTREG(RADEON_VIPH_TIMEOUT_STAT, (INREG(RADEON_VIPH_TIMEOUT_STAT) & 0xFFFFFF00) | RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS);
OUTREG(RADEON_VIPH_DV_LAT, 0x444400FF); /* set timeslice */
OUTREG(RADEON_VIPH_BM_CHUNK, 0x151);
OUTREG(RADEON_TEST_DEBUG_CNTL, INREG(RADEON_TEST_DEBUG_CNTL) & (~RADEON_TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN));
}
}
void RADEONVIP_init(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
{
pPriv->VIP=calloc(1,sizeof(GENERIC_BUS_Rec));
pPriv->VIP->pScrn=pScrn;
pPriv->VIP->DriverPrivate.ptr=pPriv;
pPriv->VIP->ioctl=RADEONVIP_ioctl;
pPriv->VIP->read=RADEONVIP_read;
pPriv->VIP->write=RADEONVIP_write;
pPriv->VIP->fifo_read=RADEONVIP_fifo_read;
pPriv->VIP->fifo_write=RADEONVIP_fifo_write;
RADEONVIP_reset(pScrn, pPriv);
}
|
