diff options
| author | Matthieu Herrb <matthieu@herrb.eu> | 2019-08-05 23:20:16 +0200 |
|---|---|---|
| committer | Matthieu Herrb <matthieu@herrb.eu> | 2019-08-05 23:39:39 +0200 |
| commit | 88fdb971690c14c7a0fce6d6443c6238df82a88b (patch) | |
| tree | c1389050b10b98a7ee18fb30b49cded01f49b4c5 | |
| parent | bba14e38708adb42a5e8f84791e6bd4147b17dd8 (diff) | |
Initial mesa
XXX not working yet
58 files changed, 4650 insertions, 0 deletions
diff --git a/graphics/mesa/Makefile b/graphics/mesa/Makefile new file mode 100644 index 0000000..1eb3549 --- /dev/null +++ b/graphics/mesa/Makefile @@ -0,0 +1,168 @@ +# $OpenBSD: Makefile.template,v 1.83 2019/07/02 12:03:14 sthen Exp $ + +#ONLY_FOR_ARCHS = ??? +#NOT_FOR_ARCHS = ??? + +COMMENT = the Mesa 3D Graphics Library + +# +# What port/package will be created +# +DISTNAME = mesa-19.0.8 + +SHARED_LIBS = EGL 1.1 gbm 0.4 glapi 0.2 GL 17.1 GLESv1_CM 2.0 GLESv2 2.0 \ + OSMesa 11.0 + +CATEGORIES = graphics + +HOMEPAGE = https://mesa3d.org/ + +MAINTAINER = xenocara@openbsd.org + +# MID +PERMIT_PACKAGE = Yes + +#WANTLIB = ??? + +MASTER_SITES = https://mesa.freedesktop.org/archive/ +EXTRACT_SUFX = .tar.xz + +# Dependencies +#MODULES = ??? +BUILD_DEPENDS = sysutils/libdrm \ + devel/xorgproto \ + x11/libX11 \ + x11/libxcb \ + x11/libXext \ + x11/libXdamage \ + x11/libXfixes \ + x11/libXxf86vm \ + x11/libxshmfence \ + x11/libXrandr \ + www/py-mako + +#RUN_DEPENDS = ??? +#LIB_DEPENDS = ??? +#TEST_DEPENDS = ??? + +#MAKE_FLAGS = ??? +#MAKE_ENV = ??? +#FAKE_FLAGS = ??? +#TEST_FLAGS = ??? + +# build/configuration variables +# +SEPARATE_BUILD = Yes +USE_GMAKE = Yes +#USE_GROFF = Yes +CONFIGURE_STYLE = autoreconf +#CONFIGURE_SCRIPT = ??? (if other than configure) +#CONFIGURE_ARGS = ??? +#CONFIGURE_ENV = ??? + +DRI_DRIVERS= swrast +GALLIUM_DRIVERS= swrast +VULKAN_DRIVERS= no +WITH_LLVM= --disable-llvm + +.if ${MACHINE} == i386 || ${MACHINE} == amd64 +DRI_DRIVERS=swrast,radeon,r200,i915,i965 +GALLIUM_DRIVERS=swrast,r300,r600,radeonsi +VULKAN_DRIVERS= intel,radeon +WITH_LLVM= --enable-llvm +.endif + +.if ${MACHINE} == arm64 || ${MACHINE} == loongson || \ + ${MACHINE} == macppc || ${MACHINE} == sparc64 +DRI_DRIVERS=swrast,radeon,r200 +GALLIUM_DRIVERS=swrast,r300,r600 +.endif + + +CONFIGURE_ARGS= --with-dri-drivers=${DRI_DRIVERS} \ + --with-gallium-drivers=${GALLIUM_DRIVERS} \ + --with-vulkan-drivers=${VULKAN_DRIVERS} \ + --disable-silent-rules \ + ${WITH_LLVM} \ + --disable-glx-tls \ + --disable-regen-sources \ + --enable-gles1 --enable-gles2 \ + --enable-shared-glapi \ + --enable-osmesa \ + --enable-gbm \ + --enable-texture-float \ + --enable-autotools \ + --with-platforms="x11,drm" \ + --prefix=${X11BASE} \ + --with-dri-driverdir=${X11BASE}/lib/modules/dri \ + --with-dri-searchpath=${X11BASE}/lib/modules/dri + +CONFIGURE_ARGS+= --enable-dri3 + +AUTOCONF_VERSION = 2.69 +AUTOMAKE_VERSION = 1.12 + +# Is the build automagic or is it interactive +# +#IS_INTERACTIVE = Yes +#TEST_IS_INTERACTIVE = Yes + +# Assume you have one multiple choice flavor: 1 2 3 and switches a b. +# You would write +# +#FLAVORS = 1 2 3 a b +#FLAVOR ?= +# grab multiple choice value +#CHOICE = ${FLAVOR:Na:Nb} +# check that CHOICE is 1 OR 2 OR 3, or error out +#.if ${CHOICE} == "1" +# code for 1 +#.elif ${CHOICE} == "2" +# code for 2 +#.elif ${CHOICE} == "3" +# code for 3 +#.else +#ERRORS += "Fatal: Conflicting flavor: ${FLAVOR}" +#.endif +# check for switches +#.if ${FLAVOR:Ma} +# code for a +#.endif +#.if ${FLAVOR:Mb} +# code for b +#.endif + +# Things that we don't want to do for this port/package +# Generally, DON'T set anything to No if it's not needed. +# The time gained is not worth it. +# +#NO_BUILD = Yes +#NO_TEST = Yes + +# Overrides for default values +# +#CFLAGS = ??? +#LDFLAGS = ??? +#MAKE_FILE = ??? +#PKG_ARCH = ??? (* for arch-independent packages) +#WRKDIST = ??? if other than ${WRKDIR}/${DISTNAME} +#WRKSRC = ??? if other than ${WRKDIST} +#WRKBUILD = ??? if other than ${WRKSRC} +#WRKCONF = ??? if other than ${WRKBUILD} + +#ALL_TARGET = ??? +#INSTALL_TARGET = ??? +#TEST_TARGET = ??? + +# For ports that use a script or autoreconf to generate autoconf/automake +# files (where "CONFIGURE_STYLE=autoconf" isn't enough), use some/all of these +# dependencies, and add a do-gen target: +# +#BUILD_DEPENDS = ${MODGNU_AUTOCONF_DEPENDS} \ +# ${MODGNU_AUTOMAKE_DEPENDS} \ +# devel/libtool +# +#do-gen: +# cd ${WRKSRC}; ${AUTOCONF_ENV} ./autogen.sh + +.include <bsd.port.mk> diff --git a/graphics/mesa/distinfo b/graphics/mesa/distinfo new file mode 100644 index 0000000..e91a230 --- /dev/null +++ b/graphics/mesa/distinfo @@ -0,0 +1,2 @@ +SHA256 (mesa-19.0.8.tar.xz) = 0BfrU6gQwy2r7t9soiOK4eiXzpCQ5HDpzh1snj8bCGI= +SIZE (mesa-19.0.8.tar.xz) = 11967592 diff --git a/graphics/mesa/patches/patch-configure_ac b/graphics/mesa/patches/patch-configure_ac new file mode 100644 index 0000000..331c162 --- /dev/null +++ b/graphics/mesa/patches/patch-configure_ac @@ -0,0 +1,98 @@ +$OpenBSD$ + +Index: configure.ac +--- configure.ac.orig ++++ configure.ac +@@ -45,6 +45,8 @@ AC_CONFIG_MACRO_DIR([m4]) + AC_CANONICAL_SYSTEM + AM_INIT_AUTOMAKE([foreign tar-ustar dist-xz subdir-objects]) + ++AM_MAINTAINER_MODE ++ + dnl We only support native Windows builds (MinGW/MSVC) through SCons. + case "$host_os" in + mingw*) +@@ -182,6 +184,15 @@ else + fi + fi + ++dnl Avoid attempting to rebuild files with python and yacc ++AC_ARG_ENABLE([regen-sources], ++ [AS_HELP_STRING([--disable-regen-sources], ++ [disable regenerating source with python and yacc @<:@default=enabled@:>@])], ++ [regen_sources="$enableval"], ++ [regen_sources=yes]) ++ ++AM_CONDITIONAL(REGEN_SOURCES, test "x$regen_sources" = xyes) ++ + AC_PROG_INSTALL + + dnl We need a POSIX shell for parts of the build. Assume we have one +@@ -503,6 +514,19 @@ if test "x$GCC_ATOMIC_BUILTINS_SUPPORTED" = xyes; then + fi + AC_SUBST([LIBATOMIC_LIBS]) + ++dnl Check if host supports 32-bit atomics ++AC_MSG_CHECKING(whether __sync_add_and_fetch_4 is supported) ++AC_LINK_IFELSE([AC_LANG_SOURCE([[ ++#include <stdint.h> ++uint64_t v; ++int main() { ++ return __sync_add_and_fetch(&v, (uint32_t)1); ++}]])], GCC_32BIT_ATOMICS_SUPPORTED=yes, GCC_32BIT_ATOMICS_SUPPORTED=no) ++if test "x$GCC_32BIT_ATOMICS_SUPPORTED" != xyes; then ++ DEFINES="$DEFINES -DMISSING_32BIT_ATOMICS" ++fi ++AC_MSG_RESULT($GCC_32BIT_ATOMICS_SUPPORTED) ++ + dnl Check if host supports 64-bit atomics + dnl note that lack of support usually results in link (not compile) error + AC_MSG_CHECKING(whether __sync_add_and_fetch_8 is supported) +@@ -736,16 +760,19 @@ LDFLAGS=$save_LDFLAGS + AM_CONDITIONAL(HAVE_LD_DYNAMIC_LIST, test "$have_ld_dynamic_list" = "yes") + + dnl +-dnl OSX linker does not support build-id ++dnl Check if linker supports build-id + dnl +-case "$host_os" in +-darwin*) +- LD_BUILD_ID="" +- ;; +-*) +- LD_BUILD_ID="-Wl,--build-id=sha1" +- ;; +-esac ++save_LDFLAGS=$LDFLAGS ++LDFLAGS="$LDFLAGS -Wl,--build-id=sha1" ++AC_MSG_CHECKING([if ld supports build-id]) ++AC_LINK_IFELSE( ++ [AC_LANG_SOURCE([int main() { return 0;}])], ++ [AC_MSG_RESULT([yes]) ++ LD_BUILD_ID="-Wl,--build-id=sha1";DEFINES="$DEFINES -DHAVE_LD_BUILD_ID";], ++ [AC_MSG_RESULT([no]) ++ LD_BUILD_ID="";]) ++LDFLAGS=$save_LDFLAGS ++ + AC_SUBST([LD_BUILD_ID]) + + dnl +@@ -954,6 +981,9 @@ esac + dnl See if posix_memalign is available + AC_CHECK_FUNC([posix_memalign], [DEFINES="$DEFINES -DHAVE_POSIX_MEMALIGN"]) + ++dnl See if arc4random_buf is available ++AC_CHECK_FUNC([arc4random_buf], [DEFINES="$DEFINES -DHAVE_ARC4RANDOM_BUF"]) ++ + dnl Check for zlib + PKG_CHECK_MODULES([ZLIB], [zlib >= $ZLIB_REQUIRED]) + DEFINES="$DEFINES -DHAVE_ZLIB" +@@ -2704,7 +2734,7 @@ if test -n "$with_gallium_drivers"; then + HAVE_GALLIUM_R300=yes + PKG_CHECK_MODULES([RADEON], [libdrm >= $LIBDRM_RADEON_REQUIRED libdrm_radeon >= $LIBDRM_RADEON_REQUIRED]) + require_libdrm "r300" +- r300_require_llvm "r300" ++# r300_require_llvm "r300" + ;; + xr600) + HAVE_GALLIUM_R600=yes diff --git a/graphics/mesa/patches/patch-src_Makefile_am b/graphics/mesa/patches/patch-src_Makefile_am new file mode 100644 index 0000000..5a58d66 --- /dev/null +++ b/graphics/mesa/patches/patch-src_Makefile_am @@ -0,0 +1,17 @@ +$OpenBSD$ + +Index: src/Makefile.am +--- src/Makefile.am.orig ++++ src/Makefile.am +@@ -22,7 +22,11 @@ + .PHONY: git_sha1.h + git_sha1.h: + @echo "updating $@" ++if REGEN_SOURCES + @$(PYTHON) $(top_srcdir)/bin/git_sha1_gen.py --output $@ ++else ++ @echo '#define MESA_GIT_SHA1 ""' > $@ ++endif + + BUILT_SOURCES = git_sha1.h + CLEANFILES = $(BUILT_SOURCES) diff --git a/graphics/mesa/patches/patch-src_amd_Makefile_common_am b/graphics/mesa/patches/patch-src_amd_Makefile_common_am new file mode 100644 index 0000000..9212f34 --- /dev/null +++ b/graphics/mesa/patches/patch-src_amd_Makefile_common_am @@ -0,0 +1,16 @@ +$OpenBSD$ + +Index: src/amd/Makefile.common.am +--- src/amd/Makefile.common.am.orig ++++ src/amd/Makefile.common.am +@@ -64,8 +64,10 @@ endif + + common_libamd_common_la_LIBADD = $(LIBELF_LIBS) + ++if REGEN_SOURCES + common/sid_tables.h: $(srcdir)/common/sid_tables.py $(srcdir)/common/sid.h $(srcdir)/common/gfx9d.h + $(AM_V_at)$(MKDIR_P) $(@D) + $(AM_V_GEN) $(PYTHON) $(srcdir)/common/sid_tables.py $(srcdir)/common/sid.h $(srcdir)/common/gfx9d.h > $@ ++endif + + BUILT_SOURCES = $(AMD_GENERATED_FILES) diff --git a/graphics/mesa/patches/patch-src_amd_vulkan_Makefile_am b/graphics/mesa/patches/patch-src_amd_vulkan_Makefile_am new file mode 100644 index 0000000..9a5e693 --- /dev/null +++ b/graphics/mesa/patches/patch-src_amd_vulkan_Makefile_am @@ -0,0 +1,50 @@ +$OpenBSD$ + +Index: src/amd/vulkan/Makefile.am +--- src/amd/vulkan/Makefile.am.orig ++++ src/amd/vulkan/Makefile.am +@@ -138,6 +138,7 @@ libvulkan_radeon_la_SOURCES = $(VULKAN_GEM_FILES) + + vulkan_api_xml = $(top_srcdir)/src/vulkan/registry/vk.xml + ++if REGEN_SOURCES + radv_entrypoints.c: radv_entrypoints_gen.py radv_extensions.py $(vulkan_api_xml) + $(MKDIR_GEN) + $(AM_V_GEN)$(PYTHON) $(srcdir)/radv_entrypoints_gen.py \ +@@ -158,6 +159,7 @@ vk_format_table.c: vk_format_table.py \ + vk_format_parse.py \ + vk_format_layout.csv + $(PYTHON) $(srcdir)/vk_format_table.py $(srcdir)/vk_format_layout.csv > $@ ++endif + + BUILT_SOURCES = $(VULKAN_GENERATED_FILES) + CLEANFILES = $(BUILT_SOURCES) dev_icd.json radeon_icd.@host_cpu@.json +@@ -189,6 +191,7 @@ icdconf_DATA = radeon_icd.@host_cpu@.json + # The following is used for development purposes, by setting VK_ICD_FILENAMES. + noinst_DATA = dev_icd.json + ++if REGEN_SOURCES + dev_icd.json : radv_extensions.py radv_icd.py + $(AM_V_GEN)$(PYTHON) $(srcdir)/radv_icd.py \ + --lib-path="${abs_top_builddir}/${LIB_DIR}" --out $@ +@@ -196,5 +199,20 @@ dev_icd.json : radv_extensions.py radv_icd.py + radeon_icd.@host_cpu@.json : radv_extensions.py radv_icd.py + $(AM_V_GEN)$(PYTHON) $(srcdir)/radv_icd.py \ + --lib-path="${libdir}" --out $@ ++else ++radeon_icd.@host_cpu@.json : ++ @echo -e "{" > $@ ++ @echo -e " \"ICD\": {" >> $@ ++ @echo -e " \"api_version\": \"1.1.70\"," >> $@ ++ @echo -e " \"library_path\": \"${libdir}/libvulkan_radeon.so\"" >> $@ ++ @echo -e " }," >> $@ ++ @echo -e " \"file_format_version\": \"1.0.0\"" >> $@ ++ @echo -ne "}" >> $@ ++ ++.PHONY: radeon_icd.@host_cpu@.json ++ ++dev_icd.json : radeon_icd.@host_cpu@.json ++ cp radeon_icd.@host_cpu@.json $@ ++endif + + include $(top_srcdir)/install-lib-links.mk diff --git a/graphics/mesa/patches/patch-src_amd_vulkan_radv_device_c b/graphics/mesa/patches/patch-src_amd_vulkan_radv_device_c new file mode 100644 index 0000000..75079f9 --- /dev/null +++ b/graphics/mesa/patches/patch-src_amd_vulkan_radv_device_c @@ -0,0 +1,16 @@ +$OpenBSD$ + +Index: src/amd/vulkan/radv_device.c +--- src/amd/vulkan/radv_device.c.orig ++++ src/amd/vulkan/radv_device.c +@@ -49,6 +49,10 @@ + #include "util/debug.h" + #include "util/mesa-sha1.h" + ++#ifndef CLOCK_MONOTONIC_RAW ++#define CLOCK_MONOTONIC_RAW CLOCK_MONOTONIC ++#endif ++ + static int + radv_device_get_cache_uuid(enum radeon_family family, void *uuid) + { diff --git a/graphics/mesa/patches/patch-src_amd_vulkan_winsys_amdgpu_radv_amdgpu_cs_c b/graphics/mesa/patches/patch-src_amd_vulkan_winsys_amdgpu_radv_amdgpu_cs_c new file mode 100644 index 0000000..1c36697 --- /dev/null +++ b/graphics/mesa/patches/patch-src_amd_vulkan_winsys_amdgpu_radv_amdgpu_cs_c @@ -0,0 +1,15 @@ +$OpenBSD$ + +Index: src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c +--- src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c.orig ++++ src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c +@@ -35,6 +35,9 @@ + #include "radv_amdgpu_bo.h" + #include "sid.h" + ++#ifndef ETIME ++#define ETIME ETIMEDOUT ++#endif + + enum { + VIRTUAL_BUFFER_HASH_TABLE_SIZE = 1024 diff --git a/graphics/mesa/patches/patch-src_broadcom_Makefile_genxml_am b/graphics/mesa/patches/patch-src_broadcom_Makefile_genxml_am new file mode 100644 index 0000000..a222486 --- /dev/null +++ b/graphics/mesa/patches/patch-src_broadcom_Makefile_genxml_am @@ -0,0 +1,21 @@ +$OpenBSD$ + +Index: src/broadcom/Makefile.genxml.am +--- src/broadcom/Makefile.genxml.am.orig ++++ src/broadcom/Makefile.genxml.am +@@ -28,6 +28,7 @@ SUFFIXES = _pack.h .xml + + $(BROADCOM_GENXML_GENERATED_FILES): cle/gen_pack_header.py + ++if REGEN_SOURCES + cle/v3d_packet_v21_pack.h: $(srcdir)/cle/v3d_packet_v21.xml $(srcdir)/cle/gen_pack_header.py + $(MKDIR_GEN) + $(PYTHON_GEN) $(srcdir)/cle/gen_pack_header.py $< 21 > $@ || ($(RM) $@; false) +@@ -48,6 +49,7 @@ GEN_ZIPPED = $(srcdir)/../intel/genxml/gen_zipped_file + cle/v3d_xml.h: $(GEN_ZIPPED) $(BROADCOM_GENXML_XML_FILES) + $(MKDIR_GEN) + $(PYTHON_GEN) $(GEN_ZIPPED) $(BROADCOM_GENXML_XML_FILES:%=$(srcdir)/%) > $@ || ($(RM) $@; false) ++endif + + EXTRA_DIST += \ + cle/gen_pack_header.py \ diff --git a/graphics/mesa/patches/patch-src_compiler_Makefile_glsl_am b/graphics/mesa/patches/patch-src_compiler_Makefile_glsl_am new file mode 100644 index 0000000..8445e4f --- /dev/null +++ b/graphics/mesa/patches/patch-src_compiler_Makefile_glsl_am @@ -0,0 +1,21 @@ +$OpenBSD$ + +Index: src/compiler/Makefile.glsl.am +--- src/compiler/Makefile.glsl.am.orig ++++ src/compiler/Makefile.glsl.am +@@ -199,6 +199,7 @@ am__v_YACC_1 = + YACC_GEN = $(AM_V_YACC)$(YACC) $(YFLAGS) + LEX_GEN = $(AM_V_LEX)$(LEX) $(LFLAGS) + ++if REGEN_SOURCES + glsl/glsl_parser.cpp glsl/glsl_parser.h: glsl/glsl_parser.yy + $(MKDIR_GEN) + $(YACC_GEN) -o $@ -p "_mesa_glsl_" --defines=$(builddir)/glsl/glsl_parser.h $(srcdir)/glsl/glsl_parser.yy +@@ -226,6 +227,7 @@ glsl/ir_expression_operation_constant.h: glsl/ir_expre + glsl/ir_expression_operation_strings.h: glsl/ir_expression_operation.py + $(MKDIR_GEN) + $(PYTHON_GEN) $(srcdir)/glsl/ir_expression_operation.py strings > $@ || ($(RM) $@; false) ++endif + + glsl/float64_glsl.h: glsl/xxd.py glsl/float64.glsl + $(MKDIR_GEN) diff --git a/graphics/mesa/patches/patch-src_compiler_Makefile_nir_am b/graphics/mesa/patches/patch-src_compiler_Makefile_nir_am new file mode 100644 index 0000000..223a451 --- /dev/null +++ b/graphics/mesa/patches/patch-src_compiler_Makefile_nir_am @@ -0,0 +1,21 @@ +$OpenBSD$ + +Index: src/compiler/Makefile.nir.am +--- src/compiler/Makefile.nir.am.orig ++++ src/compiler/Makefile.nir.am +@@ -32,6 +32,7 @@ nir_libnir_la_SOURCES = \ + $(SPIRV_GENERATED_FILES) \ + $(NIR_GENERATED_FILES) + ++if REGEN_SOURCES + nir/nir_builder_opcodes.h: nir/nir_opcodes.py nir/nir_builder_opcodes_h.py nir/nir_intrinsics.py + $(MKDIR_GEN) + $(PYTHON_GEN) $(srcdir)/nir/nir_builder_opcodes_h.py > $@ || ($(RM) $@; false) +@@ -59,6 +60,7 @@ nir/nir_opcodes.c: nir/nir_opcodes.py nir/nir_opcodes_ + nir/nir_opt_algebraic.c: nir/nir_opt_algebraic.py nir/nir_algebraic.py + $(MKDIR_GEN) + $(PYTHON_GEN) $(srcdir)/nir/nir_opt_algebraic.py > $@ || ($(RM) $@; false) ++endif + + check_PROGRAMS += \ + nir/tests/control_flow_tests \ diff --git a/graphics/mesa/patches/patch-src_compiler_Makefile_spirv_am b/graphics/mesa/patches/patch-src_compiler_Makefile_spirv_am new file mode 100644 index 0000000..f5b1287 --- /dev/null +++ b/graphics/mesa/patches/patch-src_compiler_Makefile_spirv_am @@ -0,0 +1,21 @@ +$OpenBSD$ + +Index: src/compiler/Makefile.spirv.am +--- src/compiler/Makefile.spirv.am.orig ++++ src/compiler/Makefile.spirv.am +@@ -20,6 +20,7 @@ + # FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + # IN THE SOFTWARE. + ++if REGEN_SOURCES + spirv/spirv_info.c: spirv/spirv_info_c.py spirv/spirv.core.grammar.json + $(MKDIR_GEN) + $(PYTHON_GEN) $(srcdir)/spirv/spirv_info_c.py $(srcdir)/spirv/spirv.core.grammar.json $@ || ($(RM) $@; false) +@@ -27,6 +28,7 @@ spirv/spirv_info.c: spirv/spirv_info_c.py spirv/spirv. + spirv/vtn_gather_types.c: spirv/vtn_gather_types_c.py spirv/spirv.core.grammar.json + $(MKDIR_GEN) + $(PYTHON_GEN) $(srcdir)/spirv/vtn_gather_types_c.py $(srcdir)/spirv/spirv.core.grammar.json $@ || ($(RM) $@; false) ++endif + + noinst_PROGRAMS += spirv2nir + diff --git a/graphics/mesa/patches/patch-src_compiler_glsl_ast_h b/graphics/mesa/patches/patch-src_compiler_glsl_ast_h new file mode 100644 index 0000000..bc164d2 --- /dev/null +++ b/graphics/mesa/patches/patch-src_compiler_glsl_ast_h @@ -0,0 +1,14 @@ +$OpenBSD$ + +Index: src/compiler/glsl/ast.h +--- src/compiler/glsl/ast.h.orig ++++ src/compiler/glsl/ast.h +@@ -891,7 +891,7 @@ class ast_type_specifier : public ast_node { (public) + /* empty */ + } + +- ast_type_specifier(const glsl_type *t) ++ ast_type_specifier(const struct glsl_type *t) + : type(t), type_name(t->name), structure(NULL), array_specifier(NULL), + default_precision(ast_precision_none) + { diff --git a/graphics/mesa/patches/patch-src_egl_Makefile_am b/graphics/mesa/patches/patch-src_egl_Makefile_am new file mode 100644 index 0000000..904bb25 --- /dev/null +++ b/graphics/mesa/patches/patch-src_egl_Makefile_am @@ -0,0 +1,21 @@ +$OpenBSD$ + +Index: src/egl/Makefile.am +--- src/egl/Makefile.am.orig ++++ src/egl/Makefile.am +@@ -149,6 +149,7 @@ GLVND_GEN_DEPS = $(top_scrdir)/src/mapi/new/genCommon. + $(GLVND_GEN_EGL_DEPS) + + PYTHON_GEN = $(AM_V_GEN)$(PYTHON) $(PYTHON_FLAGS) ++if REGEN_SOURCES + g_egldispatchstubs.c: $(GLVND_GEN_DEPS) + $(PYTHON_GEN) $(top_srcdir)/src/egl/generate/gen_egl_dispatch.py source \ + $(top_srcdir)/src/egl/generate/egl.xml \ +@@ -158,6 +159,7 @@ g_egldispatchstubs.h: $(GLVND_GEN_DEPS) + $(PYTHON_GEN) $(top_srcdir)/src/egl/generate/gen_egl_dispatch.py header \ + $(top_srcdir)/src/egl/generate/egl.xml \ + $(top_srcdir)/src/egl/generate/egl_other.xml > $@ ++endif + + BUILT_SOURCES += g_egldispatchstubs.c g_egldispatchstubs.h + diff --git a/graphics/mesa/patches/patch-src_gallium_auxiliary_Makefile_am b/graphics/mesa/patches/patch-src_gallium_auxiliary_Makefile_am new file mode 100644 index 0000000..061b36a --- /dev/null +++ b/graphics/mesa/patches/patch-src_gallium_auxiliary_Makefile_am @@ -0,0 +1,21 @@ +$OpenBSD$ + +Index: src/gallium/auxiliary/Makefile.am +--- src/gallium/auxiliary/Makefile.am.orig ++++ src/gallium/auxiliary/Makefile.am +@@ -54,6 +54,7 @@ libgallium_la_SOURCES += \ + endif + + MKDIR_GEN = $(AM_V_at)$(MKDIR_P) $(@D) ++if REGEN_SOURCES + PYTHON_GEN = $(AM_V_GEN)$(PYTHON) $(PYTHON_FLAGS) + + indices/u_indices_gen.c: indices/u_indices_gen.py +@@ -70,6 +71,7 @@ util/u_format_table.c: util/u_format_table.py \ + util/u_format.csv + $(MKDIR_GEN) + $(PYTHON_GEN) $(srcdir)/util/u_format_table.py $(srcdir)/util/u_format.csv > $@ ++endif + + noinst_LTLIBRARIES += libgalliumvl_stub.la + libgalliumvl_stub_la_SOURCES = \ diff --git a/graphics/mesa/patches/patch-src_gallium_auxiliary_rtasm_rtasm_execmem_c b/graphics/mesa/patches/patch-src_gallium_auxiliary_rtasm_rtasm_execmem_c new file mode 100644 index 0000000..7b5200b --- /dev/null +++ b/graphics/mesa/patches/patch-src_gallium_auxiliary_rtasm_rtasm_execmem_c @@ -0,0 +1,34 @@ +$OpenBSD$ + +Index: src/gallium/auxiliary/rtasm/rtasm_execmem.c +--- src/gallium/auxiliary/rtasm/rtasm_execmem.c.orig ++++ src/gallium/auxiliary/rtasm/rtasm_execmem.c +@@ -69,9 +69,19 @@ static struct mem_block *exec_heap = NULL; + static unsigned char *exec_mem = NULL; + + ++#ifdef __OpenBSD__ ++ + static int + init_heap(void) + { ++ return 0; ++} ++ ++#else ++ ++static int ++init_heap(void) ++{ + if (!exec_heap) + exec_heap = u_mmInit( 0, EXEC_HEAP_SIZE ); + +@@ -82,6 +92,8 @@ init_heap(void) + + return (exec_mem != MAP_FAILED); + } ++ ++#endif + + + void * diff --git a/graphics/mesa/patches/patch-src_gallium_drivers_r600_Makefile_am b/graphics/mesa/patches/patch-src_gallium_drivers_r600_Makefile_am new file mode 100644 index 0000000..8bc59c7 --- /dev/null +++ b/graphics/mesa/patches/patch-src_gallium_drivers_r600_Makefile_am @@ -0,0 +1,17 @@ +$OpenBSD$ + +Index: src/gallium/drivers/r600/Makefile.am +--- src/gallium/drivers/r600/Makefile.am.orig ++++ src/gallium/drivers/r600/Makefile.am +@@ -1,9 +1,11 @@ + include Makefile.sources + include $(top_srcdir)/src/gallium/Automake.inc + ++if REGEN_SOURCES + egd_tables.h: $(srcdir)/egd_tables.py $(srcdir)/evergreend.h + $(AM_V_at)$(MKDIR_P) $(@D) + $(AM_V_GEN) $(PYTHON) $(srcdir)/egd_tables.py $(srcdir)/evergreend.h > $@ ++endif + + BUILT_SOURCES = $(R600_GENERATED_FILES) + AM_CFLAGS = \ diff --git a/graphics/mesa/patches/patch-src_gallium_drivers_r600_egd_tables_h b/graphics/mesa/patches/patch-src_gallium_drivers_r600_egd_tables_h new file mode 100644 index 0000000..f37fcc9 --- /dev/null +++ b/graphics/mesa/patches/patch-src_gallium_drivers_r600_egd_tables_h @@ -0,0 +1,2860 @@ +$OpenBSD$ + +Index: src/gallium/drivers/r600/egd_tables.h +--- src/gallium/drivers/r600/egd_tables.h.orig ++++ src/gallium/drivers/r600/egd_tables.h +@@ -0,0 +1,2854 @@ ++/* This file is autogenerated by egd_tables.py from evergreend.h. Do not edit directly. */ ++ ++/* ++ * Copyright 2015 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * on the rights to use, copy, modify, merge, publish, distribute, sub ++ * license, and/or sell copies of the Software, and to permit persons to whom ++ * the Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice (including the next ++ * paragraph) shall be included in all copies or substantial portions of the ++ * Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL ++ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, ++ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR ++ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE ++ * USE OR OTHER DEALINGS IN THE SOFTWARE. ++ * ++ */ ++ ++#ifndef EG_TABLES_H ++#define EG_TABLES_H ++ ++struct eg_field { ++ unsigned name_offset; ++ unsigned mask; ++ unsigned num_values; ++ unsigned values_offset; /* offset into eg_strings_offsets */ ++}; ++ ++struct eg_reg { ++ unsigned name_offset; ++ unsigned offset; ++ unsigned num_fields; ++ unsigned fields_offset; ++}; ++ ++struct eg_packet3 { ++ unsigned name_offset; ++ unsigned op; ++}; ++ ++static const struct eg_packet3 packet3_table[] = { ++ {0, PKT3_NOP}, ++ {4, PKT3_DEALLOC_STATE}, ++ {18, PKT3_DISPATCH_DIRECT}, ++ {34, PKT3_DISPATCH_INDIRECT}, ++ {52, PKT3_INDIRECT_BUFFER_END}, ++ {72, PKT3_SET_PREDICATION}, ++ {88, PKT3_REG_RMW}, ++ {96, PKT3_COND_EXEC}, ++ {106, PKT3_PRED_EXEC}, ++ {116, PKT3_DRAW_INDEX_2}, ++ {129, PKT3_CONTEXT_CONTROL}, ++ {145, PKT3_DRAW_INDEX_IMMD_BE}, ++ {164, PKT3_INDEX_TYPE}, ++ {175, PKT3_DRAW_INDEX}, ++ {186, PKT3_DRAW_INDEX_AUTO}, ++ {202, PKT3_DRAW_INDEX_IMMD}, ++ {218, PKT3_NUM_INSTANCES}, ++ {232, PKT3_STRMOUT_BUFFER_UPDATE}, ++ {254, PKT3_INDIRECT_BUFFER_MP}, ++ {273, PKT3_MEM_SEMAPHORE}, ++ {287, PKT3_MPEG_INDEX}, ++ {298, PKT3_WAIT_REG_MEM}, ++ {311, PKT3_MEM_WRITE}, ++ {321, PKT3_INDIRECT_BUFFER}, ++ {337, PKT3_PFP_SYNC_ME}, ++ {349, PKT3_SURFACE_SYNC}, ++ {362, PKT3_ME_INITIALIZE}, ++ {376, PKT3_COND_WRITE}, ++ {387, PKT3_EVENT_WRITE}, ++ {399, PKT3_EVENT_WRITE_EOP}, ++ {415, PKT3_EVENT_WRITE_EOS}, ++ {431, PKT3_ONE_REG_WRITE}, ++ {445, PKT3_SET_CONFIG_REG}, ++ {460, PKT3_SET_CONTEXT_REG}, ++ {476, PKT3_SET_ALU_CONST}, ++ {490, PKT3_SET_BOOL_CONST}, ++ {505, PKT3_SET_LOOP_CONST}, ++ {520, PKT3_SET_RESOURCE}, ++ {533, PKT3_SET_SAMPLER}, ++ {545, PKT3_SET_CTL_CONST}, ++ {559, PKT3_SURFACE_BASE_UPDATE}, ++ {579, PKT3_IT_OPCODE_C}, ++ {591, PKT3_CP_DMA}, ++ {598, PKT3_SET_APPEND_CNT}, ++ {613, PKT3_SAC_SRC_SEL_DATA}, ++ {630, PKT3_SAC_SRC_SEL_REG}, ++ {646, PKT3_SAC_SRC_SEL_GDS}, ++ {662, PKT3_SAC_SRC_SEL_MEM}, ++}; ++ ++static const struct eg_field egd_fields_table[] = { ++ /* 0 */ ++ {678, S_0084FC_OFFSET_UPDATE_DONE(~0u)}, ++ /* 1 */ ++ {697, S_028B94_STREAMOUT_0_EN(~0u)}, ++ {712, S_028B94_STREAMOUT_1_EN(~0u)}, ++ {727, S_028B94_STREAMOUT_2_EN(~0u)}, ++ {742, S_028B94_STREAMOUT_3_EN(~0u)}, ++ {757, S_028B94_RAST_STREAM(~0u)}, ++ {769, S_028B94_RAST_STREAM_MASK(~0u)}, ++ {786, S_028B94_USE_RAST_STREAM_MASK(~0u)}, ++ /* 8 */ ++ {807, S_028B98_STREAM_0_BUFFER_EN(~0u)}, ++ {826, S_028B98_STREAM_1_BUFFER_EN(~0u)}, ++ {845, S_028B98_STREAM_2_BUFFER_EN(~0u)}, ++ {864, S_028B98_STREAM_3_BUFFER_EN(~0u)}, ++ {883, S_028804_MAX_ANCHOR_SAMPLES(~0u)}, ++ {902, S_028804_PS_ITER_SAMPLES(~0u)}, ++ {918, S_028804_MASK_EXPORT_NUM_SAMPLES(~0u)}, ++ {942, S_028804_ALPHA_TO_MASK_NUM_SAMPLES(~0u)}, ++ {968, S_028804_HIGH_QUALITY_INTERSECTIONS(~0u)}, ++ {995, S_028804_INCOHERENT_EQAA_READS(~0u)}, ++ {1017, S_028804_INTERPOLATE_COMP_Z(~0u)}, ++ {1036, S_028804_INTERPOLATE_SRC_Z(~0u)}, ++ {1054, S_028804_STATIC_ANCHOR_ASSOCIATIONS(~0u)}, ++ {1081, S_028804_ALPHA_TO_MASK_EQAA_DISABLE(~0u)}, ++ {1108, S_028804_OVERRASTERIZATION_AMOUNT(~0u)}, ++ {1133, S_028804_ENABLE_POSTZ_OVERRASTERIZATION(~0u)}, ++ {1164, S_028BDC_EXPAND_LINE_WIDTH(~0u)}, ++ {1182, S_028BDC_LAST_PIXEL(~0u)}, ++ {1193, S_028BDC_PERPENDICULAR_ENDCAP_ENA(~0u)}, ++ {1218, S_028BDC_DX10_DIAMOND_TEST_ENA(~0u)}, ++ {1240, S_028BE0_MSAA_NUM_SAMPLES(~0u)}, ++ {1257, S_028BE0_AA_MASK_CENTROID_DTMN(~0u)}, ++ {1279, S_028BE0_MAX_SAMPLE_DIST(~0u)}, ++ {1295, S_028BE0_MSAA_EXPOSED_SAMPLES(~0u)}, ++ {1316, S_028BE0_DETAIL_TO_EXPOSED_MODE(~0u)}, ++ /* 33 */ ++ {1339, S_008C00_VC_ENABLE(~0u)}, ++ {1349, S_008C00_EXPORT_SRC_C(~0u)}, ++ {1362, S_008C00_CS_PRIO(~0u)}, ++ {1370, S_008C00_LS_PRIO(~0u)}, ++ {1378, S_008C00_HS_PRIO(~0u)}, ++ {1386, S_008C00_PS_PRIO(~0u)}, ++ {1394, S_008C00_VS_PRIO(~0u)}, ++ {1402, S_008C00_GS_PRIO(~0u)}, ++ {1410, S_008C00_ES_PRIO(~0u)}, ++ /* 42 */ ++ {1418, S_008C04_NUM_PS_GPRS(~0u)}, ++ {1430, S_008C04_NUM_VS_GPRS(~0u)}, ++ {1442, S_008C04_NUM_CLAUSE_TEMP_GPRS(~0u)}, ++ /* 45 */ ++ {1463, S_008C08_NUM_GS_GPRS(~0u)}, ++ {1475, S_008C08_NUM_ES_GPRS(~0u)}, ++ /* 47 */ ++ {1487, S_008C0C_NUM_HS_GPRS(~0u)}, ++ {1499, S_008C0C_NUM_LS_GPRS(~0u)}, ++ /* 49 */ ++ {1511, S_008C18_NUM_PS_THREADS(~0u)}, ++ {1526, S_008C18_NUM_VS_THREADS(~0u)}, ++ {1541, S_008C18_NUM_GS_THREADS(~0u)}, ++ {1556, S_008C18_NUM_ES_THREADS(~0u)}, ++ /* 53 */ ++ {1571, S_008C1C_NUM_HS_THREADS(~0u)}, ++ {1586, S_008C1C_NUM_LS_THREADS(~0u)}, ++ /* 55 */ ++ {1601, S_008C20_NUM_PS_STACK_ENTRIES(~0u)}, ++ {1622, S_008C20_NUM_VS_STACK_ENTRIES(~0u)}, ++ /* 57 */ ++ {1643, S_008C24_NUM_GS_STACK_ENTRIES(~0u)}, ++ {1664, S_008C24_NUM_ES_STACK_ENTRIES(~0u)}, ++ /* 59 */ ++ {1685, S_008C28_NUM_HS_STACK_ENTRIES(~0u)}, ++ {1706, S_008C28_NUM_LS_STACK_ENTRIES(~0u)}, ++ /* 61 */ ++ {1727, S_008E2C_NUM_PS_LDS(~0u)}, ++ {1738, S_008E2C_NUM_LS_LDS(~0u)}, ++ /* 63 */ ++ {1749, S_008CF0_CACHE_FIFO_SIZE(~0u)}, ++ {1765, S_008CF0_FETCH_FIFO_HIWATER(~0u)}, ++ {1784, S_008CF0_DONE_FIFO_HIWATER(~0u)}, ++ {1802, S_008CF0_ALU_UPDATE_FIFO_HIWATER(~0u)}, ++ /* 67 */ ++ {1826, S_00913C_VTX_DONE_DELAY(~0u)}, ++ /* 68 */ ++ {1841, S_028C64_PITCH_TILE_MAX(~0u)}, ++ /* 69 */ ++ {1856, S_028C68_SLICE_TILE_MAX(~0u)}, ++ /* 70 */ ++ {1871, S_028C70_ENDIAN(~0u)}, ++ {2408, S_028C70_FORMAT(~0u), 49, 0}, ++ {2499, S_028C70_ARRAY_MODE(~0u), 5, 49}, ++ {2615, S_028C70_NUMBER_TYPE(~0u), 8, 54}, ++ {2671, S_028C70_COMP_SWAP(~0u), 4, 62}, ++ {2681, S_028C70_FAST_CLEAR(~0u)}, ++ {2692, S_028C70_COMPRESSION(~0u)}, ++ {2704, S_028C70_BLEND_CLAMP(~0u)}, ++ {2716, S_028C70_BLEND_BYPASS(~0u)}, ++ {2729, S_028C70_SIMPLE_FLOAT(~0u)}, ++ {2742, S_028C70_ROUND_MODE(~0u)}, ++ {2753, S_028C70_TILE_COMPACT(~0u)}, ++ {2814, S_028C70_SOURCE_FORMAT(~0u), 3, 66}, ++ {2828, S_028C70_RAT(~0u)}, ++ {2892, S_028C70_RESOURCE_TYPE(~0u), 6, 69}, ++ /* 85 */ ++ {2906, S_028C74_NON_DISP_TILING_ORDER(~0u)}, ++ {2928, S_028C74_TILE_SPLIT(~0u)}, ++ {2939, S_028C74_NUM_BANKS(~0u)}, ++ {2949, S_028C74_BANK_WIDTH(~0u)}, ++ {2960, S_028C74_BANK_HEIGHT(~0u)}, ++ {2972, S_028C74_MACRO_TILE_ASPECT(~0u)}, ++ {2990, S_028C74_FMASK_BANK_HEIGHT(~0u)}, ++ {930, S_028C74_NUM_SAMPLES(~0u)}, ++ {3008, S_028C74_NUM_FRAGMENTS(~0u)}, ++ {3022, S_028C74_FORCE_DST_ALPHA_1(~0u)}, ++ /* 95 */ ++ {3040, S_028C78_WIDTH_MAX(~0u)}, ++ {3050, S_028C78_HEIGHT_MAX(~0u)}, ++ /* 97 */ ++ {3061, S_028410_ALPHA_FUNC(~0u)}, ++ {3072, S_028410_ALPHA_TEST_ENABLE(~0u)}, ++ {3090, S_028410_ALPHA_TEST_BYPASS(~0u)}, ++ /* 100 */ ++ {170, S_028B6C_TYPE(~0u), 3, 75}, ++ {3197, S_028B6C_PARTITIONING(~0u), 4, 78}, ++ {3274, S_028B6C_TOPOLOGY(~0u), 4, 82}, ++ {3283, S_028B6C_RESERVED_REDUC_AXIS(~0u)}, ++ {3324, S_028B6C_BUFFER_ACCESS_MODE(~0u), 2, 86}, ++ {3343, S_028B6C_NUM_DS_WAVES_PER_SIMD(~0u)}, ++ /* 106 */ ++ {3365, S_028800_STENCIL_ENABLE(~0u)}, ++ {3380, S_028800_Z_ENABLE(~0u)}, ++ {3389, S_028800_Z_WRITE_ENABLE(~0u)}, ++ {3404, S_028800_ZFUNC(~0u)}, ++ {3410, S_028800_BACKFACE_ENABLE(~0u)}, ++ {3577, S_028800_STENCILFUNC(~0u), 8, 88}, ++ {3708, S_028800_STENCILFAIL(~0u), 8, 96}, ++ {3720, S_028800_STENCILZPASS(~0u)}, ++ {3733, S_028800_STENCILZFAIL(~0u)}, ++ {3746, S_028800_STENCILFUNC_BF(~0u)}, ++ {3761, S_028800_STENCILFAIL_BF(~0u)}, ++ {3776, S_028800_STENCILZPASS_BF(~0u)}, ++ {3792, S_028800_STENCILZFAIL_BF(~0u)}, ++ /* 119 */ ++ {3808, S_028808_DEGAMMA_ENABLE(~0u)}, ++ {1334, S_028808_MODE(~0u), 6, 104}, ++ {3913, S_028808_ROP3(~0u)}, ++ /* 122 */ ++ {3918, S_028810_UCP_ENA_0(~0u)}, ++ {3928, S_028810_UCP_ENA_1(~0u)}, ++ {3938, S_028810_UCP_ENA_2(~0u)}, ++ {3948, S_028810_UCP_ENA_3(~0u)}, ++ {3958, S_028810_UCP_ENA_4(~0u)}, ++ {3968, S_028810_UCP_ENA_5(~0u)}, ++ {3978, S_028810_PS_UCP_Y_SCALE_NEG(~0u)}, ++ {3997, S_028810_PS_UCP_MODE(~0u)}, ++ {4009, S_028810_CLIP_DISABLE(~0u)}, ++ {4022, S_028810_UCP_CULL_ONLY_ENA(~0u)}, ++ {4040, S_028810_BOUNDARY_EDGE_FLAG_ENA(~0u)}, ++ {4063, S_028810_DX_CLIP_SPACE_DEF(~0u)}, ++ {4081, S_028810_DIS_CLIP_ERR_DETECT(~0u)}, ++ {4101, S_028810_VTX_KILL_OR(~0u)}, ++ {4113, S_028810_DX_RASTERIZATION_KILL(~0u)}, ++ {4135, S_028810_DX_LINEAR_ATTR_CLIP_ENA(~0u)}, ++ {4159, S_028810_VTE_VPORT_PROVOKE_DISABLE(~0u)}, ++ {4185, S_028810_ZCLIP_NEAR_DISABLE(~0u)}, ++ {4204, S_028810_ZCLIP_FAR_DISABLE(~0u)}, ++ /* 141 */ ++ {2408, S_028040_FORMAT(~0u), 4, 110}, ++ {930, S_028040_NUM_SAMPLES(~0u)}, ++ {2499, S_028040_ARRAY_MODE(~0u)}, ++ {4253, S_028040_READ_SIZE(~0u)}, ++ {4263, S_028040_TILE_SURFACE_ENABLE(~0u)}, ++ {4283, S_028040_ZRANGE_PRECISION(~0u)}, ++ {2928, S_028040_TILE_SPLIT(~0u)}, ++ {2939, S_028040_NUM_BANKS(~0u)}, ++ {2949, S_028040_BANK_WIDTH(~0u)}, ++ {2960, S_028040_BANK_HEIGHT(~0u)}, ++ {2972, S_028040_MACRO_TILE_ASPECT(~0u)}, ++ /* 152 */ ++ {2408, S_028044_FORMAT(~0u), 2, 114}, ++ {2928, S_028044_TILE_SPLIT(~0u)}, ++ /* 154 */ ++ {1841, S_028058_PITCH_TILE_MAX(~0u)}, ++ {4326, S_028058_HEIGHT_TILE_MAX(~0u)}, ++ /* 156 */ ++ {1856, S_02805C_SLICE_TILE_MAX(~0u)}, ++ /* 157 */ ++ {4342, S_028430_STENCILREF(~0u)}, ++ {4353, S_028430_STENCILMASK(~0u)}, ++ {4365, S_028430_STENCILWRITEMASK(~0u)}, ++ /* 160 */ ++ {4382, S_028434_STENCILREF_BF(~0u)}, ++ {4396, S_028434_STENCILMASK_BF(~0u)}, ++ {4411, S_028434_STENCILWRITEMASK_BF(~0u)}, ++ /* 163 */ ++ {4859, S_028780_COLOR_SRCBLEND(~0u), 21, 116}, ++ {4964, S_028780_COLOR_COMB_FCN(~0u), 5, 137}, ++ {4979, S_028780_COLOR_DESTBLEND(~0u)}, ++ {4995, S_028780_OPACITY_WEIGHT(~0u)}, ++ {5010, S_028780_ALPHA_SRCBLEND(~0u)}, ++ {5025, S_028780_ALPHA_COMB_FCN(~0u)}, ++ {5040, S_028780_ALPHA_DESTBLEND(~0u)}, ++ {5056, S_028780_SEPARATE_ALPHA_BLEND(~0u)}, ++ {5077, S_028780_BLEND_CONTROL_ENABLE(~0u)}, ++ /* 172 */ ++ {5098, S_028814_CULL_FRONT(~0u)}, ++ {5109, S_028814_CULL_BACK(~0u)}, ++ {5119, S_028814_FACE(~0u)}, ++ {5124, S_028814_POLY_MODE(~0u)}, ++ {5134, S_028814_POLYMODE_FRONT_PTYPE(~0u)}, ++ {5155, S_028814_POLYMODE_BACK_PTYPE(~0u)}, ++ {5175, S_028814_POLY_OFFSET_FRONT_ENABLE(~0u)}, ++ {5200, S_028814_POLY_OFFSET_BACK_ENABLE(~0u)}, ++ {5224, S_028814_POLY_OFFSET_PARA_ENABLE(~0u)}, ++ {5248, S_028814_VTX_WINDOW_OFFSET_ENABLE(~0u)}, ++ {5273, S_028814_PROVOKING_VTX_LAST(~0u)}, ++ {5292, S_028814_PERSP_CORR_DIS(~0u)}, ++ {5307, S_028814_MULTI_PRIM_IB_ENA(~0u)}, ++ /* 185 */ ++ {5325, S_028ABC_HTILE_WIDTH(~0u)}, ++ {5337, S_028ABC_HTILE_HEIGHT(~0u)}, ++ {5350, S_028ABC_LINEAR(~0u)}, ++ {5357, S_028ABC_FULL_CACHE(~0u)}, ++ {5368, S_028ABC_HTILE_USES_PRELOAD_WIN(~0u)}, ++ {5391, S_028ABC_PRELOAD(~0u)}, ++ {5399, S_028ABC_PREFETCH_WIDTH(~0u)}, ++ {5414, S_028ABC_PREFETCH_HEIGHT(~0u)}, ++ /* 193 */ ++ {5430, S_02880C_Z_EXPORT_ENABLE(~0u)}, ++ {5446, S_02880C_STENCIL_EXPORT_ENABLE(~0u)}, ++ {5518, S_02880C_Z_ORDER(~0u), 4, 142}, ++ {5526, S_02880C_KILL_ENABLE(~0u)}, ++ {5538, S_02880C_MASK_EXPORT_ENABLE(~0u)}, ++ {5557, S_02880C_DUAL_EXPORT_ENABLE(~0u)}, ++ {5576, S_02880C_EXEC_ON_HIER_FAIL(~0u)}, ++ {5594, S_02880C_EXEC_ON_NOOP(~0u)}, ++ {5653, S_02880C_DB_SOURCE_FORMAT(~0u), 3, 146}, ++ {5670, S_02880C_ALPHA_TO_MASK_DISABLE(~0u)}, ++ {5692, S_02880C_DEPTH_BEFORE_SHADER(~0u)}, ++ {5782, S_02880C_CONSERVATIVE_Z_EXPORT(~0u), 4, 149}, ++ /* 205 */ ++ {2965, S_028A00_HEIGHT(~0u)}, ++ {1176, S_028A00_WIDTH(~0u)}, ++ /* 207 */ ++ {5804, S_028A0C_LINE_PATTERN(~0u)}, ++ {5817, S_028A0C_REPEAT_COUNT(~0u)}, ++ {5830, S_028A0C_PATTERN_BIT_ORDER(~0u)}, ++ {5848, S_028A0C_AUTO_RESET_CNTL(~0u)}, ++ /* 211 */ ++ {1334, S_028A40_MODE(~0u), 6, 153}, ++ {5937, S_028A40_ES_PASSTHRU(~0u)}, ++ {5994, S_028A40_CUT_MODE(~0u), 4, 159}, ++ {6003, S_028A40_COMPUTE_MODE(~0u)}, ++ {6016, S_028A40_PARTIAL_THD_AT_EOI(~0u)}, ++ /* 216 */ ++ {6103, S_028A6C_OUTPRIM_TYPE(~0u), 3, 163}, ++ /* 217 */ ++ {6116, S_008040_WAIT_CP_DMA_IDLE(~0u)}, ++ {6133, S_008040_WAIT_CMDFIFO(~0u)}, ++ {6146, S_008040_WAIT_2D_IDLE(~0u)}, ++ {6159, S_008040_WAIT_3D_IDLE(~0u)}, ++ {6172, S_008040_WAIT_2D_IDLECLEAN(~0u)}, ++ {6190, S_008040_WAIT_3D_IDLECLEAN(~0u)}, ++ {6208, S_008040_WAIT_EXTERN_SIG(~0u)}, ++ {6224, S_008040_CMDFIFO_ENTRIES(~0u)}, ++ /* 225 */ ++ {6240, S_0286CC_NUM_INTERP(~0u)}, ++ {6251, S_0286CC_POSITION_ENA(~0u)}, ++ {6264, S_0286CC_POSITION_CENTROID(~0u)}, ++ {6282, S_0286CC_POSITION_ADDR(~0u)}, ++ {6296, S_0286CC_PARAM_GEN(~0u)}, ++ {6306, S_0286CC_PERSP_GRADIENT_ENA(~0u)}, ++ {6325, S_0286CC_LINEAR_GRADIENT_ENA(~0u)}, ++ {6345, S_0286CC_POSITION_SAMPLE(~0u)}, ++ /* 233 */ ++ {6361, S_0286D0_FRONT_FACE_ENA(~0u)}, ++ {6376, S_0286D0_FRONT_FACE_CHAN(~0u)}, ++ {6392, S_0286D0_FRONT_FACE_ALL_BITS(~0u)}, ++ {6412, S_0286D0_FRONT_FACE_ADDR(~0u)}, ++ {6428, S_0286D0_FOG_ADDR(~0u)}, ++ {6437, S_0286D0_FIXED_PT_POSITION_ENA(~0u)}, ++ {6459, S_0286D0_FIXED_PT_POSITION_ADDR(~0u)}, ++ /* 240 */ ++ {6482, S_0286C4_VS_PER_COMPONENT(~0u)}, ++ {6499, S_0286C4_VS_EXPORT_COUNT(~0u)}, ++ {6515, S_0286C4_VS_EXPORTS_FOG(~0u)}, ++ {6530, S_0286C4_VS_OUT_FOG_VEC_ADDR(~0u)}, ++ /* 244 */ ++ {6550, S_0286E0_PERSP_CENTER_ENA(~0u)}, ++ {6567, S_0286E0_PERSP_CENTROID_ENA(~0u)}, ++ {6586, S_0286E0_PERSP_SAMPLE_ENA(~0u)}, ++ {6603, S_0286E0_PERSP_PULL_MODEL_ENA(~0u)}, ++ {6624, S_0286E0_LINEAR_CENTER_ENA(~0u)}, ++ {6642, S_0286E0_LINEAR_CENTROID_ENA(~0u)}, ++ {6662, S_0286E0_LINEAR_SAMPLE_ENA(~0u)}, ++ /* 251 */ ++ {6680, S_028250_TL_X(~0u)}, ++ {6685, S_028250_TL_Y(~0u)}, ++ {6690, S_028250_WINDOW_OFFSET_DISABLE(~0u)}, ++ /* 254 */ ++ {6712, S_028254_BR_X(~0u)}, ++ {6717, S_028254_BR_Y(~0u)}, ++ /* 256 */ ++ {6680, S_028240_TL_X(~0u)}, ++ {6685, S_028240_TL_Y(~0u)}, ++ {6690, S_028240_WINDOW_OFFSET_DISABLE(~0u)}, ++ /* 259 */ ++ {6712, S_028244_BR_X(~0u)}, ++ {6717, S_028244_BR_Y(~0u)}, ++ /* 261 */ ++ {6680, S_028030_TL_X(~0u)}, ++ {6685, S_028030_TL_Y(~0u)}, ++ /* 263 */ ++ {6712, S_028034_BR_X(~0u)}, ++ {6717, S_028034_BR_Y(~0u)}, ++ /* 265 */ ++ {6680, S_028204_TL_X(~0u)}, ++ {6685, S_028204_TL_Y(~0u)}, ++ {6690, S_028204_WINDOW_OFFSET_DISABLE(~0u)}, ++ /* 268 */ ++ {6712, S_028208_BR_X(~0u)}, ++ {6717, S_028208_BR_Y(~0u)}, ++ /* 270 */ ++ {6722, S_0287F0_SOURCE_SELECT(~0u)}, ++ {6736, S_0287F0_MAJOR_MODE(~0u)}, ++ {5927, S_0287F0_SPRITE_EN(~0u)}, ++ {6747, S_0287F0_NOT_EOP(~0u)}, ++ {6755, S_0287F0_USE_OPAQUE(~0u)}, ++ /* 275 */ ++ {6911, S_030000_DIM(~0u), 8, 166}, ++ {2906, S_030000_NON_DISP_TILING_ORDER(~0u)}, ++ {6915, S_030000_PITCH(~0u)}, ++ {6921, S_030000_TEX_WIDTH(~0u)}, ++ /* 279 */ ++ {6931, S_030004_TEX_HEIGHT(~0u)}, ++ {6942, S_030004_TEX_DEPTH(~0u)}, ++ {2499, S_030004_ARRAY_MODE(~0u)}, ++ /* 282 */ ++ {6952, S_030008_BASE_ADDRESS(~0u)}, ++ /* 283 */ ++ {6965, S_03000C_MIP_ADDRESS(~0u)}, ++ /* 284 */ ++ {7054, S_030010_FORMAT_COMP_X(~0u), 3, 174}, ++ {7068, S_030010_FORMAT_COMP_Y(~0u)}, ++ {7082, S_030010_FORMAT_COMP_Z(~0u)}, ++ {7096, S_030010_FORMAT_COMP_W(~0u)}, ++ {7168, S_030010_NUM_FORMAT_ALL(~0u), 3, 177}, ++ {7230, S_030010_SRF_MODE_ALL(~0u), 2, 180}, ++ {7243, S_030010_FORCE_DEGAMMA(~0u)}, ++ {7257, S_030010_ENDIAN_SWAP(~0u)}, ++ {7269, S_030010_LOG2_NUM_FRAGMENTS(~0u)}, ++ {7342, S_030010_DST_SEL_X(~0u), 6, 182}, ++ {7352, S_030010_DST_SEL_Y(~0u)}, ++ {7362, S_030010_DST_SEL_Z(~0u)}, ++ {7372, S_030010_DST_SEL_W(~0u)}, ++ {7382, S_030010_BASE_LEVEL(~0u)}, ++ /* 298 */ ++ {7393, S_030014_LAST_LEVEL(~0u)}, ++ {7404, S_030014_BASE_ARRAY(~0u)}, ++ {7415, S_030014_LAST_ARRAY(~0u)}, ++ /* 301 */ ++ {7426, S_030018_MAX_ANISO_RATIO(~0u)}, ++ {2990, S_030018_FMASK_BANK_HEIGHT(~0u)}, ++ {7442, S_030018_PERF_MODULATION(~0u)}, ++ {7458, S_030018_INTERLACED(~0u)}, ++ {2928, S_030018_TILE_SPLIT(~0u)}, ++ /* 306 */ ++ {7469, S_03001C_DATA_FORMAT(~0u)}, ++ {2972, S_03001C_MACRO_TILE_ASPECT(~0u)}, ++ {2949, S_03001C_BANK_WIDTH(~0u)}, ++ {2960, S_03001C_BANK_HEIGHT(~0u)}, ++ {7481, S_03001C_DEPTH_SAMPLE_ORDER(~0u)}, ++ {2939, S_03001C_NUM_BANKS(~0u)}, ++ {170, S_03001C_TYPE(~0u), 4, 188}, ++ /* 313 */ ++ {7602, S_030008_BASE_ADDRESS_HI(~0u)}, ++ {7618, S_030008_STRIDE(~0u)}, ++ {7625, S_030008_CLAMP_X(~0u)}, ++ {7469, S_030008_DATA_FORMAT(~0u)}, ++ {7168, S_030008_NUM_FORMAT_ALL(~0u), 3, 177}, ++ {7633, S_030008_FORMAT_COMP_ALL(~0u)}, ++ {7230, S_030008_SRF_MODE_ALL(~0u)}, ++ {7257, S_030008_ENDIAN_SWAP(~0u)}, ++ /* 321 */ ++ {7649, S_03000C_UNCACHED(~0u)}, ++ {7342, S_03000C_DST_SEL_X(~0u), 6, 182}, ++ {7352, S_03000C_DST_SEL_Y(~0u)}, ++ {7362, S_03000C_DST_SEL_Z(~0u)}, ++ {7372, S_03000C_DST_SEL_W(~0u)}, ++ /* 326 */ ++ {7625, S_03C000_CLAMP_X(~0u), 8, 192}, ++ {7840, S_03C000_CLAMP_Y(~0u)}, ++ {7848, S_03C000_CLAMP_Z(~0u)}, ++ {7905, S_03C000_XY_MAG_FILTER(~0u), 2, 200}, ++ {7919, S_03C000_XY_MIN_FILTER(~0u)}, ++ {7999, S_03C000_Z_FILTER(~0u), 3, 202}, ++ {8008, S_03C000_MIP_FILTER(~0u)}, ++ {7426, S_03C000_MAX_ANISO_RATIO(~0u)}, ++ {8146, S_03C000_BORDER_COLOR_TYPE(~0u), 4, 205}, ++ {8396, S_03C000_DEPTH_COMPARE_FUNCTION(~0u), 8, 209}, ++ {8492, S_03C000_CHROMA_KEY(~0u), 3, 217}, ++ /* 337 */ ++ {8503, S_03C004_MIN_LOD(~0u)}, ++ {8511, S_03C004_MAX_LOD(~0u)}, ++ {8519, S_03C004_PERF_MIP(~0u)}, ++ {8528, S_03C004_PERF_Z(~0u)}, ++ /* 341 */ ++ {8535, S_03C008_LOD_BIAS(~0u)}, ++ {8544, S_03C008_LOD_BIAS_SEC(~0u)}, ++ {8557, S_03C008_MC_COORD_TRUNCATE(~0u)}, ++ {7243, S_03C008_FORCE_DEGAMMA(~0u)}, ++ {8575, S_03C008_ANISO_BIAS(~0u)}, ++ {8586, S_03C008_TRUNCATE_COORD(~0u)}, ++ {8601, S_03C008_DISABLE_CUBE_WRAP(~0u)}, ++ {170, S_03C008_TYPE(~0u)}, ++ /* 349 */ ++ {6106, S_008958_PRIM_TYPE(~0u), 29, 220}, ++ /* 350 */ ++ {9135, S_02881C_CLIP_DIST_ENA_0(~0u)}, ++ {9151, S_02881C_CLIP_DIST_ENA_1(~0u)}, ++ {9167, S_02881C_CLIP_DIST_ENA_2(~0u)}, ++ {9183, S_02881C_CLIP_DIST_ENA_3(~0u)}, ++ {9199, S_02881C_CLIP_DIST_ENA_4(~0u)}, ++ {9215, S_02881C_CLIP_DIST_ENA_5(~0u)}, ++ {9231, S_02881C_CLIP_DIST_ENA_6(~0u)}, ++ {9247, S_02881C_CLIP_DIST_ENA_7(~0u)}, ++ {9263, S_02881C_CULL_DIST_ENA_0(~0u)}, ++ {9279, S_02881C_CULL_DIST_ENA_1(~0u)}, ++ {9295, S_02881C_CULL_DIST_ENA_2(~0u)}, ++ {9311, S_02881C_CULL_DIST_ENA_3(~0u)}, ++ {9327, S_02881C_CULL_DIST_ENA_4(~0u)}, ++ {9343, S_02881C_CULL_DIST_ENA_5(~0u)}, ++ {9359, S_02881C_CULL_DIST_ENA_6(~0u)}, ++ {9375, S_02881C_CULL_DIST_ENA_7(~0u)}, ++ {9391, S_02881C_USE_VTX_POINT_SIZE(~0u)}, ++ {9410, S_02881C_USE_VTX_EDGE_FLAG(~0u)}, ++ {9428, S_02881C_USE_VTX_RENDER_TARGET_INDX(~0u)}, ++ {9455, S_02881C_USE_VTX_VIEWPORT_INDX(~0u)}, ++ {9477, S_02881C_USE_VTX_KILL_FLAG(~0u)}, ++ {9495, S_02881C_VS_OUT_MISC_VEC_ENA(~0u)}, ++ {9515, S_02881C_VS_OUT_CCDIST0_VEC_ENA(~0u)}, ++ {9538, S_02881C_VS_OUT_CCDIST1_VEC_ENA(~0u)}, ++ /* 374 */ ++ {9561, S_028860_NUM_GPRS(~0u)}, ++ {9570, S_028860_STACK_SIZE(~0u)}, ++ {9581, S_028860_DX10_CLAMP(~0u)}, ++ {9592, S_028860_UNCACHED_FIRST_INST(~0u)}, ++ /* 378 */ ++ {9561, S_028878_NUM_GPRS(~0u)}, ++ {9570, S_028878_STACK_SIZE(~0u)}, ++ {9581, S_028878_DX10_CLAMP(~0u)}, ++ {9592, S_028878_UNCACHED_FIRST_INST(~0u)}, ++ /* 382 */ ++ {9561, S_028890_NUM_GPRS(~0u)}, ++ {9570, S_028890_STACK_SIZE(~0u)}, ++ {9581, S_028890_DX10_CLAMP(~0u)}, ++ {9592, S_028890_UNCACHED_FIRST_INST(~0u)}, ++ /* 386 */ ++ {9686, S_028864_SINGLE_ROUND(~0u), 4, 249}, ++ {9699, S_028864_DOUBLE_ROUND(~0u)}, ++ {9712, S_028864_ALLOW_SINGLE_DENORM_IN(~0u)}, ++ {9735, S_028864_ALLOW_SINGLE_DENORM_OUT(~0u)}, ++ {9759, S_028864_ALLOW_DOUBLE_DENORM_IN(~0u)}, ++ {9782, S_028864_ALLOW_DOUBLE_DENORM_OUT(~0u)}, ++ /* 392 */ ++ {9561, S_028844_NUM_GPRS(~0u)}, ++ {9570, S_028844_STACK_SIZE(~0u)}, ++ {9581, S_028844_DX10_CLAMP(~0u)}, ++ {9806, S_028844_PRIME_CACHE_ON_DRAW(~0u)}, ++ {9592, S_028844_UNCACHED_FIRST_INST(~0u)}, ++ {9826, S_028844_CLAMP_CONSTS(~0u)}, ++ /* 398 */ ++ {9686, S_028848_SINGLE_ROUND(~0u)}, ++ {9699, S_028848_DOUBLE_ROUND(~0u)}, ++ {9712, S_028848_ALLOW_SINGLE_DENORM_IN(~0u)}, ++ {9735, S_028848_ALLOW_SINGLE_DENORM_OUT(~0u)}, ++ {9759, S_028848_ALLOW_DOUBLE_DENORM_IN(~0u)}, ++ {9782, S_028848_ALLOW_DOUBLE_DENORM_OUT(~0u)}, ++ /* 404 */ ++ {9561, S_0288BC_NUM_GPRS(~0u)}, ++ {9570, S_0288BC_STACK_SIZE(~0u)}, ++ {9581, S_0288BC_DX10_CLAMP(~0u)}, ++ {9806, S_0288BC_PRIME_CACHE_ON_DRAW(~0u)}, ++ {9592, S_0288BC_UNCACHED_FIRST_INST(~0u)}, ++ /* 409 */ ++ {9561, S_0288D4_NUM_GPRS(~0u)}, ++ {9570, S_0288D4_STACK_SIZE(~0u)}, ++ {9581, S_0288D4_DX10_CLAMP(~0u)}, ++ {9806, S_0288D4_PRIME_CACHE_ON_DRAW(~0u)}, ++ {9592, S_0288D4_UNCACHED_FIRST_INST(~0u)}, ++ /* 414 */ ++ {9839, S_028644_SEMANTIC(~0u)}, ++ {9848, S_028644_DEFAULT_VAL(~0u)}, ++ {9860, S_028644_FLAT_SHADE(~0u)}, ++ {9871, S_028644_SEL_CENTROID(~0u)}, ++ {9884, S_028644_SEL_LINEAR(~0u)}, ++ {9895, S_028644_CYL_WRAP(~0u)}, ++ {9904, S_028644_PT_SPRITE_TEX(~0u)}, ++ {9918, S_028644_SEL_SAMPLE(~0u)}, ++ /* 422 */ ++ {9929, S_0286D4_FLAT_SHADE_ENA(~0u)}, ++ {9944, S_0286D4_PNT_SPRITE_ENA(~0u)}, ++ {9959, S_0286D4_PNT_SPRITE_OVRD_X(~0u)}, ++ {9977, S_0286D4_PNT_SPRITE_OVRD_Y(~0u)}, ++ {9995, S_0286D4_PNT_SPRITE_OVRD_Z(~0u)}, ++ {10013, S_0286D4_PNT_SPRITE_OVRD_W(~0u)}, ++ {10031, S_0286D4_PNT_SPRITE_TOP_1(~0u)}, ++ /* 429 */ ++ {10048, S_028000_DEPTH_CLEAR_ENABLE(~0u)}, ++ {10067, S_028000_STENCIL_CLEAR_ENABLE(~0u)}, ++ {10088, S_028000_DEPTH_COPY_ENABLE(~0u)}, ++ {10106, S_028000_STENCIL_COPY_ENABLE(~0u)}, ++ {10126, S_028000_RESUMMARIZE_ENABLE(~0u)}, ++ {10145, S_028000_STENCIL_COMPRESS_DISABLE(~0u)}, ++ {10170, S_028000_DEPTH_COMPRESS_DISABLE(~0u)}, ++ {10193, S_028000_COPY_CENTROID(~0u)}, ++ {10207, S_028000_COPY_SAMPLE(~0u)}, ++ {10219, S_028000_COLOR_DISABLE(~0u)}, ++ /* 439 */ ++ {10233, S_028004_ZPASS_INCREMENT_DISABLE(~0u)}, ++ {10257, S_028004_PERFECT_ZPASS_COUNTS(~0u)}, ++ {10278, S_028004_SAMPLE_RATE(~0u)}, ++ /* 442 */ ++ {10290, S_028008_SLICE_START(~0u)}, ++ {10339, S_028008_SLICE_MAX(~0u), 3, 253}, ++ /* 444 */ ++ {10349, S_02800C_FORCE_HIZ_ENABLE(~0u)}, ++ {10366, S_02800C_FORCE_HIS_ENABLE0(~0u)}, ++ {10384, S_02800C_FORCE_HIS_ENABLE1(~0u)}, ++ {10402, S_02800C_FORCE_SHADER_Z_ORDER(~0u)}, ++ {10423, S_02800C_FAST_Z_DISABLE(~0u)}, ++ {10438, S_02800C_FAST_STENCIL_DISABLE(~0u)}, ++ {10459, S_02800C_NOOP_CULL_DISABLE(~0u)}, ++ {10477, S_02800C_FORCE_COLOR_KILL(~0u)}, ++ {10494, S_02800C_FORCE_Z_READ(~0u)}, ++ {10507, S_02800C_FORCE_STENCIL_READ(~0u)}, ++ {10526, S_02800C_FORCE_FULL_Z_RANGE(~0u)}, ++ {10545, S_02800C_FORCE_QC_SMASK_CONFLICT(~0u)}, ++ {10569, S_02800C_DISABLE_VIEWPORT_CLAMP(~0u)}, ++ {10592, S_02800C_IGNORE_SC_ZRANGE(~0u)}, ++ {10609, S_02800C_DISABLE_PIXEL_RATE_TILES(~0u)}, ++ /* 459 */ ++ {10634, S_028350_MULTIPASS(~0u)}, ++ /* 460 */ ++ {10644, S_028354_SURFACE_SYNC_MASK(~0u)}, ++ /* 461 */ ++ {10662, S_0286D8_PROVIDE_Z_TO_SPI(~0u)}, ++ /* 462 */ ++ {10679, S_0286E8_TID_IN_GROUP_ENA(~0u)}, ++ {10696, S_0286E8_TGID_ENA(~0u)}, ++ {10705, S_0286E8_DISABLE_INDEX_PACK(~0u)}, ++ /* 465 */ ++ {10724, S_028818_VPORT_X_SCALE_ENA(~0u)}, ++ {10742, S_028818_VPORT_X_OFFSET_ENA(~0u)}, ++ {10761, S_028818_VPORT_Y_SCALE_ENA(~0u)}, ++ {10779, S_028818_VPORT_Y_OFFSET_ENA(~0u)}, ++ {10798, S_028818_VPORT_Z_SCALE_ENA(~0u)}, ++ {10816, S_028818_VPORT_Z_OFFSET_ENA(~0u)}, ++ {10835, S_028818_VTX_XY_FMT(~0u)}, ++ {10846, S_028818_VTX_Z_FMT(~0u)}, ++ {10856, S_028818_VTX_W0_FMT(~0u)}, ++ /* 474 */ ++ {1422, S_028838_PS_GPRS(~0u)}, ++ {1434, S_028838_VS_GPRS(~0u)}, ++ {1467, S_028838_GS_GPRS(~0u)}, ++ {1479, S_028838_ES_GPRS(~0u)}, ++ {1491, S_028838_HS_GPRS(~0u)}, ++ {1503, S_028838_LS_GPRS(~0u)}, ++ /* 480 */ ++ {10867, S_02884C_EXPORT_COLORS(~0u)}, ++ {10881, S_02884C_EXPORT_Z(~0u)}, ++ /* 482 */ ++ {10890, S_028A04_MIN_SIZE(~0u)}, ++ {10899, S_028A04_MAX_SIZE(~0u)}, ++ /* 484 */ ++ {1176, S_028A08_WIDTH(~0u)}, ++ /* 485 */ ++ {10908, S_028A48_MSAA_ENABLE(~0u)}, ++ {10920, S_028A48_VPORT_SCISSOR_ENABLE(~0u)}, ++ {10941, S_028A48_LINE_STIPPLE_ENABLE(~0u)}, ++ /* 488 */ ++ {10961, S_028A84_PRIMITIVEID_EN(~0u)}, ++ /* 489 */ ++ {10976, S_028A94_RESET_EN(~0u)}, ++ /* 490 */ ++ {10985, S_028AC8_MAX_X(~0u)}, ++ {10991, S_028AC8_MAX_Y(~0u)}, ++ /* 492 */ ++ {10997, S_028B38_MAX_VERT_OUT(~0u)}, ++ /* 493 */ ++ {11047, S_028B54_LS_EN(~0u), 3, 256}, ++ {11053, S_028B54_HS_EN(~0u)}, ++ {11098, S_028B54_ES_EN(~0u), 3, 259}, ++ {11104, S_028B54_GS_EN(~0u)}, ++ {11157, S_028B54_VS_EN(~0u), 3, 262}, ++ /* 498 */ ++ {11163, S_028B58_NUM_PATCHES(~0u)}, ++ {11175, S_028B58_HS_NUM_INPUT_CP(~0u)}, ++ {11191, S_028B58_HS_NUM_OUTPUT_CP(~0u)}, ++ /* 501 */ ++ {1760, S_028B5C_SIZE(~0u)}, ++ {11208, S_028B5C_PATCH_CP_SIZE(~0u)}, ++ /* 503 */ ++ {1760, S_028B60_SIZE(~0u)}, ++ {11208, S_028B60_PATCH_CP_SIZE(~0u)}, ++ /* 505 */ ++ {11222, S_028B64_HS_TOTAL_OUTPUT(~0u)}, ++ {11238, S_028B64_LS_HS_TOTAL_OUTPUT(~0u)}, ++ /* 507 */ ++ {1760, S_028B68_SIZE(~0u)}, ++ {7618, S_028B68_STRIDE(~0u)}, ++ /* 509 */ ++ {11257, S_028B70_ALPHA_TO_MASK_ENABLE(~0u)}, ++ {11278, S_028B70_ALPHA_TO_MASK_OFFSET0(~0u)}, ++ {11300, S_028B70_ALPHA_TO_MASK_OFFSET1(~0u)}, ++ {11322, S_028B70_ALPHA_TO_MASK_OFFSET2(~0u)}, ++ {11344, S_028B70_ALPHA_TO_MASK_OFFSET3(~0u)}, ++ {11366, S_028B70_OFFSET_ROUND(~0u)}, ++ /* 515 */ ++ {11379, S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(~0u)}, ++ {11407, S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(~0u)}, ++ /* 517 */ ++ {11435, S_028B80_SCALE(~0u)}, ++ /* 518 */ ++ {11441, S_028B84_OFFSET(~0u)}, ++ /* 519 */ ++ {11435, S_028B88_SCALE(~0u)}, ++ /* 520 */ ++ {11441, S_028B8C_OFFSET(~0u)}, ++ /* 521 */ ++ {1342, S_028B90_ENABLE(~0u)}, ++ {609, S_028B90_CNT(~0u)}, ++ /* 523 */ ++ {1164, S_028C00_EXPAND_LINE_WIDTH(~0u)}, ++ {1182, S_028C00_LAST_PIXEL(~0u)}, ++ /* 525 */ ++ {1240, S_028C04_MSAA_NUM_SAMPLES(~0u)}, ++ {1257, S_028C04_AA_MASK_CENTROID_DTMN(~0u)}, ++ {1279, S_028C04_MAX_SAMPLE_DIST(~0u)}, ++ /* 528 */ ++ {11448, S_028C08_PIX_CENTER_HALF(~0u)}, ++ {11531, S_028C08_QUANT_MODE(~0u), 8, 265}, ++ /* 530 */ ++ {10290, S_028C6C_SLICE_START(~0u)}, ++ {10339, S_028C6C_SLICE_MAX(~0u)}, ++ /* 532 */ ++ {1847, S_028C80_TILE_MAX(~0u)}, ++ /* 533 */ ++ {1847, S_028C88_TILE_MAX(~0u)}, ++ /* 534 */ ++ {11542, S_0085F0_DEST_BASE_0_ENA(~0u)}, ++ {11558, S_0085F0_DEST_BASE_1_ENA(~0u)}, ++ {11574, S_0085F0_SO0_DEST_BASE_ENA(~0u)}, ++ {11592, S_0085F0_SO1_DEST_BASE_ENA(~0u)}, ++ {11610, S_0085F0_SO2_DEST_BASE_ENA(~0u)}, ++ {11628, S_0085F0_SO3_DEST_BASE_ENA(~0u)}, ++ {11646, S_0085F0_CB0_DEST_BASE_ENA(~0u)}, ++ {11664, S_0085F0_CB1_DEST_BASE_ENA(~0u)}, ++ {11682, S_0085F0_CB2_DEST_BASE_ENA(~0u)}, ++ {11700, S_0085F0_CB3_DEST_BASE_ENA(~0u)}, ++ {11718, S_0085F0_CB4_DEST_BASE_ENA(~0u)}, ++ {11736, S_0085F0_CB5_DEST_BASE_ENA(~0u)}, ++ {11754, S_0085F0_CB6_DEST_BASE_ENA(~0u)}, ++ {11772, S_0085F0_CB7_DEST_BASE_ENA(~0u)}, ++ {11790, S_0085F0_DB_DEST_BASE_ENA(~0u)}, ++ {11807, S_0085F0_CB8_DEST_BASE_ENA(~0u)}, ++ {11825, S_0085F0_CB9_DEST_BASE_ENA(~0u)}, ++ {11843, S_0085F0_CB10_DEST_BASE_ENA(~0u)}, ++ {11862, S_0085F0_CB11_DEST_BASE_ENA(~0u)}, ++ {11881, S_0085F0_TC_ACTION_ENA(~0u)}, ++ {11895, S_0085F0_VC_ACTION_ENA(~0u)}, ++ {11909, S_0085F0_CB_ACTION_ENA(~0u)}, ++ {11923, S_0085F0_DB_ACTION_ENA(~0u)}, ++ {11937, S_0085F0_SH_ACTION_ENA(~0u)}, ++ {11951, S_0085F0_SMX_ACTION_ENA(~0u)}, ++ {11966, S_0085F0_CR0_ACTION_ENA(~0u)}, ++ {11981, S_0085F0_CR1_ACTION_ENA(~0u)}, ++ {11996, S_0085F0_CR2_ACTION_ENA(~0u)}, ++ /* 562 */ ++ {1727, S_0286FC_NUM_PS_LDS(~0u)}, ++ {1738, S_0286FC_NUM_LS_LDS(~0u)}, ++ {883, S_028804_MAX_ANCHOR_SAMPLES(~0u)}, ++ {902, S_028804_PS_ITER_SAMPLES(~0u)}, ++ {918, S_028804_MASK_EXPORT_NUM_SAMPLES(~0u)}, ++ {942, S_028804_ALPHA_TO_MASK_NUM_SAMPLES(~0u)}, ++ {968, S_028804_HIGH_QUALITY_INTERSECTIONS(~0u)}, ++ {995, S_028804_INCOHERENT_EQAA_READS(~0u)}, ++ {1017, S_028804_INTERPOLATE_COMP_Z(~0u)}, ++ {1036, S_028804_INTERPOLATE_SRC_Z(~0u)}, ++ {1054, S_028804_STATIC_ANCHOR_ASSOCIATIONS(~0u)}, ++ {1081, S_028804_ALPHA_TO_MASK_EQAA_DISABLE(~0u)}, ++ {1240, S_028BE0_MSAA_NUM_SAMPLES(~0u)}, ++ {1257, S_028BE0_AA_MASK_CENTROID_DTMN(~0u)}, ++ {1279, S_028BE0_MAX_SAMPLE_DIST(~0u)}, ++ {1295, S_028BE0_MSAA_EXPOSED_SAMPLES(~0u)}, ++ {1316, S_028BE0_DETAIL_TO_EXPOSED_MODE(~0u)}, ++ {12011, S_028AA8_PRIMGROUP_SIZE(~0u)}, ++ {12026, S_028AA8_PARTIAL_VS_WAVE_ON(~0u)}, ++ {12045, S_028AA8_SWITCH_ON_EOP(~0u)}, ++}; ++ ++static const struct eg_reg egd_reg_table[] = { ++ {12059, R_0084FC_CP_STRMOUT_CNTL, 1, 0}, ++ {12075, R_028B94_VGT_STRMOUT_CONFIG, 7, 1}, ++ {12094, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 25, 8}, ++ {12120, R_008960_VGT_STRMOUT_BUFFER_FILLED_SIZE_0}, ++ {12153, R_008964_VGT_STRMOUT_BUFFER_FILLED_SIZE_1}, ++ {12186, R_008968_VGT_STRMOUT_BUFFER_FILLED_SIZE_2}, ++ {12219, R_00896C_VGT_STRMOUT_BUFFER_FILLED_SIZE_3}, ++ {12252, R_008C00_SQ_CONFIG, 9, 33}, ++ {12262, R_008C04_SQ_GPR_RESOURCE_MGMT_1, 3, 42}, ++ {12285, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 2, 45}, ++ {12308, R_008C0C_SQ_GPR_RESOURCE_MGMT_3, 2, 47}, ++ {12331, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1}, ++ {12361, R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2}, ++ {12391, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 4, 49}, ++ {12417, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, 2, 53}, ++ {12443, R_008C20_SQ_STACK_RESOURCE_MGMT_1, 2, 55}, ++ {12468, R_008C24_SQ_STACK_RESOURCE_MGMT_2, 2, 57}, ++ {12493, R_008C28_SQ_STACK_RESOURCE_MGMT_3, 2, 59}, ++ {12518, R_008E2C_SQ_LDS_RESOURCE_MGMT, 2, 61}, ++ {12539, R_008C40_SQ_ESGS_RING_BASE}, ++ {12557, R_008C44_SQ_ESGS_RING_SIZE}, ++ {12575, R_008C48_SQ_GSVS_RING_BASE}, ++ {12593, R_008C4C_SQ_GSVS_RING_SIZE}, ++ {12611, R_008CF0_SQ_MS_FIFO_SIZES, 4, 63}, ++ {12628, R_008E20_SQ_STATIC_THREAD_MGMT1}, ++ {12651, R_008E24_SQ_STATIC_THREAD_MGMT2}, ++ {12674, R_008E28_SQ_STATIC_THREAD_MGMT3}, ++ {12697, R_00899C_VGT_COMPUTE_START_X}, ++ {12717, R_0089A0_VGT_COMPUTE_START_Y}, ++ {12737, R_0089A4_VGT_COMPUTE_START_Z}, ++ {12757, R_0089AC_VGT_COMPUTE_THREAD_GROUP_SIZE}, ++ {12787, R_009100_SPI_CONFIG_CNTL}, ++ {12803, R_00913C_SPI_CONFIG_CNTL_1, 1, 67}, ++ {12821, R_028C64_CB_COLOR0_PITCH, 1, 68}, ++ {12837, R_028C68_CB_COLOR0_SLICE, 1, 69}, ++ {12853, R_028C70_CB_COLOR0_INFO, 15, 70}, ++ {12868, R_028C74_CB_COLOR0_ATTRIB, 10, 85}, ++ {12885, R_028C78_CB_COLOR0_DIM, 2, 95}, ++ {12899, R_028410_SX_ALPHA_TEST_CONTROL, 3, 97}, ++ {12921, R_0286EC_SPI_COMPUTE_NUM_THREAD_X}, ++ {12946, R_0286F0_SPI_COMPUTE_NUM_THREAD_Y}, ++ {12971, R_0286F4_SPI_COMPUTE_NUM_THREAD_Z}, ++ {12996, R_028B6C_VGT_TF_PARAM, 6, 100}, ++ {13009, R_028B74_VGT_DISPATCH_INITIATOR}, ++ {13032, R_028800_DB_DEPTH_CONTROL, 13, 106}, ++ {13049, R_028808_CB_COLOR_CONTROL, 3, 119}, ++ {13066, R_028810_PA_CL_CLIP_CNTL, 19, 122}, ++ {13082, R_028040_DB_Z_INFO, 11, 141}, ++ {13092, R_028044_DB_STENCIL_INFO, 2, 152}, ++ {13108, R_028058_DB_DEPTH_SIZE, 2, 154}, ++ {13122, R_02805C_DB_DEPTH_SLICE, 1, 156}, ++ {13137, R_028430_DB_STENCILREFMASK, 3, 157}, ++ {13155, R_028434_DB_STENCILREFMASK_BF, 3, 160}, ++ {13176, R_028780_CB_BLEND0_CONTROL, 9, 163}, ++ {13194, R_028814_PA_SU_SC_MODE_CNTL, 13, 172}, ++ {13213, R_028ABC_DB_HTILE_SURFACE, 8, 185}, ++ {13230, R_02880C_DB_SHADER_CONTROL, 12, 193}, ++ {13248, R_028A00_PA_SU_POINT_SIZE, 2, 205}, ++ {13265, R_028A0C_PA_SC_LINE_STIPPLE, 4, 207}, ++ {13284, R_028A40_VGT_GS_MODE, 5, 211}, ++ {13296, R_028A6C_VGT_GS_OUT_PRIM_TYPE, 1, 216}, ++ {13317, R_008040_WAIT_UNTIL, 8, 217}, ++ {13328, R_0286CC_SPI_PS_IN_CONTROL_0, 8, 225}, ++ {13348, R_0286D0_SPI_PS_IN_CONTROL_1, 7, 233}, ++ {13368, R_0286C4_SPI_VS_OUT_CONFIG, 4, 240}, ++ {13386, R_0286E0_SPI_BARYC_CNTL, 7, 244}, ++ {13401, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 3, 251}, ++ {13426, R_028254_PA_SC_VPORT_SCISSOR_0_BR, 2, 254}, ++ {13451, R_028240_PA_SC_GENERIC_SCISSOR_TL, 3, 256}, ++ {13476, R_028244_PA_SC_GENERIC_SCISSOR_BR, 2, 259}, ++ {13501, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2, 261}, ++ {13525, R_028034_PA_SC_SCREEN_SCISSOR_BR, 2, 263}, ++ {13549, R_028204_PA_SC_WINDOW_SCISSOR_TL, 3, 265}, ++ {13573, R_028208_PA_SC_WINDOW_SCISSOR_BR, 2, 268}, ++ {13597, R_028A78_VGT_DMA_MAX_SIZE}, ++ {13614, R_028A7C_VGT_DMA_INDEX_TYPE}, ++ {13633, R_028A88_VGT_NUM_INSTANCES}, ++ {13651, R_0287E4_VGT_DMA_BASE_HI}, ++ {13667, R_0287E8_VGT_DMA_BASE}, ++ {13680, R_0287F0_VGT_DRAW_INITIATOR, 5, 270}, ++ {13699, R_030000_SQ_TEX_RESOURCE_WORD0_0, 4, 275}, ++ {13723, R_030004_SQ_TEX_RESOURCE_WORD1_0, 3, 279}, ++ {13747, R_030008_SQ_TEX_RESOURCE_WORD2_0, 1, 282}, ++ {13771, R_03000C_SQ_TEX_RESOURCE_WORD3_0, 1, 283}, ++ {13795, R_030010_SQ_TEX_RESOURCE_WORD4_0, 14, 284}, ++ {13819, R_030014_SQ_TEX_RESOURCE_WORD5_0, 3, 298}, ++ {13843, R_030018_SQ_TEX_RESOURCE_WORD6_0, 5, 301}, ++ {13867, R_03001C_SQ_TEX_RESOURCE_WORD7_0, 7, 306}, ++ {13891, R_030008_SQ_VTX_CONSTANT_WORD2_0, 8, 313}, ++ {13915, R_03000C_SQ_VTX_CONSTANT_WORD3_0, 5, 321}, ++ {13939, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX}, ++ {13967, R_00A404_TD_PS_SAMPLER0_BORDER_RED}, ++ {13993, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN}, ++ {14021, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE}, ++ {14048, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA}, ++ {14076, R_00A414_TD_VS_SAMPLER0_BORDER_INDEX}, ++ {14104, R_00A418_TD_VS_SAMPLER0_BORDER_RED}, ++ {14130, R_00A41C_TD_VS_SAMPLER0_BORDER_GREEN}, ++ {14158, R_00A420_TD_VS_SAMPLER0_BORDER_BLUE}, ++ {14185, R_00A424_TD_VS_SAMPLER0_BORDER_ALPHA}, ++ {14213, R_00A428_TD_GS_SAMPLER0_BORDER_INDEX}, ++ {14241, R_00A42C_TD_GS_SAMPLER0_BORDER_RED}, ++ {14267, R_00A430_TD_GS_SAMPLER0_BORDER_GREEN}, ++ {14295, R_00A434_TD_GS_SAMPLER0_BORDER_BLUE}, ++ {14322, R_00A438_TD_GS_SAMPLER0_BORDER_ALPHA}, ++ {14350, R_00A43C_TD_HS_SAMPLER0_BORDER_COLOR_INDEX}, ++ {14384, R_00A440_TD_HS_SAMPLER0_BORDER_COLOR_RED}, ++ {14416, R_00A444_TD_HS_SAMPLER0_BORDER_COLOR_GREEN}, ++ {14450, R_00A448_TD_HS_SAMPLER0_BORDER_COLOR_BLUE}, ++ {14483, R_00A44C_TD_HS_SAMPLER0_BORDER_COLOR_ALPHA}, ++ {14517, R_00A450_TD_LS_SAMPLER0_BORDER_COLOR_INDEX}, ++ {14551, R_00A454_TD_LS_SAMPLER0_BORDER_COLOR_RED}, ++ {14583, R_00A458_TD_LS_SAMPLER0_BORDER_COLOR_GREEN}, ++ {14617, R_00A45C_TD_LS_SAMPLER0_BORDER_COLOR_BLUE}, ++ {14650, R_00A460_TD_LS_SAMPLER0_BORDER_COLOR_ALPHA}, ++ {14684, R_00A464_TD_CS_SAMPLER0_BORDER_INDEX}, ++ {14712, R_00A468_TD_CS_SAMPLER0_BORDER_RED}, ++ {14738, R_00A46C_TD_CS_SAMPLER0_BORDER_GREEN}, ++ {14766, R_00A470_TD_CS_SAMPLER0_BORDER_BLUE}, ++ {14793, R_00A474_TD_CS_SAMPLER0_BORDER_ALPHA}, ++ {14821, R_03C000_SQ_TEX_SAMPLER_WORD0_0, 11, 326}, ++ {14844, R_03C004_SQ_TEX_SAMPLER_WORD1_0, 4, 337}, ++ {14867, R_03C008_SQ_TEX_SAMPLER_WORD2_0, 8, 341}, ++ {14890, R_008958_VGT_PRIMITIVE_TYPE, 1, 349}, ++ {14909, R_02881C_PA_CL_VS_OUT_CNTL, 24, 350}, ++ {14927, R_028860_SQ_PGM_RESOURCES_VS, 4, 374}, ++ {14947, R_028878_SQ_PGM_RESOURCES_GS, 4, 378}, ++ {14967, R_02887C_SQ_PGM_RESOURCES_2_GS}, ++ {14989, R_028890_SQ_PGM_RESOURCES_ES, 4, 382}, ++ {15009, R_028894_SQ_PGM_RESOURCES_2_ES}, ++ {15031, R_028864_SQ_PGM_RESOURCES_2_VS, 6, 386}, ++ {15053, R_028844_SQ_PGM_RESOURCES_PS, 6, 392}, ++ {15073, R_028848_SQ_PGM_RESOURCES_2_PS, 6, 398}, ++ {15095, R_0288BC_SQ_PGM_RESOURCES_HS, 5, 404}, ++ {15115, R_0288C0_SQ_PGM_RESOURCES_2_HS}, ++ {15137, R_0288D4_SQ_PGM_RESOURCES_LS, 5, 409}, ++ {15157, R_0288D8_SQ_PGM_RESOURCES_2_LS}, ++ {15179, R_028644_SPI_PS_INPUT_CNTL_0, 8, 414}, ++ {15199, R_0286D4_SPI_INTERP_CONTROL_0, 7, 422}, ++ {15220, R_008A14_PA_CL_ENHANCE}, ++ {15234, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ}, ++ {15263, R_028000_DB_RENDER_CONTROL, 10, 429}, ++ {15281, R_028004_DB_COUNT_CONTROL, 3, 439}, ++ {15298, R_028008_DB_DEPTH_VIEW, 2, 442}, ++ {15312, R_02800C_DB_RENDER_OVERRIDE, 15, 444}, ++ {15331, R_028010_DB_RENDER_OVERRIDE2}, ++ {15351, R_028014_DB_HTILE_DATA_BASE}, ++ {15370, R_028028_DB_STENCIL_CLEAR}, ++ {15387, R_02802C_DB_DEPTH_CLEAR}, ++ {15402, R_028048_DB_Z_READ_BASE}, ++ {15417, R_02804C_DB_STENCIL_READ_BASE}, ++ {15438, R_028050_DB_Z_WRITE_BASE}, ++ {15454, R_028054_DB_STENCIL_WRITE_BASE}, ++ {15476, R_028140_ALU_CONST_BUFFER_SIZE_PS_0}, ++ {15503, R_028144_ALU_CONST_BUFFER_SIZE_PS_1}, ++ {15530, R_028180_ALU_CONST_BUFFER_SIZE_VS_0}, ++ {15557, R_028184_ALU_CONST_BUFFER_SIZE_VS_1}, ++ {15584, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0}, ++ {15611, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0}, ++ {15638, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0}, ++ {15665, R_028200_PA_SC_WINDOW_OFFSET}, ++ {15685, R_02820C_PA_SC_CLIPRECT_RULE}, ++ {15705, R_028210_PA_SC_CLIPRECT_0_TL}, ++ {15725, R_028214_PA_SC_CLIPRECT_0_BR}, ++ {15745, R_028218_PA_SC_CLIPRECT_1_TL}, ++ {15765, R_02821C_PA_SC_CLIPRECT_1_BR}, ++ {15785, R_028220_PA_SC_CLIPRECT_2_TL}, ++ {15805, R_028224_PA_SC_CLIPRECT_2_BR}, ++ {15825, R_028228_PA_SC_CLIPRECT_3_TL}, ++ {15845, R_02822C_PA_SC_CLIPRECT_3_BR}, ++ {15865, R_028230_PA_SC_EDGERULE}, ++ {15880, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET}, ++ {15909, R_028238_CB_TARGET_MASK}, ++ {15924, R_02823C_CB_SHADER_MASK}, ++ {15939, R_028350_SX_MISC, 1, 459}, ++ {15947, R_028354_SX_SURFACE_SYNC, 1, 460}, ++ {15963, R_028380_SQ_VTX_SEMANTIC_0}, ++ {15981, R_028384_SQ_VTX_SEMANTIC_1}, ++ {15999, R_028388_SQ_VTX_SEMANTIC_2}, ++ {16017, R_02838C_SQ_VTX_SEMANTIC_3}, ++ {16035, R_028390_SQ_VTX_SEMANTIC_4}, ++ {16053, R_028394_SQ_VTX_SEMANTIC_5}, ++ {16071, R_028398_SQ_VTX_SEMANTIC_6}, ++ {16089, R_02839C_SQ_VTX_SEMANTIC_7}, ++ {16107, R_0283A0_SQ_VTX_SEMANTIC_8}, ++ {16125, R_0283A4_SQ_VTX_SEMANTIC_9}, ++ {16143, R_0283A8_SQ_VTX_SEMANTIC_10}, ++ {16162, R_0283AC_SQ_VTX_SEMANTIC_11}, ++ {16181, R_0283B0_SQ_VTX_SEMANTIC_12}, ++ {16200, R_0283B4_SQ_VTX_SEMANTIC_13}, ++ {16219, R_0283B8_SQ_VTX_SEMANTIC_14}, ++ {16238, R_0283BC_SQ_VTX_SEMANTIC_15}, ++ {16257, R_0283C0_SQ_VTX_SEMANTIC_16}, ++ {16276, R_0283C4_SQ_VTX_SEMANTIC_17}, ++ {16295, R_0283C8_SQ_VTX_SEMANTIC_18}, ++ {16314, R_0283CC_SQ_VTX_SEMANTIC_19}, ++ {16333, R_0283D0_SQ_VTX_SEMANTIC_20}, ++ {16352, R_0283D4_SQ_VTX_SEMANTIC_21}, ++ {16371, R_0283D8_SQ_VTX_SEMANTIC_22}, ++ {16390, R_0283DC_SQ_VTX_SEMANTIC_23}, ++ {16409, R_0283E0_SQ_VTX_SEMANTIC_24}, ++ {16428, R_0283E4_SQ_VTX_SEMANTIC_25}, ++ {16447, R_0283E8_SQ_VTX_SEMANTIC_26}, ++ {16466, R_0283EC_SQ_VTX_SEMANTIC_27}, ++ {16485, R_0283F0_SQ_VTX_SEMANTIC_28}, ++ {16504, R_0283F4_SQ_VTX_SEMANTIC_29}, ++ {16523, R_0283F8_SQ_VTX_SEMANTIC_30}, ++ {16542, R_0283FC_SQ_VTX_SEMANTIC_31}, ++ {16561, R_0288F0_SQ_VTX_SEMANTIC_CLEAR}, ++ {16583, R_0282D0_PA_SC_VPORT_ZMIN_0}, ++ {16602, R_0282D4_PA_SC_VPORT_ZMAX_0}, ++ {16621, R_028400_VGT_MAX_VTX_INDX}, ++ {16638, R_028404_VGT_MIN_VTX_INDX}, ++ {16655, R_028408_VGT_INDX_OFFSET}, ++ {16671, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX}, ++ {16700, R_028414_CB_BLEND_RED}, ++ {16713, R_028418_CB_BLEND_GREEN}, ++ {16728, R_02841C_CB_BLEND_BLUE}, ++ {16742, R_028420_CB_BLEND_ALPHA}, ++ {16757, R_028438_SX_ALPHA_REF}, ++ {16770, R_02843C_PA_CL_VPORT_XSCALE_0}, ++ {16791, R_028440_PA_CL_VPORT_XOFFSET_0}, ++ {16813, R_028444_PA_CL_VPORT_YSCALE_0}, ++ {16834, R_028448_PA_CL_VPORT_YOFFSET_0}, ++ {16856, R_02844C_PA_CL_VPORT_ZSCALE_0}, ++ {16877, R_028450_PA_CL_VPORT_ZOFFSET_0}, ++ {16899, R_0285BC_PA_CL_UCP0_X}, ++ {16912, R_0285C0_PA_CL_UCP0_Y}, ++ {16925, R_0285C4_PA_CL_UCP0_Z}, ++ {16938, R_0285C8_PA_CL_UCP0_W}, ++ {16951, R_0285CC_PA_CL_UCP1_X}, ++ {16964, R_0285D0_PA_CL_UCP1_Y}, ++ {16977, R_0285D4_PA_CL_UCP1_Z}, ++ {16990, R_0285D8_PA_CL_UCP1_W}, ++ {17003, R_0285DC_PA_CL_UCP2_X}, ++ {17016, R_0285E0_PA_CL_UCP2_Y}, ++ {17029, R_0285E4_PA_CL_UCP2_Z}, ++ {17042, R_0285E8_PA_CL_UCP2_W}, ++ {17055, R_0285EC_PA_CL_UCP3_X}, ++ {17068, R_0285F0_PA_CL_UCP3_Y}, ++ {17081, R_0285F4_PA_CL_UCP3_Z}, ++ {17094, R_0285F8_PA_CL_UCP3_W}, ++ {17107, R_0285FC_PA_CL_UCP4_X}, ++ {17120, R_028600_PA_CL_UCP4_Y}, ++ {17133, R_028604_PA_CL_UCP4_Z}, ++ {17146, R_028608_PA_CL_UCP4_W}, ++ {17159, R_02860C_PA_CL_UCP5_X}, ++ {17172, R_028610_PA_CL_UCP5_Y}, ++ {17185, R_028614_PA_CL_UCP5_Z}, ++ {17198, R_028618_PA_CL_UCP5_W}, ++ {17211, R_02861C_SPI_VS_OUT_ID_0}, ++ {17227, R_028620_SPI_VS_OUT_ID_1}, ++ {17243, R_028624_SPI_VS_OUT_ID_2}, ++ {17259, R_028628_SPI_VS_OUT_ID_3}, ++ {17275, R_02862C_SPI_VS_OUT_ID_4}, ++ {17291, R_028630_SPI_VS_OUT_ID_5}, ++ {17307, R_028634_SPI_VS_OUT_ID_6}, ++ {17323, R_028638_SPI_VS_OUT_ID_7}, ++ {17339, R_02863C_SPI_VS_OUT_ID_8}, ++ {17355, R_028640_SPI_VS_OUT_ID_9}, ++ {17371, R_028648_SPI_PS_INPUT_CNTL_1, 8, 414}, ++ {17391, R_02864C_SPI_PS_INPUT_CNTL_2, 8, 414}, ++ {17411, R_028650_SPI_PS_INPUT_CNTL_3, 8, 414}, ++ {17431, R_028654_SPI_PS_INPUT_CNTL_4, 8, 414}, ++ {17451, R_028658_SPI_PS_INPUT_CNTL_5, 8, 414}, ++ {17471, R_02865C_SPI_PS_INPUT_CNTL_6, 8, 414}, ++ {17491, R_028660_SPI_PS_INPUT_CNTL_7, 8, 414}, ++ {17511, R_028664_SPI_PS_INPUT_CNTL_8, 8, 414}, ++ {17531, R_028668_SPI_PS_INPUT_CNTL_9, 8, 414}, ++ {17551, R_02866C_SPI_PS_INPUT_CNTL_10, 8, 414}, ++ {17572, R_028670_SPI_PS_INPUT_CNTL_11, 8, 414}, ++ {17593, R_028674_SPI_PS_INPUT_CNTL_12, 8, 414}, ++ {17614, R_028678_SPI_PS_INPUT_CNTL_13, 8, 414}, ++ {17635, R_02867C_SPI_PS_INPUT_CNTL_14, 8, 414}, ++ {17656, R_028680_SPI_PS_INPUT_CNTL_15, 8, 414}, ++ {17677, R_028684_SPI_PS_INPUT_CNTL_16, 8, 414}, ++ {17698, R_028688_SPI_PS_INPUT_CNTL_17, 8, 414}, ++ {17719, R_02868C_SPI_PS_INPUT_CNTL_18, 8, 414}, ++ {17740, R_028690_SPI_PS_INPUT_CNTL_19, 8, 414}, ++ {17761, R_028694_SPI_PS_INPUT_CNTL_20, 8, 414}, ++ {17782, R_028698_SPI_PS_INPUT_CNTL_21, 8, 414}, ++ {17803, R_02869C_SPI_PS_INPUT_CNTL_22, 8, 414}, ++ {17824, R_0286A0_SPI_PS_INPUT_CNTL_23, 8, 414}, ++ {17845, R_0286A4_SPI_PS_INPUT_CNTL_24, 8, 414}, ++ {17866, R_0286A8_SPI_PS_INPUT_CNTL_25, 8, 414}, ++ {17887, R_0286AC_SPI_PS_INPUT_CNTL_26, 8, 414}, ++ {17908, R_0286B0_SPI_PS_INPUT_CNTL_27, 8, 414}, ++ {17929, R_0286B4_SPI_PS_INPUT_CNTL_28, 8, 414}, ++ {17950, R_0286B8_SPI_PS_INPUT_CNTL_29, 8, 414}, ++ {17971, R_0286BC_SPI_PS_INPUT_CNTL_30, 8, 414}, ++ {17992, R_0286C0_SPI_PS_INPUT_CNTL_31, 8, 414}, ++ {18013, R_0286C8_SPI_THREAD_GROUPING}, ++ {18033, R_0286D8_SPI_INPUT_Z, 1, 461}, ++ {18045, R_0286DC_SPI_FOG_CNTL}, ++ {18058, R_0286E4_SPI_PS_IN_CONTROL_2, 8, 225}, ++ {18078, R_0286E8_SPI_COMPUTE_INPUT_CNTL, 3, 462}, ++ {18101, R_028720_GDS_ADDR_BASE}, ++ {18115, R_028724_GDS_ADDR_SIZE}, ++ {18129, R_028728_GDS_ORDERED_WAVE_PER_SE}, ++ {18153, R_02872C_GDS_APPEND_COUNT_0}, ++ {18172, R_028730_GDS_APPEND_COUNT_1}, ++ {18191, R_028734_GDS_APPEND_COUNT_2}, ++ {18210, R_028738_GDS_APPEND_COUNT_3}, ++ {18229, R_02873C_GDS_APPEND_COUNT_4}, ++ {18248, R_028740_GDS_APPEND_COUNT_5}, ++ {18267, R_028748_GDS_APPEND_COUNT_6}, ++ {18286, R_028744_GDS_APPEND_COUNT_7}, ++ {18305, R_028744_GDS_APPEND_COUNT_8}, ++ {18324, R_028744_GDS_APPEND_COUNT_9}, ++ {18343, R_028744_GDS_APPEND_COUNT_10}, ++ {18363, R_028744_GDS_APPEND_COUNT_11}, ++ {18383, R_028784_CB_BLEND1_CONTROL, 9, 163}, ++ {18401, R_028788_CB_BLEND2_CONTROL, 9, 163}, ++ {18419, R_02878C_CB_BLEND3_CONTROL, 9, 163}, ++ {18437, R_028790_CB_BLEND4_CONTROL, 9, 163}, ++ {18455, R_028794_CB_BLEND5_CONTROL, 9, 163}, ++ {18473, R_028798_CB_BLEND6_CONTROL, 9, 163}, ++ {18491, R_02879C_CB_BLEND7_CONTROL, 9, 163}, ++ {18509, R_028818_PA_CL_VTE_CNTL, 9, 465}, ++ {18524, R_028820_PA_CL_NANINF_CNTL}, ++ {18542, R_028830_SQ_LSTMP_RING_ITEMSIZE}, ++ {18565, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1, 6, 474}, ++ {18593, R_028840_SQ_PGM_START_PS}, ++ {18609, R_02884C_SQ_PGM_EXPORTS_PS, 2, 480}, ++ {18627, R_02885C_SQ_PGM_START_VS}, ++ {18643, R_028874_SQ_PGM_START_GS}, ++ {18659, R_02888C_SQ_PGM_START_ES}, ++ {18675, R_0288A4_SQ_PGM_START_FS}, ++ {18691, R_0288B8_SQ_PGM_START_HS}, ++ {18707, R_0288D0_SQ_PGM_START_LS}, ++ {18723, R_0288A8_SQ_PGM_RESOURCES_FS}, ++ {18743, R_0288E8_SQ_LDS_ALLOC}, ++ {18756, R_0288EC_SQ_LDS_ALLOC_PS}, ++ {18772, R_028900_SQ_ESGS_RING_ITEMSIZE}, ++ {18794, R_028904_SQ_GSVS_RING_ITEMSIZE}, ++ {18816, R_008C50_SQ_ESTMP_RING_BASE}, ++ {18835, R_028908_SQ_ESTMP_RING_ITEMSIZE}, ++ {18858, R_008C54_SQ_ESTMP_RING_SIZE}, ++ {18877, R_008C58_SQ_GSTMP_RING_BASE}, ++ {18896, R_02890C_SQ_GSTMP_RING_ITEMSIZE}, ++ {18919, R_008C5C_SQ_GSTMP_RING_SIZE}, ++ {18938, R_008C60_SQ_VSTMP_RING_BASE}, ++ {18957, R_028910_SQ_VSTMP_RING_ITEMSIZE}, ++ {18980, R_008C64_SQ_VSTMP_RING_SIZE}, ++ {18999, R_008C68_SQ_PSTMP_RING_BASE}, ++ {19018, R_028914_SQ_PSTMP_RING_ITEMSIZE}, ++ {19041, R_008C6C_SQ_PSTMP_RING_SIZE}, ++ {19060, R_008E10_SQ_LSTMP_RING_BASE}, ++ {19079, R_008E14_SQ_LSTMP_RING_SIZE}, ++ {19098, R_008E18_SQ_HSTMP_RING_BASE}, ++ {19117, R_028834_SQ_HSTMP_RING_ITEMSIZE}, ++ {19140, R_008E1C_SQ_HSTMP_RING_SIZE}, ++ {19159, R_02891C_SQ_GS_VERT_ITEMSIZE}, ++ {19179, R_028920_SQ_GS_VERT_ITEMSIZE_1}, ++ {19201, R_028924_SQ_GS_VERT_ITEMSIZE_2}, ++ {19223, R_028928_SQ_GS_VERT_ITEMSIZE_3}, ++ {19245, R_02892C_SQ_GSVS_RING_OFFSET_1}, ++ {19267, R_028930_SQ_GSVS_RING_OFFSET_2}, ++ {19289, R_028934_SQ_GSVS_RING_OFFSET_3}, ++ {19311, R_028940_ALU_CONST_CACHE_PS_0}, ++ {19332, R_028944_ALU_CONST_CACHE_PS_1}, ++ {19353, R_028980_ALU_CONST_CACHE_VS_0}, ++ {19374, R_028984_ALU_CONST_CACHE_VS_1}, ++ {19395, R_0289C0_ALU_CONST_CACHE_GS_0}, ++ {19416, R_028F00_ALU_CONST_CACHE_HS_0}, ++ {19437, R_028F40_ALU_CONST_CACHE_LS_0}, ++ {19458, R_028A04_PA_SU_POINT_MINMAX, 2, 482}, ++ {19477, R_028A08_PA_SU_LINE_CNTL, 1, 484}, ++ {19493, R_028A10_VGT_OUTPUT_PATH_CNTL}, ++ {19514, R_028A14_VGT_HOS_CNTL}, ++ {19527, R_028A18_VGT_HOS_MAX_TESS_LEVEL}, ++ {19550, R_028A1C_VGT_HOS_MIN_TESS_LEVEL}, ++ {19573, R_028A20_VGT_HOS_REUSE_DEPTH}, ++ {19593, R_028A24_VGT_GROUP_PRIM_TYPE}, ++ {19613, R_028A28_VGT_GROUP_FIRST_DECR}, ++ {19634, R_028A2C_VGT_GROUP_DECR}, ++ {19649, R_028A30_VGT_GROUP_VECT_0_CNTL}, ++ {19671, R_028A34_VGT_GROUP_VECT_1_CNTL}, ++ {19693, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL}, ++ {19719, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL}, ++ {19745, R_028A48_PA_SC_MODE_CNTL_0, 3, 485}, ++ {19763, R_028A4C_PA_SC_MODE_CNTL_1, 3, 485}, ++ {19781, R_028A54_GS_PER_ES}, ++ {19791, R_028A58_ES_PER_GS}, ++ {19801, R_028A5C_GS_PER_VS}, ++ {19811, R_028A84_VGT_PRIMITIVEID_EN, 1, 488}, ++ {19830, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 1, 489}, ++ {19857, R_028AB4_VGT_REUSE_OFF}, ++ {19871, R_028AB8_VGT_VTX_CNT_EN}, ++ {19886, R_028AC0_DB_SRESULTS_COMPARE_STATE0}, ++ {19913, R_028AC4_DB_SRESULTS_COMPARE_STATE1}, ++ {19940, R_028AC8_DB_PRELOAD_CONTROL, 2, 490}, ++ {19959, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0}, ++ {19985, R_028AD4_VGT_STRMOUT_VTX_STRIDE_0}, ++ {20010, R_028AD8_VGT_STRMOUT_BUFFER_BASE_0}, ++ {20036, R_028ADC_VGT_STRMOUT_BUFFER_OFFSET_0}, ++ {20064, R_028AE0_VGT_STRMOUT_BUFFER_SIZE_1}, ++ {20090, R_028AE4_VGT_STRMOUT_VTX_STRIDE_1}, ++ {20115, R_028AE8_VGT_STRMOUT_BUFFER_BASE_1}, ++ {20141, R_028AEC_VGT_STRMOUT_BUFFER_OFFSET_1}, ++ {20169, R_028AF0_VGT_STRMOUT_BUFFER_SIZE_2}, ++ {20195, R_028AF4_VGT_STRMOUT_VTX_STRIDE_2}, ++ {20220, R_028AF8_VGT_STRMOUT_BUFFER_BASE_2}, ++ {20246, R_028AFC_VGT_STRMOUT_BUFFER_OFFSET_2}, ++ {20274, R_028B00_VGT_STRMOUT_BUFFER_SIZE_3}, ++ {20300, R_028B04_VGT_STRMOUT_VTX_STRIDE_3}, ++ {20325, R_028B08_VGT_STRMOUT_BUFFER_BASE_3}, ++ {20351, R_028B0C_VGT_STRMOUT_BUFFER_OFFSET_3}, ++ {20379, R_028B10_VGT_STRMOUT_BASE_OFFSET_0}, ++ {20405, R_028B14_VGT_STRMOUT_BASE_OFFSET_1}, ++ {20431, R_028B18_VGT_STRMOUT_BASE_OFFSET_2}, ++ {20457, R_028B1C_VGT_STRMOUT_BASE_OFFSET_3}, ++ {20483, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET}, ++ {20514, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE}, ++ {20557, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE}, ++ {20595, R_028B38_VGT_GS_MAX_VERT_OUT, 1, 492}, ++ {20615, R_028B44_VGT_STRMOUT_BASE_OFFSET_HI_0}, ++ {20644, R_028B48_VGT_STRMOUT_BASE_OFFSET_HI_1}, ++ {20673, R_028B4C_VGT_STRMOUT_BASE_OFFSET_HI_2}, ++ {20702, R_028B50_VGT_STRMOUT_BASE_OFFSET_HI_3}, ++ {20731, R_028B54_VGT_SHADER_STAGES_EN, 5, 493}, ++ {20752, R_028B58_VGT_LS_HS_CONFIG, 3, 498}, ++ {20769, R_028B5C_VGT_LS_SIZE, 2, 501}, ++ {20781, R_028B60_VGT_HS_SIZE, 2, 503}, ++ {20793, R_028B64_VGT_LS_HS_ALLOC, 2, 505}, ++ {20809, R_028B68_VGT_HS_PATCH_CONST, 2, 507}, ++ {20828, R_028B70_DB_ALPHA_TO_MASK, 6, 509}, ++ {20845, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 2, 515}, ++ {20875, R_028B7C_PA_SU_POLY_OFFSET_CLAMP}, ++ {20899, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 1, 517}, ++ {20929, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, 1, 518}, ++ {20960, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, 1, 519}, ++ {20989, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, 1, 520}, ++ {21019, R_028B90_VGT_GS_INSTANCE_CNT, 2, 521}, ++ {21039, R_028B9C_CB_IMMED0_BASE}, ++ {21054, R_028BA0_CB_IMMED1_BASE}, ++ {21069, R_028BA4_CB_IMMED2_BASE}, ++ {21084, R_028BA4_CB_IMMED3_BASE}, ++ {21099, R_028BA4_CB_IMMED4_BASE}, ++ {21114, R_028BA4_CB_IMMED5_BASE}, ++ {21129, R_028BA4_CB_IMMED6_BASE}, ++ {21144, R_028BA4_CB_IMMED7_BASE}, ++ {21159, R_028BA4_CB_IMMED8_BASE}, ++ {21174, R_028BA4_CB_IMMED9_BASE}, ++ {21189, R_028BA4_CB_IMMED10_BASE}, ++ {21205, R_028BA4_CB_IMMED11_BASE}, ++ {21221, R_028C00_PA_SC_LINE_CNTL, 2, 523}, ++ {21237, R_028C04_PA_SC_AA_CONFIG, 3, 525}, ++ {21253, R_028C08_PA_SU_VTX_CNTL, 2, 528}, ++ {21268, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ}, ++ {21291, R_028C10_PA_CL_GB_VERT_DISC_ADJ}, ++ {21314, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ}, ++ {21337, R_028C18_PA_CL_GB_HORZ_DISC_ADJ}, ++ {21360, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0}, ++ {21383, R_028C20_PA_SC_AA_SAMPLE_LOCS_1}, ++ {21406, R_028C24_PA_SC_AA_SAMPLE_LOCS_2}, ++ {21429, R_028C28_PA_SC_AA_SAMPLE_LOCS_3}, ++ {21452, R_028C2C_PA_SC_AA_SAMPLE_LOCS_4}, ++ {21475, R_028C30_PA_SC_AA_SAMPLE_LOCS_5}, ++ {21498, R_028C34_PA_SC_AA_SAMPLE_LOCS_6}, ++ {21521, R_028C38_PA_SC_AA_SAMPLE_LOCS_7}, ++ {21544, R_028C3C_PA_SC_AA_MASK}, ++ {21558, R_028C60_CB_COLOR0_BASE}, ++ {21573, R_028C6C_CB_COLOR0_VIEW, 2, 530}, ++ {21588, R_028C7C_CB_COLOR0_CMASK}, ++ {21604, R_028C80_CB_COLOR0_CMASK_SLICE, 1, 532}, ++ {21626, R_028C84_CB_COLOR0_FMASK}, ++ {21642, R_028C88_CB_COLOR0_FMASK_SLICE, 1, 533}, ++ {21664, R_028C8C_CB_COLOR0_CLEAR_WORD0}, ++ {21686, R_028C90_CB_COLOR0_CLEAR_WORD1}, ++ {21708, R_028C94_CB_COLOR0_CLEAR_WORD2}, ++ {21730, R_028C98_CB_COLOR0_CLEAR_WORD3}, ++ {21752, R_028C9C_CB_COLOR1_BASE}, ++ {21767, R_028CA0_CB_COLOR1_PITCH, 1, 68}, ++ {21783, R_028CA4_CB_COLOR1_SLICE, 1, 69}, ++ {21799, R_028CA8_CB_COLOR1_VIEW, 2, 530}, ++ {21814, R_028CAC_CB_COLOR1_INFO, 15, 70}, ++ {21829, R_028CB0_CB_COLOR1_ATTRIB, 10, 85}, ++ {21846, R_028CB4_CB_COLOR1_DIM, 2, 95}, ++ {21860, R_028CB8_CB_COLOR1_CMASK}, ++ {21876, R_028CBC_CB_COLOR1_CMASK_SLICE, 1, 532}, ++ {21898, R_028CC0_CB_COLOR1_FMASK}, ++ {21914, R_028CC4_CB_COLOR1_FMASK_SLICE, 1, 533}, ++ {21936, R_028CC8_CB_COLOR1_CLEAR_WORD0}, ++ {21958, R_028CCC_CB_COLOR1_CLEAR_WORD1}, ++ {21980, R_028CD0_CB_COLOR1_CLEAR_WORD2}, ++ {22002, R_028CD4_CB_COLOR1_CLEAR_WORD3}, ++ {22024, R_028CD8_CB_COLOR2_BASE}, ++ {22039, R_028CDC_CB_COLOR2_PITCH, 1, 68}, ++ {22055, R_028CE0_CB_COLOR2_SLICE, 1, 69}, ++ {22071, R_028CE4_CB_COLOR2_VIEW, 2, 530}, ++ {22086, R_028CE8_CB_COLOR2_INFO, 15, 70}, ++ {22101, R_028CEC_CB_COLOR2_ATTRIB, 10, 85}, ++ {22118, R_028CF0_CB_COLOR2_DIM, 2, 95}, ++ {22132, R_028CF4_CB_COLOR2_CMASK}, ++ {22148, R_028CF8_CB_COLOR2_CMASK_SLICE, 1, 532}, ++ {22170, R_028CFC_CB_COLOR2_FMASK}, ++ {22186, R_028D00_CB_COLOR2_FMASK_SLICE, 1, 533}, ++ {22208, R_028D04_CB_COLOR2_CLEAR_WORD0}, ++ {22230, R_028D08_CB_COLOR2_CLEAR_WORD1}, ++ {22252, R_028D0C_CB_COLOR2_CLEAR_WORD2}, ++ {22274, R_028D10_CB_COLOR2_CLEAR_WORD3}, ++ {22296, R_028D14_CB_COLOR3_BASE}, ++ {22311, R_028D18_CB_COLOR3_PITCH, 1, 68}, ++ {22327, R_028D1C_CB_COLOR3_SLICE, 1, 69}, ++ {22343, R_028D20_CB_COLOR3_VIEW, 2, 530}, ++ {22358, R_028D24_CB_COLOR3_INFO, 15, 70}, ++ {22373, R_028D28_CB_COLOR3_ATTRIB, 10, 85}, ++ {22390, R_028D2C_CB_COLOR3_DIM, 2, 95}, ++ {22404, R_028D30_CB_COLOR3_CMASK}, ++ {22420, R_028D34_CB_COLOR3_CMASK_SLICE, 1, 532}, ++ {22442, R_028D38_CB_COLOR3_FMASK}, ++ {22458, R_028D3C_CB_COLOR3_FMASK_SLICE, 1, 533}, ++ {22480, R_028D40_CB_COLOR3_CLEAR_WORD0}, ++ {22502, R_028D44_CB_COLOR3_CLEAR_WORD1}, ++ {22524, R_028D48_CB_COLOR3_CLEAR_WORD2}, ++ {22546, R_028D4C_CB_COLOR3_CLEAR_WORD3}, ++ {22568, R_028D50_CB_COLOR4_BASE}, ++ {22583, R_028D54_CB_COLOR4_PITCH, 1, 68}, ++ {22599, R_028D58_CB_COLOR4_SLICE, 1, 69}, ++ {22615, R_028D5C_CB_COLOR4_VIEW, 2, 530}, ++ {22630, R_028D60_CB_COLOR4_INFO, 15, 70}, ++ {22645, R_028D64_CB_COLOR4_ATTRIB, 10, 85}, ++ {22662, R_028D68_CB_COLOR4_DIM, 2, 95}, ++ {22676, R_028D6C_CB_COLOR4_CMASK}, ++ {22692, R_028D70_CB_COLOR4_CMASK_SLICE, 1, 532}, ++ {22714, R_028D74_CB_COLOR4_FMASK}, ++ {22730, R_028D78_CB_COLOR4_FMASK_SLICE, 1, 533}, ++ {22752, R_028D7C_CB_COLOR4_CLEAR_WORD0}, ++ {22774, R_028D80_CB_COLOR4_CLEAR_WORD1}, ++ {22796, R_028D84_CB_COLOR4_CLEAR_WORD2}, ++ {22818, R_028D88_CB_COLOR4_CLEAR_WORD3}, ++ {22840, R_028D8C_CB_COLOR5_BASE}, ++ {22855, R_028D90_CB_COLOR5_PITCH, 1, 68}, ++ {22871, R_028D94_CB_COLOR5_SLICE, 1, 69}, ++ {22887, R_028D98_CB_COLOR5_VIEW, 2, 530}, ++ {22902, R_028D9C_CB_COLOR5_INFO, 15, 70}, ++ {22917, R_028DA0_CB_COLOR5_ATTRIB, 10, 85}, ++ {22934, R_028DA4_CB_COLOR5_DIM, 2, 95}, ++ {22948, R_028DA8_CB_COLOR5_CMASK}, ++ {22964, R_028DAC_CB_COLOR5_CMASK_SLICE, 1, 532}, ++ {22986, R_028DB0_CB_COLOR5_FMASK}, ++ {23002, R_028DB4_CB_COLOR5_FMASK_SLICE, 1, 533}, ++ {23024, R_028DB8_CB_COLOR5_CLEAR_WORD0}, ++ {23046, R_028DBC_CB_COLOR5_CLEAR_WORD1}, ++ {23068, R_028DC0_CB_COLOR5_CLEAR_WORD2}, ++ {23090, R_028DC4_CB_COLOR5_CLEAR_WORD3}, ++ {23112, R_028DC8_CB_COLOR6_BASE}, ++ {23127, R_028DCC_CB_COLOR6_PITCH, 1, 68}, ++ {23143, R_028DD0_CB_COLOR6_SLICE, 1, 69}, ++ {23159, R_028DD4_CB_COLOR6_VIEW, 2, 530}, ++ {23174, R_028DD8_CB_COLOR6_INFO, 15, 70}, ++ {23189, R_028DDC_CB_COLOR6_ATTRIB, 10, 85}, ++ {23206, R_028DE0_CB_COLOR6_DIM, 2, 95}, ++ {23220, R_028DE4_CB_COLOR6_CMASK}, ++ {23236, R_028DE8_CB_COLOR6_CMASK_SLICE, 1, 532}, ++ {23258, R_028DEC_CB_COLOR6_FMASK}, ++ {23274, R_028DF0_CB_COLOR6_FMASK_SLICE, 1, 533}, ++ {23296, R_028DF4_CB_COLOR6_CLEAR_WORD0}, ++ {23318, R_028DF8_CB_COLOR6_CLEAR_WORD1}, ++ {23340, R_028DFC_CB_COLOR6_CLEAR_WORD2}, ++ {23362, R_028E00_CB_COLOR6_CLEAR_WORD3}, ++ {23384, R_028E04_CB_COLOR7_BASE}, ++ {23399, R_028E08_CB_COLOR7_PITCH, 1, 68}, ++ {23415, R_028E0C_CB_COLOR7_SLICE, 1, 69}, ++ {23431, R_028E10_CB_COLOR7_VIEW, 2, 530}, ++ {23446, R_028E14_CB_COLOR7_INFO, 15, 70}, ++ {23461, R_028E18_CB_COLOR7_ATTRIB, 10, 85}, ++ {23478, R_028E1C_CB_COLOR7_DIM, 2, 95}, ++ {23492, R_028E20_CB_COLOR7_CMASK}, ++ {23508, R_028E24_CB_COLOR7_CMASK_SLICE, 1, 532}, ++ {23530, R_028E28_CB_COLOR7_FMASK}, ++ {23546, R_028E2C_CB_COLOR7_FMASK_SLICE, 1, 533}, ++ {23568, R_028E30_CB_COLOR7_CLEAR_WORD0}, ++ {23590, R_028E34_CB_COLOR7_CLEAR_WORD1}, ++ {23612, R_028E38_CB_COLOR7_CLEAR_WORD2}, ++ {23634, R_028E3C_CB_COLOR7_CLEAR_WORD3}, ++ {23656, R_028E40_CB_COLOR8_BASE}, ++ {23671, R_028E44_CB_COLOR8_PITCH, 1, 68}, ++ {23687, R_028E48_CB_COLOR8_SLICE, 1, 69}, ++ {23703, R_028E4C_CB_COLOR8_VIEW, 2, 530}, ++ {23718, R_028E50_CB_COLOR8_INFO, 15, 70}, ++ {23733, R_028E54_CB_COLOR8_ATTRIB, 10, 85}, ++ {23750, R_028E58_CB_COLOR8_DIM, 2, 95}, ++ {23764, R_028E5C_CB_COLOR9_BASE}, ++ {23779, R_028E60_CB_COLOR9_PITCH, 1, 68}, ++ {23795, R_028E64_CB_COLOR9_SLICE, 1, 69}, ++ {23811, R_028E68_CB_COLOR9_VIEW, 2, 530}, ++ {23826, R_028E6C_CB_COLOR9_INFO, 15, 70}, ++ {23841, R_028E70_CB_COLOR9_ATTRIB, 10, 85}, ++ {23858, R_028E74_CB_COLOR9_DIM, 2, 95}, ++ {23872, R_028E78_CB_COLOR10_BASE}, ++ {23888, R_028E7C_CB_COLOR10_PITCH, 1, 68}, ++ {23905, R_028E80_CB_COLOR10_SLICE, 1, 69}, ++ {23922, R_028E84_CB_COLOR10_VIEW, 2, 530}, ++ {23938, R_028E88_CB_COLOR10_INFO, 15, 70}, ++ {23954, R_028E8C_CB_COLOR10_ATTRIB, 10, 85}, ++ {23972, R_028E90_CB_COLOR10_DIM, 2, 95}, ++ {23987, R_028E94_CB_COLOR11_BASE}, ++ {24003, R_028E98_CB_COLOR11_PITCH, 1, 68}, ++ {24020, R_028E9C_CB_COLOR11_SLICE, 1, 69}, ++ {24037, R_028EA0_CB_COLOR11_VIEW, 2, 530}, ++ {24053, R_028EA4_CB_COLOR11_INFO, 15, 70}, ++ {24069, R_028EA8_CB_COLOR11_ATTRIB, 10, 85}, ++ {24087, R_028EAC_CB_COLOR11_DIM, 2, 95}, ++ {24102, R_030000_RESOURCE0_WORD0}, ++ {24118, R_030004_RESOURCE0_WORD1}, ++ {24134, R_030008_RESOURCE0_WORD2}, ++ {24150, R_03000C_RESOURCE0_WORD3}, ++ {24166, R_030010_RESOURCE0_WORD4}, ++ {24182, R_030014_RESOURCE0_WORD5}, ++ {24198, R_030018_RESOURCE0_WORD6}, ++ {24214, R_03001C_RESOURCE0_WORD7}, ++ {24230, R_0085F0_CP_COHER_CNTL, 28, 534}, ++ {24244, R_0085F4_CP_COHER_SIZE}, ++ {24258, R_0085F8_CP_COHER_BASE}, ++ {24272, R_008970_VGT_NUM_INDICES}, ++ {24288, R_03CFF0_SQ_VTX_BASE_VTX_LOC}, ++ {24308, R_03CFF4_SQ_VTX_START_INST_LOC}, ++ {24330, R_03A200_SQ_LOOP_CONST_0, 20, 562}, ++}; ++ ++static const char egd_strings[] = ++ "NOP\0" /* 0 */ ++ "DEALLOC_STATE\0" /* 4 */ ++ "DISPATCH_DIRECT\0" /* 18 */ ++ "DISPATCH_INDIRECT\0" /* 34 */ ++ "INDIRECT_BUFFER_END\0" /* 52 */ ++ "SET_PREDICATION\0" /* 72 */ ++ "REG_RMW\0" /* 88 */ ++ "COND_EXEC\0" /* 96 */ ++ "PRED_EXEC\0" /* 106 */ ++ "DRAW_INDEX_2\0" /* 116 */ ++ "CONTEXT_CONTROL\0" /* 129 */ ++ "DRAW_INDEX_IMMD_BE\0" /* 145 */ ++ "INDEX_TYPE\0" /* 170, 164 */ ++ "DRAW_INDEX\0" /* 175 */ ++ "DRAW_INDEX_AUTO\0" /* 186 */ ++ "DRAW_INDEX_IMMD\0" /* 202 */ ++ "NUM_INSTANCES\0" /* 218 */ ++ "STRMOUT_BUFFER_UPDATE\0" /* 232 */ ++ "INDIRECT_BUFFER_MP\0" /* 254 */ ++ "MEM_SEMAPHORE\0" /* 273 */ ++ "MPEG_INDEX\0" /* 287 */ ++ "WAIT_REG_MEM\0" /* 298 */ ++ "MEM_WRITE\0" /* 311 */ ++ "INDIRECT_BUFFER\0" /* 321, 330 */ ++ "PFP_SYNC_ME\0" /* 337 */ ++ "SURFACE_SYNC\0" /* 349 */ ++ "ME_INITIALIZE\0" /* 362 */ ++ "COND_WRITE\0" /* 376 */ ++ "EVENT_WRITE\0" /* 387 */ ++ "EVENT_WRITE_EOP\0" /* 399 */ ++ "EVENT_WRITE_EOS\0" /* 415 */ ++ "ONE_REG_WRITE\0" /* 431 */ ++ "SET_CONFIG_REG\0" /* 445 */ ++ "SET_CONTEXT_REG\0" /* 460 */ ++ "SET_ALU_CONST\0" /* 476 */ ++ "SET_BOOL_CONST\0" /* 490 */ ++ "SET_LOOP_CONST\0" /* 505 */ ++ "SET_RESOURCE\0" /* 520 */ ++ "SET_SAMPLER\0" /* 533 */ ++ "SET_CTL_CONST\0" /* 545 */ ++ "SURFACE_BASE_UPDATE\0" /* 559 */ ++ "IT_OPCODE_C\0" /* 579 */ ++ "CP_DMA\0" /* 591 */ ++ "SET_APPEND_CNT\0" /* 609, 598 */ ++ "SAC_SRC_SEL_DATA\0" /* 613 */ ++ "SAC_SRC_SEL_REG\0" /* 630 */ ++ "SAC_SRC_SEL_GDS\0" /* 646 */ ++ "SAC_SRC_SEL_MEM\0" /* 662 */ ++ "OFFSET_UPDATE_DONE\0" /* 678 */ ++ "STREAMOUT_0_EN\0" /* 697 */ ++ "STREAMOUT_1_EN\0" /* 712 */ ++ "STREAMOUT_2_EN\0" /* 727 */ ++ "STREAMOUT_3_EN\0" /* 742 */ ++ "RAST_STREAM\0" /* 757 */ ++ "RAST_STREAM_MASK\0" /* 769 */ ++ "USE_RAST_STREAM_MASK\0" /* 786 */ ++ "STREAM_0_BUFFER_EN\0" /* 807 */ ++ "STREAM_1_BUFFER_EN\0" /* 826 */ ++ "STREAM_2_BUFFER_EN\0" /* 845 */ ++ "STREAM_3_BUFFER_EN\0" /* 864 */ ++ "MAX_ANCHOR_SAMPLES\0" /* 883 */ ++ "PS_ITER_SAMPLES\0" /* 902 */ ++ "MASK_EXPORT_NUM_SAMPLES\0" /* 930, 918 */ ++ "ALPHA_TO_MASK_NUM_SAMPLES\0" /* 942 */ ++ "HIGH_QUALITY_INTERSECTIONS\0" /* 968 */ ++ "INCOHERENT_EQAA_READS\0" /* 995 */ ++ "INTERPOLATE_COMP_Z\0" /* 1017 */ ++ "INTERPOLATE_SRC_Z\0" /* 1036 */ ++ "STATIC_ANCHOR_ASSOCIATIONS\0" /* 1054 */ ++ "ALPHA_TO_MASK_EQAA_DISABLE\0" /* 1081 */ ++ "OVERRASTERIZATION_AMOUNT\0" /* 1108 */ ++ "ENABLE_POSTZ_OVERRASTERIZATION\0" /* 1133 */ ++ "EXPAND_LINE_WIDTH\0" /* 1176, 1164 */ ++ "LAST_PIXEL\0" /* 1182 */ ++ "PERPENDICULAR_ENDCAP_ENA\0" /* 1193 */ ++ "DX10_DIAMOND_TEST_ENA\0" /* 1218 */ ++ "MSAA_NUM_SAMPLES\0" /* 1240 */ ++ "AA_MASK_CENTROID_DTMN\0" /* 1257 */ ++ "MAX_SAMPLE_DIST\0" /* 1279 */ ++ "MSAA_EXPOSED_SAMPLES\0" /* 1295 */ ++ "DETAIL_TO_EXPOSED_MODE\0" /* 1316, 1334 */ ++ "VC_ENABLE\0" /* 1339, 1342 */ ++ "EXPORT_SRC_C\0" /* 1349 */ ++ "CS_PRIO\0" /* 1362 */ ++ "LS_PRIO\0" /* 1370 */ ++ "HS_PRIO\0" /* 1378 */ ++ "PS_PRIO\0" /* 1386 */ ++ "VS_PRIO\0" /* 1394 */ ++ "GS_PRIO\0" /* 1402 */ ++ "ES_PRIO\0" /* 1410 */ ++ "NUM_PS_GPRS\0" /* 1418, 1422 */ ++ "NUM_VS_GPRS\0" /* 1434, 1430 */ ++ "NUM_CLAUSE_TEMP_GPRS\0" /* 1442 */ ++ "NUM_GS_GPRS\0" /* 1467, 1463 */ ++ "NUM_ES_GPRS\0" /* 1475, 1479 */ ++ "NUM_HS_GPRS\0" /* 1491, 1487 */ ++ "NUM_LS_GPRS\0" /* 1499, 1503 */ ++ "NUM_PS_THREADS\0" /* 1511 */ ++ "NUM_VS_THREADS\0" /* 1526 */ ++ "NUM_GS_THREADS\0" /* 1541 */ ++ "NUM_ES_THREADS\0" /* 1556 */ ++ "NUM_HS_THREADS\0" /* 1571 */ ++ "NUM_LS_THREADS\0" /* 1586 */ ++ "NUM_PS_STACK_ENTRIES\0" /* 1601 */ ++ "NUM_VS_STACK_ENTRIES\0" /* 1622 */ ++ "NUM_GS_STACK_ENTRIES\0" /* 1643 */ ++ "NUM_ES_STACK_ENTRIES\0" /* 1664 */ ++ "NUM_HS_STACK_ENTRIES\0" /* 1685 */ ++ "NUM_LS_STACK_ENTRIES\0" /* 1706 */ ++ "NUM_PS_LDS\0" /* 1727 */ ++ "NUM_LS_LDS\0" /* 1738 */ ++ "CACHE_FIFO_SIZE\0" /* 1760, 1749 */ ++ "FETCH_FIFO_HIWATER\0" /* 1765 */ ++ "DONE_FIFO_HIWATER\0" /* 1784 */ ++ "ALU_UPDATE_FIFO_HIWATER\0" /* 1802 */ ++ "VTX_DONE_DELAY\0" /* 1826 */ ++ "PITCH_TILE_MAX\0" /* 1841, 1847 */ ++ "SLICE_TILE_MAX\0" /* 1856 */ ++ "ENDIAN\0" /* 1871 */ ++ "COLOR_INVALID\0" /* 1878 */ ++ "COLOR_8\0" /* 1892 */ ++ "COLOR_4_4\0" /* 1900 */ ++ "COLOR_3_3_2\0" /* 1910 */ ++ "COLOR_16\0" /* 1922 */ ++ "COLOR_16_FLOAT\0" /* 1931 */ ++ "COLOR_8_8\0" /* 1946 */ ++ "COLOR_5_6_5\0" /* 1956 */ ++ "COLOR_6_5_5\0" /* 1968 */ ++ "COLOR_1_5_5_5\0" /* 1980 */ ++ "COLOR_4_4_4_4\0" /* 1994 */ ++ "COLOR_5_5_5_1\0" /* 2008 */ ++ "COLOR_32\0" /* 2022 */ ++ "COLOR_32_FLOAT\0" /* 2031 */ ++ "COLOR_16_16\0" /* 2046 */ ++ "COLOR_16_16_FLOAT\0" /* 2058 */ ++ "COLOR_8_24\0" /* 2076 */ ++ "COLOR_8_24_FLOAT\0" /* 2087 */ ++ "COLOR_24_8\0" /* 2104 */ ++ "COLOR_24_8_FLOAT\0" /* 2115 */ ++ "COLOR_10_11_11\0" /* 2132 */ ++ "COLOR_10_11_11_FLOAT\0" /* 2147 */ ++ "COLOR_11_11_10\0" /* 2168 */ ++ "COLOR_11_11_10_FLOAT\0" /* 2183 */ ++ "COLOR_2_10_10_10\0" /* 2204 */ ++ "COLOR_8_8_8_8\0" /* 2221 */ ++ "COLOR_10_10_10_2\0" /* 2235 */ ++ "COLOR_X24_8_32_FLOAT\0" /* 2252 */ ++ "COLOR_32_32\0" /* 2273 */ ++ "COLOR_32_32_FLOAT\0" /* 2285 */ ++ "COLOR_16_16_16_16\0" /* 2303 */ ++ "COLOR_16_16_16_16_FLOAT\0" /* 2321 */ ++ "COLOR_32_32_32_32\0" /* 2345 */ ++ "COLOR_32_32_32_32_FLOAT\0" /* 2363 */ ++ "COLOR_32_32_32_FLOAT\0" /* 2387 */ ++ "FORMAT\0" /* 2408 */ ++ "ARRAY_LINEAR_GENERAL\0" /* 2415 */ ++ "ARRAY_LINEAR_ALIGNED\0" /* 2436 */ ++ "ARRAY_1D_TILED_THIN1\0" /* 2457 */ ++ "ARRAY_2D_TILED_THIN1\0" /* 2478 */ ++ "ARRAY_MODE\0" /* 2499 */ ++ "NUMBER_UNORM\0" /* 2510 */ ++ "NUMBER_SNORM\0" /* 2523 */ ++ "NUMBER_USCALED\0" /* 2536 */ ++ "NUMBER_SSCALED\0" /* 2551 */ ++ "NUMBER_UINT\0" /* 2566 */ ++ "NUMBER_SINT\0" /* 2578 */ ++ "NUMBER_SRGB\0" /* 2590 */ ++ "NUMBER_FLOAT\0" /* 2602 */ ++ "NUMBER_TYPE\0" /* 2615 */ ++ "SWAP_STD\0" /* 2627 */ ++ "SWAP_ALT\0" /* 2636 */ ++ "SWAP_STD_REV\0" /* 2645 */ ++ "SWAP_ALT_REV\0" /* 2658 */ ++ "COMP_SWAP\0" /* 2671 */ ++ "FAST_CLEAR\0" /* 2681 */ ++ "COMPRESSION\0" /* 2692 */ ++ "BLEND_CLAMP\0" /* 2704 */ ++ "BLEND_BYPASS\0" /* 2716 */ ++ "SIMPLE_FLOAT\0" /* 2729 */ ++ "ROUND_MODE\0" /* 2742 */ ++ "TILE_COMPACT\0" /* 2753 */ ++ "EXPORT_4C_32BPC\0" /* 2766 */ ++ "EXPORT_4C_16BPC\0" /* 2782 */ ++ "EXPORT_2C_32BPC\0" /* 2798 */ ++ "SOURCE_FORMAT\0" /* 2814 */ ++ "RAT\0" /* 2828 */ ++ "TEXTURE1D\0" /* 2832 */ ++ "TEXTURE1DARRAY\0" /* 2842 */ ++ "TEXTURE2D\0" /* 2857 */ ++ "TEXTURE2DARRAY\0" /* 2867 */ ++ "TEXTURE3D\0" /* 2882 */ ++ "RESOURCE_TYPE\0" /* 2892 */ ++ "NON_DISP_TILING_ORDER\0" /* 2906 */ ++ "TILE_SPLIT\0" /* 2928 */ ++ "NUM_BANKS\0" /* 2939 */ ++ "BANK_WIDTH\0" /* 2949 */ ++ "BANK_HEIGHT\0" /* 2960, 2965 */ ++ "MACRO_TILE_ASPECT\0" /* 2972 */ ++ "FMASK_BANK_HEIGHT\0" /* 2990 */ ++ "NUM_FRAGMENTS\0" /* 3008 */ ++ "FORCE_DST_ALPHA_1\0" /* 3022 */ ++ "WIDTH_MAX\0" /* 3040 */ ++ "HEIGHT_MAX\0" /* 3050 */ ++ "ALPHA_FUNC\0" /* 3061 */ ++ "ALPHA_TEST_ENABLE\0" /* 3072 */ ++ "ALPHA_TEST_BYPASS\0" /* 3090 */ ++ "TESS_ISOLINE\0" /* 3108 */ ++ "TESS_TRIANGLE\0" /* 3121 */ ++ "TESS_QUAD\0" /* 3135 */ ++ "PART_INTEGER\0" /* 3145 */ ++ "PART_POW2\0" /* 3158 */ ++ "PART_FRAC_ODD\0" /* 3168 */ ++ "PART_FRAC_EVEN\0" /* 3182 */ ++ "PARTITIONING\0" /* 3197 */ ++ "OUTPUT_POINT\0" /* 3210 */ ++ "OUTPUT_LINE\0" /* 3223 */ ++ "OUTPUT_TRIANGLE_CW\0" /* 3235 */ ++ "OUTPUT_TRIANGLE_CCW\0" /* 3254 */ ++ "TOPOLOGY\0" /* 3274 */ ++ "RESERVED_REDUC_AXIS\0" /* 3283 */ ++ "PATCH_MAJOR\0" /* 3303 */ ++ "TF_MAJOR\0" /* 3315 */ ++ "BUFFER_ACCESS_MODE\0" /* 3324 */ ++ "NUM_DS_WAVES_PER_SIMD\0" /* 3343 */ ++ "STENCIL_ENABLE\0" /* 3365 */ ++ "Z_ENABLE\0" /* 3380 */ ++ "Z_WRITE_ENABLE\0" /* 3389 */ ++ "ZFUNC\0" /* 3404 */ ++ "BACKFACE_ENABLE\0" /* 3410 */ ++ "STENCILFUNC_NEVER\0" /* 3426 */ ++ "STENCILFUNC_LESS\0" /* 3444 */ ++ "STENCILFUNC_EQUAL\0" /* 3461 */ ++ "STENCILFUNC_LEQUAL\0" /* 3479 */ ++ "STENCILFUNC_GREATER\0" /* 3498 */ ++ "STENCILFUNC_NOTEQUAL\0" /* 3518 */ ++ "STENCILFUNC_GEQUAL\0" /* 3539 */ ++ "STENCILFUNC_ALWAYS\0" /* 3558 */ ++ "STENCILFUNC\0" /* 3577 */ ++ "STENCIL_KEEP\0" /* 3589 */ ++ "STENCIL_ZERO\0" /* 3602 */ ++ "STENCIL_REPLACE\0" /* 3615 */ ++ "STENCIL_INCR\0" /* 3631 */ ++ "STENCIL_DECR\0" /* 3644 */ ++ "STENCIL_INVERT\0" /* 3657 */ ++ "STENCIL_INCR_WRAP\0" /* 3672 */ ++ "STENCIL_DECR_WRAP\0" /* 3690 */ ++ "STENCILFAIL\0" /* 3708 */ ++ "STENCILZPASS\0" /* 3720 */ ++ "STENCILZFAIL\0" /* 3733 */ ++ "STENCILFUNC_BF\0" /* 3746 */ ++ "STENCILFAIL_BF\0" /* 3761 */ ++ "STENCILZPASS_BF\0" /* 3776 */ ++ "STENCILZFAIL_BF\0" /* 3792 */ ++ "DEGAMMA_ENABLE\0" /* 3808 */ ++ "CB_DISABLE\0" /* 3823 */ ++ "CB_NORMAL\0" /* 3834 */ ++ "CB_ELIMINATE_FAST_CLEAR\0" /* 3844 */ ++ "CB_RESOLVE\0" /* 3868 */ ++ "CB_DECOMPRESS\0" /* 3879 */ ++ "CB_FMASK_DECOMPRESS\0" /* 3893 */ ++ "ROP3\0" /* 3913 */ ++ "UCP_ENA_0\0" /* 3918 */ ++ "UCP_ENA_1\0" /* 3928 */ ++ "UCP_ENA_2\0" /* 3938 */ ++ "UCP_ENA_3\0" /* 3948 */ ++ "UCP_ENA_4\0" /* 3958 */ ++ "UCP_ENA_5\0" /* 3968 */ ++ "PS_UCP_Y_SCALE_NEG\0" /* 3978 */ ++ "PS_UCP_MODE\0" /* 3997 */ ++ "CLIP_DISABLE\0" /* 4009 */ ++ "UCP_CULL_ONLY_ENA\0" /* 4022 */ ++ "BOUNDARY_EDGE_FLAG_ENA\0" /* 4040 */ ++ "DX_CLIP_SPACE_DEF\0" /* 4063 */ ++ "DIS_CLIP_ERR_DETECT\0" /* 4081 */ ++ "VTX_KILL_OR\0" /* 4101 */ ++ "DX_RASTERIZATION_KILL\0" /* 4113 */ ++ "DX_LINEAR_ATTR_CLIP_ENA\0" /* 4135 */ ++ "VTE_VPORT_PROVOKE_DISABLE\0" /* 4159 */ ++ "ZCLIP_NEAR_DISABLE\0" /* 4185 */ ++ "ZCLIP_FAR_DISABLE\0" /* 4204 */ ++ "Z_INVALID\0" /* 4222 */ ++ "Z_16\0" /* 4232 */ ++ "Z_24\0" /* 4237 */ ++ "Z_32_FLOAT\0" /* 4242 */ ++ "READ_SIZE\0" /* 4253 */ ++ "TILE_SURFACE_ENABLE\0" /* 4263 */ ++ "ZRANGE_PRECISION\0" /* 4283 */ ++ "STENCIL_INVALID\0" /* 4300 */ ++ "STENCIL_8\0" /* 4316 */ ++ "HEIGHT_TILE_MAX\0" /* 4326 */ ++ "STENCILREF\0" /* 4342 */ ++ "STENCILMASK\0" /* 4353 */ ++ "STENCILWRITEMASK\0" /* 4365 */ ++ "STENCILREF_BF\0" /* 4382 */ ++ "STENCILMASK_BF\0" /* 4396 */ ++ "STENCILWRITEMASK_BF\0" /* 4411 */ ++ "BLEND_ZERO\0" /* 4431 */ ++ "BLEND_ONE\0" /* 4442 */ ++ "BLEND_SRC_COLOR\0" /* 4452 */ ++ "BLEND_ONE_MINUS_SRC_COLOR\0" /* 4468 */ ++ "BLEND_SRC_ALPHA\0" /* 4494 */ ++ "BLEND_ONE_MINUS_SRC_ALPHA\0" /* 4510 */ ++ "BLEND_DST_ALPHA\0" /* 4536 */ ++ "BLEND_ONE_MINUS_DST_ALPHA\0" /* 4552 */ ++ "BLEND_DST_COLOR\0" /* 4578 */ ++ "BLEND_ONE_MINUS_DST_COLOR\0" /* 4594 */ ++ "BLEND_SRC_ALPHA_SATURATE\0" /* 4620 */ ++ "BLEND_BOTH_SRC_ALPHA\0" /* 4645 */ ++ "BLEND_BOTH_INV_SRC_ALPHA\0" /* 4666 */ ++ "BLEND_CONST_COLOR\0" /* 4691 */ ++ "BLEND_ONE_MINUS_CONST_COLOR\0" /* 4709 */ ++ "BLEND_SRC1_COLOR\0" /* 4737 */ ++ "BLEND_INV_SRC1_COLOR\0" /* 4754 */ ++ "BLEND_SRC1_ALPHA\0" /* 4775 */ ++ "BLEND_INV_SRC1_ALPHA\0" /* 4792 */ ++ "BLEND_CONST_ALPHA\0" /* 4813 */ ++ "BLEND_ONE_MINUS_CONST_ALPHA\0" /* 4831 */ ++ "COLOR_SRCBLEND\0" /* 4859 */ ++ "COMB_DST_PLUS_SRC\0" /* 4874 */ ++ "COMB_SRC_MINUS_DST\0" /* 4892 */ ++ "COMB_MIN_DST_SRC\0" /* 4911 */ ++ "COMB_MAX_DST_SRC\0" /* 4928 */ ++ "COMB_DST_MINUS_SRC\0" /* 4945 */ ++ "COLOR_COMB_FCN\0" /* 4964 */ ++ "COLOR_DESTBLEND\0" /* 4979 */ ++ "OPACITY_WEIGHT\0" /* 4995 */ ++ "ALPHA_SRCBLEND\0" /* 5010 */ ++ "ALPHA_COMB_FCN\0" /* 5025 */ ++ "ALPHA_DESTBLEND\0" /* 5040 */ ++ "SEPARATE_ALPHA_BLEND\0" /* 5056 */ ++ "BLEND_CONTROL_ENABLE\0" /* 5077 */ ++ "CULL_FRONT\0" /* 5098 */ ++ "CULL_BACK\0" /* 5109 */ ++ "FACE\0" /* 5119 */ ++ "POLY_MODE\0" /* 5124 */ ++ "POLYMODE_FRONT_PTYPE\0" /* 5134 */ ++ "POLYMODE_BACK_PTYPE\0" /* 5155 */ ++ "POLY_OFFSET_FRONT_ENABLE\0" /* 5175 */ ++ "POLY_OFFSET_BACK_ENABLE\0" /* 5200 */ ++ "POLY_OFFSET_PARA_ENABLE\0" /* 5224 */ ++ "VTX_WINDOW_OFFSET_ENABLE\0" /* 5248 */ ++ "PROVOKING_VTX_LAST\0" /* 5273 */ ++ "PERSP_CORR_DIS\0" /* 5292 */ ++ "MULTI_PRIM_IB_ENA\0" /* 5307 */ ++ "HTILE_WIDTH\0" /* 5325 */ ++ "HTILE_HEIGHT\0" /* 5337 */ ++ "LINEAR\0" /* 5350 */ ++ "FULL_CACHE\0" /* 5357 */ ++ "HTILE_USES_PRELOAD_WIN\0" /* 5368 */ ++ "PRELOAD\0" /* 5391 */ ++ "PREFETCH_WIDTH\0" /* 5399 */ ++ "PREFETCH_HEIGHT\0" /* 5414 */ ++ "Z_EXPORT_ENABLE\0" /* 5430 */ ++ "STENCIL_EXPORT_ENABLE\0" /* 5446 */ ++ "LATE_Z\0" /* 5468 */ ++ "EARLY_Z_THEN_LATE_Z\0" /* 5475 */ ++ "RE_Z\0" /* 5495 */ ++ "EARLY_Z_THEN_RE_Z\0" /* 5500 */ ++ "Z_ORDER\0" /* 5518 */ ++ "KILL_ENABLE\0" /* 5526 */ ++ "MASK_EXPORT_ENABLE\0" /* 5538 */ ++ "DUAL_EXPORT_ENABLE\0" /* 5557 */ ++ "EXEC_ON_HIER_FAIL\0" /* 5576 */ ++ "EXEC_ON_NOOP\0" /* 5594 */ ++ "EXPORT_DB_FULL\0" /* 5607 */ ++ "EXPORT_DB_FOUR16\0" /* 5622 */ ++ "EXPORT_DB_TWO\0" /* 5639 */ ++ "DB_SOURCE_FORMAT\0" /* 5653 */ ++ "ALPHA_TO_MASK_DISABLE\0" /* 5670 */ ++ "DEPTH_BEFORE_SHADER\0" /* 5692 */ ++ "EXPORT_ANY_Z\0" /* 5712 */ ++ "EXPORT_LESS_THAN_Z\0" /* 5725 */ ++ "EXPORT_GREATER_THAN_Z\0" /* 5744 */ ++ "EXPORT_RESERVED\0" /* 5766 */ ++ "CONSERVATIVE_Z_EXPORT\0" /* 5782 */ ++ "LINE_PATTERN\0" /* 5804 */ ++ "REPEAT_COUNT\0" /* 5817 */ ++ "PATTERN_BIT_ORDER\0" /* 5830 */ ++ "AUTO_RESET_CNTL\0" /* 5848 */ ++ "GS_OFF\0" /* 5864 */ ++ "GS_SCENARIO_A\0" /* 5871 */ ++ "GS_SCENARIO_B\0" /* 5885 */ ++ "GS_SCENARIO_G\0" /* 5899 */ ++ "GS_SCENARIO_C\0" /* 5913 */ ++ "SPRITE_EN\0" /* 5927 */ ++ "ES_PASSTHRU\0" /* 5937 */ ++ "GS_CUT_1024\0" /* 5949 */ ++ "GS_CUT_512\0" /* 5961 */ ++ "GS_CUT_256\0" /* 5972 */ ++ "GS_CUT_128\0" /* 5983 */ ++ "CUT_MODE\0" /* 5994 */ ++ "COMPUTE_MODE\0" /* 6003 */ ++ "PARTIAL_THD_AT_EOI\0" /* 6016 */ ++ "OUTPRIM_TYPE_POINTLIST\0" /* 6035 */ ++ "OUTPRIM_TYPE_LINESTRIP\0" /* 6058 */ ++ "OUTPRIM_TYPE_TRISTRIP\0" /* 6081 */ ++ "OUTPRIM_TYPE\0" /* 6106, 6103 */ ++ "WAIT_CP_DMA_IDLE\0" /* 6116 */ ++ "WAIT_CMDFIFO\0" /* 6133 */ ++ "WAIT_2D_IDLE\0" /* 6146 */ ++ "WAIT_3D_IDLE\0" /* 6159 */ ++ "WAIT_2D_IDLECLEAN\0" /* 6172 */ ++ "WAIT_3D_IDLECLEAN\0" /* 6190 */ ++ "WAIT_EXTERN_SIG\0" /* 6208 */ ++ "CMDFIFO_ENTRIES\0" /* 6224 */ ++ "NUM_INTERP\0" /* 6240 */ ++ "POSITION_ENA\0" /* 6251 */ ++ "POSITION_CENTROID\0" /* 6264 */ ++ "POSITION_ADDR\0" /* 6282 */ ++ "PARAM_GEN\0" /* 6296 */ ++ "PERSP_GRADIENT_ENA\0" /* 6306 */ ++ "LINEAR_GRADIENT_ENA\0" /* 6325 */ ++ "POSITION_SAMPLE\0" /* 6345 */ ++ "FRONT_FACE_ENA\0" /* 6361 */ ++ "FRONT_FACE_CHAN\0" /* 6376 */ ++ "FRONT_FACE_ALL_BITS\0" /* 6392 */ ++ "FRONT_FACE_ADDR\0" /* 6412 */ ++ "FOG_ADDR\0" /* 6428 */ ++ "FIXED_PT_POSITION_ENA\0" /* 6437 */ ++ "FIXED_PT_POSITION_ADDR\0" /* 6459 */ ++ "VS_PER_COMPONENT\0" /* 6482 */ ++ "VS_EXPORT_COUNT\0" /* 6499 */ ++ "VS_EXPORTS_FOG\0" /* 6515 */ ++ "VS_OUT_FOG_VEC_ADDR\0" /* 6530 */ ++ "PERSP_CENTER_ENA\0" /* 6550 */ ++ "PERSP_CENTROID_ENA\0" /* 6567 */ ++ "PERSP_SAMPLE_ENA\0" /* 6586 */ ++ "PERSP_PULL_MODEL_ENA\0" /* 6603 */ ++ "LINEAR_CENTER_ENA\0" /* 6624 */ ++ "LINEAR_CENTROID_ENA\0" /* 6642 */ ++ "LINEAR_SAMPLE_ENA\0" /* 6662 */ ++ "TL_X\0" /* 6680 */ ++ "TL_Y\0" /* 6685 */ ++ "WINDOW_OFFSET_DISABLE\0" /* 6690 */ ++ "BR_X\0" /* 6712 */ ++ "BR_Y\0" /* 6717 */ ++ "SOURCE_SELECT\0" /* 6722 */ ++ "MAJOR_MODE\0" /* 6736 */ ++ "NOT_EOP\0" /* 6747 */ ++ "USE_OPAQUE\0" /* 6755 */ ++ "SQ_TEX_DIM_1D\0" /* 6766 */ ++ "SQ_TEX_DIM_2D\0" /* 6780 */ ++ "SQ_TEX_DIM_3D\0" /* 6794 */ ++ "SQ_TEX_DIM_CUBEMAP\0" /* 6808 */ ++ "SQ_TEX_DIM_1D_ARRAY\0" /* 6827 */ ++ "SQ_TEX_DIM_2D_ARRAY\0" /* 6847 */ ++ "SQ_TEX_DIM_2D_MSAA\0" /* 6867 */ ++ "SQ_TEX_DIM_2D_ARRAY_MSAA\0" /* 6886 */ ++ "DIM\0" /* 6911 */ ++ "PITCH\0" /* 6915 */ ++ "TEX_WIDTH\0" /* 6921 */ ++ "TEX_HEIGHT\0" /* 6931 */ ++ "TEX_DEPTH\0" /* 6942 */ ++ "BASE_ADDRESS\0" /* 6952 */ ++ "MIP_ADDRESS\0" /* 6965 */ ++ "SQ_FORMAT_COMP_UNSIGNED\0" /* 6977 */ ++ "SQ_FORMAT_COMP_SIGNED\0" /* 7001 */ ++ "SQ_FORMAT_COMP_UNSIGNED_BIASED\0" /* 7023 */ ++ "FORMAT_COMP_X\0" /* 7054 */ ++ "FORMAT_COMP_Y\0" /* 7068 */ ++ "FORMAT_COMP_Z\0" /* 7082 */ ++ "FORMAT_COMP_W\0" /* 7096 */ ++ "SQ_NUM_FORMAT_NORM\0" /* 7110 */ ++ "SQ_NUM_FORMAT_INT\0" /* 7129 */ ++ "SQ_NUM_FORMAT_SCALED\0" /* 7147 */ ++ "NUM_FORMAT_ALL\0" /* 7168 */ ++ "SRF_MODE_ZERO_CLAMP_MINUS_ONE\0" /* 7183 */ ++ "SRF_MODE_NO_ZERO\0" /* 7213 */ ++ "SRF_MODE_ALL\0" /* 7230 */ ++ "FORCE_DEGAMMA\0" /* 7243 */ ++ "ENDIAN_SWAP\0" /* 7257 */ ++ "LOG2_NUM_FRAGMENTS\0" /* 7269 */ ++ "SQ_SEL_X\0" /* 7288 */ ++ "SQ_SEL_Y\0" /* 7297 */ ++ "SQ_SEL_Z\0" /* 7306 */ ++ "SQ_SEL_W\0" /* 7315 */ ++ "SQ_SEL_0\0" /* 7324 */ ++ "SQ_SEL_1\0" /* 7333 */ ++ "DST_SEL_X\0" /* 7342 */ ++ "DST_SEL_Y\0" /* 7352 */ ++ "DST_SEL_Z\0" /* 7362 */ ++ "DST_SEL_W\0" /* 7372 */ ++ "BASE_LEVEL\0" /* 7382 */ ++ "LAST_LEVEL\0" /* 7393 */ ++ "BASE_ARRAY\0" /* 7404 */ ++ "LAST_ARRAY\0" /* 7415 */ ++ "MAX_ANISO_RATIO\0" /* 7426 */ ++ "PERF_MODULATION\0" /* 7442 */ ++ "INTERLACED\0" /* 7458 */ ++ "DATA_FORMAT\0" /* 7469 */ ++ "DEPTH_SAMPLE_ORDER\0" /* 7481 */ ++ "SQ_TEX_VTX_INVALID_TEXTURE\0" /* 7500 */ ++ "SQ_TEX_VTX_INVALID_BUFFER\0" /* 7527 */ ++ "SQ_TEX_VTX_VALID_TEXTURE\0" /* 7553 */ ++ "SQ_TEX_VTX_VALID_BUFFER\0" /* 7578 */ ++ "BASE_ADDRESS_HI\0" /* 7602 */ ++ "STRIDE\0" /* 7618 */ ++ "CLAMP_X\0" /* 7625 */ ++ "FORMAT_COMP_ALL\0" /* 7633 */ ++ "UNCACHED\0" /* 7649 */ ++ "SQ_TEX_WRAP\0" /* 7658 */ ++ "SQ_TEX_MIRROR\0" /* 7670 */ ++ "SQ_TEX_CLAMP_LAST_TEXEL\0" /* 7684 */ ++ "SQ_TEX_MIRROR_ONCE_LAST_TEXEL\0" /* 7708 */ ++ "SQ_TEX_CLAMP_HALF_BORDER\0" /* 7738 */ ++ "SQ_TEX_MIRROR_ONCE_HALF_BORDER\0" /* 7763 */ ++ "SQ_TEX_CLAMP_BORDER\0" /* 7794 */ ++ "SQ_TEX_MIRROR_ONCE_BORDER\0" /* 7814 */ ++ "CLAMP_Y\0" /* 7840 */ ++ "CLAMP_Z\0" /* 7848 */ ++ "SQ_TEX_XY_FILTER_POINT\0" /* 7856 */ ++ "SQ_TEX_XY_FILTER_BILINEAR\0" /* 7879 */ ++ "XY_MAG_FILTER\0" /* 7905 */ ++ "XY_MIN_FILTER\0" /* 7919 */ ++ "SQ_TEX_Z_FILTER_NONE\0" /* 7933 */ ++ "SQ_TEX_Z_FILTER_POINT\0" /* 7954 */ ++ "SQ_TEX_Z_FILTER_LINEAR\0" /* 7976 */ ++ "Z_FILTER\0" /* 7999 */ ++ "MIP_FILTER\0" /* 8008 */ ++ "SQ_TEX_BORDER_COLOR_TRANS_BLACK\0" /* 8019 */ ++ "SQ_TEX_BORDER_COLOR_OPAQUE_BLACK\0" /* 8051 */ ++ "SQ_TEX_BORDER_COLOR_OPAQUE_WHITE\0" /* 8084 */ ++ "SQ_TEX_BORDER_COLOR_REGISTER\0" /* 8117 */ ++ "BORDER_COLOR_TYPE\0" /* 8146 */ ++ "SQ_TEX_DEPTH_COMPARE_NEVER\0" /* 8164 */ ++ "SQ_TEX_DEPTH_COMPARE_LESS\0" /* 8191 */ ++ "SQ_TEX_DEPTH_COMPARE_EQUAL\0" /* 8217 */ ++ "SQ_TEX_DEPTH_COMPARE_LESSEQUAL\0" /* 8244 */ ++ "SQ_TEX_DEPTH_COMPARE_GREATER\0" /* 8275 */ ++ "SQ_TEX_DEPTH_COMPARE_NOTEQUAL\0" /* 8304 */ ++ "SQ_TEX_DEPTH_COMPARE_GREATEREQUAL\0" /* 8334 */ ++ "SQ_TEX_DEPTH_COMPARE_ALWAYS\0" /* 8368 */ ++ "DEPTH_COMPARE_FUNCTION\0" /* 8396 */ ++ "SQ_TEX_CHROMA_KEY_DISABLE\0" /* 8419 */ ++ "SQ_TEX_CHROMA_KEY_KILL\0" /* 8445 */ ++ "SQ_TEX_CHROMA_KEY_BLEND\0" /* 8468 */ ++ "CHROMA_KEY\0" /* 8492 */ ++ "MIN_LOD\0" /* 8503 */ ++ "MAX_LOD\0" /* 8511 */ ++ "PERF_MIP\0" /* 8519 */ ++ "PERF_Z\0" /* 8528 */ ++ "LOD_BIAS\0" /* 8535 */ ++ "LOD_BIAS_SEC\0" /* 8544 */ ++ "MC_COORD_TRUNCATE\0" /* 8557 */ ++ "ANISO_BIAS\0" /* 8575 */ ++ "TRUNCATE_COORD\0" /* 8586 */ ++ "DISABLE_CUBE_WRAP\0" /* 8601 */ ++ "DI_PT_NONE\0" /* 8619 */ ++ "DI_PT_POINTLIST\0" /* 8630 */ ++ "DI_PT_LINELIST\0" /* 8646 */ ++ "DI_PT_LINESTRIP\0" /* 8661 */ ++ "DI_PT_TRILIST\0" /* 8677 */ ++ "DI_PT_TRIFAN\0" /* 8691 */ ++ "DI_PT_TRISTRIP\0" /* 8704 */ ++ "DI_PT_UNUSED_0\0" /* 8719 */ ++ "DI_PT_UNUSED_1\0" /* 8734 */ ++ "DI_PT_PATCH\0" /* 8749 */ ++ "DI_PT_LINELIST_ADJ\0" /* 8761 */ ++ "DI_PT_LINESTRIP_ADJ\0" /* 8780 */ ++ "DI_PT_TRILIST_ADJ\0" /* 8800 */ ++ "DI_PT_TRISTRIP_ADJ\0" /* 8818 */ ++ "DI_PT_UNUSED_3\0" /* 8837 */ ++ "DI_PT_UNUSED_4\0" /* 8852 */ ++ "DI_PT_TRI_WITH_WFLAGS\0" /* 8867 */ ++ "DI_PT_RECTLIST\0" /* 8889 */ ++ "DI_PT_LINELOOP\0" /* 8904 */ ++ "DI_PT_QUADLIST\0" /* 8919 */ ++ "DI_PT_QUADSTRIP\0" /* 8934 */ ++ "DI_PT_POLYGON\0" /* 8950 */ ++ "DI_PT_2D_COPY_RECT_LIST_V0\0" /* 8964 */ ++ "DI_PT_2D_COPY_RECT_LIST_V1\0" /* 8991 */ ++ "DI_PT_2D_COPY_RECT_LIST_V2\0" /* 9018 */ ++ "DI_PT_2D_COPY_RECT_LIST_V3\0" /* 9045 */ ++ "DI_PT_2D_FILL_RECT_LIST\0" /* 9072 */ ++ "DI_PT_2D_LINE_STRIP\0" /* 9096 */ ++ "DI_PT_2D_TRI_STRIP\0" /* 9116 */ ++ "CLIP_DIST_ENA_0\0" /* 9135 */ ++ "CLIP_DIST_ENA_1\0" /* 9151 */ ++ "CLIP_DIST_ENA_2\0" /* 9167 */ ++ "CLIP_DIST_ENA_3\0" /* 9183 */ ++ "CLIP_DIST_ENA_4\0" /* 9199 */ ++ "CLIP_DIST_ENA_5\0" /* 9215 */ ++ "CLIP_DIST_ENA_6\0" /* 9231 */ ++ "CLIP_DIST_ENA_7\0" /* 9247 */ ++ "CULL_DIST_ENA_0\0" /* 9263 */ ++ "CULL_DIST_ENA_1\0" /* 9279 */ ++ "CULL_DIST_ENA_2\0" /* 9295 */ ++ "CULL_DIST_ENA_3\0" /* 9311 */ ++ "CULL_DIST_ENA_4\0" /* 9327 */ ++ "CULL_DIST_ENA_5\0" /* 9343 */ ++ "CULL_DIST_ENA_6\0" /* 9359 */ ++ "CULL_DIST_ENA_7\0" /* 9375 */ ++ "USE_VTX_POINT_SIZE\0" /* 9391 */ ++ "USE_VTX_EDGE_FLAG\0" /* 9410 */ ++ "USE_VTX_RENDER_TARGET_INDX\0" /* 9428 */ ++ "USE_VTX_VIEWPORT_INDX\0" /* 9455 */ ++ "USE_VTX_KILL_FLAG\0" /* 9477 */ ++ "VS_OUT_MISC_VEC_ENA\0" /* 9495 */ ++ "VS_OUT_CCDIST0_VEC_ENA\0" /* 9515 */ ++ "VS_OUT_CCDIST1_VEC_ENA\0" /* 9538 */ ++ "NUM_GPRS\0" /* 9561 */ ++ "STACK_SIZE\0" /* 9570 */ ++ "DX10_CLAMP\0" /* 9581 */ ++ "UNCACHED_FIRST_INST\0" /* 9592 */ ++ "ROUND_NEAREST_EVEN\0" /* 9612 */ ++ "ROUND_PLUS_INFINITY\0" /* 9631 */ ++ "ROUND_MINUS_INFINITY\0" /* 9651 */ ++ "ROUND_TO_ZERO\0" /* 9672 */ ++ "SINGLE_ROUND\0" /* 9686 */ ++ "DOUBLE_ROUND\0" /* 9699 */ ++ "ALLOW_SINGLE_DENORM_IN\0" /* 9712 */ ++ "ALLOW_SINGLE_DENORM_OUT\0" /* 9735 */ ++ "ALLOW_DOUBLE_DENORM_IN\0" /* 9759 */ ++ "ALLOW_DOUBLE_DENORM_OUT\0" /* 9782 */ ++ "PRIME_CACHE_ON_DRAW\0" /* 9806 */ ++ "CLAMP_CONSTS\0" /* 9826 */ ++ "SEMANTIC\0" /* 9839 */ ++ "DEFAULT_VAL\0" /* 9848 */ ++ "FLAT_SHADE\0" /* 9860 */ ++ "SEL_CENTROID\0" /* 9871 */ ++ "SEL_LINEAR\0" /* 9884 */ ++ "CYL_WRAP\0" /* 9895 */ ++ "PT_SPRITE_TEX\0" /* 9904 */ ++ "SEL_SAMPLE\0" /* 9918 */ ++ "FLAT_SHADE_ENA\0" /* 9929 */ ++ "PNT_SPRITE_ENA\0" /* 9944 */ ++ "PNT_SPRITE_OVRD_X\0" /* 9959 */ ++ "PNT_SPRITE_OVRD_Y\0" /* 9977 */ ++ "PNT_SPRITE_OVRD_Z\0" /* 9995 */ ++ "PNT_SPRITE_OVRD_W\0" /* 10013 */ ++ "PNT_SPRITE_TOP_1\0" /* 10031 */ ++ "DEPTH_CLEAR_ENABLE\0" /* 10048 */ ++ "STENCIL_CLEAR_ENABLE\0" /* 10067 */ ++ "DEPTH_COPY_ENABLE\0" /* 10088 */ ++ "STENCIL_COPY_ENABLE\0" /* 10106 */ ++ "RESUMMARIZE_ENABLE\0" /* 10126 */ ++ "STENCIL_COMPRESS_DISABLE\0" /* 10145 */ ++ "DEPTH_COMPRESS_DISABLE\0" /* 10170 */ ++ "COPY_CENTROID\0" /* 10193 */ ++ "COPY_SAMPLE\0" /* 10207 */ ++ "COLOR_DISABLE\0" /* 10219 */ ++ "ZPASS_INCREMENT_DISABLE\0" /* 10233 */ ++ "PERFECT_ZPASS_COUNTS\0" /* 10257 */ ++ "SAMPLE_RATE\0" /* 10278 */ ++ "SLICE_START\0" /* 10290 */ ++ "FORCE_OFF\0" /* 10302 */ ++ "FORCE_ENABLE\0" /* 10312 */ ++ "FORCE_DISABLE\0" /* 10325 */ ++ "SLICE_MAX\0" /* 10339 */ ++ "FORCE_HIZ_ENABLE\0" /* 10349 */ ++ "FORCE_HIS_ENABLE0\0" /* 10366 */ ++ "FORCE_HIS_ENABLE1\0" /* 10384 */ ++ "FORCE_SHADER_Z_ORDER\0" /* 10402 */ ++ "FAST_Z_DISABLE\0" /* 10423 */ ++ "FAST_STENCIL_DISABLE\0" /* 10438 */ ++ "NOOP_CULL_DISABLE\0" /* 10459 */ ++ "FORCE_COLOR_KILL\0" /* 10477 */ ++ "FORCE_Z_READ\0" /* 10494 */ ++ "FORCE_STENCIL_READ\0" /* 10507 */ ++ "FORCE_FULL_Z_RANGE\0" /* 10526 */ ++ "FORCE_QC_SMASK_CONFLICT\0" /* 10545 */ ++ "DISABLE_VIEWPORT_CLAMP\0" /* 10569 */ ++ "IGNORE_SC_ZRANGE\0" /* 10592 */ ++ "DISABLE_PIXEL_RATE_TILES\0" /* 10609 */ ++ "MULTIPASS\0" /* 10634 */ ++ "SURFACE_SYNC_MASK\0" /* 10644 */ ++ "PROVIDE_Z_TO_SPI\0" /* 10662 */ ++ "TID_IN_GROUP_ENA\0" /* 10679 */ ++ "TGID_ENA\0" /* 10696 */ ++ "DISABLE_INDEX_PACK\0" /* 10705 */ ++ "VPORT_X_SCALE_ENA\0" /* 10724 */ ++ "VPORT_X_OFFSET_ENA\0" /* 10742 */ ++ "VPORT_Y_SCALE_ENA\0" /* 10761 */ ++ "VPORT_Y_OFFSET_ENA\0" /* 10779 */ ++ "VPORT_Z_SCALE_ENA\0" /* 10798 */ ++ "VPORT_Z_OFFSET_ENA\0" /* 10816 */ ++ "VTX_XY_FMT\0" /* 10835 */ ++ "VTX_Z_FMT\0" /* 10846 */ ++ "VTX_W0_FMT\0" /* 10856 */ ++ "EXPORT_COLORS\0" /* 10867 */ ++ "EXPORT_Z\0" /* 10881 */ ++ "MIN_SIZE\0" /* 10890 */ ++ "MAX_SIZE\0" /* 10899 */ ++ "MSAA_ENABLE\0" /* 10908 */ ++ "VPORT_SCISSOR_ENABLE\0" /* 10920 */ ++ "LINE_STIPPLE_ENABLE\0" /* 10941 */ ++ "PRIMITIVEID_EN\0" /* 10961 */ ++ "RESET_EN\0" /* 10976 */ ++ "MAX_X\0" /* 10985 */ ++ "MAX_Y\0" /* 10991 */ ++ "MAX_VERT_OUT\0" /* 10997 */ ++ "LS_STAGE_OFF\0" /* 11010 */ ++ "LS_STAGE_ON\0" /* 11023 */ ++ "CS_STAGE_ON\0" /* 11035 */ ++ "LS_EN\0" /* 11047 */ ++ "HS_EN\0" /* 11053 */ ++ "ES_STAGE_OFF\0" /* 11059 */ ++ "ES_STAGE_DS\0" /* 11072 */ ++ "ES_STAGE_REAL\0" /* 11084 */ ++ "ES_EN\0" /* 11098 */ ++ "GS_EN\0" /* 11104 */ ++ "VS_STAGE_REAL\0" /* 11110 */ ++ "VS_STAGE_DS\0" /* 11124 */ ++ "VS_STAGE_COPY_SHADER\0" /* 11136 */ ++ "VS_EN\0" /* 11157 */ ++ "NUM_PATCHES\0" /* 11163 */ ++ "HS_NUM_INPUT_CP\0" /* 11175 */ ++ "HS_NUM_OUTPUT_CP\0" /* 11191 */ ++ "PATCH_CP_SIZE\0" /* 11208 */ ++ "HS_TOTAL_OUTPUT\0" /* 11222 */ ++ "LS_HS_TOTAL_OUTPUT\0" /* 11238 */ ++ "ALPHA_TO_MASK_ENABLE\0" /* 11257 */ ++ "ALPHA_TO_MASK_OFFSET0\0" /* 11278 */ ++ "ALPHA_TO_MASK_OFFSET1\0" /* 11300 */ ++ "ALPHA_TO_MASK_OFFSET2\0" /* 11322 */ ++ "ALPHA_TO_MASK_OFFSET3\0" /* 11344 */ ++ "OFFSET_ROUND\0" /* 11366 */ ++ "POLY_OFFSET_NEG_NUM_DB_BITS\0" /* 11379 */ ++ "POLY_OFFSET_DB_IS_FLOAT_FMT\0" /* 11407 */ ++ "SCALE\0" /* 11435 */ ++ "OFFSET\0" /* 11441 */ ++ "PIX_CENTER_HALF\0" /* 11448 */ ++ "X_1_16TH\0" /* 11464 */ ++ "X_1_8TH\0" /* 11473 */ ++ "X_1_4TH\0" /* 11481 */ ++ "X_1_2\0" /* 11489 */ ++ "X_1\0" /* 11495 */ ++ "X_1_256TH\0" /* 11499 */ ++ "X_1_1024TH\0" /* 11509 */ ++ "X_1_4096TH\0" /* 11520 */ ++ "QUANT_MODE\0" /* 11531 */ ++ "DEST_BASE_0_ENA\0" /* 11542 */ ++ "DEST_BASE_1_ENA\0" /* 11558 */ ++ "SO0_DEST_BASE_ENA\0" /* 11574 */ ++ "SO1_DEST_BASE_ENA\0" /* 11592 */ ++ "SO2_DEST_BASE_ENA\0" /* 11610 */ ++ "SO3_DEST_BASE_ENA\0" /* 11628 */ ++ "CB0_DEST_BASE_ENA\0" /* 11646 */ ++ "CB1_DEST_BASE_ENA\0" /* 11664 */ ++ "CB2_DEST_BASE_ENA\0" /* 11682 */ ++ "CB3_DEST_BASE_ENA\0" /* 11700 */ ++ "CB4_DEST_BASE_ENA\0" /* 11718 */ ++ "CB5_DEST_BASE_ENA\0" /* 11736 */ ++ "CB6_DEST_BASE_ENA\0" /* 11754 */ ++ "CB7_DEST_BASE_ENA\0" /* 11772 */ ++ "DB_DEST_BASE_ENA\0" /* 11790 */ ++ "CB8_DEST_BASE_ENA\0" /* 11807 */ ++ "CB9_DEST_BASE_ENA\0" /* 11825 */ ++ "CB10_DEST_BASE_ENA\0" /* 11843 */ ++ "CB11_DEST_BASE_ENA\0" /* 11862 */ ++ "TC_ACTION_ENA\0" /* 11881 */ ++ "VC_ACTION_ENA\0" /* 11895 */ ++ "CB_ACTION_ENA\0" /* 11909 */ ++ "DB_ACTION_ENA\0" /* 11923 */ ++ "SH_ACTION_ENA\0" /* 11937 */ ++ "SMX_ACTION_ENA\0" /* 11951 */ ++ "CR0_ACTION_ENA\0" /* 11966 */ ++ "CR1_ACTION_ENA\0" /* 11981 */ ++ "CR2_ACTION_ENA\0" /* 11996 */ ++ "PRIMGROUP_SIZE\0" /* 12011 */ ++ "PARTIAL_VS_WAVE_ON\0" /* 12026 */ ++ "SWITCH_ON_EOP\0" /* 12045 */ ++ "CP_STRMOUT_CNTL\0" /* 12059 */ ++ "VGT_STRMOUT_CONFIG\0" /* 12075 */ ++ "VGT_STRMOUT_BUFFER_CONFIG\0" /* 12094 */ ++ "VGT_STRMOUT_BUFFER_FILLED_SIZE_0\0" /* 12120 */ ++ "VGT_STRMOUT_BUFFER_FILLED_SIZE_1\0" /* 12153 */ ++ "VGT_STRMOUT_BUFFER_FILLED_SIZE_2\0" /* 12186 */ ++ "VGT_STRMOUT_BUFFER_FILLED_SIZE_3\0" /* 12219 */ ++ "SQ_CONFIG\0" /* 12252 */ ++ "SQ_GPR_RESOURCE_MGMT_1\0" /* 12262 */ ++ "SQ_GPR_RESOURCE_MGMT_2\0" /* 12285 */ ++ "SQ_GPR_RESOURCE_MGMT_3\0" /* 12308 */ ++ "SQ_GLOBAL_GPR_RESOURCE_MGMT_1\0" /* 12331 */ ++ "SQ_GLOBAL_GPR_RESOURCE_MGMT_2\0" /* 12361 */ ++ "SQ_THREAD_RESOURCE_MGMT_1\0" /* 12391 */ ++ "SQ_THREAD_RESOURCE_MGMT_2\0" /* 12417 */ ++ "SQ_STACK_RESOURCE_MGMT_1\0" /* 12443 */ ++ "SQ_STACK_RESOURCE_MGMT_2\0" /* 12468 */ ++ "SQ_STACK_RESOURCE_MGMT_3\0" /* 12493 */ ++ "SQ_LDS_RESOURCE_MGMT\0" /* 12518 */ ++ "SQ_ESGS_RING_BASE\0" /* 12539 */ ++ "SQ_ESGS_RING_SIZE\0" /* 12557 */ ++ "SQ_GSVS_RING_BASE\0" /* 12575 */ ++ "SQ_GSVS_RING_SIZE\0" /* 12593 */ ++ "SQ_MS_FIFO_SIZES\0" /* 12611 */ ++ "SQ_STATIC_THREAD_MGMT1\0" /* 12628 */ ++ "SQ_STATIC_THREAD_MGMT2\0" /* 12651 */ ++ "SQ_STATIC_THREAD_MGMT3\0" /* 12674 */ ++ "VGT_COMPUTE_START_X\0" /* 12697 */ ++ "VGT_COMPUTE_START_Y\0" /* 12717 */ ++ "VGT_COMPUTE_START_Z\0" /* 12737 */ ++ "VGT_COMPUTE_THREAD_GROUP_SIZE\0" /* 12757 */ ++ "SPI_CONFIG_CNTL\0" /* 12787 */ ++ "SPI_CONFIG_CNTL_1\0" /* 12803 */ ++ "CB_COLOR0_PITCH\0" /* 12821 */ ++ "CB_COLOR0_SLICE\0" /* 12837 */ ++ "CB_COLOR0_INFO\0" /* 12853 */ ++ "CB_COLOR0_ATTRIB\0" /* 12868 */ ++ "CB_COLOR0_DIM\0" /* 12885 */ ++ "SX_ALPHA_TEST_CONTROL\0" /* 12899 */ ++ "SPI_COMPUTE_NUM_THREAD_X\0" /* 12921 */ ++ "SPI_COMPUTE_NUM_THREAD_Y\0" /* 12946 */ ++ "SPI_COMPUTE_NUM_THREAD_Z\0" /* 12971 */ ++ "VGT_TF_PARAM\0" /* 12996 */ ++ "VGT_DISPATCH_INITIATOR\0" /* 13009 */ ++ "DB_DEPTH_CONTROL\0" /* 13032 */ ++ "CB_COLOR_CONTROL\0" /* 13049 */ ++ "PA_CL_CLIP_CNTL\0" /* 13066 */ ++ "DB_Z_INFO\0" /* 13082 */ ++ "DB_STENCIL_INFO\0" /* 13092 */ ++ "DB_DEPTH_SIZE\0" /* 13108 */ ++ "DB_DEPTH_SLICE\0" /* 13122 */ ++ "DB_STENCILREFMASK\0" /* 13137 */ ++ "DB_STENCILREFMASK_BF\0" /* 13155 */ ++ "CB_BLEND0_CONTROL\0" /* 13176 */ ++ "PA_SU_SC_MODE_CNTL\0" /* 13194 */ ++ "DB_HTILE_SURFACE\0" /* 13213 */ ++ "DB_SHADER_CONTROL\0" /* 13230 */ ++ "PA_SU_POINT_SIZE\0" /* 13248 */ ++ "PA_SC_LINE_STIPPLE\0" /* 13265 */ ++ "VGT_GS_MODE\0" /* 13284 */ ++ "VGT_GS_OUT_PRIM_TYPE\0" /* 13296 */ ++ "WAIT_UNTIL\0" /* 13317 */ ++ "SPI_PS_IN_CONTROL_0\0" /* 13328 */ ++ "SPI_PS_IN_CONTROL_1\0" /* 13348 */ ++ "SPI_VS_OUT_CONFIG\0" /* 13368 */ ++ "SPI_BARYC_CNTL\0" /* 13386 */ ++ "PA_SC_VPORT_SCISSOR_0_TL\0" /* 13401 */ ++ "PA_SC_VPORT_SCISSOR_0_BR\0" /* 13426 */ ++ "PA_SC_GENERIC_SCISSOR_TL\0" /* 13451 */ ++ "PA_SC_GENERIC_SCISSOR_BR\0" /* 13476 */ ++ "PA_SC_SCREEN_SCISSOR_TL\0" /* 13501 */ ++ "PA_SC_SCREEN_SCISSOR_BR\0" /* 13525 */ ++ "PA_SC_WINDOW_SCISSOR_TL\0" /* 13549 */ ++ "PA_SC_WINDOW_SCISSOR_BR\0" /* 13573 */ ++ "VGT_DMA_MAX_SIZE\0" /* 13597 */ ++ "VGT_DMA_INDEX_TYPE\0" /* 13614 */ ++ "VGT_NUM_INSTANCES\0" /* 13633 */ ++ "VGT_DMA_BASE_HI\0" /* 13651 */ ++ "VGT_DMA_BASE\0" /* 13667 */ ++ "VGT_DRAW_INITIATOR\0" /* 13680 */ ++ "SQ_TEX_RESOURCE_WORD0_0\0" /* 13699 */ ++ "SQ_TEX_RESOURCE_WORD1_0\0" /* 13723 */ ++ "SQ_TEX_RESOURCE_WORD2_0\0" /* 13747 */ ++ "SQ_TEX_RESOURCE_WORD3_0\0" /* 13771 */ ++ "SQ_TEX_RESOURCE_WORD4_0\0" /* 13795 */ ++ "SQ_TEX_RESOURCE_WORD5_0\0" /* 13819 */ ++ "SQ_TEX_RESOURCE_WORD6_0\0" /* 13843 */ ++ "SQ_TEX_RESOURCE_WORD7_0\0" /* 13867 */ ++ "SQ_VTX_CONSTANT_WORD2_0\0" /* 13891 */ ++ "SQ_VTX_CONSTANT_WORD3_0\0" /* 13915 */ ++ "TD_PS_SAMPLER0_BORDER_INDEX\0" /* 13939 */ ++ "TD_PS_SAMPLER0_BORDER_RED\0" /* 13967 */ ++ "TD_PS_SAMPLER0_BORDER_GREEN\0" /* 13993 */ ++ "TD_PS_SAMPLER0_BORDER_BLUE\0" /* 14021 */ ++ "TD_PS_SAMPLER0_BORDER_ALPHA\0" /* 14048 */ ++ "TD_VS_SAMPLER0_BORDER_INDEX\0" /* 14076 */ ++ "TD_VS_SAMPLER0_BORDER_RED\0" /* 14104 */ ++ "TD_VS_SAMPLER0_BORDER_GREEN\0" /* 14130 */ ++ "TD_VS_SAMPLER0_BORDER_BLUE\0" /* 14158 */ ++ "TD_VS_SAMPLER0_BORDER_ALPHA\0" /* 14185 */ ++ "TD_GS_SAMPLER0_BORDER_INDEX\0" /* 14213 */ ++ "TD_GS_SAMPLER0_BORDER_RED\0" /* 14241 */ ++ "TD_GS_SAMPLER0_BORDER_GREEN\0" /* 14267 */ ++ "TD_GS_SAMPLER0_BORDER_BLUE\0" /* 14295 */ ++ "TD_GS_SAMPLER0_BORDER_ALPHA\0" /* 14322 */ ++ "TD_HS_SAMPLER0_BORDER_COLOR_INDEX\0" /* 14350 */ ++ "TD_HS_SAMPLER0_BORDER_COLOR_RED\0" /* 14384 */ ++ "TD_HS_SAMPLER0_BORDER_COLOR_GREEN\0" /* 14416 */ ++ "TD_HS_SAMPLER0_BORDER_COLOR_BLUE\0" /* 14450 */ ++ "TD_HS_SAMPLER0_BORDER_COLOR_ALPHA\0" /* 14483 */ ++ "TD_LS_SAMPLER0_BORDER_COLOR_INDEX\0" /* 14517 */ ++ "TD_LS_SAMPLER0_BORDER_COLOR_RED\0" /* 14551 */ ++ "TD_LS_SAMPLER0_BORDER_COLOR_GREEN\0" /* 14583 */ ++ "TD_LS_SAMPLER0_BORDER_COLOR_BLUE\0" /* 14617 */ ++ "TD_LS_SAMPLER0_BORDER_COLOR_ALPHA\0" /* 14650 */ ++ "TD_CS_SAMPLER0_BORDER_INDEX\0" /* 14684 */ ++ "TD_CS_SAMPLER0_BORDER_RED\0" /* 14712 */ ++ "TD_CS_SAMPLER0_BORDER_GREEN\0" /* 14738 */ ++ "TD_CS_SAMPLER0_BORDER_BLUE\0" /* 14766 */ ++ "TD_CS_SAMPLER0_BORDER_ALPHA\0" /* 14793 */ ++ "SQ_TEX_SAMPLER_WORD0_0\0" /* 14821 */ ++ "SQ_TEX_SAMPLER_WORD1_0\0" /* 14844 */ ++ "SQ_TEX_SAMPLER_WORD2_0\0" /* 14867 */ ++ "VGT_PRIMITIVE_TYPE\0" /* 14890 */ ++ "PA_CL_VS_OUT_CNTL\0" /* 14909 */ ++ "SQ_PGM_RESOURCES_VS\0" /* 14927 */ ++ "SQ_PGM_RESOURCES_GS\0" /* 14947 */ ++ "SQ_PGM_RESOURCES_2_GS\0" /* 14967 */ ++ "SQ_PGM_RESOURCES_ES\0" /* 14989 */ ++ "SQ_PGM_RESOURCES_2_ES\0" /* 15009 */ ++ "SQ_PGM_RESOURCES_2_VS\0" /* 15031 */ ++ "SQ_PGM_RESOURCES_PS\0" /* 15053 */ ++ "SQ_PGM_RESOURCES_2_PS\0" /* 15073 */ ++ "SQ_PGM_RESOURCES_HS\0" /* 15095 */ ++ "SQ_PGM_RESOURCES_2_HS\0" /* 15115 */ ++ "SQ_PGM_RESOURCES_LS\0" /* 15137 */ ++ "SQ_PGM_RESOURCES_2_LS\0" /* 15157 */ ++ "SPI_PS_INPUT_CNTL_0\0" /* 15179 */ ++ "SPI_INTERP_CONTROL_0\0" /* 15199 */ ++ "PA_CL_ENHANCE\0" /* 15220 */ ++ "SQ_DYN_GPR_CNTL_PS_FLUSH_REQ\0" /* 15234 */ ++ "DB_RENDER_CONTROL\0" /* 15263 */ ++ "DB_COUNT_CONTROL\0" /* 15281 */ ++ "DB_DEPTH_VIEW\0" /* 15298 */ ++ "DB_RENDER_OVERRIDE\0" /* 15312 */ ++ "DB_RENDER_OVERRIDE2\0" /* 15331 */ ++ "DB_HTILE_DATA_BASE\0" /* 15351 */ ++ "DB_STENCIL_CLEAR\0" /* 15370 */ ++ "DB_DEPTH_CLEAR\0" /* 15387 */ ++ "DB_Z_READ_BASE\0" /* 15402 */ ++ "DB_STENCIL_READ_BASE\0" /* 15417 */ ++ "DB_Z_WRITE_BASE\0" /* 15438 */ ++ "DB_STENCIL_WRITE_BASE\0" /* 15454 */ ++ "ALU_CONST_BUFFER_SIZE_PS_0\0" /* 15476 */ ++ "ALU_CONST_BUFFER_SIZE_PS_1\0" /* 15503 */ ++ "ALU_CONST_BUFFER_SIZE_VS_0\0" /* 15530 */ ++ "ALU_CONST_BUFFER_SIZE_VS_1\0" /* 15557 */ ++ "ALU_CONST_BUFFER_SIZE_GS_0\0" /* 15584 */ ++ "ALU_CONST_BUFFER_SIZE_HS_0\0" /* 15611 */ ++ "ALU_CONST_BUFFER_SIZE_LS_0\0" /* 15638 */ ++ "PA_SC_WINDOW_OFFSET\0" /* 15665 */ ++ "PA_SC_CLIPRECT_RULE\0" /* 15685 */ ++ "PA_SC_CLIPRECT_0_TL\0" /* 15705 */ ++ "PA_SC_CLIPRECT_0_BR\0" /* 15725 */ ++ "PA_SC_CLIPRECT_1_TL\0" /* 15745 */ ++ "PA_SC_CLIPRECT_1_BR\0" /* 15765 */ ++ "PA_SC_CLIPRECT_2_TL\0" /* 15785 */ ++ "PA_SC_CLIPRECT_2_BR\0" /* 15805 */ ++ "PA_SC_CLIPRECT_3_TL\0" /* 15825 */ ++ "PA_SC_CLIPRECT_3_BR\0" /* 15845 */ ++ "PA_SC_EDGERULE\0" /* 15865 */ ++ "PA_SU_HARDWARE_SCREEN_OFFSET\0" /* 15880 */ ++ "CB_TARGET_MASK\0" /* 15909 */ ++ "CB_SHADER_MASK\0" /* 15924 */ ++ "SX_MISC\0" /* 15939 */ ++ "SX_SURFACE_SYNC\0" /* 15947 */ ++ "SQ_VTX_SEMANTIC_0\0" /* 15963 */ ++ "SQ_VTX_SEMANTIC_1\0" /* 15981 */ ++ "SQ_VTX_SEMANTIC_2\0" /* 15999 */ ++ "SQ_VTX_SEMANTIC_3\0" /* 16017 */ ++ "SQ_VTX_SEMANTIC_4\0" /* 16035 */ ++ "SQ_VTX_SEMANTIC_5\0" /* 16053 */ ++ "SQ_VTX_SEMANTIC_6\0" /* 16071 */ ++ "SQ_VTX_SEMANTIC_7\0" /* 16089 */ ++ "SQ_VTX_SEMANTIC_8\0" /* 16107 */ ++ "SQ_VTX_SEMANTIC_9\0" /* 16125 */ ++ "SQ_VTX_SEMANTIC_10\0" /* 16143 */ ++ "SQ_VTX_SEMANTIC_11\0" /* 16162 */ ++ "SQ_VTX_SEMANTIC_12\0" /* 16181 */ ++ "SQ_VTX_SEMANTIC_13\0" /* 16200 */ ++ "SQ_VTX_SEMANTIC_14\0" /* 16219 */ ++ "SQ_VTX_SEMANTIC_15\0" /* 16238 */ ++ "SQ_VTX_SEMANTIC_16\0" /* 16257 */ ++ "SQ_VTX_SEMANTIC_17\0" /* 16276 */ ++ "SQ_VTX_SEMANTIC_18\0" /* 16295 */ ++ "SQ_VTX_SEMANTIC_19\0" /* 16314 */ ++ "SQ_VTX_SEMANTIC_20\0" /* 16333 */ ++ "SQ_VTX_SEMANTIC_21\0" /* 16352 */ ++ "SQ_VTX_SEMANTIC_22\0" /* 16371 */ ++ "SQ_VTX_SEMANTIC_23\0" /* 16390 */ ++ "SQ_VTX_SEMANTIC_24\0" /* 16409 */ ++ "SQ_VTX_SEMANTIC_25\0" /* 16428 */ ++ "SQ_VTX_SEMANTIC_26\0" /* 16447 */ ++ "SQ_VTX_SEMANTIC_27\0" /* 16466 */ ++ "SQ_VTX_SEMANTIC_28\0" /* 16485 */ ++ "SQ_VTX_SEMANTIC_29\0" /* 16504 */ ++ "SQ_VTX_SEMANTIC_30\0" /* 16523 */ ++ "SQ_VTX_SEMANTIC_31\0" /* 16542 */ ++ "SQ_VTX_SEMANTIC_CLEAR\0" /* 16561 */ ++ "PA_SC_VPORT_ZMIN_0\0" /* 16583 */ ++ "PA_SC_VPORT_ZMAX_0\0" /* 16602 */ ++ "VGT_MAX_VTX_INDX\0" /* 16621 */ ++ "VGT_MIN_VTX_INDX\0" /* 16638 */ ++ "VGT_INDX_OFFSET\0" /* 16655 */ ++ "VGT_MULTI_PRIM_IB_RESET_INDX\0" /* 16671 */ ++ "CB_BLEND_RED\0" /* 16700 */ ++ "CB_BLEND_GREEN\0" /* 16713 */ ++ "CB_BLEND_BLUE\0" /* 16728 */ ++ "CB_BLEND_ALPHA\0" /* 16742 */ ++ "SX_ALPHA_REF\0" /* 16757 */ ++ "PA_CL_VPORT_XSCALE_0\0" /* 16770 */ ++ "PA_CL_VPORT_XOFFSET_0\0" /* 16791 */ ++ "PA_CL_VPORT_YSCALE_0\0" /* 16813 */ ++ "PA_CL_VPORT_YOFFSET_0\0" /* 16834 */ ++ "PA_CL_VPORT_ZSCALE_0\0" /* 16856 */ ++ "PA_CL_VPORT_ZOFFSET_0\0" /* 16877 */ ++ "PA_CL_UCP0_X\0" /* 16899 */ ++ "PA_CL_UCP0_Y\0" /* 16912 */ ++ "PA_CL_UCP0_Z\0" /* 16925 */ ++ "PA_CL_UCP0_W\0" /* 16938 */ ++ "PA_CL_UCP1_X\0" /* 16951 */ ++ "PA_CL_UCP1_Y\0" /* 16964 */ ++ "PA_CL_UCP1_Z\0" /* 16977 */ ++ "PA_CL_UCP1_W\0" /* 16990 */ ++ "PA_CL_UCP2_X\0" /* 17003 */ ++ "PA_CL_UCP2_Y\0" /* 17016 */ ++ "PA_CL_UCP2_Z\0" /* 17029 */ ++ "PA_CL_UCP2_W\0" /* 17042 */ ++ "PA_CL_UCP3_X\0" /* 17055 */ ++ "PA_CL_UCP3_Y\0" /* 17068 */ ++ "PA_CL_UCP3_Z\0" /* 17081 */ ++ "PA_CL_UCP3_W\0" /* 17094 */ ++ "PA_CL_UCP4_X\0" /* 17107 */ ++ "PA_CL_UCP4_Y\0" /* 17120 */ ++ "PA_CL_UCP4_Z\0" /* 17133 */ ++ "PA_CL_UCP4_W\0" /* 17146 */ ++ "PA_CL_UCP5_X\0" /* 17159 */ ++ "PA_CL_UCP5_Y\0" /* 17172 */ ++ "PA_CL_UCP5_Z\0" /* 17185 */ ++ "PA_CL_UCP5_W\0" /* 17198 */ ++ "SPI_VS_OUT_ID_0\0" /* 17211 */ ++ "SPI_VS_OUT_ID_1\0" /* 17227 */ ++ "SPI_VS_OUT_ID_2\0" /* 17243 */ ++ "SPI_VS_OUT_ID_3\0" /* 17259 */ ++ "SPI_VS_OUT_ID_4\0" /* 17275 */ ++ "SPI_VS_OUT_ID_5\0" /* 17291 */ ++ "SPI_VS_OUT_ID_6\0" /* 17307 */ ++ "SPI_VS_OUT_ID_7\0" /* 17323 */ ++ "SPI_VS_OUT_ID_8\0" /* 17339 */ ++ "SPI_VS_OUT_ID_9\0" /* 17355 */ ++ "SPI_PS_INPUT_CNTL_1\0" /* 17371 */ ++ "SPI_PS_INPUT_CNTL_2\0" /* 17391 */ ++ "SPI_PS_INPUT_CNTL_3\0" /* 17411 */ ++ "SPI_PS_INPUT_CNTL_4\0" /* 17431 */ ++ "SPI_PS_INPUT_CNTL_5\0" /* 17451 */ ++ "SPI_PS_INPUT_CNTL_6\0" /* 17471 */ ++ "SPI_PS_INPUT_CNTL_7\0" /* 17491 */ ++ "SPI_PS_INPUT_CNTL_8\0" /* 17511 */ ++ "SPI_PS_INPUT_CNTL_9\0" /* 17531 */ ++ "SPI_PS_INPUT_CNTL_10\0" /* 17551 */ ++ "SPI_PS_INPUT_CNTL_11\0" /* 17572 */ ++ "SPI_PS_INPUT_CNTL_12\0" /* 17593 */ ++ "SPI_PS_INPUT_CNTL_13\0" /* 17614 */ ++ "SPI_PS_INPUT_CNTL_14\0" /* 17635 */ ++ "SPI_PS_INPUT_CNTL_15\0" /* 17656 */ ++ "SPI_PS_INPUT_CNTL_16\0" /* 17677 */ ++ "SPI_PS_INPUT_CNTL_17\0" /* 17698 */ ++ "SPI_PS_INPUT_CNTL_18\0" /* 17719 */ ++ "SPI_PS_INPUT_CNTL_19\0" /* 17740 */ ++ "SPI_PS_INPUT_CNTL_20\0" /* 17761 */ ++ "SPI_PS_INPUT_CNTL_21\0" /* 17782 */ ++ "SPI_PS_INPUT_CNTL_22\0" /* 17803 */ ++ "SPI_PS_INPUT_CNTL_23\0" /* 17824 */ ++ "SPI_PS_INPUT_CNTL_24\0" /* 17845 */ ++ "SPI_PS_INPUT_CNTL_25\0" /* 17866 */ ++ "SPI_PS_INPUT_CNTL_26\0" /* 17887 */ ++ "SPI_PS_INPUT_CNTL_27\0" /* 17908 */ ++ "SPI_PS_INPUT_CNTL_28\0" /* 17929 */ ++ "SPI_PS_INPUT_CNTL_29\0" /* 17950 */ ++ "SPI_PS_INPUT_CNTL_30\0" /* 17971 */ ++ "SPI_PS_INPUT_CNTL_31\0" /* 17992 */ ++ "SPI_THREAD_GROUPING\0" /* 18013 */ ++ "SPI_INPUT_Z\0" /* 18033 */ ++ "SPI_FOG_CNTL\0" /* 18045 */ ++ "SPI_PS_IN_CONTROL_2\0" /* 18058 */ ++ "SPI_COMPUTE_INPUT_CNTL\0" /* 18078 */ ++ "GDS_ADDR_BASE\0" /* 18101 */ ++ "GDS_ADDR_SIZE\0" /* 18115 */ ++ "GDS_ORDERED_WAVE_PER_SE\0" /* 18129 */ ++ "GDS_APPEND_COUNT_0\0" /* 18153 */ ++ "GDS_APPEND_COUNT_1\0" /* 18172 */ ++ "GDS_APPEND_COUNT_2\0" /* 18191 */ ++ "GDS_APPEND_COUNT_3\0" /* 18210 */ ++ "GDS_APPEND_COUNT_4\0" /* 18229 */ ++ "GDS_APPEND_COUNT_5\0" /* 18248 */ ++ "GDS_APPEND_COUNT_6\0" /* 18267 */ ++ "GDS_APPEND_COUNT_7\0" /* 18286 */ ++ "GDS_APPEND_COUNT_8\0" /* 18305 */ ++ "GDS_APPEND_COUNT_9\0" /* 18324 */ ++ "GDS_APPEND_COUNT_10\0" /* 18343 */ ++ "GDS_APPEND_COUNT_11\0" /* 18363 */ ++ "CB_BLEND1_CONTROL\0" /* 18383 */ ++ "CB_BLEND2_CONTROL\0" /* 18401 */ ++ "CB_BLEND3_CONTROL\0" /* 18419 */ ++ "CB_BLEND4_CONTROL\0" /* 18437 */ ++ "CB_BLEND5_CONTROL\0" /* 18455 */ ++ "CB_BLEND6_CONTROL\0" /* 18473 */ ++ "CB_BLEND7_CONTROL\0" /* 18491 */ ++ "PA_CL_VTE_CNTL\0" /* 18509 */ ++ "PA_CL_NANINF_CNTL\0" /* 18524 */ ++ "SQ_LSTMP_RING_ITEMSIZE\0" /* 18542 */ ++ "SQ_DYN_GPR_RESOURCE_LIMIT_1\0" /* 18565 */ ++ "SQ_PGM_START_PS\0" /* 18593 */ ++ "SQ_PGM_EXPORTS_PS\0" /* 18609 */ ++ "SQ_PGM_START_VS\0" /* 18627 */ ++ "SQ_PGM_START_GS\0" /* 18643 */ ++ "SQ_PGM_START_ES\0" /* 18659 */ ++ "SQ_PGM_START_FS\0" /* 18675 */ ++ "SQ_PGM_START_HS\0" /* 18691 */ ++ "SQ_PGM_START_LS\0" /* 18707 */ ++ "SQ_PGM_RESOURCES_FS\0" /* 18723 */ ++ "SQ_LDS_ALLOC\0" /* 18743 */ ++ "SQ_LDS_ALLOC_PS\0" /* 18756 */ ++ "SQ_ESGS_RING_ITEMSIZE\0" /* 18772 */ ++ "SQ_GSVS_RING_ITEMSIZE\0" /* 18794 */ ++ "SQ_ESTMP_RING_BASE\0" /* 18816 */ ++ "SQ_ESTMP_RING_ITEMSIZE\0" /* 18835 */ ++ "SQ_ESTMP_RING_SIZE\0" /* 18858 */ ++ "SQ_GSTMP_RING_BASE\0" /* 18877 */ ++ "SQ_GSTMP_RING_ITEMSIZE\0" /* 18896 */ ++ "SQ_GSTMP_RING_SIZE\0" /* 18919 */ ++ "SQ_VSTMP_RING_BASE\0" /* 18938 */ ++ "SQ_VSTMP_RING_ITEMSIZE\0" /* 18957 */ ++ "SQ_VSTMP_RING_SIZE\0" /* 18980 */ ++ "SQ_PSTMP_RING_BASE\0" /* 18999 */ ++ "SQ_PSTMP_RING_ITEMSIZE\0" /* 19018 */ ++ "SQ_PSTMP_RING_SIZE\0" /* 19041 */ ++ "SQ_LSTMP_RING_BASE\0" /* 19060 */ ++ "SQ_LSTMP_RING_SIZE\0" /* 19079 */ ++ "SQ_HSTMP_RING_BASE\0" /* 19098 */ ++ "SQ_HSTMP_RING_ITEMSIZE\0" /* 19117 */ ++ "SQ_HSTMP_RING_SIZE\0" /* 19140 */ ++ "SQ_GS_VERT_ITEMSIZE\0" /* 19159 */ ++ "SQ_GS_VERT_ITEMSIZE_1\0" /* 19179 */ ++ "SQ_GS_VERT_ITEMSIZE_2\0" /* 19201 */ ++ "SQ_GS_VERT_ITEMSIZE_3\0" /* 19223 */ ++ "SQ_GSVS_RING_OFFSET_1\0" /* 19245 */ ++ "SQ_GSVS_RING_OFFSET_2\0" /* 19267 */ ++ "SQ_GSVS_RING_OFFSET_3\0" /* 19289 */ ++ "ALU_CONST_CACHE_PS_0\0" /* 19311 */ ++ "ALU_CONST_CACHE_PS_1\0" /* 19332 */ ++ "ALU_CONST_CACHE_VS_0\0" /* 19353 */ ++ "ALU_CONST_CACHE_VS_1\0" /* 19374 */ ++ "ALU_CONST_CACHE_GS_0\0" /* 19395 */ ++ "ALU_CONST_CACHE_HS_0\0" /* 19416 */ ++ "ALU_CONST_CACHE_LS_0\0" /* 19437 */ ++ "PA_SU_POINT_MINMAX\0" /* 19458 */ ++ "PA_SU_LINE_CNTL\0" /* 19477 */ ++ "VGT_OUTPUT_PATH_CNTL\0" /* 19493 */ ++ "VGT_HOS_CNTL\0" /* 19514 */ ++ "VGT_HOS_MAX_TESS_LEVEL\0" /* 19527 */ ++ "VGT_HOS_MIN_TESS_LEVEL\0" /* 19550 */ ++ "VGT_HOS_REUSE_DEPTH\0" /* 19573 */ ++ "VGT_GROUP_PRIM_TYPE\0" /* 19593 */ ++ "VGT_GROUP_FIRST_DECR\0" /* 19613 */ ++ "VGT_GROUP_DECR\0" /* 19634 */ ++ "VGT_GROUP_VECT_0_CNTL\0" /* 19649 */ ++ "VGT_GROUP_VECT_1_CNTL\0" /* 19671 */ ++ "VGT_GROUP_VECT_0_FMT_CNTL\0" /* 19693 */ ++ "VGT_GROUP_VECT_1_FMT_CNTL\0" /* 19719 */ ++ "PA_SC_MODE_CNTL_0\0" /* 19745 */ ++ "PA_SC_MODE_CNTL_1\0" /* 19763 */ ++ "GS_PER_ES\0" /* 19781 */ ++ "ES_PER_GS\0" /* 19791 */ ++ "GS_PER_VS\0" /* 19801 */ ++ "VGT_PRIMITIVEID_EN\0" /* 19811 */ ++ "VGT_MULTI_PRIM_IB_RESET_EN\0" /* 19830 */ ++ "VGT_REUSE_OFF\0" /* 19857 */ ++ "VGT_VTX_CNT_EN\0" /* 19871 */ ++ "DB_SRESULTS_COMPARE_STATE0\0" /* 19886 */ ++ "DB_SRESULTS_COMPARE_STATE1\0" /* 19913 */ ++ "DB_PRELOAD_CONTROL\0" /* 19940 */ ++ "VGT_STRMOUT_BUFFER_SIZE_0\0" /* 19959 */ ++ "VGT_STRMOUT_VTX_STRIDE_0\0" /* 19985 */ ++ "VGT_STRMOUT_BUFFER_BASE_0\0" /* 20010 */ ++ "VGT_STRMOUT_BUFFER_OFFSET_0\0" /* 20036 */ ++ "VGT_STRMOUT_BUFFER_SIZE_1\0" /* 20064 */ ++ "VGT_STRMOUT_VTX_STRIDE_1\0" /* 20090 */ ++ "VGT_STRMOUT_BUFFER_BASE_1\0" /* 20115 */ ++ "VGT_STRMOUT_BUFFER_OFFSET_1\0" /* 20141 */ ++ "VGT_STRMOUT_BUFFER_SIZE_2\0" /* 20169 */ ++ "VGT_STRMOUT_VTX_STRIDE_2\0" /* 20195 */ ++ "VGT_STRMOUT_BUFFER_BASE_2\0" /* 20220 */ ++ "VGT_STRMOUT_BUFFER_OFFSET_2\0" /* 20246 */ ++ "VGT_STRMOUT_BUFFER_SIZE_3\0" /* 20274 */ ++ "VGT_STRMOUT_VTX_STRIDE_3\0" /* 20300 */ ++ "VGT_STRMOUT_BUFFER_BASE_3\0" /* 20325 */ ++ "VGT_STRMOUT_BUFFER_OFFSET_3\0" /* 20351 */ ++ "VGT_STRMOUT_BASE_OFFSET_0\0" /* 20379 */ ++ "VGT_STRMOUT_BASE_OFFSET_1\0" /* 20405 */ ++ "VGT_STRMOUT_BASE_OFFSET_2\0" /* 20431 */ ++ "VGT_STRMOUT_BASE_OFFSET_3\0" /* 20457 */ ++ "VGT_STRMOUT_DRAW_OPAQUE_OFFSET\0" /* 20483 */ ++ "VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE\0" /* 20514 */ ++ "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE\0" /* 20557 */ ++ "VGT_GS_MAX_VERT_OUT\0" /* 20595 */ ++ "VGT_STRMOUT_BASE_OFFSET_HI_0\0" /* 20615 */ ++ "VGT_STRMOUT_BASE_OFFSET_HI_1\0" /* 20644 */ ++ "VGT_STRMOUT_BASE_OFFSET_HI_2\0" /* 20673 */ ++ "VGT_STRMOUT_BASE_OFFSET_HI_3\0" /* 20702 */ ++ "VGT_SHADER_STAGES_EN\0" /* 20731 */ ++ "VGT_LS_HS_CONFIG\0" /* 20752 */ ++ "VGT_LS_SIZE\0" /* 20769 */ ++ "VGT_HS_SIZE\0" /* 20781 */ ++ "VGT_LS_HS_ALLOC\0" /* 20793 */ ++ "VGT_HS_PATCH_CONST\0" /* 20809 */ ++ "DB_ALPHA_TO_MASK\0" /* 20828 */ ++ "PA_SU_POLY_OFFSET_DB_FMT_CNTL\0" /* 20845 */ ++ "PA_SU_POLY_OFFSET_CLAMP\0" /* 20875 */ ++ "PA_SU_POLY_OFFSET_FRONT_SCALE\0" /* 20899 */ ++ "PA_SU_POLY_OFFSET_FRONT_OFFSET\0" /* 20929 */ ++ "PA_SU_POLY_OFFSET_BACK_SCALE\0" /* 20960 */ ++ "PA_SU_POLY_OFFSET_BACK_OFFSET\0" /* 20989 */ ++ "VGT_GS_INSTANCE_CNT\0" /* 21019 */ ++ "CB_IMMED0_BASE\0" /* 21039 */ ++ "CB_IMMED1_BASE\0" /* 21054 */ ++ "CB_IMMED2_BASE\0" /* 21069 */ ++ "CB_IMMED3_BASE\0" /* 21084 */ ++ "CB_IMMED4_BASE\0" /* 21099 */ ++ "CB_IMMED5_BASE\0" /* 21114 */ ++ "CB_IMMED6_BASE\0" /* 21129 */ ++ "CB_IMMED7_BASE\0" /* 21144 */ ++ "CB_IMMED8_BASE\0" /* 21159 */ ++ "CB_IMMED9_BASE\0" /* 21174 */ ++ "CB_IMMED10_BASE\0" /* 21189 */ ++ "CB_IMMED11_BASE\0" /* 21205 */ ++ "PA_SC_LINE_CNTL\0" /* 21221 */ ++ "PA_SC_AA_CONFIG\0" /* 21237 */ ++ "PA_SU_VTX_CNTL\0" /* 21253 */ ++ "PA_CL_GB_VERT_CLIP_ADJ\0" /* 21268 */ ++ "PA_CL_GB_VERT_DISC_ADJ\0" /* 21291 */ ++ "PA_CL_GB_HORZ_CLIP_ADJ\0" /* 21314 */ ++ "PA_CL_GB_HORZ_DISC_ADJ\0" /* 21337 */ ++ "PA_SC_AA_SAMPLE_LOCS_0\0" /* 21360 */ ++ "PA_SC_AA_SAMPLE_LOCS_1\0" /* 21383 */ ++ "PA_SC_AA_SAMPLE_LOCS_2\0" /* 21406 */ ++ "PA_SC_AA_SAMPLE_LOCS_3\0" /* 21429 */ ++ "PA_SC_AA_SAMPLE_LOCS_4\0" /* 21452 */ ++ "PA_SC_AA_SAMPLE_LOCS_5\0" /* 21475 */ ++ "PA_SC_AA_SAMPLE_LOCS_6\0" /* 21498 */ ++ "PA_SC_AA_SAMPLE_LOCS_7\0" /* 21521 */ ++ "PA_SC_AA_MASK\0" /* 21544 */ ++ "CB_COLOR0_BASE\0" /* 21558 */ ++ "CB_COLOR0_VIEW\0" /* 21573 */ ++ "CB_COLOR0_CMASK\0" /* 21588 */ ++ "CB_COLOR0_CMASK_SLICE\0" /* 21604 */ ++ "CB_COLOR0_FMASK\0" /* 21626 */ ++ "CB_COLOR0_FMASK_SLICE\0" /* 21642 */ ++ "CB_COLOR0_CLEAR_WORD0\0" /* 21664 */ ++ "CB_COLOR0_CLEAR_WORD1\0" /* 21686 */ ++ "CB_COLOR0_CLEAR_WORD2\0" /* 21708 */ ++ "CB_COLOR0_CLEAR_WORD3\0" /* 21730 */ ++ "CB_COLOR1_BASE\0" /* 21752 */ ++ "CB_COLOR1_PITCH\0" /* 21767 */ ++ "CB_COLOR1_SLICE\0" /* 21783 */ ++ "CB_COLOR1_VIEW\0" /* 21799 */ ++ "CB_COLOR1_INFO\0" /* 21814 */ ++ "CB_COLOR1_ATTRIB\0" /* 21829 */ ++ "CB_COLOR1_DIM\0" /* 21846 */ ++ "CB_COLOR1_CMASK\0" /* 21860 */ ++ "CB_COLOR1_CMASK_SLICE\0" /* 21876 */ ++ "CB_COLOR1_FMASK\0" /* 21898 */ ++ "CB_COLOR1_FMASK_SLICE\0" /* 21914 */ ++ "CB_COLOR1_CLEAR_WORD0\0" /* 21936 */ ++ "CB_COLOR1_CLEAR_WORD1\0" /* 21958 */ ++ "CB_COLOR1_CLEAR_WORD2\0" /* 21980 */ ++ "CB_COLOR1_CLEAR_WORD3\0" /* 22002 */ ++ "CB_COLOR2_BASE\0" /* 22024 */ ++ "CB_COLOR2_PITCH\0" /* 22039 */ ++ "CB_COLOR2_SLICE\0" /* 22055 */ ++ "CB_COLOR2_VIEW\0" /* 22071 */ ++ "CB_COLOR2_INFO\0" /* 22086 */ ++ "CB_COLOR2_ATTRIB\0" /* 22101 */ ++ "CB_COLOR2_DIM\0" /* 22118 */ ++ "CB_COLOR2_CMASK\0" /* 22132 */ ++ "CB_COLOR2_CMASK_SLICE\0" /* 22148 */ ++ "CB_COLOR2_FMASK\0" /* 22170 */ ++ "CB_COLOR2_FMASK_SLICE\0" /* 22186 */ ++ "CB_COLOR2_CLEAR_WORD0\0" /* 22208 */ ++ "CB_COLOR2_CLEAR_WORD1\0" /* 22230 */ ++ "CB_COLOR2_CLEAR_WORD2\0" /* 22252 */ ++ "CB_COLOR2_CLEAR_WORD3\0" /* 22274 */ ++ "CB_COLOR3_BASE\0" /* 22296 */ ++ "CB_COLOR3_PITCH\0" /* 22311 */ ++ "CB_COLOR3_SLICE\0" /* 22327 */ ++ "CB_COLOR3_VIEW\0" /* 22343 */ ++ "CB_COLOR3_INFO\0" /* 22358 */ ++ "CB_COLOR3_ATTRIB\0" /* 22373 */ ++ "CB_COLOR3_DIM\0" /* 22390 */ ++ "CB_COLOR3_CMASK\0" /* 22404 */ ++ "CB_COLOR3_CMASK_SLICE\0" /* 22420 */ ++ "CB_COLOR3_FMASK\0" /* 22442 */ ++ "CB_COLOR3_FMASK_SLICE\0" /* 22458 */ ++ "CB_COLOR3_CLEAR_WORD0\0" /* 22480 */ ++ "CB_COLOR3_CLEAR_WORD1\0" /* 22502 */ ++ "CB_COLOR3_CLEAR_WORD2\0" /* 22524 */ ++ "CB_COLOR3_CLEAR_WORD3\0" /* 22546 */ ++ "CB_COLOR4_BASE\0" /* 22568 */ ++ "CB_COLOR4_PITCH\0" /* 22583 */ ++ "CB_COLOR4_SLICE\0" /* 22599 */ ++ "CB_COLOR4_VIEW\0" /* 22615 */ ++ "CB_COLOR4_INFO\0" /* 22630 */ ++ "CB_COLOR4_ATTRIB\0" /* 22645 */ ++ "CB_COLOR4_DIM\0" /* 22662 */ ++ "CB_COLOR4_CMASK\0" /* 22676 */ ++ "CB_COLOR4_CMASK_SLICE\0" /* 22692 */ ++ "CB_COLOR4_FMASK\0" /* 22714 */ ++ "CB_COLOR4_FMASK_SLICE\0" /* 22730 */ ++ "CB_COLOR4_CLEAR_WORD0\0" /* 22752 */ ++ "CB_COLOR4_CLEAR_WORD1\0" /* 22774 */ ++ "CB_COLOR4_CLEAR_WORD2\0" /* 22796 */ ++ "CB_COLOR4_CLEAR_WORD3\0" /* 22818 */ ++ "CB_COLOR5_BASE\0" /* 22840 */ ++ "CB_COLOR5_PITCH\0" /* 22855 */ ++ "CB_COLOR5_SLICE\0" /* 22871 */ ++ "CB_COLOR5_VIEW\0" /* 22887 */ ++ "CB_COLOR5_INFO\0" /* 22902 */ ++ "CB_COLOR5_ATTRIB\0" /* 22917 */ ++ "CB_COLOR5_DIM\0" /* 22934 */ ++ "CB_COLOR5_CMASK\0" /* 22948 */ ++ "CB_COLOR5_CMASK_SLICE\0" /* 22964 */ ++ "CB_COLOR5_FMASK\0" /* 22986 */ ++ "CB_COLOR5_FMASK_SLICE\0" /* 23002 */ ++ "CB_COLOR5_CLEAR_WORD0\0" /* 23024 */ ++ "CB_COLOR5_CLEAR_WORD1\0" /* 23046 */ ++ "CB_COLOR5_CLEAR_WORD2\0" /* 23068 */ ++ "CB_COLOR5_CLEAR_WORD3\0" /* 23090 */ ++ "CB_COLOR6_BASE\0" /* 23112 */ ++ "CB_COLOR6_PITCH\0" /* 23127 */ ++ "CB_COLOR6_SLICE\0" /* 23143 */ ++ "CB_COLOR6_VIEW\0" /* 23159 */ ++ "CB_COLOR6_INFO\0" /* 23174 */ ++ "CB_COLOR6_ATTRIB\0" /* 23189 */ ++ "CB_COLOR6_DIM\0" /* 23206 */ ++ "CB_COLOR6_CMASK\0" /* 23220 */ ++ "CB_COLOR6_CMASK_SLICE\0" /* 23236 */ ++ "CB_COLOR6_FMASK\0" /* 23258 */ ++ "CB_COLOR6_FMASK_SLICE\0" /* 23274 */ ++ "CB_COLOR6_CLEAR_WORD0\0" /* 23296 */ ++ "CB_COLOR6_CLEAR_WORD1\0" /* 23318 */ ++ "CB_COLOR6_CLEAR_WORD2\0" /* 23340 */ ++ "CB_COLOR6_CLEAR_WORD3\0" /* 23362 */ ++ "CB_COLOR7_BASE\0" /* 23384 */ ++ "CB_COLOR7_PITCH\0" /* 23399 */ ++ "CB_COLOR7_SLICE\0" /* 23415 */ ++ "CB_COLOR7_VIEW\0" /* 23431 */ ++ "CB_COLOR7_INFO\0" /* 23446 */ ++ "CB_COLOR7_ATTRIB\0" /* 23461 */ ++ "CB_COLOR7_DIM\0" /* 23478 */ ++ "CB_COLOR7_CMASK\0" /* 23492 */ ++ "CB_COLOR7_CMASK_SLICE\0" /* 23508 */ ++ "CB_COLOR7_FMASK\0" /* 23530 */ ++ "CB_COLOR7_FMASK_SLICE\0" /* 23546 */ ++ "CB_COLOR7_CLEAR_WORD0\0" /* 23568 */ ++ "CB_COLOR7_CLEAR_WORD1\0" /* 23590 */ ++ "CB_COLOR7_CLEAR_WORD2\0" /* 23612 */ ++ "CB_COLOR7_CLEAR_WORD3\0" /* 23634 */ ++ "CB_COLOR8_BASE\0" /* 23656 */ ++ "CB_COLOR8_PITCH\0" /* 23671 */ ++ "CB_COLOR8_SLICE\0" /* 23687 */ ++ "CB_COLOR8_VIEW\0" /* 23703 */ ++ "CB_COLOR8_INFO\0" /* 23718 */ ++ "CB_COLOR8_ATTRIB\0" /* 23733 */ ++ "CB_COLOR8_DIM\0" /* 23750 */ ++ "CB_COLOR9_BASE\0" /* 23764 */ ++ "CB_COLOR9_PITCH\0" /* 23779 */ ++ "CB_COLOR9_SLICE\0" /* 23795 */ ++ "CB_COLOR9_VIEW\0" /* 23811 */ ++ "CB_COLOR9_INFO\0" /* 23826 */ ++ "CB_COLOR9_ATTRIB\0" /* 23841 */ ++ "CB_COLOR9_DIM\0" /* 23858 */ ++ "CB_COLOR10_BASE\0" /* 23872 */ ++ "CB_COLOR10_PITCH\0" /* 23888 */ ++ "CB_COLOR10_SLICE\0" /* 23905 */ ++ "CB_COLOR10_VIEW\0" /* 23922 */ ++ "CB_COLOR10_INFO\0" /* 23938 */ ++ "CB_COLOR10_ATTRIB\0" /* 23954 */ ++ "CB_COLOR10_DIM\0" /* 23972 */ ++ "CB_COLOR11_BASE\0" /* 23987 */ ++ "CB_COLOR11_PITCH\0" /* 24003 */ ++ "CB_COLOR11_SLICE\0" /* 24020 */ ++ "CB_COLOR11_VIEW\0" /* 24037 */ ++ "CB_COLOR11_INFO\0" /* 24053 */ ++ "CB_COLOR11_ATTRIB\0" /* 24069 */ ++ "CB_COLOR11_DIM\0" /* 24087 */ ++ "RESOURCE0_WORD0\0" /* 24102 */ ++ "RESOURCE0_WORD1\0" /* 24118 */ ++ "RESOURCE0_WORD2\0" /* 24134 */ ++ "RESOURCE0_WORD3\0" /* 24150 */ ++ "RESOURCE0_WORD4\0" /* 24166 */ ++ "RESOURCE0_WORD5\0" /* 24182 */ ++ "RESOURCE0_WORD6\0" /* 24198 */ ++ "RESOURCE0_WORD7\0" /* 24214 */ ++ "CP_COHER_CNTL\0" /* 24230 */ ++ "CP_COHER_SIZE\0" /* 24244 */ ++ "CP_COHER_BASE\0" /* 24258 */ ++ "VGT_NUM_INDICES\0" /* 24272 */ ++ "SQ_VTX_BASE_VTX_LOC\0" /* 24288 */ ++ "SQ_VTX_START_INST_LOC\0" /* 24308 */ ++ "SQ_LOOP_CONST_0\0" /* 24330 */; ++ ++static const int egd_strings_offsets[] = { ++ /* 0 */ 1878, 1892, 1900, 1910, -1, 1922, 1931, 1946, 1956, 1968, 1980, 1994, 2008, 2022, 2031, 2046, 2058, 2076, 2087, 2104, 2115, 2132, 2147, 2168, 2183, 2204, 2221, 2235, 2252, 2273, 2285, 2303, 2321, -1, 2345, 2363, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2387, ++ /* 49 */ 2415, 2436, 2457, -1, 2478, ++ /* 54 */ 2510, 2523, 2536, 2551, 2566, 2578, 2590, 2602, ++ /* 62 */ 2627, 2636, 2645, 2658, ++ /* 66 */ 2766, 2782, 2798, ++ /* 69 */ 330, 2832, 2842, 2857, 2867, 2882, ++ /* 75 */ 3108, 3121, 3135, ++ /* 78 */ 3145, 3158, 3168, 3182, ++ /* 82 */ 3210, 3223, 3235, 3254, ++ /* 86 */ 3303, 3315, ++ /* 88 */ 3426, 3444, 3461, 3479, 3498, 3518, 3539, 3558, ++ /* 96 */ 3589, 3602, 3615, 3631, 3644, 3657, 3672, 3690, ++ /* 104 */ 3823, 3834, 3844, 3868, 3879, 3893, ++ /* 110 */ 4222, 4232, 4237, 4242, ++ /* 114 */ 4300, 4316, ++ /* 116 */ 4431, 4442, 4452, 4468, 4494, 4510, 4536, 4552, 4578, 4594, 4620, 4645, 4666, 4691, 4709, 4737, 4754, 4775, 4792, 4813, 4831, ++ /* 137 */ 4874, 4892, 4911, 4928, 4945, ++ /* 142 */ 5468, 5475, 5495, 5500, ++ /* 146 */ 5607, 5622, 5639, ++ /* 149 */ 5712, 5725, 5744, 5766, ++ /* 153 */ 5864, 5871, 5885, 5899, 5913, 5927, ++ /* 159 */ 5949, 5961, 5972, 5983, ++ /* 163 */ 6035, 6058, 6081, ++ /* 166 */ 6766, 6780, 6794, 6808, 6827, 6847, 6867, 6886, ++ /* 174 */ 6977, 7001, 7023, ++ /* 177 */ 7110, 7129, 7147, ++ /* 180 */ 7183, 7213, ++ /* 182 */ 7288, 7297, 7306, 7315, 7324, 7333, ++ /* 188 */ 7500, 7527, 7553, 7578, ++ /* 192 */ 7658, 7670, 7684, 7708, 7738, 7763, 7794, 7814, ++ /* 200 */ 7856, 7879, ++ /* 202 */ 7933, 7954, 7976, ++ /* 205 */ 8019, 8051, 8084, 8117, ++ /* 209 */ 8164, 8191, 8217, 8244, 8275, 8304, 8334, 8368, ++ /* 217 */ 8419, 8445, 8468, ++ /* 220 */ 8619, 8630, 8646, 8661, 8677, 8691, 8704, 8719, 8734, 8749, 8761, 8780, 8800, 8818, 8837, 8852, 8867, 8889, 8904, 8919, 8934, 8950, 8964, 8991, 9018, 9045, 9072, 9096, 9116, ++ /* 249 */ 9612, 9631, 9651, 9672, ++ /* 253 */ 10302, 10312, 10325, ++ /* 256 */ 11010, 11023, 11035, ++ /* 259 */ 11059, 11072, 11084, ++ /* 262 */ 11110, 11124, 11136, ++ /* 265 */ 11464, 11473, 11481, 11489, 11495, 11499, 11509, 11520, ++}; ++ ++#endif diff --git a/graphics/mesa/patches/patch-src_gallium_drivers_radeonsi_Makefile_am b/graphics/mesa/patches/patch-src_gallium_drivers_radeonsi_Makefile_am new file mode 100644 index 0000000..6e4abe5 --- /dev/null +++ b/graphics/mesa/patches/patch-src_gallium_drivers_radeonsi_Makefile_am @@ -0,0 +1,16 @@ +$OpenBSD$ + +Index: src/gallium/drivers/radeonsi/Makefile.am +--- src/gallium/drivers/radeonsi/Makefile.am.orig ++++ src/gallium/drivers/radeonsi/Makefile.am +@@ -51,8 +51,10 @@ GEN_DRIINFO_INPUTS = \ + PYTHON_GEN = $(AM_V_GEN)$(PYTHON) $(PYTHON_FLAGS) + MERGE_DRIINFO = $(top_srcdir)/src/util/merge_driinfo.py + ++if REGEN_SOURCES + si_driinfo.h: $(MERGE_DRIINFO) $(GEN_DRIINFO_INPUTS) + $(PYTHON_GEN) $(MERGE_DRIINFO) $(GEN_DRIINFO_INPUTS) > $@ || ($(RM) $@; false) ++endif + + BUILT_SOURCES = $(GENERATED_SOURCES) + CLEANFILES = $(GENERATED_SOURCES) diff --git a/graphics/mesa/patches/patch-src_gallium_drivers_swr_Makefile_am b/graphics/mesa/patches/patch-src_gallium_drivers_swr_Makefile_am new file mode 100644 index 0000000..262e3bf --- /dev/null +++ b/graphics/mesa/patches/patch-src_gallium_drivers_swr_Makefile_am @@ -0,0 +1,37 @@ +$OpenBSD$ + +Index: src/gallium/drivers/swr/Makefile.am +--- src/gallium/drivers/swr/Makefile.am.orig ++++ src/gallium/drivers/swr/Makefile.am +@@ -97,6 +97,7 @@ BUILT_SOURCES = \ + rasterizer/core/backends/gen_rasterizer3.cpp \ + rasterizer/core/backends/gen_rasterizer.hpp + ++if REGEN_SOURCES + MKDIR_GEN = $(AM_V_at)$(MKDIR_P) $(@D) + PYTHON_GEN = $(AM_V_GEN)$(PYTHON) $(PYTHON_FLAGS) + gen_swr_context_llvm.h: rasterizer/codegen/gen_llvm_types.py rasterizer/codegen/templates/gen_llvm.hpp swr_context.h +@@ -194,6 +195,7 @@ rasterizer/archrast/gen_ar_eventhandlerfile.hpp: raste + --output rasterizer/archrast/gen_ar_eventhandlerfile.hpp \ + --gen_eventhandlerfile_hpp + $(AM_V_GEN)touch $@ ++endif + + rasterizer/core/backends/gen_BackendPixelRate0.cpp \ + rasterizer/core/backends/gen_BackendPixelRate1.cpp \ +@@ -212,6 +214,7 @@ backend.intermediate + # use intermediate rule to tell make that all files can be + # generated in one invocation of gen_backends.py (prevents + # parallel make race condition) ++if REGEN_SOURCES + .INTERMEDIATE: backend.intermediate + backend.intermediate: rasterizer/codegen/gen_backends.py rasterizer/codegen/templates/gen_backend.cpp rasterizer/codegen/templates/gen_header_init.hpp + $(MKDIR_GEN) +@@ -251,6 +254,7 @@ rasterizer.intermediate: rasterizer/codegen/gen_backen + --numfiles 4 \ + --cpp \ + --hpp ++endif + + COMMON_LDFLAGS = \ + -shared \ diff --git a/graphics/mesa/patches/patch-src_gallium_targets_xvmc_Makefile_am b/graphics/mesa/patches/patch-src_gallium_targets_xvmc_Makefile_am new file mode 100644 index 0000000..2fb31ad --- /dev/null +++ b/graphics/mesa/patches/patch-src_gallium_targets_xvmc_Makefile_am @@ -0,0 +1,23 @@ +$OpenBSD$ + +Index: src/gallium/targets/xvmc/Makefile.am +--- src/gallium/targets/xvmc/Makefile.am.orig ++++ src/gallium/targets/xvmc/Makefile.am +@@ -74,15 +74,9 @@ install-data-hook: + for i in $(TARGET_DRIVERS); do \ + j=libXvMCgallium.$(LIB_EXT); \ + k=libXvMC$${i}.$(LIB_EXT); \ +- l=$${k}.$(XVMC_MAJOR).$(XVMC_MINOR).0; \ +- ln -f $${dest_dir}/$${j}.$(XVMC_MAJOR).$(XVMC_MINOR).0 \ ++ l=$${k}.$(XVMC_MAJOR).$(XVMC_MINOR); \ ++ ln -f $${dest_dir}/$${j}.$(XVMC_MAJOR).$(XVMC_MINOR) \ + $${dest_dir}/$${l}; \ +- ln -sf $${l} \ +- $${dest_dir}/$${k}.$(XVMC_MAJOR).$(XVMC_MINOR); \ +- ln -sf $${l} \ +- $${dest_dir}/$${k}.$(XVMC_MAJOR); \ +- ln -sf $${l} \ +- $${dest_dir}/$${k}; \ + done; \ + $(RM) $${dest_dir}/libXvMCgallium.*; \ + $(RM) -d $${dest_dir} &>/dev/null || true diff --git a/graphics/mesa/patches/patch-src_gbm_backends_dri_gbm_dri_c b/graphics/mesa/patches/patch-src_gbm_backends_dri_gbm_dri_c new file mode 100644 index 0000000..892c07b --- /dev/null +++ b/graphics/mesa/patches/patch-src_gbm_backends_dri_gbm_dri_c @@ -0,0 +1,17 @@ +$OpenBSD$ + +Index: src/gbm/backends/dri/gbm_dri.c +--- src/gbm/backends/dri/gbm_dri.c.orig ++++ src/gbm/backends/dri/gbm_dri.c +@@ -310,7 +310,11 @@ dri_open_driver(struct gbm_dri_device *dri) + /* XXX: Library name differs on per platforms basis. Update this as + * osx/cygwin/windows/bsd gets support for GBM.. + */ ++#ifdef __OpenBSD__ ++ dlopen("libglapi.so", RTLD_LAZY | RTLD_GLOBAL); ++#else + dlopen("libglapi.so.0", RTLD_LAZY | RTLD_GLOBAL); ++#endif + + static const char *search_path_vars[] = { + /* Read GBM_DRIVERS_PATH first for compatibility, but LIBGL_DRIVERS_PATH diff --git a/graphics/mesa/patches/patch-src_glx_Makefile_am b/graphics/mesa/patches/patch-src_glx_Makefile_am new file mode 100644 index 0000000..90fb1bb --- /dev/null +++ b/graphics/mesa/patches/patch-src_glx_Makefile_am @@ -0,0 +1,14 @@ +$OpenBSD$ + +Index: src/glx/Makefile.am +--- src/glx/Makefile.am.orig ++++ src/glx/Makefile.am +@@ -149,7 +149,7 @@ endif + + if USE_LIBGLVND + AM_CFLAGS += \ +- -DGL_LIB_NAME=\"lib@GL_LIB@.so.0\" \ ++ -DGL_LIB_NAME=\"lib@GL_LIB@.so\" \ + $(GLVND_CFLAGS) + + libglx_la_SOURCES += \ diff --git a/graphics/mesa/patches/patch-src_glx_dri_common_c b/graphics/mesa/patches/patch-src_glx_dri_common_c new file mode 100644 index 0000000..b35769e --- /dev/null +++ b/graphics/mesa/patches/patch-src_glx_dri_common_c @@ -0,0 +1,16 @@ +$OpenBSD$ + +Index: src/glx/dri_common.c +--- src/glx/dri_common.c.orig ++++ src/glx/dri_common.c +@@ -73,6 +73,10 @@ dri_message(int level, const char *f, ...) + } + } + ++#ifdef __OpenBSD__ ++#define GL_LIB_NAME "libGL.so" ++#endif ++ + #ifndef GL_LIB_NAME + #define GL_LIB_NAME "libGL.so.1" + #endif diff --git a/graphics/mesa/patches/patch-src_intel_Makefile_compiler_am b/graphics/mesa/patches/patch-src_intel_Makefile_compiler_am new file mode 100644 index 0000000..f946b26 --- /dev/null +++ b/graphics/mesa/patches/patch-src_intel_Makefile_compiler_am @@ -0,0 +1,18 @@ +$OpenBSD$ + +Index: src/intel/Makefile.compiler.am +--- src/intel/Makefile.compiler.am.orig ++++ src/intel/Makefile.compiler.am +@@ -32,10 +32,12 @@ compiler_libintel_compiler_la_SOURCES = \ + + BUILT_SOURCES += $(COMPILER_GENERATED_FILES) + ++if REGEN_SOURCES + compiler/brw_nir_trig_workarounds.c: compiler/brw_nir_trig_workarounds.py \ + $(top_srcdir)/src/compiler/nir/nir_algebraic.py + $(MKDIR_GEN) + $(AM_V_GEN) $(PYTHON) $(PYTHON_FLAGS) $(srcdir)/compiler/brw_nir_trig_workarounds.py -p $(top_srcdir)/src/compiler/nir > $@ || ($(RM) $@; false) ++endif + + EXTRA_DIST += \ + compiler/brw_nir_trig_workarounds.py diff --git a/graphics/mesa/patches/patch-src_intel_Makefile_genxml_am b/graphics/mesa/patches/patch-src_intel_Makefile_genxml_am new file mode 100644 index 0000000..3e9bf9a --- /dev/null +++ b/graphics/mesa/patches/patch-src_intel_Makefile_genxml_am @@ -0,0 +1,21 @@ +$OpenBSD$ + +Index: src/intel/Makefile.genxml.am +--- src/intel/Makefile.genxml.am.orig ++++ src/intel/Makefile.genxml.am +@@ -30,6 +30,7 @@ SUFFIXES = _pack.h _xml.h .xml + + $(GENXML_GENERATED_PACK_FILES): genxml/gen_pack_header.py + ++if REGEN_SOURCES + .xml_pack.h: + $(MKDIR_GEN) + $(PYTHON_GEN) $(srcdir)/genxml/gen_pack_header.py $< > $@ || ($(RM) $@; false) +@@ -41,6 +42,7 @@ genxml/genX_xml.h: genxml/gen_zipped_file.py $(GENXML_ + genxml/genX_bits.h: genxml/gen_bits_header.py $(GENXML_XML_FILES) + $(MKDIR_GEN) + $(PYTHON_GEN) $(srcdir)/genxml/gen_bits_header.py -o $@ $(GENXML_XML_FILES:%=$(srcdir)/%) ++endif + + EXTRA_DIST += \ + genxml/genX_pack.h \ diff --git a/graphics/mesa/patches/patch-src_intel_Makefile_isl_am b/graphics/mesa/patches/patch-src_intel_Makefile_isl_am new file mode 100644 index 0000000..e024bd9 --- /dev/null +++ b/graphics/mesa/patches/patch-src_intel_Makefile_isl_am @@ -0,0 +1,19 @@ +$OpenBSD$ + +Index: src/intel/Makefile.isl.am +--- src/intel/Makefile.isl.am.orig ++++ src/intel/Makefile.isl.am +@@ -83,11 +83,13 @@ isl_libisl_gen11_la_CFLAGS = $(AM_CFLAGS) -DGEN_VERSIO + + BUILT_SOURCES += $(ISL_GENERATED_FILES) + ++if REGEN_SOURCES + isl/isl_format_layout.c: isl/gen_format_layout.py \ + isl/isl_format_layout.csv + $(MKDIR_GEN) + $(PYTHON_GEN) $(srcdir)/isl/gen_format_layout.py \ + --csv $(srcdir)/isl/isl_format_layout.csv --out $@ ++endif + + # ---------------------------------------------------------------------------- + # Tests diff --git a/graphics/mesa/patches/patch-src_intel_Makefile_vulkan_am b/graphics/mesa/patches/patch-src_intel_Makefile_vulkan_am new file mode 100644 index 0000000..ce952e9 --- /dev/null +++ b/graphics/mesa/patches/patch-src_intel_Makefile_vulkan_am @@ -0,0 +1,52 @@ +$OpenBSD$ + +Index: src/intel/Makefile.vulkan.am +--- src/intel/Makefile.vulkan.am.orig ++++ src/intel/Makefile.vulkan.am +@@ -24,6 +24,7 @@ + # out and we'll fail at `make dist' + vulkan_api_xml = $(top_srcdir)/src/vulkan/registry/vk.xml + ++if REGEN_SOURCES + vulkan/anv_entrypoints.c: vulkan/anv_entrypoints_gen.py \ + vulkan/anv_extensions.py \ + $(vulkan_api_xml) +@@ -48,6 +49,7 @@ vulkan/anv_extensions.h: vulkan/anv_extensions_gen.py + $(AM_V_GEN)$(PYTHON) $(srcdir)/vulkan/anv_extensions_gen.py \ + --xml $(vulkan_api_xml) \ + --out-h $@ ++endif + + BUILT_SOURCES += $(VULKAN_GENERATED_FILES) + CLEANFILES += \ +@@ -63,6 +65,7 @@ EXTRA_DIST += \ + vulkan/anv_icd.py \ + vulkan/TODO + ++if REGEN_SOURCES + vulkan/dev_icd.json : vulkan/anv_extensions.py vulkan/anv_icd.py + $(MKDIR_GEN) + $(AM_V_GEN)$(PYTHON) $(srcdir)/vulkan/anv_icd.py \ +@@ -72,6 +75,22 @@ vulkan/intel_icd.@host_cpu@.json : vulkan/anv_extensio + $(MKDIR_GEN) + $(AM_V_GEN)$(PYTHON) $(srcdir)/vulkan/anv_icd.py \ + --lib-path="${libdir}" --out $@ ++else ++vulkan/intel_icd.@host_cpu@.json : ++ $(MKDIR_GEN) ++ @echo -e "{" > $@ ++ @echo -e " \"ICD\": {" >> $@ ++ @echo -e " \"api_version\": \"1.1.96\"," >> $@ ++ @echo -e " \"library_path\": \"${libdir}/libvulkan_intel.so\"" >> $@ ++ @echo -e " }," >> $@ ++ @echo -e " \"file_format_version\": \"1.0.0\"" >> $@ ++ @echo -ne "}" >> $@ ++ ++.PHONY: vulkan/intel_icd.@host_cpu@.json ++ ++vulkan/dev_icd.json : vulkan/intel_icd.@host_cpu@.json ++ cp vulkan/intel_icd.@host_cpu@.json $@ ++endif + + if HAVE_INTEL_VULKAN + diff --git a/graphics/mesa/patches/patch-src_intel_tools_aub_mem_c b/graphics/mesa/patches/patch-src_intel_tools_aub_mem_c new file mode 100644 index 0000000..1ca2d18 --- /dev/null +++ b/graphics/mesa/patches/patch-src_intel_tools_aub_mem_c @@ -0,0 +1,29 @@ +$OpenBSD$ + +Index: src/intel/tools/aub_mem.c +--- src/intel/tools/aub_mem.c.orig ++++ src/intel/tools/aub_mem.c +@@ -28,7 +28,7 @@ + + #include "aub_mem.h" + +-#ifndef HAVE_MEMFD_CREATE ++#if !defined(HAVE_MEMFD_CREATE) && !defined(__OpenBSD__) + #include <sys/syscall.h> + + static inline int +@@ -373,7 +373,14 @@ aub_mem_init(struct aub_mem *mem) + + list_inithead(&mem->maps); + ++#ifdef __OpenBSD__ ++ char mem_path[] = "/tmp/mesa-XXXXXXXXXX"; ++ mem->mem_fd = shm_mkstemp(mem_path); ++ if (mem->mem_fd != -1) ++ shm_unlink(mem_path); ++#else + mem->mem_fd = memfd_create("phys memory", 0); ++#endif + + return mem->mem_fd != -1; + } diff --git a/graphics/mesa/patches/patch-src_intel_vulkan_anv_allocator_c b/graphics/mesa/patches/patch-src_intel_vulkan_anv_allocator_c new file mode 100644 index 0000000..f643c4d --- /dev/null +++ b/graphics/mesa/patches/patch-src_intel_vulkan_anv_allocator_c @@ -0,0 +1,43 @@ +$OpenBSD$ + +Index: src/intel/vulkan/anv_allocator.c +--- src/intel/vulkan/anv_allocator.c.orig ++++ src/intel/vulkan/anv_allocator.c +@@ -25,9 +25,21 @@ + #include <unistd.h> + #include <limits.h> + #include <assert.h> ++#ifdef __linux__ + #include <linux/memfd.h> ++#else ++#include <fcntl.h> ++#endif + #include <sys/mman.h> + ++#ifndef MAP_POPULATE ++#define MAP_POPULATE 0 ++#endif ++ ++#ifndef MFD_CLOEXEC ++#define MFD_CLOEXEC O_CLOEXEC ++#endif ++ + #include "anv_private.h" + + #include "util/hash_table.h" +@@ -115,7 +127,15 @@ struct anv_mmap_cleanup { + static inline int + memfd_create(const char *name, unsigned int flags) + { ++#ifdef __linux__ + return syscall(SYS_memfd_create, name, flags); ++#else ++ char template[] = "/tmp/mesa-XXXXXXXXXX"; ++ int fd = shm_mkstemp(template); ++ if (fd != -1) ++ shm_unlink(template); ++ return fd; ++#endif + } + #endif + diff --git a/graphics/mesa/patches/patch-src_intel_vulkan_anv_device_c b/graphics/mesa/patches/patch-src_intel_vulkan_anv_device_c new file mode 100644 index 0000000..43453f3 --- /dev/null +++ b/graphics/mesa/patches/patch-src_intel_vulkan_anv_device_c @@ -0,0 +1,41 @@ +$OpenBSD$ + +Index: src/intel/vulkan/anv_device.c +--- src/intel/vulkan/anv_device.c.orig ++++ src/intel/vulkan/anv_device.c +@@ -25,7 +25,12 @@ + #include <stdbool.h> + #include <string.h> + #include <sys/mman.h> ++#ifdef __linux__ + #include <sys/sysinfo.h> ++#else ++#include <sys/types.h> ++#include <sys/sysctl.h> ++#endif + #include <unistd.h> + #include <fcntl.h> + #include <xf86drm.h> +@@ -64,10 +69,22 @@ static uint64_t + anv_compute_heap_size(int fd, uint64_t gtt_size) + { + /* Query the total ram from the system */ ++#ifdef __linux__ + struct sysinfo info; + sysinfo(&info); + + uint64_t total_ram = (uint64_t)info.totalram * (uint64_t)info.mem_unit; ++#else ++ int mib[2]; ++ uint64_t total_ram; ++ size_t size; ++ ++ mib[0] = CTL_HW; ++ mib[1] = HW_PHYSMEM64; ++ size = sizeof(total_ram); ++ if (sysctl(mib, 2, &total_ram, &size, NULL, 0) == -1) ++ return vk_error(VK_ERROR_INITIALIZATION_FAILED); ++#endif + + /* We don't want to burn too much ram with the GPU. If the user has 4GiB + * or less, we use at most half. If they have more than 4GiB, we use 3/4. diff --git a/graphics/mesa/patches/patch-src_intel_vulkan_anv_private_h b/graphics/mesa/patches/patch-src_intel_vulkan_anv_private_h new file mode 100644 index 0000000..61f63a9 --- /dev/null +++ b/graphics/mesa/patches/patch-src_intel_vulkan_anv_private_h @@ -0,0 +1,22 @@ +$OpenBSD$ + +Index: src/intel/vulkan/anv_private.h +--- src/intel/vulkan/anv_private.h.orig ++++ src/intel/vulkan/anv_private.h +@@ -32,6 +32,16 @@ + #include <stdint.h> + #include <i915_drm.h> + ++#include <errno.h> ++#ifndef ETIME ++#define ETIME ETIMEDOUT ++#endif ++ ++#include <time.h> ++#ifndef CLOCK_MONOTONIC_RAW ++#define CLOCK_MONOTONIC_RAW CLOCK_MONOTONIC ++#endif ++ + #ifdef HAVE_VALGRIND + #include <valgrind.h> + #include <memcheck.h> diff --git a/graphics/mesa/patches/patch-src_intel_vulkan_anv_queue_c b/graphics/mesa/patches/patch-src_intel_vulkan_anv_queue_c new file mode 100644 index 0000000..dffa1e3 --- /dev/null +++ b/graphics/mesa/patches/patch-src_intel_vulkan_anv_queue_c @@ -0,0 +1,15 @@ +$OpenBSD$ + +Index: src/intel/vulkan/anv_queue.c +--- src/intel/vulkan/anv_queue.c.orig ++++ src/intel/vulkan/anv_queue.c +@@ -27,7 +27,9 @@ + + #include <fcntl.h> + #include <unistd.h> ++#ifdef __linux__ + #include <sys/eventfd.h> ++#endif + + #include "anv_private.h" + #include "vk_util.h" diff --git a/graphics/mesa/patches/patch-src_mapi_Makefile_am b/graphics/mesa/patches/patch-src_mapi_Makefile_am new file mode 100644 index 0000000..edd9016 --- /dev/null +++ b/graphics/mesa/patches/patch-src_mapi_Makefile_am @@ -0,0 +1,42 @@ +$OpenBSD$ + +Index: src/mapi/Makefile.am +--- src/mapi/Makefile.am.orig ++++ src/mapi/Makefile.am +@@ -110,10 +110,12 @@ shared_glapi_test_LDADD = \ + $(top_builddir)/src/gtest/libgtest.la + endif + ++if REGEN_SOURCES + shared-glapi/glapi_mapi_tmp.h : glapi/gen/gl_and_es_API.xml $(shared_glapi_gen_mapi_deps) + $(MKDIR_GEN) + $(PYTHON_GEN) $(srcdir)/mapi_abi.py --printer shared-glapi \ + $(srcdir)/glapi/gen/gl_and_es_API.xml > $@ ++endif + + if HAVE_OPENGL + noinst_LTLIBRARIES = glapi/libglapi.la +@@ -209,9 +211,11 @@ es1api_libGLESv1_CM_la_LDFLAGS = \ + es1api_libGLESv1_CM_la_LIBADD += shared-glapi/libglapi.la + endif + ++if REGEN_SOURCES + es1api/glapi_mapi_tmp.h: $(glapi_gen_mapi_deps) + $(MKDIR_GEN) + $(glapi_gen_mapi) glesv1 $(glapi_gen_gl_xml) > $@ ++endif + + if HAVE_OPENGL_ES2 + TESTS += es2api/ABI-check +@@ -253,9 +257,11 @@ es2api_libGLESv2_la_LDFLAGS = \ + es2api_libGLESv2_la_LIBADD += shared-glapi/libglapi.la + endif + ++if REGEN_SOURCES + es2api/glapi_mapi_tmp.h: $(glapi_gen_mapi_deps) + $(MKDIR_GEN) + $(glapi_gen_mapi) glesv2 $(glapi_gen_gl_xml) > $@ ++endif + + include $(top_srcdir)/install-lib-links.mk + diff --git a/graphics/mesa/patches/patch-src_mapi_entry_x86_tsd_h b/graphics/mesa/patches/patch-src_mapi_entry_x86_tsd_h new file mode 100644 index 0000000..e8bdc56 --- /dev/null +++ b/graphics/mesa/patches/patch-src_mapi_entry_x86_tsd_h @@ -0,0 +1,53 @@ +$OpenBSD$ + +Index: src/mapi/entry_x86_tsd.h +--- src/mapi/entry_x86_tsd.h.orig ++++ src/mapi/entry_x86_tsd.h +@@ -31,25 +31,31 @@ + #define HIDDEN + #endif + +-#define X86_ENTRY_SIZE 32 ++#define X86_ENTRY_SIZE 64 + + __asm__(".text\n" +- ".balign 32\n" ++ ".balign " U_STRINGIFY(X86_ENTRY_SIZE) "\n" + "x86_entry_start:"); + + #define STUB_ASM_ENTRY(func) \ + ".globl " func "\n" \ + ".type " func ", @function\n" \ +- ".balign 32\n" \ ++ ".balign " U_STRINGIFY(X86_ENTRY_SIZE) "\n" \ + func ":" + + #define STUB_ASM_CODE(slot) \ +- "movl " ENTRY_CURRENT_TABLE ", %eax\n\t" \ ++ "push %ebx\n\t" \ ++ "call 1f\n" \ ++ "1:\n\t" \ ++ "popl %ebx\n\t" \ ++ "addl $_GLOBAL_OFFSET_TABLE_+[.-1b], %ebx\n\t" \ ++ "movl " ENTRY_CURRENT_TABLE "@GOT(%ebx), %eax\n\t" \ ++ "mov (%eax), %eax\n\t" \ + "testl %eax, %eax\n\t" \ +- "je 1f\n\t" \ +- "jmp *(4 * " slot ")(%eax)\n" \ ++ "jne 1f\n\t" \ ++ "call " ENTRY_CURRENT_TABLE_GET "@PLT\n" \ + "1:\n\t" \ +- "call " ENTRY_CURRENT_TABLE_GET "\n\t" \ ++ "pop %ebx\n\t" \ + "jmp *(4 * " slot ")(%eax)" + + #define MAPI_TMP_STUB_ASM_GCC +@@ -57,7 +63,7 @@ __asm__(".text\n" + + #ifndef MAPI_MODE_BRIDGE + +-__asm__(".balign 32\n" ++__asm__(".balign " U_STRINGIFY(X86_ENTRY_SIZE) "\n" + "x86_entry_end:"); + + #include <string.h> diff --git a/graphics/mesa/patches/patch-src_mapi_glapi_gen_Makefile_am b/graphics/mesa/patches/patch-src_mapi_glapi_gen_Makefile_am new file mode 100644 index 0000000..64a3a67 --- /dev/null +++ b/graphics/mesa/patches/patch-src_mapi_glapi_gen_Makefile_am @@ -0,0 +1,18 @@ +$OpenBSD$ + +Index: src/mapi/glapi/gen/Makefile.am +--- src/mapi/glapi/gen/Makefile.am.orig ++++ src/mapi/glapi/gen/Makefile.am +@@ -268,6 +268,7 @@ $(XORG_GLAPI_DIR)/%.h: $(MESA_GLAPI_DIR)/%.h + + ###################################################################### + ++if REGEN_SOURCES + $(MESA_GLAPI_DIR)/glapi_mapi_tmp.h: $(MESA_MAPI_DIR)/mapi_abi.py $(COMMON) + $(PYTHON_GEN) $(MESA_MAPI_DIR)/mapi_abi.py \ + --printer glapi $(srcdir)/gl_and_es_API.xml > $@ +@@ -371,3 +372,4 @@ $(XORG_GLX_DIR)/indirect_reqsize.c: glX_proto_size.py + $(XORG_GLX_DIR)/indirect_table.c: glX_server_table.py gl_and_glX_API.xml $(COMMON_GLX) + $(PYTHON_GEN) $< -f $(srcdir)/gl_and_glX_API.xml \ + | $(INDENT) $(XORG_INDENT_FLAGS) > $@ ++endif diff --git a/graphics/mesa/patches/patch-src_mapi_u_execmem_c b/graphics/mesa/patches/patch-src_mapi_u_execmem_c new file mode 100644 index 0000000..e64bc0f --- /dev/null +++ b/graphics/mesa/patches/patch-src_mapi_u_execmem_c @@ -0,0 +1,22 @@ +$OpenBSD$ + +Index: src/mapi/u_execmem.c +--- src/mapi/u_execmem.c.orig ++++ src/mapi/u_execmem.c +@@ -45,8 +45,15 @@ static unsigned int head = 0; + + static unsigned char *exec_mem = (unsigned char *)0; + ++#if defined(__OpenBSD__) + +-#if defined(__linux__) || defined(__OpenBSD__) || defined(_NetBSD__) || defined(__sun) || defined(__HAIKU__) ++static int ++init_map(void) ++{ ++ return 0; ++} ++ ++#elif defined(__linux__) || defined(_NetBSD__) || defined(__sun) || defined(__HAIKU__) + + #include <unistd.h> + #include <sys/mman.h> diff --git a/graphics/mesa/patches/patch-src_mesa_Makefile_am b/graphics/mesa/patches/patch-src_mesa_Makefile_am new file mode 100644 index 0000000..a390ef3 --- /dev/null +++ b/graphics/mesa/patches/patch-src_mesa_Makefile_am @@ -0,0 +1,38 @@ +$OpenBSD$ + +Index: src/mesa/Makefile.am +--- src/mesa/Makefile.am.orig ++++ src/mesa/Makefile.am +@@ -73,6 +73,7 @@ CLEANFILES = \ + $(BUILT_SOURCES) \ + program/program_parse.tab.h + ++if REGEN_SOURCES + PYTHON_GEN = $(AM_V_GEN)$(PYTHON) $(PYTHON_FLAGS) + + main/get_hash.h: ../mapi/glapi/gen/gl_and_es_API.xml main/get_hash_params.py \ +@@ -96,6 +97,7 @@ main/format_pack.c: main/format_pack.py main/formats.c + main/format_unpack.c: main/format_unpack.py main/formats.csv \ + main/format_parser.py + $(PYTHON_GEN) $(srcdir)/main/format_unpack.py $(srcdir)/main/formats.csv > $@ ++endif + + main/formats.c: main/format_info.h + +@@ -173,6 +175,8 @@ libmesa_sse41_la_SOURCES = \ + libmesa_sse41_la_CFLAGS = $(AM_CFLAGS) $(SSE41_CFLAGS) + + MKDIR_GEN = $(AM_V_at)$(MKDIR_P) $(@D) ++ ++if REGEN_SOURCES + YACC_GEN = $(AM_V_GEN)$(YACC) $(YFLAGS) + LEX_GEN = $(AM_V_GEN)$(LEX) $(LFLAGS) + +@@ -183,6 +187,7 @@ program/lex.yy.c: program/program_lexer.l + program/program_parse.tab.c program/program_parse.tab.h: program/program_parse.y + $(MKDIR_GEN) + $(YACC_GEN) -o $@ -p "_mesa_program_" --defines=$(builddir)/program/program_parse.tab.h $(srcdir)/program/program_parse.y ++endif + + if GEN_ASM_OFFSETS + matypes.h: $(gen_matypes_SOURCES) diff --git a/graphics/mesa/patches/patch-src_mesa_drivers_dri_i965_Makefile_am b/graphics/mesa/patches/patch-src_mesa_drivers_dri_i965_Makefile_am new file mode 100644 index 0000000..157e48e --- /dev/null +++ b/graphics/mesa/patches/patch-src_mesa_drivers_dri_i965_Makefile_am @@ -0,0 +1,18 @@ +$OpenBSD$ + +Index: src/mesa/drivers/dri/i965/Makefile.am +--- src/mesa/drivers/dri/i965/Makefile.am.orig ++++ src/mesa/drivers/dri/i965/Makefile.am +@@ -117,10 +117,12 @@ EXTRA_DIST = \ + $(i965_oa_xml_FILES) \ + meson.build + ++if REGEN_SOURCES + brw_oa_metrics.c: brw_oa.py $(i965_oa_xml_FILES) + $(PYTHON) $(PYTHON_FLAGS) $(srcdir)/brw_oa.py \ + --code=$(builddir)/brw_oa_metrics.c \ + --header=$(builddir)/brw_oa_metrics.h \ + $(i965_oa_xml_FILES:%=$(srcdir)/%) ++endif + + brw_oa_metrics.h: brw_oa_metrics.c diff --git a/graphics/mesa/patches/patch-src_mesa_main_compiler_h b/graphics/mesa/patches/patch-src_mesa_main_compiler_h new file mode 100644 index 0000000..020ce1f --- /dev/null +++ b/graphics/mesa/patches/patch-src_mesa_main_compiler_h @@ -0,0 +1,39 @@ +$OpenBSD$ + +Index: src/mesa/main/compiler.h +--- src/mesa/main/compiler.h.orig ++++ src/mesa/main/compiler.h +@@ -47,28 +47,16 @@ + * Try to use a runtime test instead. + * For now, only used by some DRI hardware drivers for color/texel packing. + */ +-#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && BYTE_ORDER == BIG_ENDIAN +-#if defined(__linux__) +-#include <byteswap.h> +-#define CPU_TO_LE32( x ) bswap_32( x ) +-#elif defined(__APPLE__) +-#include <CoreFoundation/CFByteOrder.h> +-#define CPU_TO_LE32( x ) CFSwapInt32HostToLittle( x ) +-#elif defined(__OpenBSD__) +-#include <sys/types.h> ++#ifdef __OpenBSD__ ++#include <endian.h> + #define CPU_TO_LE32( x ) htole32( x ) +-#else /*__linux__ */ +-#include <sys/endian.h> +-#define CPU_TO_LE32( x ) bswap32( x ) +-#endif /*__linux__*/ ++#define LE32_TO_CPU( x ) letoh32( x ) ++#if BYTE_ORDER == BIG_ENDIAN + #define MESA_BIG_ENDIAN 1 + #else +-#define CPU_TO_LE32( x ) ( x ) + #define MESA_LITTLE_ENDIAN 1 + #endif +-#define LE32_TO_CPU( x ) CPU_TO_LE32( x ) +- +- ++#endif /* __OpenBSD__ */ + + #define IEEE_ONE 0x3f800000 + diff --git a/graphics/mesa/patches/patch-src_mesa_main_execmem_c b/graphics/mesa/patches/patch-src_mesa_main_execmem_c new file mode 100644 index 0000000..21fa773 --- /dev/null +++ b/graphics/mesa/patches/patch-src_mesa_main_execmem_c @@ -0,0 +1,27 @@ +$OpenBSD$ + +Index: src/mesa/main/execmem.c +--- src/mesa/main/execmem.c.orig ++++ src/mesa/main/execmem.c +@@ -37,7 +37,20 @@ + #include "c11/threads.h" + + +-#if defined(__linux__) || defined(__OpenBSD__) || defined(_NetBSD__) || defined(__sun) || defined(__HAIKU__) ++#if defined(__OpenBSD__) ++ ++void * ++_mesa_exec_malloc(GLuint size) ++{ ++ return NULL; ++} ++ ++void ++_mesa_exec_free(void *addr) ++{ ++} ++ ++#elif defined(__linux__) || defined(_NetBSD__) || defined(__sun) || defined(__HAIKU__) + + /* + * Allocate a large block of memory which can hold code then dole it out diff --git a/graphics/mesa/patches/patch-src_util_Makefile_am b/graphics/mesa/patches/patch-src_util_Makefile_am new file mode 100644 index 0000000..a2ed0ee --- /dev/null +++ b/graphics/mesa/patches/patch-src_util_Makefile_am @@ -0,0 +1,24 @@ +$OpenBSD$ + +Index: src/util/Makefile.am +--- src/util/Makefile.am.orig ++++ src/util/Makefile.am +@@ -75,7 +75,7 @@ libxmlconfig_la_CFLAGS = \ + libxmlconfig_la_LIBADD = $(EXPAT_LIBS) -lm + + drircdir = $(datadir)/drirc.d +-drirc_DATA = 00-mesa-defaults.conf ++drirc_DATA = + + u_atomic_test_LDADD = libmesautil.la + roundeven_test_LDADD = -lm +@@ -95,7 +95,9 @@ EXTRA_DIST = \ + sha1/README \ + meson.build + ++if REGEN_SOURCES + PYTHON_GEN = $(AM_V_GEN)$(PYTHON) $(PYTHON_FLAGS) + + format_srgb.c: format_srgb.py + $(PYTHON_GEN) $(srcdir)/format_srgb.py > $@ ++endif diff --git a/graphics/mesa/patches/patch-src_util_build_id_c b/graphics/mesa/patches/patch-src_util_build_id_c new file mode 100644 index 0000000..9403ff0 --- /dev/null +++ b/graphics/mesa/patches/patch-src_util_build_id_c @@ -0,0 +1,14 @@ +$OpenBSD$ + +Index: src/util/build_id.c +--- src/util/build_id.c.orig ++++ src/util/build_id.c +@@ -21,7 +21,7 @@ + * IN THE SOFTWARE. + */ + +-#ifdef HAVE_DL_ITERATE_PHDR ++#if defined(HAVE_DL_ITERATE_PHDR) && defined(HAVE_LD_BUILD_ID) + #include <dlfcn.h> + #include <link.h> + #include <stddef.h> diff --git a/graphics/mesa/patches/patch-src_util_build_id_h b/graphics/mesa/patches/patch-src_util_build_id_h new file mode 100644 index 0000000..0560142 --- /dev/null +++ b/graphics/mesa/patches/patch-src_util_build_id_h @@ -0,0 +1,14 @@ +$OpenBSD$ + +Index: src/util/build_id.h +--- src/util/build_id.h.orig ++++ src/util/build_id.h +@@ -24,7 +24,7 @@ + #ifndef BUILD_ID_H + #define BUILD_ID_H + +-#ifdef HAVE_DL_ITERATE_PHDR ++#if defined(HAVE_DL_ITERATE_PHDR) && defined(HAVE_LD_BUILD_ID) + + struct build_id_note; + diff --git a/graphics/mesa/patches/patch-src_util_disk_cache_c b/graphics/mesa/patches/patch-src_util_disk_cache_c new file mode 100644 index 0000000..c73bb54 --- /dev/null +++ b/graphics/mesa/patches/patch-src_util_disk_cache_c @@ -0,0 +1,17 @@ +$OpenBSD$ + +Index: src/util/disk_cache.c +--- src/util/disk_cache.c.orig ++++ src/util/disk_cache.c +@@ -203,6 +203,11 @@ disk_cache_create(const char *gpu_name, const char *dr + uint8_t cache_version = CACHE_VERSION; + size_t cv_size = sizeof(cache_version); + ++#ifdef __OpenBSD__ ++ /* default to no disk shader cache to avoid pledge violations in chromium */ ++ return NULL; ++#endif ++ + /* If running as a users other than the real user disable cache */ + if (geteuid() != getuid()) + return NULL; diff --git a/graphics/mesa/patches/patch-src_util_disk_cache_h b/graphics/mesa/patches/patch-src_util_disk_cache_h new file mode 100644 index 0000000..dff5d65 --- /dev/null +++ b/graphics/mesa/patches/patch-src_util_disk_cache_h @@ -0,0 +1,14 @@ +$OpenBSD$ + +Index: src/util/disk_cache.h +--- src/util/disk_cache.h.orig ++++ src/util/disk_cache.h +@@ -120,7 +120,7 @@ disk_cache_get_function_identifier(void *ptr, struct m + { + uint32_t timestamp; + +-#ifdef HAVE_DL_ITERATE_PHDR ++#if defined(HAVE_DL_ITERATE_PHDR) && defined(HAVE_LD_BUILD_ID) + const struct build_id_note *note = NULL; + if ((note = build_id_find_nhdr_for_addr(ptr))) { + _mesa_sha1_update(ctx, build_id_data(note), build_id_length(note)); diff --git a/graphics/mesa/patches/patch-src_util_futex_h b/graphics/mesa/patches/patch-src_util_futex_h new file mode 100644 index 0000000..05e873d --- /dev/null +++ b/graphics/mesa/patches/patch-src_util_futex_h @@ -0,0 +1,30 @@ +$OpenBSD$ + +Index: src/util/futex.h +--- src/util/futex.h.orig ++++ src/util/futex.h +@@ -53,4 +53,24 @@ static inline int futex_wait(uint32_t *addr, int32_t v + + #endif + ++#ifdef __OpenBSD__ ++ ++#include <sys/time.h> ++#include <sys/futex.h> ++ ++static inline int futex_wake(uint32_t *addr, int count) ++{ ++ return futex(addr, FUTEX_WAKE, count, NULL, NULL); ++} ++ ++static inline int futex_wait(uint32_t *addr, int32_t value, const struct timespec *timeout) ++{ ++ struct timespec tsrel, tsnow; ++ clock_gettime(CLOCK_MONOTONIC, &tsnow); ++ timespecsub(timeout, &tsrel, &tsrel); ++ return futex(addr, FUTEX_WAIT, value, &tsrel, NULL); ++} ++ ++#endif ++ + #endif /* UTIL_FUTEX_H */ diff --git a/graphics/mesa/patches/patch-src_util_ralloc_h b/graphics/mesa/patches/patch-src_util_ralloc_h new file mode 100644 index 0000000..7a4bfa4 --- /dev/null +++ b/graphics/mesa/patches/patch-src_util_ralloc_h @@ -0,0 +1,44 @@ +$OpenBSD$ + +Index: src/util/ralloc.h +--- src/util/ralloc.h.orig ++++ src/util/ralloc.h +@@ -426,7 +426,7 @@ bool ralloc_vasprintf_append(char **str, const char *f + * + * which is more idiomatic in C++ than calling ralloc. + */ +-#define DECLARE_ALLOC_CXX_OPERATORS_TEMPLATE(TYPE, ALLOC_FUNC) \ ++#define DECLARE_ALLOC_CXX_OPERATORS_TEMPLATE(TYPE, ALLOC_FUNC, USE_DESTRUCTOR) \ + private: \ + static void _ralloc_destructor(void *p) \ + { \ +@@ -437,7 +437,7 @@ bool ralloc_vasprintf_append(char **str, const char *f + { \ + void *p = ALLOC_FUNC(mem_ctx, size); \ + assert(p != NULL); \ +- if (!HAS_TRIVIAL_DESTRUCTOR(TYPE)) \ ++ if (USE_DESTRUCTOR && !HAS_TRIVIAL_DESTRUCTOR(TYPE)) \ + ralloc_set_destructor(p, _ralloc_destructor); \ + return p; \ + } \ +@@ -454,16 +454,16 @@ bool ralloc_vasprintf_append(char **str, const char *f + } + + #define DECLARE_RALLOC_CXX_OPERATORS(type) \ +- DECLARE_ALLOC_CXX_OPERATORS_TEMPLATE(type, ralloc_size) ++ DECLARE_ALLOC_CXX_OPERATORS_TEMPLATE(type, ralloc_size, true) + + #define DECLARE_RZALLOC_CXX_OPERATORS(type) \ +- DECLARE_ALLOC_CXX_OPERATORS_TEMPLATE(type, rzalloc_size) ++ DECLARE_ALLOC_CXX_OPERATORS_TEMPLATE(type, rzalloc_size, true) + + #define DECLARE_LINEAR_ALLOC_CXX_OPERATORS(type) \ +- DECLARE_ALLOC_CXX_OPERATORS_TEMPLATE(type, linear_alloc_child) ++ DECLARE_ALLOC_CXX_OPERATORS_TEMPLATE(type, linear_alloc_child, false) + + #define DECLARE_LINEAR_ZALLOC_CXX_OPERATORS(type) \ +- DECLARE_ALLOC_CXX_OPERATORS_TEMPLATE(type, linear_zalloc_child) ++ DECLARE_ALLOC_CXX_OPERATORS_TEMPLATE(type, linear_zalloc_child, false) + + + /** diff --git a/graphics/mesa/patches/patch-src_util_rand_xor_c b/graphics/mesa/patches/patch-src_util_rand_xor_c new file mode 100644 index 0000000..250779c --- /dev/null +++ b/graphics/mesa/patches/patch-src_util_rand_xor_c @@ -0,0 +1,26 @@ +$OpenBSD$ + +Index: src/util/rand_xor.c +--- src/util/rand_xor.c.orig ++++ src/util/rand_xor.c +@@ -28,6 +28,7 @@ + #include <fcntl.h> + #else + #include <time.h> ++#include <stdlib.h> + #endif + + #include "rand_xor.h" +@@ -57,7 +58,11 @@ s_rand_xorshift128plus(uint64_t *seed, bool randomised + if (!randomised_seed) + goto fixed_seed; + +-#if defined(__linux__) ++#ifdef HAVE_ARC4RANDOM_BUF ++ size_t seed_size = sizeof(uint64_t) * 2; ++ arc4random_buf(seed, seed_size); ++ return; ++#elif defined(__linux__) + int fd = open("/dev/urandom", O_RDONLY); + if (fd < 0) + goto fixed_seed; diff --git a/graphics/mesa/patches/patch-src_util_u_atomic_c b/graphics/mesa/patches/patch-src_util_u_atomic_c new file mode 100644 index 0000000..278cb49 --- /dev/null +++ b/graphics/mesa/patches/patch-src_util_u_atomic_c @@ -0,0 +1,160 @@ +$OpenBSD$ + +Index: src/util/u_atomic.c +--- src/util/u_atomic.c.orig ++++ src/util/u_atomic.c +@@ -21,7 +21,8 @@ + * IN THE SOFTWARE. + */ + +-#if defined(MISSING_64BIT_ATOMICS) && defined(HAVE_PTHREAD) ++#if (defined(MISSING_32BIT_ATOMICS) || defined(MISSING_64BIT_ATOMICS)) && \ ++ defined(HAVE_PTHREAD) + + #include <stdint.h> + #include <pthread.h> +@@ -34,6 +35,129 @@ + + static pthread_mutex_t sync_mutex = PTHREAD_MUTEX_INITIALIZER; + ++#ifdef MISSING_32BIT_ATOMICS ++ ++WEAK uint8_t ++__sync_add_and_fetch_1(uint8_t *ptr, uint8_t val) ++{ ++ uint8_t r; ++ ++ pthread_mutex_lock(&sync_mutex); ++ *ptr += val; ++ r = *ptr; ++ pthread_mutex_unlock(&sync_mutex); ++ ++ return r; ++} ++ ++WEAK uint8_t ++__sync_sub_and_fetch_1(uint8_t *ptr, uint8_t val) ++{ ++ uint8_t r; ++ ++ pthread_mutex_lock(&sync_mutex); ++ *ptr -= val; ++ r = *ptr; ++ pthread_mutex_unlock(&sync_mutex); ++ ++ return r; ++} ++ ++WEAK uint8_t ++__sync_val_compare_and_swap_1(uint8_t *ptr, uint8_t oldval, uint8_t newval) ++{ ++ uint8_t r; ++ ++ pthread_mutex_lock(&sync_mutex); ++ r = *ptr; ++ if (*ptr == oldval) ++ *ptr = newval; ++ pthread_mutex_unlock(&sync_mutex); ++ ++ return r; ++} ++ ++WEAK uint16_t ++__sync_add_and_fetch_2(uint16_t *ptr, uint16_t val) ++{ ++ uint16_t r; ++ ++ pthread_mutex_lock(&sync_mutex); ++ *ptr += val; ++ r = *ptr; ++ pthread_mutex_unlock(&sync_mutex); ++ ++ return r; ++} ++ ++WEAK uint16_t ++__sync_sub_and_fetch_2(uint16_t *ptr, uint16_t val) ++{ ++ uint16_t r; ++ ++ pthread_mutex_lock(&sync_mutex); ++ *ptr -= val; ++ r = *ptr; ++ pthread_mutex_unlock(&sync_mutex); ++ ++ return r; ++} ++ ++WEAK uint16_t ++__sync_val_compare_and_swap_2(uint16_t *ptr, uint16_t oldval, uint16_t newval) ++{ ++ uint16_t r; ++ ++ pthread_mutex_lock(&sync_mutex); ++ r = *ptr; ++ if (*ptr == oldval) ++ *ptr = newval; ++ pthread_mutex_unlock(&sync_mutex); ++ ++ return r; ++} ++ ++WEAK uint32_t ++__sync_add_and_fetch_4(uint32_t *ptr, uint32_t val) ++{ ++ uint32_t r; ++ ++ pthread_mutex_lock(&sync_mutex); ++ *ptr += val; ++ r = *ptr; ++ pthread_mutex_unlock(&sync_mutex); ++ ++ return r; ++} ++ ++WEAK uint32_t ++__sync_sub_and_fetch_4(uint32_t *ptr, uint32_t val) ++{ ++ uint32_t r; ++ ++ pthread_mutex_lock(&sync_mutex); ++ *ptr -= val; ++ r = *ptr; ++ pthread_mutex_unlock(&sync_mutex); ++ ++ return r; ++} ++ ++WEAK uint32_t ++__sync_val_compare_and_swap_4(uint32_t *ptr, uint32_t oldval, uint32_t newval) ++{ ++ uint32_t r; ++ ++ pthread_mutex_lock(&sync_mutex); ++ r = *ptr; ++ if (*ptr == oldval) ++ *ptr = newval; ++ pthread_mutex_unlock(&sync_mutex); ++ ++ return r; ++} ++#endif /* MISSING_32BIT_ATOMICS */ ++ + WEAK uint64_t + __sync_add_and_fetch_8(uint64_t *ptr, uint64_t val) + { +@@ -60,6 +184,7 @@ __sync_sub_and_fetch_8(uint64_t *ptr, uint64_t val) + return r; + } + ++#ifdef USE_GCC_ATOMIC_BUILTINS + WEAK uint64_t + __sync_val_compare_and_swap_8(uint64_t *ptr, uint64_t oldval, uint64_t newval) + { +@@ -73,5 +198,6 @@ __sync_val_compare_and_swap_8(uint64_t *ptr, uint64_t + + return r; + } ++#endif /* USE_GCC_ATOMIC_BUILTINS */ + + #endif diff --git a/graphics/mesa/patches/patch-src_util_u_cpu_detect_c b/graphics/mesa/patches/patch-src_util_u_cpu_detect_c new file mode 100644 index 0000000..c89f92a --- /dev/null +++ b/graphics/mesa/patches/patch-src_util_u_cpu_detect_c @@ -0,0 +1,19 @@ +$OpenBSD$ + +Index: src/util/u_cpu_detect.c +--- src/util/u_cpu_detect.c.orig ++++ src/util/u_cpu_detect.c +@@ -162,10 +162,13 @@ check_os_altivec_support(void) + + util_cpu_caps.has_altivec = 1; + ++/* no support for POWER7 VSX instructions in binutils 2.17 */ ++#ifndef __OpenBSD__ + if (enable_vsx) { + __asm __volatile("xxland %vs0, %vs0, %vs0"); + util_cpu_caps.has_vsx = 1; + } ++#endif + signal(SIGILL, SIG_DFL); + } else { + util_cpu_caps.has_altivec = 0; diff --git a/graphics/mesa/patches/patch-src_util_u_endian_h b/graphics/mesa/patches/patch-src_util_u_endian_h new file mode 100644 index 0000000..818a3ed --- /dev/null +++ b/graphics/mesa/patches/patch-src_util_u_endian_h @@ -0,0 +1,39 @@ +$OpenBSD$ + +Index: src/util/u_endian.h +--- src/util/u_endian.h.orig ++++ src/util/u_endian.h +@@ -30,12 +30,20 @@ + #ifdef HAVE_ENDIAN_H + #include <endian.h> + +-#if __BYTE_ORDER == __LITTLE_ENDIAN ++/* glibc */ ++#if defined(__BYTE_ORDER) && (__BYTE_ORDER == __LITTLE_ENDIAN) + # define PIPE_ARCH_LITTLE_ENDIAN +-#elif __BYTE_ORDER == __BIG_ENDIAN ++#elif defined(__BYTE_ORDER) && (__BYTE_ORDER == __BIG_ENDIAN) + # define PIPE_ARCH_BIG_ENDIAN + #endif + ++/* OpenBSD */ ++#if defined(BYTE_ORDER) && (BYTE_ORDER == LITTLE_ENDIAN) ++# define PIPE_ARCH_LITTLE_ENDIAN ++#elif defined(BYTE_ORDER) && (BYTE_ORDER == BIG_ENDIAN) ++# define PIPE_ARCH_BIG_ENDIAN ++#endif ++ + #elif defined(__APPLE__) + #include <machine/endian.h> + +@@ -54,8 +62,8 @@ + # define PIPE_ARCH_BIG_ENDIAN + #endif + +-#elif defined(__OpenBSD__) || defined(__NetBSD__) || \ +- defined(__FreeBSD__) || defined(__DragonFly__) ++#elif defined(__NetBSD__) || defined(__FreeBSD__) || \ ++ defined(__DragonFly__) + #include <sys/types.h> + #include <machine/endian.h> + diff --git a/graphics/mesa/patches/patch-src_util_u_thread_h b/graphics/mesa/patches/patch-src_util_u_thread_h new file mode 100644 index 0000000..2304a55 --- /dev/null +++ b/graphics/mesa/patches/patch-src_util_u_thread_h @@ -0,0 +1,14 @@ +$OpenBSD$ + +Index: src/util/u_thread.h +--- src/util/u_thread.h.orig ++++ src/util/u_thread.h +@@ -134,7 +134,7 @@ util_get_L3_for_pinned_thread(thrd_t thread, unsigned + static inline int64_t + u_thread_get_time_nano(thrd_t thread) + { +-#if defined(__linux__) && defined(HAVE_PTHREAD) ++#if defined(HAVE_PTHREAD) + struct timespec ts; + clockid_t cid; + diff --git a/graphics/mesa/patches/patch-src_util_xmlconfig_c b/graphics/mesa/patches/patch-src_util_xmlconfig_c new file mode 100644 index 0000000..7a6dd42 --- /dev/null +++ b/graphics/mesa/patches/patch-src_util_xmlconfig_c @@ -0,0 +1,28 @@ +$OpenBSD$ + +Index: src/util/xmlconfig.c +--- src/util/xmlconfig.c.orig ++++ src/util/xmlconfig.c +@@ -991,6 +991,14 @@ driParseConfigFiles(driOptionCache *cache, const driOp + int screenNum, const char *driverName, + const char *kernelDriverName) + { ++#if defined(__OpenBSD__) ++ /* ++ * Opening drirc files is disabled by default so sandboxed ++ * browser processes with OpenGL contexts can drop the ability ++ * to read files. ++ */ ++ initOptionCache (cache, info); ++#else + char *home; + struct OptConfData userData; + +@@ -1011,6 +1019,7 @@ driParseConfigFiles(driOptionCache *cache, const driOp + snprintf(filename, PATH_MAX, "%s/.drirc", home); + parseOneConfigFile(&userData, filename); + } ++#endif + } + + void diff --git a/graphics/mesa/patches/patch-src_util_xmlpool_Makefile_am b/graphics/mesa/patches/patch-src_util_xmlpool_Makefile_am new file mode 100644 index 0000000..5920d2e --- /dev/null +++ b/graphics/mesa/patches/patch-src_util_xmlpool_Makefile_am @@ -0,0 +1,24 @@ +$OpenBSD$ + +Index: src/util/xmlpool/Makefile.am +--- src/util/xmlpool/Makefile.am.orig ++++ src/util/xmlpool/Makefile.am +@@ -74,15 +74,17 @@ clean-local: + + # Default target options.h + LOCALEDIR := . ++if REGEN_SOURCES + options.h: t_options.h $(MOS) + $(AM_V_GEN) $(PYTHON) $(PYTHON_FLAGS) $(srcdir)/gen_xmlpool.py \ + --template $(srcdir)/t_options.h \ + --output options.h \ + --localedir $(LOCALEDIR) \ + --languages $(LANGS) ++endif + + # Update .mo files from the corresponding .po files. +-%.gmo: %.po ++.po.gmo: + @mo="$@"; \ + lang=$${mo%%/*}; \ + echo "Updating ($$lang) $@ from $?."; \ diff --git a/graphics/mesa/patches/patch-src_vulkan_Makefile_am b/graphics/mesa/patches/patch-src_vulkan_Makefile_am new file mode 100644 index 0000000..34664e4 --- /dev/null +++ b/graphics/mesa/patches/patch-src_vulkan_Makefile_am @@ -0,0 +1,20 @@ +$OpenBSD$ + +Index: src/vulkan/Makefile.am +--- src/vulkan/Makefile.am.orig ++++ src/vulkan/Makefile.am +@@ -18,12 +18,14 @@ VULKAN_UTIL_SOURCES = \ + $(VULKAN_UTIL_FILES) \ + $(VULKAN_UTIL_GENERATED_FILES) + ++if REGEN_SOURCES + util/vk_enum_to_str.c util/vk_enum_to_str.h: util/gen_enum_to_str.py \ + $(vulkan_api_xml) + $(MKDIR_GEN) + $(PYTHON_GEN) $(srcdir)/util/gen_enum_to_str.py \ + --xml $(vulkan_api_xml) \ + --outdir $(top_builddir)/src/vulkan/util ++endif + + libvulkan_util_la_SOURCES = $(VULKAN_UTIL_SOURCES) + diff --git a/graphics/mesa/pkg/DESCR b/graphics/mesa/pkg/DESCR new file mode 100644 index 0000000..f3e9425 --- /dev/null +++ b/graphics/mesa/pkg/DESCR @@ -0,0 +1,14 @@ + The Mesa project began as an open-source implementation of the OpenGL + specification - a system for rendering interactive 3D graphics. + +Over the years the project has grown to implement more graphics APIs, +including OpenGL ES (versions 1, 2, 3), OpenCL, OpenMAX, VDPAU, VA +API, XvMC and Vulkan. + +A variety of device drivers allows the Mesa libraries to be used in +many different environments ranging from software emulation to +complete hardware acceleration for modern GPUs. + +Mesa ties into several other open-source projects: the Direct +Rendering Infrastructure and X.org to provide OpenGL support on Linux, +FreeBSD and other operating systems. diff --git a/graphics/mesa/pkg/PLIST b/graphics/mesa/pkg/PLIST new file mode 100644 index 0000000..5ab8bff --- /dev/null +++ b/graphics/mesa/pkg/PLIST @@ -0,0 +1,76 @@ +@comment $OpenBSD: PLIST,v$ +include/EGL/ +include/EGL/egl.h +include/EGL/eglext.h +include/EGL/eglextchromium.h +include/EGL/eglmesaext.h +include/EGL/eglplatform.h +include/GL/ +include/GL/gl.h +include/GL/gl_mangle.h +include/GL/glcorearb.h +include/GL/glext.h +include/GL/glx.h +include/GL/glx_mangle.h +include/GL/glxext.h +include/GL/internal/ +include/GL/internal/dri_interface.h +include/GL/osmesa.h +include/GLES/ +include/GLES/egl.h +include/GLES/gl.h +include/GLES/glext.h +include/GLES/glplatform.h +include/GLES2/ +include/GLES2/gl2.h +include/GLES2/gl2ext.h +include/GLES2/gl2platform.h +include/GLES3/ +include/GLES3/gl3.h +include/GLES3/gl31.h +include/GLES3/gl32.h +include/GLES3/gl3ext.h +include/GLES3/gl3platform.h +include/KHR/ +include/KHR/khrplatform.h +include/gbm.h +include/vulkan/ +include/vulkan/vulkan_intel.h +lib/libEGL.a +lib/libEGL.la +@lib lib/libEGL.so.${LIBEGL_VERSION} +lib/libGL.a +lib/libGL.la +@lib lib/libGL.so.${LIBGL_VERSION} +lib/libGLESv1_CM.a +lib/libGLESv1_CM.la +@lib lib/libGLESv1_CM.so.${LIBGLESv1_CM_VERSION} +lib/libGLESv2.a +lib/libGLESv2.la +@lib lib/libGLESv2.so.${LIBGLESv2_VERSION} +lib/libOSMesa.a +lib/libOSMesa.la +@lib lib/libOSMesa.so.${LIBOSMesa_VERSION} +lib/libgbm.a +lib/libgbm.la +@lib lib/libgbm.so.${LIBgbm_VERSION} +lib/libglapi.a +lib/libglapi.la +@lib lib/libglapi.so.${LIBglapi_VERSION} +lib/libvulkan_intel.a +lib/libvulkan_intel.la +lib/libvulkan_intel.so +lib/libvulkan_radeon.a +lib/libvulkan_radeon.la +lib/libvulkan_radeon.so +lib/pkgconfig/dri.pc +lib/pkgconfig/egl.pc +lib/pkgconfig/gbm.pc +lib/pkgconfig/gl.pc +lib/pkgconfig/glesv1_cm.pc +lib/pkgconfig/glesv2.pc +lib/pkgconfig/osmesa.pc +share/vulkan/ +share/vulkan/icd.d/ +share/vulkan/icd.d/intel_icd.x86_64.json +share/vulkan/icd.d/radeon_icd.x86_64.json |