diff options
| author | Michel Dänzer <michel.daenzer@amd.com> | 2015-06-01 18:33:33 +0900 |
|---|---|---|
| committer | Michel Dänzer <michel@daenzer.net> | 2015-06-08 17:04:31 +0900 |
| commit | a30060d22a42688371166a861e5050fdd5ce8f7b (patch) | |
| tree | 27e01f2a1dce5dab106092087c0a54c1d60a6306 /src/amdgpu_dri2.c | |
| parent | 9a554a683b970660b467566cf05b921393705a20 (diff) | |
DRI2: Split out helper for getting UST and MSC of a specific CRTC
(Cherry picked from radeon commits 76c2923ac5c7230a8b2f9f8329c308d28b44d9c0
and d7c82731a8bf3d381bc571b94d80d9bb2dd6e40d)
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'src/amdgpu_dri2.c')
| -rw-r--r-- | src/amdgpu_dri2.c | 34 |
1 files changed, 11 insertions, 23 deletions
diff --git a/src/amdgpu_dri2.c b/src/amdgpu_dri2.c index 95db216..28c56e7 100644 --- a/src/amdgpu_dri2.c +++ b/src/amdgpu_dri2.c @@ -851,17 +851,13 @@ CARD32 amdgpu_dri2_extrapolate_msc_delay(xf86CrtcPtr crtc, CARD64 * target_msc, } /* - * Get current frame count and frame count timestamp, based on drawable's - * crtc. + * Get current interpolated frame count and frame count timestamp, based on + * drawable's crtc. */ static int amdgpu_dri2_get_msc(DrawablePtr draw, CARD64 * ust, CARD64 * msc) { - ScreenPtr screen = draw->pScreen; - ScrnInfoPtr scrn = xf86ScreenToScrn(screen); - AMDGPUInfoPtr info = AMDGPUPTR(scrn); - drmVBlank vbl; - int ret; xf86CrtcPtr crtc = amdgpu_dri2_drawable_crtc(draw, TRUE); + int ret; /* Drawable not displayed, make up a value */ if (crtc == NULL) { @@ -869,29 +865,20 @@ static int amdgpu_dri2_get_msc(DrawablePtr draw, CARD64 * ust, CARD64 * msc) *msc = 0; return TRUE; } + if (amdgpu_crtc_is_enabled(crtc)) { /* CRTC is running, read vblank counter and timestamp */ - vbl.request.type = DRM_VBLANK_RELATIVE; - vbl.request.type |= amdgpu_populate_vbl_request_type(crtc); - vbl.request.sequence = 0; - - ret = drmWaitVBlank(info->dri2.drm_fd, &vbl); - if (ret) { - xf86DrvMsg(scrn->scrnIndex, X_WARNING, - "get vblank counter failed: %s\n", - strerror(errno)); + ret = drmmode_crtc_get_ust_msc(crtc, ust, msc); + if (ret != Success) return FALSE; - } - *ust = - ((CARD64) vbl.reply.tval_sec * 1000000) + - vbl.reply.tval_usec; - *msc = - vbl.reply.sequence + amdgpu_get_interpolated_vblanks(crtc); + *msc += amdgpu_get_interpolated_vblanks(crtc); *msc &= 0xffffffff; } else { /* CRTC is not running, extrapolate MSC and timestamp */ drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; + ScrnInfoPtr scrn = crtc->scrn; + AMDGPUInfoPtr info = AMDGPUPTR(scrn); CARD64 now, delta_t, delta_seq; if (!drmmode_crtc->dpms_last_ust) @@ -914,7 +901,8 @@ static int amdgpu_dri2_get_msc(DrawablePtr draw, CARD64 * ust, CARD64 * msc) *msc += delta_seq; *msc &= 0xffffffff; } - return TRUE; + + return ret == Success; } static |