Cleanup leading/trailing whitespace in source files

Signed-off-by: Alan Coopersmith <alan.coopersmith@oracle.com>

1 files changed, 498 insertions, 498 deletions

diff --git a/src/ast_vgatool.c b/src/ast_vgatool.c
index 964b826..04d311c 100644
--- a/src/ast_vgatool.c
+++ b/src/ast_vgatool.c
@@ -78,11 +78,11 @@ void GetAST1180DRAMInfo(ScrnInfoPtr pScrn);
 
 void
 vASTOpenKey(ScrnInfoPtr pScrn)
-{   	
+{
    ASTRecPtr pAST = ASTPTR(pScrn);
-   
-   SetIndexReg(CRTC_PORT,0x80, 0xA8);     
-   
+
+   SetIndexReg(CRTC_PORT,0x80, 0xA8);
+
 }
 
 Bool
@@ -97,34 +97,34 @@ bASTRegInit(ScrnInfoPtr pScrn)
 #if	defined(__sparc__)
    SetIndexRegMask(CRTC_PORT,0xA2, 0xFF, 0x80);
 #endif
-   
+
    return (TRUE);
-   	
+
 }
 
 void
 GetDRAMInfo(ScrnInfoPtr pScrn)
 {
     ASTRecPtr pAST = ASTPTR(pScrn);
-    ULONG ulRefPLL, ulDeNumerator, ulNumerator, ulDivider;    
+    ULONG ulRefPLL, ulDeNumerator, ulNumerator, ulDivider;
     ULONG ulData, ulData2;
-    
+
     *(ULONG *) (pAST->MMIOVirtualAddr + 0xF004) = 0x1e6e0000;
     *(ULONG *) (pAST->MMIOVirtualAddr + 0xF000) = 0x1;
-                    
+
     *(ULONG *) (pAST->MMIOVirtualAddr + 0x10000) = 0xFC600309;
     do {
-       ; 	
+       ;
     } while (*(volatile ULONG *) (pAST->MMIOVirtualAddr + 0x10000) != 0x01);
-    
+
     ulData = *(volatile ULONG *) (pAST->MMIOVirtualAddr + 0x10004);
-    
+
     /* Get BusWidth */
     if (ulData & 0x40)
        pAST->ulDRAMBusWidth = 16;
-    else    
+    else
        pAST->ulDRAMBusWidth = 32;
-    
+
     /* Get DRAM Type */
     if (pAST->jChipType == AST2300)
     {
@@ -132,67 +132,67 @@ GetDRAMInfo(ScrnInfoPtr pScrn)
         {
         case 0x00:
             pAST->jDRAMType = DRAMTYPE_512Mx16;
-            break;            
-        default:    
+            break;
+        default:
         case 0x01:
             pAST->jDRAMType = DRAMTYPE_1Gx16;
-            break;                        
+            break;
         case 0x02:
             pAST->jDRAMType = DRAMTYPE_2Gx16;
-            break;                        
-        case 0x03:	
+            break;
+        case 0x03:
             pAST->jDRAMType = DRAMTYPE_4Gx16;
-            break;                        
-        }	        	
+            break;
+        }
     }
     else
     {
         switch (ulData & 0x0C)
         {
-        case 0x00:	
+        case 0x00:
         case 0x04:
             pAST->jDRAMType = DRAMTYPE_512Mx16;
-            break;        
-    
+            break;
+
         case 0x08:
             if (ulData & 0x40)		/* 16bits */
                 pAST->jDRAMType = DRAMTYPE_1Gx16;
             else			/* 32bits */
                 pAST->jDRAMType = DRAMTYPE_512Mx32;
             break;
-        
+
         case 0x0C:
             pAST->jDRAMType = DRAMTYPE_1Gx32;
             break;
         }
-    }	
-                    
+    }
+
     /* Get MCLK */
-    ulData = *(ULONG *) (pAST->MMIOVirtualAddr + 0x10120);       
-    ulData2 = *(ULONG *) (pAST->MMIOVirtualAddr + 0x10170);       
+    ulData = *(ULONG *) (pAST->MMIOVirtualAddr + 0x10120);
+    ulData2 = *(ULONG *) (pAST->MMIOVirtualAddr + 0x10170);
     if (ulData2 & 0x2000)
         ulRefPLL = 14318;
     else
         ulRefPLL = 12000;
-        
+
     ulDeNumerator = ulData & 0x1F;
     ulNumerator = (ulData & 0x3FE0) >> 5;
-            
-    ulData = (ulData & 0xC000) >> 14;        
+
+    ulData = (ulData & 0xC000) >> 14;
     switch (ulData)
     {
     case 0x03:
         ulDivider = 0x04;
         break;
     case 0x02:
-    case 0x01:        
+    case 0x01:
         ulDivider = 0x02;
         break;
     default:
-        ulDivider = 0x01;                         
-    }        
-    pAST->ulMCLK = ulRefPLL * (ulNumerator + 2) / ((ulDeNumerator + 2) * ulDivider * 1000);                    
-      	
+        ulDivider = 0x01;
+    }
+    pAST->ulMCLK = ulRefPLL * (ulNumerator + 2) / ((ulDeNumerator + 2) * ulDivider * 1000);
+
 } /* GetDRAMInfo */
 
 ULONG
@@ -203,22 +203,22 @@ GetVRAMInfo(ScrnInfoPtr pScrn)
 
    vASTOpenKey(pScrn);
 
-   GetIndexRegMask(CRTC_PORT, 0xAA, 0xFF, jReg);  
+   GetIndexRegMask(CRTC_PORT, 0xAA, 0xFF, jReg);
 
    switch (jReg & 0x03)
    {
    case 0x00:
-       return (VIDEOMEM_SIZE_08M);           
+       return (VIDEOMEM_SIZE_08M);
    case 0x01:
-       return (VIDEOMEM_SIZE_16M);                  
+       return (VIDEOMEM_SIZE_16M);
    case 0x02:
-       return (VIDEOMEM_SIZE_32M);                 
-   case 0x03:	
-       return (VIDEOMEM_SIZE_64M); 
-   }                     
- 
+       return (VIDEOMEM_SIZE_32M);
+   case 0x03:
+       return (VIDEOMEM_SIZE_64M);
+   }
+
    return (DEFAULT_VIDEOMEM_SIZE);
-   	
+
 }
 
 ULONG
@@ -230,32 +230,32 @@ GetMaxDCLK(ScrnInfoPtr pScrn)
    ULONG ulDCLK;
 
    ulMCLK = pAST->ulMCLK;
-   ulDRAMBusWidth = pAST->ulDRAMBusWidth;       		
-   
+   ulDRAMBusWidth = pAST->ulDRAMBusWidth;
+
    /* Get Bandwidth */
    /* Modify DARM utilization to 60% for AST1100/2100 16bits DRAM, ycchen@032508 */
    if ( ((pAST->jChipType == AST2100) || (pAST->jChipType == AST1100) || (pAST->jChipType == AST2200) || (pAST->jChipType == AST2150)) && (ulDRAMBusWidth == 16) )
        DRAMEfficiency = 600;
    else if (pAST->jChipType == AST2300)
-       DRAMEfficiency = 400;   
+       DRAMEfficiency = 400;
    ulDRAMBandwidth = ulMCLK * ulDRAMBusWidth * 2 / 8;
    ActualDRAMBandwidth = ulDRAMBandwidth * DRAMEfficiency / 1000;
-   
+
    /* Get Max DCLK */
    if (pAST->jChipType == AST1180)
    {
        ulDCLK = ActualDRAMBandwidth / ((pScrn->bitsPerPixel+1) / 8);
    }
    else
-   {	   
-       /* Fixed Fixed KVM + CRT threshold issue on AST2100 8bpp modes, ycchen@100708 */    
-       GetIndexRegMask(CRTC_PORT, 0xD0, 0xFF, jReg);  
-       if ((jReg & 0x08) && (pAST->jChipType == AST2000))                     
-           ulDCLK = ActualDRAMBandwidth / ((pScrn->bitsPerPixel+1+16) / 8);	
+   {
+       /* Fixed Fixed KVM + CRT threshold issue on AST2100 8bpp modes, ycchen@100708 */
+       GetIndexRegMask(CRTC_PORT, 0xD0, 0xFF, jReg);
+       if ((jReg & 0x08) && (pAST->jChipType == AST2000))
+           ulDCLK = ActualDRAMBandwidth / ((pScrn->bitsPerPixel+1+16) / 8);
        else if ((jReg & 0x08) && (pScrn->bitsPerPixel == 8))
-           ulDCLK = ActualDRAMBandwidth / ((pScrn->bitsPerPixel+1+24) / 8);	       
-       else    
-           ulDCLK = ActualDRAMBandwidth / ((pScrn->bitsPerPixel+1) / 8);	   
+           ulDCLK = ActualDRAMBandwidth / ((pScrn->bitsPerPixel+1+24) / 8);
+       else
+           ulDCLK = ActualDRAMBandwidth / ((pScrn->bitsPerPixel+1) / 8);
    }
 
    /* Add for AST2100, ycchen@061807 */
@@ -265,11 +265,11 @@ GetMaxDCLK(ScrnInfoPtr pScrn)
    }
    else
    {
-       if (ulDCLK > 165) ulDCLK = 165;       
+       if (ulDCLK > 165) ulDCLK = 165;
    }
-    
+
    return(ulDCLK);
-   
+
 }
 
 void
@@ -278,30 +278,30 @@ GetChipType(ScrnInfoPtr pScrn)
    ASTRecPtr pAST = ASTPTR(pScrn);
    ULONG ulData;
    UCHAR jReg;
-   
+
    pAST->jChipType = AST2100;
 
    *(ULONG *) (pAST->MMIOVirtualAddr + 0xF004) = 0x1e6e0000;
-   *(ULONG *) (pAST->MMIOVirtualAddr + 0xF000) = 0x1;        
-   ulData = *(ULONG *) (pAST->MMIOVirtualAddr + 0x1207c);       
+   *(ULONG *) (pAST->MMIOVirtualAddr + 0xF000) = 0x1;
+   ulData = *(ULONG *) (pAST->MMIOVirtualAddr + 0x1207c);
    switch (ulData & 0x0300)
    {
    case 0x0200:
        xf86DrvMsg(pScrn->scrnIndex, X_INFO, "AST1100 Detected.\n");
-       pAST->jChipType = AST1100;   
+       pAST->jChipType = AST1100;
        break;
    case 0x0100:
-       xf86DrvMsg(pScrn->scrnIndex, X_INFO, "AST2200 Detected.\n");   
-       pAST->jChipType = AST2200;   
+       xf86DrvMsg(pScrn->scrnIndex, X_INFO, "AST2200 Detected.\n");
+       pAST->jChipType = AST2200;
        break;
    case 0x0000:
-       xf86DrvMsg(pScrn->scrnIndex, X_INFO, "AST2150 Detected.\n");   
-       pAST->jChipType = AST2150;   
+       xf86DrvMsg(pScrn->scrnIndex, X_INFO, "AST2150 Detected.\n");
+       pAST->jChipType = AST2150;
        break;
-   default:           
-       xf86DrvMsg(pScrn->scrnIndex, X_INFO, "AST2100 Detected.\n");   
+   default:
+       xf86DrvMsg(pScrn->scrnIndex, X_INFO, "AST2100 Detected.\n");
        pAST->jChipType = AST2100;
-   }	
+   }
 
 }
 
@@ -311,18 +311,18 @@ GetScratchOptions(ScrnInfoPtr pScrn)
    ASTRecPtr pAST = ASTPTR(pScrn);
    ULONG ulData;
    UCHAR jReg;
-   
-   /* VGA2 Clone Support */    
+
+   /* VGA2 Clone Support */
    GetIndexRegMask(CRTC_PORT, 0x90, 0xFF, jReg);
    if (jReg & 0x10)
        pAST->VGA2Clone = TRUE;
- 
+
    /* WideScreen Support */
    switch (pAST->jChipType)
    {
    case AST1180:
        pAST->SupportWideScreen = TRUE;
-       break; 	  
+       break;
    case AST2000:
        pAST->SupportWideScreen = FALSE;
        break;
@@ -330,7 +330,7 @@ GetScratchOptions(ScrnInfoPtr pScrn)
        GetIndexRegMask(CRTC_PORT, 0xD0, 0xFF, jReg);
        if (!(jReg & 0x80))
            pAST->SupportWideScreen = TRUE;
-       else if (jReg & 0x01)    
+       else if (jReg & 0x01)
            pAST->SupportWideScreen = TRUE;
        else
        {
@@ -338,34 +338,34 @@ GetScratchOptions(ScrnInfoPtr pScrn)
            if (pAST->jChipType == AST2300)	/* for AST1300 */
            {
                *(ULONG *) (pAST->MMIOVirtualAddr + 0xF004) = 0x1e6e0000;
-               *(ULONG *) (pAST->MMIOVirtualAddr + 0xF000) = 0x1;        
-               ulData = *(ULONG *) (pAST->MMIOVirtualAddr + 0x1207c);       
+               *(ULONG *) (pAST->MMIOVirtualAddr + 0xF000) = 0x1;
+               ulData = *(ULONG *) (pAST->MMIOVirtualAddr + 0x1207c);
                if ((ulData & 0x0300) == 0)	/* AST1300 */
-                   pAST->SupportWideScreen = TRUE;              
-           }        
-       }	              
+                   pAST->SupportWideScreen = TRUE;
+           }
+       }
     } /* switch case */
-       
+
 } /* GetScratchOptions */
 
 void
 vSetStartAddressCRT1(ASTRecPtr pAST, ULONG base)
 {
     ULONG addr;
-    	
+
     if (pAST->jChipType == AST1180)
     {
         addr = pAST->ulVRAMBase + base;
-        WriteAST1180SOC(AST1180_GFX_BASE + AST1180_VGA1_STARTADDR, addr);                        	
+        WriteAST1180SOC(AST1180_GFX_BASE + AST1180_VGA1_STARTADDR, addr);
     }
     else
     {
         addr = base >> 2;			/* DW unit */
-    			
+
         SetIndexReg(CRTC_PORT,0x0D, (UCHAR) (addr & 0xFF));
         SetIndexReg(CRTC_PORT,0x0C, (UCHAR) ((addr >> 8) & 0xFF));
         SetIndexReg(CRTC_PORT,0xAF, (UCHAR) ((addr >> 16) & 0xFF));
-    }    
+    }
 
 }
 
@@ -373,14 +373,14 @@ void
 vAST1000DisplayOff(ASTRecPtr pAST)
 {
     ULONG ulData;
-    	
+
     if (pAST->jChipType == AST1180)
     {
-        ReadAST1180SOC(AST1180_GFX_BASE + AST1180_VGA1_CTRL, ulData);                
-        ulData |= 0x00100000;    
-        WriteAST1180SOC(AST1180_GFX_BASE + AST1180_VGA1_CTRL, ulData);                
+        ReadAST1180SOC(AST1180_GFX_BASE + AST1180_VGA1_CTRL, ulData);
+        ulData |= 0x00100000;
+        WriteAST1180SOC(AST1180_GFX_BASE + AST1180_VGA1_CTRL, ulData);
     }
-    else    
+    else
         SetIndexRegMask(SEQ_PORT,0x01, 0xDF, 0x20);
 }
 
@@ -389,38 +389,38 @@ void
 vAST1000DisplayOn(ASTRecPtr pAST)
 {
    ULONG ulData;
-	
+
     if (pAST->jChipType == AST1180)
     {
-        ReadAST1180SOC(AST1180_GFX_BASE + AST1180_VGA1_CTRL, ulData);                
-        ulData &= 0xFFEFFFFF;    
-        WriteAST1180SOC(AST1180_GFX_BASE + AST1180_VGA1_CTRL, ulData);                
+        ReadAST1180SOC(AST1180_GFX_BASE + AST1180_VGA1_CTRL, ulData);
+        ulData &= 0xFFEFFFFF;
+        WriteAST1180SOC(AST1180_GFX_BASE + AST1180_VGA1_CTRL, ulData);
     }
     else
         SetIndexRegMask(SEQ_PORT,0x01, 0xDF, 0x00);
-}	
+}
 
 void ASTBlankScreen(ScrnInfoPtr pScrn, Bool unblack)
 {
    ASTRecPtr pAST;
 
    pAST = ASTPTR(pScrn);
-	
+
     if (unblack)
         vAST1000DisplayOn(pAST);
     else
-        vAST1000DisplayOff(pAST);	
-} 
+        vAST1000DisplayOff(pAST);
+}
 
 void
 vASTLoadPalette(ScrnInfoPtr pScrn, int numColors, int *indices, LOCO *colors,
                VisualPtr pVisual)
 {
-	
+
     ASTRecPtr  pAST = ASTPTR(pScrn);
     int     i, j, index;
     UCHAR DACIndex, DACR, DACG, DACB;
-  
+
     switch (pScrn->bitsPerPixel) {
     case 15:
         for(i=0; i<numColors; i++) {
@@ -430,12 +430,12 @@ vASTLoadPalette(ScrnInfoPtr pScrn, int numColors, int *indices, LOCO *colors,
                 DACR = colors[index].red << (8- pScrn->rgbBits);
                 DACG = colors[index].green << (8- pScrn->rgbBits);
                 DACB = colors[index].blue << (8- pScrn->rgbBits);
-                         
-                VGA_LOAD_PALETTE_INDEX (DACIndex, DACR, DACG, DACB);                         
+
+                VGA_LOAD_PALETTE_INDEX (DACIndex, DACR, DACG, DACB);
 	    }
         }
         break;
-        
+
     case 16:
         for(i=0; i<numColors; i++) {
             index = indices[i];
@@ -444,12 +444,12 @@ vASTLoadPalette(ScrnInfoPtr pScrn, int numColors, int *indices, LOCO *colors,
                 DACR = colors[index/2].red << (8- pScrn->rgbBits);
                 DACG = colors[index].green << (8- pScrn->rgbBits);
                 DACB = colors[index/2].blue << (8- pScrn->rgbBits);
-                         
-                VGA_LOAD_PALETTE_INDEX (DACIndex, DACR, DACG, DACB);                         
+
+                VGA_LOAD_PALETTE_INDEX (DACIndex, DACR, DACG, DACB);
 	    }
         }
         break;
-        
+
     case 24:
         for(i=0; i<numColors; i++) {
             index = indices[i];
@@ -457,11 +457,11 @@ vASTLoadPalette(ScrnInfoPtr pScrn, int numColors, int *indices, LOCO *colors,
             DACR = colors[index].red;
             DACG = colors[index].green;
             DACB = colors[index].blue;
-                         
-            VGA_LOAD_PALETTE_INDEX (DACIndex, DACR, DACG, DACB);                         
-        }    
+
+            VGA_LOAD_PALETTE_INDEX (DACIndex, DACR, DACG, DACB);
+        }
         break;
-        
+
     default:
         for(i=0; i<numColors; i++) {
             index = indices[i];
@@ -469,12 +469,12 @@ vASTLoadPalette(ScrnInfoPtr pScrn, int numColors, int *indices, LOCO *colors,
             DACR = colors[index].red >> (8 - pScrn->rgbBits);
             DACG = colors[index].green >> (8 - pScrn->rgbBits);
             DACB = colors[index].blue >> (8 - pScrn->rgbBits);
-                         
-            VGA_LOAD_PALETTE_INDEX (DACIndex, DACR, DACG, DACB);                         
-        }    
+
+            VGA_LOAD_PALETTE_INDEX (DACIndex, DACR, DACG, DACB);
+        }
 
     } /* end of switch */
-    
+
 } /* end of vASTLoadPalette */
 
 void
@@ -483,7 +483,7 @@ ASTDisplayPowerManagementSet(ScrnInfoPtr pScrn, int PowerManagementMode, int fla
    ASTRecPtr pAST;
    UCHAR SEQ01, CRB6;
    ULONG ulData, ulTemp;
-   
+
    pAST = ASTPTR(pScrn);
    SEQ01=CRB6=0;
    ulData = 0;
@@ -501,34 +501,34 @@ ASTDisplayPowerManagementSet(ScrnInfoPtr pScrn, int PowerManagementMode, int fla
       /* Screen: Off; HSync: Off, VSync: On */
       SEQ01 = 0x20;
       CRB6  = 0x01;
-      ulData = 0x00140000;      
+      ulData = 0x00140000;
       break;
    case DPMSModeSuspend:
       /* Screen: Off; HSync: On, VSync: Off */
       SEQ01 = 0x20;
       CRB6  = 0x02;
-      ulData = 0x00180000;      
+      ulData = 0x00180000;
       break;
    case DPMSModeOff:
       /* Screen: Off; HSync: Off, VSync: Off */
       SEQ01 = 0x20;
       CRB6  = 0x03;
-      ulData = 0x001C0000;            
+      ulData = 0x001C0000;
       break;
    }
 
    if (pAST->jChipType == AST1180)
    {
-       ReadAST1180SOC(AST1180_GFX_BASE + AST1180_VGA1_CTRL, ulTemp);                
-       ulTemp &= 0xFFE3FFFF; 
-       ulTemp |= ulData;  
-       WriteAST1180SOC(AST1180_GFX_BASE + AST1180_VGA1_CTRL, ulTemp);                
+       ReadAST1180SOC(AST1180_GFX_BASE + AST1180_VGA1_CTRL, ulTemp);
+       ulTemp &= 0xFFE3FFFF;
+       ulTemp |= ulData;
+       WriteAST1180SOC(AST1180_GFX_BASE + AST1180_VGA1_CTRL, ulTemp);
    }
    else
-   {  
+   {
        SetIndexRegMask(SEQ_PORT,0x01, 0xDF, SEQ01);
        SetIndexRegMask(CRTC_PORT,0xB6, 0xFC, CRB6);
-   }    
+   }
 
 }
 
@@ -545,11 +545,11 @@ Bool
 GetVGA2EDID(ScrnInfoPtr pScrn, unsigned char *pEDIDBuffer)
 {
     ASTRecPtr pAST = ASTPTR(pScrn);
-    ULONG i, ulData;    
+    ULONG i, ulData;
     UCHAR *pjEDID;
     ULONG base, deviceaddr;
     UCHAR *offset;
-    
+
     pjEDID = pEDIDBuffer;
 
     if (pAST->jChipType == AST1180)
@@ -563,16 +563,16 @@ GetVGA2EDID(ScrnInfoPtr pScrn, unsigned char *pEDIDBuffer)
         base   = I2C_BASE;
         offset = pAST->MMIOVirtualAddr + 0x10000 + I2C_OFFSET;
         deviceaddr = I2C_DEVICEADDR;
-    		
+
         /* SCU settings */
         *(ULONG *) (pAST->MMIOVirtualAddr + 0xF004) = 0x1e6e0000;
         *(ULONG *) (pAST->MMIOVirtualAddr + 0xF000) = 0x1;
         usleep(10000);
-     
-        *(ULONG *) (pAST->MMIOVirtualAddr + 0x12000) = 0x1688A8A8;    
+
+        *(ULONG *) (pAST->MMIOVirtualAddr + 0x12000) = 0x1688A8A8;
         ulData = *(ULONG *) (pAST->MMIOVirtualAddr + 0x12004);
         ulData &= 0xfffffffb;
-        *(ULONG *) (pAST->MMIOVirtualAddr + 0x12004) = ulData;    
+        *(ULONG *) (pAST->MMIOVirtualAddr + 0x12004) = ulData;
         usleep(10000);
     }
 
@@ -580,7 +580,7 @@ GetVGA2EDID(ScrnInfoPtr pScrn, unsigned char *pEDIDBuffer)
     *(ULONG *) (pAST->MMIOVirtualAddr + 0xF004) = base;
     *(ULONG *) (pAST->MMIOVirtualAddr + 0xF000) = 0x1;
     usleep(10000);
-    
+
     /* I2C Start */
     *(ULONG *) (offset + 0x00) = 0x0;
     *(ULONG *) (offset + 0x04) = 0x77777355;
@@ -603,11 +603,11 @@ GetVGA2EDID(ScrnInfoPtr pScrn, unsigned char *pEDIDBuffer)
     } while (!(ulData & 0x01));
     *(ULONG *) (offset + 0x10) = 0xffffffff;
     *(ULONG *) (offset + 0x20) = deviceaddr + 1;
-    *(ULONG *) (offset + 0x14) = 0x03; 
+    *(ULONG *) (offset + 0x14) = 0x03;
     do {
         ulData = *(volatile ULONG *) (offset + 0x10);
     } while (!(ulData & 0x01));
-    
+
     /* I2C Read */
     for (i=0; i<127; i++)
     {
@@ -618,7 +618,7 @@ GetVGA2EDID(ScrnInfoPtr pScrn, unsigned char *pEDIDBuffer)
             ulData = *(volatile ULONG *) (offset + 0x10);
         } while (!(ulData & 0x04));
         *(ULONG *) (offset + 0x10) = 0xffffffff;
-        *(UCHAR *) (pjEDID++) = (UCHAR) ((*(ULONG *) (offset + 0x20) & 0xFF00) >> 8);        	
+        *(UCHAR *) (pjEDID++) = (UCHAR) ((*(ULONG *) (offset + 0x20) & 0xFF00) >> 8);
     }
 
     /* Read Last Byte */
@@ -629,7 +629,7 @@ GetVGA2EDID(ScrnInfoPtr pScrn, unsigned char *pEDIDBuffer)
         ulData = *(volatile ULONG *) (offset + 0x10);
     } while (!(ulData & 0x04));
     *(ULONG *) (offset + 0x10) = 0xffffffff;
-    *(UCHAR *) (pjEDID++) = (UCHAR) ((*(ULONG *) (offset + 0x20) & 0xFF00) >> 8);        	
+    *(UCHAR *) (pjEDID++) = (UCHAR) ((*(ULONG *) (offset + 0x20) & 0xFF00) >> 8);
 
     /* I2C Stop	 */
     *(ULONG *) (offset + 0x10) = 0xffffffff;
@@ -637,9 +637,9 @@ GetVGA2EDID(ScrnInfoPtr pScrn, unsigned char *pEDIDBuffer)
     do {
         ulData = *(volatile ULONG *) (offset + 0x10);
     } while (!(ulData & 0x10));
-    *(ULONG *) (offset + 0x0C) &= 0xffffffef;        
+    *(ULONG *) (offset + 0x0C) &= 0xffffffef;
     *(ULONG *) (offset + 0x10) = 0xffffffff;
-    
+
     return (TRUE);
 
 } /* GetVGA2EDID */
@@ -650,44 +650,44 @@ Bool bIsVGAEnabled(ScrnInfoPtr pScrn)
     ASTRecPtr pAST;
     UCHAR ch;
     ULONG ulData;
-   
+
     pAST = ASTPTR(pScrn);
 
     if (pAST->jChipType == AST1180)
     {
         WriteAST1180SOC(AST1180_MMC_BASE+0x00, 0xFC600309);	/* unlock */
         ReadAST1180SOC(AST1180_MMC_BASE+0x08, ulData);
-        return (ulData);    	
-    }	
-    else    
+        return (ulData);
+    }
+    else
     {
-    	
+
         ch = GetReg(VGA_ENABLE_PORT);
 
         if (ch)
         {
-    	
+
             vASTOpenKey(pScrn);
-        
-            GetIndexRegMask(CRTC_PORT, 0xB6, 0xFF, ch);  
-        
+
+            GetIndexRegMask(CRTC_PORT, 0xB6, 0xFF, ch);
+
             return (ch & 0x04);
         }
     }
-    
-    return (0);	
-}	
+
+    return (0);
+}
 
 void vEnableVGA(ScrnInfoPtr pScrn)
 {
     ASTRecPtr pAST;
-   
+
     pAST = ASTPTR(pScrn);
 
     SetReg(VGA_ENABLE_PORT, 0x01);
-    SetReg(MISC_PORT_WRITE, 0x01);   
-	
-}	
+    SetReg(MISC_PORT_WRITE, 0x01);
+
+}
 
 UCHAR ExtRegInfo[] = {
     0x0F,
@@ -714,7 +714,7 @@ void vSetDefExtReg(ScrnInfoPtr pScrn)
 {
     ASTRecPtr pAST;
     UCHAR i, jIndex, jReg, *pjExtRegInfo;
-   
+
     pAST = ASTPTR(pScrn);
 
     /* Reset Scratch */
@@ -729,8 +729,8 @@ void vSetDefExtReg(ScrnInfoPtr pScrn)
        if (PCI_DEV_REVISION(pAST->PciInfo) > 0x20)
            pjExtRegInfo = ExtRegInfo_AST2300;
        else
-           pjExtRegInfo = ExtRegInfo_AST2300A0;           
-    }    
+           pjExtRegInfo = ExtRegInfo_AST2300A0;
+    }
     else
         pjExtRegInfo = ExtRegInfo;
 
@@ -744,18 +744,18 @@ void vSetDefExtReg(ScrnInfoPtr pScrn)
 
     /* disable standard IO/MEM decode if secondary */
     if (!xf86IsPrimaryPci(pAST->PciInfo))
-        SetIndexRegMask(CRTC_PORT,0xA1, 0xFF, 0x03);    	
+        SetIndexRegMask(CRTC_PORT,0xA1, 0xFF, 0x03);
 
     /* Set Ext. Default */
-    SetIndexRegMask(CRTC_PORT,0x8C, 0x00, 0x01);    	
-    SetIndexRegMask(CRTC_PORT,0xB7, 0x00, 0x00);    	
-    
+    SetIndexRegMask(CRTC_PORT,0x8C, 0x00, 0x01);
+    SetIndexRegMask(CRTC_PORT,0xB7, 0x00, 0x00);
+
     /* Enable RAMDAC for A1, ycchen@113005 */
     jReg = 0x04;
     if (pAST->jChipType == AST2300)
         jReg |= 0x20;
-    SetIndexRegMask(CRTC_PORT,0xB6, 0xFF, jReg);    	
-      	
+    SetIndexRegMask(CRTC_PORT,0xB6, 0xFF, jReg);
+
 }
 
 __inline ULONG MIndwm(UCHAR *mmiobase, ULONG r)
@@ -764,15 +764,15 @@ __inline ULONG MIndwm(UCHAR *mmiobase, ULONG r)
     *(ULONG *) (mmiobase + 0xF000) = 0x1;
 
     return ( *(volatile ULONG *) (mmiobase + 0x10000 + (r & 0x0000FFFF)) );
-    	
+
 }
 
 __inline void MOutdwm(UCHAR *mmiobase, ULONG r, ULONG v)
 {
-    
+
     *(ULONG *) (mmiobase + 0xF004) = r & 0xFFFF0000;
     *(ULONG *) (mmiobase + 0xF000) = 0x1;
-    
+
     *(volatile ULONG *) (mmiobase + 0x10000 + (r & 0x0000FFFF)) = v;
 }
 
@@ -810,7 +810,7 @@ typedef struct _AST2150DRAMParam {
 ULONG MMCTestBurst2_AST2150(PAST2150DRAMParam  param, ULONG datagen)
 {
   ULONG data, timeout;
-  UCHAR *mmiobase;	
+  UCHAR *mmiobase;
 
   mmiobase = param->pjMMIOVirtualAddress;
 
@@ -842,7 +842,7 @@ ULONG MMCTestBurst2_AST2150(PAST2150DRAMParam  param, ULONG datagen)
 ULONG MMCTestSingle2_AST2150(PAST2150DRAMParam  param, ULONG datagen)
 {
   ULONG data, timeout;
-  UCHAR *mmiobase;	
+  UCHAR *mmiobase;
 
   mmiobase = param->pjMMIOVirtualAddress;
 
@@ -863,7 +863,7 @@ ULONG MMCTestSingle2_AST2150(PAST2150DRAMParam  param, ULONG datagen)
 
 int CBRTest_AST2150(PAST2150DRAMParam  param)
 {
-  UCHAR *mmiobase;	
+  UCHAR *mmiobase;
 
   mmiobase = param->pjMMIOVirtualAddress;
 
@@ -882,7 +882,7 @@ int CBRTest_AST2150(PAST2150DRAMParam  param)
 int CBRScan_AST2150(PAST2150DRAMParam  param, int busw)
 {
   ULONG patcnt, loop;
-  UCHAR *mmiobase;	
+  UCHAR *mmiobase;
 
   mmiobase = param->pjMMIOVirtualAddress;
 
@@ -904,7 +904,7 @@ int CBRScan_AST2150(PAST2150DRAMParam  param, int busw)
 void CBRDLLI_AST2150(PAST2150DRAMParam  param, int busw)
 {
   ULONG dllmin[4], dllmax[4], dlli, data, passcnt;
-  UCHAR *mmiobase;	
+  UCHAR *mmiobase;
 
   mmiobase = param->pjMMIOVirtualAddress;
 
@@ -938,22 +938,22 @@ void CBRDLLI_AST2150(PAST2150DRAMParam  param, int busw)
 }
 
 typedef struct _AST_DRAMStruct {
-	
+
     USHORT 	Index;
     ULONG	Data;
-    
-} AST_DRAMStruct, *PAST_DRAMStruct; 
+
+} AST_DRAMStruct, *PAST_DRAMStruct;
 
 AST_DRAMStruct AST2000DRAMTableData[] = {
     { 0x0108, 0x00000000 },
     { 0x0120, 0x00004a21 },
-    { 0xFF00, 0x00000043 },   	
+    { 0xFF00, 0x00000043 },
     { 0x0000, 0xFFFFFFFF },
     { 0x0004, 0x00000089 },
     { 0x0008, 0x22331353 },
     { 0x000C, 0x0d07000b },
     { 0x0010, 0x11113333 },
-    { 0x0020, 0x00110350 },   
+    { 0x0020, 0x00110350 },
     { 0x0028, 0x1e0828f0 },
     { 0x0024, 0x00000001 },
     { 0x001C, 0x00000000 },
@@ -972,7 +972,7 @@ AST_DRAMStruct AST2000DRAMTableData[] = {
     { 0xFFFF, 0xFFFFFFFF }
 };
 
-AST_DRAMStruct AST1100DRAMTableData[] = {	
+AST_DRAMStruct AST1100DRAMTableData[] = {
     { 0x2000, 0x1688a8a8 },
     { 0x2020, 0x000041f0 },
     { 0xFF00, 0x00000043 },
@@ -1025,7 +1025,7 @@ AST_DRAMStruct AST1100DRAMTableData[] = {
     { 0xffff, 0xffffffff },
 };
 
-AST_DRAMStruct AST2100DRAMTableData[] = {	
+AST_DRAMStruct AST2100DRAMTableData[] = {
     { 0x2000, 0x1688a8a8 },
     { 0x2020, 0x00004120 },
     { 0xFF00, 0x00000043 },
@@ -1086,71 +1086,71 @@ void vInitDRAMReg(ScrnInfoPtr pScrn)
     UCHAR jReg;
     AST2150DRAMParam param;
 
-    GetIndexRegMask(CRTC_PORT, 0xD0, 0xFF, jReg);  
-    
+    GetIndexRegMask(CRTC_PORT, 0xD0, 0xFF, jReg);
+
     if ((jReg & 0x80) == 0)			/* VGA only */
     {
     	if (pAST->jChipType == AST2000)
     	{
             pjDRAMRegInfo = AST2000DRAMTableData;
-            
+
             *(ULONG *) (pAST->MMIOVirtualAddr + 0xF004) = 0x1e6e0000;
-            *(ULONG *) (pAST->MMIOVirtualAddr + 0xF000) = 0x1;        
+            *(ULONG *) (pAST->MMIOVirtualAddr + 0xF000) = 0x1;
             *(ULONG *) (pAST->MMIOVirtualAddr + 0x10100) = 0xa8;
 
             do {
-               ; 	
+               ;
             } while (*(volatile ULONG *) (pAST->MMIOVirtualAddr + 0x10100) != 0xa8);
-                
+
         }
-    	else	/* AST2100/1100 */	
-    	{           
+    	else	/* AST2100/1100 */
+    	{
     	    if ((pAST->jChipType == AST2100) || (pAST->jChipType == AST2200))
                 pjDRAMRegInfo = AST2100DRAMTableData;
     	    else
                 pjDRAMRegInfo = AST1100DRAMTableData;
-    		
+
             *(ULONG *) (pAST->MMIOVirtualAddr + 0xF004) = 0x1e6e0000;
             *(ULONG *) (pAST->MMIOVirtualAddr + 0xF000) = 0x1;
-            
+
             *(ULONG *) (pAST->MMIOVirtualAddr + 0x12000) = 0x1688A8A8;
             do {
-               ; 	
+               ;
             } while (*(volatile ULONG *) (pAST->MMIOVirtualAddr + 0x12000) != 0x01);
-            
+
             *(ULONG *) (pAST->MMIOVirtualAddr + 0x10000) = 0xFC600309;
             do {
-               ; 	
+               ;
             } while (*(volatile ULONG *) (pAST->MMIOVirtualAddr + 0x10000) != 0x01);
 
         }
-	
+
         while (pjDRAMRegInfo->Index != 0xFFFF)
         {
             if (pjDRAMRegInfo->Index == 0xFF00)			/* Delay function */
             {
-            	for (i=0; i<15; i++)				
+            	for (i=0; i<15; i++)
         	    usleep(pjDRAMRegInfo->Data);
             }
             else if ( (pjDRAMRegInfo->Index == 0x0004) && (pAST->jChipType != AST2000) )
             {
             	ulData = pjDRAMRegInfo->Data;
-            	
+
             	if (pAST->jDRAMType == DRAMTYPE_1Gx16)
             	    ulData = 0x00000d89;
             	else if (pAST->jDRAMType == DRAMTYPE_1Gx32)
             	    ulData = 0x00000c8d;
-            	        
+
                 ulTemp = *(ULONG *) (pAST->MMIOVirtualAddr + 0x12070);
                 ulTemp &= 0x0000000C;
-                ulTemp <<= 2;                
-                *(ULONG *) (pAST->MMIOVirtualAddr + 0x10000 + pjDRAMRegInfo->Index) = (ulData | ulTemp);               
-            }	                
+                ulTemp <<= 2;
+                *(ULONG *) (pAST->MMIOVirtualAddr + 0x10000 + pjDRAMRegInfo->Index) = (ulData | ulTemp);
+            }
             else
-            {	           	           
+            {
                 *(ULONG *) (pAST->MMIOVirtualAddr + 0x10000 + pjDRAMRegInfo->Index) = pjDRAMRegInfo->Data;
             }
-            pjDRAMRegInfo++;            
+            pjDRAMRegInfo++;
         }
 
         /* AST2100/2150 DRAM Calibration, ycchen@021511 */
@@ -1161,37 +1161,37 @@ void vInitDRAMReg(ScrnInfoPtr pScrn)
             ulData = *(ULONG *) (pAST->MMIOVirtualAddr + 0x10004);
             if (ulData & 0x40)
                 CBRDLLI_AST2150(&param, 16);		/* 16bits */
-            else 
+            else
                 CBRDLLI_AST2150(&param, 32);            /* 32bits */
-        }    
+        }
 
         switch (pAST->jChipType)
         {
         case AST2000:
             *(ULONG *) (pAST->MMIOVirtualAddr + 0x10140) |= 0x40;
             break;
-            
+
         case AST1100:
         case AST2100:
         case AST2200:
-        case AST2150:        
+        case AST2150:
             ulTemp = *(ULONG *) (pAST->MMIOVirtualAddr + 0x1200c);
             *(ULONG *) (pAST->MMIOVirtualAddr + 0x1200c) = (ulTemp & 0xFFFFFFFD);
 
             *(ULONG *) (pAST->MMIOVirtualAddr + 0x12040) |= 0x40;
             break;
         }
-	            	
+
     } /* Init DRAM */
-    
+
     /* wait ready */
     do {
-        GetIndexRegMask(CRTC_PORT, 0xD0, 0xFF, jReg);      	
+        GetIndexRegMask(CRTC_PORT, 0xD0, 0xFF, jReg);
     } while ((jReg & 0x40) == 0);
-       
+
 } /* vInitDRAMReg */
 
-/* 
+/*
  * AST2300 DRAM settings modules
  */
 #define	DDR3		0
@@ -1208,7 +1208,7 @@ typedef struct _AST2300DRAMParam {
     ULONG	RODT;
 
     ULONG	DRAM_CONFIG;
-    ULONG	REG_PERIOD;    
+    ULONG	REG_PERIOD;
     ULONG  	REG_MADJ;
     ULONG	REG_SADJ;
     ULONG	REG_MRS;
@@ -1216,13 +1216,13 @@ typedef struct _AST2300DRAMParam {
     ULONG	REG_AC1;
     ULONG	REG_AC2;
     ULONG	REG_DQSIC;
-    ULONG	REG_DRV;    
+    ULONG	REG_DRV;
     ULONG	REG_IOZ;
     ULONG	REG_DQIDLY;
     ULONG	REG_FREQ;
     ULONG       MADJ_MAX;
     ULONG       DLL2_FINETUNE_STEP;
-    
+
 } AST2300DRAMParam, *PAST2300DRAMParam;
 
 /*
@@ -1250,10 +1250,10 @@ ULONG pattern[8] ={
 int MMCTestBurst(PAST2300DRAMParam  param, ULONG datagen)
 {
   ULONG data, timeout;
-  UCHAR *mmiobase;	
+  UCHAR *mmiobase;
 
   mmiobase = param->pjMMIOVirtualAddress;
-  
+
   MOutdwm(mmiobase, 0x1E6E0070, 0x00000000);
   MOutdwm(mmiobase, 0x1E6E0070, 0x000000C1 | (datagen << 3));
   timeout = 0;
@@ -1274,7 +1274,7 @@ int MMCTestBurst(PAST2300DRAMParam  param, ULONG datagen)
 int MMCTestBurst2(PAST2300DRAMParam  param, ULONG datagen)
 {
   ULONG data, timeout;
-  UCHAR *mmiobase;	
+  UCHAR *mmiobase;
 
   mmiobase = param->pjMMIOVirtualAddress;
 
@@ -1297,7 +1297,7 @@ int MMCTestBurst2(PAST2300DRAMParam  param, ULONG datagen)
 int MMCTestSingle(PAST2300DRAMParam  param, ULONG datagen)
 {
   ULONG data, timeout;
-  UCHAR *mmiobase;	
+  UCHAR *mmiobase;
 
   mmiobase = param->pjMMIOVirtualAddress;
 
@@ -1321,7 +1321,7 @@ int MMCTestSingle(PAST2300DRAMParam  param, ULONG datagen)
 int MMCTestSingle2(PAST2300DRAMParam  param, ULONG datagen)
 {
   ULONG data, timeout;
-  UCHAR *mmiobase;	
+  UCHAR *mmiobase;
 
   mmiobase = param->pjMMIOVirtualAddress;
 
@@ -1344,7 +1344,7 @@ int MMCTestSingle2(PAST2300DRAMParam  param, ULONG datagen)
 int CBRTest(PAST2300DRAMParam  param)
 {
   ULONG data;
-  UCHAR *mmiobase;	
+  UCHAR *mmiobase;
 
   mmiobase = param->pjMMIOVirtualAddress;
 
@@ -1359,14 +1359,14 @@ int CBRTest(PAST2300DRAMParam  param)
   data |= MMCTestBurst2(param, 07);  if((data & 0xff) && (data & 0xff00)) return(0);
   if(!data)            return(3);
   else if(data & 0xff) return(2);
-  
+
   return(1);
 }
 
 int CBRScan(PAST2300DRAMParam  param)
 {
   ULONG data, data2, patcnt, loop;
-  UCHAR *mmiobase;	
+  UCHAR *mmiobase;
 
   mmiobase = param->pjMMIOVirtualAddress;
 
@@ -1392,7 +1392,7 @@ int CBRScan(PAST2300DRAMParam  param)
 ULONG CBRTest2(PAST2300DRAMParam  param)
 {
   ULONG data;
-  UCHAR *mmiobase;	
+  UCHAR *mmiobase;
 
   mmiobase = param->pjMMIOVirtualAddress;
 
@@ -1404,7 +1404,7 @@ ULONG CBRTest2(PAST2300DRAMParam  param)
 ULONG CBRScan2(PAST2300DRAMParam  param)
 {
   ULONG data, data2, patcnt, loop;
-  UCHAR *mmiobase;	
+  UCHAR *mmiobase;
 
   mmiobase = param->pjMMIOVirtualAddress;
 
@@ -1430,7 +1430,7 @@ ULONG CBRScan2(PAST2300DRAMParam  param)
 void finetuneDQI(PAST2300DRAMParam  param)
 {
   ULONG gold_sadj[2], dllmin[16], dllmax[16], dlli, data, cnt, mask, passcnt;
-  UCHAR *mmiobase;	
+  UCHAR *mmiobase;
 
   mmiobase = param->pjMMIOVirtualAddress;
 
@@ -1527,7 +1527,7 @@ void finetuneDQI(PAST2300DRAMParam  param)
 Bool finetuneDQI_L(PAST2300DRAMParam  param)
 {
   ULONG gold_sadj[2], dllmin[16], dllmax[16], dlli, data, cnt, mask, passcnt, retry = 0;
-  UCHAR *mmiobase;	
+  UCHAR *mmiobase;
   Bool status = FALSE;
 
   mmiobase = param->pjMMIOVirtualAddress;
@@ -1582,8 +1582,8 @@ Bool finetuneDQI_L(PAST2300DRAMParam  param)
     goto FINETUNE_START;
   }
   status = TRUE;
- 
-FINETUNE_DONE:  
+
+FINETUNE_DONE:
   gold_sadj[0] = gold_sadj[0] >> 4;
   gold_sadj[1] = gold_sadj[0];
 
@@ -1635,13 +1635,13 @@ FINETUNE_DONE:
   MOutdwm(mmiobase, 0x1E6E0084, data);
 
   return status;
-  
+
 } /* finetuneDQI_L */
 
 void finetuneDQI_L2(PAST2300DRAMParam  param)
 {
   ULONG gold_sadj[2], dllmin[16], dllmax[16], dlli, data, cnt, mask, passcnt, data2;
-  UCHAR *mmiobase;	
+  UCHAR *mmiobase;
 
   mmiobase = param->pjMMIOVirtualAddress;
 
@@ -1767,13 +1767,13 @@ void finetuneDQI_L2(PAST2300DRAMParam  param)
     data |= data2 << 21;
   }
   MOutdwm(mmiobase, 0x1E6E0084, data);
-  
+
 } /* finetuneDQI_L2 */
 
 Bool CBRDLL2(PAST2300DRAMParam  param)
 {
   ULONG dllmin[2], dllmax[2], dlli, data, data2, passcnt, retry=0;
-  UCHAR *mmiobase;	
+  UCHAR *mmiobase;
   BOOL status = FALSE;
 
   mmiobase = param->pjMMIOVirtualAddress;
@@ -1829,7 +1829,7 @@ Bool CBRDLL2(PAST2300DRAMParam  param)
     goto CBR_START2;
   }
   status = TRUE;
-  
+
 CBR_DONE2:
   dlli  = (dllmin[1] + dllmax[1]) >> 1;
   dlli <<= 8;
@@ -1852,32 +1852,32 @@ CBR_DONE2:
     data = MIndwm(mmiobase, 0x1E6E0070);
   }while(!(data & 0x00001000));
   MOutdwm(mmiobase, 0x1E6E0070, 0x00000000);
-  
+
   return status;
-  
+
 } /* CBRDLL2 */
 
 void GetDDR2Info(PAST2300DRAMParam param)
 {
   UCHAR *mmiobase;
   ULONG trap, TRAP_AC2, TRAP_MRS;
-  
+
   mmiobase = param->pjMMIOVirtualAddress;
   MOutdwm(mmiobase, 0x1E6E2000, 0x1688A8A8);
 
-  /* Ger trap info */  
+  /* Ger trap info */
   trap = (MIndwm(mmiobase, 0x1E6E2070) >> 25) & 0x3;
   TRAP_AC2  = (trap << 20) | (trap << 16);
   TRAP_AC2 += 0x00110000;
   TRAP_MRS  = 0x00000040 | (trap << 4);
-  
-  
+
+
   param->REG_MADJ 	= 0x00034C4C;
   param->REG_SADJ	= 0x00001800;
   param->REG_DRV        = 0x000000F0;
   param->REG_PERIOD     = param->DRAM_Freq;
   param->RODT		= 0;
-	
+
   switch(param->DRAM_Freq){
     case 264 : MOutdwm(mmiobase, 0x1E6E2020, 0x0130);
                param->WODT          = 0;
@@ -1906,24 +1906,24 @@ void GetDDR2Info(PAST2300DRAMParam param)
                param->REG_FREQ      = 0x00004DC0;
                param->MADJ_MAX      = 96;
                param->DLL2_FINETUNE_STEP = 3;
-               
+
                switch (param->DRAM_ChipID)
                {
-               case DRAMTYPE_512Mx16:	
+               case DRAMTYPE_512Mx16:
                    param->REG_AC2   = 0xAA009012 | TRAP_AC2;
                    break;
-               default:    
-               case DRAMTYPE_1Gx16:	
+               default:
+               case DRAMTYPE_1Gx16:
                    param->REG_AC2   = 0xAA009016 | TRAP_AC2;
                    break;
-               case DRAMTYPE_2Gx16:	
+               case DRAMTYPE_2Gx16:
                    param->REG_AC2   = 0xAA009023 | TRAP_AC2;
                    break;
-               case DRAMTYPE_4Gx16:	
+               case DRAMTYPE_4Gx16:
                    param->REG_AC2   = 0xAA00903B | TRAP_AC2;
-                   break;               	
+                   break;
                }
-                
+
                break;
     default:
     case 396 : MOutdwm(mmiobase, 0x1E6E2020, 0x03F1);
@@ -1940,26 +1940,26 @@ void GetDDR2Info(PAST2300DRAMParam param)
                param->REG_FREQ      = 0x000050C0;
                param->MADJ_MAX      = 96;
                param->DLL2_FINETUNE_STEP = 4;
-               
+
                switch (param->DRAM_ChipID)
                {
-               case DRAMTYPE_512Mx16:	
+               case DRAMTYPE_512Mx16:
                    param->REG_AC2   = 0xCC00B016 | TRAP_AC2;
                    break;
-               default:    
-               case DRAMTYPE_1Gx16:	
+               default:
+               case DRAMTYPE_1Gx16:
                    param->REG_AC2   = 0xCC00B01B | TRAP_AC2;
                    break;
-               case DRAMTYPE_2Gx16:	
+               case DRAMTYPE_2Gx16:
                    param->REG_AC2   = 0xCC00B02B | TRAP_AC2;
                    break;
-               case DRAMTYPE_4Gx16:	
+               case DRAMTYPE_4Gx16:
                    param->REG_AC2   = 0xCC00B03F | TRAP_AC2;
-                   break;               	
+                   break;
                }
-               
+
                break;
-               
+
     case 408 : MOutdwm(mmiobase, 0x1E6E2020, 0x01F0);
                param->WODT          = 1;
                param->RODT          = 0;
@@ -1974,24 +1974,24 @@ void GetDDR2Info(PAST2300DRAMParam param)
                param->REG_FREQ      = 0x000050C0;
                param->MADJ_MAX      = 96;
                param->DLL2_FINETUNE_STEP = 4;
-               
+
                switch (param->DRAM_ChipID)
                {
-               case DRAMTYPE_512Mx16:	
+               case DRAMTYPE_512Mx16:
                    param->REG_AC2   = 0xCC00B016 | TRAP_AC2;
                    break;
-               default:    
-               case DRAMTYPE_1Gx16:	
+               default:
+               case DRAMTYPE_1Gx16:
                    param->REG_AC2   = 0xCC00B01B | TRAP_AC2;
                    break;
-               case DRAMTYPE_2Gx16:	
+               case DRAMTYPE_2Gx16:
                    param->REG_AC2   = 0xCC00B02B | TRAP_AC2;
                    break;
-               case DRAMTYPE_4Gx16:	
+               case DRAMTYPE_4Gx16:
                    param->REG_AC2   = 0xCC00B03F | TRAP_AC2;
-                   break;               	
+                   break;
                }
-               
+
                break;
     case 456 : MOutdwm(mmiobase, 0x1E6E2020, 0x0230);
                param->WODT          = 0;
@@ -2071,24 +2071,24 @@ void GetDDR2Info(PAST2300DRAMParam param)
 
   switch (param->DRAM_ChipID)
   {
-  case DRAMTYPE_512Mx16:	
+  case DRAMTYPE_512Mx16:
       param->DRAM_CONFIG = 0x100;
       break;
-  default:    
-  case DRAMTYPE_1Gx16:	
+  default:
+  case DRAMTYPE_1Gx16:
       param->DRAM_CONFIG = 0x121;
       break;
-   case DRAMTYPE_2Gx16:	
+   case DRAMTYPE_2Gx16:
       param->DRAM_CONFIG = 0x122;
       break;
-  case DRAMTYPE_4Gx16:	
+  case DRAMTYPE_4Gx16:
       param->DRAM_CONFIG = 0x123;
-      break;     
+      break;
   }; /* switch size */
-  
+
   switch (param->VRAM_Size)
   {
-  default: 	
+  default:
   case VIDEOMEM_SIZE_08M:
       param->DRAM_CONFIG |= 0x00;
       break;
@@ -2100,16 +2100,16 @@ void GetDDR2Info(PAST2300DRAMParam param)
       break;
   case VIDEOMEM_SIZE_64M:
       param->DRAM_CONFIG |= 0x0c;
-      break;  	
+      break;
   }
-	
+
 }
 
 void GetDDR3Info(PAST2300DRAMParam param)
 {
   UCHAR *mmiobase;
   ULONG trap, TRAP_AC2, TRAP_MRS;
-  
+
   mmiobase = param->pjMMIOVirtualAddress;
   MOutdwm(mmiobase, 0x1E6E2000, 0x1688A8A8);
 
@@ -2119,7 +2119,7 @@ void GetDDR3Info(PAST2300DRAMParam param)
   TRAP_AC2 |= 0x00300000 +((trap & 0x2) << 19);
   TRAP_MRS  = 0x00000010 + (trap << 4);
   TRAP_MRS |=             ((trap & 0x2) << 18);
-  
+
   param->REG_MADJ 	= 0x00034C4C;
   param->REG_SADJ	= 0x00001800;
   param->REG_DRV        = 0x000000F0;
@@ -2139,22 +2139,22 @@ void GetDDR3Info(PAST2300DRAMParam param)
                param->REG_FREQ      = 0x00004DC0;
                param->MADJ_MAX      = 96;
                param->DLL2_FINETUNE_STEP = 3;
-               
+
                switch (param->DRAM_ChipID)
                {
-               default:                   	
+               default:
                case DRAMTYPE_512Mx16:
-               case DRAMTYPE_1Gx16:	
+               case DRAMTYPE_1Gx16:
                    param->REG_AC2   = 0xAA007613 | TRAP_AC2;
                    break;
-               case DRAMTYPE_2Gx16:	
+               case DRAMTYPE_2Gx16:
                    param->REG_AC2   = 0xAA00761c | TRAP_AC2;
                    break;
-               case DRAMTYPE_4Gx16:	
+               case DRAMTYPE_4Gx16:
                    param->REG_AC2   = 0xAA007636 | TRAP_AC2;
-                   break;               	
+                   break;
                }
-                
+
                break;
     default:
     case 396 : MOutdwm(mmiobase, 0x1E6E2020, 0x03F1);
@@ -2165,29 +2165,29 @@ void GetDDR3Info(PAST2300DRAMParam param)
                param->REG_MRS       = 0x04001600 | TRAP_MRS;
                param->REG_EMRS      = 0x00000000;
                param->REG_IOZ       = 0x00000034;
-               param->REG_DRV       = 0x000000FA;               
+               param->REG_DRV       = 0x000000FA;
                param->REG_DQIDLY    = 0x00000089;
                param->REG_FREQ      = 0x000050C0;
                param->MADJ_MAX      = 96;
                param->DLL2_FINETUNE_STEP = 4;
-               
+
                switch (param->DRAM_ChipID)
                {
-               default:                   	
-               case DRAMTYPE_512Mx16:	
-               case DRAMTYPE_1Gx16:	
+               default:
+               case DRAMTYPE_512Mx16:
+               case DRAMTYPE_1Gx16:
                    param->REG_AC2   = 0xCC009617 | TRAP_AC2;
                    break;
-               case DRAMTYPE_2Gx16:	
+               case DRAMTYPE_2Gx16:
                    param->REG_AC2   = 0xCC009622 | TRAP_AC2;
                    break;
-               case DRAMTYPE_4Gx16:	
+               case DRAMTYPE_4Gx16:
                    param->REG_AC2   = 0xCC00963F | TRAP_AC2;
-                   break;               	
+                   break;
                }
-               
+
                break;
-                  
+
     case 408 : MOutdwm(mmiobase, 0x1E6E2020, 0x01F0);
                param->WODT          = 1;
                param->REG_AC1       = 0x33302825;
@@ -2196,27 +2196,27 @@ void GetDDR3Info(PAST2300DRAMParam param)
                param->REG_MRS       = 0x04001600 | TRAP_MRS;
                param->REG_EMRS      = 0x00000000;
                param->REG_IOZ       = 0x00000034;
-               param->REG_DRV       = 0x000000FA;               
+               param->REG_DRV       = 0x000000FA;
                param->REG_DQIDLY    = 0x00000089;
                param->REG_FREQ      = 0x000050C0;
                param->MADJ_MAX      = 96;
                param->DLL2_FINETUNE_STEP = 4;
-               
+
                switch (param->DRAM_ChipID)
                {
-               default:                   	
-               case DRAMTYPE_512Mx16:	
-               case DRAMTYPE_1Gx16:	
+               default:
+               case DRAMTYPE_512Mx16:
+               case DRAMTYPE_1Gx16:
                    param->REG_AC2   = 0xCC009617 | TRAP_AC2;
                    break;
-               case DRAMTYPE_2Gx16:	
+               case DRAMTYPE_2Gx16:
                    param->REG_AC2   = 0xCC009622 | TRAP_AC2;
                    break;
-               case DRAMTYPE_4Gx16:	
+               case DRAMTYPE_4Gx16:
                    param->REG_AC2   = 0xCC00963F | TRAP_AC2;
-                   break;               	
+                   break;
                }
-               
+
                break;
     case 456 : MOutdwm(mmiobase, 0x1E6E2020, 0x0230);
                param->WODT          = 0;
@@ -2237,7 +2237,7 @@ void GetDDR3Info(PAST2300DRAMParam param)
                param->REG_AC2       = 0xDE44A61D;
                param->REG_DQSIC     = 0x00000117;
                param->REG_MRS       = 0x00081A30;
-               param->REG_EMRS      = 0x00000000;               
+               param->REG_EMRS      = 0x00000000;
                param->REG_IOZ       = 0x070000BB;
                param->REG_DQIDLY    = 0x000000A0;
                param->REG_FREQ      = 0x000054C0;
@@ -2252,7 +2252,7 @@ void GetDDR3Info(PAST2300DRAMParam param)
                param->REG_DQSIC     = 0x00000125;
                param->REG_MRS       = 0x00081A30;
                param->REG_EMRS      = 0x00000040;
-               param->REG_DRV       = 0x000000F5;               
+               param->REG_DRV       = 0x000000F5;
                param->REG_IOZ       = 0x00000023;
                param->REG_DQIDLY    = 0x00000088;
                param->REG_FREQ      = 0x000055C0;
@@ -2269,7 +2269,7 @@ void GetDDR3Info(PAST2300DRAMParam param)
                param->REG_DQSIC     = 0x0000013F;
                param->REG_MRS       = 0x00101A50;
                param->REG_EMRS      = 0x00000040;
-               param->REG_DRV       = 0x000000FA;                              
+               param->REG_DRV       = 0x000000FA;
                param->REG_IOZ       = 0x00000023;
                param->REG_DQIDLY    = 0x00000078;
                param->REG_FREQ      = 0x000057C0;
@@ -2278,7 +2278,7 @@ void GetDDR3Info(PAST2300DRAMParam param)
                break;
     case 600 : MOutdwm(mmiobase, 0x1E6E2020, 0x02E1);
                param->REG_MADJ 	    = 0x00136868;
-               param->REG_SADJ	    = 0x00004534;    
+               param->REG_SADJ	    = 0x00004534;
                param->WODT          = 1;
                param->RODT          = 1;
                param->REG_AC1       = 0x32302A37;
@@ -2286,7 +2286,7 @@ void GetDDR3Info(PAST2300DRAMParam param)
                param->REG_DQSIC     = 0x0000014D;
                param->REG_MRS       = 0x00101A50;
                param->REG_EMRS      = 0x00000004;
-               param->REG_DRV       = 0x000000F5;                                             
+               param->REG_DRV       = 0x000000F5;
                param->REG_IOZ       = 0x00000023;
                param->REG_DQIDLY    = 0x00000078;
                param->REG_FREQ      = 0x000058C0;
@@ -2295,7 +2295,7 @@ void GetDDR3Info(PAST2300DRAMParam param)
                break;
     case 624 : MOutdwm(mmiobase, 0x1E6E2020, 0x0160);
                param->REG_MADJ 	    = 0x00136868;
-               param->REG_SADJ	    = 0x00004534;    
+               param->REG_SADJ	    = 0x00004534;
                param->WODT          = 1;
                param->RODT          = 1;
                param->REG_AC1       = 0x32302A37;
@@ -2303,7 +2303,7 @@ void GetDDR3Info(PAST2300DRAMParam param)
                param->REG_DQSIC     = 0x0000015A;
                param->REG_MRS       = 0x02101A50;
                param->REG_EMRS      = 0x00000004;
-               param->REG_DRV       = 0x000000F5;                                                            
+               param->REG_DRV       = 0x000000F5;
                param->REG_IOZ       = 0x00000034;
                param->REG_DQIDLY    = 0x00000078;
                param->REG_FREQ      = 0x000059C0;
@@ -2314,24 +2314,24 @@ void GetDDR3Info(PAST2300DRAMParam param)
 
   switch (param->DRAM_ChipID)
   {
-  case DRAMTYPE_512Mx16:	
+  case DRAMTYPE_512Mx16:
       param->DRAM_CONFIG = 0x130;
       break;
-  default:    
-  case DRAMTYPE_1Gx16:	
+  default:
+  case DRAMTYPE_1Gx16:
       param->DRAM_CONFIG = 0x131;
       break;
-   case DRAMTYPE_2Gx16:	
+   case DRAMTYPE_2Gx16:
       param->DRAM_CONFIG = 0x132;
       break;
-  case DRAMTYPE_4Gx16:	
+  case DRAMTYPE_4Gx16:
       param->DRAM_CONFIG = 0x133;
-      break;     
+      break;
   }; /* switch size */
 
   switch (param->VRAM_Size)
   {
-  default: 	
+  default:
   case VIDEOMEM_SIZE_08M:
       param->DRAM_CONFIG |= 0x00;
       break;
@@ -2343,22 +2343,22 @@ void GetDDR3Info(PAST2300DRAMParam param)
       break;
   case VIDEOMEM_SIZE_64M:
       param->DRAM_CONFIG |= 0x0c;
-      break;  	
+      break;
   }
-  
+
 }
 
 void DDR2_Init(PAST2300DRAMParam param)
 {
   ULONG data, data2, retry = 0;
   UCHAR *mmiobase;
-  
+
   mmiobase = param->pjMMIOVirtualAddress;
 
-DDR2_Init_Start:  
+DDR2_Init_Start:
   MOutdwm(mmiobase, 0x1E6E0000, 0xFC600309);
   MOutdwm(mmiobase, 0x1E6E0064, 0x00000000);
-  MOutdwm(mmiobase, 0x1E6E0034, 0x00000000);    
+  MOutdwm(mmiobase, 0x1E6E0034, 0x00000000);
   MOutdwm(mmiobase, 0x1E6E0018, 0x00000100);
   MOutdwm(mmiobase, 0x1E6E0024, 0x00000000);
   MOutdwm(mmiobase, 0x1E6E0064, param->REG_MADJ);
@@ -2376,7 +2376,7 @@ DDR2_Init_Start:
   MOutdwm(mmiobase, 0x1E6E0084, 0x00FFFFFF);
   MOutdwm(mmiobase, 0x1E6E0088, param->REG_DQIDLY);
   MOutdwm(mmiobase, 0x1E6E0018, 0x4040A130);
-  MOutdwm(mmiobase, 0x1E6E0018, 0x20402330);                       
+  MOutdwm(mmiobase, 0x1E6E0018, 0x20402330);
   MOutdwm(mmiobase, 0x1E6E0038, 0x00000000);
   MOutdwm(mmiobase, 0x1E6E0040, 0xFF808000);
   MOutdwm(mmiobase, 0x1E6E0044, 0x88848466);
@@ -2398,7 +2398,7 @@ DDR2_Init_Start:
   }while(!(data & 0x08000000));
   MOutdwm(mmiobase, 0x1E6E0034, 0x00000001);
   MOutdwm(mmiobase, 0x1E6E000C, 0x00005C04);
-  usleep(10);                                                      
+  usleep(10);
   MOutdwm(mmiobase, 0x1E6E000C, 0x00000000);
   MOutdwm(mmiobase, 0x1E6E0034, 0x00000000);
   data = MIndwm(mmiobase, 0x1E6E001C);
@@ -2431,7 +2431,7 @@ DDR2_Init_Start:
 
     MOutdwm(mmiobase, 0x1E6E0034, 0x00000001);
     MOutdwm(mmiobase, 0x1E6E000C, 0x00005C04);
-    usleep(10);                                                     
+    usleep(10);
     MOutdwm(mmiobase, 0x1E6E000C, 0x00000000);
     MOutdwm(mmiobase, 0x1E6E0034, 0x00000000);
     data = MIndwm(mmiobase, 0x1E6E001C);
@@ -2439,7 +2439,7 @@ DDR2_Init_Start:
   }
   data = MIndwm(mmiobase, 0x1E6E0018) | 0xC00;
   MOutdwm(mmiobase, 0x1E6E0018, data);
-  
+
   MOutdwm(mmiobase, 0x1E6E0034, 0x00000001);
   MOutdwm(mmiobase, 0x1E6E000C, 0x00000000);
   usleep(50);
@@ -2499,13 +2499,13 @@ void DDR3_Init(PAST2300DRAMParam param)
 {
   ULONG data, data2, retry = 0;
   UCHAR *mmiobase;
-  
+
   mmiobase = param->pjMMIOVirtualAddress;
 
 DDR3_Init_Start:
   MOutdwm(mmiobase, 0x1E6E0000, 0xFC600309);
   MOutdwm(mmiobase, 0x1E6E0064, 0x00000000);
-  MOutdwm(mmiobase, 0x1E6E0034, 0x00000000);    
+  MOutdwm(mmiobase, 0x1E6E0034, 0x00000000);
   MOutdwm(mmiobase, 0x1E6E0018, 0x00000100);
   MOutdwm(mmiobase, 0x1E6E0024, 0x00000000);
   usleep(10);
@@ -2546,7 +2546,7 @@ DDR3_Init_Start:
   }while(!(data & 0x08000000));
   MOutdwm(mmiobase, 0x1E6E0034, 0x00000001);
   MOutdwm(mmiobase, 0x1E6E000C, 0x00005C04);
-  usleep(10);                                            
+  usleep(10);
   MOutdwm(mmiobase, 0x1E6E000C, 0x00000000);
   MOutdwm(mmiobase, 0x1E6E0034, 0x00000000);
   data = MIndwm(mmiobase, 0x1E6E001C);
@@ -2579,7 +2579,7 @@ DDR3_Init_Start:
 
     MOutdwm(mmiobase, 0x1E6E0034, 0x00000001);
     MOutdwm(mmiobase, 0x1E6E000C, 0x00005C04);
-    usleep(10);                       
+    usleep(10);
     MOutdwm(mmiobase, 0x1E6E000C, 0x00000000);
     MOutdwm(mmiobase, 0x1E6E0034, 0x00000000);
     data = MIndwm(mmiobase, 0x1E6E001C);
@@ -2645,64 +2645,64 @@ void vInitAST2300DRAMReg(ScrnInfoPtr pScrn)
     ULONG i, ulTemp;
     UCHAR jReg;
 
-    GetIndexRegMask(CRTC_PORT, 0xD0, 0xFF, jReg);  
-    
+    GetIndexRegMask(CRTC_PORT, 0xD0, 0xFF, jReg);
+
     if ((jReg & 0x80) == 0)			/* VGA only */
     {
         *(ULONG *) (pAST->MMIOVirtualAddr + 0xF004) = 0x1e6e0000;
         *(ULONG *) (pAST->MMIOVirtualAddr + 0xF000) = 0x1;
-       
+
         *(ULONG *) (pAST->MMIOVirtualAddr + 0x12000) = 0x1688A8A8;
         do {
-           ; 	
+           ;
         } while (*(volatile ULONG *) (pAST->MMIOVirtualAddr + 0x12000) != 0x01);
-       
+
         *(ULONG *) (pAST->MMIOVirtualAddr + 0x10000) = 0xFC600309;
         do {
-          ; 	
+          ;
         } while (*(volatile ULONG *) (pAST->MMIOVirtualAddr + 0x10000) != 0x01);
 
     	/* Slow down CPU/AHB CLK in VGA only mode */
         ulTemp  = *(ULONG *) (pAST->MMIOVirtualAddr + 0x12008);
         ulTemp |= 0x73;
         *(ULONG *) (pAST->MMIOVirtualAddr + 0x12008) = ulTemp;
-    	
+
         param.pjMMIOVirtualAddress = pAST->MMIOVirtualAddr;
         param.DRAM_Type = DDR3;			/* DDR3 */
-        ulTemp = MIndwm(param.pjMMIOVirtualAddress, 0x1E6E2070);    
+        ulTemp = MIndwm(param.pjMMIOVirtualAddress, 0x1E6E2070);
         if (ulTemp & 0x01000000)
             param.DRAM_Type = DDR2;		/* DDR2 */
         param.DRAM_ChipID = (ULONG) pAST->jDRAMType;
         param.DRAM_Freq = pAST->ulMCLK;
         param.VRAM_Size = pAST->ulVRAMSize;
-    
+
         if (param.DRAM_Type == DDR3)
         {
-            GetDDR3Info(&param);	
+            GetDDR3Info(&param);
             DDR3_Init(&param);
         }
         else
         {
             GetDDR2Info(&param);
-            DDR2_Init(&param);        	    	
+            DDR2_Init(&param);
         }
-        
-        ulTemp  = MIndwm(param.pjMMIOVirtualAddress, 0x1E6E2040);    
+
+        ulTemp  = MIndwm(param.pjMMIOVirtualAddress, 0x1E6E2040);
         MOutdwm(param.pjMMIOVirtualAddress, 0x1E6E2040, ulTemp | 0x40);
     }
 
     /* wait ready */
     do {
-        GetIndexRegMask(CRTC_PORT, 0xD0, 0xFF, jReg);      	
+        GetIndexRegMask(CRTC_PORT, 0xD0, 0xFF, jReg);
     } while ((jReg & 0x40) == 0);
-        	
-} /* vInitAST2300DRAMReg */	
+
+} /* vInitAST2300DRAMReg */
 
 void vGetDefaultSettings(ScrnInfoPtr pScrn)
 {
     ASTRecPtr pAST = ASTPTR(pScrn);
-    ULONG ulData;	
-	
+    ULONG ulData;
+
     if (pAST->jChipType == AST2300)
     {
         *(ULONG *) (pAST->MMIOVirtualAddr + 0xF004) = 0x1e6e0000;
@@ -2711,29 +2711,29 @@ void vGetDefaultSettings(ScrnInfoPtr pScrn)
         switch (ulData & 0x18000000)
         {
         case 0x00000000:
-            pAST->jDRAMType = DRAMTYPE_512Mx16;    	        
-            break;        
+            pAST->jDRAMType = DRAMTYPE_512Mx16;
+            break;
         case 0x08000000:
-            pAST->jDRAMType = DRAMTYPE_1Gx16;    	        
+            pAST->jDRAMType = DRAMTYPE_1Gx16;
             break;
         case 0x10000000:
-            pAST->jDRAMType = DRAMTYPE_2Gx16;    	        
-            break;        
+            pAST->jDRAMType = DRAMTYPE_2Gx16;
+            break;
         case 0x18000000:
-            pAST->jDRAMType = DRAMTYPE_4Gx16;    	        
-            break;        	
-        }	
-    }	
+            pAST->jDRAMType = DRAMTYPE_4Gx16;
+            break;
+        }
+    }
     else if ((pAST->jChipType == AST2100) || (pAST->jChipType == AST2200))
     {
-        pAST->jDRAMType = DRAMTYPE_512Mx32;    	    	
+        pAST->jDRAMType = DRAMTYPE_512Mx32;
     }
     else if ((pAST->jChipType == AST1100) || (pAST->jChipType == AST2150))
     {
-        pAST->jDRAMType = DRAMTYPE_1Gx16;    	
-    }	
-	
-} /* vGetDefaultSettings */	
+        pAST->jDRAMType = DRAMTYPE_1Gx16;
+    }
+
+} /* vGetDefaultSettings */
 
 /*
  * Flags: 0: POST init
@@ -2750,34 +2750,34 @@ Bool InitVGA(ScrnInfoPtr pScrn, ULONG Flags)
        /* Enable PCI */
        PCI_READ_LONG(pAST->PciInfo, &ulData, 0x04);
        ulData |= 0x03;
-       PCI_WRITE_LONG(pAST->PciInfo, ulData, 0x04);       
+       PCI_WRITE_LONG(pAST->PciInfo, ulData, 0x04);
 
        /* Enable VGA */
        vEnableVGA(pScrn);
-       
+
        vASTOpenKey(pScrn);
        vSetDefExtReg(pScrn);
 
        if (Flags == 0)
            vGetDefaultSettings(pScrn);
-                  
+
        if (pAST->jChipType == AST2300)
            vInitAST2300DRAMReg(pScrn);
        else
-           vInitDRAMReg(pScrn);      
-             
+           vInitDRAMReg(pScrn);
+
    }
 
-   return (TRUE);	
+   return (TRUE);
 } /* Init VGA */
 
 /* Get EDID */
-void 
+void
 I2CWriteClock(ASTRecPtr pAST, UCHAR data)
 {
     UCHAR       ujCRB7, jtemp;
     ULONG	i;
-       
+
     for (i=0;i<0x10000; i++)
     {
         ujCRB7 = ((data & 0x01) ? 0:1);			/* low active */
@@ -2785,44 +2785,44 @@ I2CWriteClock(ASTRecPtr pAST, UCHAR data)
         GetIndexRegMask(CRTC_PORT, 0xB7, 0x01, jtemp);
         if (ujCRB7 == jtemp) break;
     }
-        
+
 }
 
-void 
+void
 I2CWriteData(ASTRecPtr pAST, UCHAR data)
 {
     UCHAR       volatile ujCRB7, jtemp;
     ULONG	i;
-    
+
     for (i=0;i<0x1000; i++)
-    {        
+    {
         ujCRB7 = ((data & 0x01) ? 0:1) << 2;		/* low active */
         SetIndexRegMask(CRTC_PORT, 0xB7, 0xFB, ujCRB7);
         GetIndexRegMask(CRTC_PORT, 0xB7, 0x04, jtemp);
-        if (ujCRB7 == jtemp) break;        
+        if (ujCRB7 == jtemp) break;
     }
-    
+
 }
 
-Bool 
+Bool
 I2CReadClock(ASTRecPtr pAST)
-{	
+{
     UCHAR       volatile ujCRB7;
-          
+
     GetIndexRegMask(CRTC_PORT, 0xB7, 0x10, ujCRB7);
     ujCRB7 >>= 4;
-    
+
     return ((ujCRB7 & 0x01) ? 1:0);
 }
 
-Bool 
+Bool
 I2CReadData(ASTRecPtr pAST)
-{	
+{
     UCHAR	volatile ujCRB7;
-    
+
     GetIndexRegMask(CRTC_PORT, 0xB7, 0x20, ujCRB7);
     ujCRB7 >>= 5;
-    
+
     return ((ujCRB7 & 0x01) ? 1:0);
 
 }
@@ -2833,88 +2833,88 @@ I2CDelay(ASTRecPtr pAST)
 {
     ULONG 	i;
     UCHAR       jtemp;
-             
+
     for (i=0;i<150;i++)
         jtemp = GetReg(SEQ_PORT);
-       	
+
 }
- 
-void 
+
+void
 I2CStart(ASTRecPtr pAST)
-{    
+{
     I2CWriteClock(pAST, 0x00);				/* Set Clk Low */
     I2CDelay(pAST);
     I2CWriteData(pAST, 0x01);				/* Set Data High */
-    I2CDelay(pAST);    
+    I2CDelay(pAST);
     I2CWriteClock(pAST, 0x01);				/* Set Clk High */
-    I2CDelay(pAST);    
+    I2CDelay(pAST);
     I2CWriteData(pAST, 0x00);				/* Set Data Low */
-    I2CDelay(pAST);    
+    I2CDelay(pAST);
     I2CWriteClock(pAST, 0x01);				/* Set Clk High */
-    I2CDelay(pAST);                    
-}     
+    I2CDelay(pAST);
+}
 
-void 
+void
 I2CStop(ASTRecPtr pAST)
 {
     I2CWriteClock(pAST, 0x00);				/* Set Clk Low */
-    I2CDelay(pAST);    
+    I2CDelay(pAST);
     I2CWriteData(pAST, 0x00);				/* Set Data Low */
-    I2CDelay(pAST);    
+    I2CDelay(pAST);
     I2CWriteClock(pAST, 0x01);				/* Set Clk High */
-    I2CDelay(pAST);    
+    I2CDelay(pAST);
     I2CWriteData(pAST, 0x01);				/* Set Data High */
-    I2CDelay(pAST);    
+    I2CDelay(pAST);
     I2CWriteClock(pAST, 0x01);				/* Set Clk High */
-    I2CDelay(pAST);                      
-	
+    I2CDelay(pAST);
+
 }
 
-Bool 
+Bool
 CheckACK(ASTRecPtr pAST)
 {
     UCHAR Data;
 
     I2CWriteClock(pAST, 0x00);				/* Set Clk Low */
-    I2CDelay(pAST);    
+    I2CDelay(pAST);
     I2CWriteData(pAST, 0x01);				/* Set Data High */
-    I2CDelay(pAST);    
+    I2CDelay(pAST);
     I2CWriteClock(pAST, 0x01);				/* Set Clk High */
-    I2CDelay(pAST);    
+    I2CDelay(pAST);
     Data = (UCHAR) I2CReadData(pAST);			/* Set Data High */
-    
-    return ((Data & 0x01) ? 0:1);                
-                
+
+    return ((Data & 0x01) ? 0:1);
+
 }
 
 
-void 
+void
 SendACK(ASTRecPtr pAST)
 {
 
     I2CWriteClock(pAST, 0x00);				/* Set Clk Low */
-    I2CDelay(pAST);    
+    I2CDelay(pAST);
     I2CWriteData(pAST, 0x00);				/* Set Data low */
-    I2CDelay(pAST);    
+    I2CDelay(pAST);
     I2CWriteClock(pAST, 0x01);				/* Set Clk High */
-    I2CDelay(pAST);    
-                	
+    I2CDelay(pAST);
+
 }
 
-void 
+void
 SendNACK(ASTRecPtr pAST)
 {
 
     I2CWriteClock(pAST, 0x00);				/* Set Clk Low */
-    I2CDelay(pAST);    
+    I2CDelay(pAST);
     I2CWriteData(pAST, 0x01);				/* Set Data high */
-    I2CDelay(pAST);    
+    I2CDelay(pAST);
     I2CWriteClock(pAST, 0x01);				/* Set Clk High */
-    I2CDelay(pAST);    
-                		
+    I2CDelay(pAST);
+
 }
 
-void 
+void
 SendI2CDataByte(ASTRecPtr pAST, UCHAR data)
 {
     UCHAR jData;
@@ -2923,143 +2923,143 @@ SendI2CDataByte(ASTRecPtr pAST, UCHAR data)
     for (i=7;i>=0;i--)
     {
         I2CWriteClock(pAST, 0x00);				/* Set Clk Low */
-        I2CDelay(pAST);     	
-        
+        I2CDelay(pAST);
+
     	jData = ((data >> i) & 0x01) ? 1:0;
         I2CWriteData(pAST, jData);				/* Set Data Low */
-        I2CDelay(pAST);     	
-        
+        I2CDelay(pAST);
+
         I2CWriteClock(pAST, 0x01);				/* Set Clk High */
-        I2CDelay(pAST);                       	
-    }                
+        I2CDelay(pAST);
+    }
 }
 
-UCHAR 
+UCHAR
 ReceiveI2CDataByte(ASTRecPtr pAST)
 {
-    UCHAR jData=0, jTempData;   
+    UCHAR jData=0, jTempData;
     LONG i, j;
 
     for (i=7;i>=0;i--)
     {
         I2CWriteClock(pAST, 0x00);				/* Set Clk Low */
-        I2CDelay(pAST);     
-        	
+        I2CDelay(pAST);
+
         I2CWriteData(pAST, 0x01);				/* Set Data High */
-        I2CDelay(pAST);     	
-        
+        I2CDelay(pAST);
+
         I2CWriteClock(pAST, 0x01);				/* Set Clk High */
-        I2CDelay(pAST);           
-        
+        I2CDelay(pAST);
+
         for (j=0; j<0x1000; j++)
-        {   
+        {
             if (I2CReadClock(pAST)) break;
-        }    
-        	        
+        }
+
     	jTempData =  I2CReadData(pAST);
-    	jData |= ((jTempData & 0x01) << i); 
+    	jData |= ((jTempData & 0x01) << i);
 
         I2CWriteClock(pAST, 0x0);				/* Set Clk Low */
-        I2CDelay(pAST);                       	
-    }    
-    
-    return ((UCHAR)jData);                              
-}        
+        I2CDelay(pAST);
+    }
+
+    return ((UCHAR)jData);
+}
 
 Bool
 GetVGAEDID(ScrnInfoPtr pScrn, unsigned char *pEDIDBuffer)
 {
-    ASTRecPtr pAST;	
+    ASTRecPtr pAST;
     UCHAR *pjDstEDID;
     UCHAR jData;
     ULONG i;
 
-    pAST = ASTPTR(pScrn);    
+    pAST = ASTPTR(pScrn);
     pjDstEDID = (UCHAR *) pEDIDBuffer;
-    
+
     /* Force to DDC2 */
     I2CWriteClock(pAST, 0x01);				/* Set Clk High */
-    I2CDelay(pAST);  
+    I2CDelay(pAST);
     I2CWriteClock(pAST, 0x00);				/* Set Clk Low */
-    I2CDelay(pAST);     	
+    I2CDelay(pAST);
     I2CWriteClock(pAST, 0x01);				/* Set Clk High */
-    I2CDelay(pAST);  
+    I2CDelay(pAST);
 
     /* Validate SCL */
     if (I2CReadClock(pAST) == 0)			/* chk SCL failed */
     {
 	 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "[GetVGAEDID] Check SCL Failed \n");
-    	 return (FALSE);    	
-    }	
-                    
+    	 return (FALSE);
+    }
+
     I2CStart(pAST);
-    
+
     SendI2CDataByte(pAST, 0xA0);
     if (!CheckACK(pAST))
     {
 	 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "[GetVGAEDID] Check ACK Failed \n");
     	 return (FALSE);
-    }	
-    
+    }
+
     SendI2CDataByte(pAST, 0x00);
     if (!CheckACK(pAST))
     {
 	xf86DrvMsg(pScrn->scrnIndex, X_INFO, "[GetVGAEDID] Check ACK Failed \n");
     	return (FALSE);
-    }	
-    
+    }
+
     I2CStart(pAST);
-    
+
     SendI2CDataByte(pAST, 0xA1);
     if (!CheckACK(pAST))
     {
 	xf86DrvMsg(pScrn->scrnIndex, X_INFO, "[GetVGAEDID] Check ACK Failed \n");
     	return (FALSE);
-    }	
-            
+    }
+
     for (i=0; i<127; i++)
     {
         jData = ReceiveI2CDataByte(pAST);
         SendACK(pAST);
-        
-        *pjDstEDID++ = jData;       
+
+        *pjDstEDID++ = jData;
     }
-    
+
     jData = ReceiveI2CDataByte(pAST);
     SendNACK(pAST);
-    *pjDstEDID = jData;       
-            
+    *pjDstEDID = jData;
+
     I2CStop(pAST);
-      
+
     return (TRUE);
-    
+
 } /* GetVGAEDID */
 
 Bool bInitAST1180(ScrnInfoPtr pScrn)
 {
-    ASTRecPtr pAST;	
+    ASTRecPtr pAST;
     uint32_t ulData;
 
-    pAST = ASTPTR(pScrn);    
+    pAST = ASTPTR(pScrn);
 
     /* Enable PCI */
     PCI_READ_LONG(pAST->PciInfo, &ulData, 0x04);
     ulData |= 0x03;
-    PCI_WRITE_LONG(pAST->PciInfo, ulData, 0x04);       
-    	
+    PCI_WRITE_LONG(pAST->PciInfo, ulData, 0x04);
+
     /* init DRAM if no F/W */
     /* TODO */
 
     WriteAST1180SOC(AST1180_MMC_BASE+0x00, 0xFC600309);	/* unlock */
     WriteAST1180SOC(AST1180_SCU_BASE+0x00, 0x1688a8a8);	/* unlock */
     usleep(100);
-    
-    WriteAST1180SOC(AST1180_MMC_BASE+0x08, 0x000011e3);	/* req. */    
-    	
+
+    WriteAST1180SOC(AST1180_MMC_BASE+0x08, 0x000011e3);	/* req. */
+
     /* init SCU */
 #if 0
     ReadAST1180SOC(AST1180_SCU_BASE+0x08, ulData);	/* delay compensation */
-    ulData &= 0xFFFFE0FF;     
+    ulData &= 0xFFFFE0FF;
     ulData |= 0x00000C00;
     WriteAST1180SOC(AST1180_SCU_BASE+0x08, ulData);
 #endif
@@ -3067,38 +3067,38 @@ Bool bInitAST1180(ScrnInfoPtr pScrn)
     ReadAST1180SOC(AST1180_SCU_BASE+0x0c, ulData);	/* 2d clk */
     ulData &= 0xFFFFFFFD;
     WriteAST1180SOC(AST1180_SCU_BASE+0x0c, ulData);
-	
+
     return (TRUE);
-	
+
 } /* bInitAST1180 */
-	
+
 void GetAST1180DRAMInfo(ScrnInfoPtr pScrn)
 {
     ASTRecPtr pAST = ASTPTR(pScrn);
     ULONG ulData;
-    
+
     WriteAST1180SOC(AST1180_MMC_BASE+0x00, 0xFC600309);	/* unlock */
     ReadAST1180SOC(AST1180_MMC_BASE+0x04, ulData);
     pAST->ulDRAMBusWidth = 32;
     if (ulData & 0x40)
         pAST->ulDRAMBusWidth = 16;
-        
-    /* DRAM size */    
+
+    /* DRAM size */
     switch (ulData & 0x0C)
     {
     case 0x00:
        pAST->ulDRAMSize = DRAM_SIZE_032M;
-       break;    
+       break;
     case 0x04:
        pAST->ulDRAMSize = DRAM_SIZE_064M;
-       break;        
+       break;
     case 0x08:
        pAST->ulDRAMSize = DRAM_SIZE_128M;
-       break;        
-    case 0x0c:	
+       break;
+    case 0x0c:
        pAST->ulDRAMSize = DRAM_SIZE_256M;
-       break;        
-    }	
+       break;
+    }
 
     /* Get framebuffer size */
     switch (ulData & 0x30)
@@ -3108,23 +3108,23 @@ void GetAST1180DRAMInfo(ScrnInfoPtr pScrn)
         break;
     case 0x10:
         pAST->ulVRAMSize = DRAM_SIZE_032M;
-        break;    
+        break;
     case 0x20:
         pAST->ulVRAMSize = DRAM_SIZE_064M;
-        break;    
+        break;
     case 0x30:
         pAST->ulVRAMSize = DRAM_SIZE_128M;
-        break;    	
-    }	
+        break;
+    }
 
     /* VRAM base */
     if (pAST->ulVRAMSize >= pAST->ulDRAMSize)
-        pAST->ulVRAMSize = pAST->ulDRAMSize;    
+        pAST->ulVRAMSize = pAST->ulDRAMSize;
     pAST->ulVRAMBase = pAST->ulDRAMSize - pAST->ulVRAMSize;
-    
+
     /* MCLK */
     pAST->ulMCLK = 200;
-    
+
 } /* GetAST1180DRAMInfo */
 
 void vEnableASTVGAMMIO(ScrnInfoPtr pScrn)
@@ -3132,7 +3132,7 @@ void vEnableASTVGAMMIO(ScrnInfoPtr pScrn)
     ASTRecPtr pAST = ASTPTR(pScrn);
     ULONG ulData;
     UCHAR jReg;
-    
+
     if (!xf86IsPrimaryPci(pAST->PciInfo))
     {
        /* Enable PCI */
@@ -3141,14 +3141,14 @@ void vEnableASTVGAMMIO(ScrnInfoPtr pScrn)
        PCI_WRITE_LONG(pAST->PciInfo, ulData, 0x04);
 
        outb(pAST->RelocateIO + 0x43, 0x01);
-       outb(pAST->RelocateIO + 0x42, 0x01);	    
-    }	    
-    
+       outb(pAST->RelocateIO + 0x42, 0x01);
+    }
+
     jReg = GetReg(VGA_ENABLE_PORT);
     if (jReg == 0xFF)	/* MMIO Access is disabled */
     {
        outw(pAST->RelocateIO + 0x54, 0xa880);
-       outw(pAST->RelocateIO + 0x54, 0x04a1);	    
+       outw(pAST->RelocateIO + 0x54, 0x04a1);
     }
-	    
+
 } /* vEnableASTVGAMMIO */