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-rwxr-xr-x[-rw-r--r--].gitignore0
-rwxr-xr-x[-rw-r--r--]COPYING0
-rwxr-xr-x[-rw-r--r--]Makefile.am0
-rwxr-xr-x[-rw-r--r--]README0
-rwxr-xr-x[-rw-r--r--]configure.ac2
-rwxr-xr-x[-rw-r--r--]src/Makefile.am0
-rwxr-xr-x[-rw-r--r--]src/ast.h10
-rwxr-xr-x[-rw-r--r--]src/ast_2dtool.c0
-rwxr-xr-x[-rw-r--r--]src/ast_2dtool.h0
-rwxr-xr-x[-rw-r--r--]src/ast_accel.c0
-rwxr-xr-x[-rw-r--r--]src/ast_cursor.c0
-rwxr-xr-x[-rw-r--r--]src/ast_cursor.h0
-rwxr-xr-x[-rw-r--r--]src/ast_driver.c651
-rwxr-xr-x[-rw-r--r--]src/ast_mode.c36
-rwxr-xr-x[-rw-r--r--]src/ast_mode.h3
-rwxr-xr-x[-rw-r--r--]src/ast_pcirename.h0
-rwxr-xr-x[-rw-r--r--]src/ast_tool.c0
-rwxr-xr-x[-rw-r--r--]src/ast_vgatool.c135
-rwxr-xr-x[-rw-r--r--]src/ast_vgatool.h64
19 files changed, 565 insertions, 336 deletions
diff --git a/.gitignore b/.gitignore
index ce86c28..ce86c28 100644..100755
--- a/.gitignore
+++ b/.gitignore
diff --git a/COPYING b/COPYING
index 0d1b2a9..0d1b2a9 100644..100755
--- a/COPYING
+++ b/COPYING
diff --git a/Makefile.am b/Makefile.am
index 63c7c9e..63c7c9e 100644..100755
--- a/Makefile.am
+++ b/Makefile.am
diff --git a/README b/README
index 181d46c..181d46c 100644..100755
--- a/README
+++ b/README
diff --git a/configure.ac b/configure.ac
index 3b6d93c..a0a9edc 100644..100755
--- a/configure.ac
+++ b/configure.ac
@@ -23,7 +23,7 @@
# Initialize Autoconf
AC_PREREQ([2.60])
AC_INIT([xf86-video-ast],
- [0.93.10],
+ [0.95.00],
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
[xf86-video-ast])
AC_CONFIG_SRCDIR([Makefile.am])
diff --git a/src/Makefile.am b/src/Makefile.am
index 4cd7075..4cd7075 100644..100755
--- a/src/Makefile.am
+++ b/src/Makefile.am
diff --git a/src/ast.h b/src/ast.h
index 7ceee31..910862e 100644..100755
--- a/src/ast.h
+++ b/src/ast.h
@@ -88,8 +88,18 @@ typedef CARD32 ULONG;
/* Data Structure Definition */
typedef struct _ASTRegRec {
+
UCHAR ExtCRTC[0x50];
+
+ UCHAR MISC;
+ UCHAR SEQ[4];
+ UCHAR CRTC[25];
+ UCHAR AR[20];
+ UCHAR GR[9];
+ UCHAR DAC[256][3];
+
ULONG GFX[12];
+
} ASTRegRec, *ASTRegPtr;
typedef struct _VIDEOMODE {
diff --git a/src/ast_2dtool.c b/src/ast_2dtool.c
index 7e54370..7e54370 100644..100755
--- a/src/ast_2dtool.c
+++ b/src/ast_2dtool.c
diff --git a/src/ast_2dtool.h b/src/ast_2dtool.h
index 5bc437f..5bc437f 100644..100755
--- a/src/ast_2dtool.h
+++ b/src/ast_2dtool.h
diff --git a/src/ast_accel.c b/src/ast_accel.c
index 2d3dab3..2d3dab3 100644..100755
--- a/src/ast_accel.c
+++ b/src/ast_accel.c
diff --git a/src/ast_cursor.c b/src/ast_cursor.c
index b3f2061..b3f2061 100644..100755
--- a/src/ast_cursor.c
+++ b/src/ast_cursor.c
diff --git a/src/ast_cursor.h b/src/ast_cursor.h
index d4de479..d4de479 100644..100755
--- a/src/ast_cursor.h
+++ b/src/ast_cursor.h
diff --git a/src/ast_driver.c b/src/ast_driver.c
index 896f22c..5da19a6 100644..100755
--- a/src/ast_driver.c
+++ b/src/ast_driver.c
@@ -82,6 +82,7 @@ extern Bool InitVGA(ScrnInfoPtr pScrn, ULONG Flags);
extern Bool GetVGAEDID(ScrnInfoPtr pScrn, unsigned char *pEDIDBuffer);
extern Bool bInitAST1180(ScrnInfoPtr pScrn);
extern void GetAST1180DRAMInfo(ScrnInfoPtr pScrn);
+extern void vEnableASTVGAMMIO(ScrnInfoPtr pScrn);
extern Bool bInitCMDQInfo(ScrnInfoPtr pScrn, ASTRecPtr pAST);
extern Bool bEnableCMDQ(ScrnInfoPtr pScrn, ASTRecPtr pAST);
@@ -338,9 +339,11 @@ static Bool
ASTPreInit(ScrnInfoPtr pScrn, int flags)
{
EntityInfoPtr pEnt;
- vgaHWPtr hwp;
int flags24;
rgb defaultWeight = { 0, 0, 0 };
+#if !(defined(__sparc__)) && !(defined(__mips__))
+ vgaHWPtr hwp;
+#endif
ASTRecPtr pAST;
@@ -368,19 +371,22 @@ ASTPreInit(ScrnInfoPtr pScrn, int flags)
return FALSE;
#endif
+#if !(defined(__sparc__)) && !(defined(__mips__))
/* The vgahw module should be loaded here when needed */
if (!xf86LoadSubModule(pScrn, "vgahw"))
return FALSE;
+#endif
/* The fb module should be loaded here when needed */
if (!xf86LoadSubModule(pScrn, "fb"))
return FALSE;
-
+
+#if !(defined(__sparc__)) && !(defined(__mips__))
/* Allocate a vgaHWRec */
if (!vgaHWGetHWRec(pScrn))
return FALSE;
hwp = VGAHWPTR(pScrn);
- vgaHWSetStdFuncs(hwp);
+#endif
/* Color Depth Check */
flags24 = Support32bppFb;
@@ -579,7 +585,10 @@ ASTPreInit(ScrnInfoPtr pScrn, int flags)
}
else
- {
+ {
+ /* Enable VGA MMIO Access */
+ vEnableASTVGAMMIO(pScrn);
+
/* Init VGA Adapter */
if (!xf86IsPrimaryPci(pAST->PciInfo))
{
@@ -693,34 +702,31 @@ ASTPreInit(ScrnInfoPtr pScrn, int flags)
pAST->pCMDQPtr = NULL;
pAST->CMDQInfo.ulCMDQSize = 0;
#ifdef Accel_2D
- if (!xf86ReturnOptValBool(pAST->Options, OPTION_NOACCEL, FALSE)) do {
- if (!xf86LoadSubModule(pScrn, "xaa")) {\
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "XAA not available\n");
- pAST->noAccel = TRUE;
- break;
- }
-
- pAST->noAccel = FALSE;
-
- pAST->MMIO2D = TRUE;
-#ifndef MMIO_2D
- if (!xf86ReturnOptValBool(pAST->Options, OPTION_MMIO2D, FALSE)) {
- pAST->CMDQInfo.ulCMDQSize = DEFAULT_CMDQ_SIZE;
- pAST->MMIO2D = FALSE;
- }
+ if (!xf86ReturnOptValBool(pAST->Options, OPTION_NOACCEL, FALSE))
+ {
+ if (xf86LoadSubModule(pScrn, "xaa")) {
+
+ pAST->noAccel = FALSE;
+ pAST->MMIO2D = TRUE;
+#ifndef MMIO_2D
+ if (!xf86ReturnOptValBool(pAST->Options, OPTION_MMIO2D, FALSE)) {
+ pAST->CMDQInfo.ulCMDQSize = DEFAULT_CMDQ_SIZE;
+ pAST->MMIO2D = FALSE;
+ }
#endif
- pAST->ENGCaps = ENG_CAP_ALL;
- if (!xf86GetOptValInteger(pAST->Options, OPTION_ENG_CAPS, &pAST->ENGCaps)) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "No ENG Capability options found\n");
- }
-
- pAST->DBGSelect = 0;
- if (!xf86GetOptValInteger(pAST->Options, OPTION_DBG_SELECT, &pAST->DBGSelect)) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "No DBG Seleclt options found\n");
- }
- } while (0);
-#endif
+ pAST->ENGCaps = ENG_CAP_ALL;
+ if (!xf86GetOptValInteger(pAST->Options, OPTION_ENG_CAPS, &pAST->ENGCaps)) {
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "No ENG Capability options found\n");
+ }
+
+ pAST->DBGSelect = 0;
+ if (!xf86GetOptValInteger(pAST->Options, OPTION_DBG_SELECT, &pAST->DBGSelect)) {
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "No DBG Seleclt options found\n");
+ }
+ }
+ }
+#endif
/* HW Cursor Check */
pAST->noHWC = TRUE;
@@ -757,16 +763,13 @@ ASTScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
{
ScrnInfoPtr pScrn;
ASTRecPtr pAST;
- vgaHWPtr hwp;
VisualPtr visual;
-
/* for FB Manager */
BoxRec FBMemBox;
int AvailFBSize;
pScrn = xf86Screens[pScreen->myNum];
pAST = ASTPTR(pScrn);
- hwp = VGAHWPTR(pScrn);
if (!ASTMapMem(pScrn)) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Map FB Memory Failed \n");
@@ -795,7 +798,11 @@ ASTScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
}
- vgaHWGetIOBase(hwp);
+#if !(defined(__sparc__)) && !(defined(__mips__))
+ vgaHWPtr hwp;
+ hwp = VGAHWPTR(pScrn);
+ vgaHWSetMmioFuncs(hwp, pAST->MMIOVirtualAddr, 0);
+#endif
vFillASTModeInfo (pScrn);
@@ -999,7 +1006,9 @@ ASTLeaveVT(int scrnIndex, int flags)
ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
ASTRecPtr pAST = ASTPTR(pScrn);
+#if !(defined(__sparc__)) && !(defined(__mips__))
vgaHWPtr hwp = VGAHWPTR(pScrn);
+#endif
#ifdef HWC
if (pAST->pHWCPtr) {
@@ -1022,7 +1031,9 @@ ASTLeaveVT(int scrnIndex, int flags)
if (pAST->jChipType == AST1180)
ASTBlankScreen(pScrn, 0);
+#if !(defined(__sparc__)) && !(defined(__mips__))
vgaHWLock(hwp);
+#endif
}
@@ -1030,8 +1041,10 @@ static void
ASTFreeScreen(int scrnIndex, int flags)
{
ASTFreeRec(xf86Screens[scrnIndex]);
+#if !(defined(__sparc__)) && !(defined(__mips__))
if (xf86LoaderCheckSymbol("vgaHWFreeHWRec"))
vgaHWFreeHWRec(xf86Screens[scrnIndex]);
+#endif
}
static ModeStatus
@@ -1095,8 +1108,14 @@ ASTValidMode(int scrnIndex, DisplayModePtr mode, Bool verbose, int flags)
if ( (pAST->jChipType == AST2100) || (pAST->jChipType == AST2200) || (pAST->jChipType == AST2300) || (pAST->jChipType == AST1180) )
{
if ( (mode->CrtcHDisplay == 1920) && (mode->CrtcVDisplay == 1200) )
- return MODE_OK;
- }
+ {
+ GetIndexRegMask(CRTC_PORT, 0xD1, 0xFF, jReg);
+ if (jReg & 0x01)
+ return MODE_NOMODE;
+ else
+ return MODE_OK;
+ }
+ }
switch (mode->CrtcHDisplay)
{
@@ -1154,6 +1173,7 @@ ASTFreeRec(ScrnInfoPtr pScrn)
static Bool
ASTSaveScreen(ScreenPtr pScreen, Bool unblack)
{
+#if !(defined(__sparc__)) && !(defined(__mips__))
/* replacement of vgaHWBlankScreen(pScrn, unblank) without seq reset */
/* return vgaHWSaveScreen(pScreen, unblack); */
ScrnInfoPtr pScrn = NULL;
@@ -1165,43 +1185,50 @@ ASTSaveScreen(ScreenPtr pScreen, Bool unblack)
ASTBlankScreen(pScrn, unblack);
}
return (TRUE);
+#endif
}
static Bool
ASTCloseScreen(int scrnIndex, ScreenPtr pScreen)
{
ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
- vgaHWPtr hwp = VGAHWPTR(pScrn);
ASTRecPtr pAST = ASTPTR(pScrn);
+#if !(defined(__sparc__)) && !(defined(__mips__))
+ vgaHWPtr hwp = VGAHWPTR(pScrn);
+#endif
if (pScrn->vtSema == TRUE)
{
#ifdef HWC
- if (pAST->pHWCPtr) {
- xf86FreeOffscreenLinear(pAST->pHWCPtr); /* free HWC Cache */
- pAST->pHWCPtr = NULL;
- }
+ if (pAST->pHWCPtr) {
+ xf86FreeOffscreenLinear(pAST->pHWCPtr); /* free HWC Cache */
+ pAST->pHWCPtr = NULL;
+ }
ASTDisableHWC(pScrn);
#endif
#ifdef Accel_2D
- if (pAST->pCMDQPtr) {
- xf86FreeOffscreenLinear(pAST->pCMDQPtr); /* free CMDQ */
- pAST->pCMDQPtr = NULL;
- }
- vDisable2D(pScrn, pAST);
+ if (pAST->pCMDQPtr) {
+ xf86FreeOffscreenLinear(pAST->pCMDQPtr); /* free CMDQ */
+ pAST->pCMDQPtr = NULL;
+ }
+ vDisable2D(pScrn, pAST);
#endif
- ASTRestore(pScrn);
-
- if (pAST->jChipType == AST1180)
- ASTBlankScreen(pScrn, 0);
+ ASTRestore(pScrn);
- vgaHWLock(hwp);
+ if (pAST->jChipType == AST1180)
+ ASTBlankScreen(pScrn, 0);
+
+#if !(defined(__sparc__)) && !(defined(__mips__))
+ vgaHWLock(hwp);
+#endif
}
ASTUnmapMem(pScrn);
+#if !(defined(__sparc__)) && !(defined(__mips__))
vgaHWUnmapMem(pScrn);
+#endif
if(pAST->AccelInfoPtr) {
XAADestroyInfoRec(pAST->AccelInfoPtr);
@@ -1222,24 +1249,13 @@ static void
ASTSave(ScrnInfoPtr pScrn)
{
ASTRecPtr pAST;
- vgaRegPtr vgaReg;
ASTRegPtr astReg;
int i, icount=0;
ULONG ulData;
pAST = ASTPTR(pScrn);
- vgaReg = &VGAHWPTR(pScrn)->SavedReg;
- astReg = &pAST->SavedReg;
-
- /* do save */
- if (xf86IsPrimaryPci(pAST->PciInfo)) {
- vgaHWSave(pScrn, vgaReg, VGA_SR_ALL);
- }
- else {
- vgaHWSave(pScrn, vgaReg, VGA_SR_MODE);
- }
+ astReg = &pAST->SavedReg;
- /* Ext. Save */
if (pAST->jChipType == AST1180)
{
for (i=0; i<12; i++)
@@ -1249,7 +1265,45 @@ ASTSave(ScrnInfoPtr pScrn)
}
}
else
- {
+ {
+#if defined(__sparc__) || defined(__mips__)
+ UCHAR jReg;
+
+ /* Save Misc */
+ astReg->MISC = GetReg(MISC_PORT_READ);
+
+ /* Save SR */
+ for (i=0; i<4; i++)
+ GetIndexReg(SEQ_PORT, (UCHAR) (i), astReg->SEQ[i]);
+
+ /* Save CR */
+ for (i=0; i<25; i++)
+ GetIndexReg(CRTC_PORT, (UCHAR) (i), astReg->CRTC[i]);
+
+ /* Save GR */
+ for (i=0; i<9; i++)
+ GetIndexReg(GR_PORT, (UCHAR) (i), astReg->GR[i]);
+
+ /* Save AR */
+ jReg = GetReg(INPUT_STATUS1_READ);
+ for (i=0; i<20; i++)
+ GetIndexReg(AR_PORT_WRITE, (UCHAR) (i), astReg->AR[i]);
+ jReg = GetReg(INPUT_STATUS1_READ);
+ SetReg (AR_PORT_WRITE, 0x20); /* set POS */
+#else
+ vgaRegPtr vgaReg;
+ vgaReg = &VGAHWPTR(pScrn)->SavedReg;
+
+ /* do save */
+ if (xf86IsPrimaryPci(pAST->PciInfo)) {
+ vgaHWSave(pScrn, vgaReg, VGA_SR_MODE | VGA_SR_FONTS);
+ }
+ else {
+ vgaHWSave(pScrn, vgaReg, VGA_SR_MODE);
+ }
+#endif
+
+ /* Save Ext. */
vASTOpenKey(pScrn);
/* fixed Console Switch Refresh Rate Incorrect issue, ycchen@051106 */
@@ -1258,31 +1312,25 @@ ASTSave(ScrnInfoPtr pScrn)
for (i=0xBC; i<=0xC1; i++)
GetIndexReg(CRTC_PORT, (UCHAR) (i), astReg->ExtCRTC[icount++]);
GetIndexReg(CRTC_PORT, (UCHAR) (0xBB), astReg->ExtCRTC[icount]);
+
+ /* Save DAC */
+ for (i=0; i<256; i++)
+ VGA_GET_PALETTE_INDEX (i, astReg->DAC[i][0], astReg->DAC[i][1], astReg->DAC[i][2]);
}
-
+
}
static void
ASTRestore(ScrnInfoPtr pScrn)
{
ASTRecPtr pAST;
- vgaRegPtr vgaReg;
ASTRegPtr astReg;
int i, icount=0;
ULONG ulData;
pAST = ASTPTR(pScrn);
- vgaReg = &VGAHWPTR(pScrn)->SavedReg;
- astReg = &pAST->SavedReg;
+ astReg = &pAST->SavedReg;
- /* do restore */
- vgaHWProtect(pScrn, TRUE);
- if (xf86IsPrimaryPci(pAST->PciInfo))
- vgaHWRestore(pScrn, vgaReg, VGA_SR_ALL);
- else
- vgaHWRestore(pScrn, vgaReg, VGA_SR_MODE);
- vgaHWProtect(pScrn, FALSE);
-
if (pAST->jChipType == AST1180)
{
for (i=0; i<12; i++)
@@ -1292,7 +1340,51 @@ ASTRestore(ScrnInfoPtr pScrn)
}
}
else
- {
+ {
+#if defined(__sparc__) || defined(__mips__)
+ UCHAR jReg;
+
+ /* Restore Misc */
+ SetReg(MISC_PORT_WRITE, astReg->MISC);
+
+ /* Restore SR */
+ for (i=0; i<4; i++)
+ SetIndexReg(SEQ_PORT, (UCHAR) (i), astReg->SEQ[i]);
+
+ /* Restore CR */
+ SetIndexRegMask(CRTC_PORT,0x11, 0x7F, 0x00);
+ for (i=0; i<25; i++)
+ SetIndexReg(CRTC_PORT, (UCHAR) (i), astReg->CRTC[i]);
+
+ /* Restore GR */
+ for (i=0; i<9; i++)
+ SetIndexReg(GR_PORT, (UCHAR) (i), astReg->GR[i]);
+
+ /* Restore AR */
+ jReg = GetReg(INPUT_STATUS1_READ);
+ for (i=0; i<20; i++)
+ {
+ SetReg(AR_PORT_WRITE, (UCHAR) i);
+ SetReg(AR_PORT_WRITE, astReg->AR[i]);
+ }
+ SetReg(AR_PORT_WRITE, 0x14);
+ SetReg(AR_PORT_WRITE, 0x00);
+
+ jReg = GetReg(INPUT_STATUS1_READ);
+ SetReg (AR_PORT_WRITE, 0x20); /* set POS */
+#else
+ vgaRegPtr vgaReg;
+ vgaReg = &VGAHWPTR(pScrn)->SavedReg;
+
+ /* do restore */
+ vgaHWProtect(pScrn, TRUE);
+ if (xf86IsPrimaryPci(pAST->PciInfo))
+ vgaHWRestore(pScrn, vgaReg, VGA_SR_MODE | VGA_SR_FONTS);
+ else
+ vgaHWRestore(pScrn, vgaReg, VGA_SR_MODE);
+ vgaHWProtect(pScrn, FALSE);
+#endif
+
/* Ext. restore */
vASTOpenKey(pScrn);
@@ -1302,6 +1394,10 @@ ASTRestore(ScrnInfoPtr pScrn)
for (i=0xBC; i<=0xC1; i++)
SetIndexReg(CRTC_PORT, (UCHAR) (i), astReg->ExtCRTC[icount++]);
SetIndexReg(CRTC_PORT, (UCHAR) (0xBB), astReg->ExtCRTC[icount]);
+
+ /* Restore DAC */
+ for (i=0; i<256; i++)
+ VGA_LOAD_PALETTE_INDEX (i, astReg->DAC[i][0], astReg->DAC[i][1], astReg->DAC[i][2]);
}
}
@@ -1309,33 +1405,29 @@ ASTRestore(ScrnInfoPtr pScrn)
static void
ASTProbeDDC(ScrnInfoPtr pScrn, int index)
{
- vbeInfoPtr pVbe;
ASTRecPtr pAST = ASTPTR(pScrn);
unsigned char DDC_data[128];
Bool Flags;
- if ( (pAST->jChipType == AST1180) || (!xf86IsPrimaryPci(pAST->PciInfo)) )
+ if (xf86LoadSubModule(pScrn, "ddc"))
{
- if (pAST->jChipType == AST1180)
- Flags = GetVGA2EDID(pScrn, DDC_data);
- else
- Flags = GetVGAEDID(pScrn, DDC_data);
-
- if (Flags)
- {
- ConfiguredMonitor = xf86InterpretEDID(pScrn->scrnIndex, DDC_data);
- }
- else
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,"[ASTProbeDDC] Can't Get EDID Properly \n");
- }
+ if (pAST->jChipType == AST1180)
+ Flags = GetVGA2EDID(pScrn, DDC_data);
+ else
+ Flags = GetVGAEDID(pScrn, DDC_data);
+
+ if (Flags)
+ {
+ ConfiguredMonitor = xf86InterpretEDID(pScrn->scrnIndex, DDC_data);
+ }
+ else
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,"[ASTProbeDDC] Can't Get EDID Properly \n");
+ }
else
{
- if (xf86LoadSubModule(pScrn, "vbe")) {
- pVbe = VBEInit(NULL, index);
- ConfiguredMonitor = vbeDoEDID(pVbe, NULL);
- vbeFree(pVbe);
- }
- }
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,"[ASTProbeDDC] Can't Load DDC Sub-Modules or Read EDID Failed \n");
+ }
+
}
#define SkipDT 0x00
@@ -1345,201 +1437,194 @@ ASTProbeDDC(ScrnInfoPtr pScrn, int index)
static xf86MonPtr
ASTDoDDC(ScrnInfoPtr pScrn, int index)
{
- vbeInfoPtr pVbe;
- xf86MonPtr MonInfo = NULL, MonInfo1 = NULL, MonInfo2 = NULL;
+ xf86MonPtr MonInfo = NULL;
ASTRecPtr pAST = ASTPTR(pScrn);
- unsigned long i, j, k;
unsigned char DDC_data[128];
+ Bool Flags;
+
+ xf86MonPtr MonInfo1 = NULL, MonInfo2 = NULL;
+ unsigned long i, j, k;
struct monitor_ranges ranges, ranges1, ranges2;
int DTSelect, dclock1=0, h_active1=0, v_active1=0, dclock2=0, h_active2=0, v_active2=0;
struct std_timings stdtiming, *stdtiming1, *stdtiming2;
- Bool Flags;
-
+
/* Honour Option "noDDC" */
if (xf86ReturnOptValBool(pAST->Options, OPTION_NO_DDC, FALSE)) {
return MonInfo;
}
- if ( (pAST->jChipType == AST1180) || (!xf86IsPrimaryPci(pAST->PciInfo)) )
+ if (xf86LoadSubModule(pScrn, "ddc"))
{
-
- if (pAST->jChipType == AST1180)
- Flags = GetVGA2EDID(pScrn, DDC_data);
- else
- Flags = GetVGAEDID(pScrn, DDC_data);
-
- if (Flags)
- {
- MonInfo = xf86InterpretEDID(pScrn->scrnIndex, DDC_data);
- xf86PrintEDID(MonInfo);
- xf86SetDDCproperties(pScrn, MonInfo);
- }
- else
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,"[ASTDoDDC] Can't Get EDID Properly \n");
-
- }
- else
- {
-
- if (xf86LoadSubModule(pScrn, "vbe") && (pVbe = VBEInit(NULL, index))) {
- MonInfo1 = vbeDoEDID(pVbe, NULL);
- MonInfo = MonInfo1;
+ if (pAST->jChipType == AST1180)
+ Flags = GetVGA2EDID(pScrn, DDC_data);
+ else
+ Flags = GetVGAEDID(pScrn, DDC_data);
- /* For VGA2 CLONE Support, ycchen@012508 */
- if ((xf86ReturnOptValBool(pAST->Options, OPTION_VGA2_CLONE, FALSE)) || pAST->VGA2Clone) {
- if (GetVGA2EDID(pScrn, DDC_data) == TRUE) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Get VGA2 EDID Correctly!! \n");
- MonInfo2 = xf86InterpretEDID(pScrn->scrnIndex, DDC_data);
- if (MonInfo1 == NULL) /* No DDC1 EDID */
- MonInfo = MonInfo2;
- else { /* Check with VGA1 & VGA2 EDID */
- /* Update establishment timing */
- MonInfo->timings1.t1 = MonInfo1->timings1.t1 & MonInfo2->timings1.t1;
- MonInfo->timings1.t2 = MonInfo1->timings1.t2 & MonInfo2->timings1.t2;
- MonInfo->timings1.t_manu = MonInfo1->timings1.t_manu & MonInfo2->timings1.t_manu;
-
- /* Update Std. Timing */
- for (i=0; i<8; i++) {
- stdtiming.hsize = stdtiming.vsize = stdtiming.refresh = stdtiming.id = 0;
- for (j=0; j<8; j++) {
- if ((MonInfo1->timings2[i].hsize == MonInfo2->timings2[j].hsize) && \
- (MonInfo1->timings2[i].vsize == MonInfo2->timings2[j].vsize) && \
- (MonInfo1->timings2[i].refresh == MonInfo2->timings2[j].refresh)) {
- stdtiming = MonInfo1->timings2[i];
- break;
- }
- }
-
- MonInfo->timings2[i] = stdtiming;
- } /* Std. Timing */
+ if (Flags)
+ {
+ MonInfo = MonInfo1 = xf86InterpretEDID(pScrn->scrnIndex, DDC_data);
+ }
+
+ /* For VGA2 CLONE Support, ycchen@012508 */
+ if ((xf86ReturnOptValBool(pAST->Options, OPTION_VGA2_CLONE, FALSE)) || pAST->VGA2Clone) {
+ if (GetVGA2EDID(pScrn, DDC_data) == TRUE) {
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Get VGA2 EDID Correctly!! \n");
+ MonInfo2 = xf86InterpretEDID(pScrn->scrnIndex, DDC_data);
+ if (MonInfo1 == NULL) /* No DDC1 EDID */
+ MonInfo = MonInfo2;
+ else { /* Check with VGA1 & VGA2 EDID */
+ /* Update establishment timing */
+ MonInfo->timings1.t1 = MonInfo1->timings1.t1 & MonInfo2->timings1.t1;
+ MonInfo->timings1.t2 = MonInfo1->timings1.t2 & MonInfo2->timings1.t2;
+ MonInfo->timings1.t_manu = MonInfo1->timings1.t_manu & MonInfo2->timings1.t_manu;
- /* Get Detailed Timing */
- for (i=0;i<4;i++) {
- if (MonInfo1->det_mon[i].type == 0xFD)
- ranges1 = MonInfo1->det_mon[i].section.ranges;
- else if (MonInfo1->det_mon[i].type == 0xFA)
- stdtiming1 = MonInfo1->det_mon[i].section.std_t;
- else if (MonInfo1->det_mon[i].type == 0x00) {
- if (MonInfo1->det_mon[i].section.d_timings.clock > dclock1)
- dclock1 = MonInfo1->det_mon[i].section.d_timings.clock;
- if (MonInfo1->det_mon[i].section.d_timings.h_active > h_active1)
- h_active1 = MonInfo1->det_mon[i].section.d_timings.h_active;
- if (MonInfo1->det_mon[i].section.d_timings.v_active > v_active1)
- v_active1 = MonInfo1->det_mon[i].section.d_timings.v_active;
- }
- if (MonInfo2->det_mon[i].type == 0xFD)
- ranges2 = MonInfo2->det_mon[i].section.ranges;
- else if (MonInfo1->det_mon[i].type == 0xFA)
- stdtiming2 = MonInfo2->det_mon[i].section.std_t;
- else if (MonInfo2->det_mon[i].type == 0x00) {
- if (MonInfo2->det_mon[i].section.d_timings.clock > dclock2)
- dclock2 = MonInfo2->det_mon[i].section.d_timings.clock;
- if (MonInfo2->det_mon[i].section.d_timings.h_active > h_active2)
- h_active2 = MonInfo2->det_mon[i].section.d_timings.h_active;
- if (MonInfo2->det_mon[i].section.d_timings.v_active > v_active2)
- v_active2 = MonInfo2->det_mon[i].section.d_timings.v_active;
- }
- } /* Get Detailed Timing */
-
- /* Chk Detailed Timing */
- if ((dclock1 >= dclock2) && (h_active1 >= h_active2) && (v_active1 >= v_active2))
- DTSelect = DT2;
- else if ((dclock2 >= dclock1) && (h_active2 >= h_active1) && (v_active2 >= v_active1))
- DTSelect = DT1;
- else
- DTSelect = SkipDT;
-
- /* Chk Monitor Descriptor */
- ranges = ranges1;
- ranges.min_h = ranges1.min_h > ranges2.min_h ? ranges1.min_h:ranges2.min_h;
- ranges.min_v = ranges1.min_v > ranges2.min_v ? ranges1.min_v:ranges2.min_v;
- ranges.max_h = ranges1.max_h < ranges2.max_h ? ranges1.max_h:ranges2.max_h;
- ranges.max_v = ranges1.max_v < ranges2.max_v ? ranges1.max_v:ranges2.max_v;
- ranges.max_clock = ranges1.max_clock < ranges2.max_clock ? ranges1.max_clock:ranges2.max_clock;
-
- /* Update Detailed Timing */
- for (i=0; i<4; i++)
- {
- if (MonInfo->det_mon[i].type == 0xFD) {
- MonInfo->det_mon[i].section.ranges = ranges;
- }
- else if (MonInfo->det_mon[i].type == 0xFA) {
- for (j=0; j<5; j++) {
- stdtiming.hsize = stdtiming.vsize = stdtiming.refresh = stdtiming.id = 0;
- for (k=0; k<5; k++) {
- if ((stdtiming1[j].hsize == stdtiming2[k].hsize) && \
- (stdtiming1[j].vsize == stdtiming2[k].vsize) && \
- (stdtiming1[j].refresh == stdtiming2[k].refresh)) {
- stdtiming = stdtiming1[j];
- break;
- }
- }
- stdtiming1[j] = stdtiming;
- } /* Std. Timing */
- } /* FA */
- else if (MonInfo->det_mon[i].type == 0x00) {
- if (DTSelect == DT2)
- MonInfo->det_mon[i] = MonInfo2->det_mon[i];
- else if (DTSelect == DT1)
- MonInfo->det_mon[i] = MonInfo1->det_mon[i];
- else /* SkipDT */
- { /* use 1024x768 as default */
- MonInfo->det_mon[i] = MonInfo1->det_mon[i];
- MonInfo->det_mon[i].section.d_timings.clock = 65000000;
- MonInfo->det_mon[i].section.d_timings.h_active = 1024;
- MonInfo->det_mon[i].section.d_timings.h_blanking = 320;
- MonInfo->det_mon[i].section.d_timings.v_active = 768;
- MonInfo->det_mon[i].section.d_timings.v_blanking = 38;
- MonInfo->det_mon[i].section.d_timings.h_sync_off = 24;
- MonInfo->det_mon[i].section.d_timings.h_sync_width = 136;
- MonInfo->det_mon[i].section.d_timings.v_sync_off = 3;
- MonInfo->det_mon[i].section.d_timings.v_sync_width = 6;
- }
- } /* 00 */
- else { /* use Monitor 1 as default */
- MonInfo->det_mon[i] = MonInfo1->det_mon[i];
- }
-
- } /* Update Detailed Timing */
-
- /* set feature size */
- if (DTSelect == DT2) {
- MonInfo->features.hsize = MonInfo2->features.hsize;
- MonInfo->features.vsize = MonInfo2->features.vsize;
- }
- else if (DTSelect == DT1) {
- MonInfo->features.hsize = MonInfo1->features.hsize;
- MonInfo->features.vsize = MonInfo1->features.vsize;
- }
- else /* Skip DT */
- { /* use 1024x768 as default */
- MonInfo->features.hsize = 0x20;
- MonInfo->features.vsize = 0x18;
+ /* Update Std. Timing */
+ for (i=0; i<8; i++) {
+ stdtiming.hsize = stdtiming.vsize = stdtiming.refresh = stdtiming.id = 0;
+ for (j=0; j<8; j++) {
+ if ((MonInfo1->timings2[i].hsize == MonInfo2->timings2[j].hsize) && \
+ (MonInfo1->timings2[i].vsize == MonInfo2->timings2[j].vsize) && \
+ (MonInfo1->timings2[i].refresh == MonInfo2->timings2[j].refresh)) {
+ stdtiming = MonInfo1->timings2[i];
+ break;
+ }
+ }
+
+ MonInfo->timings2[i] = stdtiming;
+ } /* Std. Timing */
+
+ /* Get Detailed Timing */
+ for (i=0;i<4;i++) {
+ if (MonInfo1->det_mon[i].type == 0xFD)
+ ranges1 = MonInfo1->det_mon[i].section.ranges;
+ else if (MonInfo1->det_mon[i].type == 0xFA)
+ stdtiming1 = MonInfo1->det_mon[i].section.std_t;
+ else if (MonInfo1->det_mon[i].type == 0x00) {
+ if (MonInfo1->det_mon[i].section.d_timings.clock > dclock1)
+ dclock1 = MonInfo1->det_mon[i].section.d_timings.clock;
+ if (MonInfo1->det_mon[i].section.d_timings.h_active > h_active1)
+ h_active1 = MonInfo1->det_mon[i].section.d_timings.h_active;
+ if (MonInfo1->det_mon[i].section.d_timings.v_active > v_active1)
+ v_active1 = MonInfo1->det_mon[i].section.d_timings.v_active;
}
-
- } /* Check with VGA1 & VGA2 EDID */
-
- } /* GetVGA2EDID */
- else {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Can't Get VGA2 EDID Correctly!! \n");
- }
-
- }
-
- /* save MonInfo to Private */
- pAST->mon_h_active = MonInfo->det_mon[0].section.d_timings.h_active;
- pAST->mon_v_active = MonInfo->det_mon[0].section.d_timings.v_active;
-
- xf86PrintEDID(MonInfo);
- xf86SetDDCproperties(pScrn, MonInfo);
- vbeFree(pVbe);
- } else {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "this driver cannot do DDC without VBE\n");
- }
+ if (MonInfo2->det_mon[i].type == 0xFD)
+ ranges2 = MonInfo2->det_mon[i].section.ranges;
+ else if (MonInfo1->det_mon[i].type == 0xFA)
+ stdtiming2 = MonInfo2->det_mon[i].section.std_t;
+ else if (MonInfo2->det_mon[i].type == 0x00) {
+ if (MonInfo2->det_mon[i].section.d_timings.clock > dclock2)
+ dclock2 = MonInfo2->det_mon[i].section.d_timings.clock;
+ if (MonInfo2->det_mon[i].section.d_timings.h_active > h_active2)
+ h_active2 = MonInfo2->det_mon[i].section.d_timings.h_active;
+ if (MonInfo2->det_mon[i].section.d_timings.v_active > v_active2)
+ v_active2 = MonInfo2->det_mon[i].section.d_timings.v_active;
+ }
+ } /* Get Detailed Timing */
+
+ /* Chk Detailed Timing */
+ if ((dclock1 >= dclock2) && (h_active1 >= h_active2) && (v_active1 >= v_active2))
+ DTSelect = DT2;
+ else if ((dclock2 >= dclock1) && (h_active2 >= h_active1) && (v_active2 >= v_active1))
+ DTSelect = DT1;
+ else
+ DTSelect = SkipDT;
- } /* AST1180 */
+ /* Chk Monitor Descriptor */
+ ranges = ranges1;
+ ranges.min_h = ranges1.min_h > ranges2.min_h ? ranges1.min_h:ranges2.min_h;
+ ranges.min_v = ranges1.min_v > ranges2.min_v ? ranges1.min_v:ranges2.min_v;
+ ranges.max_h = ranges1.max_h < ranges2.max_h ? ranges1.max_h:ranges2.max_h;
+ ranges.max_v = ranges1.max_v < ranges2.max_v ? ranges1.max_v:ranges2.max_v;
+ ranges.max_clock = ranges1.max_clock < ranges2.max_clock ? ranges1.max_clock:ranges2.max_clock;
+
+ /* Update Detailed Timing */
+ for (i=0; i<4; i++)
+ {
+ if (MonInfo->det_mon[i].type == 0xFD) {
+ MonInfo->det_mon[i].section.ranges = ranges;
+ }
+ else if (MonInfo->det_mon[i].type == 0xFA) {
+ for (j=0; j<5; j++) {
+ stdtiming.hsize = stdtiming.vsize = stdtiming.refresh = stdtiming.id = 0;
+ for (k=0; k<5; k++) {
+ if ((stdtiming1[j].hsize == stdtiming2[k].hsize) && \
+ (stdtiming1[j].vsize == stdtiming2[k].vsize) && \
+ (stdtiming1[j].refresh == stdtiming2[k].refresh)) {
+ stdtiming = stdtiming1[j];
+ break;
+ }
+ }
+ stdtiming1[j] = stdtiming;
+ } /* Std. Timing */
+ } /* FA */
+ else if (MonInfo->det_mon[i].type == 0x00) {
+ if (DTSelect == DT2)
+ MonInfo->det_mon[i] = MonInfo2->det_mon[i];
+ else if (DTSelect == DT1)
+ MonInfo->det_mon[i] = MonInfo1->det_mon[i];
+ else /* SkipDT */
+ { /* use 1024x768 as default */
+ MonInfo->det_mon[i] = MonInfo1->det_mon[i];
+ MonInfo->det_mon[i].section.d_timings.clock = 65000000;
+ MonInfo->det_mon[i].section.d_timings.h_active = 1024;
+ MonInfo->det_mon[i].section.d_timings.h_blanking = 320;
+ MonInfo->det_mon[i].section.d_timings.v_active = 768;
+ MonInfo->det_mon[i].section.d_timings.v_blanking = 38;
+ MonInfo->det_mon[i].section.d_timings.h_sync_off = 24;
+ MonInfo->det_mon[i].section.d_timings.h_sync_width = 136;
+ MonInfo->det_mon[i].section.d_timings.v_sync_off = 3;
+ MonInfo->det_mon[i].section.d_timings.v_sync_width = 6;
+ }
+ } /* 00 */
+ else { /* use Monitor 1 as default */
+ MonInfo->det_mon[i] = MonInfo1->det_mon[i];
+ }
+
+ } /* Update Detailed Timing */
+
+ /* set feature size */
+ if (DTSelect == DT2) {
+ MonInfo->features.hsize = MonInfo2->features.hsize;
+ MonInfo->features.vsize = MonInfo2->features.vsize;
+ }
+ else if (DTSelect == DT1) {
+ MonInfo->features.hsize = MonInfo1->features.hsize;
+ MonInfo->features.vsize = MonInfo1->features.vsize;
+ }
+ else /* Skip DT */
+ { /* use 1024x768 as default */
+ MonInfo->features.hsize = 0x20;
+ MonInfo->features.vsize = 0x18;
+ }
+
+ } /* Check with VGA1 & VGA2 EDID */
+
+ } /* GetVGA2EDID */
+ else {
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Can't Get VGA2 EDID Correctly!! \n");
+ }
+ } /* VGA2Clone */
+
+ xf86PrintEDID(MonInfo);
+ xf86SetDDCproperties(pScrn, MonInfo);
+ }
+ else
+ {
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,"[ASTDoDDC] Can't Load DDC Sub-Modules or Read EDID Failed \n");
+ }
+ /* Fill pAST Monitor Info */
+ if (MonInfo == NULL)
+ { /* default for Non-EDID */
+ pAST->mon_h_active = 1024;
+ pAST->mon_v_active = 768;
+ }
+ else
+ { /* save MonInfo to Private */
+ pAST->mon_h_active = MonInfo->det_mon[0].section.d_timings.h_active;
+ pAST->mon_v_active = MonInfo->det_mon[0].section.d_timings.v_active;
+ }
+
return MonInfo;
}
@@ -1561,12 +1646,21 @@ vFillASTModeInfo (ScrnInfoPtr pScrn)
static Bool
ASTModeInit(ScrnInfoPtr pScrn, DisplayModePtr mode)
{
- vgaHWPtr hwp;
ASTRecPtr pAST;
- hwp = VGAHWPTR(pScrn);
pAST = ASTPTR(pScrn);
+ pScrn->vtSema = TRUE;
+ pAST->ModePtr = mode;
+
+#if defined(__sparc__) || defined(__mips__)
+ if (!ASTSetMode(pScrn, mode))
+ return FALSE;
+#else
+ vgaHWPtr hwp;
+
+ hwp = VGAHWPTR(pScrn);
+
vgaHWUnlock(hwp);
if (!vgaHWInit(pScrn, mode))
@@ -1579,6 +1673,7 @@ ASTModeInit(ScrnInfoPtr pScrn, DisplayModePtr mode)
return FALSE;
vgaHWProtect(pScrn, FALSE);
+#endif
return TRUE;
}
diff --git a/src/ast_mode.c b/src/ast_mode.c
index b58916f..6073ed1 100644..100755
--- a/src/ast_mode.c
+++ b/src/ast_mode.c
@@ -203,23 +203,29 @@ VBIOS_ENHTABLE_STRUCT Res1920x1200Table[] = {
/* 16:10 */
VBIOS_ENHTABLE_STRUCT Res1280x800Table[] = {
+ {1440, 1280, 48, 32, 823, 800, 3, 6, VCLK71, /* 60Hz RB */
+ (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode), 60, 1, 35 },
{1680, 1280, 72,128, 831, 800, 3, 6, VCLK83_5, /* 60Hz */
- (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode), 60, 1, 0x35 },
+ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode), 60, 2, 0x35 },
{1680, 1280, 72,128, 831, 800, 3, 6, VCLK83_5, /* 60Hz */
(SyncPN | Charx8Dot | LineCompareOff | WideScreenMode), 0xFF, 1, 0x35 },
};
VBIOS_ENHTABLE_STRUCT Res1440x900Table[] = {
+ {1600, 1440, 48, 32, 926, 900, 3, 6, VCLK88_75, /* 60Hz RB */
+ (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode), 60, 1, 0x36 },
{1904, 1440, 80,152, 934, 900, 3, 6, VCLK106_5, /* 60Hz */
- (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode), 60, 1, 0x36 },
+ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode), 60, 2, 0x36 },
{1904, 1440, 80,152, 934, 900, 3, 6, VCLK106_5, /* 60Hz */
(SyncPN | Charx8Dot | LineCompareOff | WideScreenMode), 0xFF, 1, 0x36 },
};
VBIOS_ENHTABLE_STRUCT Res1680x1050Table[] = {
+ {1840, 1680, 48, 32, 1080, 1050, 3, 6, VCLK119, /* 60Hz RB */
+ (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode), 60, 1, 0x37 },
{2240, 1680,104,176, 1089, 1050, 3, 6, VCLK146_25, /* 60Hz */
- (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode), 60, 1, 0x37 },
+ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode), 60, 2, 0x37 },
{2240, 1680,104,176, 1089, 1050, 3, 6, VCLK146_25, /* 60Hz */
(SyncPN | Charx8Dot | LineCompareOff | WideScreenMode), 0xFF, 1, 0x37 },
};
@@ -253,7 +259,10 @@ VBIOS_DCLK_INFO DCLKTable [] = {
{0xa7, 0x78, 0x80}, /* 11: VCLK83.5 */
{0x28, 0x49, 0x80}, /* 12: VCLK106.5 */
{0x37, 0x49, 0x80}, /* 13: VCLK146.25 */
- {0x1f, 0x45, 0x80}, /* 14: VCLK148.5 */
+ {0x1f, 0x45, 0x80}, /* 14: VCLK148.5 */
+ {0x47, 0x6c, 0x80}, /* 15: VCLK71 */
+ {0x25, 0x65, 0x80}, /* 16: VCLK88.75 */
+ {0x77, 0x58, 0x80}, /* 17: VCLK119 */
};
VBIOS_DCLK_INFO DCLKTable_AST2100 [] = {
@@ -277,7 +286,10 @@ VBIOS_DCLK_INFO DCLKTable_AST2100 [] = {
{0x68, 0x6f, 0x80}, /* 11: VCLK83.5 */
{0x28, 0x49, 0x80}, /* 12: VCLK106.5 */
{0x37, 0x49, 0x80}, /* 13: VCLK146.25 */
- {0x1f, 0x45, 0x80}, /* 14: VCLK148.5 */
+ {0x1f, 0x45, 0x80}, /* 14: VCLK148.5 */
+ {0x47, 0x6c, 0x80}, /* 15: VCLK71 */
+ {0x25, 0x65, 0x80}, /* 16: VCLK88.75 */
+ {0x77, 0x58, 0x80}, /* 17: VCLK119 */
};
VBIOS_DAC_INFO DAC_TEXT[] = {
@@ -549,6 +561,13 @@ Bool bGetAST1000VGAModeInfo(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_
}
}
+ /* parsing for wide scrren reduced blank mode */
+ if (pVGAModeInfo->pEnhTableEntry->Flags & WideScreenMode)
+ {
+ if ((mode->Flags & V_PVSYNC) && (mode->Flags & V_NHSYNC)) /* CVT */
+ pVGAModeInfo->pEnhTableEntry++;
+ }
+
/* Update mode CRTC info */
ulHBorder = (pVGAModeInfo->pEnhTableEntry->Flags & HBorder) ? 8:0;
ulVBorder = (pVGAModeInfo->pEnhTableEntry->Flags & VBorder) ? 8:0;
@@ -798,6 +817,13 @@ void vSetExtReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAMod
SetIndexRegMask(CRTC_PORT,0xA3, 0xF0, (UCHAR) jRegA3);
SetIndexRegMask(CRTC_PORT,0xA8, 0xFD, (UCHAR) jRegA8);
+#if defined(__sparc__)
+ UCHAR jRegA2 = 0x80;
+ if ((pScrn->bitsPerPixel == 15) || (pScrn->bitsPerPixel == 16) )
+ jRegA2 |= 0x40;
+ SetIndexRegMask(CRTC_PORT,0xA2, 0x3F, (UCHAR) jRegA2);
+#endif
+
/* Set Threshold */
if (pAST->jChipType == AST2300)
{
diff --git a/src/ast_mode.h b/src/ast_mode.h
index aae1492..04e4962 100644..100755
--- a/src/ast_mode.h
+++ b/src/ast_mode.h
@@ -54,6 +54,9 @@
#define VCLK106_5 0x12
#define VCLK146_25 0x13
#define VCLK148_5 0x14
+#define VCLK71 0x15
+#define VCLK88_75 0x16
+#define VCLK119 0x17
/* Flags Definition */
#define Charx8Dot 0x00000001
diff --git a/src/ast_pcirename.h b/src/ast_pcirename.h
index f5085bd..f5085bd 100644..100755
--- a/src/ast_pcirename.h
+++ b/src/ast_pcirename.h
diff --git a/src/ast_tool.c b/src/ast_tool.c
index 1dd87f0..1dd87f0 100644..100755
--- a/src/ast_tool.c
+++ b/src/ast_tool.c
diff --git a/src/ast_vgatool.c b/src/ast_vgatool.c
index 4a90dd4..152db1d 100644..100755
--- a/src/ast_vgatool.c
+++ b/src/ast_vgatool.c
@@ -95,6 +95,11 @@ bASTRegInit(ScrnInfoPtr pScrn)
/* Enable MMIO */
SetIndexRegMask(CRTC_PORT,0xA1, 0xFF, 0x04);
+ /* Enable Big-Endian */
+#if defined(__sparc__)
+ SetIndexRegMask(CRTC_PORT,0xA2, 0xFF, 0x80);
+#endif
+
return (TRUE);
}
@@ -627,7 +632,7 @@ Bool bIsVGAEnabled(ScrnInfoPtr pScrn)
else
{
- ch = GetReg(pAST->RelocateIO+0x43);
+ ch = GetReg(VGA_ENABLE_PORT);
if (ch)
{
@@ -649,8 +654,8 @@ void vEnableVGA(ScrnInfoPtr pScrn)
pAST = ASTPTR(pScrn);
- SetReg(pAST->RelocateIO+0x43, 0x01);
- SetReg(pAST->RelocateIO+0x42, 0x01);
+ SetReg(VGA_ENABLE_PORT, 0x01);
+ SetReg(MISC_PORT_WRITE, 0x01);
}
@@ -1489,10 +1494,11 @@ void finetuneDQI(PAST2300DRAMParam param)
} /* finetuneDQI */
-void finetuneDQI_L(PAST2300DRAMParam param)
+Bool finetuneDQI_L(PAST2300DRAMParam param)
{
- ULONG gold_sadj[2], dllmin[16], dllmax[16], dlli, data, cnt, mask, passcnt;
+ ULONG gold_sadj[2], dllmin[16], dllmax[16], dlli, data, cnt, mask, passcnt, retry = 0;
UCHAR *mmiobase;
+ Bool status = FALSE;
mmiobase = param->pjMMIOVirtualAddress;
@@ -1540,9 +1546,14 @@ void finetuneDQI_L(PAST2300DRAMParam param)
passcnt++;
}
}
+ if (retry++ > 10)
+ goto FINETUNE_DONE;
if(passcnt != 16){
goto FINETUNE_START;
}
+ status = TRUE;
+
+FINETUNE_DONE:
gold_sadj[0] = gold_sadj[0] >> 4;
gold_sadj[1] = gold_sadj[0];
@@ -1593,6 +1604,8 @@ void finetuneDQI_L(PAST2300DRAMParam param)
}
MOutdwm(mmiobase, 0x1E6E0084, data);
+ return status;
+
} /* finetuneDQI_L */
void finetuneDQI_L2(PAST2300DRAMParam param)
@@ -1727,14 +1740,16 @@ void finetuneDQI_L2(PAST2300DRAMParam param)
} /* finetuneDQI_L2 */
-void CBRDLL2(PAST2300DRAMParam param)
+Bool CBRDLL2(PAST2300DRAMParam param)
{
- ULONG dllmin[2], dllmax[2], dlli, data, data2, passcnt;
+ ULONG dllmin[2], dllmax[2], dlli, data, data2, passcnt, retry=0;
UCHAR *mmiobase;
+ BOOL status = FALSE;
mmiobase = param->pjMMIOVirtualAddress;
- finetuneDQI_L(param);
+ if (finetuneDQI_L(param) == FALSE)
+ return status;
finetuneDQI_L2(param);
CBR_START2:
@@ -1775,12 +1790,17 @@ void CBRDLL2(PAST2300DRAMParam param)
break;
}
}
+ if (retry++ > 10)
+ goto CBR_DONE2;
if(dllmax[0] == 0 || (dllmax[0]-dllmin[0]) < CBR_THRESHOLD){
goto CBR_START2;
}
if(dllmax[1] == 0 || (dllmax[1]-dllmin[1]) < CBR_THRESHOLD){
goto CBR_START2;
}
+ status = TRUE;
+
+CBR_DONE2:
dlli = (dllmin[1] + dllmax[1]) >> 1;
dlli <<= 8;
dlli += (dllmin[0] + dllmax[0]) >> 1;
@@ -1789,7 +1809,6 @@ void CBRDLL2(PAST2300DRAMParam param)
data = (MIndwm(mmiobase, 0x1E6E0080) >> 24) & 0x1F;
data2 = (MIndwm(mmiobase, 0x1E6E0018) & 0xff80ffff) | (data << 16);
MOutdwm(mmiobase, 0x1E6E0018, data2);
- MOutdwm(mmiobase, 0x1E6E0024, 0x8001 | (data << 1) | (param->DLL2_FINETUNE_STEP << 8));
/* Wait DQSI latch phase calibration */
MOutdwm(mmiobase, 0x1E6E0074, 0x00000010);
@@ -1803,6 +1822,9 @@ void CBRDLL2(PAST2300DRAMParam param)
data = MIndwm(mmiobase, 0x1E6E0070);
}while(!(data & 0x00001000));
MOutdwm(mmiobase, 0x1E6E0070, 0x00000000);
+
+ return status;
+
} /* CBRDLL2 */
void GetDDR2Info(PAST2300DRAMParam param)
@@ -1841,7 +1863,7 @@ void GetDDR2Info(PAST2300DRAMParam param)
param->MADJ_MAX = 138;
param->DLL2_FINETUNE_STEP = 3;
break;
- case 336 : MOutdwm(mmiobase, 0x1E6E2020, 0x0190);
+ case 336 : MOutdwm(mmiobase, 0x1E6E2020, 0x0331);
param->WODT = 1;
param->REG_AC1 = 0x22202613;
param->REG_AC2 = 0xAA009016 | TRAP_AC2;
@@ -1849,11 +1871,29 @@ void GetDDR2Info(PAST2300DRAMParam param)
param->REG_MRS = 0x00000A02 | TRAP_MRS;
param->REG_EMRS = 0x00000040;
param->REG_DRV = 0x000000FA;
- param->REG_IOZ = 0x00000034;
+ param->REG_IOZ = 0x00000013;
param->REG_DQIDLY = 0x00000074;
param->REG_FREQ = 0x00004DC0;
param->MADJ_MAX = 96;
param->DLL2_FINETUNE_STEP = 3;
+
+ switch (param->DRAM_ChipID)
+ {
+ case DRAMTYPE_512Mx16:
+ param->REG_AC2 = 0xAA009012 | TRAP_AC2;
+ break;
+ default:
+ case DRAMTYPE_1Gx16:
+ param->REG_AC2 = 0xAA009016 | TRAP_AC2;
+ break;
+ case DRAMTYPE_2Gx16:
+ param->REG_AC2 = 0xAA009023 | TRAP_AC2;
+ break;
+ case DRAMTYPE_4Gx16:
+ param->REG_AC2 = 0xAA00903B | TRAP_AC2;
+ break;
+ }
+
break;
default:
case 396 : MOutdwm(mmiobase, 0x1E6E2020, 0x03F1);
@@ -2057,18 +2097,34 @@ void GetDDR3Info(PAST2300DRAMParam param)
param->RODT = 0;
switch(param->DRAM_Freq){
- case 336 : MOutdwm(mmiobase, 0x1E6E2020, 0x0190);
+ case 336 : MOutdwm(mmiobase, 0x1E6E2020, 0x0331);
param->WODT = 0;
param->REG_AC1 = 0x22202725;
param->REG_AC2 = 0xAA007613 | TRAP_AC2;
param->REG_DQSIC = 0x000000BA;
param->REG_MRS = 0x04001400 | TRAP_MRS;
param->REG_EMRS = 0x00000000;
- param->REG_IOZ = 0x00000034;
+ param->REG_IOZ = 0x00000024;
param->REG_DQIDLY = 0x00000074;
param->REG_FREQ = 0x00004DC0;
param->MADJ_MAX = 96;
param->DLL2_FINETUNE_STEP = 3;
+
+ switch (param->DRAM_ChipID)
+ {
+ default:
+ case DRAMTYPE_512Mx16:
+ case DRAMTYPE_1Gx16:
+ param->REG_AC2 = 0xAA007613 | TRAP_AC2;
+ break;
+ case DRAMTYPE_2Gx16:
+ param->REG_AC2 = 0xAA00761c | TRAP_AC2;
+ break;
+ case DRAMTYPE_4Gx16:
+ param->REG_AC2 = 0xAA007636 | TRAP_AC2;
+ break;
+ }
+
break;
default:
case 396 : MOutdwm(mmiobase, 0x1E6E2020, 0x03F1);
@@ -2264,12 +2320,15 @@ void GetDDR3Info(PAST2300DRAMParam param)
void DDR2_Init(PAST2300DRAMParam param)
{
- ULONG data, data2;
+ ULONG data, data2, retry = 0;
UCHAR *mmiobase;
mmiobase = param->pjMMIOVirtualAddress;
+DDR2_Init_Start:
MOutdwm(mmiobase, 0x1E6E0000, 0xFC600309);
+ MOutdwm(mmiobase, 0x1E6E0064, 0x00000000);
+ MOutdwm(mmiobase, 0x1E6E0034, 0x00000000);
MOutdwm(mmiobase, 0x1E6E0018, 0x00000100);
MOutdwm(mmiobase, 0x1E6E0024, 0x00000000);
MOutdwm(mmiobase, 0x1E6E0064, param->REG_MADJ);
@@ -2284,7 +2343,7 @@ void DDR2_Init(PAST2300DRAMParam param)
MOutdwm(mmiobase, 0x1E6E0014, param->REG_AC2);
MOutdwm(mmiobase, 0x1E6E0020, param->REG_DQSIC);
MOutdwm(mmiobase, 0x1E6E0080, 0x00000000);
- MOutdwm(mmiobase, 0x1E6E0084, 0x00000000);
+ MOutdwm(mmiobase, 0x1E6E0084, 0x00FFFFFF);
MOutdwm(mmiobase, 0x1E6E0088, param->REG_DQIDLY);
MOutdwm(mmiobase, 0x1E6E0018, 0x4040A130);
MOutdwm(mmiobase, 0x1E6E0018, 0x20402330);
@@ -2389,7 +2448,9 @@ void DDR2_Init(PAST2300DRAMParam param)
data = MIndwm(mmiobase, 0x1E6E0020);
}while(!(data & 0x00000800));
/* Calibrate the DQSI delay */
- CBRDLL2(param);
+ if ((CBRDLL2(param)==FALSE) && (retry++ < 10))
+ goto DDR2_Init_Start;
+
/* ECC Memory Initialization */
#ifdef ECC
@@ -2406,15 +2467,17 @@ void DDR2_Init(PAST2300DRAMParam param)
void DDR3_Init(PAST2300DRAMParam param)
{
- ULONG data, data2;
+ ULONG data, data2, retry = 0;
UCHAR *mmiobase;
mmiobase = param->pjMMIOVirtualAddress;
+DDR3_Init_Start:
MOutdwm(mmiobase, 0x1E6E0000, 0xFC600309);
+ MOutdwm(mmiobase, 0x1E6E0064, 0x00000000);
+ MOutdwm(mmiobase, 0x1E6E0034, 0x00000000);
MOutdwm(mmiobase, 0x1E6E0018, 0x00000100);
MOutdwm(mmiobase, 0x1E6E0024, 0x00000000);
- MOutdwm(mmiobase, 0x1E6E0034, 0x00000000);
usleep(10);
MOutdwm(mmiobase, 0x1E6E0064, param->REG_MADJ);
MOutdwm(mmiobase, 0x1E6E0068, param->REG_SADJ);
@@ -2428,7 +2491,7 @@ void DDR3_Init(PAST2300DRAMParam param)
MOutdwm(mmiobase, 0x1E6E0014, param->REG_AC2);
MOutdwm(mmiobase, 0x1E6E0020, param->REG_DQSIC);
MOutdwm(mmiobase, 0x1E6E0080, 0x00000000);
- MOutdwm(mmiobase, 0x1E6E0084, 0x00000000);
+ MOutdwm(mmiobase, 0x1E6E0084, 0x00FFFFFF);
MOutdwm(mmiobase, 0x1E6E0088, param->REG_DQIDLY);
MOutdwm(mmiobase, 0x1E6E0018, 0x4040A170);
MOutdwm(mmiobase, 0x1E6E0018, 0x20402370);
@@ -2528,7 +2591,8 @@ void DDR3_Init(PAST2300DRAMParam param)
data = MIndwm(mmiobase, 0x1E6E0020);
}while(!(data & 0x00000800));
/* Calibrate the DQSI delay */
- CBRDLL2(param);
+ if ((CBRDLL2(param)==FALSE) && (retry++ < 10))
+ goto DDR3_Init_Start;
MOutdwm(mmiobase, 0x1E6E0120, param->REG_FREQ);
/* ECC Memory Initialization */
@@ -2973,8 +3037,9 @@ Bool bInitAST1180(ScrnInfoPtr pScrn)
ReadAST1180SOC(AST1180_SCU_BASE+0x0c, ulData); /* 2d clk */
ulData &= 0xFFFFFFFD;
WriteAST1180SOC(AST1180_SCU_BASE+0x0c, ulData);
-
- return (TRUE);
+
+ return (TRUE);
+
} /* bInitAST1180 */
void GetAST1180DRAMInfo(ScrnInfoPtr pScrn)
@@ -3031,3 +3096,29 @@ void GetAST1180DRAMInfo(ScrnInfoPtr pScrn)
pAST->ulMCLK = 200;
} /* GetAST1180DRAMInfo */
+
+void vEnableASTVGAMMIO(ScrnInfoPtr pScrn)
+{
+ ASTRecPtr pAST = ASTPTR(pScrn);
+ ULONG ulData;
+ UCHAR jReg;
+
+ if (!xf86IsPrimaryPci(pAST->PciInfo))
+ {
+ /* Enable PCI */
+ PCI_READ_LONG(pAST->PciInfo, &ulData, 0x04);
+ ulData |= 0x03;
+ PCI_WRITE_LONG(pAST->PciInfo, ulData, 0x04);
+
+ outb(pAST->RelocateIO + 0x43, 0x01);
+ outb(pAST->RelocateIO + 0x42, 0x01);
+ }
+
+ jReg = GetReg(VGA_ENABLE_PORT);
+ if (jReg == 0xFF) /* MMIO Access is disabled */
+ {
+ outw(pAST->RelocateIO + 0x54, 0xa880);
+ outw(pAST->RelocateIO + 0x54, 0x04a1);
+ }
+
+} /* vEnableASTVGAMMIO */
diff --git a/src/ast_vgatool.h b/src/ast_vgatool.h
index 53cb4c7..275369b 100644..100755
--- a/src/ast_vgatool.h
+++ b/src/ast_vgatool.h
@@ -40,36 +40,38 @@
#define DRAMTYPE_2Gx16 6
#define DRAMTYPE_4Gx16 7
-#define AR_PORT_WRITE (pAST->RelocateIO + 0x40)
-#define MISC_PORT_WRITE (pAST->RelocateIO + 0x42)
-#define SEQ_PORT (pAST->RelocateIO + 0x44)
+#define AR_PORT_WRITE (pAST->MMIOVirtualAddr + 0x3c0)
+#define MISC_PORT_WRITE (pAST->MMIOVirtualAddr + 0x3c2)
+#define VGA_ENABLE_PORT (pAST->MMIOVirtualAddr + 0x3c3)
+#define SEQ_PORT (pAST->MMIOVirtualAddr + 0x3c4)
#define DAC_INDEX_READ (pAST->MMIOVirtualAddr + 0x3c7)
-#define DAC_INDEX_WRITE (pAST->RelocateIO + 0x48)
-#define DAC_DATA (pAST->RelocateIO + 0x49)
-#define GR_PORT (pAST->RelocateIO + 0x4E)
-#define CRTC_PORT (pAST->RelocateIO + 0x54)
-#define INPUT_STATUS1_READ (pAST->RelocateIO + 0x5A)
-#define MISC_PORT_READ (pAST->RelocateIO + 0x4C)
-
-#define GetReg(base) inb(base)
-#define SetReg(base,val) outb(base,val)
-#define GetIndexReg(base,index,val) do { \
- outb(base,index); \
- val = inb(base+1); \
- } while (0)
-#define SetIndexReg(base,index, val) do { \
- outw(base, ((USHORT)(val) << 8) | index); \
- } while (0)
-#define GetIndexRegMask(base,index, and, val) do { \
- outb(base,index); \
- val = (inb(base+1) & and); \
- } while (0)
-#define SetIndexRegMask(base,index, and, val) do { \
- UCHAR __Temp; \
- outb(base,index); \
- __Temp = (inb((base)+1)&(and))|(val); \
- SetIndexReg(base,index,__Temp); \
- } while (0)
+#define DAC_INDEX_WRITE (pAST->MMIOVirtualAddr + 0x3c8)
+#define DAC_DATA (pAST->MMIOVirtualAddr + 0x3c9)
+#define GR_PORT (pAST->MMIOVirtualAddr + 0x3cE)
+#define CRTC_PORT (pAST->MMIOVirtualAddr + 0x3d4)
+#define INPUT_STATUS1_READ (pAST->MMIOVirtualAddr + 0x3dA)
+#define MISC_PORT_READ (pAST->MMIOVirtualAddr + 0x3cc)
+
+#define GetReg(base) MMIO_IN8(base, 0)
+#define SetReg(base,val) MMIO_OUT8(base, 0, val)
+#define GetIndexReg(base,index,val) { \
+ MMIO_OUT8(base, 0, index); \
+ val = MMIO_IN8(base, 1); \
+ }
+#define SetIndexReg(base,index, val) { \
+ MMIO_OUT8(base, 0, index); \
+ MMIO_OUT8(base, 1, val); \
+ }
+#define GetIndexRegMask(base,index, and, val) { \
+ MMIO_OUT8(base, 0, index); \
+ val = MMIO_IN8(base, 1) & and; \
+ }
+#define SetIndexRegMask(base,index, and, val) { \
+ UCHAR __Temp; \
+ MMIO_OUT8(base, 0, index); \
+ __Temp = (MMIO_IN8(base, 1)&(and))|(val); \
+ SetIndexReg(base,index,__Temp); \
+ }
#define VGA_GET_PALETTE_INDEX(index, red, green, blue) \
{ \
@@ -82,6 +84,7 @@
__junk = GetReg(SEQ_PORT); \
blue = GetReg(DAC_DATA); \
__junk = GetReg(SEQ_PORT); \
+ (void)__junk; \
}
#define VGA_LOAD_PALETTE_INDEX(index, red, green, blue) \
@@ -94,7 +97,8 @@
SetReg(DAC_DATA,(UCHAR)(green)); \
__junk = GetReg(SEQ_PORT); \
SetReg(DAC_DATA,(UCHAR)(blue)); \
- __junk = GetReg(SEQ_PORT); \
+ __junk = GetReg(SEQ_PORT); \
+ (void)__junk; \
}
/* Reg. Definition */
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-21 15:03:39 +0000