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authorAlex Deucher <alexdeucher@gmail.com>2009-04-01 15:23:17 -0400
committerAlex Deucher <alexdeucher@gmail.com>2009-04-15 11:45:52 -0400
commita34a8b37afbea6ed4bf8ca42364195e174250c48 (patch)
treefc84d444215e80d5601329ac82309d44987eba5c
parent1f0dc778dc25f4f85fedd73c55c847cab2c79fc5 (diff)
Set default low power PCIE lanes to 2
1 lane seems to cause occasional corruption when blitting to/from gart memory.
-rw-r--r--src/radeon_pm.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/radeon_pm.c b/src/radeon_pm.c
index d518998a..ac6b972b 100644
--- a/src/radeon_pm.c
+++ b/src/radeon_pm.c
@@ -589,7 +589,7 @@ void RADEONStaticLowPowerMode(ScrnInfoPtr pScrn, Bool enable)
RADEONSetEngineClock(pScrn, sclk/2);
if (info->cardType == CARD_PCIE)
- RADEONSetPCIELanes(pScrn, 1);
+ RADEONSetPCIELanes(pScrn, 2);
info->low_power_mode = TRUE;
} else {