diff options
| author | Karl Tomlinson <karlt+@karlt.net> | 2010-08-22 20:04:42 +1200 |
|---|---|---|
| committer | Michel Dänzer <michel@daenzer.net> | 2010-09-20 10:13:06 +0200 |
| commit | 4ced4e1eff67946e306c0c67c9ed59dd5f3c4ba9 (patch) | |
| tree | 6df2384883a08e5bbfb589057385dfc4d81f8ec4 | |
| parent | a4eef8faffbb1ea2f742273ee855f4e6f992e5c8 (diff) | |
RADEONDownloadFromScreenCS: flush CS writes before mapping BO for read
If unflushed CS operations write to the pixmap BO, then these need to be
flushed before mapping the BO for read. This currently only affects big
endian systems and only when the operation writes to the GTT domain.
| -rw-r--r-- | src/radeon_exa_funcs.c | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/src/radeon_exa_funcs.c b/src/radeon_exa_funcs.c index a82e416c..d02c787d 100644 --- a/src/radeon_exa_funcs.c +++ b/src/radeon_exa_funcs.c @@ -567,6 +567,9 @@ RADEONDownloadFromScreenCS(PixmapPtr pSrc, int x, int y, int w, unsigned bpp = pSrc->drawable.bitsPerPixel; uint32_t scratch_pitch = RADEON_ALIGN(w * bpp / 8, 64); uint32_t swap = RADEON_HOST_DATA_SWAP_NONE; +#if X_BYTE_ORDER == X_BIG_ENDIAN + Bool flush = FALSE; +#endif Bool r; if (bpp < 8) @@ -593,6 +596,10 @@ RADEONDownloadFromScreenCS(PixmapPtr pSrc, int x, int y, int w, if ((src_domain & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM)) == (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM)) src_domain = 0; +#if X_BYTE_ORDER == X_BIG_ENDIAN + else /* A write may be scheduled */ + flush = TRUE; +#endif } if (!src_domain) @@ -631,11 +638,14 @@ RADEONDownloadFromScreenCS(PixmapPtr pSrc, int x, int y, int w, scratch_pitch << 16, x, y, 0, 0, w, h, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, RADEON_GEM_DOMAIN_GTT); - FLUSH_RING(); - #if X_BYTE_ORDER == X_BIG_ENDIAN + flush = TRUE; + copy: + if (flush) #endif + FLUSH_RING(); + r = radeon_bo_map(scratch, 0); if (r) { r = FALSE; |