Fix spelling/wording issues

Found by using:
    codespell --builtin clear,rare,usage,informal,code,names

Signed-off-by: Alan Coopersmith <alan.coopersmith@oracle.com>

7 files changed, 14 insertions, 14 deletions

diff --git a/README.md b/README.md
index 7c9925c7..98666d48 100644
--- a/README.md
+++ b/README.md
@@ -10,7 +10,7 @@ Please submit bug reports to the Xorg bugzilla:
 
   https://bugs.freedesktop.org/enter_bug.cgi?product=xorg&component=Driver/Radeon
 
-The master development code repository can be found at:
+The primary development code repository can be found at:
 
   https://gitlab.freedesktop.org/xorg/driver/xf86-video-ati
 
diff --git a/src/cayman_shader.h b/src/cayman_shader.h
index c4cdc688..9cc5ed8f 100644
--- a/src/cayman_shader.h
+++ b/src/cayman_shader.h
@@ -30,7 +30,7 @@
 
 #include "radeon.h"
 
-/* Oder of instructions: All CF, All ALU, All Tex/Vtx fetches */
+/* Order of instructions: All CF, All ALU, All Tex/Vtx fetches */
 
 
 // CF insts
diff --git a/src/evergreen_shader.h b/src/evergreen_shader.h
index 8c7136b7..c82672b4 100644
--- a/src/evergreen_shader.h
+++ b/src/evergreen_shader.h
@@ -30,7 +30,7 @@
 
 #include "radeon.h"
 
-/* Oder of instructions: All CF, All ALU, All Tex/Vtx fetches */
+/* Order of instructions: All CF, All ALU, All Tex/Vtx fetches */
 
 
 // CF insts
diff --git a/src/r600_shader.h b/src/r600_shader.h
index d79ed400..b34670ee 100644
--- a/src/r600_shader.h
+++ b/src/r600_shader.h
@@ -53,12 +53,12 @@
  * Special case: square() - i.e. same component in src0+src1 doesn't need read port -> ignores swizzle for src1.
  * No restrictions for constants or PV/PS.
  * t can load multiple components in a single cycle slot, but has to share cycles with xyzw.
- * t with single constant may not load GPRs or PV/PS in cycle 0 (carefull with ALU_TRANS_210).
+ * t with single constant may not load GPRs or PV/PS in cycle 0 (careful with ALU_TRANS_210).
  * t with two constants may only load GPRs or PV/PS in cycle 2.
  */
 
 
-/* Oder of instructions: All CF, All ALU, All Tex/Vtx fetches */
+/* Order of instructions: All CF, All ALU, All Tex/Vtx fetches */
 
 
 // CF insts
@@ -174,7 +174,7 @@
     cpu_to_le32((((array_base) << 0) | ((type) << 13) | ((rw_gpr) << 15) | ((rr) << 22) | ((index_gpr) << 23) | \
 		 ((es) << 30)))
 // R7xx apparently doesn't have the ELEM_LOOP entry any more
-// We still expose it, but ELEM_LOOP is explicitely R6xx now.
+// We still expose it, but ELEM_LOOP is explicitly R6xx now.
 // TODO: is this just forgotten in the docs, or really not available any more?
 #define CF_ALLOC_IMP_EXP_DWORD1_BUF(array_size, comp_mask, el, bc, eop, vpm, cf_inst, wqm, b) \
     cpu_to_le32((((array_size) << 0) | ((comp_mask) << 12) | ((el) << 16) | ((bc) << 17) | \
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index c61d83f4..a5f9612b 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -1511,7 +1511,7 @@ static Bool R300PrepareComposite(int op, PicturePtr pSrcPicture,
      * DST_VEC_LOC is the slot in the PVS input vector memory when PVS/TCL is
      * enabled.  This memory provides the imputs to the vertex shader program
      * and ordering is not important.  When PVS/TCL is disabled, this field maps
-     * directly to the GA input memory and the order is signifigant.  In
+     * directly to the GA input memory and the order is significant.  In
      * PVS_BYPASS mode the order is as follows:
      * Position
      * Point Size
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index 0959b119..ba10c60d 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -1134,7 +1134,7 @@ R300PrepareTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
      * DST_VEC_LOC is the slot in the PVS input vector memory when PVS/TCL is
      * enabled.  This memory provides the imputs to the vertex shader program
      * and ordering is not important.  When PVS/TCL is disabled, this field maps
-     * directly to the GA input memory and the order is signifigant.  In
+     * directly to the GA input memory and the order is significant.  In
      * PVS_BYPASS mode the order is as follows:
      * Position
      * Point Size
@@ -2578,7 +2578,7 @@ R500PrepareTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
      * DST_VEC_LOC is the slot in the PVS input vector memory when PVS/TCL is
      * enabled.  This memory provides the imputs to the vertex shader program
      * and ordering is not important.  When PVS/TCL is disabled, this field maps
-     * directly to the GA input memory and the order is signifigant.  In
+     * directly to the GA input memory and the order is significant.  In
      * PVS_BYPASS mode the order is as follows:
      * Position
      * Point Size
diff --git a/src/simple_list.h b/src/simple_list.h
index ff7f8882..0be4ad1a 100644
--- a/src/simple_list.h
+++ b/src/simple_list.h
@@ -2,7 +2,7 @@
  * \file simple_list.h
  * Simple macros for type-safe, intrusive lists.
  *
- *  Intended to work with a list sentinal which is created as an empty
+ *  Intended to work with a list sentinel which is created as an empty
  *  list.  Insert & delete are O(1).
  *  
  * \author
@@ -108,12 +108,12 @@ do {						\
 /**
  * Make a empty list empty.
  *
- * \param sentinal list (sentinal element).
+ * \param sentinel list (sentinel element).
  */
-#define make_empty_list(sentinal)		\
+#define make_empty_list(sentinel)		\
 do {						\
-   (sentinal)->next = sentinal;			\
-   (sentinal)->prev = sentinal;			\
+   (sentinel)->next = sentinel;			\
+   (sentinel)->prev = sentinel;			\
 } while (0)
 
 /**