radeon: port to new space checking in libdrm interface

This uses a new libdrm interface which shares code with mesa.

It also fixes the bo to flush when full instead of never flushing.

It survives gtkperf -a here which the driver didn't before now

9 files changed, 132 insertions, 214 deletions

diff --git a/src/radeon.h b/src/radeon.h
index 82136c83..c0300348 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -1069,7 +1069,6 @@ extern void RADEONWaitForFifoFunction(ScrnInfoPtr pScrn, int entries);
 #ifdef XF86DRI
 extern drmBufPtr RADEONCPGetBuffer(ScrnInfoPtr pScrn);
 extern void RADEONCPFlushIndirect(ScrnInfoPtr pScrn, int discard);
-extern void radeon_cs_flush_indirect(ScrnInfoPtr pScrn);
 extern void RADEONCPReleaseIndirect(ScrnInfoPtr pScrn);
 extern int RADEONCPStop(ScrnInfoPtr pScrn,  RADEONInfoPtr info);
 #  ifdef USE_XAA
@@ -1266,6 +1265,12 @@ extern void
 radeon_legacy_free_memory(ScrnInfoPtr pScrn,
 		          void *mem_struct);
 
+#ifdef XF86DRM_MODE
+extern void radeon_cs_flush_indirect(ScrnInfoPtr pScrn);
+extern void radeon_ddx_cs_start(ScrnInfoPtr pScrn,
+				int num, const char *file,
+				const char *func, int line);
+#endif
 struct radeon_bo *radeon_get_pixmap_bo(PixmapPtr pPix);
 void radeon_set_pixmap_bo(PixmapPtr pPix, struct radeon_bo *bo);
 
@@ -1355,7 +1360,7 @@ do {									\
 	xf86DrvMsg(pScrn->scrnIndex, X_INFO,				\
 		   "BEGIN_RING(%d) in %s\n", (unsigned int)n, __FUNCTION__);\
     }									\
-    if (info->cs) radeon_cs_begin(info->cs, n, __FILE__, __func__, __LINE__); else { \
+    if (info->cs) { radeon_ddx_cs_start(pScrn, n, __FILE__, __func__, __LINE__); } else { \
       if (++info->cp->dma_begin_count != 1) {				\
 	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,				\
 		   "BEGIN_RING without end at %s:%d\n",			\
diff --git a/src/radeon_accel.c b/src/radeon_accel.c
index 79052a15..02905dd1 100644
--- a/src/radeon_accel.c
+++ b/src/radeon_accel.c
@@ -658,18 +658,6 @@ int RADEONCPStop(ScrnInfoPtr pScrn, RADEONInfoPtr info)
 
 #define RADEON_IB_RESERVE (16 * sizeof(uint32_t))
 
-void radeon_cs_flush_indirect(ScrnInfoPtr pScrn)
-{
-#ifdef XF86DRM_MODE
-    RADEONInfoPtr  info = RADEONPTR(pScrn);
-
-    if (!info->cs->cdw)
-	return;
-    radeon_cs_emit(info->cs);
-    radeon_cs_erase(info->cs);
-#endif
-}
-
 /* Get an indirect buffer for the CP 2D acceleration commands  */
 drmBufPtr RADEONCPGetBuffer(ScrnInfoPtr pScrn)
 {
diff --git a/src/radeon_dummy_bufmgr.h b/src/radeon_dummy_bufmgr.h
index bf89292c..b3ff9910 100644
--- a/src/radeon_dummy_bufmgr.h
+++ b/src/radeon_dummy_bufmgr.h
@@ -39,19 +39,24 @@ static inline struct radeon_bo *radeon_bo_unref(struct radeon_bo *bo) {return NU
 static inline void radeon_bo_unmap(struct radeon_bo *bo) {return;}
 static inline int radeon_bo_wait(struct radeon_bo *bo) {return 0;}
 
+static inline int radeon_cs_space_add_persistent_bo(Bool cs, struct radeon_bo *bo,
+						    uint32_t read_domains, uint32_t write_domain)
+{
+  return 0;
+}
 
-struct radeon_cs_space_check {
-  struct radeon_bo *bo;
-  int read_domains;
-  int write_domain;
-  int new_accounted;
-};
-
-static inline int radeon_cs_space_check(Bool cs, struct radeon_cs_space_check *bos, int num)
+static inline int radeon_cs_space_check(Bool cs)
 {
   return 0;
 }
-#define RADEON_CS_SPACE_OP_TO_BIG 0
-#define RADEON_CS_SPACE_FLUSH 1
+
+static inline void radeon_cs_flush_indirect(ScrnInfoPtr pScrn)
+{
+}
+
+static inline void radeon_ddx_cs_start(ScrnInfoPtr pScrn, int n,
+				       const char *file, const char *func, int line);
+{
+}
 
 #endif
diff --git a/src/radeon_exa.c b/src/radeon_exa.c
index ca4eda07..e7f1e9ca 100644
--- a/src/radeon_exa.c
+++ b/src/radeon_exa.c
@@ -120,13 +120,11 @@ static __inline__ uint32_t F_TO_DW(float val)
     return tmp.l;
 }
 
-static inline void radeon_add_pixmap(struct radeon_cs_space_check *bos, int index, PixmapPtr pPix, int read_domains, int write_domain)
+static inline void radeon_add_pixmap(struct radeon_cs *cs, PixmapPtr pPix, int read_domains, int write_domain)
 {
     struct radeon_exa_pixmap_priv *driver_priv = exaGetPixmapDriverPrivate(pPix);
-    bos[index].bo = driver_priv->bo;
-    bos[index].read_domains = read_domains;
-    bos[index].write_domain = write_domain;
-    bos[index].new_accounted = 0;
+
+    radeon_cs_space_add_persistent_bo(cs, driver_priv->bo, read_domains, write_domain);
 }
 
 /* Assumes that depth 15 and 16 can be used as depth 16, which is okay since we
@@ -344,7 +342,7 @@ static Bool RADEONPrepareAccess_CS(PixmapPtr pPix, int index)
 
     /* if we have more refs than just the BO then flush */
     if (driver_priv->bo->cref > 1)
-      radeon_cs_flush_indirect(pScrn);
+        radeon_cs_flush_indirect(pScrn);
     
     radeon_bo_wait(driver_priv->bo);
 
diff --git a/src/radeon_exa_funcs.c b/src/radeon_exa_funcs.c
index 5b723609..460824dd 100644
--- a/src/radeon_exa_funcs.c
+++ b/src/radeon_exa_funcs.c
@@ -138,9 +138,6 @@ FUNC_NAME(RADEONPrepareSolid)(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
     uint32_t datatype, dst_pitch_offset;
     struct radeon_exa_pixmap_priv *driver_priv;
     int ret;
-    int retry_count = 0;
-    struct radeon_cs_space_check bos[1];
-    int i;
 
     TRACE;
 
@@ -152,28 +149,17 @@ FUNC_NAME(RADEONPrepareSolid)(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
 	RADEON_FALLBACK(("RADEONGetPixmapOffsetPitch failed\n"));
 
     RADEON_SWITCH_TO_2D();
- retry:
+
     if (info->cs) {
       
-	i = 0;
+	radeon_cs_space_reset_bos(info->cs);
+
 	driver_priv = exaGetPixmapDriverPrivate(pPix);
-	bos[i].bo = driver_priv->bo;
-	bos[i].read_domains = 0;
-	bos[i].write_domain = RADEON_GEM_DOMAIN_VRAM;;
-	bos[i].new_accounted = 0;
-	i++;
-
-	ret = radeon_cs_space_check(info->cs, bos, i);
-	if (ret == RADEON_CS_SPACE_OP_TO_BIG) {
-	    RADEON_FALLBACK(("Not enough RAM to hw accel composite operation\n"));
-	}
-	if (ret == RADEON_CS_SPACE_FLUSH) {
-	    radeon_cs_flush_indirect(pScrn);
-	    retry_count++;
-	    if (retry_count == 2)
-	        RADEON_FALLBACK(("Not enough Video RAM for src\n"));
-	    goto retry;
-	}
+	radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM);
+
+	ret = radeon_cs_space_check(info->cs);
+	if (ret)
+	    RADEON_FALLBACK(("Not enough RAM to hw accel solid operation\n"));
     }
 
 
@@ -279,40 +265,27 @@ FUNC_NAME(RADEONPrepareCopy)(PixmapPtr pSrc,   PixmapPtr pDst,
     uint32_t datatype, src_pitch_offset, dst_pitch_offset;
     struct radeon_exa_pixmap_priv *driver_priv;
     int ret;
-    int retry_count = 0;
-    struct radeon_cs_space_check bos[2];
-    int i;
     TRACE;
 
     RADEON_SWITCH_TO_2D();
-retry:
+
     if (info->cs) {
       
+	radeon_cs_space_reset_bos(info->cs);
+
 	driver_priv = exaGetPixmapDriverPrivate(pSrc);
+	radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
 	info->state_2d.src_bo = driver_priv->bo;
 
 	driver_priv = exaGetPixmapDriverPrivate(pDst);
+	radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM);
 	info->state_2d.dst_bo = driver_priv->bo;
 
-	i = 0;
-	radeon_add_pixmap(bos, i++, pSrc, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
-
-	radeon_add_pixmap(bos, i++, pDst, 0, RADEON_GEM_DOMAIN_VRAM);
-
-	ret = radeon_cs_space_check(info->cs, bos, i);
-	if (ret == RADEON_CS_SPACE_OP_TO_BIG) {
-	    RADEON_FALLBACK(("Not enough RAM to hw accel composite operation\n"));
-	}
-	if (ret == RADEON_CS_SPACE_FLUSH) {
-	    radeon_cs_flush_indirect(pScrn);
-	    retry_count++;
-	    if (retry_count == 2)
-	        RADEON_FALLBACK(("Not enough Video RAM for src\n"));
-	    goto retry;
-	}
+	ret = radeon_cs_space_check(info->cs);
+	if (ret)
+	    RADEON_FALLBACK(("Not enough RAM to hw accel copy operation\n"));
     }
 
-
     info->accel_state->xdir = xdir;
     info->accel_state->ydir = ydir;
 
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index 60c40a23..1e07408d 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -557,9 +557,7 @@ static Bool FUNC_NAME(R100PrepareComposite)(int op,
     uint32_t pp_cntl, blendcntl, cblend, ablend;
     int pixel_shift;
     struct radeon_exa_pixmap_priv *driver_priv;
-    int retry_count = 0;
-    struct radeon_cs_space_check bos[3];
-    int i, ret;
+    int ret;
     ACCEL_PREAMBLE();
 
     TRACE;
@@ -589,28 +587,21 @@ static Bool FUNC_NAME(R100PrepareComposite)(int op,
 
     /* switch to 3D before doing buffer space checks as it may flush */
     RADEON_SWITCH_TO_3D();
- retry:
+
     if (info->cs) {
-      
-	i = 0;
-	radeon_add_pixmap(bos, i++, pSrc, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
+	radeon_cs_space_reset_bos(info->cs);
+
+	radeon_add_pixmap(info->cs, pSrc,
+			  RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
 
 	if (pMask)
-	    radeon_add_pixmap(bos, i++, pMask, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
+	    radeon_add_pixmap(info->cs, pMask, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
 
-	radeon_add_pixmap(bos, i++, pDst, 0, RADEON_GEM_DOMAIN_VRAM);
+	radeon_add_pixmap(info->cs, pDst, 0, RADEON_GEM_DOMAIN_VRAM);
 
-	ret = radeon_cs_space_check(info->cs, bos, i);
-	if (ret == RADEON_CS_SPACE_OP_TO_BIG) {
+	ret = radeon_cs_space_check(info->cs);
+	if (ret)
 	    RADEON_FALLBACK(("Not enough RAM to hw accel composite operation\n"));
-	}
-	if (ret == RADEON_CS_SPACE_FLUSH) {
-	    radeon_cs_flush_indirect(pScrn);
-	    retry_count++;
-	    if (retry_count == 2)
-	        RADEON_FALLBACK(("Not enough Video RAM for src\n"));
-	    goto retry;
-	}
     }
 
     if (!RADEONSetupSourceTile(pSrcPicture, pSrc, FALSE, TRUE))
@@ -914,9 +905,7 @@ static Bool FUNC_NAME(R200PrepareComposite)(int op, PicturePtr pSrcPicture,
     uint32_t pp_cntl, blendcntl, cblend, ablend, colorpitch;
     int pixel_shift;
     struct radeon_exa_pixmap_priv *driver_priv;
-    int retry_count = 0;
-    struct radeon_cs_space_check bos[3];
-    int i, ret;
+    int ret;
     ACCEL_PREAMBLE();
 
     TRACE;
@@ -947,29 +936,20 @@ static Bool FUNC_NAME(R200PrepareComposite)(int op, PicturePtr pSrcPicture,
     /* switch to 3D before doing buffer space checks as it may flush */
     RADEON_SWITCH_TO_3D();
 
- retry:
     if (info->cs) {
-      
-	i = 0;
-	radeon_add_pixmap(bos, i++, pSrc, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
+	radeon_cs_space_reset_bos(info->cs);
+        radeon_add_pixmap(info->cs, pSrc, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
 
 	if (pMask)
-	    radeon_add_pixmap(bos, i++, pMask, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
+	    radeon_add_pixmap(info->cs, pMask, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
 
-	radeon_add_pixmap(bos, i++, pDst, 0, RADEON_GEM_DOMAIN_VRAM);
+	radeon_add_pixmap(info->cs, pDst, 0, RADEON_GEM_DOMAIN_VRAM);
 
-	ret = radeon_cs_space_check(info->cs, bos, i);
-	if (ret == RADEON_CS_SPACE_OP_TO_BIG) {
-	    RADEON_FALLBACK(("Not enough RAM to hw accel composite operation\n"));
-	}
-	if (ret == RADEON_CS_SPACE_FLUSH) {
-	    radeon_cs_flush_indirect(pScrn);
-	    retry_count++;
-	    if (retry_count == 2)
-	        RADEON_FALLBACK(("Not enough Video RAM for src\n"));
-	    goto retry;
-	}
+	ret = radeon_cs_space_check(info->cs);
+	if (ret)
+ 	  RADEON_FALLBACK(("Not enough RAM to hw accel composite operation\n"));
     }
+
     if (!RADEONSetupSourceTile(pSrcPicture, pSrc, FALSE, TRUE))
 	return FALSE;
 
@@ -1404,10 +1384,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
     uint32_t mask_color, mask_alpha;
     int pixel_shift;
     int ret;
-    int retry_count = 0;
     struct radeon_exa_pixmap_priv *driver_priv;
-    struct radeon_cs_space_check bos[3];
-    int i;
     ACCEL_PREAMBLE();
     TRACE;
 
@@ -1436,29 +1413,19 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
 
     /* have to execute switch before doing buffer sizing check as it flushes */
     RADEON_SWITCH_TO_3D();
- retry:
+
     if (info->cs) {
-      
-	i = 0;
-	driver_priv = exaGetPixmapDriverPrivate(pSrc);
-	radeon_add_pixmap(bos, i++, pSrc, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
+      	radeon_cs_space_reset_bos(info->cs);
+	radeon_add_pixmap(info->cs, pSrc, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
 
 	if (pMask)
-	    radeon_add_pixmap(bos, i++, pMask, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
+	  radeon_add_pixmap(info->cs, pMask, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
 
-	radeon_add_pixmap(bos, i++, pDst, 0, RADEON_GEM_DOMAIN_VRAM);
+	radeon_add_pixmap(info->cs, pDst, 0, RADEON_GEM_DOMAIN_VRAM);
 
-	ret = radeon_cs_space_check(info->cs, bos, i);
-	if (ret == RADEON_CS_SPACE_OP_TO_BIG) {
+	ret = radeon_cs_space_check(info->cs);
+	if (ret)
 	    RADEON_FALLBACK(("Not enough RAM to hw accel composite operation\n"));
-	}
-	if (ret == RADEON_CS_SPACE_FLUSH) {
-            radeon_cs_flush_indirect(pScrn);
-	    retry_count++;
-	    if (retry_count == 2)
-	        RADEON_FALLBACK(("Not enough Video RAM - this really shouldn't happen\nm"));
-	    goto retry;
-	}
     }
 
     if (!RADEONSetupSourceTile(pSrcPicture, pSrc, TRUE, FALSE))
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index cd3ec9a6..7ecfe88c 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -70,6 +70,34 @@ const OptionInfoRec RADEONOptions_KMS[] = {
     { -1,                    NULL,               OPTV_NONE,    {0}, FALSE }
 };
 
+void radeon_cs_flush_indirect(ScrnInfoPtr pScrn)
+{
+    RADEONInfoPtr  info = RADEONPTR(pScrn);
+
+    if (!info->cs->cdw)
+	return;
+    radeon_cs_emit(info->cs);
+    radeon_cs_erase(info->cs);
+}
+
+void radeon_ddx_cs_start(ScrnInfoPtr pScrn,
+			 int n, const char *file,
+			 const char *func, int line)
+{
+    RADEONInfoPtr  info = RADEONPTR(pScrn);
+    int ret;
+
+    if (info->cs->cdw + n > info->cs->ndw) {
+	radeon_cs_flush_indirect(pScrn);
+	ret = radeon_cs_space_check(info->cs);
+	if (ret)
+	    ErrorF("space check failed in DDX CS start %s:%s:%d\n",
+		   file, func, line);
+    }
+    radeon_cs_begin(info->cs, n, file, func, line);
+}
+
+
 extern _X_EXPORT int gRADEONEntityIndex;
 
 static int getRADEONEntityIndex(void)
@@ -532,6 +560,7 @@ Bool RADEONScreenInit_KMS(int scrnIndex, ScreenPtr pScreen,
     }
 
     radeon_cs_set_limit(info->cs, RADEON_GEM_DOMAIN_GTT, info->gart_size);
+    radeon_cs_space_set_flush(info->cs, (void(*)(void *))radeon_cs_flush_indirect, pScrn); 
 
     radeon_setup_kernel_mem(pScreen);
     front_ptr = info->front_bo->ptr;
diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c
index 184258c9..10414b91 100644
--- a/src/radeon_textured_video.c
+++ b/src/radeon_textured_video.c
@@ -137,14 +137,6 @@ static REF_TRANSFORM trans[2] =
     {1.1643, 0.0, 1.7927, -0.2132, -0.5329, 2.1124, 0.0}  /* BT.709 */
 };
 
-static inline void radeon_add_bo(struct radeon_cs_space_check *bos, int index, struct radeon_bo *bo, int read_domains, int write_domain)
-{
-    bos[index].bo = bo;
-    bos[index].read_domains = read_domains;
-    bos[index].write_domain = write_domain;
-    bos[index].new_accounted = 0;
-}
-
 #define ACCEL_MMIO
 #define ACCEL_PREAMBLE()	unsigned char *RADEONMMIO = info->MMIO
 #define BEGIN_ACCEL(n)		RADEONWaitForFifo(pScrn, (n))
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index 2efe449a..b814921f 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -93,7 +93,6 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
     RADEONInfoPtr info = RADEONPTR(pScrn);
     PixmapPtr pPixmap = pPriv->pPixmap;
     struct radeon_exa_pixmap_priv *driver_priv;
-    struct radeon_cs_space_check bos[3];
     uint32_t txformat, txsize, txpitch, txoffset;
     uint32_t dst_pitch, dst_format;
     uint32_t colorpitch;
@@ -101,34 +100,24 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
     int dstxoff, dstyoff, pixel_shift, vtx_count;
     BoxPtr pBox = REGION_RECTS(&pPriv->clip);
     int nBox = REGION_NUM_RECTS(&pPriv->clip);
-    int i, ret, retry_count = 0;
+    int ret;
     ACCEL_PREAMBLE();
 
- retry:
     if (info->cs) {
-	i = 0;
-	radeon_add_bo(bos, i++, pPriv->src_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
+	radeon_cs_space_reset_bos(info->cs);
+        radeon_cs_space_add_persistent_bo(info->cs, pPriv->src_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
 
 	if (pPriv->bicubic_enabled)
-	    radeon_add_bo(bos, i++, pPriv->bicubic_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
+	    radeon_cs_space_add_persistent_bo(info->cs, pPriv->bicubic_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
 
 	driver_priv = exaGetPixmapDriverPrivate(pPixmap);
-	radeon_add_bo(bos, i++, driver_priv->bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
+	radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM);
 
-	ret = radeon_cs_space_check(info->cs, bos, i);
-	if (ret == RADEON_CS_SPACE_OP_TO_BIG) {
+	ret = radeon_cs_space_check(info->cs);
+	if (ret) {
 	    ErrorF("Not enough RAM to hw accel xv operation\n");
 	    return;
 	}
-	if (ret == RADEON_CS_SPACE_FLUSH) {
-	    radeon_cs_flush_indirect(pScrn);
-	    retry_count++;
-	    if (retry_count == 2) {
-	        ErrorF("Not enough RAM to hw accel xv operation\n");
-	        return;
-	    }
-	    goto retry;
-	}
     }
 
     pixel_shift = pPixmap->drawable.bitsPerPixel >> 4;
@@ -497,35 +486,24 @@ FUNC_NAME(R200DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
     int ref = pPriv->transform_index;
     float ucscale = 0.25, vcscale = 0.25;
     Bool needux8 = FALSE, needvx8 = FALSE;
-    struct radeon_cs_space_check bos[3];
-    int i, ret, retry_count = 0;
+    int ret;
     ACCEL_PREAMBLE();
 
- retry:
     if (info->cs) {
-	i = 0;
-	radeon_add_bo(bos, i++, pPriv->src_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
+	radeon_cs_space_reset_bos(info->cs);
+        radeon_cs_space_add_persistent_bo(info->cs, pPriv->src_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
 
 	if (pPriv->bicubic_enabled)
-	    radeon_add_bo(bos, i++, pPriv->bicubic_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
+	    radeon_cs_space_add_persistent_bo(info->cs, pPriv->bicubic_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
 
 	driver_priv = exaGetPixmapDriverPrivate(pPixmap);
-	radeon_add_bo(bos, i++, driver_priv->bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
+	radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM);
 
-	ret = radeon_cs_space_check(info->cs, bos, i);
-	if (ret == RADEON_CS_SPACE_OP_TO_BIG) {
+	ret = radeon_cs_space_check(info->cs);
+	if (ret) {
 	    ErrorF("Not enough RAM to hw accel xv operation\n");
 	    return;
 	}
-	if (ret == RADEON_CS_SPACE_FLUSH) {
-	    radeon_cs_flush_indirect(pScrn);
-	    retry_count++;
-	    if (retry_count == 2) {
-	        ErrorF("Not enough RAM to hw accel xv operation\n");
-	        return;
-	    }
-	    goto retry;
-	}
     }
 
     pixel_shift = pPixmap->drawable.bitsPerPixel >> 4;
@@ -1047,35 +1025,24 @@ FUNC_NAME(R300DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
     int dstxoff, dstyoff, pixel_shift, vtx_count;
     BoxPtr pBox = REGION_RECTS(&pPriv->clip);
     int nBox = REGION_NUM_RECTS(&pPriv->clip);
-    struct radeon_cs_space_check bos[3];
-    int i, ret, retry_count = 0;
+    int ret;
     ACCEL_PREAMBLE();
 
- retry:
     if (info->cs) {
-	i = 0;
-	radeon_add_bo(bos, i++, pPriv->src_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
+	radeon_cs_space_reset_bos(info->cs);
+	radeon_cs_space_add_persistent_bo(info->cs, pPriv->src_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
 
 	if (pPriv->bicubic_enabled)
-	    radeon_add_bo(bos, i++, pPriv->bicubic_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
+	  radeon_cs_space_add_persistent_bo(info->cs, pPriv->bicubic_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
 
 	driver_priv = exaGetPixmapDriverPrivate(pPixmap);
-	radeon_add_bo(bos, i++, driver_priv->bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
+	radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM);
 
-	ret = radeon_cs_space_check(info->cs, bos, i);
-	if (ret == RADEON_CS_SPACE_OP_TO_BIG) {
+	ret = radeon_cs_space_check(info->cs);
+	if (ret) {
 	    ErrorF("Not enough RAM to hw accel xv operation\n");
 	    return;
 	}
-	if (ret == RADEON_CS_SPACE_FLUSH) {
-	    radeon_cs_flush_indirect(pScrn);
-	    retry_count++;
-	    if (retry_count == 2) {
-	        ErrorF("Not enough RAM to hw accel xv operation\n");
-	        return;
-	    }
-	    goto retry;
-	}
     }
 
     pixel_shift = pPixmap->drawable.bitsPerPixel >> 4;
@@ -2500,41 +2467,30 @@ FUNC_NAME(R500DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
     struct radeon_exa_pixmap_priv *driver_priv;
     uint32_t txfilter, txformat0, txformat1, txoffset, txpitch;
     uint32_t dst_pitch, dst_format;
-    uint32_t txenable, colorpitch;
+    uint32_t txenable, colorpitch, bicubic_offset;
     uint32_t output_fmt;
     Bool isplanar = FALSE;
     int dstxoff, dstyoff, pixel_shift, vtx_count;
     BoxPtr pBox = REGION_RECTS(&pPriv->clip);
     int nBox = REGION_NUM_RECTS(&pPriv->clip);
-    struct radeon_cs_space_check bos[3];
-    int i, ret, retry_count = 0;
+    int ret;
     ACCEL_PREAMBLE();
 
- retry:
     if (info->cs) {
-	i = 0;
-	radeon_add_bo(bos, i++, pPriv->src_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
+	radeon_cs_space_reset_bos(info->cs);
+	radeon_cs_space_add_persistent_bo(info->cs, pPriv->src_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
 
 	if (pPriv->bicubic_enabled)
-	    radeon_add_bo(bos, i++, pPriv->bicubic_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
+	    radeon_cs_space_add_persistent_bo(info->cs, pPriv->bicubic_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
 
 	driver_priv = exaGetPixmapDriverPrivate(pPixmap);
-	radeon_add_bo(bos, i++, driver_priv->bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
+	radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM);
 
-	ret = radeon_cs_space_check(info->cs, bos, i);
-	if (ret == RADEON_CS_SPACE_OP_TO_BIG) {
+	ret = radeon_cs_space_check(info->cs);
+	if (ret) {
 	    ErrorF("Not enough RAM to hw accel xv operation\n");
 	    return;
 	}
-	if (ret == RADEON_CS_SPACE_FLUSH) {
-	    radeon_cs_flush_indirect(pScrn);
-	    retry_count++;
-	    if (retry_count == 2) {
-	        ErrorF("Not enough RAM to hw accel xv operation\n");
-	        return;
-	    }
-	    goto retry;
-	}
     }
 
     pixel_shift = pPixmap->drawable.bitsPerPixel >> 4;
@@ -2702,13 +2658,18 @@ FUNC_NAME(R500DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
 		    R300_TX_MAG_FILTER_NEAREST |
 		    (1 << R300_TX_ID_SHIFT));
 
+	if (info->cs)
+	    bicubic_offset = 0;
+	else
+	    bicubic_offset = pPriv->bicubic_src_offset;
+
 	BEGIN_ACCEL(6);
 	OUT_ACCEL_REG(R300_TX_FILTER0_1, txfilter);
 	OUT_ACCEL_REG(R300_TX_FILTER1_1, 0);
 	OUT_ACCEL_REG(R300_TX_FORMAT0_1, txformat0);
 	OUT_ACCEL_REG(R300_TX_FORMAT1_1, txformat1);
 	OUT_ACCEL_REG(R300_TX_FORMAT2_1, txpitch);
-	OUT_ACCEL_REG(R300_TX_OFFSET_1, pPriv->bicubic_src_offset);
+	OUT_TEXTURE_REG(R300_TX_OFFSET_1, bicubic_offset, pPriv->bicubic_bo);
 	FINISH_ACCEL();
 
 	/* Enable tex 1 */