summaryrefslogtreecommitdiff
path: root/src/evergreen_accel.c
diff options
context:
space:
mode:
authorAlex Deucher <alexdeucher@gmail.com>2011-02-16 15:07:35 -0500
committerAlex Deucher <alexdeucher@gmail.com>2011-02-16 15:19:16 -0500
commit0471d8412acd82e281a35fc4c6bb2d53b1ff5802 (patch)
tree378467b004b772b08309240642cece37bd14305f /src/evergreen_accel.c
parent4d7e1498f7d9eb50e2eddabca193fc27bde24f0e (diff)
kms: EXA/Xv tiling fixes
- properly set tiling flags for temp surfaces - fix CB non_disp_tiling bits on evergreen Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Diffstat (limited to 'src/evergreen_accel.c')
-rw-r--r--src/evergreen_accel.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/evergreen_accel.c b/src/evergreen_accel.c
index d41ce722..12626c32 100644
--- a/src/evergreen_accel.c
+++ b/src/evergreen_accel.c
@@ -148,7 +148,7 @@ evergreen_sq_setup(ScrnInfoPtr pScrn, sq_config_t *sq_conf)
void
evergreen_set_render_target(ScrnInfoPtr pScrn, cb_config_t *cb_conf, uint32_t domain)
{
- uint32_t cb_color_info, cb_color_attrib, cb_color_dim;
+ uint32_t cb_color_info, cb_color_attrib = 0, cb_color_dim;
int pitch, slice, h;
RADEONInfoPtr info = RADEONPTR(pScrn);
@@ -177,7 +177,8 @@ evergreen_set_render_target(ScrnInfoPtr pScrn, cb_config_t *cb_conf, uint32_t do
cb_color_info |= RAT_bit;
/* bit 4 needs to be set for linear and depth/stencil surfaces */
- cb_color_attrib = CB_COLOR0_ATTRIB__NON_DISP_TILING_ORDER_bit;
+ if (cb_conf->non_disp_tiling)
+ cb_color_attrib |= CB_COLOR0_ATTRIB__NON_DISP_TILING_ORDER_bit;
pitch = (cb_conf->w / 8) - 1;
h = RADEON_ALIGN(cb_conf->h, 8);