diff options
| author | Alex Deucher <alexdeucher@gmail.com> | 2011-02-11 17:21:10 -0500 |
|---|---|---|
| committer | Alex Deucher <alexdeucher@gmail.com> | 2011-02-11 17:21:10 -0500 |
| commit | f1dc419c989addc4737aed06ec8b8acdb4d40063 (patch) | |
| tree | 6e327ff35e25afb224eab1754a9711d8a436a07a /src/evergreen_shader.c | |
| parent | e8dc728a549323f1babe337b9d42ad504af1ca39 (diff) | |
kms: evergreen/ni big endian accel support
Based on 6xx/7xx patches from Cédric Cano.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Diffstat (limited to 'src/evergreen_shader.c')
| -rw-r--r-- | src/evergreen_shader.c | 60 |
1 files changed, 50 insertions, 10 deletions
diff --git a/src/evergreen_shader.c b/src/evergreen_shader.c index ef56d2d4..bbdd7a76 100644 --- a/src/evergreen_shader.c +++ b/src/evergreen_shader.c @@ -110,7 +110,11 @@ int evergreen_solid_vs(RADEONChipFamily ChipSet, uint32_t* shader) FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); shader[i++] = VTX_DWORD2(OFFSET(0), - ENDIAN_SWAP(ENDIAN_NONE), +#if X_BYTE_ORDER == X_BIG_ENDIAN + ENDIAN_SWAP(SQ_ENDIAN_8IN32), +#else + ENDIAN_SWAP(SQ_ENDIAN_NONE), +#endif CONST_BUF_NO_STRIDE(0), MEGA_FETCH(1), ALT_CONST(0), @@ -331,7 +335,11 @@ int evergreen_copy_vs(RADEONChipFamily ChipSet, uint32_t* shader) FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); shader[i++] = VTX_DWORD2(OFFSET(0), - ENDIAN_SWAP(ENDIAN_NONE), +#if X_BYTE_ORDER == X_BIG_ENDIAN + ENDIAN_SWAP(SQ_ENDIAN_8IN32), +#else + ENDIAN_SWAP(SQ_ENDIAN_NONE), +#endif CONST_BUF_NO_STRIDE(0), MEGA_FETCH(1), ALT_CONST(0), @@ -358,7 +366,11 @@ int evergreen_copy_vs(RADEONChipFamily ChipSet, uint32_t* shader) FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); shader[i++] = VTX_DWORD2(OFFSET(8), - ENDIAN_SWAP(ENDIAN_NONE), +#if X_BYTE_ORDER == X_BIG_ENDIAN + ENDIAN_SWAP(SQ_ENDIAN_8IN32), +#else + ENDIAN_SWAP(SQ_ENDIAN_NONE), +#endif CONST_BUF_NO_STRIDE(0), MEGA_FETCH(0), ALT_CONST(0), @@ -689,7 +701,11 @@ int evergreen_xv_vs(RADEONChipFamily ChipSet, uint32_t* shader) FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); shader[i++] = VTX_DWORD2(OFFSET(0), - ENDIAN_SWAP(ENDIAN_NONE), +#if X_BYTE_ORDER == X_BIG_ENDIAN + ENDIAN_SWAP(SQ_ENDIAN_8IN32), +#else + ENDIAN_SWAP(SQ_ENDIAN_NONE), +#endif CONST_BUF_NO_STRIDE(0), MEGA_FETCH(1), ALT_CONST(0), @@ -716,7 +732,11 @@ int evergreen_xv_vs(RADEONChipFamily ChipSet, uint32_t* shader) FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); shader[i++] = VTX_DWORD2(OFFSET(8), - ENDIAN_SWAP(ENDIAN_NONE), +#if X_BYTE_ORDER == X_BIG_ENDIAN + ENDIAN_SWAP(SQ_ENDIAN_8IN32), +#else + ENDIAN_SWAP(SQ_ENDIAN_NONE), +#endif CONST_BUF_NO_STRIDE(0), MEGA_FETCH(0), ALT_CONST(0), @@ -2344,7 +2364,11 @@ int evergreen_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader) FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); shader[i++] = VTX_DWORD2(OFFSET(0), - ENDIAN_SWAP(ENDIAN_NONE), +#if X_BYTE_ORDER == X_BIG_ENDIAN + ENDIAN_SWAP(SQ_ENDIAN_8IN32), +#else + ENDIAN_SWAP(SQ_ENDIAN_NONE), +#endif CONST_BUF_NO_STRIDE(0), MEGA_FETCH(1), ALT_CONST(0), @@ -2371,7 +2395,11 @@ int evergreen_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader) FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); shader[i++] = VTX_DWORD2(OFFSET(8), - ENDIAN_SWAP(ENDIAN_NONE), +#if X_BYTE_ORDER == X_BIG_ENDIAN + ENDIAN_SWAP(SQ_ENDIAN_8IN32), +#else + ENDIAN_SWAP(SQ_ENDIAN_NONE), +#endif CONST_BUF_NO_STRIDE(0), MEGA_FETCH(0), ALT_CONST(0), @@ -2398,7 +2426,11 @@ int evergreen_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader) FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); shader[i++] = VTX_DWORD2(OFFSET(16), - ENDIAN_SWAP(ENDIAN_NONE), +#if X_BYTE_ORDER == X_BIG_ENDIAN + ENDIAN_SWAP(SQ_ENDIAN_8IN32), +#else + ENDIAN_SWAP(SQ_ENDIAN_NONE), +#endif CONST_BUF_NO_STRIDE(0), MEGA_FETCH(0), ALT_CONST(0), @@ -2426,7 +2458,11 @@ int evergreen_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader) FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); shader[i++] = VTX_DWORD2(OFFSET(0), - ENDIAN_SWAP(ENDIAN_NONE), +#if X_BYTE_ORDER == X_BIG_ENDIAN + ENDIAN_SWAP(SQ_ENDIAN_8IN32), +#else + ENDIAN_SWAP(SQ_ENDIAN_NONE), +#endif CONST_BUF_NO_STRIDE(0), MEGA_FETCH(1), ALT_CONST(0), @@ -2453,7 +2489,11 @@ int evergreen_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader) FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED), SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE)); shader[i++] = VTX_DWORD2(OFFSET(8), - ENDIAN_SWAP(ENDIAN_NONE), +#if X_BYTE_ORDER == X_BIG_ENDIAN + ENDIAN_SWAP(SQ_ENDIAN_8IN32), +#else + ENDIAN_SWAP(SQ_ENDIAN_NONE), +#endif CONST_BUF_NO_STRIDE(0), MEGA_FETCH(0), ALT_CONST(0), |