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authorAlex Deucher <alexdeucher@gmail.com>2008-08-14 14:49:45 -0400
committerAlex Deucher <alexdeucher@gmail.com>2008-08-14 14:49:45 -0400
commit92ee21df344a989778e37369c7beb3904a00ead6 (patch)
tree614c1163751f139fbb4e881889550dbffce8d0ca /src/radeon_crtc.c
parent0d5e0347af4322713075193154b8a348de4a0b52 (diff)
PLL adjustments
Seems higher dotclocks prefer a higher FB div. Someone with a lot of should try and find out where the div sweet spots are for various dotclock ranges. fixes bug 17125
Diffstat (limited to 'src/radeon_crtc.c')
-rw-r--r--src/radeon_crtc.c7
1 files changed, 6 insertions, 1 deletions
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index 13166698..5ab00c1f 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -228,7 +228,12 @@ RADEONComputePLL(RADEONPLLPtr pll,
best_freq = current_freq;
best_error = error;
best_vco_diff = vco_diff;
- } else if ((flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) {
+ } else if (((flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
+ ((flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
+ ((flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
+ ((flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
+ ((flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
+ ((flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
best_post_div = post_div;
best_ref_div = ref_div;
best_feedback_div = feedback_div;