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authorIlija Hadzic <ihadzic@research.bell-labs.com>2012-12-19 10:35:43 -0500
committerMichel Dänzer <michel.daenzer@amd.com>2013-01-03 10:59:37 +0100
commit6981a5c087165b126c15ba0025cffdba218ab652 (patch)
tree09abdf221318025fdd9b93c0e04f2d1ec3a038c4 /src/radeon_video.h
parent3657672207322be651cdb94a811337b7c5668c84 (diff)
DRI2: limit the swap rate when CRTC is in DPMS-off state
If drawable is displayed on a CRTC and relevant CRTC is in DPMS off state, defer the swap by a fixed (hard-coded) time. This patch fixes a bug that caused an application to render at uncontrolled rate when CRTC goes into DPMS "off" state, thus thrashing the GPU and CPU and likely offsetting the power savings achieved by shutting off the display. Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Diffstat (limited to 'src/radeon_video.h')
-rw-r--r--src/radeon_video.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/radeon_video.h b/src/radeon_video.h
index f097f2f8..e6068e86 100644
--- a/src/radeon_video.h
+++ b/src/radeon_video.h
@@ -100,4 +100,6 @@ RADEONCopyMungedData(ScrnInfoPtr pScrn,
unsigned int srcPitch, unsigned int srcPitch2,
unsigned int dstPitch, unsigned int h, unsigned int w);
+Bool radeon_crtc_is_enabled(xf86CrtcPtr crtc);
+
#endif