radeon: more unused stuff

Remove all CurrentLayout stuff.

Signed-off-by: Dave Airlie <airlied@redhat.com>

5 files changed, 12 insertions, 61 deletions

diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index 0cd461df..481eb2f9 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -274,8 +274,8 @@ void drmmode_copy_fb(ScrnInfoPtr pScrn, drmmode_ptr drmmode)
 	}
 
 	pitch = RADEON_ALIGN(pScrn->displayWidth,
-			     drmmode_get_pitch_align(pScrn, info->CurrentLayout.pixel_bytes, tiling_flags)) *
-		info->CurrentLayout.pixel_bytes;
+			     drmmode_get_pitch_align(pScrn, info->pixel_bytes, tiling_flags)) *
+		info->pixel_bytes;
 
 	dst = drmmode_create_bo_pixmap(pScrn, pScrn->virtualX,
 				       pScrn->virtualY, pScrn->depth,
@@ -339,8 +339,8 @@ drmmode_set_mode_major(xf86CrtcPtr crtc, DisplayModePtr mode,
 			tiling_flags |= RADEON_TILING_MACRO;
 	}
 
-	pitch = RADEON_ALIGN(pScrn->displayWidth, drmmode_get_pitch_align(pScrn, info->CurrentLayout.pixel_bytes, tiling_flags)) *
-		info->CurrentLayout.pixel_bytes;
+	pitch = RADEON_ALIGN(pScrn->displayWidth, drmmode_get_pitch_align(pScrn, info->pixel_bytes, tiling_flags)) *
+		info->pixel_bytes;
 	height = RADEON_ALIGN(pScrn->virtualY, drmmode_get_height_align(pScrn, tiling_flags));
 	if (info->ChipFamily >= CHIP_FAMILY_R600) {
 		pitch = info->front_surface.level[0].pitch_bytes;
@@ -1257,7 +1257,7 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int height)
 	uint32_t    old_fb_id;
 	int	    i, pitch, old_width, old_height, old_pitch;
 	int screen_size;
-	int cpp = info->CurrentLayout.pixel_bytes;
+	int cpp = info->pixel_bytes;
 	struct radeon_bo *front_bo;
 	struct radeon_surface surface;
 	struct radeon_surface *psurface;
@@ -1785,8 +1785,8 @@ Bool radeon_do_pageflip(ScrnInfoPtr scrn, struct radeon_bo *new_front, void *dat
 			tiling_flags |= RADEON_TILING_MACRO;
 	}
 
-	pitch = RADEON_ALIGN(scrn->displayWidth, drmmode_get_pitch_align(scrn, info->CurrentLayout.pixel_bytes, tiling_flags)) *
-		info->CurrentLayout.pixel_bytes;
+	pitch = RADEON_ALIGN(scrn->displayWidth, drmmode_get_pitch_align(scrn, info->pixel_bytes, tiling_flags)) *
+		info->pixel_bytes;
 	height = RADEON_ALIGN(scrn->virtualY, drmmode_get_height_align(scrn, tiling_flags));
 	if (info->ChipFamily >= CHIP_FAMILY_R600 && info->surf_man) {
 		pitch = info->front_surface.level[0].pitch_bytes;
diff --git a/src/radeon.h b/src/radeon.h
index b7d67de6..fca4078a 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -179,16 +179,6 @@ typedef enum {
 #define RADEON_ALIGN(x,bytes) (((x) + ((bytes) - 1)) & ~((bytes) - 1))
 #define RADEONPTR(pScrn)      ((RADEONInfoPtr)(pScrn)->driverPrivate)
 
-typedef struct {
-    int               bitsPerPixel;
-    int               depth;
-    int               displayWidth;
-    int               displayHeight;
-    int               pixel_code;
-    int               pixel_bytes;
-    DisplayModePtr    mode;
-} RADEONFBLayout;
-
 #define IS_RV100_VARIANT ((info->ChipFamily == CHIP_FAMILY_RV100)  ||  \
         (info->ChipFamily == CHIP_FAMILY_RV200)  ||  \
         (info->ChipFamily == CHIP_FAMILY_RS100)  ||  \
@@ -309,10 +299,6 @@ struct radeon_vbo_object {
 };
 
 struct radeon_accel_state {
-    /* common accel data */
-				/* Computed values for Radeon */
-    uint32_t          dp_gui_master_cntl;
-    uint32_t          dp_gui_master_cntl_clip;
 
 				/* Saved values for ScreenToScreenCopy */
     int               xdir;
@@ -425,8 +411,6 @@ typedef struct {
     int               Chipset;
     RADEONChipFamily  ChipFamily;
 
-    Bool              IsIGP;            /* IGP chips */
-
     Bool              (*CloseScreen)(CLOSE_SCREEN_ARGS_DECL);
 
     void              (*BlockHandler)(BLOCKHANDLER_ARGS_DECL);
@@ -434,7 +418,7 @@ typedef struct {
     int               pix24bpp;         /* Depth of pixmap for 24bpp fb      */
     Bool              dac6bits;         /* Use 6 bit DAC?                    */
 
-    RADEONFBLayout    CurrentLayout;
+    int               pixel_bytes;
 
     Bool              directRenderingEnabled;
     struct radeon_dri2  dri2;
diff --git a/src/radeon_accel.c b/src/radeon_accel.c
index 32f3095b..15cf2bd8 100644
--- a/src/radeon_accel.c
+++ b/src/radeon_accel.c
@@ -104,14 +104,8 @@ static int RADEONDRMGetNumPipes(ScrnInfoPtr pScrn, int *num_pipes)
 void RADEONEngineInit(ScrnInfoPtr pScrn)
 {
     RADEONInfoPtr  info       = RADEONPTR(pScrn);
-    int datatype = 0;
     info->accel_state->num_gb_pipes = 0;
 
-    xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
-		   "EngineInit (%d/%d)\n",
-		   info->CurrentLayout.pixel_code,
-		   info->CurrentLayout.bitsPerPixel);
-
     if (info->directRenderingEnabled && (IS_R300_3D || IS_R500_3D)) {
 	int num_pipes;
 
@@ -124,26 +118,6 @@ void RADEONEngineInit(ScrnInfoPtr pScrn)
 	    info->accel_state->num_gb_pipes = num_pipes;
 	}
     }
-
-    switch (info->CurrentLayout.pixel_code) {
-    case 8:  datatype = 2; break;
-    case 15: datatype = 3; break;
-    case 16: datatype = 4; break;
-    case 24: datatype = 5; break;
-    case 32: datatype = 6; break;
-    default:
-	xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
-		       "Unknown depth/bpp = %d/%d (code = %d)\n",
-		       info->CurrentLayout.depth,
-		       info->CurrentLayout.bitsPerPixel,
-		       info->CurrentLayout.pixel_code);
-    }
-
-    info->accel_state->dp_gui_master_cntl =
-	((datatype << RADEON_GMC_DST_DATATYPE_SHIFT)
-	 | RADEON_GMC_CLR_CMP_CNTL_DIS
-	 | RADEON_GMC_DST_PITCH_OFFSET_CNTL);
-
 }
 
 int radeon_cs_space_remaining(ScrnInfoPtr pScrn)
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 28c1040e..3e39b4b5 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -172,12 +172,7 @@ Bool RADEONPreInitVisual(ScrnInfoPtr pScrn)
 
     info->pix24bpp                   = xf86GetBppFromDepth(pScrn,
 							   pScrn->depth);
-    info->CurrentLayout.bitsPerPixel = pScrn->bitsPerPixel;
-    info->CurrentLayout.depth        = pScrn->depth;
-    info->CurrentLayout.pixel_bytes  = pScrn->bitsPerPixel / 8;
-    info->CurrentLayout.pixel_code   = (pScrn->bitsPerPixel != 16
-				       ? pScrn->bitsPerPixel
-				       : pScrn->depth);
+    info->pixel_bytes  = pScrn->bitsPerPixel / 8;
 
     if (info->pix24bpp == 24) {
 	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
@@ -188,8 +183,8 @@ Bool RADEONPreInitVisual(ScrnInfoPtr pScrn)
     xf86DrvMsg(pScrn->scrnIndex, X_INFO,
 	       "Pixel depth = %d bits stored in %d byte%s (%d bpp pixmaps)\n",
 	       pScrn->depth,
-	       info->CurrentLayout.pixel_bytes,
-	       info->CurrentLayout.pixel_bytes > 1 ? "s" : "",
+	       info->pixel_bytes,
+	       info->pixel_bytes > 1 ? "s" : "",
 	       info->pix24bpp);
 
     if (!xf86SetDefaultVisual(pScrn, -1)) return FALSE;
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index 274f7ddf..7180c600 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -358,7 +358,6 @@ static Bool RADEONPreInitChipType_KMS(ScrnInfoPtr pScrn)
 	if (info->Chipset == RADEONCards[i].pci_device_id) {
 	    RADEONCardInfo *card = &RADEONCards[i];
 	    info->ChipFamily = card->chip_family;
-	    info->IsIGP = card->igp;
 	    break;
 	}
     }
@@ -743,7 +742,6 @@ Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int flags)
     cpp = pScrn->bitsPerPixel / 8;
     pScrn->displayWidth =
 	RADEON_ALIGN(pScrn->virtualX, drmmode_get_pitch_align(pScrn, cpp, tiling));
-    info->CurrentLayout.displayWidth = pScrn->displayWidth;
 
     /* Set display resolution */
     xf86SetDpi(pScrn, 0, 0);
@@ -1196,7 +1194,7 @@ static Bool radeon_setup_kernel_mem(ScreenPtr pScreen)
     ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen);
     RADEONInfoPtr info = RADEONPTR(pScrn);
     xf86CrtcConfigPtr   xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
-    int cpp = info->CurrentLayout.pixel_bytes;
+    int cpp = info->pixel_bytes;
     int screen_size;
     int pitch, base_align;
     int total_size_bytes = 0;