diff options
| -rw-r--r-- | src/evergreen_accel.c | 6 | ||||
| -rw-r--r-- | src/evergreen_exa.c | 4 | ||||
| -rw-r--r-- | src/evergreen_textured_videofuncs.c | 4 | ||||
| -rw-r--r-- | src/r6xx_accel.c | 6 | ||||
| -rw-r--r-- | src/radeon.h | 1 |
5 files changed, 10 insertions, 11 deletions
diff --git a/src/evergreen_accel.c b/src/evergreen_accel.c index 7ea3c8cb..10f2e511 100644 --- a/src/evergreen_accel.c +++ b/src/evergreen_accel.c @@ -645,12 +645,12 @@ evergreen_set_vtx_resource(ScrnInfoPtr pScrn, vtx_resource_t *res, uint32_t doma (info->ChipFamily == CHIP_FAMILY_CAYMAN) || (info->ChipFamily == CHIP_FAMILY_ARUBA)) evergreen_cp_set_surface_sync(pScrn, TC_ACTION_ENA_bit, - accel_state->vbo.vb_offset, accel_state->vbo.vb_mc_addr, + accel_state->vbo.vb_offset, 0, res->bo, domain, 0); else evergreen_cp_set_surface_sync(pScrn, VC_ACTION_ENA_bit, - accel_state->vbo.vb_offset, accel_state->vbo.vb_mc_addr, + accel_state->vbo.vb_offset, 0, res->bo, domain, 0); @@ -1450,7 +1450,7 @@ void evergreen_finish_op(ScrnInfoPtr pScrn, int vtx_size) vtx_res.id = SQ_FETCH_RESOURCE_vs; vtx_res.vtx_size_dw = vtx_size / 4; vtx_res.vtx_num_entries = accel_state->vbo.vb_size / 4; - vtx_res.vb_addr = accel_state->vbo.vb_mc_addr + accel_state->vbo.vb_start_op; + vtx_res.vb_addr = accel_state->vbo.vb_start_op; vtx_res.bo = accel_state->vbo.vb_bo; vtx_res.dst_sel_x = SQ_SEL_X; vtx_res.dst_sel_y = SQ_SEL_Y; diff --git a/src/evergreen_exa.c b/src/evergreen_exa.c index 942d7feb..f906cbf2 100644 --- a/src/evergreen_exa.c +++ b/src/evergreen_exa.c @@ -169,7 +169,7 @@ EVERGREENPrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg) ps_const_conf.type = SHADER_TYPE_PS; ps_alu_consts = radeon_vbo_space(pScrn, &accel_state->cbuf, 256); ps_const_conf.bo = accel_state->cbuf.vb_bo; - ps_const_conf.const_addr = accel_state->cbuf.vb_mc_addr + accel_state->cbuf.vb_offset; + ps_const_conf.const_addr = accel_state->cbuf.vb_offset; ps_const_conf.cpu_ptr = (uint32_t *)(char *)ps_alu_consts; if (accel_state->dst_obj.bpp == 16) { r = (fg >> 11) & 0x1f; @@ -1340,7 +1340,7 @@ static Bool EVERGREENPrepareComposite(int op, PicturePtr pSrcPicture, vs_const_conf.type = SHADER_TYPE_VS; cbuf = radeon_vbo_space(pScrn, &accel_state->cbuf, 256); vs_const_conf.bo = accel_state->cbuf.vb_bo; - vs_const_conf.const_addr = accel_state->cbuf.vb_mc_addr + accel_state->cbuf.vb_offset; + vs_const_conf.const_addr = accel_state->cbuf.vb_offset; vs_const_conf.cpu_ptr = (uint32_t *)(char *)cbuf; EVERGREENXFormSetup(pSrcPicture, pSrc, 0, cbuf); diff --git a/src/evergreen_textured_videofuncs.c b/src/evergreen_textured_videofuncs.c index 1ae0ae2f..6daf30e6 100644 --- a/src/evergreen_textured_videofuncs.c +++ b/src/evergreen_textured_videofuncs.c @@ -422,7 +422,7 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) ps_const_conf.type = SHADER_TYPE_PS; ps_alu_consts = radeon_vbo_space(pScrn, &accel_state->cbuf, 256); ps_const_conf.bo = accel_state->cbuf.vb_bo; - ps_const_conf.const_addr = accel_state->cbuf.vb_mc_addr + accel_state->cbuf.vb_offset; + ps_const_conf.const_addr = accel_state->cbuf.vb_offset; ps_const_conf.cpu_ptr = (uint32_t *)(char *)ps_alu_consts; ps_alu_consts[0] = off[0]; @@ -448,7 +448,7 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) vs_const_conf.type = SHADER_TYPE_VS; vs_alu_consts = radeon_vbo_space(pScrn, &accel_state->cbuf, 256); vs_const_conf.bo = accel_state->cbuf.vb_bo; - vs_const_conf.const_addr = accel_state->cbuf.vb_mc_addr + accel_state->cbuf.vb_offset; + vs_const_conf.const_addr = accel_state->cbuf.vb_offset; vs_const_conf.cpu_ptr = (uint32_t *)(char *)vs_alu_consts; vs_alu_consts[0] = 1.0 / pPriv->w; diff --git a/src/r6xx_accel.c b/src/r6xx_accel.c index eb0241c7..6bbf6637 100644 --- a/src/r6xx_accel.c +++ b/src/r6xx_accel.c @@ -513,12 +513,12 @@ r600_set_vtx_resource(ScrnInfoPtr pScrn, vtx_resource_t *res, uint32_t domain) (info->ChipFamily == CHIP_FAMILY_RS880) || (info->ChipFamily == CHIP_FAMILY_RV710)) r600_cp_set_surface_sync(pScrn, TC_ACTION_ENA_bit, - accel_state->vbo.vb_offset, accel_state->vbo.vb_mc_addr, + accel_state->vbo.vb_offset, 0, res->bo, domain, 0); else r600_cp_set_surface_sync(pScrn, VC_ACTION_ENA_bit, - accel_state->vbo.vb_offset, accel_state->vbo.vb_mc_addr, + accel_state->vbo.vb_offset, 0, res->bo, domain, 0); @@ -1212,7 +1212,7 @@ void r600_finish_op(ScrnInfoPtr pScrn, int vtx_size) vtx_res.vtx_size_dw = vtx_size / 4; vtx_res.vtx_num_entries = accel_state->vbo.vb_size / 4; vtx_res.mem_req_size = 1; - vtx_res.vb_addr = accel_state->vbo.vb_mc_addr + accel_state->vbo.vb_start_op; + vtx_res.vb_addr = accel_state->vbo.vb_start_op; vtx_res.bo = accel_state->vbo.vb_bo; #if X_BYTE_ORDER == X_BIG_ENDIAN vtx_res.endian = SQ_ENDIAN_8IN32; diff --git a/src/radeon.h b/src/radeon.h index 9efe5d1c..7ed64054 100644 --- a/src/radeon.h +++ b/src/radeon.h @@ -306,7 +306,6 @@ struct r600_accel_object { struct radeon_vbo_object { int vb_offset; - uint64_t vb_mc_addr; int vb_total; uint32_t vb_size; uint32_t vb_op_vert_size; |