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-rw-r--r--src/legacy_crtc.c12
-rw-r--r--src/radeon.h260
-rw-r--r--src/radeon_accel.c148
-rw-r--r--src/radeon_commonfuncs.c2
-rw-r--r--src/radeon_crtc.c2
-rw-r--r--src/radeon_dri.c606
-rw-r--r--src/radeon_driver.c233
-rw-r--r--src/radeon_exa.c50
-rw-r--r--src/radeon_exa_funcs.c6
9 files changed, 663 insertions, 656 deletions
diff --git a/src/legacy_crtc.c b/src/legacy_crtc.c
index 8995679f..14e4259b 100644
--- a/src/legacy_crtc.c
+++ b/src/legacy_crtc.c
@@ -631,7 +631,7 @@ radeon_crtc_modeset_ioctl(xf86CrtcPtr crtc, Bool post)
modeset.crtc = radeon_crtc->crtc_id;
modeset.cmd = post ? _DRM_POST_MODESET : _DRM_PRE_MODESET;
- ioctl(info->drmFD, DRM_IOCTL_MODESET_CTL, &modeset);
+ ioctl(info->dri->drmFD, DRM_IOCTL_MODESET_CTL, &modeset);
#endif
}
@@ -761,7 +761,7 @@ RADEONInitCrtcBase(xf86CrtcPtr crtc, RADEONSavePtr save,
save->crtc_offset = pScrn->fbOffset;
#ifdef XF86DRI
- if (info->allowPageFlip)
+ if (info->dri && info->dri->allowPageFlip)
save->crtc_offset_cntl = RADEON_CRTC_OFFSET_FLIP_CNTL;
else
#endif
@@ -854,7 +854,7 @@ RADEONInitCrtcBase(xf86CrtcPtr crtc, RADEONSavePtr save,
pSAREA->frame.height = pScrn->frameY1 - y + 1;
if (pSAREAPriv->pfCurrentPage == 1) {
- Base += info->backOffset - info->frontOffset;
+ Base += info->dri->backOffset - info->dri->frontOffset;
}
}
#endif
@@ -981,7 +981,7 @@ RADEONInitCrtc2Base(xf86CrtcPtr crtc, RADEONSavePtr save,
*/
save->crtc2_offset = pScrn->fbOffset;
#ifdef XF86DRI
- if (info->allowPageFlip)
+ if (info->dri && info->dri->allowPageFlip)
save->crtc2_offset_cntl = RADEON_CRTC_OFFSET_FLIP_CNTL;
else
#endif
@@ -1068,7 +1068,7 @@ RADEONInitCrtc2Base(xf86CrtcPtr crtc, RADEONSavePtr save,
pSAREAPriv->crtc2_base = Base;
if (pSAREAPriv->pfCurrentPage == 1) {
- Base += info->backOffset - info->frontOffset;
+ Base += info->dri->backOffset - info->dri->frontOffset;
}
}
#endif
@@ -1460,7 +1460,7 @@ RADEONInitDispBandwidthLegacy(ScrnInfoPtr pScrn,
} else {
#ifdef XF86DRI
if (info->directRenderingEnabled)
- sclk_eff = info->sclk - (info->agpMode * 50.0 / 3.0);
+ sclk_eff = info->sclk - (info->dri->agpMode * 50.0 / 3.0);
else
#endif
sclk_eff = info->sclk;
diff --git a/src/radeon.h b/src/radeon.h
index 78733abf..06c76891 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -433,6 +433,118 @@ struct radeon_cp {
int dma_debug_lineno;
};
+
+struct radeon_dri {
+ Bool noBackBuffer;
+
+ Bool newMemoryMap;
+ drmVersionPtr pLibDRMVersion;
+ drmVersionPtr pKernelDRMVersion;
+ DRIInfoPtr pDRIInfo;
+ int drmFD;
+ int numVisualConfigs;
+ __GLXvisualConfig *pVisualConfigs;
+ RADEONConfigPrivPtr pVisualConfigsPriv;
+ Bool (*DRICloseScreen)(int, ScreenPtr);
+
+ drm_handle_t fbHandle;
+
+ drmSize registerSize;
+ drm_handle_t registerHandle;
+
+ drmSize pciSize;
+ drm_handle_t pciMemHandle;
+ unsigned char *PCI; /* Map */
+
+ Bool depthMoves; /* Enable depth moves -- slow! */
+ Bool allowPageFlip; /* Enable 3d page flipping */
+#ifdef DAMAGE
+ DamagePtr pDamage;
+ RegionRec driRegion;
+#endif
+ Bool have3DWindows; /* Are there any 3d clients? */
+
+ int pciAperSize;
+ drmSize gartSize;
+ drm_handle_t agpMemHandle; /* Handle from drmAgpAlloc */
+ unsigned long gartOffset;
+ unsigned char *AGP; /* Map */
+ int agpMode;
+
+ uint32_t pciCommand;
+
+ /* CP ring buffer data */
+ unsigned long ringStart; /* Offset into GART space */
+ drm_handle_t ringHandle; /* Handle from drmAddMap */
+ drmSize ringMapSize; /* Size of map */
+ int ringSize; /* Size of ring (in MB) */
+ drmAddress ring; /* Map */
+ int ringSizeLog2QW;
+
+ unsigned long ringReadOffset; /* Offset into GART space */
+ drm_handle_t ringReadPtrHandle; /* Handle from drmAddMap */
+ drmSize ringReadMapSize; /* Size of map */
+ drmAddress ringReadPtr; /* Map */
+
+ /* CP vertex/indirect buffer data */
+ unsigned long bufStart; /* Offset into GART space */
+ drm_handle_t bufHandle; /* Handle from drmAddMap */
+ drmSize bufMapSize; /* Size of map */
+ int bufSize; /* Size of buffers (in MB) */
+ drmAddress buf; /* Map */
+ int bufNumBufs; /* Number of buffers */
+ drmBufMapPtr buffers; /* Buffer map */
+
+ /* CP GART Texture data */
+ unsigned long gartTexStart; /* Offset into GART space */
+ drm_handle_t gartTexHandle; /* Handle from drmAddMap */
+ drmSize gartTexMapSize; /* Size of map */
+ int gartTexSize; /* Size of GART tex space (in MB) */
+ drmAddress gartTex; /* Map */
+ int log2GARTTexGran;
+
+ /* DRI screen private data */
+ int fbX;
+ int fbY;
+ int backX;
+ int backY;
+ int depthX;
+ int depthY;
+
+ int frontOffset;
+ int frontPitch;
+ int backOffset;
+ int backPitch;
+ int depthOffset;
+ int depthPitch;
+ int depthBits;
+ int textureOffset;
+ int textureSize;
+ int log2TexGran;
+
+ int pciGartSize;
+ uint32_t pciGartOffset;
+ void *pciGartBackup;
+
+ int irq;
+
+#ifdef PER_CONTEXT_SAREA
+ int perctx_sarea_size;
+#endif
+
+#ifdef USE_XAA
+ uint32_t frontPitchOffset;
+ uint32_t backPitchOffset;
+ uint32_t depthPitchOffset;
+
+ /* offscreen memory management */
+ int backLines;
+ FBAreaPtr backArea;
+ int depthTexLines;
+ FBAreaPtr depthTexArea;
+#endif
+
+};
#endif
struct radeon_accel_state {
@@ -578,17 +690,7 @@ typedef struct {
Bool PaletteSavedOnVT; /* Palette saved on last VT switch */
- struct radeon_accel_state *accel_state;
-
-#ifdef USE_EXA
-#ifdef XF86DRI
- Bool accelDFS;
-#endif
-#endif
- Bool accelOn;
xf86CursorInfoPtr cursor;
- Bool allowColorTiling;
- Bool tilingEnabled; /* mirror of sarea->tiling_enabled */
#ifdef ARGB_CURSOR
Bool cursor_argb;
#endif
@@ -607,121 +709,30 @@ typedef struct {
RADEONFBLayout CurrentLayout;
#ifdef XF86DRI
- Bool noBackBuffer;
Bool directRenderingEnabled;
Bool directRenderingInited;
- Bool newMemoryMap;
- drmVersionPtr pLibDRMVersion;
- drmVersionPtr pKernelDRMVersion;
- DRIInfoPtr pDRIInfo;
- int drmFD;
- int numVisualConfigs;
- __GLXvisualConfig *pVisualConfigs;
- RADEONConfigPrivPtr pVisualConfigsPriv;
- Bool (*DRICloseScreen)(int, ScreenPtr);
-
- drm_handle_t fbHandle;
-
- drmSize registerSize;
- drm_handle_t registerHandle;
-
RADEONCardType cardType; /* Current card is a PCI card */
- drmSize pciSize;
- drm_handle_t pciMemHandle;
- unsigned char *PCI; /* Map */
-
- Bool depthMoves; /* Enable depth moves -- slow! */
- Bool allowPageFlip; /* Enable 3d page flipping */
-#ifdef DAMAGE
- DamagePtr pDamage;
- RegionRec driRegion;
-#endif
- Bool have3DWindows; /* Are there any 3d clients? */
-
- int pciAperSize;
- drmSize gartSize;
- drm_handle_t agpMemHandle; /* Handle from drmAgpAlloc */
- unsigned long gartOffset;
- unsigned char *AGP; /* Map */
- int agpMode;
-
- uint32_t pciCommand;
-
struct radeon_cp *cp;
-
- /* CP ring buffer data */
- unsigned long ringStart; /* Offset into GART space */
- drm_handle_t ringHandle; /* Handle from drmAddMap */
- drmSize ringMapSize; /* Size of map */
- int ringSize; /* Size of ring (in MB) */
- drmAddress ring; /* Map */
- int ringSizeLog2QW;
-
- unsigned long ringReadOffset; /* Offset into GART space */
- drm_handle_t ringReadPtrHandle; /* Handle from drmAddMap */
- drmSize ringReadMapSize; /* Size of map */
- drmAddress ringReadPtr; /* Map */
-
- /* CP vertex/indirect buffer data */
- unsigned long bufStart; /* Offset into GART space */
- drm_handle_t bufHandle; /* Handle from drmAddMap */
- drmSize bufMapSize; /* Size of map */
- int bufSize; /* Size of buffers (in MB) */
- drmAddress buf; /* Map */
- int bufNumBufs; /* Number of buffers */
- drmBufMapPtr buffers; /* Buffer map */
-
- /* CP GART Texture data */
- unsigned long gartTexStart; /* Offset into GART space */
- drm_handle_t gartTexHandle; /* Handle from drmAddMap */
- drmSize gartTexMapSize; /* Size of map */
- int gartTexSize; /* Size of GART tex space (in MB) */
- drmAddress gartTex; /* Map */
- int log2GARTTexGran;
-
- /* DRI screen private data */
- int fbX;
- int fbY;
- int backX;
- int backY;
- int depthX;
- int depthY;
-
- int frontOffset;
- int frontPitch;
- int backOffset;
- int backPitch;
- int depthOffset;
- int depthPitch;
- int depthBits;
- int textureOffset;
- int textureSize;
- int log2TexGran;
-
- int pciGartSize;
- uint32_t pciGartOffset;
- void *pciGartBackup;
-#ifdef USE_XAA
- uint32_t frontPitchOffset;
- uint32_t backPitchOffset;
- uint32_t depthPitchOffset;
-
- /* offscreen memory management */
- int backLines;
- FBAreaPtr backArea;
- int depthTexLines;
- FBAreaPtr depthTexArea;
+ struct radeon_dri *dri;
+#ifdef USE_EXA
+ Bool accelDFS;
#endif
-
- int irq;
-
Bool DMAForXv;
+#endif /* XF86DRI */
-#ifdef PER_CONTEXT_SAREA
- int perctx_sarea_size;
+ /* accel */
+ Bool RenderAccel; /* Render */
+ Bool allowColorTiling;
+ Bool tilingEnabled; /* mirror of sarea->tiling_enabled */
+ struct radeon_accel_state *accel_state;
+ Bool accelOn;
+ Bool useEXA;
+#ifdef USE_EXA
+ XF86ModReqInfo exaReq;
+#endif
+#ifdef USE_XAA
+ XF86ModReqInfo xaaReq;
#endif
-
-#endif /* XF86DRI */
/* XVideo */
XF86VideoAdaptorPtr adaptor;
@@ -751,21 +762,10 @@ typedef struct {
int overlay_scaler_buffer_width;
int ecp_div;
- /* Render */
- Bool RenderAccel;
-
/* general */
Bool showCache;
OptionInfoPtr Options;
- Bool useEXA;
-#ifdef USE_EXA
- XF86ModReqInfo exaReq;
-#endif
-#ifdef USE_XAA
- XF86ModReqInfo xaaReq;
-#endif
-
DisplayModePtr currentMode, savedCurrentMode;
/* special handlings for DELL triple-head server */
@@ -1060,7 +1060,7 @@ extern void RADEONAccelInitCP(ScreenPtr pScreen, XAAInfoRecPtr a);
#define RADEONCP_START(pScrn, info) \
do { \
- int _ret = drmCommandNone(info->drmFD, DRM_RADEON_CP_START); \
+ int _ret = drmCommandNone(info->dri->drmFD, DRM_RADEON_CP_START); \
if (_ret) { \
xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \
"%s: CP start %d\n", __FUNCTION__, _ret); \
@@ -1095,7 +1095,7 @@ do { \
#define RADEONCP_RESET(pScrn, info) \
do { \
- int _ret = drmCommandNone(info->drmFD, DRM_RADEON_CP_RESET); \
+ int _ret = drmCommandNone(info->dri->drmFD, DRM_RADEON_CP_RESET); \
if (_ret) { \
xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \
"%s: CP reset %d\n", __FUNCTION__, _ret); \
diff --git a/src/radeon_accel.c b/src/radeon_accel.c
index 132a2f43..79ebf84e 100644
--- a/src/radeon_accel.c
+++ b/src/radeon_accel.c
@@ -380,7 +380,7 @@ void RADEONEngineInit(ScrnInfoPtr pScrn)
np.param = RADEON_PARAM_NUM_GB_PIPES;
np.value = &num_pipes;
- if (drmCommandWriteRead(info->drmFD, DRM_RADEON_GETPARAM, &np,
+ if (drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_GETPARAM, &np,
sizeof(np)) < 0) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"Failed to determine num pipes from DRM, falling back to "
@@ -519,7 +519,7 @@ int RADEONCPStop(ScrnInfoPtr pScrn, RADEONInfoPtr info)
stop.flush = 1;
stop.idle = 1;
- ret = drmCommandWrite(info->drmFD, DRM_RADEON_CP_STOP, &stop,
+ ret = drmCommandWrite(info->dri->drmFD, DRM_RADEON_CP_STOP, &stop,
sizeof(drmRadeonCPStop));
if (ret == 0) {
@@ -532,7 +532,7 @@ int RADEONCPStop(ScrnInfoPtr pScrn, RADEONInfoPtr info)
i = 0;
do {
- ret = drmCommandWrite(info->drmFD, DRM_RADEON_CP_STOP, &stop,
+ ret = drmCommandWrite(info->dri->drmFD, DRM_RADEON_CP_STOP, &stop,
sizeof(drmRadeonCPStop));
} while (ret && errno == EBUSY && i++ < RADEON_IDLE_RETRY);
@@ -544,7 +544,7 @@ int RADEONCPStop(ScrnInfoPtr pScrn, RADEONInfoPtr info)
stop.idle = 0;
- if (drmCommandWrite(info->drmFD, DRM_RADEON_CP_STOP,
+ if (drmCommandWrite(info->dri->drmFD, DRM_RADEON_CP_STOP,
&stop, sizeof(drmRadeonCPStop))) {
return -errno;
} else {
@@ -587,7 +587,7 @@ drmBufPtr RADEONCPGetBuffer(ScrnInfoPtr pScrn)
while (1) {
do {
- ret = drmDMA(info->drmFD, &dma);
+ ret = drmDMA(info->dri->drmFD, &dma);
if (ret && ret != -EBUSY) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"%s: CP GetBuffer %d\n", __FUNCTION__, ret);
@@ -595,7 +595,7 @@ drmBufPtr RADEONCPGetBuffer(ScrnInfoPtr pScrn)
} while ((ret == -EBUSY) && (i++ < RADEON_TIMEOUT));
if (ret == 0) {
- buf = &info->buffers->list[indx];
+ buf = &info->dri->buffers->list[indx];
buf->used = 0;
if (RADEON_VERBOSE) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
@@ -637,7 +637,7 @@ void RADEONCPFlushIndirect(ScrnInfoPtr pScrn, int discard)
indirect.end = buffer->used;
indirect.discard = discard;
- drmCommandWriteRead(info->drmFD, DRM_RADEON_INDIRECT,
+ drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_INDIRECT,
&indirect, sizeof(drmRadeonIndirect));
if (discard) {
@@ -676,7 +676,7 @@ void RADEONCPReleaseIndirect(ScrnInfoPtr pScrn)
indirect.end = buffer->used;
indirect.discard = 1;
- drmCommandWriteRead(info->drmFD, DRM_RADEON_INDIRECT,
+ drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_INDIRECT,
&indirect, sizeof(drmRadeonIndirect));
}
@@ -992,7 +992,7 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen)
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
RADEONInfoPtr info = RADEONPTR(pScrn);
int cpp = info->CurrentLayout.pixel_bytes;
- int depthCpp = (info->depthBits - 8) / 4;
+ int depthCpp = (info->dri->depthBits - 8) / 4;
int width_bytes = pScrn->displayWidth * cpp;
int bufferSize;
int depthSize;
@@ -1002,9 +1002,9 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen)
BoxRec MemBox;
FBAreaPtr fbarea;
- info->frontOffset = 0;
- info->frontPitch = pScrn->displayWidth;
- info->backPitch = pScrn->displayWidth;
+ info->dri->frontOffset = 0;
+ info->dri->frontPitch = pScrn->displayWidth;
+ info->dri->backPitch = pScrn->displayWidth;
/* make sure we use 16 line alignment for tiling (8 might be enough).
* Might need that for non-XF86DRI too?
@@ -1021,18 +1021,18 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen)
* which is always the case if color tiling is used due to color pitch
* but not necessarily otherwise, and its height a multiple of 16 lines.
*/
- info->depthPitch = (pScrn->displayWidth + 31) & ~31;
- depthSize = ((((pScrn->virtualY + 15) & ~15) * info->depthPitch
+ info->dri->depthPitch = (pScrn->displayWidth + 31) & ~31;
+ depthSize = ((((pScrn->virtualY + 15) & ~15) * info->dri->depthPitch
* depthCpp + RADEON_BUFFER_ALIGN) & ~RADEON_BUFFER_ALIGN);
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Using %d MB GART aperture\n", info->gartSize);
+ "Using %d MB GART aperture\n", info->dri->gartSize);
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Using %d MB for the ring buffer\n", info->ringSize);
+ "Using %d MB for the ring buffer\n", info->dri->ringSize);
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Using %d MB for vertex/indirect buffers\n", info->bufSize);
+ "Using %d MB for vertex/indirect buffers\n", info->dri->bufSize);
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Using %d MB for GART textures\n", info->gartTexSize);
+ "Using %d MB for GART textures\n", info->dri->gartTexSize);
/* Try for front, back, depth, and three framebuffers worth of
* pixmap cache. Should be enough for a fullscreen background
@@ -1042,35 +1042,35 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen)
* otherwise probably), and never reserve more than 3 offscreen buffers as it's
* probably useless for XAA.
*/
- if (info->textureSize >= 0) {
+ if (info->dri->textureSize >= 0) {
texsizerequest = ((int)info->FbMapSize - 2 * bufferSize - depthSize
- 2 * width_bytes - 16384 - info->FbSecureSize)
/* first divide, then multiply or we'll get an overflow (been there...) */
- / 100 * info->textureSize;
+ / 100 * info->dri->textureSize;
}
else {
texsizerequest = (int)info->FbMapSize / 2;
}
- info->textureSize = info->FbMapSize - info->FbSecureSize - 5 * bufferSize - depthSize;
+ info->dri->textureSize = info->FbMapSize - info->FbSecureSize - 5 * bufferSize - depthSize;
/* If that gives us less than the requested memory, let's
* be greedy and grab some more. Sorry, I care more about 3D
* performance than playing nicely, and you'll get around a full
* framebuffer's worth of pixmap cache anyway.
*/
- if (info->textureSize < texsizerequest) {
- info->textureSize = info->FbMapSize - 4 * bufferSize - depthSize;
+ if (info->dri->textureSize < texsizerequest) {
+ info->dri->textureSize = info->FbMapSize - 4 * bufferSize - depthSize;
}
- if (info->textureSize < texsizerequest) {
- info->textureSize = info->FbMapSize - 3 * bufferSize - depthSize;
+ if (info->dri->textureSize < texsizerequest) {
+ info->dri->textureSize = info->FbMapSize - 3 * bufferSize - depthSize;
}
/* If there's still no space for textures, try without pixmap cache, but
* never use the reserved space, the space hw cursor and PCIGART table might
* use.
*/
- if (info->textureSize < 0) {
- info->textureSize = info->FbMapSize - 2 * bufferSize - depthSize
+ if (info->dri->textureSize < 0) {
+ info->dri->textureSize = info->FbMapSize - 2 * bufferSize - depthSize
- 2 * width_bytes - 16384 - info->FbSecureSize;
}
@@ -1079,14 +1079,14 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen)
*/
/* FIXME: what's this good for? condition is pretty much impossible to meet */
if ((int)info->FbMapSize - 8192*width_bytes - bufferSize - depthSize
- > info->textureSize) {
- info->textureSize =
+ > info->dri->textureSize) {
+ info->dri->textureSize =
info->FbMapSize - 8192*width_bytes - bufferSize - depthSize;
}
/* If backbuffer is disabled, don't allocate memory for it */
- if (info->noBackBuffer) {
- info->textureSize += bufferSize;
+ if (info->dri->noBackBuffer) {
+ info->dri->textureSize += bufferSize;
}
/* RADEON_BUFFER_ALIGN is not sufficient for backbuffer!
@@ -1098,61 +1098,61 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen)
can't be used (?) due to that log_tex_granularity thing???
Could use different copyscreentoscreen function for the pageflip copies
(which would use different src and dst offsets) to avoid this. */
- if (info->allowColorTiling && !info->noBackBuffer) {
- info->textureSize = info->FbMapSize - ((info->FbMapSize - info->textureSize +
+ if (info->allowColorTiling && !info->dri->noBackBuffer) {
+ info->dri->textureSize = info->FbMapSize - ((info->FbMapSize - info->dri->textureSize +
width_bytes * 16 - 1) / (width_bytes * 16)) * (width_bytes * 16);
}
- if (info->textureSize > 0) {
- l = RADEONMinBits((info->textureSize-1) / RADEON_NR_TEX_REGIONS);
+ if (info->dri->textureSize > 0) {
+ l = RADEONMinBits((info->dri->textureSize-1) / RADEON_NR_TEX_REGIONS);
if (l < RADEON_LOG_TEX_GRANULARITY)
l = RADEON_LOG_TEX_GRANULARITY;
/* Round the texture size up to the nearest whole number of
* texture regions. Again, be greedy about this, don't
* round down.
*/
- info->log2TexGran = l;
- info->textureSize = (info->textureSize >> l) << l;
+ info->dri->log2TexGran = l;
+ info->dri->textureSize = (info->dri->textureSize >> l) << l;
} else {
- info->textureSize = 0;
+ info->dri->textureSize = 0;
}
/* Set a minimum usable local texture heap size. This will fit
* two 256x256x32bpp textures.
*/
- if (info->textureSize < 512 * 1024) {
- info->textureOffset = 0;
- info->textureSize = 0;
+ if (info->dri->textureSize < 512 * 1024) {
+ info->dri->textureOffset = 0;
+ info->dri->textureSize = 0;
}
- if (info->allowColorTiling && !info->noBackBuffer) {
- info->textureOffset = ((info->FbMapSize - info->textureSize) /
- (width_bytes * 16)) * (width_bytes * 16);
+ if (info->allowColorTiling && !info->dri->noBackBuffer) {
+ info->dri->textureOffset = ((info->FbMapSize - info->dri->textureSize) /
+ (width_bytes * 16)) * (width_bytes * 16);
}
else {
/* Reserve space for textures */
- info->textureOffset = ((info->FbMapSize - info->textureSize +
- RADEON_BUFFER_ALIGN) &
- ~(uint32_t)RADEON_BUFFER_ALIGN);
+ info->dri->textureOffset = ((info->FbMapSize - info->dri->textureSize +
+ RADEON_BUFFER_ALIGN) &
+ ~(uint32_t)RADEON_BUFFER_ALIGN);
}
/* Reserve space for the shared depth
* buffer.
*/
- info->depthOffset = ((info->textureOffset - depthSize +
- RADEON_BUFFER_ALIGN) &
- ~(uint32_t)RADEON_BUFFER_ALIGN);
+ info->dri->depthOffset = ((info->dri->textureOffset - depthSize +
+ RADEON_BUFFER_ALIGN) &
+ ~(uint32_t)RADEON_BUFFER_ALIGN);
/* Reserve space for the shared back buffer */
- if (info->noBackBuffer) {
- info->backOffset = info->depthOffset;
+ if (info->dri->noBackBuffer) {
+ info->dri->backOffset = info->dri->depthOffset;
} else {
- info->backOffset = ((info->depthOffset - bufferSize +
- RADEON_BUFFER_ALIGN) &
- ~(uint32_t)RADEON_BUFFER_ALIGN);
+ info->dri->backOffset = ((info->dri->depthOffset - bufferSize +
+ RADEON_BUFFER_ALIGN) &
+ ~(uint32_t)RADEON_BUFFER_ALIGN);
}
- info->backY = info->backOffset / width_bytes;
- info->backX = (info->backOffset - (info->backY * width_bytes)) / cpp;
+ info->dri->backY = info->dri->backOffset / width_bytes;
+ info->dri->backX = (info->dri->backOffset - (info->dri->backY * width_bytes)) / cpp;
scanlines = (info->FbMapSize-info->FbSecureSize) / width_bytes;
if (scanlines > 8191)
@@ -1203,12 +1203,12 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen)
/* Lines in offscreen area needed for depth buffer and
* textures
*/
- info->depthTexLines = (scanlines
- - info->depthOffset / width_bytes);
- info->backLines = (scanlines
- - info->backOffset / width_bytes
- - info->depthTexLines);
- info->backArea = NULL;
+ info->dri->depthTexLines = (scanlines
+ - info->dri->depthOffset / width_bytes);
+ info->dri->backLines = (scanlines
+ - info->dri->backOffset / width_bytes
+ - info->dri->depthTexLines);
+ info->dri->backArea = NULL;
} else {
xf86DrvMsg(scrnIndex, X_ERROR,
"Unable to determine largest offscreen area "
@@ -1219,30 +1219,30 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen)
xf86DrvMsg(scrnIndex, X_INFO,
"Will use front buffer at offset 0x%x\n",
- info->frontOffset);
+ info->dri->frontOffset);
xf86DrvMsg(scrnIndex, X_INFO,
"Will use back buffer at offset 0x%x\n",
- info->backOffset);
+ info->dri->backOffset);
xf86DrvMsg(scrnIndex, X_INFO,
"Will use depth buffer at offset 0x%x\n",
- info->depthOffset);
+ info->dri->depthOffset);
if (info->cardType==CARD_PCIE)
xf86DrvMsg(scrnIndex, X_INFO,
"Will use %d kb for PCI GART table at offset 0x%x\n",
- info->pciGartSize/1024, (unsigned)info->pciGartOffset);
+ info->dri->pciGartSize/1024, (unsigned)info->dri->pciGartOffset);
xf86DrvMsg(scrnIndex, X_INFO,
"Will use %d kb for textures at offset 0x%x\n",
- info->textureSize/1024, info->textureOffset);
+ info->dri->textureSize/1024, info->dri->textureOffset);
- info->frontPitchOffset = (((info->frontPitch * cpp / 64) << 22) |
- ((info->frontOffset + info->fbLocation) >> 10));
+ info->dri->frontPitchOffset = (((info->dri->frontPitch * cpp / 64) << 22) |
+ ((info->dri->frontOffset + info->fbLocation) >> 10));
- info->backPitchOffset = (((info->backPitch * cpp / 64) << 22) |
- ((info->backOffset + info->fbLocation) >> 10));
+ info->dri->backPitchOffset = (((info->dri->backPitch * cpp / 64) << 22) |
+ ((info->dri->backOffset + info->fbLocation) >> 10));
- info->depthPitchOffset = (((info->depthPitch * depthCpp / 64) << 22) |
- ((info->depthOffset + info->fbLocation) >> 10));
+ info->dri->depthPitchOffset = (((info->dri->depthPitch * depthCpp / 64) << 22) |
+ ((info->dri->depthOffset + info->fbLocation) >> 10));
return TRUE;
}
#endif /* XF86DRI */
diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c
index a70a2751..dba197eb 100644
--- a/src/radeon_commonfuncs.c
+++ b/src/radeon_commonfuncs.c
@@ -694,7 +694,7 @@ void FUNC_NAME(RADEONWaitForIdle)(ScrnInfoPtr pScrn)
for (;;) {
do {
- ret = drmCommandNone(info->drmFD, DRM_RADEON_CP_IDLE);
+ ret = drmCommandNone(info->dri->drmFD, DRM_RADEON_CP_IDLE);
if (ret && ret != -EBUSY) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"%s: CP idle %d\n", __FUNCTION__, ret);
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index 9eb94481..beb63b58 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -492,7 +492,7 @@ radeon_crtc_shadow_allocate (xf86CrtcPtr crtc, int width, int height)
return NULL;
}
#ifdef XF86DRI
- rotate_offset = info->frontOffset +
+ rotate_offset = info->dri->frontOffset +
radeon_crtc->rotate_mem_xaa->offset * cpp;
#endif
}
diff --git a/src/radeon_dri.c b/src/radeon_dri.c
index c10301bd..1baed4b3 100644
--- a/src/radeon_dri.c
+++ b/src/radeon_dri.c
@@ -92,7 +92,7 @@ static Bool RADEONInitVisualConfigs(ScreenPtr pScreen)
RADEONConfigPrivPtr *pRADEONConfigPtrs = 0;
int i, accum, stencil, db, use_db;
- use_db = !info->noBackBuffer ? 1 : 0;
+ use_db = !info->dri->noBackBuffer ? 1 : 0;
switch (info->CurrentLayout.pixel_code) {
case 8: /* 8bpp mode is not support */
@@ -166,7 +166,7 @@ static Bool RADEONInitVisualConfigs(ScreenPtr pScreen)
pConfigs[i].doubleBuffer = FALSE;
pConfigs[i].stereo = FALSE;
pConfigs[i].bufferSize = 16;
- pConfigs[i].depthSize = info->depthBits;
+ pConfigs[i].depthSize = info->dri->depthBits;
if (pConfigs[i].depthSize == 24 ? (RADEON_USE_STENCIL - stencil)
: stencil) {
pConfigs[i].stencilSize = 8;
@@ -252,7 +252,7 @@ static Bool RADEONInitVisualConfigs(ScreenPtr pScreen)
pConfigs[i].doubleBuffer = FALSE;
pConfigs[i].stereo = FALSE;
pConfigs[i].bufferSize = 32;
- pConfigs[i].depthSize = info->depthBits;
+ pConfigs[i].depthSize = info->dri->depthBits;
if (pConfigs[i].depthSize == 24 ? (RADEON_USE_STENCIL - stencil)
: stencil) {
pConfigs[i].stencilSize = 8;
@@ -280,9 +280,9 @@ static Bool RADEONInitVisualConfigs(ScreenPtr pScreen)
break;
}
- info->numVisualConfigs = numConfigs;
- info->pVisualConfigs = pConfigs;
- info->pVisualConfigsPriv = pRADEONConfigs;
+ info->dri->numVisualConfigs = numConfigs;
+ info->dri->pVisualConfigs = pConfigs;
+ info->dri->pVisualConfigsPriv = pRADEONConfigs;
GlxSetVisualConfigs(numConfigs, pConfigs, (void**)pRADEONConfigPtrs);
return TRUE;
}
@@ -300,8 +300,8 @@ static Bool RADEONCreateContext(ScreenPtr pScreen, VisualPtr visual,
ctx_info = (RADEONDRIContextPtr)contextStore;
if (!ctx_info) return FALSE;
- if (drmAddMap(info->drmFD, 0,
- info->perctx_sarea_size,
+ if (drmAddMap(info->dri->drmFD, 0,
+ info->dri->perctx_sarea_size,
DRM_SHM,
DRM_REMOVABLE,
&ctx_info->sarea_handle) < 0) {
@@ -311,12 +311,12 @@ static Bool RADEONCreateContext(ScreenPtr pScreen, VisualPtr visual,
return FALSE;
}
- if (drmAddContextPrivateMapping(info->drmFD, hwContext,
+ if (drmAddContextPrivateMapping(info->dri->drmFD, hwContext,
ctx_info->sarea_handle) < 0) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"[dri] could not associate private sarea to ctx id (%d)\n",
(int)hwContext);
- drmRmMap(info->drmFD, ctx_info->sarea_handle);
+ drmRmMap(info->dri->drmFD, ctx_info->sarea_handle);
return FALSE;
}
@@ -337,7 +337,7 @@ static void RADEONDestroyContext(ScreenPtr pScreen, drm_context_t hwContext,
ctx_info = (RADEONDRIContextPtr)contextStore;
if (!ctx_info) return;
- if (drmRmMap(info->drmFD, ctx_info->sarea_handle) < 0) {
+ if (drmRmMap(info->dri->drmFD, ctx_info->sarea_handle) < 0) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"[dri] could not remove private sarea for ctx id (%d)\n",
(int)hwContext);
@@ -368,17 +368,17 @@ static void RADEONEnterServer(ScreenPtr pScreen)
}
#ifdef DAMAGE
- if (!info->pDamage && info->allowPageFlip) {
+ if (!info->dri->pDamage && info->dri->allowPageFlip) {
PixmapPtr pPix = pScreen->GetScreenPixmap(pScreen);
- info->pDamage = DamageCreate(NULL, NULL, DamageReportNone, TRUE,
- pScreen, pPix);
+ info->dri->pDamage = DamageCreate(NULL, NULL, DamageReportNone, TRUE,
+ pScreen, pPix);
- if (info->pDamage == NULL) {
+ if (info->dri->pDamage == NULL) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"No screen damage record, page flipping disabled\n");
- info->allowPageFlip = 0;
+ info->dri->allowPageFlip = 0;
} else {
- DamageRegister(&pPix->drawable, info->pDamage);
+ DamageRegister(&pPix->drawable, info->dri->pDamage);
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Damage tracking initialized for page flipping\n");
@@ -401,8 +401,8 @@ static void RADEONLeaveServer(ScreenPtr pScreen)
RING_LOCALS;
#ifdef DAMAGE
- if (info->pDamage) {
- RegionPtr pDamageReg = DamageRegion(info->pDamage);
+ if (info->dri->pDamage) {
+ RegionPtr pDamageReg = DamageRegion(info->dri->pDamage);
int nrects = pDamageReg ? REGION_NUM_RECTS(pDamageReg) : 0;
if (nrects) {
@@ -451,17 +451,17 @@ static void RADEONDRISwapContext(ScreenPtr pScreen, DRISyncType syncType,
/* 16-bit depth buffer functions */
#define WRITE_DEPTH16(_x, _y, d) \
- *(uint16_t *)(pointer)(buf + 2*(_x + _y*info->frontPitch)) = (d)
+ *(uint16_t *)(pointer)(buf + 2*(_x + _y*info->dri->frontPitch)) = (d)
#define READ_DEPTH16(d, _x, _y) \
- (d) = *(uint16_t *)(pointer)(buf + 2*(_x + _y*info->frontPitch))
+ (d) = *(uint16_t *)(pointer)(buf + 2*(_x + _y*info->dri->frontPitch))
/* 32-bit depth buffer (stencil and depth simultaneously) functions */
#define WRITE_DEPTHSTENCIL32(_x, _y, d) \
- *(uint32_t *)(pointer)(buf + 4*(_x + _y*info->frontPitch)) = (d)
+ *(uint32_t *)(pointer)(buf + 4*(_x + _y*info->dri->frontPitch)) = (d)
#define READ_DEPTHSTENCIL32(d, _x, _y) \
- (d) = *(uint32_t *)(pointer)(buf + 4*(_x + _y*info->frontPitch))
+ (d) = *(uint32_t *)(pointer)(buf + 4*(_x + _y*info->dri->frontPitch))
/* Screen to screen copy of data in the depth buffer */
static void RADEONScreenToScreenCopyDepth(ScrnInfoPtr pScrn,
@@ -470,7 +470,7 @@ static void RADEONScreenToScreenCopyDepth(ScrnInfoPtr pScrn,
int w, int h)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *buf = info->FB + info->depthOffset;
+ unsigned char *buf = info->FB + info->dri->depthOffset;
int xstart, xend, xdir;
int ystart, yend, ydir;
int x, y, d;
@@ -641,7 +641,7 @@ static void RADEONDRIMoveBuffers(WindowPtr pParent, DDXPointRec ptOldOrg,
}
/* pretty much a hack. */
- info->accel_state->dst_pitch_offset = info->backPitchOffset;
+ info->accel_state->dst_pitch_offset = info->dri->backPitchOffset;
if (info->tilingEnabled)
info->accel_state->dst_pitch_offset |= RADEON_DST_TILE_MACRO;
@@ -669,7 +669,7 @@ static void RADEONDRIMoveBuffers(WindowPtr pParent, DDXPointRec ptOldOrg,
destx, desty,
w, h);
- if (info->depthMoves) {
+ if (info->dri->depthMoves) {
RADEONScreenToScreenCopyDepth(pScrn,
xa, ya,
destx, desty,
@@ -677,7 +677,7 @@ static void RADEONDRIMoveBuffers(WindowPtr pParent, DDXPointRec ptOldOrg,
}
}
- info->accel_state->dst_pitch_offset = info->frontPitchOffset;;
+ info->accel_state->dst_pitch_offset = info->dri->frontPitchOffset;;
xfree(pptNew2);
xfree(pboxNew2);
@@ -692,36 +692,36 @@ static void RADEONDRIInitGARTValues(RADEONInfoPtr info)
{
int s, l;
- info->gartOffset = 0;
+ info->dri->gartOffset = 0;
/* Initialize the CP ring buffer data */
- info->ringStart = info->gartOffset;
- info->ringMapSize = info->ringSize*1024*1024 + radeon_drm_page_size;
- info->ringSizeLog2QW = RADEONMinBits(info->ringSize*1024*1024/8)-1;
+ info->dri->ringStart = info->dri->gartOffset;
+ info->dri->ringMapSize = info->dri->ringSize*1024*1024 + radeon_drm_page_size;
+ info->dri->ringSizeLog2QW = RADEONMinBits(info->dri->ringSize*1024*1024/8)-1;
- info->ringReadOffset = info->ringStart + info->ringMapSize;
- info->ringReadMapSize = radeon_drm_page_size;
+ info->dri->ringReadOffset = info->dri->ringStart + info->dri->ringMapSize;
+ info->dri->ringReadMapSize = radeon_drm_page_size;
/* Reserve space for vertex/indirect buffers */
- info->bufStart = info->ringReadOffset + info->ringReadMapSize;
- info->bufMapSize = info->bufSize*1024*1024;
+ info->dri->bufStart = info->dri->ringReadOffset + info->dri->ringReadMapSize;
+ info->dri->bufMapSize = info->dri->bufSize*1024*1024;
/* Reserve the rest for GART textures */
- info->gartTexStart = info->bufStart + info->bufMapSize;
- s = (info->gartSize*1024*1024 - info->gartTexStart);
+ info->dri->gartTexStart = info->dri->bufStart + info->dri->bufMapSize;
+ s = (info->dri->gartSize*1024*1024 - info->dri->gartTexStart);
l = RADEONMinBits((s-1) / RADEON_NR_TEX_REGIONS);
if (l < RADEON_LOG_TEX_GRANULARITY) l = RADEON_LOG_TEX_GRANULARITY;
- info->gartTexMapSize = (s >> l) << l;
- info->log2GARTTexGran = l;
+ info->dri->gartTexMapSize = (s >> l) << l;
+ info->dri->log2GARTTexGran = l;
}
/* Set AGP transfer mode according to requests and constraints */
static Bool RADEONSetAgpMode(RADEONInfoPtr info, ScreenPtr pScreen)
{
unsigned char *RADEONMMIO = info->MMIO;
- unsigned long mode = drmAgpGetMode(info->drmFD); /* Default mode */
- unsigned int vendor = drmAgpVendorId(info->drmFD);
- unsigned int device = drmAgpDeviceId(info->drmFD);
+ unsigned long mode = drmAgpGetMode(info->dri->drmFD); /* Default mode */
+ unsigned int vendor = drmAgpVendorId(info->dri->drmFD);
+ unsigned int device = drmAgpDeviceId(info->dri->drmFD);
/* ignore agp 3.0 mode bit from the chip as it's buggy on some cards with
pcie-agp rialto bridge chip - use the one from bridge which must match */
uint32_t agp_status = (INREG(RADEON_AGP_STATUS) | RADEON_AGPv3_MODE) & mode;
@@ -739,26 +739,26 @@ static Bool RADEONSetAgpMode(RADEONInfoPtr info, ScreenPtr pScreen)
from = X_DEFAULT;
- if (xf86GetOptValInteger(info->Options, OPTION_AGP_MODE, &info->agpMode)) {
- if ((info->agpMode < (is_v3 ? 4 : 1)) ||
- (info->agpMode > (is_v3 ? 8 : 4)) ||
- (info->agpMode & (info->agpMode - 1))) {
+ if (xf86GetOptValInteger(info->Options, OPTION_AGP_MODE, &info->dri->agpMode)) {
+ if ((info->dri->agpMode < (is_v3 ? 4 : 1)) ||
+ (info->dri->agpMode > (is_v3 ? 8 : 4)) ||
+ (info->dri->agpMode & (info->dri->agpMode - 1))) {
xf86DrvMsg(pScreen->myNum, X_ERROR,
"Illegal AGP Mode: %d (valid values: %s), leaving at "
- "%dx\n", info->agpMode, is_v3 ? "4, 8" : "1, 2, 4",
+ "%dx\n", info->dri->agpMode, is_v3 ? "4, 8" : "1, 2, 4",
defaultMode);
- info->agpMode = defaultMode;
+ info->dri->agpMode = defaultMode;
} else
from = X_CONFIG;
} else
- info->agpMode = defaultMode;
+ info->dri->agpMode = defaultMode;
- xf86DrvMsg(pScreen->myNum, from, "Using AGP %dx\n", info->agpMode);
+ xf86DrvMsg(pScreen->myNum, from, "Using AGP %dx\n", info->dri->agpMode);
mode &= ~RADEON_AGP_MODE_MASK;
if (is_v3) {
/* only set one mode bit for AGPv3 */
- switch (info->agpMode) {
+ switch (info->dri->agpMode) {
case 8: mode |= RADEON_AGPv3_8X_MODE; break;
case 4: default: mode |= RADEON_AGPv3_4X_MODE;
}
@@ -766,7 +766,7 @@ static Bool RADEONSetAgpMode(RADEONInfoPtr info, ScreenPtr pScreen)
* currently these bits are not used in all tested cards.
*/
} else {
- switch (info->agpMode) {
+ switch (info->dri->agpMode) {
case 4: mode |= RADEON_AGP_4X_MODE;
case 2: mode |= RADEON_AGP_2X_MODE;
case 1: default: mode |= RADEON_AGP_1X_MODE;
@@ -800,9 +800,9 @@ static Bool RADEONSetAgpMode(RADEONInfoPtr info, ScreenPtr pScreen)
PCI_DEV_VENDOR_ID(info->PciInfo),
PCI_DEV_DEVICE_ID(info->PciInfo));
- if (drmAgpEnable(info->drmFD, mode) < 0) {
+ if (drmAgpEnable(info->dri->drmFD, mode) < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR, "[agp] AGP not enabled\n");
- drmAgpRelease(info->drmFD);
+ drmAgpRelease(info->dri->drmFD);
return FALSE;
}
@@ -829,15 +829,15 @@ static void RADEONSetAgpBase(RADEONInfoPtr info, ScreenPtr pScreen)
* agp_base_2 ?
*/
if (info->ChipFamily == CHIP_FAMILY_RV515)
- OUTMC(pScrn, RV515_MC_AGP_BASE, drmAgpBase(info->drmFD));
+ OUTMC(pScrn, RV515_MC_AGP_BASE, drmAgpBase(info->dri->drmFD));
else if ((info->ChipFamily >= CHIP_FAMILY_R520) &&
(info->ChipFamily <= CHIP_FAMILY_RV570))
- OUTMC(pScrn, R520_MC_AGP_BASE, drmAgpBase(info->drmFD));
+ OUTMC(pScrn, R520_MC_AGP_BASE, drmAgpBase(info->dri->drmFD));
else if ((info->ChipFamily == CHIP_FAMILY_RS690) ||
(info->ChipFamily == CHIP_FAMILY_RS740))
- OUTMC(pScrn, RS690_MC_AGP_BASE, drmAgpBase(info->drmFD));
+ OUTMC(pScrn, RS690_MC_AGP_BASE, drmAgpBase(info->dri->drmFD));
else if (info->ChipFamily < CHIP_FAMILY_RV515)
- OUTREG(RADEON_AGP_BASE, drmAgpBase(info->drmFD));
+ OUTREG(RADEON_AGP_BASE, drmAgpBase(info->dri->drmFD));
}
/* Initialize the AGP state. Request memory for use in AGP space, and
@@ -847,7 +847,7 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen)
{
int ret;
- if (drmAgpAcquire(info->drmFD) < 0) {
+ if (drmAgpAcquire(info->dri->drmFD) < 0) {
xf86DrvMsg(pScreen->myNum, X_WARNING, "[agp] AGP not available\n");
return FALSE;
}
@@ -857,101 +857,101 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen)
RADEONDRIInitGARTValues(info);
- if ((ret = drmAgpAlloc(info->drmFD, info->gartSize*1024*1024, 0, NULL,
- &info->agpMemHandle)) < 0) {
+ if ((ret = drmAgpAlloc(info->dri->drmFD, info->dri->gartSize*1024*1024, 0, NULL,
+ &info->dri->agpMemHandle)) < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR, "[agp] Out of memory (%d)\n", ret);
- drmAgpRelease(info->drmFD);
+ drmAgpRelease(info->dri->drmFD);
return FALSE;
}
xf86DrvMsg(pScreen->myNum, X_INFO,
"[agp] %d kB allocated with handle 0x%08x\n",
- info->gartSize*1024, info->agpMemHandle);
+ info->dri->gartSize*1024, info->dri->agpMemHandle);
- if (drmAgpBind(info->drmFD,
- info->agpMemHandle, info->gartOffset) < 0) {
+ if (drmAgpBind(info->dri->drmFD,
+ info->dri->agpMemHandle, info->dri->gartOffset) < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR, "[agp] Could not bind\n");
- drmAgpFree(info->drmFD, info->agpMemHandle);
- drmAgpRelease(info->drmFD);
+ drmAgpFree(info->dri->drmFD, info->dri->agpMemHandle);
+ drmAgpRelease(info->dri->drmFD);
return FALSE;
}
- if (drmAddMap(info->drmFD, info->ringStart, info->ringMapSize,
- DRM_AGP, DRM_READ_ONLY, &info->ringHandle) < 0) {
+ if (drmAddMap(info->dri->drmFD, info->dri->ringStart, info->dri->ringMapSize,
+ DRM_AGP, DRM_READ_ONLY, &info->dri->ringHandle) < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[agp] Could not add ring mapping\n");
return FALSE;
}
xf86DrvMsg(pScreen->myNum, X_INFO,
- "[agp] ring handle = 0x%08x\n", info->ringHandle);
+ "[agp] ring handle = 0x%08x\n", info->dri->ringHandle);
- if (drmMap(info->drmFD, info->ringHandle, info->ringMapSize,
- &info->ring) < 0) {
+ if (drmMap(info->dri->drmFD, info->dri->ringHandle, info->dri->ringMapSize,
+ &info->dri->ring) < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR, "[agp] Could not map ring\n");
return FALSE;
}
xf86DrvMsg(pScreen->myNum, X_INFO,
"[agp] Ring mapped at 0x%08lx\n",
- (unsigned long)info->ring);
+ (unsigned long)info->dri->ring);
- if (drmAddMap(info->drmFD, info->ringReadOffset, info->ringReadMapSize,
- DRM_AGP, DRM_READ_ONLY, &info->ringReadPtrHandle) < 0) {
+ if (drmAddMap(info->dri->drmFD, info->dri->ringReadOffset, info->dri->ringReadMapSize,
+ DRM_AGP, DRM_READ_ONLY, &info->dri->ringReadPtrHandle) < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[agp] Could not add ring read ptr mapping\n");
return FALSE;
}
xf86DrvMsg(pScreen->myNum, X_INFO,
"[agp] ring read ptr handle = 0x%08x\n",
- info->ringReadPtrHandle);
+ info->dri->ringReadPtrHandle);
- if (drmMap(info->drmFD, info->ringReadPtrHandle, info->ringReadMapSize,
- &info->ringReadPtr) < 0) {
+ if (drmMap(info->dri->drmFD, info->dri->ringReadPtrHandle, info->dri->ringReadMapSize,
+ &info->dri->ringReadPtr) < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[agp] Could not map ring read ptr\n");
return FALSE;
}
xf86DrvMsg(pScreen->myNum, X_INFO,
"[agp] Ring read ptr mapped at 0x%08lx\n",
- (unsigned long)info->ringReadPtr);
+ (unsigned long)info->dri->ringReadPtr);
- if (drmAddMap(info->drmFD, info->bufStart, info->bufMapSize,
- DRM_AGP, 0, &info->bufHandle) < 0) {
+ if (drmAddMap(info->dri->drmFD, info->dri->bufStart, info->dri->bufMapSize,
+ DRM_AGP, 0, &info->dri->bufHandle) < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[agp] Could not add vertex/indirect buffers mapping\n");
return FALSE;
}
xf86DrvMsg(pScreen->myNum, X_INFO,
"[agp] vertex/indirect buffers handle = 0x%08x\n",
- info->bufHandle);
+ info->dri->bufHandle);
- if (drmMap(info->drmFD, info->bufHandle, info->bufMapSize,
- &info->buf) < 0) {
+ if (drmMap(info->dri->drmFD, info->dri->bufHandle, info->dri->bufMapSize,
+ &info->dri->buf) < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[agp] Could not map vertex/indirect buffers\n");
return FALSE;
}
xf86DrvMsg(pScreen->myNum, X_INFO,
"[agp] Vertex/indirect buffers mapped at 0x%08lx\n",
- (unsigned long)info->buf);
+ (unsigned long)info->dri->buf);
- if (drmAddMap(info->drmFD, info->gartTexStart, info->gartTexMapSize,
- DRM_AGP, 0, &info->gartTexHandle) < 0) {
+ if (drmAddMap(info->dri->drmFD, info->dri->gartTexStart, info->dri->gartTexMapSize,
+ DRM_AGP, 0, &info->dri->gartTexHandle) < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[agp] Could not add GART texture map mapping\n");
return FALSE;
}
xf86DrvMsg(pScreen->myNum, X_INFO,
"[agp] GART texture map handle = 0x%08x\n",
- info->gartTexHandle);
+ info->dri->gartTexHandle);
- if (drmMap(info->drmFD, info->gartTexHandle, info->gartTexMapSize,
- &info->gartTex) < 0) {
+ if (drmMap(info->dri->drmFD, info->dri->gartTexHandle, info->dri->gartTexMapSize,
+ &info->dri->gartTex) < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[agp] Could not map GART texture map\n");
return FALSE;
}
xf86DrvMsg(pScreen->myNum, X_INFO,
"[agp] GART Texture map mapped at 0x%08lx\n",
- (unsigned long)info->gartTex);
+ (unsigned long)info->dri->gartTex);
RADEONSetAgpBase(info, pScreen);
@@ -966,104 +966,104 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen)
int ret;
int flags = DRM_READ_ONLY | DRM_LOCKED | DRM_KERNEL;
- ret = drmScatterGatherAlloc(info->drmFD, info->gartSize*1024*1024,
- &info->pciMemHandle);
+ ret = drmScatterGatherAlloc(info->dri->drmFD, info->dri->gartSize*1024*1024,
+ &info->dri->pciMemHandle);
if (ret < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR, "[pci] Out of memory (%d)\n", ret);
return FALSE;
}
xf86DrvMsg(pScreen->myNum, X_INFO,
"[pci] %d kB allocated with handle 0x%08x\n",
- info->gartSize*1024, info->pciMemHandle);
+ info->dri->gartSize*1024, info->dri->pciMemHandle);
RADEONDRIInitGARTValues(info);
- if (drmAddMap(info->drmFD, info->ringStart, info->ringMapSize,
- DRM_SCATTER_GATHER, flags, &info->ringHandle) < 0) {
+ if (drmAddMap(info->dri->drmFD, info->dri->ringStart, info->dri->ringMapSize,
+ DRM_SCATTER_GATHER, flags, &info->dri->ringHandle) < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[pci] Could not add ring mapping\n");
return FALSE;
}
xf86DrvMsg(pScreen->myNum, X_INFO,
- "[pci] ring handle = 0x%08x\n", info->ringHandle);
+ "[pci] ring handle = 0x%08x\n", info->dri->ringHandle);
- if (drmMap(info->drmFD, info->ringHandle, info->ringMapSize,
- &info->ring) < 0) {
+ if (drmMap(info->dri->drmFD, info->dri->ringHandle, info->dri->ringMapSize,
+ &info->dri->ring) < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR, "[pci] Could not map ring\n");
return FALSE;
}
xf86DrvMsg(pScreen->myNum, X_INFO,
"[pci] Ring mapped at 0x%08lx\n",
- (unsigned long)info->ring);
+ (unsigned long)info->dri->ring);
xf86DrvMsg(pScreen->myNum, X_INFO,
"[pci] Ring contents 0x%08lx\n",
- *(unsigned long *)(pointer)info->ring);
+ *(unsigned long *)(pointer)info->dri->ring);
- if (drmAddMap(info->drmFD, info->ringReadOffset, info->ringReadMapSize,
- DRM_SCATTER_GATHER, flags, &info->ringReadPtrHandle) < 0) {
+ if (drmAddMap(info->dri->drmFD, info->dri->ringReadOffset, info->dri->ringReadMapSize,
+ DRM_SCATTER_GATHER, flags, &info->dri->ringReadPtrHandle) < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[pci] Could not add ring read ptr mapping\n");
return FALSE;
}
xf86DrvMsg(pScreen->myNum, X_INFO,
"[pci] ring read ptr handle = 0x%08x\n",
- info->ringReadPtrHandle);
+ info->dri->ringReadPtrHandle);
- if (drmMap(info->drmFD, info->ringReadPtrHandle, info->ringReadMapSize,
- &info->ringReadPtr) < 0) {
+ if (drmMap(info->dri->drmFD, info->dri->ringReadPtrHandle, info->dri->ringReadMapSize,
+ &info->dri->ringReadPtr) < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[pci] Could not map ring read ptr\n");
return FALSE;
}
xf86DrvMsg(pScreen->myNum, X_INFO,
"[pci] Ring read ptr mapped at 0x%08lx\n",
- (unsigned long)info->ringReadPtr);
+ (unsigned long)info->dri->ringReadPtr);
xf86DrvMsg(pScreen->myNum, X_INFO,
"[pci] Ring read ptr contents 0x%08lx\n",
- *(unsigned long *)(pointer)info->ringReadPtr);
+ *(unsigned long *)(pointer)info->dri->ringReadPtr);
- if (drmAddMap(info->drmFD, info->bufStart, info->bufMapSize,
- DRM_SCATTER_GATHER, 0, &info->bufHandle) < 0) {
+ if (drmAddMap(info->dri->drmFD, info->dri->bufStart, info->dri->bufMapSize,
+ DRM_SCATTER_GATHER, 0, &info->dri->bufHandle) < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[pci] Could not add vertex/indirect buffers mapping\n");
return FALSE;
}
xf86DrvMsg(pScreen->myNum, X_INFO,
"[pci] vertex/indirect buffers handle = 0x%08x\n",
- info->bufHandle);
+ info->dri->bufHandle);
- if (drmMap(info->drmFD, info->bufHandle, info->bufMapSize,
- &info->buf) < 0) {
+ if (drmMap(info->dri->drmFD, info->dri->bufHandle, info->dri->bufMapSize,
+ &info->dri->buf) < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[pci] Could not map vertex/indirect buffers\n");
return FALSE;
}
xf86DrvMsg(pScreen->myNum, X_INFO,
"[pci] Vertex/indirect buffers mapped at 0x%08lx\n",
- (unsigned long)info->buf);
+ (unsigned long)info->dri->buf);
xf86DrvMsg(pScreen->myNum, X_INFO,
"[pci] Vertex/indirect buffers contents 0x%08lx\n",
- *(unsigned long *)(pointer)info->buf);
+ *(unsigned long *)(pointer)info->dri->buf);
- if (drmAddMap(info->drmFD, info->gartTexStart, info->gartTexMapSize,
- DRM_SCATTER_GATHER, 0, &info->gartTexHandle) < 0) {
+ if (drmAddMap(info->dri->drmFD, info->dri->gartTexStart, info->dri->gartTexMapSize,
+ DRM_SCATTER_GATHER, 0, &info->dri->gartTexHandle) < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[pci] Could not add GART texture map mapping\n");
return FALSE;
}
xf86DrvMsg(pScreen->myNum, X_INFO,
"[pci] GART texture map handle = 0x%08x\n",
- info->gartTexHandle);
+ info->dri->gartTexHandle);
- if (drmMap(info->drmFD, info->gartTexHandle, info->gartTexMapSize,
- &info->gartTex) < 0) {
+ if (drmMap(info->dri->drmFD, info->dri->gartTexHandle, info->dri->gartTexMapSize,
+ &info->dri->gartTex) < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[pci] Could not map GART texture map\n");
return FALSE;
}
xf86DrvMsg(pScreen->myNum, X_INFO,
"[pci] GART Texture map mapped at 0x%08lx\n",
- (unsigned long)info->gartTex);
+ (unsigned long)info->dri->gartTex);
return TRUE;
}
@@ -1074,13 +1074,13 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen)
static Bool RADEONDRIMapInit(RADEONInfoPtr info, ScreenPtr pScreen)
{
/* Map registers */
- info->registerSize = info->MMIOSize;
- if (drmAddMap(info->drmFD, info->MMIOAddr, info->registerSize,
- DRM_REGISTERS, DRM_READ_ONLY, &info->registerHandle) < 0) {
+ info->dri->registerSize = info->MMIOSize;
+ if (drmAddMap(info->dri->drmFD, info->MMIOAddr, info->dri->registerSize,
+ DRM_REGISTERS, DRM_READ_ONLY, &info->dri->registerHandle) < 0) {
return FALSE;
}
xf86DrvMsg(pScreen->myNum, X_INFO,
- "[drm] register handle = 0x%08x\n", info->registerHandle);
+ "[drm] register handle = 0x%08x\n", info->dri->registerHandle);
return TRUE;
}
@@ -1104,28 +1104,28 @@ static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen)
drmInfo.sarea_priv_offset = sizeof(XF86DRISAREARec);
drmInfo.is_pci = (info->cardType!=CARD_AGP);
drmInfo.cp_mode = RADEON_CSQ_PRIBM_INDBM;
- drmInfo.gart_size = info->gartSize*1024*1024;
- drmInfo.ring_size = info->ringSize*1024*1024;
+ drmInfo.gart_size = info->dri->gartSize*1024*1024;
+ drmInfo.ring_size = info->dri->ringSize*1024*1024;
drmInfo.usec_timeout = info->cp->CPusecTimeout;
drmInfo.fb_bpp = info->CurrentLayout.pixel_code;
- drmInfo.depth_bpp = (info->depthBits - 8) * 2;
-
- drmInfo.front_offset = info->frontOffset;
- drmInfo.front_pitch = info->frontPitch * cpp;
- drmInfo.back_offset = info->backOffset;
- drmInfo.back_pitch = info->backPitch * cpp;
- drmInfo.depth_offset = info->depthOffset;
- drmInfo.depth_pitch = info->depthPitch * drmInfo.depth_bpp / 8;
-
- drmInfo.fb_offset = info->fbHandle;
- drmInfo.mmio_offset = info->registerHandle;
- drmInfo.ring_offset = info->ringHandle;
- drmInfo.ring_rptr_offset = info->ringReadPtrHandle;
- drmInfo.buffers_offset = info->bufHandle;
- drmInfo.gart_textures_offset= info->gartTexHandle;
-
- if (drmCommandWrite(info->drmFD, DRM_RADEON_CP_INIT,
+ drmInfo.depth_bpp = (info->dri->depthBits - 8) * 2;
+
+ drmInfo.front_offset = info->dri->frontOffset;
+ drmInfo.front_pitch = info->dri->frontPitch * cpp;
+ drmInfo.back_offset = info->dri->backOffset;
+ drmInfo.back_pitch = info->dri->backPitch * cpp;
+ drmInfo.depth_offset = info->dri->depthOffset;
+ drmInfo.depth_pitch = info->dri->depthPitch * drmInfo.depth_bpp / 8;
+
+ drmInfo.fb_offset = info->dri->fbHandle;
+ drmInfo.mmio_offset = info->dri->registerHandle;
+ drmInfo.ring_offset = info->dri->ringHandle;
+ drmInfo.ring_rptr_offset = info->dri->ringReadPtrHandle;
+ drmInfo.buffers_offset = info->dri->bufHandle;
+ drmInfo.gart_textures_offset= info->dri->gartTexHandle;
+
+ if (drmCommandWrite(info->dri->drmFD, DRM_RADEON_CP_INIT,
&drmInfo, sizeof(drmRadeonInit)) < 0)
return FALSE;
@@ -1145,16 +1145,16 @@ static void RADEONDRIGartHeapInit(RADEONInfoPtr info, ScreenPtr pScreen)
/* Start up the simple memory manager for GART space */
drmHeap.region = RADEON_MEM_REGION_GART;
drmHeap.start = 0;
- drmHeap.size = info->gartTexMapSize;
+ drmHeap.size = info->dri->gartTexMapSize;
- if (drmCommandWrite(info->drmFD, DRM_RADEON_INIT_HEAP,
+ if (drmCommandWrite(info->dri->drmFD, DRM_RADEON_INIT_HEAP,
&drmHeap, sizeof(drmHeap))) {
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[drm] Failed to initialize GART heap manager\n");
} else {
xf86DrvMsg(pScreen->myNum, X_INFO,
"[drm] Initialized kernel GART heap manager, %d\n",
- info->gartTexMapSize);
+ info->dri->gartTexMapSize);
}
}
@@ -1164,29 +1164,29 @@ static void RADEONDRIGartHeapInit(RADEONInfoPtr info, ScreenPtr pScreen)
static Bool RADEONDRIBufInit(RADEONInfoPtr info, ScreenPtr pScreen)
{
/* Initialize vertex buffers */
- info->bufNumBufs = drmAddBufs(info->drmFD,
- info->bufMapSize / RADEON_BUFFER_SIZE,
- RADEON_BUFFER_SIZE,
- (info->cardType!=CARD_AGP) ? DRM_SG_BUFFER : DRM_AGP_BUFFER,
- info->bufStart);
+ info->dri->bufNumBufs = drmAddBufs(info->dri->drmFD,
+ info->dri->bufMapSize / RADEON_BUFFER_SIZE,
+ RADEON_BUFFER_SIZE,
+ (info->cardType!=CARD_AGP) ? DRM_SG_BUFFER : DRM_AGP_BUFFER,
+ info->dri->bufStart);
- if (info->bufNumBufs <= 0) {
+ if (info->dri->bufNumBufs <= 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[drm] Could not create vertex/indirect buffers list\n");
return FALSE;
}
xf86DrvMsg(pScreen->myNum, X_INFO,
"[drm] Added %d %d byte vertex/indirect buffers\n",
- info->bufNumBufs, RADEON_BUFFER_SIZE);
+ info->dri->bufNumBufs, RADEON_BUFFER_SIZE);
- if (!(info->buffers = drmMapBufs(info->drmFD))) {
+ if (!(info->dri->buffers = drmMapBufs(info->dri->drmFD))) {
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[drm] Failed to map vertex/indirect buffers list\n");
return FALSE;
}
xf86DrvMsg(pScreen->myNum, X_INFO,
"[drm] Mapped %d vertex/indirect buffers\n",
- info->buffers->count);
+ info->dri->buffers->count);
return TRUE;
}
@@ -1195,19 +1195,19 @@ static void RADEONDRIIrqInit(RADEONInfoPtr info, ScreenPtr pScreen)
{
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- if (!info->irq) {
- info->irq = drmGetInterruptFromBusID(
- info->drmFD,
+ if (!info->dri->irq) {
+ info->dri->irq = drmGetInterruptFromBusID(
+ info->dri->drmFD,
PCI_CFG_BUS(info->PciInfo),
PCI_CFG_DEV(info->PciInfo),
PCI_CFG_FUNC(info->PciInfo));
- if ((drmCtlInstHandler(info->drmFD, info->irq)) != 0) {
+ if ((drmCtlInstHandler(info->dri->drmFD, info->dri->irq)) != 0) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"[drm] failure adding irq handler, "
"there is a device already using that irq\n"
"[drm] falling back to irq-free operation\n");
- info->irq = 0;
+ info->dri->irq = 0;
} else {
unsigned char *RADEONMMIO = info->MMIO;
info->ModeReg->gen_int_cntl = INREG( RADEON_GEN_INT_CNTL );
@@ -1220,10 +1220,10 @@ static void RADEONDRIIrqInit(RADEONInfoPtr info, ScreenPtr pScreen)
}
}
- if (info->irq)
+ if (info->dri->irq)
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"[drm] dma control initialized, using IRQ %d\n",
- info->irq);
+ info->dri->irq);
}
@@ -1239,7 +1239,7 @@ static void RADEONDRICPInit(ScrnInfoPtr pScrn)
RADEONCP_START(pScrn, info);
#ifdef USE_XAA
if (!info->useEXA)
- info->accel_state->dst_pitch_offset = info->frontPitchOffset;
+ info->accel_state->dst_pitch_offset = info->dri->frontPitchOffset;
#endif
}
@@ -1280,16 +1280,16 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn)
/* Check the lib version */
if (xf86LoaderCheckSymbol("drmGetLibVersion"))
- info->pLibDRMVersion = drmGetLibVersion(info->drmFD);
- if (info->pLibDRMVersion == NULL) {
+ info->dri->pLibDRMVersion = drmGetLibVersion(info->dri->drmFD);
+ if (info->dri->pLibDRMVersion == NULL) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"[dri] RADEONDRIGetVersion failed because libDRM is really "
"way to old to even get a version number out of it.\n"
"[dri] Disabling DRI.\n");
return FALSE;
}
- if (info->pLibDRMVersion->version_major != 1 ||
- info->pLibDRMVersion->version_minor < 2) {
+ if (info->dri->pLibDRMVersion->version_major != 1 ||
+ info->dri->pLibDRMVersion->version_minor < 2) {
/* incompatible drm library version */
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"[dri] RADEONDRIGetVersion failed because of a "
@@ -1297,11 +1297,11 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn)
"[dri] libdrm.a module version is %d.%d.%d but "
"version 1.2.x is needed.\n"
"[dri] Disabling DRI.\n",
- info->pLibDRMVersion->version_major,
- info->pLibDRMVersion->version_minor,
- info->pLibDRMVersion->version_patchlevel);
- drmFreeVersion(info->pLibDRMVersion);
- info->pLibDRMVersion = NULL;
+ info->dri->pLibDRMVersion->version_major,
+ info->dri->pLibDRMVersion->version_minor,
+ info->dri->pLibDRMVersion->version_patchlevel);
+ drmFreeVersion(info->dri->pLibDRMVersion);
+ info->dri->pLibDRMVersion = NULL;
return FALSE;
}
@@ -1328,9 +1328,9 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn)
}
/* Get DRM version & close DRM */
- info->pKernelDRMVersion = drmGetVersion(fd);
+ info->dri->pKernelDRMVersion = drmGetVersion(fd);
drmClose(fd);
- if (info->pKernelDRMVersion == NULL) {
+ if (info->dri->pKernelDRMVersion == NULL) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"[dri] RADEONDRIGetVersion failed to get the DRM version\n"
"[dri] Disabling DRI.\n");
@@ -1350,10 +1350,10 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn)
}
/* We don't, bummer ! */
- if (info->pKernelDRMVersion->version_major != 1 ||
- info->pKernelDRMVersion->version_minor < req_minor ||
- (info->pKernelDRMVersion->version_minor == req_minor &&
- info->pKernelDRMVersion->version_patchlevel < req_patch)) {
+ if (info->dri->pKernelDRMVersion->version_major != 1 ||
+ info->dri->pKernelDRMVersion->version_minor < req_minor ||
+ (info->dri->pKernelDRMVersion->version_minor == req_minor &&
+ info->dri->pKernelDRMVersion->version_patchlevel < req_patch)) {
/* Incompatible drm version */
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"[dri] RADEONDRIGetVersion failed because of a version "
@@ -1361,13 +1361,13 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn)
"[dri] radeon.o kernel module version is %d.%d.%d "
"but version 1.%d.%d or newer is needed.\n"
"[dri] Disabling DRI.\n",
- info->pKernelDRMVersion->version_major,
- info->pKernelDRMVersion->version_minor,
- info->pKernelDRMVersion->version_patchlevel,
+ info->dri->pKernelDRMVersion->version_major,
+ info->dri->pKernelDRMVersion->version_minor,
+ info->dri->pKernelDRMVersion->version_patchlevel,
req_minor,
req_patch);
- drmFreeVersion(info->pKernelDRMVersion);
- info->pKernelDRMVersion = NULL;
+ drmFreeVersion(info->dri->pKernelDRMVersion);
+ info->dri->pKernelDRMVersion = NULL;
return FALSE;
}
@@ -1383,7 +1383,7 @@ Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on)
if (!info->want_vblank_interrupts)
on = FALSE;
- if (info->directRenderingEnabled && info->pKernelDRMVersion->version_minor >= 28) {
+ if (info->directRenderingEnabled && info->dri->pKernelDRMVersion->version_minor >= 28) {
if (on) {
if (xf86_config->num_crtc > 1 && xf86_config->crtc[1]->enabled)
value = DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2;
@@ -1412,7 +1412,7 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen)
DRIInfoPtr pDRIInfo;
RADEONDRIPtr pRADEONDRI;
- info->DRICloseScreen = NULL;
+ info->dri->DRICloseScreen = NULL;
switch (info->CurrentLayout.pixel_code) {
case 8:
@@ -1438,7 +1438,7 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen)
*/
if (!(pDRIInfo = DRICreateInfoRec())) return FALSE;
- info->pDRIInfo = pDRIInfo;
+ info->dri->pDRIInfo = pDRIInfo;
pDRIInfo->drmDriverName = RADEON_DRIVER_NAME;
if ( (info->ChipFamily >= CHIP_FAMILY_R300) ) {
@@ -1462,7 +1462,7 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen)
pDRIInfo->ddxDriverMajorVersion = info->allowColorTiling ? 5 : 4;
pDRIInfo->ddxDriverMinorVersion = 3;
pDRIInfo->ddxDriverPatchVersion = 0;
- pDRIInfo->frameBufferPhysicalAddress = (void *)info->LinearAddr + info->frontOffset;
+ pDRIInfo->frameBufferPhysicalAddress = (void *)info->LinearAddr + info->dri->frontOffset;
pDRIInfo->frameBufferSize = info->FbMapSize - info->FbSecureSize;
pDRIInfo->frameBufferStride = (pScrn->displayWidth *
info->CurrentLayout.pixel_bytes);
@@ -1500,8 +1500,8 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen)
#endif
if (!(pRADEONDRI = (RADEONDRIPtr)xcalloc(sizeof(RADEONDRIRec),1))) {
- DRIDestroyInfoRec(info->pDRIInfo);
- info->pDRIInfo = NULL;
+ DRIDestroyInfoRec(info->dri->pDRIInfo);
+ info->dri->pDRIInfo = NULL;
return FALSE;
}
pDRIInfo->devPrivate = pRADEONDRI;
@@ -1543,7 +1543,7 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen)
}
#endif
- if (!DRIScreenInit(pScreen, pDRIInfo, &info->drmFD)) {
+ if (!DRIScreenInit(pScreen, pDRIInfo, &info->dri->drmFD)) {
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[dri] DRIScreenInit failed. Disabling DRI.\n");
xfree(pDRIInfo->devPrivate);
@@ -1586,7 +1586,7 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen)
void *scratch_ptr;
int scratch_int;
- DRIGetDeviceInfo(pScreen, &info->fbHandle,
+ DRIGetDeviceInfo(pScreen, &info->dri->fbHandle,
&scratch_int, &scratch_int,
&scratch_int, &scratch_int,
&scratch_ptr);
@@ -1610,7 +1610,7 @@ static Bool RADEONDRIDoCloseScreen(int scrnIndex, ScreenPtr pScreen)
RADEONDRICloseScreen(pScreen);
- pScreen->CloseScreen = info->DRICloseScreen;
+ pScreen->CloseScreen = info->dri->DRICloseScreen;
return (*pScreen->CloseScreen)(scrnIndex, pScreen);
}
@@ -1625,8 +1625,8 @@ Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen)
RADEONSAREAPrivPtr pSAREAPriv;
RADEONDRIPtr pRADEONDRI;
- info->pDRIInfo->driverSwapMethod = DRI_HIDE_X_CONTEXT;
- /* info->pDRIInfo->driverSwapMethod = DRI_SERVER_SWAP; */
+ info->dri->pDRIInfo->driverSwapMethod = DRI_HIDE_X_CONTEXT;
+ /* info->dri->pDRIInfo->driverSwapMethod = DRI_SERVER_SWAP; */
/* NOTE: DRIFinishScreenInit must be called before *DRIKernelInit
* because *DRIKernelInit requires that the hardware lock is held by
@@ -1663,7 +1663,7 @@ Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen)
pSAREAPriv = (RADEONSAREAPrivPtr)DRIGetSAREAPrivate(pScreen);
memset(pSAREAPriv, 0, sizeof(*pSAREAPriv));
- pRADEONDRI = (RADEONDRIPtr)info->pDRIInfo->devPrivate;
+ pRADEONDRI = (RADEONDRIPtr)info->dri->pDRIInfo->devPrivate;
pRADEONDRI->deviceID = info->Chipset;
pRADEONDRI->width = pScrn->virtualX;
@@ -1672,40 +1672,40 @@ Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen)
pRADEONDRI->bpp = pScrn->bitsPerPixel;
pRADEONDRI->IsPCI = (info->cardType!=CARD_AGP);
- pRADEONDRI->AGPMode = info->agpMode;
+ pRADEONDRI->AGPMode = info->dri->agpMode;
- pRADEONDRI->frontOffset = info->frontOffset;
- pRADEONDRI->frontPitch = info->frontPitch;
- pRADEONDRI->backOffset = info->backOffset;
- pRADEONDRI->backPitch = info->backPitch;
- pRADEONDRI->depthOffset = info->depthOffset;
- pRADEONDRI->depthPitch = info->depthPitch;
- pRADEONDRI->textureOffset = info->textureOffset;
- pRADEONDRI->textureSize = info->textureSize;
- pRADEONDRI->log2TexGran = info->log2TexGran;
+ pRADEONDRI->frontOffset = info->dri->frontOffset;
+ pRADEONDRI->frontPitch = info->dri->frontPitch;
+ pRADEONDRI->backOffset = info->dri->backOffset;
+ pRADEONDRI->backPitch = info->dri->backPitch;
+ pRADEONDRI->depthOffset = info->dri->depthOffset;
+ pRADEONDRI->depthPitch = info->dri->depthPitch;
+ pRADEONDRI->textureOffset = info->dri->textureOffset;
+ pRADEONDRI->textureSize = info->dri->textureSize;
+ pRADEONDRI->log2TexGran = info->dri->log2TexGran;
- pRADEONDRI->registerHandle = info->registerHandle;
- pRADEONDRI->registerSize = info->registerSize;
+ pRADEONDRI->registerHandle = info->dri->registerHandle;
+ pRADEONDRI->registerSize = info->dri->registerSize;
- pRADEONDRI->statusHandle = info->ringReadPtrHandle;
- pRADEONDRI->statusSize = info->ringReadMapSize;
+ pRADEONDRI->statusHandle = info->dri->ringReadPtrHandle;
+ pRADEONDRI->statusSize = info->dri->ringReadMapSize;
- pRADEONDRI->gartTexHandle = info->gartTexHandle;
- pRADEONDRI->gartTexMapSize = info->gartTexMapSize;
- pRADEONDRI->log2GARTTexGran = info->log2GARTTexGran;
- pRADEONDRI->gartTexOffset = info->gartTexStart;
+ pRADEONDRI->gartTexHandle = info->dri->gartTexHandle;
+ pRADEONDRI->gartTexMapSize = info->dri->gartTexMapSize;
+ pRADEONDRI->log2GARTTexGran = info->dri->log2GARTTexGran;
+ pRADEONDRI->gartTexOffset = info->dri->gartTexStart;
pRADEONDRI->sarea_priv_offset = sizeof(XF86DRISAREARec);
#ifdef PER_CONTEXT_SAREA
/* Set per-context SAREA size */
- pRADEONDRI->perctx_sarea_size = info->perctx_sarea_size;
+ pRADEONDRI->perctx_sarea_size = info->dri->perctx_sarea_size;
#endif
info->directRenderingInited = TRUE;
/* Wrap CloseScreen */
- info->DRICloseScreen = pScreen->CloseScreen;
+ info->dri->DRICloseScreen = pScreen->CloseScreen;
pScreen->CloseScreen = RADEONDRIDoCloseScreen;
/* disable vblank at startup */
@@ -1726,7 +1726,7 @@ void RADEONDRIResume(ScreenPtr pScreen)
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
RADEONInfoPtr info = RADEONPTR(pScrn);
- if (info->pKernelDRMVersion->version_minor >= 9) {
+ if (info->dri->pKernelDRMVersion->version_minor >= 9) {
xf86DrvMsg(pScreen->myNum, X_INFO,
"[RESUME] Attempting to re-init Radeon hardware.\n");
} else {
@@ -1743,7 +1743,7 @@ void RADEONDRIResume(ScreenPtr pScreen)
RADEONSetAgpBase(info, pScreen);
}
- _ret = drmCommandNone(info->drmFD, DRM_RADEON_CP_RESUME);
+ _ret = drmCommandNone(info->dri->drmFD, DRM_RADEON_CP_RESUME);
if (_ret) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"%s: CP resume %d\n", __FUNCTION__, _ret);
@@ -1788,80 +1788,80 @@ void RADEONDRICloseScreen(ScreenPtr pScreen)
"RADEONDRICloseScreen\n");
#ifdef DAMAGE
- REGION_UNINIT(pScreen, &info->driRegion);
+ REGION_UNINIT(pScreen, &info->dri->driRegion);
#endif
- if (info->irq) {
+ if (info->dri->irq) {
RADEONDRISetVBlankInterrupt (pScrn, FALSE);
- drmCtlUninstHandler(info->drmFD);
- info->irq = 0;
+ drmCtlUninstHandler(info->dri->drmFD);
+ info->dri->irq = 0;
info->ModeReg->gen_int_cntl = 0;
}
/* De-allocate vertex buffers */
- if (info->buffers) {
- drmUnmapBufs(info->buffers);
- info->buffers = NULL;
+ if (info->dri->buffers) {
+ drmUnmapBufs(info->dri->buffers);
+ info->dri->buffers = NULL;
}
/* De-allocate all kernel resources */
memset(&drmInfo, 0, sizeof(drmRadeonInit));
drmInfo.func = DRM_RADEON_CLEANUP_CP;
- drmCommandWrite(info->drmFD, DRM_RADEON_CP_INIT,
+ drmCommandWrite(info->dri->drmFD, DRM_RADEON_CP_INIT,
&drmInfo, sizeof(drmRadeonInit));
/* De-allocate all GART resources */
- if (info->gartTex) {
- drmUnmap(info->gartTex, info->gartTexMapSize);
- info->gartTex = NULL;
+ if (info->dri->gartTex) {
+ drmUnmap(info->dri->gartTex, info->dri->gartTexMapSize);
+ info->dri->gartTex = NULL;
}
- if (info->buf) {
- drmUnmap(info->buf, info->bufMapSize);
- info->buf = NULL;
+ if (info->dri->buf) {
+ drmUnmap(info->dri->buf, info->dri->bufMapSize);
+ info->dri->buf = NULL;
}
- if (info->ringReadPtr) {
- drmUnmap(info->ringReadPtr, info->ringReadMapSize);
- info->ringReadPtr = NULL;
+ if (info->dri->ringReadPtr) {
+ drmUnmap(info->dri->ringReadPtr, info->dri->ringReadMapSize);
+ info->dri->ringReadPtr = NULL;
}
- if (info->ring) {
- drmUnmap(info->ring, info->ringMapSize);
- info->ring = NULL;
+ if (info->dri->ring) {
+ drmUnmap(info->dri->ring, info->dri->ringMapSize);
+ info->dri->ring = NULL;
}
- if (info->agpMemHandle != DRM_AGP_NO_HANDLE) {
- drmAgpUnbind(info->drmFD, info->agpMemHandle);
- drmAgpFree(info->drmFD, info->agpMemHandle);
- info->agpMemHandle = DRM_AGP_NO_HANDLE;
- drmAgpRelease(info->drmFD);
+ if (info->dri->agpMemHandle != DRM_AGP_NO_HANDLE) {
+ drmAgpUnbind(info->dri->drmFD, info->dri->agpMemHandle);
+ drmAgpFree(info->dri->drmFD, info->dri->agpMemHandle);
+ info->dri->agpMemHandle = DRM_AGP_NO_HANDLE;
+ drmAgpRelease(info->dri->drmFD);
}
- if (info->pciMemHandle) {
- drmScatterGatherFree(info->drmFD, info->pciMemHandle);
- info->pciMemHandle = 0;
+ if (info->dri->pciMemHandle) {
+ drmScatterGatherFree(info->dri->drmFD, info->dri->pciMemHandle);
+ info->dri->pciMemHandle = 0;
}
- if (info->pciGartBackup) {
- xfree(info->pciGartBackup);
- info->pciGartBackup = NULL;
+ if (info->dri->pciGartBackup) {
+ xfree(info->dri->pciGartBackup);
+ info->dri->pciGartBackup = NULL;
}
/* De-allocate all DRI resources */
DRICloseScreen(pScreen);
/* De-allocate all DRI data structures */
- if (info->pDRIInfo) {
- if (info->pDRIInfo->devPrivate) {
- xfree(info->pDRIInfo->devPrivate);
- info->pDRIInfo->devPrivate = NULL;
+ if (info->dri->pDRIInfo) {
+ if (info->dri->pDRIInfo->devPrivate) {
+ xfree(info->dri->pDRIInfo->devPrivate);
+ info->dri->pDRIInfo->devPrivate = NULL;
}
- DRIDestroyInfoRec(info->pDRIInfo);
- info->pDRIInfo = NULL;
+ DRIDestroyInfoRec(info->dri->pDRIInfo);
+ info->dri->pDRIInfo = NULL;
}
- if (info->pVisualConfigs) {
- xfree(info->pVisualConfigs);
- info->pVisualConfigs = NULL;
+ if (info->dri->pVisualConfigs) {
+ xfree(info->dri->pVisualConfigs);
+ info->dri->pVisualConfigs = NULL;
}
- if (info->pVisualConfigsPriv) {
- xfree(info->pVisualConfigsPriv);
- info->pVisualConfigsPriv = NULL;
+ if (info->dri->pVisualConfigsPriv) {
+ xfree(info->dri->pVisualConfigsPriv);
+ info->dri->pVisualConfigsPriv = NULL;
}
}
@@ -1907,7 +1907,7 @@ static void RADEONDRIRefreshArea(ScrnInfoPtr pScrn, RegionPtr pReg)
return;
REGION_NULL(pScreen, &region);
- REGION_SUBTRACT(pScreen, &region, pReg, &info->driRegion);
+ REGION_SUBTRACT(pScreen, &region, pReg, &info->dri->driRegion);
num = REGION_NUM_RECTS(&region);
@@ -1924,7 +1924,7 @@ static void RADEONDRIRefreshArea(ScrnInfoPtr pScrn, RegionPtr pReg)
uint32_t src_pitch_offset, dst_pitch_offset, datatype;
RADEONGetPixmapOffsetPitch(pPix, &src_pitch_offset);
- dst_pitch_offset = src_pitch_offset + (info->backOffset >> 10);
+ dst_pitch_offset = src_pitch_offset + (info->dri->backOffset >> 10);
RADEONGetDatatypeBpp(pScrn->bitsPerPixel, &datatype);
info->accel_state->xdir = info->accel_state->ydir = 1;
@@ -1961,8 +1961,8 @@ static void RADEONDRIRefreshArea(ScrnInfoPtr pScrn, RegionPtr pReg)
#ifdef USE_XAA
if (!info->useEXA) {
(*info->accel_state->accel->SubsequentScreenToScreenCopy)(pScrn, xa, ya,
- xa + info->backX,
- ya + info->backY,
+ xa + info->dri->backX,
+ ya + info->dri->backY,
xb - xa + 1,
yb - ya + 1);
}
@@ -1976,7 +1976,7 @@ static void RADEONDRIRefreshArea(ScrnInfoPtr pScrn, RegionPtr pReg)
out:
REGION_NULL(pScreen, &region);
- DamageEmpty(info->pDamage);
+ DamageEmpty(info->dri->pDamage);
}
#endif /* DAMAGE */
@@ -1987,7 +1987,7 @@ static void RADEONEnablePageFlip(ScreenPtr pScreen)
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
RADEONInfoPtr info = RADEONPTR(pScrn);
- if (info->allowPageFlip) {
+ if (info->dri->allowPageFlip) {
RADEONSAREAPrivPtr pSAREAPriv = DRIGetSAREAPrivate(pScreen);
BoxRec box = { .x1 = 0, .y1 = 0, .x2 = pScrn->virtualX - 1,
.y2 = pScrn->virtualY - 1 };
@@ -2040,9 +2040,9 @@ static void RADEONDRITransitionTo3d(ScreenPtr pScreen)
* first so we always start with all free offscreen memory, except
* maybe for Xv
*/
- if (info->backArea) {
- xf86FreeOffscreenArea(info->backArea);
- info->backArea = NULL;
+ if (info->dri->backArea) {
+ xf86FreeOffscreenArea(info->dri->backArea);
+ info->dri->backArea = NULL;
}
xf86PurgeUnlockedOffscreenAreas(pScreen);
@@ -2053,7 +2053,7 @@ static void RADEONDRITransitionTo3d(ScreenPtr pScreen)
* FIXME: This is hideous. What about telling xv "oh btw you have no memory
* any more?" -- anholt
*/
- if (height < (info->depthTexLines + info->backLines)) {
+ if (height < (info->dri->depthTexLines + info->dri->backLines)) {
RADEONPortPrivPtr portPriv = info->adaptor->pPortPrivates[0].ptr;
xf86FreeOffscreenLinear((FBLinearPtr)portPriv->video_memory);
portPriv->video_memory = NULL;
@@ -2067,29 +2067,29 @@ static void RADEONDRITransitionTo3d(ScreenPtr pScreen)
*/
fbarea = xf86AllocateOffscreenArea(pScreen, pScrn->displayWidth,
height
- - info->depthTexLines
- - info->backLines,
+ - info->dri->depthTexLines
+ - info->dri->backLines,
pScrn->displayWidth,
NULL, NULL, NULL);
if (!fbarea)
xf86DrvMsg(pScreen->myNum, X_ERROR, "Unable to reserve placeholder "
"offscreen area, you might experience screen corruption\n");
- info->backArea = xf86AllocateOffscreenArea(pScreen, pScrn->displayWidth,
- info->backLines,
- pScrn->displayWidth,
- NULL, NULL, NULL);
- if (!info->backArea)
+ info->dri->backArea = xf86AllocateOffscreenArea(pScreen, pScrn->displayWidth,
+ info->dri->backLines,
+ pScrn->displayWidth,
+ NULL, NULL, NULL);
+ if (!info->dri->backArea)
xf86DrvMsg(pScreen->myNum, X_ERROR, "Unable to reserve offscreen "
"area for back buffer, you might experience screen "
"corruption\n");
- info->depthTexArea = xf86AllocateOffscreenArea(pScreen,
- pScrn->displayWidth,
- info->depthTexLines,
- pScrn->displayWidth,
- NULL, NULL, NULL);
- if (!info->depthTexArea)
+ info->dri->depthTexArea = xf86AllocateOffscreenArea(pScreen,
+ pScrn->displayWidth,
+ info->dri->depthTexLines,
+ pScrn->displayWidth,
+ NULL, NULL, NULL);
+ if (!info->dri->depthTexArea)
xf86DrvMsg(pScreen->myNum, X_ERROR, "Unable to reserve offscreen "
"area for depth buffer and textures, you might "
"experience screen corruption\n");
@@ -2098,7 +2098,7 @@ static void RADEONDRITransitionTo3d(ScreenPtr pScreen)
}
#endif /* USE_XAA */
- info->have3DWindows = 1;
+ info->dri->have3DWindows = 1;
RADEONChangeSurfaces(pScrn);
RADEONEnablePageFlip(pScreen);
@@ -2118,15 +2118,15 @@ static void RADEONDRITransitionTo2d(ScreenPtr pScreen)
/* Try flipping back to the front page if necessary */
if (pSAREAPriv->pfCurrentPage == 1)
- drmCommandNone(info->drmFD, DRM_RADEON_FLIP);
+ drmCommandNone(info->dri->drmFD, DRM_RADEON_FLIP);
/* Shut down shadowing if we've made it back to the front page */
if (pSAREAPriv->pfCurrentPage == 0) {
RADEONDisablePageFlip(pScreen);
#ifdef USE_XAA
if (!info->useEXA) {
- xf86FreeOffscreenArea(info->backArea);
- info->backArea = NULL;
+ xf86FreeOffscreenArea(info->dri->backArea);
+ info->dri->backArea = NULL;
}
#endif
} else {
@@ -2137,10 +2137,10 @@ static void RADEONDRITransitionTo2d(ScreenPtr pScreen)
#ifdef USE_XAA
if (!info->useEXA)
- xf86FreeOffscreenArea(info->depthTexArea);
+ xf86FreeOffscreenArea(info->dri->depthTexArea);
#endif
- info->have3DWindows = 0;
+ info->dri->have3DWindows = 0;
RADEONChangeSurfaces(pScrn);
@@ -2160,8 +2160,8 @@ RADEONDRIClipNotify(ScreenPtr pScreen, WindowPtr *ppWin, int num)
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
RADEONInfoPtr info = RADEONPTR(pScrn);
- REGION_UNINIT(pScreen, &info->driRegion);
- REGION_NULL(pScreen, &info->driRegion);
+ REGION_UNINIT(pScreen, &info->dri->driRegion);
+ REGION_NULL(pScreen, &info->dri->driRegion);
if (num > 0) {
int i;
@@ -2170,8 +2170,8 @@ RADEONDRIClipNotify(ScreenPtr pScreen, WindowPtr *ppWin, int num)
WindowPtr pWin = ppWin[i];
if (pWin) {
- REGION_UNION(pScreen, &info->driRegion, &pWin->clipList,
- &info->driRegion);
+ REGION_UNION(pScreen, &info->dri->driRegion, &pWin->clipList,
+ &info->dri->driRegion);
}
}
}
@@ -2184,24 +2184,24 @@ void RADEONDRIAllocatePCIGARTTable(ScreenPtr pScreen)
RADEONInfoPtr info = RADEONPTR(pScrn);
if (info->cardType != CARD_PCIE ||
- info->pKernelDRMVersion->version_minor < 19)
+ info->dri->pKernelDRMVersion->version_minor < 19)
return;
if (info->FbSecureSize==0)
return;
/* set the old default size of pci gart table */
- if (info->pKernelDRMVersion->version_minor < 26)
- info->pciGartSize = 32768;
+ if (info->dri->pKernelDRMVersion->version_minor < 26)
+ info->dri->pciGartSize = 32768;
- info->pciGartSize = RADEONDRIGetPciAperTableSize(pScrn);
+ info->dri->pciGartSize = RADEONDRIGetPciAperTableSize(pScrn);
/* allocate space to back up PCIEGART table */
- info->pciGartBackup = xnfcalloc(1, info->pciGartSize);
- if (info->pciGartBackup == NULL)
+ info->dri->pciGartBackup = xnfcalloc(1, info->dri->pciGartSize);
+ if (info->dri->pciGartBackup == NULL)
return;
- info->pciGartOffset = (info->FbMapSize - info->FbSecureSize);
+ info->dri->pciGartOffset = (info->FbMapSize - info->FbSecureSize);
}
@@ -2213,7 +2213,7 @@ int RADEONDRIGetPciAperTableSize(ScrnInfoPtr pScrn)
int ret_size;
int num_pages;
- num_pages = (info->pciAperSize * 1024 * 1024) / page_size;
+ num_pages = (info->dri->pciAperSize * 1024 * 1024) / page_size;
ret_size = num_pages * sizeof(unsigned int);
@@ -2229,7 +2229,7 @@ int RADEONDRISetParam(ScrnInfoPtr pScrn, unsigned int param, int64_t value)
memset(&radeonsetparam, 0, sizeof(drmRadeonSetParam));
radeonsetparam.param = param;
radeonsetparam.value = value;
- ret = drmCommandWrite(info->drmFD, DRM_RADEON_SETPARAM,
+ ret = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SETPARAM,
&radeonsetparam, sizeof(drmRadeonSetParam));
return ret;
}
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index d485865f..9dd420ef 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -1284,7 +1284,7 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn)
#ifdef XF86DRI
/* Apply memory map limitation if using an old DRI */
- if (info->directRenderingEnabled && !info->newMemoryMap) {
+ if (info->directRenderingEnabled && !info->dri->newMemoryMap) {
if (aper_size < mem_size)
mem_size = aper_size;
}
@@ -1299,7 +1299,7 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn)
#ifdef XF86DRI
/* Old DRI has restrictions on the memory map */
if ( info->directRenderingEnabled &&
- info->pKernelDRMVersion->version_minor < 10 )
+ info->dri->pKernelDRMVersion->version_minor < 10 )
info->mc_fb_location = (mem_size - 1) & 0xffff0000U;
else
#endif
@@ -1487,18 +1487,18 @@ static uint32_t RADEONGetAccessibleVRAM(ScrnInfoPtr pScrn)
* we need to limit the amount of accessible video memory
*/
if (info->directRenderingEnabled &&
- info->pKernelDRMVersion->version_minor < 23) {
+ info->dri->pKernelDRMVersion->version_minor < 23) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"[dri] limiting video memory to one aperture of %uK\n",
(unsigned)aper_size);
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"[dri] detected radeon kernel module version 1.%d but"
" 1.23 or newer is required for full memory mapping.\n",
- info->pKernelDRMVersion->version_minor);
- info->newMemoryMap = FALSE;
+ info->dri->pKernelDRMVersion->version_minor);
+ info->dri->newMemoryMap = FALSE;
return aper_size;
}
- info->newMemoryMap = TRUE;
+ info->dri->newMemoryMap = TRUE;
#endif /* XF86DRI */
/* Set HDP_APER_CNTL only on cards that are known not to be broken,
@@ -2111,8 +2111,11 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn)
info->directRenderingEnabled = FALSE;
info->directRenderingInited = FALSE;
- info->pLibDRMVersion = NULL;
- info->pKernelDRMVersion = NULL;
+
+ if (!(info->dri = xcalloc(1, sizeof(struct radeon_dri)))) {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Unable to allocate dri rec!\n");
+ return FALSE;
+ }
if (!(info->cp = xcalloc(1, sizeof(struct radeon_cp)))) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Unable to allocate cp rec!\n");
@@ -2163,18 +2166,26 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn)
return FALSE;
}
+ if (!(info->dri = xcalloc(1, sizeof(struct radeon_dri)))) {
+ ErrorF("Unable to allocate dri rec!\n");
+ return FALSE;
+ }
+
+ info->dri->pLibDRMVersion = NULL;
+ info->dri->pKernelDRMVersion = NULL;
+
if (!RADEONDRIGetVersion(pScrn))
return FALSE;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"[dri] Found DRI library version %d.%d.%d and kernel"
" module version %d.%d.%d\n",
- info->pLibDRMVersion->version_major,
- info->pLibDRMVersion->version_minor,
- info->pLibDRMVersion->version_patchlevel,
- info->pKernelDRMVersion->version_major,
- info->pKernelDRMVersion->version_minor,
- info->pKernelDRMVersion->version_patchlevel);
+ info->dri->pLibDRMVersion->version_major,
+ info->dri->pLibDRMVersion->version_minor,
+ info->dri->pLibDRMVersion->version_patchlevel,
+ info->dri->pKernelDRMVersion->version_major,
+ info->dri->pKernelDRMVersion->version_minor,
+ info->dri->pKernelDRMVersion->version_patchlevel);
if (info->Chipset == PCI_CHIP_RS400_5A41 ||
info->Chipset == PCI_CHIP_RS400_5A42 ||
@@ -2185,7 +2196,7 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn)
info->Chipset == PCI_CHIP_RS482_5974 ||
info->Chipset == PCI_CHIP_RS485_5975) {
- if (info->pKernelDRMVersion->version_minor < 27) {
+ if (info->dri->pKernelDRMVersion->version_minor < 27) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Direct rendering broken on XPRESS 200 and 200M with DRI less than 1.27\n");
return FALSE;
@@ -2195,21 +2206,21 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn)
}
if (info->ChipFamily >= CHIP_FAMILY_R300)
- info->gartSize = R300_DEFAULT_GART_SIZE;
+ info->dri->gartSize = R300_DEFAULT_GART_SIZE;
else
- info->gartSize = RADEON_DEFAULT_GART_SIZE;
+ info->dri->gartSize = RADEON_DEFAULT_GART_SIZE;
- info->ringSize = RADEON_DEFAULT_RING_SIZE;
- info->bufSize = RADEON_DEFAULT_BUFFER_SIZE;
- info->gartTexSize = RADEON_DEFAULT_GART_TEX_SIZE;
- info->pciAperSize = RADEON_DEFAULT_PCI_APER_SIZE;
+ info->dri->ringSize = RADEON_DEFAULT_RING_SIZE;
+ info->dri->bufSize = RADEON_DEFAULT_BUFFER_SIZE;
+ info->dri->gartTexSize = RADEON_DEFAULT_GART_TEX_SIZE;
+ info->dri->pciAperSize = RADEON_DEFAULT_PCI_APER_SIZE;
info->cp->CPusecTimeout = RADEON_DEFAULT_CP_TIMEOUT;
if ((xf86GetOptValInteger(info->Options,
- OPTION_GART_SIZE, (int *)&(info->gartSize))) ||
+ OPTION_GART_SIZE, (int *)&(info->dri->gartSize))) ||
(xf86GetOptValInteger(info->Options,
- OPTION_GART_SIZE_OLD, (int *)&(info->gartSize)))) {
- switch (info->gartSize) {
+ OPTION_GART_SIZE_OLD, (int *)&(info->dri->gartSize)))) {
+ switch (info->dri->gartSize) {
case 4:
case 8:
case 16:
@@ -2221,24 +2232,24 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn)
default:
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Illegal GART size: %d MB\n", info->gartSize);
+ "Illegal GART size: %d MB\n", info->dri->gartSize);
return FALSE;
}
}
if (xf86GetOptValInteger(info->Options,
- OPTION_RING_SIZE, &(info->ringSize))) {
- if (info->ringSize < 1 || info->ringSize >= (int)info->gartSize) {
+ OPTION_RING_SIZE, &(info->dri->ringSize))) {
+ if (info->dri->ringSize < 1 || info->dri->ringSize >= (int)info->dri->gartSize) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Illegal ring buffer size: %d MB\n",
- info->ringSize);
+ info->dri->ringSize);
return FALSE;
}
}
if (xf86GetOptValInteger(info->Options,
- OPTION_PCIAPER_SIZE, &(info->pciAperSize))) {
- switch(info->pciAperSize) {
+ OPTION_PCIAPER_SIZE, &(info->dri->pciAperSize))) {
+ switch(info->dri->pciAperSize) {
case 32:
case 64:
case 128:
@@ -2247,38 +2258,38 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn)
default:
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Illegal pci aper size: %d MB\n",
- info->pciAperSize);
+ info->dri->pciAperSize);
return FALSE;
}
}
if (xf86GetOptValInteger(info->Options,
- OPTION_BUFFER_SIZE, &(info->bufSize))) {
- if (info->bufSize < 1 || info->bufSize >= (int)info->gartSize) {
+ OPTION_BUFFER_SIZE, &(info->dri->bufSize))) {
+ if (info->dri->bufSize < 1 || info->dri->bufSize >= (int)info->dri->gartSize) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Illegal vertex/indirect buffers size: %d MB\n",
- info->bufSize);
+ info->dri->bufSize);
return FALSE;
}
- if (info->bufSize > 2) {
+ if (info->dri->bufSize > 2) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Illegal vertex/indirect buffers size: %d MB\n",
- info->bufSize);
+ info->dri->bufSize);
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Clamping vertex/indirect buffers size to 2 MB\n");
- info->bufSize = 2;
+ info->dri->bufSize = 2;
}
}
- if (info->ringSize + info->bufSize + info->gartTexSize >
- (int)info->gartSize) {
+ if (info->dri->ringSize + info->dri->bufSize + info->dri->gartTexSize >
+ (int)info->dri->gartSize) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Buffers are too big for requested GART space\n");
return FALSE;
}
- info->gartTexSize = info->gartSize - (info->ringSize + info->bufSize);
+ info->dri->gartTexSize = info->dri->gartSize - (info->dri->ringSize + info->dri->bufSize);
if (xf86GetOptValInteger(info->Options, OPTION_USEC_TIMEOUT,
&(info->cp->CPusecTimeout))) {
@@ -2288,22 +2299,22 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn)
/* Two options to try and squeeze as much texture memory as possible
* for dedicated 3d rendering boxes
*/
- info->noBackBuffer = xf86ReturnOptValBool(info->Options,
- OPTION_NO_BACKBUFFER,
- FALSE);
+ info->dri->noBackBuffer = xf86ReturnOptValBool(info->Options,
+ OPTION_NO_BACKBUFFER,
+ FALSE);
- info->allowPageFlip = 0;
+ info->dri->allowPageFlip = 0;
#ifdef DAMAGE
- if (info->noBackBuffer) {
+ if (info->dri->noBackBuffer) {
from = X_DEFAULT;
reason = " because back buffer disabled";
} else {
from = xf86GetOptValBool(info->Options, OPTION_PAGE_FLIP,
- &info->allowPageFlip) ? X_CONFIG : X_DEFAULT;
+ &info->dri->allowPageFlip) ? X_CONFIG : X_DEFAULT;
if (IS_AVIVO_VARIANT) {
- info->allowPageFlip = 0;
+ info->dri->allowPageFlip = 0;
reason = " on r5xx and newer chips.\n";
} else {
reason = "";
@@ -2316,7 +2327,7 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn)
#endif
xf86DrvMsg(pScrn->scrnIndex, from, "Page Flipping %sabled%s\n",
- info->allowPageFlip ? "en" : "dis", reason);
+ info->dri->allowPageFlip ? "en" : "dis", reason);
info->DMAForXv = TRUE;
from = xf86GetOptValBool(info->Options, OPTION_XV_DMA, &info->DMAForXv)
@@ -2356,15 +2367,15 @@ static void RADEONPreInitColorTiling(ScrnInfoPtr pScrn)
#ifdef XF86DRI
if (info->directRenderingEnabled &&
- info->pKernelDRMVersion->version_minor < 14) {
+ info->dri->pKernelDRMVersion->version_minor < 14) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"[dri] color tiling disabled because of version "
"mismatch.\n"
"[dri] radeon.o kernel module version is %d.%d.%d but "
"1.14.0 or later is required for color tiling.\n",
- info->pKernelDRMVersion->version_major,
- info->pKernelDRMVersion->version_minor,
- info->pKernelDRMVersion->version_patchlevel);
+ info->dri->pKernelDRMVersion->version_major,
+ info->dri->pKernelDRMVersion->version_minor,
+ info->dri->pKernelDRMVersion->version_patchlevel);
info->allowColorTiling = FALSE;
return;
}
@@ -3202,14 +3213,14 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
info->accel_state->accel = NULL;
#endif
#ifdef XF86DRI
- pScrn->fbOffset = info->frontOffset;
+ pScrn->fbOffset = info->dri->frontOffset;
#endif
if (info->IsSecondary) pScrn->fbOffset = pScrn->videoRam * 1024;
#ifdef XF86DRI
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"RADEONScreenInit %lx %ld %d\n",
- pScrn->memPhysBase, pScrn->fbOffset, info->frontOffset);
+ pScrn->memPhysBase, pScrn->fbOffset, info->dri->frontOffset);
#else
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"RADEONScreenInit %lx %ld\n",
@@ -3218,8 +3229,8 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
if (!RADEONMapMem(pScrn)) return FALSE;
#ifdef XF86DRI
- info->fbX = 0;
- info->fbY = 0;
+ info->dri->fbX = 0;
+ info->dri->fbY = 0;
#endif
info->PaletteSavedOnVT = FALSE;
@@ -3273,21 +3284,21 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
if (info->directRenderingEnabled) {
MessageType from;
- info->depthBits = pScrn->depth;
+ info->dri->depthBits = pScrn->depth;
from = xf86GetOptValInteger(info->Options, OPTION_DEPTH_BITS,
- &info->depthBits)
+ &info->dri->depthBits)
? X_CONFIG : X_DEFAULT;
- if (info->depthBits != 16 && info->depthBits != 24) {
+ if (info->dri->depthBits != 16 && info->dri->depthBits != 24) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Value for Option \"DepthBits\" must be 16 or 24\n");
- info->depthBits = pScrn->depth;
+ info->dri->depthBits = pScrn->depth;
from = X_DEFAULT;
}
xf86DrvMsg(pScrn->scrnIndex, from,
- "Using %d bit depth buffer\n", info->depthBits);
+ "Using %d bit depth buffer\n", info->dri->depthBits);
}
@@ -3312,14 +3323,14 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
#ifdef XF86DRI
/* Depth moves are disabled by default since they are extremely slow */
- info->depthMoves = xf86ReturnOptValBool(info->Options,
+ info->dri->depthMoves = xf86ReturnOptValBool(info->Options,
OPTION_DEPTH_MOVE, FALSE);
- if (info->depthMoves && info->allowColorTiling) {
+ if (info->dri->depthMoves && info->allowColorTiling) {
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Enabling depth moves\n");
- } else if (info->depthMoves) {
+ } else if (info->dri->depthMoves) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Depth moves don't work without color tiling, disabled\n");
- info->depthMoves = FALSE;
+ info->dri->depthMoves = FALSE;
} else {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Depth moves disabled by default\n");
@@ -3355,15 +3366,15 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
* default, can be overridden with Option "FBTexPercent".
* Round down to a whole number of texture regions.
*/
- info->textureSize = 50;
+ info->dri->textureSize = 50;
if (xf86GetOptValInteger(info->Options, OPTION_FBTEX_PERCENT,
- &(info->textureSize))) {
- if (info->textureSize < 0 || info->textureSize > 100) {
+ &(info->dri->textureSize))) {
+ if (info->dri->textureSize < 0 || info->dri->textureSize > 100) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Illegal texture memory percentage: %dx, setting to default 50%%\n",
- info->textureSize);
- info->textureSize = 50;
+ info->dri->textureSize);
+ info->dri->textureSize = 50;
}
}
}
@@ -3380,19 +3391,19 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
#if defined(XF86DRI) && defined(USE_XAA)
if (!info->useEXA && hasDRI) {
- info->textureSize = -1;
+ info->dri->textureSize = -1;
if (xf86GetOptValInteger(info->Options, OPTION_FBTEX_PERCENT,
- &(info->textureSize))) {
- if (info->textureSize < 0 || info->textureSize > 100) {
+ &(info->dri->textureSize))) {
+ if (info->dri->textureSize < 0 || info->dri->textureSize > 100) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Illegal texture memory percentage: %dx, using default behaviour\n",
- info->textureSize);
- info->textureSize = -1;
+ info->dri->textureSize);
+ info->dri->textureSize = -1;
}
}
if (!RADEONSetupMemXAA_DRI(scrnIndex, pScreen))
return FALSE;
- pScrn->fbOffset = info->frontOffset;
+ pScrn->fbOffset = info->dri->frontOffset;
}
#endif
@@ -3433,7 +3444,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
}
/* Tell DRI about new memory map */
- if (info->directRenderingEnabled && info->newMemoryMap) {
+ if (info->directRenderingEnabled && info->dri->newMemoryMap) {
if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_NEW_MEMMAP, 1) < 0) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"[drm] failed to enable new memory map\n");
@@ -3520,14 +3531,14 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
/* DRI finalisation */
#ifdef XF86DRI
if (info->directRenderingEnabled && info->cardType==CARD_PCIE &&
- info->pKernelDRMVersion->version_minor >= 19)
+ info->dri->pKernelDRMVersion->version_minor >= 19)
{
- if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_PCIGART_LOCATION, info->pciGartOffset) < 0)
+ if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_PCIGART_LOCATION, info->dri->pciGartOffset) < 0)
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"[drm] failed set pci gart location\n");
- if (info->pKernelDRMVersion->version_minor >= 26) {
- if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_PCIGART_TABLE_SIZE, info->pciGartSize) < 0)
+ if (info->dri->pKernelDRMVersion->version_minor >= 26) {
+ if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_PCIGART_TABLE_SIZE, info->dri->pciGartSize) < 0)
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"[drm] failed set pci gart table size\n");
}
@@ -3544,10 +3555,6 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
*/
RADEONAdjustMemMapRegisters(pScrn, info->ModeReg);
- if ((info->DispPriority == 1) && (info->cardType==CARD_AGP)) {
- /* we need to re-calculate bandwidth because of AGPMode difference. */
- RADEONInitDispBandwidth(pScrn);
- }
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct rendering enabled\n");
/* we might already be in tiled mode, tell drm about it */
@@ -3952,7 +3959,7 @@ static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
gp.param = RADEON_PARAM_GART_BASE;
gp.value = &gart_base;
- if (drmCommandWriteRead(info->drmFD, DRM_RADEON_GETPARAM, &gp,
+ if (drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_GETPARAM, &gp,
sizeof(gp)) < 0) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Failed to determine GART area MC location, not using "
@@ -4039,32 +4046,32 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn)
drmRadeonSurfaceFree drmsurffree;
drmRadeonSurfaceAlloc drmsurfalloc;
int retvalue;
- int depthCpp = (info->depthBits - 8) / 4;
+ int depthCpp = (info->dri->depthBits - 8) / 4;
int depth_width_bytes = pScrn->displayWidth * depthCpp;
int depthBufferSize = ((((pScrn->virtualY + 15) & ~15) * depth_width_bytes
+ RADEON_BUFFER_ALIGN) & ~RADEON_BUFFER_ALIGN);
unsigned int depth_pattern;
- drmsurffree.address = info->frontOffset;
- retvalue = drmCommandWrite(info->drmFD, DRM_RADEON_SURF_FREE,
+ drmsurffree.address = info->dri->frontOffset;
+ retvalue = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_FREE,
&drmsurffree, sizeof(drmsurffree));
if (!((info->ChipFamily == CHIP_FAMILY_RV100) ||
(info->ChipFamily == CHIP_FAMILY_RS100) ||
(info->ChipFamily == CHIP_FAMILY_RS200))) {
- drmsurffree.address = info->depthOffset;
- retvalue = drmCommandWrite(info->drmFD, DRM_RADEON_SURF_FREE,
+ drmsurffree.address = info->dri->depthOffset;
+ retvalue = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_FREE,
&drmsurffree, sizeof(drmsurffree));
}
- if (!info->noBackBuffer) {
- drmsurffree.address = info->backOffset;
- retvalue = drmCommandWrite(info->drmFD, DRM_RADEON_SURF_FREE,
+ if (!info->dri->noBackBuffer) {
+ drmsurffree.address = info->dri->backOffset;
+ retvalue = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_FREE,
&drmsurffree, sizeof(drmsurffree));
}
drmsurfalloc.size = bufferSize;
- drmsurfalloc.address = info->frontOffset;
+ drmsurfalloc.address = info->dri->frontOffset;
drmsurfalloc.flags = swap_pattern;
if (info->tilingEnabled) {
@@ -4073,15 +4080,15 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn)
else
drmsurfalloc.flags |= (width_bytes / 16) | color_pattern;
}
- retvalue = drmCommandWrite(info->drmFD, DRM_RADEON_SURF_ALLOC,
+ retvalue = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_ALLOC,
&drmsurfalloc, sizeof(drmsurfalloc));
if (retvalue < 0)
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"drm: could not allocate surface for front buffer!\n");
- if ((info->have3DWindows) && (!info->noBackBuffer)) {
- drmsurfalloc.address = info->backOffset;
- retvalue = drmCommandWrite(info->drmFD, DRM_RADEON_SURF_ALLOC,
+ if ((info->dri->have3DWindows) && (!info->dri->noBackBuffer)) {
+ drmsurfalloc.address = info->dri->backOffset;
+ retvalue = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_ALLOC,
&drmsurfalloc, sizeof(drmsurfalloc));
if (retvalue < 0)
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
@@ -4106,18 +4113,18 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn)
}
/* rv100 and probably the derivative igps don't have depth tiling on all the time? */
- if (info->have3DWindows &&
+ if (info->dri->have3DWindows &&
(!((info->ChipFamily == CHIP_FAMILY_RV100) ||
(info->ChipFamily == CHIP_FAMILY_RS100) ||
(info->ChipFamily == CHIP_FAMILY_RS200)))) {
drmRadeonSurfaceAlloc drmsurfalloc;
drmsurfalloc.size = depthBufferSize;
- drmsurfalloc.address = info->depthOffset;
+ drmsurfalloc.address = info->dri->depthOffset;
if (IS_R300_VARIANT || IS_AVIVO_VARIANT)
drmsurfalloc.flags = swap_pattern | (depth_width_bytes / 8) | depth_pattern;
else
drmsurfalloc.flags = swap_pattern | (depth_width_bytes / 16) | depth_pattern;
- retvalue = drmCommandWrite(info->drmFD, DRM_RADEON_SURF_ALLOC,
+ retvalue = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_ALLOC,
&drmsurfalloc, sizeof(drmsurfalloc));
if (retvalue < 0)
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
@@ -5286,7 +5293,7 @@ void RADEONDoAdjustFrame(ScrnInfoPtr pScrn, int x, int y, Bool crtc2)
#if 0
/* try to get rid of flickering when scrolling at least for 2d */
#ifdef XF86DRI
- if (!info->have3DWindows)
+ if (!info->dri->have3DWindows)
#endif
crtcoffsetcntl &= ~RADEON_CRTC_OFFSET_FLIP_CNTL;
#endif
@@ -5343,7 +5350,7 @@ void RADEONDoAdjustFrame(ScrnInfoPtr pScrn, int x, int y, Bool crtc2)
}
if (pSAREAPriv->pfCurrentPage == 1) {
- Base += info->backOffset - info->frontOffset;
+ Base += info->dri->backOffset - info->dri->frontOffset;
}
}
#endif
@@ -5451,10 +5458,10 @@ Bool RADEONEnterVT(int scrnIndex, int flags)
#ifdef XF86DRI
if (info->directRenderingEnabled) {
if (info->cardType == CARD_PCIE &&
- info->pKernelDRMVersion->version_minor >= 19 &&
+ info->dri->pKernelDRMVersion->version_minor >= 19 &&
info->FbSecureSize) {
/* we need to backup the PCIE GART TABLE from fb memory */
- memcpy(info->FB + info->pciGartOffset, info->pciGartBackup, info->pciGartSize);
+ memcpy(info->FB + info->dri->pciGartOffset, info->dri->pciGartBackup, info->dri->pciGartSize);
}
/* get the DRI back into shape after resume */
@@ -5502,14 +5509,14 @@ void RADEONLeaveVT(int scrnIndex, int flags)
RADEONCP_STOP(pScrn, info);
if (info->cardType == CARD_PCIE &&
- info->pKernelDRMVersion->version_minor >= 19 &&
+ info->dri->pKernelDRMVersion->version_minor >= 19 &&
info->FbSecureSize) {
/* we need to backup the PCIE GART TABLE from fb memory */
- memcpy(info->pciGartBackup, (info->FB + info->pciGartOffset), info->pciGartSize);
+ memcpy(info->dri->pciGartBackup, (info->FB + info->dri->pciGartOffset), info->dri->pciGartSize);
}
/* Make sure 3D clients will re-upload textures to video RAM */
- if (info->textureSize) {
+ if (info->dri->textureSize) {
RADEONSAREAPrivPtr pSAREAPriv =
(RADEONSAREAPrivPtr)DRIGetSAREAPrivate(pScrn->pScreen);
drmTextureRegionPtr list = pSAREAPriv->texList[0];
@@ -5570,12 +5577,12 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen)
#ifdef XF86DRI
#ifdef DAMAGE
- if (info->pDamage) {
+ if (info->dri && info->dri->pDamage) {
PixmapPtr pPix = pScreen->GetScreenPixmap(pScreen);
- DamageUnregister(&pPix->drawable, info->pDamage);
- DamageDestroy(info->pDamage);
- info->pDamage = NULL;
+ DamageUnregister(&pPix->drawable, info->dri->pDamage);
+ DamageDestroy(info->dri->pDamage);
+ info->dri->pDamage = NULL;
}
#endif
diff --git a/src/radeon_exa.c b/src/radeon_exa.c
index d8dcbac9..f77235a9 100644
--- a/src/radeon_exa.c
+++ b/src/radeon_exa.c
@@ -244,7 +244,7 @@ static Bool RADEONPrepareAccess(PixmapPtr pPix, int index)
drmsurfalloc.size = size;
drmsurfalloc.flags = flags | 1; /* bogus pitch to please DRM */
- rc = drmCommandWrite(info->drmFD, DRM_RADEON_SURF_ALLOC,
+ rc = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_ALLOC,
&drmsurfalloc, sizeof(drmsurfalloc));
if (rc < 0) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
@@ -283,7 +283,7 @@ static void RADEONFinishAccess(PixmapPtr pPix, int index)
drmRadeonSurfaceFree drmsurffree;
drmsurffree.address = offset;
- drmCommandWrite(info->drmFD, DRM_RADEON_SURF_FREE,
+ drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_FREE,
&drmsurffree, sizeof(drmsurffree));
swapper_surfaces[index] = 0;
return;
@@ -444,21 +444,21 @@ Bool RADEONSetupMemEXA (ScreenPtr pScreen)
#if defined(XF86DRI)
if (info->directRenderingEnabled) {
- int depthCpp = (info->depthBits - 8) / 4, l, next, depth_size;
+ int depthCpp = (info->dri->depthBits - 8) / 4, l, next, depth_size;
- info->frontOffset = 0;
- info->frontPitch = pScrn->displayWidth;
+ info->dri->frontOffset = 0;
+ info->dri->frontPitch = pScrn->displayWidth;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Will use %d kb for front buffer at offset 0x%08x\n",
- screen_size / 1024, info->frontOffset);
+ screen_size / 1024, info->dri->frontOffset);
RADEONDRIAllocatePCIGARTTable(pScreen);
if (info->cardType==CARD_PCIE)
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Will use %d kb for PCI GART at offset 0x%08x\n",
- info->pciGartSize / 1024,
- (int)info->pciGartOffset);
+ info->dri->pciGartSize / 1024,
+ (int)info->dri->pciGartOffset);
/* Reserve a static area for the back buffer the same size as the
* visible screen. XXX: This would be better initialized in ati_dri.c
@@ -466,49 +466,49 @@ Bool RADEONSetupMemEXA (ScreenPtr pScreen)
* don't last through VT switches, while the kernel's understanding of
* offscreen locations does.
*/
- info->backPitch = pScrn->displayWidth;
+ info->dri->backPitch = pScrn->displayWidth;
next = RADEON_ALIGN(info->accel_state->exa->offScreenBase, RADEON_BUFFER_ALIGN);
- if (!info->noBackBuffer &&
+ if (!info->dri->noBackBuffer &&
next + screen_size <= info->accel_state->exa->memorySize)
{
- info->backOffset = next;
+ info->dri->backOffset = next;
info->accel_state->exa->offScreenBase = next + screen_size;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Will use %d kb for back buffer at offset 0x%08x\n",
- screen_size / 1024, info->backOffset);
+ screen_size / 1024, info->dri->backOffset);
}
/* Reserve the static depth buffer, and adjust pitch and height to
* handle tiling.
*/
- info->depthPitch = RADEON_ALIGN(pScrn->displayWidth, 32);
- depth_size = RADEON_ALIGN(pScrn->virtualY, 16) * info->depthPitch * depthCpp;
+ info->dri->depthPitch = RADEON_ALIGN(pScrn->displayWidth, 32);
+ depth_size = RADEON_ALIGN(pScrn->virtualY, 16) * info->dri->depthPitch * depthCpp;
next = RADEON_ALIGN(info->accel_state->exa->offScreenBase, RADEON_BUFFER_ALIGN);
if (next + depth_size <= info->accel_state->exa->memorySize)
{
- info->depthOffset = next;
+ info->dri->depthOffset = next;
info->accel_state->exa->offScreenBase = next + depth_size;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Will use %d kb for depth buffer at offset 0x%08x\n",
- depth_size / 1024, info->depthOffset);
+ depth_size / 1024, info->dri->depthOffset);
}
- info->textureSize *= (info->accel_state->exa->memorySize -
- info->accel_state->exa->offScreenBase) / 100;
+ info->dri->textureSize *= (info->accel_state->exa->memorySize -
+ info->accel_state->exa->offScreenBase) / 100;
- l = RADEONLog2(info->textureSize / RADEON_NR_TEX_REGIONS);
+ l = RADEONLog2(info->dri->textureSize / RADEON_NR_TEX_REGIONS);
if (l < RADEON_LOG_TEX_GRANULARITY)
l = RADEON_LOG_TEX_GRANULARITY;
- info->textureSize = (info->textureSize >> l) << l;
- if (info->textureSize >= 512 * 1024) {
- info->textureOffset = info->accel_state->exa->offScreenBase;
- info->accel_state->exa->offScreenBase += info->textureSize;
+ info->dri->textureSize = (info->dri->textureSize >> l) << l;
+ if (info->dri->textureSize >= 512 * 1024) {
+ info->dri->textureOffset = info->accel_state->exa->offScreenBase;
+ info->accel_state->exa->offScreenBase += info->dri->textureSize;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Will use %d kb for textures at offset 0x%08x\n",
- info->textureSize / 1024, info->textureOffset);
+ info->dri->textureSize / 1024, info->dri->textureOffset);
} else {
/* Minimum texture size is for 2 256x256x32bpp textures */
- info->textureSize = 0;
+ info->dri->textureSize = 0;
}
} else
#endif /* XF86DRI */
diff --git a/src/radeon_exa_funcs.c b/src/radeon_exa_funcs.c
index 783e83dc..2be9a8de 100644
--- a/src/radeon_exa_funcs.c
+++ b/src/radeon_exa_funcs.c
@@ -401,7 +401,7 @@ FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x, int y, int w, int h,
int swap = RADEON_HOST_DATA_SWAP_NONE, wpass = w * bpp / 8;
int hpass = min(h, scratch->total/2 / scratch_pitch);
uint32_t scratch_pitch_offset = scratch_pitch << 16
- | (info->gartLocation + info->bufStart
+ | (info->gartLocation + info->dri->bufStart
+ scratch->idx * scratch->total) >> 10;
drmRadeonIndirect indirect;
ACCEL_PREAMBLE();
@@ -450,7 +450,7 @@ FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x, int y, int w, int h,
* we'd really need is a way to reliably wait for the host interface
* to be done with pushing the data to the host.
*/
- while ((drmCommandNone(info->drmFD, DRM_RADEON_CP_IDLE) == -EBUSY)
+ while ((drmCommandNone(info->dri->drmFD, DRM_RADEON_CP_IDLE) == -EBUSY)
&& (i++ < RADEON_TIMEOUT))
;
@@ -473,7 +473,7 @@ FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x, int y, int w, int h,
indirect.start = indirect.end = 0;
indirect.discard = 1;
- drmCommandWriteRead(info->drmFD, DRM_RADEON_INDIRECT,
+ drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_INDIRECT,
&indirect, sizeof(drmRadeonIndirect));
info->accel_state->exaMarkerSynced = info->accel_state->exaSyncMarker;
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-26 09:10:45 +0000