summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--src/radeon_commonfuncs.c31
-rw-r--r--src/radeon_exa_render.c309
-rw-r--r--src/radeon_textured_videofuncs.c222
3 files changed, 445 insertions, 117 deletions
diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c
index 987dac65..deb2c991 100644
--- a/src/radeon_commonfuncs.c
+++ b/src/radeon_commonfuncs.c
@@ -60,7 +60,9 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
info->texW[0] = info->texH[0] = info->texW[1] = info->texH[1] = 1;
- if (IS_R300_3D || IS_R500_3D) {
+ if (IS_R300_VARIANT || IS_AVIVO_VARIANT ||
+ (info->ChipFamily == CHIP_FAMILY_RS690) ||
+ (info->ChipFamily == CHIP_FAMILY_RS740)) {
BEGIN_ACCEL(3);
OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
@@ -142,27 +144,6 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
OUT_ACCEL_REG(R300_SU_DEPTH_OFFSET, 0);
FINISH_ACCEL();
- /* setup the VAP */
- BEGIN_ACCEL(6);
- /* disable TCL/PVS */
- OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
- OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, R300_PVS_BYPASS);
- if (IS_R300_3D)
- OUT_ACCEL_REG(R300_VAP_CNTL, ((10 << R300_PVS_NUM_SLOTS_SHIFT) |
- (6 << R300_PVS_NUM_CNTLRS_SHIFT) |
- (6 << R300_PVS_NUM_FPUS_SHIFT) |
- (12 << R300_VF_MAX_VTX_NUM_SHIFT)));
- else
- OUT_ACCEL_REG(R300_VAP_CNTL, ((10 << R300_PVS_NUM_SLOTS_SHIFT) |
- (6 << R300_PVS_NUM_CNTLRS_SHIFT) |
- (6 << R300_PVS_NUM_FPUS_SHIFT) |
- (12 << R300_VF_MAX_VTX_NUM_SHIFT) |
- R500_TCL_STATE_OPTIMIZATION));
- OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
- OUT_ACCEL_REG(R300_VAP_VTE_CNTL, R300_VTX_XY_FMT | R300_VTX_Z_FMT);
- OUT_ACCEL_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0);
- FINISH_ACCEL();
-
BEGIN_ACCEL(4);
OUT_ACCEL_REG(R300_US_W_FMT, 0);
OUT_ACCEL_REG(R300_US_OUT_FMT_1, (R300_OUT_FMT_UNUSED |
@@ -189,8 +170,7 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
OUT_ACCEL_REG(R300_FG_ALPHA_FUNC, 0);
FINISH_ACCEL();
- BEGIN_ACCEL(13);
- OUT_ACCEL_REG(R300_RB3D_ABLENDCNTL, 0);
+ BEGIN_ACCEL(12);
OUT_ACCEL_REG(R300_RB3D_ZSTENCILCNTL, 0);
OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE);
OUT_ACCEL_REG(R300_RB3D_BW_CNTL, 0);
@@ -216,7 +196,8 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
OUT_ACCEL_REG(R300_SC_SCISSOR1, ((8191 << R300_SCISSOR_X_SHIFT) |
(8191 << R300_SCISSOR_Y_SHIFT)));
- if (IS_R300_3D) {
+ if (IS_R300_VARIANT || (info->ChipFamily == CHIP_FAMILY_RS690) ||
+ (info->ChipFamily == CHIP_FAMILY_RS740)) {
/* clip has offset 1440 */
OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((1088 << R300_CLIP_X_SHIFT) |
(1088 << R300_CLIP_Y_SHIFT)));
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index cd0fa488..6317ecb4 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -1051,6 +1051,10 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
CARD32 txenable, colorpitch;
CARD32 blendcntl;
int pixel_shift;
+ int has_tcl = ((info->ChipFamily != CHIP_FAMILY_RS690) &&
+ (info->ChipFamily != CHIP_FAMILY_RS740) &&
+ (info->ChipFamily != CHIP_FAMILY_RS400) &&
+ (info->ChipFamily != CHIP_FAMILY_RV515));
ACCEL_PREAMBLE();
TRACE;
@@ -1091,49 +1095,234 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
RADEON_SWITCH_TO_3D();
- BEGIN_ACCEL(8);
- OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0,
- ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) |
- (0 << R300_SKIP_DWORDS_0_SHIFT) |
- (0 << R300_DST_VEC_LOC_0_SHIFT) |
- R300_SIGNED_0 |
- (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) |
- (0 << R300_SKIP_DWORDS_1_SHIFT) |
- (6 << R300_DST_VEC_LOC_1_SHIFT) |
- R300_SIGNED_1));
- OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_1,
- ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_2_SHIFT) |
- (0 << R300_SKIP_DWORDS_2_SHIFT) |
- (7 << R300_DST_VEC_LOC_2_SHIFT) |
- R300_LAST_VEC_2 |
- R300_SIGNED_2));
- OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0,
- ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) |
- (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) |
- (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_0_SHIFT) |
- (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_0_SHIFT) |
- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
- << R300_WRITE_ENA_0_SHIFT) |
- (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) |
- (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) |
- (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_1_SHIFT) |
- (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_1_SHIFT) |
- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
- << R300_WRITE_ENA_1_SHIFT)));
- OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1,
- ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_2_SHIFT) |
- (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_2_SHIFT) |
- (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_2_SHIFT) |
- (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_2_SHIFT) |
- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
- << R300_WRITE_ENA_2_SHIFT)));
+ /* setup the VAP */
+ if (has_tcl) {
+ BEGIN_ACCEL(9);
+ OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, 0);
+ OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
+ OUT_ACCEL_REG(R300_VAP_CNTL, ((6 << R300_PVS_NUM_SLOTS_SHIFT) |
+ (5 << R300_PVS_NUM_CNTLRS_SHIFT) |
+ (4 << R300_PVS_NUM_FPUS_SHIFT) |
+ (12 << R300_VF_MAX_VTX_NUM_SHIFT)));
+ } else {
+ BEGIN_ACCEL(8);
+ OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, R300_PVS_BYPASS);
+ OUT_ACCEL_REG(R300_VAP_CNTL, ((10 << R300_PVS_NUM_SLOTS_SHIFT) |
+ (5 << R300_PVS_NUM_CNTLRS_SHIFT) |
+ (4 << R300_PVS_NUM_FPUS_SHIFT) |
+ (5 << R300_VF_MAX_VTX_NUM_SHIFT)));
+ }
+
+ OUT_ACCEL_REG(R300_VAP_VTE_CNTL, R300_VTX_XY_FMT | R300_VTX_Z_FMT);
+ OUT_ACCEL_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0);
+
+ if (has_tcl) {
+ OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0,
+ ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) |
+ (0 << R300_SKIP_DWORDS_0_SHIFT) |
+ (0 << R300_DST_VEC_LOC_0_SHIFT) |
+ R300_SIGNED_0 |
+ (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) |
+ (0 << R300_SKIP_DWORDS_1_SHIFT) |
+ (1 << R300_DST_VEC_LOC_1_SHIFT) |
+ R300_SIGNED_1));
+ OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_1,
+ ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_2_SHIFT) |
+ (0 << R300_SKIP_DWORDS_2_SHIFT) |
+ (2 << R300_DST_VEC_LOC_2_SHIFT) |
+ R300_LAST_VEC_2 |
+ R300_SIGNED_2));
+ OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0,
+ ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) |
+ (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) |
+ (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_0_SHIFT) |
+ (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_0_SHIFT) |
+ ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
+ << R300_WRITE_ENA_0_SHIFT) |
+ (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) |
+ (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) |
+ (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_1_SHIFT) |
+ (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_1_SHIFT) |
+ ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
+ << R300_WRITE_ENA_1_SHIFT)));
+ OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1,
+ ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_2_SHIFT) |
+ (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_2_SHIFT) |
+ (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_2_SHIFT) |
+ (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_2_SHIFT) |
+ ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
+ << R300_WRITE_ENA_2_SHIFT)));
+ } else {
+ OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0,
+ ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) |
+ (0 << R300_SKIP_DWORDS_0_SHIFT) |
+ (0 << R300_DST_VEC_LOC_0_SHIFT) |
+ R300_SIGNED_0 |
+ (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) |
+ (0 << R300_SKIP_DWORDS_1_SHIFT) |
+ (6 << R300_DST_VEC_LOC_1_SHIFT) |
+ R300_SIGNED_1));
+ OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_1,
+ ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_2_SHIFT) |
+ (0 << R300_SKIP_DWORDS_2_SHIFT) |
+ (7 << R300_DST_VEC_LOC_2_SHIFT) |
+ R300_LAST_VEC_2 |
+ R300_SIGNED_2));
+ OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0,
+ ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) |
+ (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) |
+ (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_0_SHIFT) |
+ (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_0_SHIFT) |
+ ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
+ << R300_WRITE_ENA_0_SHIFT) |
+ (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) |
+ (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) |
+ (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_1_SHIFT) |
+ (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_1_SHIFT) |
+ ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
+ << R300_WRITE_ENA_1_SHIFT)));
+ OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1,
+ ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_2_SHIFT) |
+ (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_2_SHIFT) |
+ (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_2_SHIFT) |
+ (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_2_SHIFT) |
+ ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
+ << R300_WRITE_ENA_2_SHIFT)));
+ }
+ FINISH_ACCEL();
+
+ /* setup the vertex shader */
+ if (has_tcl) {
+ if (pMask) {
+ BEGIN_ACCEL(22);
+ /* flush the PVS before updating??? */
+ OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
+
+ OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0,
+ ((0 << R300_PVS_FIRST_INST_SHIFT) |
+ (2 << R300_PVS_XYZW_VALID_INST_SHIFT) |
+ (2 << R300_PVS_LAST_INST_SHIFT)));
+ OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1,
+ (2 << R300_PVS_LAST_VTX_SRC_INST_SHIFT));
+ } else {
+ BEGIN_ACCEL(18);
+ /* flush the PVS before updating??? */
+ OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
+
+ OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0,
+ ((0 << R300_PVS_FIRST_INST_SHIFT) |
+ (1 << R300_PVS_XYZW_VALID_INST_SHIFT) |
+ (1 << R300_PVS_LAST_INST_SHIFT)));
+ OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1,
+ (1 << R300_PVS_LAST_VTX_SRC_INST_SHIFT));
+ }
+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
+ /* PVS inst 0 */
+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_DST_OPCODE(R300_VE_ADD) |
+ R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
+ R300_PVS_DST_OFFSET(0) |
+ R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
+ R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(0) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(0) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(0) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+
+ /* PVS inst 1 */
+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_DST_OPCODE(R300_VE_ADD) |
+ R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
+ R300_PVS_DST_OFFSET(1) |
+ R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
+ R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(1) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(1) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(1) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+
+ if (pMask) {
+ /* PVS inst 2 */
+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_DST_OPCODE(R300_VE_ADD) |
+ R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
+ R300_PVS_DST_OFFSET(2) |
+ R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
+ R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(2) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(2) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(2) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+ }
+
+ OUT_ACCEL_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0);
+ OUT_ACCEL_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000);
+ OUT_ACCEL_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000);
+ OUT_ACCEL_REG(R300_VAP_GB_HORZ_CLIP_ADJ, 0x3f800000);
+ OUT_ACCEL_REG(R300_VAP_GB_HORZ_DISC_ADJ, 0x3f800000);
+ OUT_ACCEL_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
+ FINISH_ACCEL();
+ }
+
+ BEGIN_ACCEL(4);
OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_0, R300_VTX_POS_PRESENT);
OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_1,
((2 << R300_TEX_0_COMP_CNT_SHIFT) |
(2 << R300_TEX_1_COMP_CNT_SHIFT)));
- OUT_ACCEL_REG(R300_TX_INVALTAGS, 0);
+ OUT_ACCEL_REG(R300_TX_INVALTAGS, 0x0);
OUT_ACCEL_REG(R300_TX_ENABLE, txenable);
FINISH_ACCEL();
@@ -1384,80 +1573,103 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
CARD32 mask_color, mask_alpha;
if (PICT_FORMAT_RGB(pSrcPicture->format) == 0)
+ //src_color = R300_ALU_RGB_0_0;
src_color = (R500_ALU_RGB_R_SWIZ_A_0 |
R500_ALU_RGB_G_SWIZ_A_0 |
R500_ALU_RGB_B_SWIZ_A_0);
else
+ //src_color = R300_ALU_RGB_SRC0_RGB;
src_color = (R500_ALU_RGB_R_SWIZ_A_R |
R500_ALU_RGB_G_SWIZ_A_G |
R500_ALU_RGB_B_SWIZ_A_B);
if (PICT_FORMAT_A(pSrcPicture->format) == 0)
+ //src_alpha = R300_ALU_ALPHA_1_0;
src_alpha = R500_ALPHA_SWIZ_A_1;
else
+ //src_alpha = R300_ALU_ALPHA_SRC0_A;
src_alpha = R500_ALPHA_SWIZ_A_A;
if (pMask && pMaskPicture->componentAlpha) {
if (RadeonBlendOp[op].src_alpha) {
if (PICT_FORMAT_A(pSrcPicture->format) == 0) {
+ //src_color = R300_ALU_RGB_1_0;
+ //src_alpha = R300_ALU_ALPHA_1_0;
src_color = (R500_ALU_RGB_R_SWIZ_A_1 |
R500_ALU_RGB_G_SWIZ_A_1 |
R500_ALU_RGB_B_SWIZ_A_1);
src_alpha = R500_ALPHA_SWIZ_A_1;
} else {
+ //src_color = R300_ALU_RGB_SRC0_AAA;
+ //src_alpha = R300_ALU_ALPHA_SRC0_A;
src_color = (R500_ALU_RGB_R_SWIZ_A_A |
R500_ALU_RGB_G_SWIZ_A_A |
R500_ALU_RGB_B_SWIZ_A_A);
src_alpha = R500_ALPHA_SWIZ_A_A;
}
+ //mask_color = R300_ALU_RGB_SRC1_RGB;
mask_color = (R500_ALU_RGB_R_SWIZ_B_R |
R500_ALU_RGB_G_SWIZ_B_G |
R500_ALU_RGB_B_SWIZ_B_B);
if (PICT_FORMAT_A(pMaskPicture->format) == 0)
+ //mask_alpha = R300_ALU_ALPHA_1_0;
mask_alpha = R500_ALPHA_SWIZ_B_1;
else
+ //mask_alpha = R300_ALU_ALPHA_SRC1_A;
mask_alpha = R500_ALPHA_SWIZ_B_A;
} else {
+ //src_color = R300_ALU_RGB_SRC0_RGB;
src_color = (R500_ALU_RGB_R_SWIZ_A_R |
R500_ALU_RGB_G_SWIZ_A_G |
R500_ALU_RGB_B_SWIZ_A_B);
if (PICT_FORMAT_A(pSrcPicture->format) == 0)
+ //src_alpha = R300_ALU_ALPHA_1_0;
src_alpha = R500_ALPHA_SWIZ_A_1;
else
+ //src_alpha = R300_ALU_ALPHA_SRC0_A;
src_alpha = R500_ALPHA_SWIZ_A_A;
+ //mask_color = R300_ALU_RGB_SRC1_RGB;
mask_color = (R500_ALU_RGB_R_SWIZ_B_R |
R500_ALU_RGB_G_SWIZ_B_G |
R500_ALU_RGB_B_SWIZ_B_B);
if (PICT_FORMAT_A(pMaskPicture->format) == 0)
+ //mask_alpha = R300_ALU_ALPHA_1_0;
mask_alpha = R500_ALPHA_SWIZ_B_1;
else
+ //mask_alpha = R300_ALU_ALPHA_SRC1_A;
mask_alpha = R500_ALPHA_SWIZ_B_A;
}
} else if (pMask) {
if (PICT_FORMAT_A(pMaskPicture->format) == 0)
+ //mask_color = R300_ALU_RGB_1_0;
mask_color = (R500_ALU_RGB_R_SWIZ_B_1 |
R500_ALU_RGB_G_SWIZ_B_1 |
R500_ALU_RGB_B_SWIZ_B_1);
else
+ //mask_color = R300_ALU_RGB_SRC1_AAA;
mask_color = (R500_ALU_RGB_R_SWIZ_B_A |
R500_ALU_RGB_G_SWIZ_B_A |
R500_ALU_RGB_B_SWIZ_B_A);
if (PICT_FORMAT_A(pMaskPicture->format) == 0)
+ //mask_alpha = R300_ALU_ALPHA_1_0;
mask_alpha = R500_ALPHA_SWIZ_B_1;
else
+ //mask_alpha = R300_ALU_ALPHA_SRC1_A;
mask_alpha = R500_ALPHA_SWIZ_B_A;
} else {
+ //mask_color = R300_ALU_RGB_1_0;
mask_color = (R500_ALU_RGB_R_SWIZ_B_1 |
R500_ALU_RGB_G_SWIZ_B_1 |
R500_ALU_RGB_B_SWIZ_B_1);
+ //mask_alpha = R300_ALU_ALPHA_1_0;
mask_alpha = R500_ALPHA_SWIZ_B_1;
}
@@ -1531,7 +1743,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
(R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
(R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT)));
- OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6));
+ OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1) | R300_TX_OFFSET_RS(6));
/* src tex */
OUT_ACCEL_REG(R500_RS_INST_0, ((0 << R500_RS_INST_TEX_ID_SHIFT) |
@@ -1583,9 +1795,9 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
R500_DY_S_SWIZ_R |
R500_DY_T_SWIZ_R |
R500_DY_R_SWIZ_R |
- R500_DY_Q_SWIZ_R));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ R500_DY_Q_SWIZ_R)); // TEX_ADDR_DXDY
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz
OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_TEX_SEM_WAIT |
@@ -1618,9 +1830,9 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
R500_DY_S_SWIZ_R |
R500_DY_T_SWIZ_R |
R500_DY_R_SWIZ_R |
- R500_DY_Q_SWIZ_R));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ R500_DY_Q_SWIZ_R)); // TEX_ADDR_DXDY
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz
} else {
BEGIN_ACCEL(13);
OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, 0);
@@ -1655,9 +1867,9 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
R500_DY_S_SWIZ_R |
R500_DY_T_SWIZ_R |
R500_DY_R_SWIZ_R |
- R500_DY_Q_SWIZ_R));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ R500_DY_Q_SWIZ_R)); // TEX_ADDR_DXDY
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz
}
OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT |
@@ -1701,13 +1913,14 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
FINISH_ACCEL();
}
- BEGIN_ACCEL(3);
+ BEGIN_ACCEL(4);
OUT_ACCEL_REG(R300_RB3D_COLOROFFSET0, dst_offset);
OUT_ACCEL_REG(R300_RB3D_COLORPITCH0, colorpitch);
blendcntl = RADEONGetBlendCntl(op, pMaskPicture, pDstPicture->format);
OUT_ACCEL_REG(R300_RB3D_BLENDCNTL, blendcntl | R300_ALPHA_BLEND_ENABLE | R300_READ_ENABLE);
+ OUT_ACCEL_REG(R300_RB3D_ABLENDCNTL, 0);
FINISH_ACCEL();
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index aa756f71..f5282cc2 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -106,6 +106,15 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
dstyoff = 0;
#endif
+#if 0
+ ErrorF("dst_offset: 0x%x\n", dst_offset);
+ ErrorF("dst_pitch: 0x%x\n", dst_pitch);
+ ErrorF("dstxoff: 0x%x\n", dstxoff);
+ ErrorF("dstyoff: 0x%x\n", dstyoff);
+ ErrorF("src_offset: 0x%x\n", pPriv->src_offset);
+ ErrorF("src_pitch: 0x%x\n", pPriv->src_pitch);
+#endif
+
if (!info->XInited3D)
RADEONInit3DEngine(pScrn);
@@ -122,6 +131,10 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
if (IS_R300_3D || IS_R500_3D) {
CARD32 output_fmt;
+ int has_tcl = ((info->ChipFamily != CHIP_FAMILY_RS690) &&
+ (info->ChipFamily != CHIP_FAMILY_RS740) &&
+ (info->ChipFamily != CHIP_FAMILY_RS400) &&
+ (info->ChipFamily != CHIP_FAMILY_RV515));
switch (pPixmap->drawable.bitsPerPixel) {
case 16:
@@ -191,36 +204,154 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
txenable = R300_TEX_0_ENABLE;
- BEGIN_VIDEO(7);
- OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_0,
- ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) |
- (0 << R300_SKIP_DWORDS_0_SHIFT) |
- (0 << R300_DST_VEC_LOC_0_SHIFT) |
- R300_SIGNED_0 |
- (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) |
- (0 << R300_SKIP_DWORDS_1_SHIFT) |
- (6 << R300_DST_VEC_LOC_1_SHIFT) |
- R300_LAST_VEC_1 |
- R300_SIGNED_1));
- OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0,
- ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) |
- (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) |
- (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_0_SHIFT) |
- (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_0_SHIFT) |
- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y)
- << R300_WRITE_ENA_0_SHIFT) |
- (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) |
- (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) |
- (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_1_SHIFT) |
- (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_1_SHIFT) |
- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y)
- << R300_WRITE_ENA_1_SHIFT)));
+ /* setup the VAP */
+ if (has_tcl) {
+ BEGIN_VIDEO(27);
+ OUT_VIDEO_REG(R300_VAP_CNTL_STATUS, 0);
+ OUT_VIDEO_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
+ OUT_VIDEO_REG(R300_VAP_CNTL, ((6 << R300_PVS_NUM_SLOTS_SHIFT) |
+ (5 << R300_PVS_NUM_CNTLRS_SHIFT) |
+ (4 << R300_PVS_NUM_FPUS_SHIFT) |
+ (12 << R300_VF_MAX_VTX_NUM_SHIFT)));
+ } else {
+ BEGIN_VIDEO(9);
+ OUT_VIDEO_REG(R300_VAP_CNTL_STATUS, R300_PVS_BYPASS);
+ OUT_VIDEO_REG(R300_VAP_CNTL, ((10 << R300_PVS_NUM_SLOTS_SHIFT) |
+ (5 << R300_PVS_NUM_CNTLRS_SHIFT) |
+ (4 << R300_PVS_NUM_FPUS_SHIFT) |
+ (5 << R300_VF_MAX_VTX_NUM_SHIFT)));
+ }
+
+ OUT_VIDEO_REG(R300_VAP_VTE_CNTL, R300_VTX_XY_FMT | R300_VTX_Z_FMT);
+ OUT_VIDEO_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0);
+
+ if (has_tcl) {
+ OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_0,
+ ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) |
+ (0 << R300_SKIP_DWORDS_0_SHIFT) |
+ (0 << R300_DST_VEC_LOC_0_SHIFT) |
+ R300_SIGNED_0 |
+ (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) |
+ (0 << R300_SKIP_DWORDS_1_SHIFT) |
+ (10 << R300_DST_VEC_LOC_1_SHIFT) |
+ R300_LAST_VEC_1 |
+ R300_SIGNED_1));
+ OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0,
+ ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) |
+ (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) |
+ (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_0_SHIFT) |
+ (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_0_SHIFT) |
+ ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
+ << R300_WRITE_ENA_0_SHIFT) |
+ (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) |
+ (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) |
+ (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_1_SHIFT) |
+ (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_1_SHIFT) |
+ ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
+ << R300_WRITE_ENA_1_SHIFT)));
+ } else {
+ OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_0,
+ ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) |
+ (0 << R300_SKIP_DWORDS_0_SHIFT) |
+ (0 << R300_DST_VEC_LOC_0_SHIFT) |
+ R300_SIGNED_0 |
+ (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) |
+ (0 << R300_SKIP_DWORDS_1_SHIFT) |
+ (6 << R300_DST_VEC_LOC_1_SHIFT) |
+ R300_LAST_VEC_1 |
+ R300_SIGNED_1));
+ OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0,
+ ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) |
+ (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) |
+ (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_0_SHIFT) |
+ (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_0_SHIFT) |
+ ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y)
+ << R300_WRITE_ENA_0_SHIFT) |
+ (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) |
+ (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) |
+ (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_1_SHIFT) |
+ (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_1_SHIFT) |
+ ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y)
+ << R300_WRITE_ENA_1_SHIFT)));
+ }
+
+ /* setup vertex shader */
+ if (has_tcl) {
+ OUT_VIDEO_REG(R300_VAP_PVS_CODE_CNTL_0,
+ ((0 << R300_PVS_FIRST_INST_SHIFT) |
+ (1 << R300_PVS_XYZW_VALID_INST_SHIFT) |
+ (1 << R300_PVS_LAST_INST_SHIFT)));
+ OUT_VIDEO_REG(R300_VAP_PVS_CODE_CNTL_1,
+ (1 << R300_PVS_LAST_VTX_SRC_INST_SHIFT));
+ OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
+
+ OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_DST_OPCODE(R300_VE_ADD) |
+ R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
+ R300_PVS_DST_OFFSET(0) |
+ R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
+ R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
+ OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(0) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
+ OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(0) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+ OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(0) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+
+ OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_DST_OPCODE(R300_VE_ADD) |
+ R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
+ R300_PVS_DST_OFFSET(1) |
+ R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
+ R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
+ OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(10) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
+ OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(10) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+ OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(10) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+
+ OUT_VIDEO_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0);
+
+ OUT_VIDEO_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000);
+ OUT_VIDEO_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000);
+ OUT_VIDEO_REG(R300_VAP_GB_HORZ_CLIP_ADJ, 0x3f800000);
+ OUT_VIDEO_REG(R300_VAP_GB_HORZ_DISC_ADJ, 0x3f800000);
+ OUT_VIDEO_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
+ }
OUT_VIDEO_REG(R300_VAP_OUT_VTX_FMT_0, R300_VTX_POS_PRESENT);
OUT_VIDEO_REG(R300_VAP_OUT_VTX_FMT_1, (2 << R300_TEX_0_COMP_CNT_SHIFT));
-
- OUT_VIDEO_REG(R300_TX_INVALTAGS, 0);
- OUT_VIDEO_REG(R300_TX_ENABLE, txenable);
OUT_VIDEO_REG(R300_US_OUT_FMT_0, output_fmt);
FINISH_VIDEO();
@@ -238,7 +369,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R300_RS_SEL_T(R300_RS_SEL_C1) |
R300_RS_SEL_R(R300_RS_SEL_K0) |
R300_RS_SEL_Q(R300_RS_SEL_K1)));
- OUT_VIDEO_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6));
+ OUT_VIDEO_REG(R300_RS_INST_COUNT, R300_TX_OFFSET_RS(6));
OUT_VIDEO_REG(R300_RS_INST_0, R300_RS_INST_TEX_CN_WRITE);
OUT_VIDEO_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX);
OUT_VIDEO_REG(R300_US_PIXSIZE, 0);
@@ -325,11 +456,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
(R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
(R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT)));
- OUT_VIDEO_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6));
-
- OUT_VIDEO_REG(R500_RS_INST_0, ((0 << R500_RS_INST_TEX_ID_SHIFT) |
- R500_RS_INST_TEX_CN_WRITE |
- (0 << R500_RS_INST_TEX_ADDR_SHIFT)));
+ OUT_VIDEO_REG(R300_RS_INST_COUNT, 0);
+ OUT_VIDEO_REG(R500_RS_INST_0, R500_RS_INST_TEX_CN_WRITE);
OUT_VIDEO_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
OUT_VIDEO_REG(R300_US_PIXSIZE, 0);
OUT_VIDEO_REG(R500_US_FC_CTRL, 0);
@@ -339,7 +467,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_US_CODE_RANGE_SIZE(1)));
OUT_VIDEO_REG(R500_US_CODE_OFFSET, 0);
OUT_VIDEO_REG(R500_GA_US_VECTOR_INDEX, 0);
-
+ // 7807
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
@@ -371,10 +499,11 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_DY_S_SWIZ_R |
R500_DY_T_SWIZ_R |
R500_DY_R_SWIZ_R |
- R500_DY_Q_SWIZ_R));
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+ R500_DY_Q_SWIZ_R)); // TEX_ADDR_DXDY
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz
+ // 0x78105
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT |
R500_INST_TEX_SEM_WAIT |
R500_INST_LAST |
@@ -390,13 +519,13 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_RGB_ADDR1_CONST |
R500_RGB_ADDR2(0) |
R500_RGB_ADDR2_CONST |
- R500_RGB_SRCP_OP_1_MINUS_2RGB0));
+ R500_RGB_SRCP_OP_1_MINUS_2RGB0)); //0x10040000
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
R500_ALPHA_ADDR1(0) |
R500_ALPHA_ADDR1_CONST |
R500_ALPHA_ADDR2(0) |
R500_ALPHA_ADDR2_CONST |
- R500_ALPHA_SRCP_OP_1_MINUS_2A0));
+ R500_ALPHA_SRCP_OP_1_MINUS_2A0)); //0x10040000
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
R500_ALU_RGB_R_SWIZ_A_R |
@@ -405,28 +534,33 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_ALU_RGB_SEL_B_SRC0 |
R500_ALU_RGB_R_SWIZ_B_1 |
R500_ALU_RGB_B_SWIZ_B_1 |
- R500_ALU_RGB_G_SWIZ_B_1));
+ R500_ALU_RGB_G_SWIZ_B_1));//0x00db0220
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD |
R500_ALPHA_SWIZ_A_A |
- R500_ALPHA_SWIZ_B_1));
+ R500_ALPHA_SWIZ_B_1));//0x00c0c000)
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD |
R500_ALU_RGBA_R_SWIZ_0 |
R500_ALU_RGBA_G_SWIZ_0 |
R500_ALU_RGBA_B_SWIZ_0 |
- R500_ALU_RGBA_A_SWIZ_0));
+ R500_ALU_RGBA_A_SWIZ_0));//0x20490000
FINISH_VIDEO();
}
- BEGIN_VIDEO(4);
+ BEGIN_VIDEO(6);
+ OUT_VIDEO_REG(R300_TX_INVALTAGS, 0);
+ OUT_VIDEO_REG(R300_TX_ENABLE, txenable);
OUT_VIDEO_REG(R300_RB3D_COLOROFFSET0, dst_offset);
OUT_VIDEO_REG(R300_RB3D_COLORPITCH0, colorpitch);
blendcntl = RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO;
- OUT_VIDEO_REG(R300_RB3D_BLENDCNTL, blendcntl | R300_ALPHA_BLEND_ENABLE | R300_READ_ENABLE);
+ OUT_VIDEO_REG(R300_RB3D_BLENDCNTL, blendcntl);
+ OUT_VIDEO_REG(R300_RB3D_ABLENDCNTL, 0);
+ FINISH_VIDEO();
+ BEGIN_VIDEO(1);
OUT_VIDEO_REG(R300_VAP_VTX_SIZE, VTX_DWORD_COUNT);
FINISH_VIDEO();
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 21:56:26 +0000