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-rw-r--r--src/evergreen_exa.c16
-rw-r--r--src/r600_exa.c16
-rw-r--r--src/radeon.h2
-rw-r--r--src/radeon_exa.c22
-rw-r--r--src/radeon_exa_funcs.c14
5 files changed, 25 insertions, 45 deletions
diff --git a/src/evergreen_exa.c b/src/evergreen_exa.c
index ae73e385..d93cb424 100644
--- a/src/evergreen_exa.c
+++ b/src/evergreen_exa.c
@@ -1402,7 +1402,7 @@ EVERGREENUploadToScreen(PixmapPtr pDst, int x, int y, int w, int h,
Bool r;
int i;
struct r600_accel_object src_obj, dst_obj;
- uint32_t tiling_flags = 0, pitch = 0, height, base_align;
+ uint32_t height, base_align;
if (bpp < 8)
return FALSE;
@@ -1411,14 +1411,10 @@ EVERGREENUploadToScreen(PixmapPtr pDst, int x, int y, int w, int h,
if (!driver_priv || !driver_priv->bo)
return FALSE;
- ret = radeon_bo_get_tiling(driver_priv->bo, &tiling_flags, &pitch);
- if (ret)
- ErrorF("radeon_bo_get_tiling failed\n");
-
/* If we know the BO won't be busy, don't bother with a scratch */
copy_dst = driver_priv->bo;
copy_pitch = pDst->devKind;
- if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) {
+ if (!(driver_priv->tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) {
if (!radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs)) {
flush = FALSE;
if (!radeon_bo_is_busy(driver_priv->bo, &dst_domain))
@@ -1519,7 +1515,7 @@ EVERGREENDownloadFromScreen(PixmapPtr pSrc, int x, int y, int w,
Bool flush = FALSE;
Bool r;
struct r600_accel_object src_obj, dst_obj;
- uint32_t tiling_flags = 0, pitch = 0, height, base_align;
+ uint32_t height, base_align;
if (bpp < 8)
return FALSE;
@@ -1528,14 +1524,10 @@ EVERGREENDownloadFromScreen(PixmapPtr pSrc, int x, int y, int w,
if (!driver_priv || !driver_priv->bo)
return FALSE;
- ret = radeon_bo_get_tiling(driver_priv->bo, &tiling_flags, &pitch);
- if (ret)
- ErrorF("radeon_bo_get_tiling failed\n");
-
/* If we know the BO won't end up in VRAM anyway, don't bother with a scratch */
copy_src = driver_priv->bo;
copy_pitch = pSrc->devKind;
- if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) {
+ if (!(driver_priv->tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) {
if (radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs)) {
src_domain = radeon_bo_get_src_domain(driver_priv->bo);
if ((src_domain & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM)) ==
diff --git a/src/r600_exa.c b/src/r600_exa.c
index 7736d243..c6a244c4 100644
--- a/src/r600_exa.c
+++ b/src/r600_exa.c
@@ -1784,7 +1784,7 @@ R600UploadToScreenCS(PixmapPtr pDst, int x, int y, int w, int h,
Bool r;
int i;
struct r600_accel_object src_obj, dst_obj;
- uint32_t tiling_flags = 0, pitch = 0, height, base_align;
+ uint32_t height, base_align;
if (bpp < 8)
return FALSE;
@@ -1793,14 +1793,10 @@ R600UploadToScreenCS(PixmapPtr pDst, int x, int y, int w, int h,
if (!driver_priv || !driver_priv->bo)
return FALSE;
- ret = radeon_bo_get_tiling(driver_priv->bo, &tiling_flags, &pitch);
- if (ret)
- ErrorF("radeon_bo_get_tiling failed\n");
-
/* If we know the BO won't be busy, don't bother with a scratch */
copy_dst = driver_priv->bo;
copy_pitch = pDst->devKind;
- if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) {
+ if (!(driver_priv->tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) {
if (!radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs)) {
flush = FALSE;
if (!radeon_bo_is_busy(driver_priv->bo, &dst_domain))
@@ -1901,7 +1897,7 @@ R600DownloadFromScreenCS(PixmapPtr pSrc, int x, int y, int w,
Bool flush = FALSE;
Bool r;
struct r600_accel_object src_obj, dst_obj;
- uint32_t tiling_flags = 0, pitch = 0, height, base_align;
+ uint32_t height, base_align;
if (bpp < 8)
return FALSE;
@@ -1910,14 +1906,10 @@ R600DownloadFromScreenCS(PixmapPtr pSrc, int x, int y, int w,
if (!driver_priv || !driver_priv->bo)
return FALSE;
- ret = radeon_bo_get_tiling(driver_priv->bo, &tiling_flags, &pitch);
- if (ret)
- ErrorF("radeon_bo_get_tiling failed\n");
-
/* If we know the BO won't end up in VRAM anyway, don't bother with a scratch */
copy_src = driver_priv->bo;
copy_pitch = pSrc->devKind;
- if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) {
+ if (!(driver_priv->tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) {
if (radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs)) {
src_domain = radeon_bo_get_src_domain(driver_priv->bo);
if ((src_domain & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM)) ==
diff --git a/src/radeon.h b/src/radeon.h
index a6d20d71..9283c4dd 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -495,7 +495,7 @@ typedef struct _atomBiosHandle *atomBiosHandlePtr;
struct radeon_exa_pixmap_priv {
struct radeon_bo *bo;
- int flags;
+ uint32_t tiling_flags;
Bool bo_mapped;
};
diff --git a/src/radeon_exa.c b/src/radeon_exa.c
index 1c647b94..c11c938a 100644
--- a/src/radeon_exa.c
+++ b/src/radeon_exa.c
@@ -130,6 +130,13 @@ static Bool RADEONPixmapIsColortiled(PixmapPtr pPix)
{
RINFO_FROM_SCREEN(pPix->drawable.pScreen);
+#ifdef XF86DRM_MODE
+ if (info->cs) {
+ /* Taken care of by the kernel relocation handling */
+ return FALSE;
+ }
+#endif
+
/* This doesn't account for the back buffer, which we may want to wrap in
* a pixmap at some point for the purposes of DRI buffer moves.
*/
@@ -308,7 +315,6 @@ Bool RADEONPrepareAccess_CS(PixmapPtr pPix, int index)
#endif
Bool flush = FALSE;
int ret;
- uint32_t tiling_flags = 0, pitch = 0;
#if X_BYTE_ORDER == X_BIG_ENDIAN
/* May need to handle byte swapping in DownloadFrom/UploadToScreen */
@@ -320,12 +326,8 @@ Bool RADEONPrepareAccess_CS(PixmapPtr pPix, int index)
if (!driver_priv)
return FALSE;
- /* check if we are tiled */
- ret = radeon_bo_get_tiling(driver_priv->bo, &tiling_flags, &pitch);
- if (ret)
- return FALSE;
/* untile in DFS/UTS */
- if (tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))
+ if (driver_priv->tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))
return FALSE;
/* if we have more refs than just the BO then flush */
@@ -505,8 +507,8 @@ void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height,
return NULL;
}
- if (tiling)
- radeon_bo_set_tiling(new_priv->bo, tiling, *new_pitch);
+ if (tiling && !radeon_bo_set_tiling(new_priv->bo, tiling, *new_pitch))
+ new_priv->tiling_flags = tiling;
return new_priv;
}
@@ -536,11 +538,15 @@ void radeon_set_pixmap_bo(PixmapPtr pPix, struct radeon_bo *bo)
driver_priv = exaGetPixmapDriverPrivate(pPix);
if (driver_priv) {
+ uint32_t pitch;
+
if (driver_priv->bo)
radeon_bo_unref(driver_priv->bo);
radeon_bo_ref(bo);
driver_priv->bo = bo;
+
+ radeon_bo_get_tiling(bo, &driver_priv->tiling_flags, &pitch);
}
}
diff --git a/src/radeon_exa_funcs.c b/src/radeon_exa_funcs.c
index e8c55718..b6767f08 100644
--- a/src/radeon_exa_funcs.c
+++ b/src/radeon_exa_funcs.c
@@ -474,7 +474,6 @@ RADEONUploadToScreenCS(PixmapPtr pDst, int x, int y, int w, int h,
Bool flush = TRUE;
Bool r;
int i;
- uint32_t tiling_flags = 0, pitch = 0;
if (bpp < 8)
return FALSE;
@@ -483,10 +482,6 @@ RADEONUploadToScreenCS(PixmapPtr pDst, int x, int y, int w, int h,
if (!driver_priv || !driver_priv->bo)
return FALSE;
- ret = radeon_bo_get_tiling(driver_priv->bo, &tiling_flags, &pitch);
- if (ret)
- ErrorF("radeon_bo_get_tiling failed\n");
-
#if X_BYTE_ORDER == X_BIG_ENDIAN
switch (bpp) {
case 32:
@@ -501,7 +496,7 @@ RADEONUploadToScreenCS(PixmapPtr pDst, int x, int y, int w, int h,
/* If we know the BO won't be busy, don't bother with a scratch */
copy_dst = driver_priv->bo;
copy_pitch = pDst->devKind;
- if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) {
+ if (!(driver_priv->tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) {
if (!radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs)) {
flush = FALSE;
if (!radeon_bo_is_busy(driver_priv->bo, &dst_domain))
@@ -580,7 +575,6 @@ RADEONDownloadFromScreenCS(PixmapPtr pSrc, int x, int y, int w,
int ret;
Bool flush = FALSE;
Bool r;
- uint32_t tiling_flags = 0, pitch = 0;
if (bpp < 8)
return FALSE;
@@ -589,10 +583,6 @@ RADEONDownloadFromScreenCS(PixmapPtr pSrc, int x, int y, int w,
if (!driver_priv || !driver_priv->bo)
return FALSE;
- ret = radeon_bo_get_tiling(driver_priv->bo, &tiling_flags, &pitch);
- if (ret)
- ErrorF("radeon_bo_get_tiling failed\n");
-
#if X_BYTE_ORDER == X_BIG_ENDIAN
switch (bpp) {
case 32:
@@ -607,7 +597,7 @@ RADEONDownloadFromScreenCS(PixmapPtr pSrc, int x, int y, int w,
/* If we know the BO won't end up in VRAM anyway, don't bother with a scratch */
copy_src = driver_priv->bo;
copy_pitch = pSrc->devKind;
- if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) {
+ if (!(driver_priv->tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) {
if (radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs)) {
src_domain = radeon_bo_get_src_domain(driver_priv->bo);
if ((src_domain & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM)) ==
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 16:58:52 +0000