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-rw-r--r--src/radeon.h214
1 files changed, 41 insertions, 173 deletions
diff --git a/src/radeon.h b/src/radeon.h
index 801d616a..7f4d0015 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -206,189 +206,26 @@ typedef struct {
CARD16 rr4_offset;
} RADEONBIOSInitTable;
-typedef struct {
- /* Common registers */
- CARD32 ovr_clr;
- CARD32 ovr_wid_left_right;
- CARD32 ovr_wid_top_bottom;
- CARD32 ov0_scale_cntl;
- CARD32 mpp_tb_config;
- CARD32 mpp_gp_config;
- CARD32 subpic_cntl;
- CARD32 viph_control;
- CARD32 i2c_cntl_1;
- CARD32 gen_int_cntl;
- CARD32 cap0_trig_cntl;
- CARD32 cap1_trig_cntl;
- CARD32 bus_cntl;
- CARD32 bios_4_scratch;
- CARD32 bios_5_scratch;
- CARD32 bios_6_scratch;
- CARD32 surface_cntl;
- CARD32 surfaces[8][3];
- CARD32 mc_agp_location;
- CARD32 mc_fb_location;
- CARD32 display_base_addr;
- CARD32 display2_base_addr;
- CARD32 ov0_base_addr;
-
- /* Other registers to save for VT switches */
- CARD32 dp_datatype;
- CARD32 rbbm_soft_reset;
- CARD32 clock_cntl_index;
- CARD32 amcgpio_en_reg;
- CARD32 amcgpio_mask;
-
- /* CRTC registers */
- CARD32 crtc_gen_cntl;
- CARD32 crtc_ext_cntl;
- CARD32 dac_cntl;
- CARD32 crtc_h_total_disp;
- CARD32 crtc_h_sync_strt_wid;
- CARD32 crtc_v_total_disp;
- CARD32 crtc_v_sync_strt_wid;
- CARD32 crtc_offset;
- CARD32 crtc_offset_cntl;
- CARD32 crtc_pitch;
- CARD32 disp_merge_cntl;
- CARD32 grph_buffer_cntl;
- CARD32 crtc_more_cntl;
- CARD32 crtc_tile_x0_y0;
-
- /* CRTC2 registers */
- CARD32 crtc2_gen_cntl;
- CARD32 dac_macro_cntl;
- CARD32 dac2_cntl;
- CARD32 disp_output_cntl;
- CARD32 disp_tv_out_cntl;
- CARD32 disp_hw_debug;
- CARD32 disp2_merge_cntl;
- CARD32 grph2_buffer_cntl;
- CARD32 crtc2_h_total_disp;
- CARD32 crtc2_h_sync_strt_wid;
- CARD32 crtc2_v_total_disp;
- CARD32 crtc2_v_sync_strt_wid;
- CARD32 crtc2_offset;
- CARD32 crtc2_offset_cntl;
- CARD32 crtc2_pitch;
- CARD32 crtc2_tile_x0_y0;
-
- /* Flat panel registers */
- CARD32 fp_crtc_h_total_disp;
- CARD32 fp_crtc_v_total_disp;
- CARD32 fp_gen_cntl;
- CARD32 fp2_gen_cntl;
- CARD32 fp_h_sync_strt_wid;
- CARD32 fp_h2_sync_strt_wid;
- CARD32 fp_horz_stretch;
- CARD32 fp_panel_cntl;
- CARD32 fp_v_sync_strt_wid;
- CARD32 fp_v2_sync_strt_wid;
- CARD32 fp_vert_stretch;
- CARD32 lvds_gen_cntl;
- CARD32 lvds_pll_cntl;
- CARD32 tmds_pll_cntl;
- CARD32 tmds_transmitter_cntl;
-
- /* Computed values for PLL */
- CARD32 dot_clock_freq;
- CARD32 pll_output_freq;
- int feedback_div;
- int reference_div;
- int post_div;
-
- /* PLL registers */
- unsigned ppll_ref_div;
- unsigned ppll_div_3;
- CARD32 htotal_cntl;
- CARD32 vclk_ecp_cntl;
-
- /* Computed values for PLL2 */
- CARD32 dot_clock_freq_2;
- CARD32 pll_output_freq_2;
- int feedback_div_2;
- int reference_div_2;
- int post_div_2;
-
- /* PLL2 registers */
- CARD32 p2pll_ref_div;
- CARD32 p2pll_div_0;
- CARD32 htotal_cntl2;
- CARD32 pixclks_cntl;
-
- /* Pallet */
- Bool palette_valid;
- CARD32 palette[256];
- CARD32 palette2[256];
-
- CARD32 rs480_unk_e30;
- CARD32 rs480_unk_e34;
- CARD32 rs480_unk_e38;
- CARD32 rs480_unk_e3c;
-
- /* TV out registers */
- CARD32 tv_master_cntl;
- CARD32 tv_htotal;
- CARD32 tv_hsize;
- CARD32 tv_hdisp;
- CARD32 tv_hstart;
- CARD32 tv_vtotal;
- CARD32 tv_vdisp;
- CARD32 tv_timing_cntl;
- CARD32 tv_vscaler_cntl1;
- CARD32 tv_vscaler_cntl2;
- CARD32 tv_sync_size;
- CARD32 tv_vrestart;
- CARD32 tv_hrestart;
- CARD32 tv_frestart;
- CARD32 tv_ftotal;
- CARD32 tv_clock_sel_cntl;
- CARD32 tv_clkout_cntl;
- CARD32 tv_data_delay_a;
- CARD32 tv_data_delay_b;
- CARD32 tv_dac_cntl;
- CARD32 tv_pll_cntl;
- CARD32 tv_pll_cntl1;
- CARD32 tv_pll_fine_cntl;
- CARD32 tv_modulator_cntl1;
- CARD32 tv_modulator_cntl2;
- CARD32 tv_frame_lock_cntl;
- CARD32 tv_pre_dac_mux_cntl;
- CARD32 tv_rgb_cntl;
- CARD32 tv_y_saw_tooth_cntl;
- CARD32 tv_y_rise_cntl;
- CARD32 tv_y_fall_cntl;
- CARD32 tv_uv_adr;
- CARD32 tv_upsamp_and_gain_cntl;
- CARD32 tv_gain_limit_settings;
- CARD32 tv_linear_gain_settings;
- CARD32 tv_crc_cntl;
- CARD32 tv_sync_cntl;
- CARD32 gpiopad_a;
- CARD32 pll_test_cntl;
-
- CARD16 h_code_timing[MAX_H_CODE_TIMING_LEN];
- CARD16 v_code_timing[MAX_V_CODE_TIMING_LEN];
-
-} RADEONSaveRec, *RADEONSavePtr;
-
#define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
#define RADEON_PLL_USE_REF_DIV (1 << 2)
+#define RADEON_PLL_LEGACY (1 << 3)
typedef struct {
CARD16 reference_freq;
CARD16 reference_div;
- CARD32 min_pll_freq;
- CARD32 max_pll_freq;
+ CARD32 pll_in_min;
+ CARD32 pll_in_max;
+ CARD32 pll_out_min;
+ CARD32 pll_out_max;
CARD16 xclk;
CARD32 min_ref_div;
CARD32 max_ref_div;
+ CARD32 min_post_div;
+ CARD32 max_post_div;
CARD32 min_feedback_div;
CARD32 max_feedback_div;
- CARD32 pll_in_min;
- CARD32 pll_in_max;
CARD32 best_vco;
} RADEONPLLRec, *RADEONPLLPtr;
@@ -421,6 +258,18 @@ typedef enum {
CHIP_FAMILY_R420, /* R420/R423/M18 */
CHIP_FAMILY_RV410, /* RV410, M26 */
CHIP_FAMILY_RS400, /* xpress 200, 200m (RS400/410/480) */
+ CHIP_FAMILY_RV515, /* rv515 */
+ CHIP_FAMILY_R520, /* r520 */
+ CHIP_FAMILY_RV530, /* rv530 */
+ CHIP_FAMILY_R580, /* r580 */
+ CHIP_FAMILY_RV560, /* rv560 */
+ CHIP_FAMILY_RV570, /* rv570 */
+ CHIP_FAMILY_RS690,
+ CHIP_FAMILY_R600, /* r60 */
+ CHIP_FAMILY_R630,
+ CHIP_FAMILY_RV610,
+ CHIP_FAMILY_RV630,
+ CHIP_FAMILY_RS740,
CHIP_FAMILY_LAST
} RADEONChipFamily;
@@ -441,6 +290,8 @@ typedef enum {
(info->ChipFamily == CHIP_FAMILY_RV410) || \
(info->ChipFamily == CHIP_FAMILY_RS400))
+#define IS_AVIVO_VARIANT ((info->ChipFamily >= CHIP_FAMILY_RV515))
+
/*
* Errata workarounds
*/
@@ -475,6 +326,8 @@ typedef enum {
CARD_PCIE
} RADEONCardType;
+typedef struct _atomBiosHandle *atomBiosHandlePtr;
+
typedef struct {
CARD32 pci_device_id;
RADEONChipFamily chip_family;
@@ -500,6 +353,7 @@ typedef struct {
CARD32 gartLocation;
CARD32 mc_fb_location;
CARD32 mc_agp_location;
+ CARD32 mc_agp_location_hi;
void *MMIO; /* Map of MMIO region */
void *FB; /* Map of frame buffer */
@@ -542,8 +396,8 @@ typedef struct {
Bool IsDDR;
int DispPriority;
- RADEONSaveRec SavedReg; /* Original (text) mode */
- RADEONSaveRec ModeReg; /* Current mode */
+ RADEONSavePtr SavedReg; /* Original (text) mode */
+ RADEONSavePtr ModeReg; /* Current mode */
Bool (*CloseScreen)(int, ScreenPtr);
void (*BlockHandler)(int, pointer, pointer, pointer);
@@ -856,6 +710,10 @@ typedef struct {
#endif
RADEONExtTMDSChip ext_tmds_chip;
+ atomBiosHandlePtr atomBIOS;
+ unsigned long FbFreeStart, FbFreeSize;
+ unsigned char* BIOSCopy;
+
/* output enable masks for outputs shared across connectors */
int output_crt1;
int output_crt2;
@@ -867,6 +725,13 @@ typedef struct {
Rotation rotation;
void (*PointerMoved)(int, int, int);
CreateScreenResourcesProcPtr CreateScreenResources;
+
+
+ Bool IsSecondary;
+ Bool IsPrimary;
+
+ Bool r600_shadow_fb;
+ void *fb_shadow;
} RADEONInfoRec, *RADEONInfoPtr;
#define RADEONWaitForFifo(pScrn, entries) \
@@ -894,6 +759,9 @@ extern void RADEONEngineRestore(ScrnInfoPtr pScrn);
extern unsigned RADEONINPLL(ScrnInfoPtr pScrn, int addr);
extern void RADEONOUTPLL(ScrnInfoPtr pScrn, int addr, CARD32 data);
+extern unsigned RADEONINMC(ScrnInfoPtr pScrn, int addr);
+extern void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, CARD32 data);
+
extern void RADEONWaitForVerticalSync(ScrnInfoPtr pScrn);
extern void RADEONWaitForVerticalSync2(ScrnInfoPtr pScrn);
@@ -987,7 +855,7 @@ extern void RADEONBlank(ScrnInfoPtr pScrn);
extern void RADEONDisplayPowerManagementSet(ScrnInfoPtr pScrn,
int PowerManagementMode,
int flags);
-extern Bool RADEONAllocateControllers(ScrnInfoPtr pScrn);
+extern Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask);
extern Bool RADEONAllocateConnectors(ScrnInfoPtr pScrn);
extern int RADEONValidateMergeModes(ScrnInfoPtr pScrn);
extern int RADEONValidateDDCModes(ScrnInfoPtr pScrn1, char **ppModeName,
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-20 06:44:58 +0000