diff options
Diffstat (limited to 'src')
83 files changed, 956 insertions, 58706 deletions
diff --git a/src/AtomBios/CD_Operations.c b/src/AtomBios/CD_Operations.c deleted file mode 100644 index f8b47e3e..00000000 --- a/src/AtomBios/CD_Operations.c +++ /dev/null @@ -1,983 +0,0 @@ -/* - * Copyright 2006-2007 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/** - -Module Name: - - CD_Operations.c - -Abstract: - - Functions Implementing Command Operations and other common functions - -Revision History: - - NEG:27.09.2002 Initiated. ---*/ -#define __SW_4 - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include <X11/Xos.h> -#include "xorg-server.h" -#include "compiler.h" - -#include "Decoder.h" - -VOID PutDataRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData); -VOID PutDataPS(PARSER_TEMP_DATA STACK_BASED * pParserTempData); -VOID PutDataWS(PARSER_TEMP_DATA STACK_BASED * pParserTempData); -VOID PutDataFB(PARSER_TEMP_DATA STACK_BASED * pParserTempData); -VOID PutDataPLL(PARSER_TEMP_DATA STACK_BASED * pParserTempData); -VOID PutDataMC(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - -UINT32 GetParametersDirect32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); -UINT32 GetParametersDirect16(PARSER_TEMP_DATA STACK_BASED * pParserTempData); -UINT32 GetParametersDirect8(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - -UINT32 GetParametersRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData); -UINT32 GetParametersPS(PARSER_TEMP_DATA STACK_BASED * pParserTempData); -UINT32 GetParametersWS(PARSER_TEMP_DATA STACK_BASED * pParserTempData); -UINT32 GetParametersFB(PARSER_TEMP_DATA STACK_BASED * pParserTempData); -UINT32 GetParametersPLL(PARSER_TEMP_DATA STACK_BASED * pParserTempData); -UINT32 GetParametersMC(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - -VOID SkipParameters16(PARSER_TEMP_DATA STACK_BASED * pParserTempData); -VOID SkipParameters8(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - -UINT32 GetParametersIndirect(PARSER_TEMP_DATA STACK_BASED * pParserTempData); -UINT32 GetParametersDirect(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - -UINT16* GetDataMasterTablePointer(DEVICE_DATA STACK_BASED* pDeviceData); -UINT8 GetTrueIndexInMasterTable(PARSER_TEMP_DATA STACK_BASED * pParserTempData, UINT8 IndexInMasterTable); - - -WRITE_IO_FUNCTION WritePCIFunctions[8] = { - WritePCIReg32, - WritePCIReg16, WritePCIReg16, WritePCIReg16, - WritePCIReg8,WritePCIReg8,WritePCIReg8,WritePCIReg8 -}; -WRITE_IO_FUNCTION WriteIOFunctions[8] = { - WriteSysIOReg32, - WriteSysIOReg16,WriteSysIOReg16,WriteSysIOReg16, - WriteSysIOReg8,WriteSysIOReg8,WriteSysIOReg8,WriteSysIOReg8 -}; -READ_IO_FUNCTION ReadPCIFunctions[8] = { - (READ_IO_FUNCTION)ReadPCIReg32, - (READ_IO_FUNCTION)ReadPCIReg16, - (READ_IO_FUNCTION)ReadPCIReg16, - (READ_IO_FUNCTION)ReadPCIReg16, - (READ_IO_FUNCTION)ReadPCIReg8, - (READ_IO_FUNCTION)ReadPCIReg8, - (READ_IO_FUNCTION)ReadPCIReg8, - (READ_IO_FUNCTION)ReadPCIReg8 -}; -READ_IO_FUNCTION ReadIOFunctions[8] = { - (READ_IO_FUNCTION)ReadSysIOReg32, - (READ_IO_FUNCTION)ReadSysIOReg16, - (READ_IO_FUNCTION)ReadSysIOReg16, - (READ_IO_FUNCTION)ReadSysIOReg16, - (READ_IO_FUNCTION)ReadSysIOReg8, - (READ_IO_FUNCTION)ReadSysIOReg8, - (READ_IO_FUNCTION)ReadSysIOReg8, - (READ_IO_FUNCTION)ReadSysIOReg8 -}; -READ_IO_FUNCTION GetParametersDirectArray[8]={ - GetParametersDirect32, - GetParametersDirect16,GetParametersDirect16,GetParametersDirect16, - GetParametersDirect8,GetParametersDirect8,GetParametersDirect8, - GetParametersDirect8 -}; - -COMMANDS_DECODER PutDataFunctions[6] = { - PutDataRegister, - PutDataPS, - PutDataWS, - PutDataFB, - PutDataPLL, - PutDataMC -}; -CD_GET_PARAMETERS GetDestination[6] = { - GetParametersRegister, - GetParametersPS, - GetParametersWS, - GetParametersFB, - GetParametersPLL, - GetParametersMC -}; - -COMMANDS_DECODER SkipDestination[6] = { - SkipParameters16, - SkipParameters8, - SkipParameters8, - SkipParameters8, - SkipParameters8, - SkipParameters8 -}; - -CD_GET_PARAMETERS GetSource[8] = { - GetParametersRegister, - GetParametersPS, - GetParametersWS, - GetParametersFB, - GetParametersIndirect, - GetParametersDirect, - GetParametersPLL, - GetParametersMC -}; - -UINT32 AlignmentMask[8] = {0xFFFFFFFF,0xFFFF,0xFFFF,0xFFFF,0xFF,0xFF,0xFF,0xFF}; -UINT8 SourceAlignmentShift[8] = {0,0,8,16,0,8,16,24}; -UINT8 DestinationAlignmentShift[4] = {0,8,16,24}; - -#define INDIRECTIO_ID 1 -#define INDIRECTIO_END_OF_ID 9 - -VOID IndirectIOCommand(PARSER_TEMP_DATA STACK_BASED * pParserTempData); -VOID IndirectIOCommand_MOVE(PARSER_TEMP_DATA STACK_BASED * pParserTempData, UINT32 temp); -VOID IndirectIOCommand_MOVE_INDEX(PARSER_TEMP_DATA STACK_BASED * pParserTempData); -VOID IndirectIOCommand_MOVE_ATTR(PARSER_TEMP_DATA STACK_BASED * pParserTempData); -VOID IndirectIOCommand_MOVE_DATA(PARSER_TEMP_DATA STACK_BASED * pParserTempData); -VOID IndirectIOCommand_SET(PARSER_TEMP_DATA STACK_BASED * pParserTempData); -VOID IndirectIOCommand_CLEAR(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - - -INDIRECT_IO_PARSER_COMMANDS IndirectIOParserCommands[10]={ - {IndirectIOCommand,1}, - {IndirectIOCommand,2}, - {ReadIndReg32,3}, - {WriteIndReg32,3}, - {IndirectIOCommand_CLEAR,3}, - {IndirectIOCommand_SET,3}, - {IndirectIOCommand_MOVE_INDEX,4}, - {IndirectIOCommand_MOVE_ATTR,4}, - {IndirectIOCommand_MOVE_DATA,4}, - {IndirectIOCommand,3} -}; - - -VOID IndirectIOCommand(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ -} - - -VOID IndirectIOCommand_MOVE_INDEX(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->IndirectData &= ~((0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1])) << pParserTempData->IndirectIOTablePointer[3]); - pParserTempData->IndirectData |=(((pParserTempData->Index >> pParserTempData->IndirectIOTablePointer[2]) & - (0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1]))) << pParserTempData->IndirectIOTablePointer[3]); -} - -VOID IndirectIOCommand_MOVE_ATTR(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->IndirectData &= ~((0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1])) << pParserTempData->IndirectIOTablePointer[3]); - pParserTempData->IndirectData |=(((pParserTempData->AttributesData >> pParserTempData->IndirectIOTablePointer[2]) - & (0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1]))) << pParserTempData->IndirectIOTablePointer[3]); -} - -VOID IndirectIOCommand_MOVE_DATA(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->IndirectData &= ~((0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1])) << pParserTempData->IndirectIOTablePointer[3]); - pParserTempData->IndirectData |=(((pParserTempData->DestData32 >> pParserTempData->IndirectIOTablePointer[2]) - & (0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1]))) << pParserTempData->IndirectIOTablePointer[3]); -} - - -VOID IndirectIOCommand_SET(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->IndirectData |= ((0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1])) << pParserTempData->IndirectIOTablePointer[2]); -} - -VOID IndirectIOCommand_CLEAR(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->IndirectData &= ~((0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1])) << pParserTempData->IndirectIOTablePointer[2]); -} - - -UINT32 IndirectInputOutput(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - // if ((pParserTempData->IndirectData & 0x7f)==INDIRECT_IO_MM) pParserTempData->IndirectData|=pParserTempData->CurrentPortID; -// pParserTempData->IndirectIOTablePointer=pParserTempData->IndirectIOTable; - while (*pParserTempData->IndirectIOTablePointer) - { - if ((pParserTempData->IndirectIOTablePointer[0] == INDIRECTIO_ID) && - (pParserTempData->IndirectIOTablePointer[1] == pParserTempData->IndirectData)) - { - pParserTempData->IndirectIOTablePointer+=IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].csize; - while (*pParserTempData->IndirectIOTablePointer != INDIRECTIO_END_OF_ID) - { - IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].func(pParserTempData); - pParserTempData->IndirectIOTablePointer+=IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].csize; - } - pParserTempData->IndirectIOTablePointer-=UINT16LE_TO_CPU(ldw_u((uint16_t *)(pParserTempData->IndirectIOTablePointer+1))); - pParserTempData->IndirectIOTablePointer++; - return pParserTempData->IndirectData; - } else pParserTempData->IndirectIOTablePointer+=IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].csize; - } - return 0; -} - - - -VOID PutDataRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->Index=(UINT32)UINT16LE_TO_CPU(pParserTempData->pCmd->Parameters.WordXX.PA_Destination); - pParserTempData->Index+=pParserTempData->CurrentRegBlock; - switch(pParserTempData->Multipurpose.CurrentPort){ - case ATI_RegsPort: - if (pParserTempData->CurrentPortID == INDIRECT_IO_MM) - { - if (pParserTempData->Index==0) pParserTempData->DestData32 <<= 2; - WriteReg32( pParserTempData); - } else - { - pParserTempData->IndirectData=pParserTempData->CurrentPortID+INDIRECT_IO_WRITE; - IndirectInputOutput(pParserTempData); - } - break; - case PCI_Port: - WritePCIFunctions[pParserTempData->pCmd->Header.Attribute.SourceAlignment](pParserTempData); - break; - case SystemIO_Port: - WriteIOFunctions[pParserTempData->pCmd->Header.Attribute.SourceAlignment](pParserTempData); - break; - } -} - -VOID PutDataPS(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - stl_u(CPU_TO_UINT32LE(pParserTempData->DestData32), - pParserTempData->pDeviceData->pParameterSpace+pParserTempData->pCmd->Parameters.ByteXX.PA_Destination); -} - -VOID PutDataWS(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - if (pParserTempData->pCmd->Parameters.ByteXX.PA_Destination < WS_QUOTIENT_C) - *(pParserTempData->pWorkingTableData->pWorkSpace+pParserTempData->pCmd->Parameters.ByteXX.PA_Destination) = pParserTempData->DestData32; - else - switch (pParserTempData->pCmd->Parameters.ByteXX.PA_Destination) - { - case WS_REMINDER_C: - pParserTempData->MultiplicationOrDivision.Division.Reminder32=pParserTempData->DestData32; - break; - case WS_QUOTIENT_C: - pParserTempData->MultiplicationOrDivision.Division.Quotient32=pParserTempData->DestData32; - break; - case WS_DATAPTR_C: -#ifndef UEFI_BUILD - pParserTempData->CurrentDataBlock=(UINT16)pParserTempData->DestData32; -#else - pParserTempData->CurrentDataBlock=(UINTN)pParserTempData->DestData32; -#endif - break; - case WS_SHIFT_C: - pParserTempData->Shift2MaskConverter=(UINT8)pParserTempData->DestData32; - break; - case WS_FB_WINDOW_C: - pParserTempData->CurrentFB_Window=pParserTempData->DestData32; - break; - case WS_ATTRIBUTES_C: - pParserTempData->AttributesData=(UINT16)pParserTempData->DestData32; - break; - case WS_REGPTR_C: - pParserTempData->CurrentRegBlock=(UINT16)pParserTempData->DestData32; - break; - } - -} - -VOID PutDataFB(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->Index=(UINT32)pParserTempData->pCmd->Parameters.ByteXX.PA_Destination; - //Make an Index from address first, then add to the Index - pParserTempData->Index+=(pParserTempData->CurrentFB_Window>>2); - WriteFrameBuffer32(pParserTempData); -} - -VOID PutDataPLL(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->Index=(UINT32)pParserTempData->pCmd->Parameters.ByteXX.PA_Destination; - WritePLL32( pParserTempData ); -} - -VOID PutDataMC(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->Index=(UINT32)pParserTempData->pCmd->Parameters.ByteXX.PA_Destination; - WriteMC32( pParserTempData ); -} - - -VOID SkipParameters8(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->pWorkingTableData->IP+=sizeof(UINT8); -} - -VOID SkipParameters16(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->pWorkingTableData->IP+=sizeof(UINT16); -} - - -UINT32 GetParametersRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->Index=UINT16LE_TO_CPU(ldw_u((uint16_t *)pParserTempData->pWorkingTableData->IP)); - pParserTempData->pWorkingTableData->IP+=sizeof(UINT16); - pParserTempData->Index+=pParserTempData->CurrentRegBlock; - switch(pParserTempData->Multipurpose.CurrentPort) - { - case PCI_Port: - return ReadPCIFunctions[pParserTempData->pCmd->Header.Attribute.SourceAlignment](pParserTempData); - case SystemIO_Port: - return ReadIOFunctions[pParserTempData->pCmd->Header.Attribute.SourceAlignment](pParserTempData); - case ATI_RegsPort: - default: - if (pParserTempData->CurrentPortID == INDIRECT_IO_MM) return ReadReg32( pParserTempData ); - else - { - pParserTempData->IndirectData=pParserTempData->CurrentPortID+INDIRECT_IO_READ; - return IndirectInputOutput(pParserTempData); - } - } -} - -UINT32 GetParametersPS(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - UINT32 data; - pParserTempData->Index=*pParserTempData->pWorkingTableData->IP; - pParserTempData->pWorkingTableData->IP+=sizeof(UINT8); - data = UINT32LE_TO_CPU(ldl_u(pParserTempData->pDeviceData->pParameterSpace+pParserTempData->Index)); - return data; -} - -UINT32 GetParametersWS(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->Index=*pParserTempData->pWorkingTableData->IP; - pParserTempData->pWorkingTableData->IP+=sizeof(UINT8); - if (pParserTempData->Index < WS_QUOTIENT_C) - return *(pParserTempData->pWorkingTableData->pWorkSpace+pParserTempData->Index); - else - switch (pParserTempData->Index) - { - case WS_REMINDER_C: - return pParserTempData->MultiplicationOrDivision.Division.Reminder32; - case WS_QUOTIENT_C: - return pParserTempData->MultiplicationOrDivision.Division.Quotient32; - case WS_DATAPTR_C: - return (UINT32)pParserTempData->CurrentDataBlock; - case WS_OR_MASK_C: - return ((UINT32)1) << pParserTempData->Shift2MaskConverter; - case WS_AND_MASK_C: - return ~(((UINT32)1) << pParserTempData->Shift2MaskConverter); - case WS_FB_WINDOW_C: - return pParserTempData->CurrentFB_Window; - case WS_ATTRIBUTES_C: - return pParserTempData->AttributesData; - case WS_REGPTR_C: - return (UINT32)pParserTempData->CurrentRegBlock; - } - return 0; - -} - -UINT32 GetParametersFB(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->Index=*pParserTempData->pWorkingTableData->IP; - pParserTempData->pWorkingTableData->IP+=sizeof(UINT8); - pParserTempData->Index+=(pParserTempData->CurrentFB_Window>>2); - return ReadFrameBuffer32(pParserTempData); -} - -UINT32 GetParametersPLL(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->Index=*pParserTempData->pWorkingTableData->IP; - pParserTempData->pWorkingTableData->IP+=sizeof(UINT8); - return ReadPLL32( pParserTempData ); -} - -UINT32 GetParametersMC(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->Index=*pParserTempData->pWorkingTableData->IP; - pParserTempData->pWorkingTableData->IP+=sizeof(UINT8); - return ReadMC32( pParserTempData ); -} - - -UINT32 GetParametersIndirect(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - UINT32 ret; - - pParserTempData->Index=UINT16LE_TO_CPU(ldw_u((uint16_t *)pParserTempData->pWorkingTableData->IP)); - pParserTempData->pWorkingTableData->IP+=sizeof(UINT16); - ret = UINT32LE_TO_CPU(ldl_u((UINT32*)(RELATIVE_TO_BIOS_IMAGE(pParserTempData->Index)+pParserTempData->CurrentDataBlock))); - return ret; -} - -UINT32 GetParametersDirect8(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->CD_Mask.SrcAlignment=alignmentByte0; - pParserTempData->Index=*(UINT8*)pParserTempData->pWorkingTableData->IP; - pParserTempData->pWorkingTableData->IP+=sizeof(UINT8); - return pParserTempData->Index; -} - -UINT32 GetParametersDirect16(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->CD_Mask.SrcAlignment=alignmentLowerWord; - pParserTempData->Index=UINT16LE_TO_CPU(ldw_u((uint16_t *)pParserTempData->pWorkingTableData->IP)); - pParserTempData->pWorkingTableData->IP+=sizeof(UINT16); - return pParserTempData->Index; -} - -UINT32 GetParametersDirect32(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->CD_Mask.SrcAlignment=alignmentDword; - pParserTempData->Index=UINT32LE_TO_CPU(ldl_u((UINT32*)pParserTempData->pWorkingTableData->IP)); - pParserTempData->pWorkingTableData->IP+=sizeof(UINT32); - return pParserTempData->Index; -} - - -UINT32 GetParametersDirect(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - return GetParametersDirectArray[pParserTempData->pCmd->Header.Attribute.SourceAlignment](pParserTempData); -} - - -VOID CommonSourceDataTransformation(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->SourceData32 >>= SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment]; - pParserTempData->SourceData32 &= AlignmentMask[pParserTempData->CD_Mask.SrcAlignment]; - pParserTempData->SourceData32 <<= DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment]; -} - -VOID CommonOperationDataTransformation(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->SourceData32 >>= SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment]; - pParserTempData->SourceData32 &= AlignmentMask[pParserTempData->CD_Mask.SrcAlignment]; - pParserTempData->DestData32 >>= DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment]; - pParserTempData->DestData32 &= AlignmentMask[pParserTempData->CD_Mask.SrcAlignment]; -} - -VOID ProcessMove(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - if (pParserTempData->CD_Mask.SrcAlignment!=alignmentDword) - { - pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); - } else - { - SkipDestination[pParserTempData->ParametersType.Destination](pParserTempData); - } - pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); - - if (pParserTempData->CD_Mask.SrcAlignment!=alignmentDword) - { - pParserTempData->DestData32 &= ~(AlignmentMask[pParserTempData->CD_Mask.SrcAlignment] << DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment]); - CommonSourceDataTransformation(pParserTempData); - pParserTempData->DestData32 |= pParserTempData->SourceData32; - } else - { - pParserTempData->DestData32=pParserTempData->SourceData32; - } - PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData); -} - -VOID ProcessMask(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - UINT8 src; - - pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); - src = pParserTempData->CD_Mask.SrcAlignment; - pParserTempData->SourceData32=GetParametersDirect(pParserTempData); - pParserTempData->Index=GetSource[pParserTempData->ParametersType.Source](pParserTempData); - pParserTempData->SourceData32 <<= DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment]; - pParserTempData->SourceData32 |= ~(AlignmentMask[pParserTempData->CD_Mask.SrcAlignment] << DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment]); - pParserTempData->DestData32 &= pParserTempData->SourceData32; - pParserTempData->Index >>= SourceAlignmentShift[src]; - pParserTempData->Index &= AlignmentMask[pParserTempData->CD_Mask.SrcAlignment]; - pParserTempData->Index <<= DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment]; - pParserTempData->DestData32 |= pParserTempData->Index; - PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData); -} - -VOID ProcessAnd(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); - pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); - pParserTempData->SourceData32 >>= SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment]; - pParserTempData->SourceData32 <<= DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment]; - pParserTempData->SourceData32 |= ~(AlignmentMask[pParserTempData->CD_Mask.SrcAlignment] << DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment]); - pParserTempData->DestData32 &= pParserTempData->SourceData32; - PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData); -} - -VOID ProcessOr(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); - pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); - CommonSourceDataTransformation(pParserTempData); - pParserTempData->DestData32 |= pParserTempData->SourceData32; - PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData); -} - -VOID ProcessXor(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); - pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); - CommonSourceDataTransformation(pParserTempData); - pParserTempData->DestData32 ^= pParserTempData->SourceData32; - PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData); -} - -VOID ProcessShl(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); - pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); - CommonSourceDataTransformation(pParserTempData); - pParserTempData->DestData32 <<= pParserTempData->SourceData32; - PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData); -} - -VOID ProcessShr(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); - pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); - CommonSourceDataTransformation(pParserTempData); - pParserTempData->DestData32 >>= pParserTempData->SourceData32; - PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData); -} - - -VOID ProcessADD(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); - pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); - CommonSourceDataTransformation(pParserTempData); - pParserTempData->DestData32 += pParserTempData->SourceData32; - PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData); -} - -VOID ProcessSUB(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); - pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); - CommonSourceDataTransformation(pParserTempData); - pParserTempData->DestData32 -= pParserTempData->SourceData32; - PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData); -} - -VOID ProcessMUL(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); - pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); - CommonOperationDataTransformation(pParserTempData); - pParserTempData->MultiplicationOrDivision.Multiplication.Low32Bit=pParserTempData->DestData32 * pParserTempData->SourceData32; -} - -VOID ProcessDIV(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); - pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); - - CommonOperationDataTransformation(pParserTempData); - pParserTempData->MultiplicationOrDivision.Division.Quotient32= - pParserTempData->DestData32 / pParserTempData->SourceData32; - pParserTempData->MultiplicationOrDivision.Division.Reminder32= - pParserTempData->DestData32 % pParserTempData->SourceData32; -} - - -VOID ProcessCompare(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); - pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); - - CommonOperationDataTransformation(pParserTempData); - - // Here we just set flags based on evaluation - if (pParserTempData->DestData32==pParserTempData->SourceData32) - pParserTempData->CompareFlags = Equal; - else - pParserTempData->CompareFlags = - (UINT8)((pParserTempData->DestData32<pParserTempData->SourceData32) ? Below : Above); - -} - -VOID ProcessClear(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); - - if (pParserTempData->ParametersType.Destination == 0 && - pParserTempData->Multipurpose.CurrentPort == ATI_RegsPort && - pParserTempData->Index == 0) { - pParserTempData->DestData32 = 0; - } else - pParserTempData->DestData32 &= ~(AlignmentMask[pParserTempData->CD_Mask.SrcAlignment] << SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment]); - PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData); - -} - -VOID ProcessShift(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - UINT32 mask = AlignmentMask[pParserTempData->CD_Mask.SrcAlignment] << SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment]; - pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); - pParserTempData->SourceData32=GetParametersDirect8(pParserTempData); - - // save original value of the destination - pParserTempData->Index = pParserTempData->DestData32 & ~mask; - pParserTempData->DestData32 &= mask; - - if (pParserTempData->pCmd->Header.Opcode < SHIFT_RIGHT_REG_OPCODE) - pParserTempData->DestData32 <<= pParserTempData->SourceData32; else - pParserTempData->DestData32 >>= pParserTempData->SourceData32; - - // Clear any bits shifted out of masked area... - pParserTempData->DestData32 &= mask; - // ... and restore the area outside of masked with original values - pParserTempData->DestData32 |= pParserTempData->Index; - - // write data back - PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData); -} - -VOID ProcessTest(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); - pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); - CommonOperationDataTransformation(pParserTempData); - pParserTempData->CompareFlags = - (UINT8)((pParserTempData->DestData32 & pParserTempData->SourceData32) ? NotEqual : Equal); - -} - -VOID ProcessSetFB_Base(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); - pParserTempData->SourceData32 >>= SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment]; - pParserTempData->SourceData32 &= AlignmentMask[pParserTempData->CD_Mask.SrcAlignment]; - pParserTempData->CurrentFB_Window=pParserTempData->SourceData32; -} - -VOID ProcessSwitch(PARSER_TEMP_DATA STACK_BASED * pParserTempData){ - pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); - pParserTempData->SourceData32 >>= SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment]; - pParserTempData->SourceData32 &= AlignmentMask[pParserTempData->CD_Mask.SrcAlignment]; - - while ( UINT16LE_TO_CPU(ldw_u((uint16_t *)pParserTempData->pWorkingTableData->IP)) != (((UINT16)NOP_OPCODE << 8)+NOP_OPCODE)) - { - if (*pParserTempData->pWorkingTableData->IP == 'c') - { - pParserTempData->pWorkingTableData->IP++; - pParserTempData->DestData32=GetParametersDirect(pParserTempData); - pParserTempData->Index=GetParametersDirect16(pParserTempData); - if (pParserTempData->SourceData32 == pParserTempData->DestData32) - { - pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(pParserTempData->Index); - return; - } - } - } - pParserTempData->pWorkingTableData->IP+=sizeof(UINT16); -} - - -VOID cmdSetDataBlock(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - UINT8 value; - UINT16* pMasterDataTable; - value=((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.ByteXX.PA_Destination; - if (value == 0) pParserTempData->CurrentDataBlock=0; else - { - if (value == DB_CURRENT_COMMAND_TABLE) - { - pParserTempData->CurrentDataBlock= (UINT16)(pParserTempData->pWorkingTableData->pTableHead-pParserTempData->pDeviceData->pBIOS_Image); - } else - { - pMasterDataTable = GetDataMasterTablePointer(pParserTempData->pDeviceData); - pParserTempData->CurrentDataBlock= UINT16LE_TO_CPU((TABLE_UNIT_TYPE)((PTABLE_UNIT_TYPE)pMasterDataTable)[value]); - } - } - pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_VALUE_BYTE); -} - -VOID cmdSet_ATI_Port(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->Multipurpose.CurrentPort=ATI_RegsPort; - pParserTempData->CurrentPortID = (UINT8)UINT16LE_TO_CPU(((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.WordXX.PA_Destination); - pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16); -} - -VOID cmdSet_Reg_Block(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->CurrentRegBlock = UINT16LE_TO_CPU(((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.WordXX.PA_Destination); - pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16); -} - - -//Atavism!!! Review!!! -VOID cmdSet_X_Port(PARSER_TEMP_DATA STACK_BASED * pParserTempData){ - pParserTempData->Multipurpose.CurrentPort=pParserTempData->ParametersType.Destination; - pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_ONLY); - -} - -VOID cmdDelay_Millisec(PARSER_TEMP_DATA STACK_BASED * pParserTempData){ - pParserTempData->SourceData32 = - ((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.ByteXX.PA_Destination; - DelayMilliseconds(pParserTempData); - pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_VALUE_BYTE); -} -VOID cmdDelay_Microsec(PARSER_TEMP_DATA STACK_BASED * pParserTempData){ - pParserTempData->SourceData32 = - ((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.ByteXX.PA_Destination; - DelayMicroseconds(pParserTempData); - pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_VALUE_BYTE); -} - -VOID ProcessPostChar(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->SourceData32 = - ((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.ByteXX.PA_Destination; - PostCharOutput(pParserTempData); - pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_VALUE_BYTE); -} - -VOID ProcessDebug(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->SourceData32 = - ((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.ByteXX.PA_Destination; - CallerDebugFunc(pParserTempData); - pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_VALUE_BYTE); -} - - -VOID ProcessDS(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->pWorkingTableData->IP+=UINT16LE_TO_CPU(((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.WordXX.PA_Destination)+sizeof(COMMAND_TYPE_OPCODE_OFFSET16); -} - - -VOID cmdCall_Table(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - UINT16* MasterTableOffset; - pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_VALUE_BYTE); - MasterTableOffset = GetCommandMasterTablePointer(pParserTempData->pDeviceData); - if(((PTABLE_UNIT_TYPE)MasterTableOffset)[((COMMAND_TYPE_OPCODE_VALUE_BYTE*)pParserTempData->pCmd)->Value]!=0 ) // if the offset is not ZERO - { - ATOM_TABLE_ATTRIBUTE lTableAttr; - - pParserTempData->CommandSpecific.IndexInMasterTable=GetTrueIndexInMasterTable(pParserTempData,((COMMAND_TYPE_OPCODE_VALUE_BYTE*)pParserTempData->pCmd)->Value); - - lTableAttr = GetCommandTableAttribute(pParserTempData->pWorkingTableData->pTableHead); - pParserTempData->Multipurpose.PS_SizeInDwordsUsedByCallingTable = (lTableAttr.PS_SizeInBytes >>2); - pParserTempData->pDeviceData->pParameterSpace+= - pParserTempData->Multipurpose.PS_SizeInDwordsUsedByCallingTable; - pParserTempData->Status=CD_CALL_TABLE; - pParserTempData->pCmd=(GENERIC_ATTRIBUTE_COMMAND*)MasterTableOffset; - } -} - - -VOID cmdNOP_(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ -} - - -static VOID NotImplemented(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->Status = CD_NOT_IMPLEMENTED; -} - - -VOID ProcessJump(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - if ((pParserTempData->ParametersType.Destination == NoCondition) || - (pParserTempData->ParametersType.Destination == pParserTempData->CompareFlags )) - { - - pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(UINT16LE_TO_CPU(((COMMAND_TYPE_OPCODE_OFFSET16*)pParserTempData->pWorkingTableData->IP)->CD_Offset16)); - } else - { - pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16); - } -} - -VOID ProcessJumpE(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - if ((pParserTempData->CompareFlags == Equal) || - (pParserTempData->CompareFlags == pParserTempData->ParametersType.Destination)) - { - - pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(UINT16LE_TO_CPU(((COMMAND_TYPE_OPCODE_OFFSET16*)pParserTempData->pWorkingTableData->IP)->CD_Offset16)); - } else - { - pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16); - } -} - -VOID ProcessJumpNE(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - if (pParserTempData->CompareFlags != Equal) - { - - pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(UINT16LE_TO_CPU(((COMMAND_TYPE_OPCODE_OFFSET16*)pParserTempData->pWorkingTableData->IP)->CD_Offset16)); - } else - { - pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16); - } -} - - - -COMMANDS_PROPERTIES CallTable[] = -{ - { NULL, 0,0}, - { ProcessMove, destRegister, sizeof(COMMAND_HEADER)}, - { ProcessMove, destParamSpace, sizeof(COMMAND_HEADER)}, - { ProcessMove, destWorkSpace, sizeof(COMMAND_HEADER)}, - { ProcessMove, destFrameBuffer, sizeof(COMMAND_HEADER)}, - { ProcessMove, destPLL, sizeof(COMMAND_HEADER)}, - { ProcessMove, destMC, sizeof(COMMAND_HEADER)}, - { ProcessAnd, destRegister, sizeof(COMMAND_HEADER)}, - { ProcessAnd, destParamSpace, sizeof(COMMAND_HEADER)}, - { ProcessAnd, destWorkSpace, sizeof(COMMAND_HEADER)}, - { ProcessAnd, destFrameBuffer, sizeof(COMMAND_HEADER)}, - { ProcessAnd, destPLL, sizeof(COMMAND_HEADER)}, - { ProcessAnd, destMC, sizeof(COMMAND_HEADER)}, - { ProcessOr, destRegister, sizeof(COMMAND_HEADER)}, - { ProcessOr, destParamSpace, sizeof(COMMAND_HEADER)}, - { ProcessOr, destWorkSpace, sizeof(COMMAND_HEADER)}, - { ProcessOr, destFrameBuffer, sizeof(COMMAND_HEADER)}, - { ProcessOr, destPLL, sizeof(COMMAND_HEADER)}, - { ProcessOr, destMC, sizeof(COMMAND_HEADER)}, - { ProcessShift, destRegister, sizeof(COMMAND_HEADER)}, - { ProcessShift, destParamSpace, sizeof(COMMAND_HEADER)}, - { ProcessShift, destWorkSpace, sizeof(COMMAND_HEADER)}, - { ProcessShift, destFrameBuffer, sizeof(COMMAND_HEADER)}, - { ProcessShift, destPLL, sizeof(COMMAND_HEADER)}, - { ProcessShift, destMC, sizeof(COMMAND_HEADER)}, - { ProcessShift, destRegister, sizeof(COMMAND_HEADER)}, - { ProcessShift, destParamSpace, sizeof(COMMAND_HEADER)}, - { ProcessShift, destWorkSpace, sizeof(COMMAND_HEADER)}, - { ProcessShift, destFrameBuffer, sizeof(COMMAND_HEADER)}, - { ProcessShift, destPLL, sizeof(COMMAND_HEADER)}, - { ProcessShift, destMC, sizeof(COMMAND_HEADER)}, - { ProcessMUL, destRegister, sizeof(COMMAND_HEADER)}, - { ProcessMUL, destParamSpace, sizeof(COMMAND_HEADER)}, - { ProcessMUL, destWorkSpace, sizeof(COMMAND_HEADER)}, - { ProcessMUL, destFrameBuffer, sizeof(COMMAND_HEADER)}, - { ProcessMUL, destPLL, sizeof(COMMAND_HEADER)}, - { ProcessMUL, destMC, sizeof(COMMAND_HEADER)}, - { ProcessDIV, destRegister, sizeof(COMMAND_HEADER)}, - { ProcessDIV, destParamSpace, sizeof(COMMAND_HEADER)}, - { ProcessDIV, destWorkSpace, sizeof(COMMAND_HEADER)}, - { ProcessDIV, destFrameBuffer, sizeof(COMMAND_HEADER)}, - { ProcessDIV, destPLL, sizeof(COMMAND_HEADER)}, - { ProcessDIV, destMC, sizeof(COMMAND_HEADER)}, - { ProcessADD, destRegister, sizeof(COMMAND_HEADER)}, - { ProcessADD, destParamSpace, sizeof(COMMAND_HEADER)}, - { ProcessADD, destWorkSpace, sizeof(COMMAND_HEADER)}, - { ProcessADD, destFrameBuffer, sizeof(COMMAND_HEADER)}, - { ProcessADD, destPLL, sizeof(COMMAND_HEADER)}, - { ProcessADD, destMC, sizeof(COMMAND_HEADER)}, - { ProcessSUB, destRegister, sizeof(COMMAND_HEADER)}, - { ProcessSUB, destParamSpace, sizeof(COMMAND_HEADER)}, - { ProcessSUB, destWorkSpace, sizeof(COMMAND_HEADER)}, - { ProcessSUB, destFrameBuffer, sizeof(COMMAND_HEADER)}, - { ProcessSUB, destPLL, sizeof(COMMAND_HEADER)}, - { ProcessSUB, destMC, sizeof(COMMAND_HEADER)}, - { cmdSet_ATI_Port, ATI_RegsPort, 0}, - { cmdSet_X_Port, PCI_Port, 0}, - { cmdSet_X_Port, SystemIO_Port, 0}, - { cmdSet_Reg_Block, 0, 0}, - { ProcessSetFB_Base,0, sizeof(COMMAND_HEADER)}, - { ProcessCompare, destRegister, sizeof(COMMAND_HEADER)}, - { ProcessCompare, destParamSpace, sizeof(COMMAND_HEADER)}, - { ProcessCompare, destWorkSpace, sizeof(COMMAND_HEADER)}, - { ProcessCompare, destFrameBuffer, sizeof(COMMAND_HEADER)}, - { ProcessCompare, destPLL, sizeof(COMMAND_HEADER)}, - { ProcessCompare, destMC, sizeof(COMMAND_HEADER)}, - { ProcessSwitch, 0, sizeof(COMMAND_HEADER)}, - { ProcessJump, NoCondition, 0}, - { ProcessJump, Equal, 0}, - { ProcessJump, Below, 0}, - { ProcessJump, Above, 0}, - { ProcessJumpE, Below, 0}, - { ProcessJumpE, Above, 0}, - { ProcessJumpNE, 0, 0}, - { ProcessTest, destRegister, sizeof(COMMAND_HEADER)}, - { ProcessTest, destParamSpace, sizeof(COMMAND_HEADER)}, - { ProcessTest, destWorkSpace, sizeof(COMMAND_HEADER)}, - { ProcessTest, destFrameBuffer, sizeof(COMMAND_HEADER)}, - { ProcessTest, destPLL, sizeof(COMMAND_HEADER)}, - { ProcessTest, destMC, sizeof(COMMAND_HEADER)}, - { cmdDelay_Millisec,0, 0}, - { cmdDelay_Microsec,0, 0}, - { cmdCall_Table, 0, 0}, - /*cmdRepeat*/ { NotImplemented, 0, 0}, - { ProcessClear, destRegister, sizeof(COMMAND_HEADER)}, - { ProcessClear, destParamSpace, sizeof(COMMAND_HEADER)}, - { ProcessClear, destWorkSpace, sizeof(COMMAND_HEADER)}, - { ProcessClear, destFrameBuffer, sizeof(COMMAND_HEADER)}, - { ProcessClear, destPLL, sizeof(COMMAND_HEADER)}, - { ProcessClear, destMC, sizeof(COMMAND_HEADER)}, - { cmdNOP_, 0, sizeof(COMMAND_TYPE_OPCODE_ONLY)}, - /*cmdEOT*/ { cmdNOP_, 0, sizeof(COMMAND_TYPE_OPCODE_ONLY)}, - { ProcessMask, destRegister, sizeof(COMMAND_HEADER)}, - { ProcessMask, destParamSpace, sizeof(COMMAND_HEADER)}, - { ProcessMask, destWorkSpace, sizeof(COMMAND_HEADER)}, - { ProcessMask, destFrameBuffer, sizeof(COMMAND_HEADER)}, - { ProcessMask, destPLL, sizeof(COMMAND_HEADER)}, - { ProcessMask, destMC, sizeof(COMMAND_HEADER)}, - /*cmdPost_Card*/ { ProcessPostChar, 0, 0}, - /*cmdBeep*/ { NotImplemented, 0, 0}, - /*cmdSave_Reg*/ { NotImplemented, 0, 0}, - /*cmdRestore_Reg*/{ NotImplemented, 0, 0}, - { cmdSetDataBlock, 0, 0}, - { ProcessXor, destRegister, sizeof(COMMAND_HEADER)}, - { ProcessXor, destParamSpace, sizeof(COMMAND_HEADER)}, - { ProcessXor, destWorkSpace, sizeof(COMMAND_HEADER)}, - { ProcessXor, destFrameBuffer, sizeof(COMMAND_HEADER)}, - { ProcessXor, destPLL, sizeof(COMMAND_HEADER)}, - { ProcessXor, destMC, sizeof(COMMAND_HEADER)}, - - { ProcessShl, destRegister, sizeof(COMMAND_HEADER)}, - { ProcessShl, destParamSpace, sizeof(COMMAND_HEADER)}, - { ProcessShl, destWorkSpace, sizeof(COMMAND_HEADER)}, - { ProcessShl, destFrameBuffer, sizeof(COMMAND_HEADER)}, - { ProcessShl, destPLL, sizeof(COMMAND_HEADER)}, - { ProcessShl, destMC, sizeof(COMMAND_HEADER)}, - - { ProcessShr, destRegister, sizeof(COMMAND_HEADER)}, - { ProcessShr, destParamSpace, sizeof(COMMAND_HEADER)}, - { ProcessShr, destWorkSpace, sizeof(COMMAND_HEADER)}, - { ProcessShr, destFrameBuffer, sizeof(COMMAND_HEADER)}, - { ProcessShr, destPLL, sizeof(COMMAND_HEADER)}, - { ProcessShr, destMC, sizeof(COMMAND_HEADER)}, - /*cmdDebug*/ { ProcessDebug, 0, 0}, - { ProcessDS, 0, 0}, - -}; - -// EOF diff --git a/src/AtomBios/Decoder.c b/src/AtomBios/Decoder.c deleted file mode 100644 index 73aac94a..00000000 --- a/src/AtomBios/Decoder.c +++ /dev/null @@ -1,258 +0,0 @@ -/* - * Copyright 2006-2007 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/** - -Module Name: - - Decoder.c - -Abstract: - - Commands Decoder - -Revision History: - - NEG:24.09.2002 Initiated. ---*/ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include <X11/Xos.h> -#include "xorg-server.h" - -#include "Decoder.h" - -#ifndef DISABLE_EASF - #include "easf.h" -#endif - - - -#define INDIRECT_IO_TABLE (((UINT16)(ULONG_PTR)&((ATOM_MASTER_LIST_OF_DATA_TABLES*)0)->IndirectIOAccess)/sizeof(TABLE_UNIT_TYPE) ) -extern COMMANDS_PROPERTIES CallTable[]; - - -UINT8 ProcessCommandProperties(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - UINT8 opcode=((COMMAND_HEADER*)pParserTempData->pWorkingTableData->IP)->Opcode; - pParserTempData->pWorkingTableData->IP+=CallTable[opcode].headersize; - pParserTempData->ParametersType.Destination=CallTable[opcode].destination; - pParserTempData->ParametersType.Source = pParserTempData->pCmd->Header.Attribute.Source; - pParserTempData->CD_Mask.SrcAlignment=pParserTempData->pCmd->Header.Attribute.SourceAlignment; - pParserTempData->CD_Mask.DestAlignment=pParserTempData->pCmd->Header.Attribute.DestinationAlignment; - return opcode; -} - -UINT16* GetCommandMasterTablePointer(DEVICE_DATA STACK_BASED* pDeviceData) -{ - UINT16 *MasterTableOffset; -#ifndef DISABLE_EASF - if (pDeviceData->format == TABLE_FORMAT_EASF) - { - /* - make MasterTableOffset point to EASF_ASIC_SETUP_TABLE structure, including usSize. - */ - MasterTableOffset = (UINT16 *) (pDeviceData->pBIOS_Image+(UINT16LE_TO_CPU(((EASF_ASIC_DESCRIPTOR*)pDeviceData->pBIOS_Image)->usAsicSetupTable_Offset)); - } else -#endif - { -#ifndef UEFI_BUILD - MasterTableOffset = (UINT16 *)(UINT16LE_TO_CPU(*(UINT16 *)(pDeviceData->pBIOS_Image+OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER)) + pDeviceData->pBIOS_Image); - MasterTableOffset = (UINT16 *)((ULONG)UINT16LE_TO_CPU(((ATOM_ROM_HEADER *)MasterTableOffset)->usMasterCommandTableOffset) + pDeviceData->pBIOS_Image ); - MasterTableOffset =(UINT16 *) &(((ATOM_MASTER_COMMAND_TABLE *)MasterTableOffset)->ListOfCommandTables); -#else - MasterTableOffset = (UINT16 *)(&(GetCommandMasterTable( )->ListOfCommandTables)); -#endif - } - return MasterTableOffset; -} - -UINT16* GetDataMasterTablePointer(DEVICE_DATA STACK_BASED* pDeviceData) -{ - UINT16 *MasterTableOffset; - -#ifndef UEFI_BUILD - MasterTableOffset = (UINT16 *)(UINT16LE_TO_CPU(*(UINT16 *)(pDeviceData->pBIOS_Image+OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER)) + pDeviceData->pBIOS_Image); - MasterTableOffset = (UINT16 *)((ULONG)(UINT16LE_TO_CPU(((ATOM_ROM_HEADER *)MasterTableOffset)->usMasterDataTableOffset)) + pDeviceData->pBIOS_Image ); - MasterTableOffset =(UINT16 *) &(((ATOM_MASTER_DATA_TABLE *)MasterTableOffset)->ListOfDataTables); -#else - MasterTableOffset = (UINT16 *)(&(GetDataMasterTable( )->ListOfDataTables)); -#endif - return MasterTableOffset; -} - - -UINT8 GetTrueIndexInMasterTable(PARSER_TEMP_DATA STACK_BASED * pParserTempData, UINT8 IndexInMasterTable) -{ -#ifndef DISABLE_EASF - UINT16 i; - if ( pParserTempData->pDeviceData->format == TABLE_FORMAT_EASF) - { -/* - Consider EASF_ASIC_SETUP_TABLE structure pointed by pParserTempData->pCmd as UINT16[] - ((UINT16*)pParserTempData->pCmd)[0] = EASF_ASIC_SETUP_TABLE.usSize; - ((UINT16*)pParserTempData->pCmd)[1+n*4] = usFunctionID; - usFunctionID has to be shifted left by 2 before compare it to the value provided by caller. -*/ - for (i=1; (i < ((UINT16*)pParserTempData->pCmd)[0] >> 1);i+=4) - if ((UINT8)(((UINT16*)pParserTempData->pCmd)[i] << 2)==(IndexInMasterTable & EASF_TABLE_INDEX_MASK)) return (i+1+(IndexInMasterTable & EASF_TABLE_ATTR_MASK)); - return 1; - } else -#endif - { - return IndexInMasterTable; - } -} - -ATOM_TABLE_ATTRIBUTE GetCommandTableAttribute(UINT8 *pTableHeader) -{ - ATOM_TABLE_ATTRIBUTE_ACCESS lTableAccess; - - /* It's unclear whether this union trick breaks C aliasing rules, - * however, it's explicitely permitted by gcc, and we have other - * case where the code relies on a union being accessed by either - * of the "ways" and stay consistent so if a compiler breaks this - * assumption, it will probably need us to compile without strict - * aliasing enforcement - */ - lTableAccess.sbfAccess = ((ATOM_COMMON_ROM_COMMAND_TABLE_HEADER *)pTableHeader)->TableAttribute; - lTableAccess.susAccess = UINT16LE_TO_CPU(lTableAccess.susAccess); - - return lTableAccess.sbfAccess; -} - -CD_STATUS ParseTable(DEVICE_DATA STACK_BASED* pDeviceData, UINT8 IndexInMasterTable) -{ - PARSER_TEMP_DATA ParserTempData; - WORKING_TABLE_DATA STACK_BASED* prevWorkingTableData; - - memset(&ParserTempData, 0, sizeof(PARSER_TEMP_DATA)); - ParserTempData.pDeviceData=(DEVICE_DATA*)pDeviceData; -#ifndef DISABLE_EASF - if (pDeviceData->format == TABLE_FORMAT_EASF) - { - ParserTempData.IndirectIOTablePointer = 0; - } else -#endif - { - ParserTempData.pCmd=(GENERIC_ATTRIBUTE_COMMAND*)GetDataMasterTablePointer(pDeviceData); - ParserTempData.IndirectIOTablePointer=(UINT8*)((ULONG)(UINT16LE_TO_CPU(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[INDIRECT_IO_TABLE])) + pDeviceData->pBIOS_Image); - ParserTempData.IndirectIOTablePointer+=sizeof(ATOM_COMMON_TABLE_HEADER); - } - - ParserTempData.pCmd=(GENERIC_ATTRIBUTE_COMMAND*)GetCommandMasterTablePointer(pDeviceData); - IndexInMasterTable=GetTrueIndexInMasterTable((PARSER_TEMP_DATA STACK_BASED *)&ParserTempData,IndexInMasterTable); - if(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable]!=0 ) // if the offset is not ZERO - { - ParserTempData.CommandSpecific.IndexInMasterTable=IndexInMasterTable; - ParserTempData.Multipurpose.CurrentPort=ATI_RegsPort; - ParserTempData.CurrentPortID=INDIRECT_IO_MM; - ParserTempData.CurrentRegBlock=0; - ParserTempData.CurrentFB_Window=0; - prevWorkingTableData=NULL; - ParserTempData.Status=CD_CALL_TABLE; - - do{ - - if (ParserTempData.Status==CD_CALL_TABLE) - { - IndexInMasterTable=ParserTempData.CommandSpecific.IndexInMasterTable; - if(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable]!=0) // if the offset is not ZERO - { - ATOM_TABLE_ATTRIBUTE lTableAttr; - lTableAttr = GetCommandTableAttribute(UINT16LE_TO_CPU(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable])+pDeviceData->pBIOS_Image); -#ifndef UEFI_BUILD - ParserTempData.pWorkingTableData =(WORKING_TABLE_DATA STACK_BASED*) AllocateWorkSpace(pDeviceData, - lTableAttr.WS_SizeInBytes+sizeof(WORKING_TABLE_DATA)); -#else - ParserTempData.pWorkingTableData =(WORKING_TABLE_DATA STACK_BASED*) AllocateWorkSpace(pDeviceData, - lTableAttr.WS_SizeInBytes+sizeof(WORKING_TABLE_DATA)); -#endif - if (ParserTempData.pWorkingTableData!=NULL) - { - ParserTempData.pWorkingTableData->pWorkSpace=(WORKSPACE_POINTER STACK_BASED*)((UINT8*)ParserTempData.pWorkingTableData+sizeof(WORKING_TABLE_DATA)); -#ifndef UEFI_BUILD - ParserTempData.pWorkingTableData->pTableHead = (UINT8 *)(UINT16LE_TO_CPU(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable])+pDeviceData->pBIOS_Image); -#else - ParserTempData.pWorkingTableData->pTableHead = (UINT8 *)(UINT16LE_TO_CPU(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable])); -#endif - ParserTempData.pWorkingTableData->IP=((UINT8*)ParserTempData.pWorkingTableData->pTableHead)+sizeof(ATOM_COMMON_ROM_COMMAND_TABLE_HEADER); - ParserTempData.pWorkingTableData->prevWorkingTableData=prevWorkingTableData; - prevWorkingTableData=ParserTempData.pWorkingTableData; - ParserTempData.Status = CD_SUCCESS; - } else ParserTempData.Status = CD_UNEXPECTED_BEHAVIOR; - } else ParserTempData.Status = CD_EXEC_TABLE_NOT_FOUND; - } - if (!CD_ERROR(ParserTempData.Status)) - { - ParserTempData.Status = CD_SUCCESS; - while (!CD_ERROR_OR_COMPLETED(ParserTempData.Status)) - { - if (IS_COMMAND_VALID(((COMMAND_HEADER*)ParserTempData.pWorkingTableData->IP)->Opcode)) - { - ParserTempData.pCmd = (GENERIC_ATTRIBUTE_COMMAND*)ParserTempData.pWorkingTableData->IP; - - if (IS_END_OF_TABLE(((COMMAND_HEADER*)ParserTempData.pWorkingTableData->IP)->Opcode)) - { - ParserTempData.Status=CD_COMPLETED; - prevWorkingTableData=ParserTempData.pWorkingTableData->prevWorkingTableData; - - FreeWorkSpace(pDeviceData, ParserTempData.pWorkingTableData); - ParserTempData.pWorkingTableData=prevWorkingTableData; - if (prevWorkingTableData!=NULL) - { - ATOM_TABLE_ATTRIBUTE lTableAttr; - lTableAttr = GetCommandTableAttribute(ParserTempData.pWorkingTableData->pTableHead); - ParserTempData.pDeviceData->pParameterSpace-=(lTableAttr.PS_SizeInBytes>>2); - } - // if there is a parent table where to return, then restore PS_pointer to the original state - } - else - { - IndexInMasterTable=ProcessCommandProperties((PARSER_TEMP_DATA STACK_BASED *)&ParserTempData); - (*CallTable[IndexInMasterTable].function)((PARSER_TEMP_DATA STACK_BASED *)&ParserTempData); -#if (PARSER_TYPE!=DRIVER_TYPE_PARSER) - BIOS_STACK_MODIFIER(); -#endif - } - } - else - { - ParserTempData.Status=CD_INVALID_OPCODE; - break; - } - - } // while - } // if - else - break; - } while (prevWorkingTableData!=NULL); - if (ParserTempData.Status == CD_COMPLETED) return CD_SUCCESS; - return ParserTempData.Status; - } else return CD_SUCCESS; -} - -// EOF - diff --git a/src/AtomBios/hwserv_drv.c b/src/AtomBios/hwserv_drv.c deleted file mode 100644 index 9f2b6b92..00000000 --- a/src/AtomBios/hwserv_drv.c +++ /dev/null @@ -1,354 +0,0 @@ -/* - * Copyright 2006-2007 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/** - -Module Name: - - hwserv_drv.c - -Abstract: - - Functions defined in the Command Decoder Specification document - -Revision History: - - NEG:27.09.2002 Initiated. ---*/ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include <X11/Xos.h> -#include "xorg-server.h" - -#include "Decoder.h" - -//trace settings -#if DEBUG_OUTPUT_DEVICE & 1 - #define TRACE_USING_STDERR //define it to use stderr as trace output, -#endif -#if DEBUG_OUTPUT_DEVICE & 2 - #define TRACE_USING_RS232 -#endif -#if DEBUG_OUTPUT_DEVICE & 4 - #define TRACE_USING_LPT -#endif - - -#if DEBUG_PARSER == 4 - #define IO_TRACE //IO access trace switch, undefine it to turn off - #define PCI_TRACE //PCI access trace switch, undefine it to turn off - #define MEM_TRACE //MEM access trace switch, undefine it to turn off -#endif - -UINT32 CailReadATIRegister(VOID*,UINT32); -VOID CailWriteATIRegister(VOID*,UINT32,UINT32); -VOID* CailAllocateMemory(VOID*,UINT16); -VOID CailReleaseMemory(VOID *,VOID *); -VOID CailDelayMicroSeconds(VOID *,UINT32 ); -VOID CailReadPCIConfigData(VOID*,VOID*,UINT32,UINT16); -VOID CailWritePCIConfigData(VOID*,VOID*,UINT32,UINT16); -UINT32 CailReadFBData(VOID*,UINT32); -VOID CailWriteFBData(VOID*,UINT32,UINT32); -ULONG CailReadPLL(VOID *Context ,ULONG Address); -VOID CailWritePLL(VOID *Context,ULONG Address,ULONG Data); -ULONG CailReadMC(VOID *Context ,ULONG Address); -VOID CailWriteMC(VOID *Context ,ULONG Address,ULONG Data); - - -#if DEBUG_PARSER>0 -VOID CailVideoDebugPrint(VOID*,ULONG_PTR, UINT16); -#endif -// Delay function -#if ( defined ENABLE_PARSER_DELAY || defined ENABLE_ALL_SERVICE_FUNCTIONS ) - -VOID DelayMilliseconds(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - CailDelayMicroSeconds(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->SourceData32*1000); -} - -VOID DelayMicroseconds(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - CailDelayMicroSeconds(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->SourceData32); -} -#endif - -VOID PostCharOutput(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ -} - -VOID CallerDebugFunc(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ -} - - -// PCI READ Access - -#if ( defined ENABLE_PARSER_PCIREAD8 || defined ENABLE_ALL_SERVICE_FUNCTIONS ) -UINT8 ReadPCIReg8(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - UINT8 rvl; - CailReadPCIConfigData(pWorkingTableData->pDeviceData->CAIL,&rvl,pWorkingTableData->Index,sizeof(UINT8)); - return rvl; -} -#endif - - -#if ( defined ENABLE_PARSER_PCIREAD16 || defined ENABLE_ALL_SERVICE_FUNCTIONS ) -UINT16 ReadPCIReg16(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - - UINT16 rvl; - CailReadPCIConfigData(pWorkingTableData->pDeviceData->CAIL,&rvl,pWorkingTableData->Index,sizeof(UINT16)); - return rvl; - -} -#endif - - - -#if ( defined ENABLE_PARSER_PCIREAD32 || defined ENABLE_ALL_SERVICE_FUNCTIONS ) -UINT32 ReadPCIReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - - UINT32 rvl; - CailReadPCIConfigData(pWorkingTableData->pDeviceData->CAIL,&rvl,pWorkingTableData->Index,sizeof(UINT32)); - return rvl; -} -#endif - - -// PCI WRITE Access - -#if ( defined ENABLE_PARSER_PCIWRITE8 || defined ENABLE_ALL_SERVICE_FUNCTIONS ) -VOID WritePCIReg8 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - - CailWritePCIConfigData(pWorkingTableData->pDeviceData->CAIL,&(pWorkingTableData->DestData32),pWorkingTableData->Index,sizeof(UINT8)); - -} - -#endif - - -#if ( defined ENABLE_PARSER_PCIWRITE16 || defined ENABLE_ALL_SERVICE_FUNCTIONS ) -VOID WritePCIReg16 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - - CailWritePCIConfigData(pWorkingTableData->pDeviceData->CAIL,&(pWorkingTableData->DestData32),pWorkingTableData->Index,sizeof(UINT16)); -} - -#endif - - -#if ( defined ENABLE_PARSER_PCIWRITE32 || defined ENABLE_ALL_SERVICE_FUNCTIONS ) -VOID WritePCIReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - CailWritePCIConfigData(pWorkingTableData->pDeviceData->CAIL,&(pWorkingTableData->DestData32),pWorkingTableData->Index,sizeof(UINT32)); -} -#endif - - - - -// System IO Access -#if ( defined ENABLE_PARSER_SYS_IOREAD8 || defined ENABLE_ALL_SERVICE_FUNCTIONS ) -UINT8 ReadSysIOReg8 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - UINT8 rvl; - rvl=0; - //rvl= (UINT8) ReadGenericPciCfg(dev,reg,sizeof(UINT8)); - return rvl; -} -#endif - - -#if ( defined ENABLE_PARSER_SYS_IOREAD16 || defined ENABLE_ALL_SERVICE_FUNCTIONS ) -UINT16 ReadSysIOReg16(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - - UINT16 rvl; - rvl=0; - //rvl= (UINT16) ReadGenericPciCfg(dev,reg,sizeof(UINT16)); - return rvl; - -} -#endif - - - -#if ( defined ENABLE_PARSER_SYS_IOREAD32 || defined ENABLE_ALL_SERVICE_FUNCTIONS ) -UINT32 ReadSysIOReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - - UINT32 rvl; - rvl=0; - //rvl= (UINT32) ReadGenericPciCfg(dev,reg,sizeof(UINT32)); - return rvl; -} -#endif - - -// PCI WRITE Access - -#if ( defined ENABLE_PARSER_SYS_IOWRITE8 || defined ENABLE_ALL_SERVICE_FUNCTIONS ) -VOID WriteSysIOReg8 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - - //WriteGenericPciCfg(dev,reg,sizeof(UINT8),(UINT32)value); -} - -#endif - - -#if ( defined ENABLE_PARSER_SYS_IOWRITE16 || defined ENABLE_ALL_SERVICE_FUNCTIONS ) -VOID WriteSysIOReg16 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - - //WriteGenericPciCfg(dev,reg,sizeof(UINT16),(UINT32)value); -} - -#endif - - -#if ( defined ENABLE_PARSER_SYS_IOWRITE32 || defined ENABLE_ALL_SERVICE_FUNCTIONS ) -VOID WriteSysIOReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - //WriteGenericPciCfg(dev,reg,sizeof(UINT32),(UINT32)value); -} -#endif - -// ATI Registers Memory Mapped Access - -#if ( defined ENABLE_PARSER_REGISTERS_MEMORY_ACCESS || defined ENABLE_ALL_SERVICE_FUNCTIONS) - -UINT32 ReadReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - return CailReadATIRegister(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->Index); -} - -VOID WriteReg32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - CailWriteATIRegister(pWorkingTableData->pDeviceData->CAIL,(UINT16)pWorkingTableData->Index,pWorkingTableData->DestData32 ); -} - - -VOID ReadIndReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - pWorkingTableData->IndirectData = CailReadATIRegister(pWorkingTableData->pDeviceData->CAIL,UINT16LE_TO_CPU(*(UINT16*)(pWorkingTableData->IndirectIOTablePointer+1))); -} - -VOID WriteIndReg32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - CailWriteATIRegister(pWorkingTableData->pDeviceData->CAIL,UINT16LE_TO_CPU(*(UINT16*)(pWorkingTableData->IndirectIOTablePointer+1)),pWorkingTableData->IndirectData); -} - -#endif - -// ATI Registers IO Mapped Access - -#if ( defined ENABLE_PARSER_REGISTERS_IO_ACCESS || defined ENABLE_ALL_SERVICE_FUNCTIONS ) -UINT32 ReadRegIO (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - //return CailReadATIRegister(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->Index); - return 0; -} -VOID WriteRegIO(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - // return CailWriteATIRegister(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->Index,pWorkingTableData->DestData32 ); -} -#endif - -// access to Frame buffer, dummy function, need more information to implement it -UINT32 ReadFrameBuffer32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - - return CailReadFBData(pWorkingTableData->pDeviceData->CAIL, (pWorkingTableData->Index <<2 )); - -} - -VOID WriteFrameBuffer32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - CailWriteFBData(pWorkingTableData->pDeviceData->CAIL,(pWorkingTableData->Index <<2), pWorkingTableData->DestData32); - -} - - -VOID *AllocateMemory(DEVICE_DATA *pDeviceData , UINT16 MemSize) -{ - if(MemSize) - return(CailAllocateMemory(pDeviceData->CAIL,MemSize)); - else - return NULL; -} - - -VOID ReleaseMemory(DEVICE_DATA *pDeviceData , WORKING_TABLE_DATA* pWorkingTableData) -{ - if( pWorkingTableData) - CailReleaseMemory(pDeviceData->CAIL, pWorkingTableData); -} - - -UINT32 ReadMC32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - UINT32 ReadData; - ReadData=(UINT32)CailReadMC(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->Index); - return ReadData; -} - -VOID WriteMC32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - CailWriteMC(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->Index,pWorkingTableData->DestData32); -} - -UINT32 ReadPLL32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - UINT32 ReadData; - ReadData=(UINT32)CailReadPLL(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->Index); - return ReadData; - -} - -VOID WritePLL32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - CailWritePLL(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->Index,pWorkingTableData->DestData32); - -} - - - -#if DEBUG_PARSER>0 -VOID CD_print_string (DEVICE_DATA *pDeviceData, UINT8 *str) -{ - CailVideoDebugPrint( pDeviceData->CAIL, (ULONG_PTR) str, PARSER_STRINGS); -} - -VOID CD_print_value (DEVICE_DATA *pDeviceData, ULONG_PTR value, UINT16 value_type ) -{ - CailVideoDebugPrint( pDeviceData->CAIL, (ULONG_PTR)value, value_type); -} - -#endif - -// EOF diff --git a/src/AtomBios/includes/CD_Common_Types.h b/src/AtomBios/includes/CD_Common_Types.h deleted file mode 100644 index 071b8fd4..00000000 --- a/src/AtomBios/includes/CD_Common_Types.h +++ /dev/null @@ -1,172 +0,0 @@ -/* - * Copyright 2006-2007 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/*++ - -Module Name: - - CD_Common_Types.h - -Abstract: - - Defines common data types to use across platforms/SW components - -Revision History: - - NEG:17.09.2002 Initiated. ---*/ -#ifndef _COMMON_TYPES_H_ - #define _COMMON_TYPES_H_ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - - #ifndef LINUX - #if _MSC_EXTENSIONS - - // - // use Microsoft* C complier dependent interger width types - // - // typedef unsigned __int64 uint64_t; - // typedef __int64 int64_t; - typedef unsigned __int32 uint32_t; - typedef __int32 int32_t; -#elif defined (__linux__) || defined (__NetBSD__) \ - || defined(__sun) || defined(__OpenBSD__) \ - || defined (__FreeBSD__) || defined(__DragonFly__) || defined(__GLIBC__) - typedef unsigned int uint32_t; - typedef int int32_t; - #else - typedef unsigned long uint32_t; - typedef signed long int32_t; - #endif - typedef unsigned char uint8_t; -#if (defined(__sun) && defined(_CHAR_IS_SIGNED)) - typedef char int8_t; -#else - typedef signed char int8_t; -#endif - typedef unsigned short uint16_t; - typedef signed short int16_t; - #endif -#ifndef UEFI_BUILD - typedef signed int intn_t; - typedef unsigned int uintn_t; -#else -#ifndef EFIX64 - typedef signed int intn_t; - typedef unsigned int uintn_t; -#endif -#endif -#ifndef FGL_LINUX -#pragma warning ( disable : 4142 ) -#endif - - -#ifndef VOID -typedef void VOID; -#endif -#ifndef UEFI_BUILD - typedef intn_t INTN; - typedef uintn_t UINTN; -#else -#ifndef EFIX64 - typedef intn_t INTN; - typedef uintn_t UINTN; -#endif -#endif -#ifndef BOOLEAN -typedef uint8_t BOOLEAN; -#endif -#ifndef INT8 -typedef int8_t INT8; -#endif -#ifndef UINT8 -typedef uint8_t UINT8; -#endif -#ifndef INT16 -typedef int16_t INT16; -#endif -#ifndef UINT16 -typedef uint16_t UINT16; -#endif -#ifndef INT32 -typedef int32_t INT32; -#endif -#ifndef UINT32 -typedef uint32_t UINT32; -#endif -//typedef int64_t INT64; -//typedef uint64_t UINT64; -typedef uint8_t CHAR8; -typedef uint16_t CHAR16; -#ifndef USHORT -typedef UINT16 USHORT; -#endif -#ifndef UCHAR -typedef UINT8 UCHAR; -#endif -#ifndef ULONG -typedef UINT32 ULONG; -#endif - -#ifndef _WIN64 -#ifndef ULONG_PTR -typedef unsigned long ULONG_PTR; -#endif // ULONG_PTR -#endif // _WIN64 - -//#define FAR __far -#ifndef TRUE - #define TRUE ((BOOLEAN) 1 == 1) -#endif - -#ifndef FALSE - #define FALSE ((BOOLEAN) 0 == 1) -#endif - -#ifndef NULL - #define NULL ((VOID *) 0) -#endif - -//typedef UINTN CD_STATUS; - - -#ifndef FGL_LINUX -#pragma warning ( default : 4142 ) -#endif - -#ifndef ATOM_BIG_ENDIAN -#ifdef X_BYTE_ORDER -#if X_BYTE_ORDER == X_BIG_ENDIAN -#define ATOM_BIG_ENDIAN 1 -#endif -#endif -#endif -#ifndef ATOM_BIG_ENDIAN -#define ATOM_BIG_ENDIAN 0 -#endif - -#endif // _COMMON_TYPES_H_ - -// EOF diff --git a/src/AtomBios/includes/CD_Definitions.h b/src/AtomBios/includes/CD_Definitions.h deleted file mode 100644 index c00e93e8..00000000 --- a/src/AtomBios/includes/CD_Definitions.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright 2006-2007 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/*++ - -Module Name: - -CD_Definitions.h - -Abstract: - -Defines Script Language commands - -Revision History: - -NEG:27.08.2002 Initiated. ---*/ - -#include "CD_Structs.h" -#ifndef _CD_DEFINITIONS_H -#define _CD_DEFINITIONS_H_ -#ifdef DRIVER_PARSER -VOID *AllocateMemory(DEVICE_DATA *, UINT16); -VOID ReleaseMemory(DEVICE_DATA * , WORKING_TABLE_DATA* ); -#endif -CD_STATUS ParseTable(DEVICE_DATA* pDeviceData, UINT8 IndexInMasterTable); -//CD_STATUS CD_MainLoop(PARSER_TEMP_DATA_POINTER pParserTempData); -CD_STATUS Main_Loop(DEVICE_DATA* pDeviceData,UINT16 *MasterTableOffset,UINT8 IndexInMasterTable); -UINT16* GetCommandMasterTablePointer(DEVICE_DATA* pDeviceData); -ATOM_TABLE_ATTRIBUTE GetCommandTableAttribute(UINT8 *pTableHeader); -#endif //CD_DEFINITIONS diff --git a/src/AtomBios/includes/CD_Opcodes.h b/src/AtomBios/includes/CD_Opcodes.h deleted file mode 100644 index 2f3bec5f..00000000 --- a/src/AtomBios/includes/CD_Opcodes.h +++ /dev/null @@ -1,181 +0,0 @@ -/* - * Copyright 2006-2007 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/*++ - -Module Name: - -CD_OPCODEs.h - -Abstract: - -Defines Command Decoder OPCODEs - -Revision History: - -NEG:24.09.2002 Initiated. ---*/ -#ifndef _CD_OPCODES_H_ -#define _CD_OPCODES_H_ - -typedef enum _OPCODE { - Reserved_00= 0, // 0 = 0x00 - // MOVE_ group - MOVE_REG_OPCODE, // 1 = 0x01 - FirstValidCommand=MOVE_REG_OPCODE, - MOVE_PS_OPCODE, // 2 = 0x02 - MOVE_WS_OPCODE, // 3 = 0x03 - MOVE_FB_OPCODE, // 4 = 0x04 - MOVE_PLL_OPCODE, // 5 = 0x05 - MOVE_MC_OPCODE, // 6 = 0x06 - // Logic group - AND_REG_OPCODE, // 7 = 0x07 - AND_PS_OPCODE, // 8 = 0x08 - AND_WS_OPCODE, // 9 = 0x09 - AND_FB_OPCODE, // 10 = 0x0A - AND_PLL_OPCODE, // 11 = 0x0B - AND_MC_OPCODE, // 12 = 0x0C - OR_REG_OPCODE, // 13 = 0x0D - OR_PS_OPCODE, // 14 = 0x0E - OR_WS_OPCODE, // 15 = 0x0F - OR_FB_OPCODE, // 16 = 0x10 - OR_PLL_OPCODE, // 17 = 0x11 - OR_MC_OPCODE, // 18 = 0x12 - SHIFT_LEFT_REG_OPCODE, // 19 = 0x13 - SHIFT_LEFT_PS_OPCODE, // 20 = 0x14 - SHIFT_LEFT_WS_OPCODE, // 21 = 0x15 - SHIFT_LEFT_FB_OPCODE, // 22 = 0x16 - SHIFT_LEFT_PLL_OPCODE, // 23 = 0x17 - SHIFT_LEFT_MC_OPCODE, // 24 = 0x18 - SHIFT_RIGHT_REG_OPCODE, // 25 = 0x19 - SHIFT_RIGHT_PS_OPCODE, // 26 = 0x1A - SHIFT_RIGHT_WS_OPCODE, // 27 = 0x1B - SHIFT_RIGHT_FB_OPCODE, // 28 = 0x1C - SHIFT_RIGHT_PLL_OPCODE, // 29 = 0x1D - SHIFT_RIGHT_MC_OPCODE, // 30 = 0x1E - // Arithmetic group - MUL_REG_OPCODE, // 31 = 0x1F - MUL_PS_OPCODE, // 32 = 0x20 - MUL_WS_OPCODE, // 33 = 0x21 - MUL_FB_OPCODE, // 34 = 0x22 - MUL_PLL_OPCODE, // 35 = 0x23 - MUL_MC_OPCODE, // 36 = 0x24 - DIV_REG_OPCODE, // 37 = 0x25 - DIV_PS_OPCODE, // 38 = 0x26 - DIV_WS_OPCODE, // 39 = 0x27 - DIV_FB_OPCODE, // 40 = 0x28 - DIV_PLL_OPCODE, // 41 = 0x29 - DIV_MC_OPCODE, // 42 = 0x2A - ADD_REG_OPCODE, // 43 = 0x2B - ADD_PS_OPCODE, // 44 = 0x2C - ADD_WS_OPCODE, // 45 = 0x2D - ADD_FB_OPCODE, // 46 = 0x2E - ADD_PLL_OPCODE, // 47 = 0x2F - ADD_MC_OPCODE, // 48 = 0x30 - SUB_REG_OPCODE, // 49 = 0x31 - SUB_PS_OPCODE, // 50 = 0x32 - SUB_WS_OPCODE, // 51 = 0x33 - SUB_FB_OPCODE, // 52 = 0x34 - SUB_PLL_OPCODE, // 53 = 0x35 - SUB_MC_OPCODE, // 54 = 0x36 - // Control grouop - SET_ATI_PORT_OPCODE, // 55 = 0x37 - SET_PCI_PORT_OPCODE, // 56 = 0x38 - SET_SYS_IO_PORT_OPCODE, // 57 = 0x39 - SET_REG_BLOCK_OPCODE, // 58 = 0x3A - SET_FB_BASE_OPCODE, // 59 = 0x3B - COMPARE_REG_OPCODE, // 60 = 0x3C - COMPARE_PS_OPCODE, // 61 = 0x3D - COMPARE_WS_OPCODE, // 62 = 0x3E - COMPARE_FB_OPCODE, // 63 = 0x3F - COMPARE_PLL_OPCODE, // 64 = 0x40 - COMPARE_MC_OPCODE, // 65 = 0x41 - SWITCH_OPCODE, // 66 = 0x42 - JUMP__OPCODE, // 67 = 0x43 - JUMP_EQUAL_OPCODE, // 68 = 0x44 - JUMP_BELOW_OPCODE, // 69 = 0x45 - JUMP_ABOVE_OPCODE, // 70 = 0x46 - JUMP_BELOW_OR_EQUAL_OPCODE, // 71 = 0x47 - JUMP_ABOVE_OR_EQUAL_OPCODE, // 72 = 0x48 - JUMP_NOT_EQUAL_OPCODE, // 73 = 0x49 - TEST_REG_OPCODE, // 74 = 0x4A - TEST_PS_OPCODE, // 75 = 0x4B - TEST_WS_OPCODE, // 76 = 0x4C - TEST_FB_OPCODE, // 77 = 0x4D - TEST_PLL_OPCODE, // 78 = 0x4E - TEST_MC_OPCODE, // 79 = 0x4F - DELAY_MILLISEC_OPCODE, // 80 = 0x50 - DELAY_MICROSEC_OPCODE, // 81 = 0x51 - CALL_TABLE_OPCODE, // 82 = 0x52 - REPEAT_OPCODE, // 83 = 0x53 - // Miscellaneous group - CLEAR_REG_OPCODE, // 84 = 0x54 - CLEAR_PS_OPCODE, // 85 = 0x55 - CLEAR_WS_OPCODE, // 86 = 0x56 - CLEAR_FB_OPCODE, // 87 = 0x57 - CLEAR_PLL_OPCODE, // 88 = 0x58 - CLEAR_MC_OPCODE, // 89 = 0x59 - NOP_OPCODE, // 90 = 0x5A - EOT_OPCODE, // 91 = 0x5B - MASK_REG_OPCODE, // 92 = 0x5C - MASK_PS_OPCODE, // 93 = 0x5D - MASK_WS_OPCODE, // 94 = 0x5E - MASK_FB_OPCODE, // 95 = 0x5F - MASK_PLL_OPCODE, // 96 = 0x60 - MASK_MC_OPCODE, // 97 = 0x61 - // BIOS dedicated group - POST_CARD_OPCODE, // 98 = 0x62 - BEEP_OPCODE, // 99 = 0x63 - SAVE_REG_OPCODE, // 100 = 0x64 - RESTORE_REG_OPCODE, // 101 = 0x65 - SET_DATA_BLOCK_OPCODE, // 102 = 0x66 - - XOR_REG_OPCODE, // 103 = 0x67 - XOR_PS_OPCODE, // 104 = 0x68 - XOR_WS_OPCODE, // 105 = 0x69 - XOR_FB_OPCODE, // 106 = 0x6a - XOR_PLL_OPCODE, // 107 = 0x6b - XOR_MC_OPCODE, // 108 = 0x6c - - SHL_REG_OPCODE, // 109 = 0x6d - SHL_PS_OPCODE, // 110 = 0x6e - SHL_WS_OPCODE, // 111 = 0x6f - SHL_FB_OPCODE, // 112 = 0x70 - SHL_PLL_OPCODE, // 113 = 0x71 - SHL_MC_OPCODE, // 114 = 0x72 - - SHR_REG_OPCODE, // 115 = 0x73 - SHR_PS_OPCODE, // 116 = 0x74 - SHR_WS_OPCODE, // 117 = 0x75 - SHR_FB_OPCODE, // 118 = 0x76 - SHR_PLL_OPCODE, // 119 = 0x77 - SHR_MC_OPCODE, // 120 = 0x78 - - DEBUG_OPCODE, // 121 = 0x79 - CTB_DS_OPCODE, // 122 = 0x7A - - LastValidCommand = CTB_DS_OPCODE, - // Extension specificaTOR - Extension = 0x80, // 128 = 0x80 // Next byte is an OPCODE as well - Reserved_FF = 255 // 255 = 0xFF -}OPCODE; -#endif // _CD_OPCODES_H_ diff --git a/src/AtomBios/includes/CD_Structs.h b/src/AtomBios/includes/CD_Structs.h deleted file mode 100644 index 01fb80ec..00000000 --- a/src/AtomBios/includes/CD_Structs.h +++ /dev/null @@ -1,486 +0,0 @@ -/* - * Copyright 2006-2007 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/*++ - -Module Name: - -CD_Struct.h - -Abstract: - -Defines Script Language commands - -Revision History: - -NEG:26.08.2002 Initiated. ---*/ - -#ifndef _CD_STRUCTS_H_ -#define _CD_STRUCTS_H_ - -#include "CD_binding.h" - -/* Endaianness should be specified before inclusion, - * default to little endian - */ -#ifndef ATOM_BIG_ENDIAN -#error Endian not specified -#endif - -#ifdef UEFI_BUILD -typedef UINT16** PTABLE_UNIT_TYPE; -typedef UINTN TABLE_UNIT_TYPE; -#else -typedef UINT16* PTABLE_UNIT_TYPE; -typedef UINT16 TABLE_UNIT_TYPE; -#endif - -#include <regsdef.h> //This important file is dynamically generated based on the ASIC!!!! - -#define PARSER_MAJOR_REVISION 5 -#define PARSER_MINOR_REVISION 0 - -//#include "atombios.h" -#if (PARSER_TYPE==DRIVER_TYPE_PARSER) -#ifdef FGL_LINUX -#pragma pack(push,1) -#else -#pragma pack(push) -#pragma pack(1) -#endif -#endif - -#include "CD_Common_Types.h" -#include "CD_Opcodes.h" -typedef UINT16 WORK_SPACE_SIZE; -typedef enum _CD_STATUS{ - CD_SUCCESS, - CD_CALL_TABLE, - CD_COMPLETED=0x10, - CD_GENERAL_ERROR=0x80, - CD_INVALID_OPCODE, - CD_NOT_IMPLEMENTED, - CD_EXEC_TABLE_NOT_FOUND, - CD_EXEC_PARAMETER_ERROR, - CD_EXEC_PARSER_ERROR, - CD_INVALID_DESTINATION_TYPE, - CD_UNEXPECTED_BEHAVIOR, - CD_INVALID_SWITCH_OPERAND_SIZE -}CD_STATUS; - -#define PARSER_STRINGS 0 -#define PARSER_DEC 1 -#define PARSER_HEX 2 - -#define DB_CURRENT_COMMAND_TABLE 0xFF - -#define TABLE_FORMAT_BIOS 0 -#define TABLE_FORMAT_EASF 1 - -#define EASF_TABLE_INDEX_MASK 0xfc -#define EASF_TABLE_ATTR_MASK 0x03 - -#define CD_ERROR(a) (((INTN) (a)) > CD_COMPLETED) -#define CD_ERROR_OR_COMPLETED(a) (((INTN) (a)) > CD_SUCCESS) - - -#if (BIOS_PARSER==1) -#ifdef _H2INC -#define STACK_BASED -#else -extern __segment farstack; -#define STACK_BASED __based(farstack) -#endif -#else -#define STACK_BASED -#endif - -typedef enum _COMPARE_FLAGS{ - Below, - Equal, - Above, - NotEqual, - Overflow, - NoCondition -}COMPARE_FLAGS; - -typedef UINT16 IO_BASE_ADDR; - -typedef struct _BUS_DEV_FUNC_PCI_ADDR{ - UINT8 Register; - UINT8 Function; - UINT8 Device; - UINT8 Bus; -} BUS_DEV_FUNC_PCI_ADDR; - -typedef struct _BUS_DEV_FUNC{ - UINT8 Function : 3; - UINT8 Device : 5; - UINT8 Bus; -} BUS_DEV_FUNC; - -#ifndef UEFI_BUILD -typedef struct _PCI_CONFIG_ACCESS_CF8{ - UINT32 Reg : 8; - UINT32 Func : 3; - UINT32 Dev : 5; - UINT32 Bus : 8; - UINT32 Reserved: 7; - UINT32 Enable : 1; -} PCI_CONFIG_ACCESS_CF8; -#endif - -typedef enum _MEM_RESOURCE { - Stack_Resource, - FrameBuffer_Resource, - BIOS_Image_Resource -}MEM_RESOURCE; - -typedef enum _PORTS{ - ATI_RegsPort, - PCI_Port, - SystemIO_Port -}PORTS; - -typedef enum _OPERAND_TYPE { - typeRegister, - typeParamSpace, - typeWorkSpace, - typeFrameBuffer, - typeIndirect, - typeDirect, - typePLL, - typeMC -}OPERAND_TYPE; - -typedef enum _DESTINATION_OPERAND_TYPE { - destRegister, - destParamSpace, - destWorkSpace, - destFrameBuffer, - destPLL, - destMC -}DESTINATION_OPERAND_TYPE; - -typedef enum _SOURCE_OPERAND_TYPE { - sourceRegister, - sourceParamSpace, - sourceWorkSpace, - sourceFrameBuffer, - sourceIndirect, - sourceDirect, - sourcePLL, - sourceMC -}SOURCE_OPERAND_TYPE; - -typedef enum _ALIGNMENT_TYPE { - alignmentDword, - alignmentLowerWord, - alignmentMiddleWord, - alignmentUpperWord, - alignmentByte0, - alignmentByte1, - alignmentByte2, - alignmentByte3 -}ALIGNMENT_TYPE; - - -#define INDIRECT_IO_READ 0 -#define INDIRECT_IO_WRITE 0x80 -#define INDIRECT_IO_MM 0 -#define INDIRECT_IO_PLL 1 -#define INDIRECT_IO_MC 2 - -typedef struct _PARAMETERS_TYPE{ - UINT8 Destination; - UINT8 Source; -}PARAMETERS_TYPE; -/* The following structures don't used to allocate any type of objects(variables). - they are serve the only purpose: Get proper access to data(commands), found in the tables*/ -typedef struct _PA_BYTE_BYTE{ - UINT8 PA_Destination; - UINT8 PA_Source; - UINT8 PA_Padding[8]; -}PA_BYTE_BYTE; -typedef struct _PA_BYTE_WORD{ - UINT8 PA_Destination; - UINT16 PA_Source; - UINT8 PA_Padding[7]; -}PA_BYTE_WORD; -typedef struct _PA_BYTE_DWORD{ - UINT8 PA_Destination; - UINT32 PA_Source; - UINT8 PA_Padding[5]; -}PA_BYTE_DWORD; -typedef struct _PA_WORD_BYTE{ - UINT16 PA_Destination; - UINT8 PA_Source; - UINT8 PA_Padding[7]; -}PA_WORD_BYTE; -typedef struct _PA_WORD_WORD{ - UINT16 PA_Destination; - UINT16 PA_Source; - UINT8 PA_Padding[6]; -}PA_WORD_WORD; -typedef struct _PA_WORD_DWORD{ - UINT16 PA_Destination; - UINT32 PA_Source; - UINT8 PA_Padding[4]; -}PA_WORD_DWORD; -typedef struct _PA_WORD_XX{ - UINT16 PA_Destination; - UINT8 PA_Padding[8]; -}PA_WORD_XX; -typedef struct _PA_BYTE_XX{ - UINT8 PA_Destination; - UINT8 PA_Padding[9]; -}PA_BYTE_XX; -/*The following 6 definitions used for Mask operation*/ -typedef struct _PA_BYTE_BYTE_BYTE{ - UINT8 PA_Destination; - UINT8 PA_AndMaskByte; - UINT8 PA_OrMaskByte; - UINT8 PA_Padding[7]; -}PA_BYTE_BYTE_BYTE; -typedef struct _PA_BYTE_WORD_WORD{ - UINT8 PA_Destination; - UINT16 PA_AndMaskWord; - UINT16 PA_OrMaskWord; - UINT8 PA_Padding[5]; -}PA_BYTE_WORD_WORD; -typedef struct _PA_BYTE_DWORD_DWORD{ - UINT8 PA_Destination; - UINT32 PA_AndMaskDword; - UINT32 PA_OrMaskDword; - UINT8 PA_Padding; -}PA_BYTE_DWORD_DWORD; -typedef struct _PA_WORD_BYTE_BYTE{ - UINT16 PA_Destination; - UINT8 PA_AndMaskByte; - UINT8 PA_OrMaskByte; - UINT8 PA_Padding[6]; -}PA_WORD_BYTE_BYTE; -typedef struct _PA_WORD_WORD_WORD{ - UINT16 PA_Destination; - UINT16 PA_AndMaskWord; - UINT16 PA_OrMaskWord; - UINT8 PA_Padding[4]; -}PA_WORD_WORD_WORD; -typedef struct _PA_WORD_DWORD_DWORD{ - UINT16 PA_Destination; - UINT32 PA_AndMaskDword; - UINT32 PA_OrMaskDword; -}PA_WORD_DWORD_DWORD; - - -typedef union _PARAMETER_ACCESS { - PA_BYTE_XX ByteXX; - PA_BYTE_BYTE ByteByte; - PA_BYTE_WORD ByteWord; - PA_BYTE_DWORD ByteDword; - PA_WORD_BYTE WordByte; - PA_WORD_WORD WordWord; - PA_WORD_DWORD WordDword; - PA_WORD_XX WordXX; -/*The following 6 definitions used for Mask operation*/ - PA_BYTE_BYTE_BYTE ByteByteAndByteOr; - PA_BYTE_WORD_WORD ByteWordAndWordOr; - PA_BYTE_DWORD_DWORD ByteDwordAndDwordOr; - PA_WORD_BYTE_BYTE WordByteAndByteOr; - PA_WORD_WORD_WORD WordWordAndWordOr; - PA_WORD_DWORD_DWORD WordDwordAndDwordOr; -}PARAMETER_ACCESS; - -typedef struct _COMMAND_ATTRIBUTE { -#if ATOM_BIG_ENDIAN - UINT8 DestinationAlignment:2; - UINT8 SourceAlignment:3; - UINT8 Source:3; -#else - UINT8 Source:3; - UINT8 SourceAlignment:3; - UINT8 DestinationAlignment:2; -#endif -}COMMAND_ATTRIBUTE; - -typedef struct _SOURCE_DESTINATION_ALIGNMENT{ - UINT8 DestAlignment; - UINT8 SrcAlignment; -}SOURCE_DESTINATION_ALIGNMENT; -typedef struct _MULTIPLICATION_RESULT{ - UINT32 Low32Bit; - UINT32 High32Bit; -}MULTIPLICATION_RESULT; -typedef struct _DIVISION_RESULT{ - UINT32 Quotient32; - UINT32 Reminder32; -}DIVISION_RESULT; -typedef union _DIVISION_MULTIPLICATION_RESULT{ - MULTIPLICATION_RESULT Multiplication; - DIVISION_RESULT Division; -}DIVISION_MULTIPLICATION_RESULT; -typedef struct _COMMAND_HEADER { - UINT8 Opcode; - COMMAND_ATTRIBUTE Attribute; -}COMMAND_HEADER; - -typedef struct _GENERIC_ATTRIBUTE_COMMAND{ - COMMAND_HEADER Header; - PARAMETER_ACCESS Parameters; -} GENERIC_ATTRIBUTE_COMMAND; - -typedef struct _COMMAND_TYPE_1{ - UINT8 Opcode; - PARAMETER_ACCESS Parameters; -} COMMAND_TYPE_1; - -typedef struct _COMMAND_TYPE_OPCODE_OFFSET16{ - UINT8 Opcode; - UINT16 CD_Offset16; -} COMMAND_TYPE_OPCODE_OFFSET16; - -typedef struct _COMMAND_TYPE_OPCODE_OFFSET32{ - UINT8 Opcode; - UINT32 CD_Offset32; -} COMMAND_TYPE_OPCODE_OFFSET32; - -typedef struct _COMMAND_TYPE_OPCODE_VALUE_BYTE{ - UINT8 Opcode; - UINT8 Value; -} COMMAND_TYPE_OPCODE_VALUE_BYTE; - -typedef union _COMMAND_SPECIFIC_UNION{ - UINT8 ContinueSwitch; - UINT8 ControlOperandSourcePosition; - UINT8 IndexInMasterTable; -} COMMAND_SPECIFIC_UNION; - - -typedef struct _CD_GENERIC_BYTE{ -#if ATOM_BIG_ENDIAN - UINT16 PS_SizeInDwordsUsedByCallingTable:5; - UINT16 CurrentPort:2; - UINT16 CommandAccessType:3; - UINT16 CurrentParameterSize:3; - UINT16 CommandType:3; -#else - UINT16 CommandType:3; - UINT16 CurrentParameterSize:3; - UINT16 CommandAccessType:3; - UINT16 CurrentPort:2; - UINT16 PS_SizeInDwordsUsedByCallingTable:5; -#endif -}CD_GENERIC_BYTE; - -typedef UINT8 COMMAND_TYPE_OPCODE_ONLY; - -typedef UINT8 COMMAND_HEADER_POINTER; - - -#if (PARSER_TYPE==BIOS_TYPE_PARSER) - -typedef struct _DEVICE_DATA { - UINT32 STACK_BASED *pParameterSpace; - UINT8 *pBIOS_Image; - UINT8 format; -#if (IO_INTERFACE==PARSER_INTERFACE) - IO_BASE_ADDR IOBase; -#endif -} DEVICE_DATA; - -#else - -typedef struct _DEVICE_DATA { - UINT32 *pParameterSpace; - VOID *CAIL; - UINT8 *pBIOS_Image; - UINT32 format; -} DEVICE_DATA; - -#endif - -struct _PARSER_TEMP_DATA; -typedef UINT32 WORKSPACE_POINTER; - -struct _WORKING_TABLE_DATA{ - UINT8 * pTableHead; - COMMAND_HEADER_POINTER * IP; // Commands pointer - WORKSPACE_POINTER STACK_BASED * pWorkSpace; - struct _WORKING_TABLE_DATA STACK_BASED * prevWorkingTableData; -}; - - - -typedef struct _PARSER_TEMP_DATA{ - DEVICE_DATA STACK_BASED *pDeviceData; - struct _WORKING_TABLE_DATA STACK_BASED *pWorkingTableData; - UINT32 SourceData32; - UINT32 DestData32; - DIVISION_MULTIPLICATION_RESULT MultiplicationOrDivision; - UINT32 Index; - UINT32 CurrentFB_Window; - UINT32 IndirectData; - UINT16 CurrentRegBlock; - TABLE_UNIT_TYPE CurrentDataBlock; - UINT16 AttributesData; -// UINT8 *IndirectIOTable; - UINT8 *IndirectIOTablePointer; - GENERIC_ATTRIBUTE_COMMAND *pCmd; //CurrentCommand; - SOURCE_DESTINATION_ALIGNMENT CD_Mask; - PARAMETERS_TYPE ParametersType; - CD_GENERIC_BYTE Multipurpose; - UINT8 CompareFlags; - COMMAND_SPECIFIC_UNION CommandSpecific; - CD_STATUS Status; - UINT8 Shift2MaskConverter; - UINT8 CurrentPortID; -} PARSER_TEMP_DATA; - - -typedef struct _WORKING_TABLE_DATA WORKING_TABLE_DATA; - - - -typedef VOID (*COMMANDS_DECODER)(PARSER_TEMP_DATA STACK_BASED * pParserTempData); -typedef VOID (*WRITE_IO_FUNCTION)(PARSER_TEMP_DATA STACK_BASED * pParserTempData); -typedef UINT32 (*READ_IO_FUNCTION)(PARSER_TEMP_DATA STACK_BASED * pParserTempData); -typedef UINT32 (*CD_GET_PARAMETERS)(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - -typedef struct _COMMANDS_PROPERTIES -{ - COMMANDS_DECODER function; - UINT8 destination; - UINT8 headersize; -} COMMANDS_PROPERTIES; - -typedef struct _INDIRECT_IO_PARSER_COMMANDS -{ - COMMANDS_DECODER func; - UINT8 csize; -} INDIRECT_IO_PARSER_COMMANDS; - -#if (PARSER_TYPE==DRIVER_TYPE_PARSER) -#pragma pack(pop) -#endif - -#endif diff --git a/src/AtomBios/includes/CD_binding.h b/src/AtomBios/includes/CD_binding.h deleted file mode 100644 index 7b021d3e..00000000 --- a/src/AtomBios/includes/CD_binding.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright 2006-2007 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifdef NT_BUILD -#ifdef LH_BUILD -#include <ntddk.h> -#else -#include <miniport.h> -#endif // LH_BUILD -#endif // NT_BUILD - - -#if ((defined DBG) || (defined DEBUG)) -#define DEBUG_PARSER 1 // enable parser debug output -#endif - -#define USE_SWITCH_COMMAND 1 -#define DRIVER_TYPE_PARSER 0x48 - -#define PARSER_TYPE DRIVER_TYPE_PARSER - -#define AllocateWorkSpace(x,y) AllocateMemory(pDeviceData,y) -#define FreeWorkSpace(x,y) ReleaseMemory(x,y) - -#define RELATIVE_TO_BIOS_IMAGE( x ) ((ULONG_PTR)x + (ULONG_PTR)((DEVICE_DATA*)pParserTempData->pDeviceData->pBIOS_Image)) -#define RELATIVE_TO_TABLE( x ) (x + (UCHAR *)(pParserTempData->pWorkingTableData->pTableHead)) - diff --git a/src/AtomBios/includes/CD_hw_services.h b/src/AtomBios/includes/CD_hw_services.h deleted file mode 100644 index 529fde59..00000000 --- a/src/AtomBios/includes/CD_hw_services.h +++ /dev/null @@ -1,318 +0,0 @@ -/* - * Copyright 2006-2007 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _HW_SERVICES_INTERFACE_ -#define _HW_SERVICES_INTERFACE_ - -#include "CD_Common_Types.h" -#include "CD_Structs.h" - - -// CD - from Command Decoder -typedef UINT16 CD_REG_INDEX; -typedef UINT8 CD_PCI_OFFSET; -typedef UINT16 CD_FB_OFFSET; -typedef UINT16 CD_SYS_IO_PORT; -typedef UINT8 CD_MEM_TYPE; -typedef UINT8 CD_MEM_SIZE; - -typedef VOID * CD_VIRT_ADDR; -typedef UINT32 CD_PHYS_ADDR; -typedef UINT32 CD_IO_ADDR; - -/***********************ATI Registers access routines**************************/ - - VOID ReadIndReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - - VOID WriteIndReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - - UINT32 ReadReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - - VOID WriteReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - - UINT32 ReadPLL32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - - VOID WritePLL32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - - UINT32 ReadMC32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - - VOID WriteMC32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - -/************************PCI Registers access routines*************************/ - - UINT8 ReadPCIReg8(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - - UINT16 ReadPCIReg16(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - - UINT32 ReadPCIReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - - VOID WritePCIReg8(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - - VOID WritePCIReg16(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - - VOID WritePCIReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - -/***************************Frame buffer access routines************************/ - - UINT32 ReadFrameBuffer32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - - VOID WriteFrameBuffer32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - -/******************System IO Registers access routines********************/ - - UINT8 ReadSysIOReg8(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - - UINT16 ReadSysIOReg16(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - - UINT32 ReadSysIOReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - - VOID WriteSysIOReg8(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - - VOID WriteSysIOReg16(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - - VOID WriteSysIOReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - -/****************************Delay routines****************************************/ - - VOID DelayMicroseconds(PARSER_TEMP_DATA STACK_BASED * pParserTempData); // take WORKING_TABLE_DATA->SourceData32 as a delay value - - VOID DelayMilliseconds(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - - VOID PostCharOutput(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - - VOID CallerDebugFunc(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - - -//************************Tracing/Debugging routines and macroses******************/ -#define KEYPRESSED -1 - -#if (DEBUG_PARSER != 0) - -#ifdef DRIVER_PARSER - -VOID CD_print_string (DEVICE_DATA STACK_BASED *pDeviceData, UINT8 *str); -VOID CD_print_value (DEVICE_DATA STACK_BASED *pDeviceData, ULONG_PTR value, UINT16 value_type ); - -// Level 1 : can use WorkingTableData or pDeviceData -#define CD_TRACE_DL1(string) CD_print_string(pDeviceData, string); -#define CD_TRACETAB_DL1(string) CD_TRACE_DL1("\n");CD_TRACE_DL1(string) -#define CD_TRACEDEC_DL1(value) CD_print_value( pDeviceData, (ULONG_PTR)value, PARSER_DEC); -#define CD_TRACEHEX_DL1(value) CD_print_value( pDeviceData, (ULONG_PTR)value, PARSER_HEX); - -// Level 2:can use pWorkingTableData -#define CD_TRACE_DL2(string) CD_print_string( pWorkingTableData->pParserTempData->pDeviceData, string); -#define CD_TRACETAB_DL2(string) CD_TRACE_DL2("\n");CD_TRACE_DL2(string) -#define CD_TRACEDEC_DL2(value) CD_print_value( pWorkingTableData->pParserTempData->pDeviceData, (ULONG_PTR)value, PARSER_DEC); -#define CD_TRACEHEX_DL2(value) CD_print_value( pWorkingTableData->pParserTempData->pDeviceData, (ULONG_PTR)value, PARSER_HEX); - -// Level 3:can use pWorkingTableData -#define CD_TRACE_DL3(string) CD_print_string( pWorkingTableData->pParserTempData->pDeviceData, string); -#define CD_TRACETAB_DL3(string) CD_TRACE_DL3("\n");CD_TRACE_DL3(string) -#define CD_TRACEDEC_DL3(value) CD_print_value( pWorkingTableData->pParserTempData->pDeviceData, value, PARSER_DEC); -#define CD_TRACEHEX_DL3(value) CD_print_value( pWorkingTableData->pParserTempData->pDeviceData, value, PARSER_HEX); - -#define CD_TRACE(string) -#define CD_WAIT(what) -#define CD_BREAKPOINT() - -#else - - -VOID CD_assert (UINT8 *file, INTN lineno); //output file/line to debug console -VOID CD_postcode(UINT8 value); //output post code to debug console -VOID CD_print (UINT8 *str); //output text to debug console -VOID CD_print_dec(UINTN value); //output value in decimal format to debug console -VOID CD_print_hex(UINT32 value, UINT8 len); //output value in hexadecimal format to debug console -VOID CD_print_buf(UINT8 *p, UINTN len); //output dump of memory to debug console -VOID CD_wait(INT32 what); //wait for KEYPRESSED=-1 or Delay value expires -VOID CD_breakpoint(); //insert int3 opcode or 0xF1 (for American Arium) - -#define CD_ASSERT(condition) if(!(condition)) CD_assert(__FILE__, __LINE__) -#define CD_POSTCODE(value) CD_postcode(value) -#define CD_TRACE(string) CD_print(string) -#define CD_TRACETAB(string) CD_print(string) -#define CD_TRACEDEC(value) CD_print_dec( (UINTN)(value)) -#define CD_TRACEHEX(value) CD_print_hex( (UINT32)(value), sizeof(value) ) -#define CD_TRACEBUF(pointer, len) CD_print_buf( (UINT8 *)(pointer), (UINTN) len) -#define CD_WAIT(what) CD_wait((INT32)what) -#define CD_BREAKPOINT() CD_breakpoint() - -#if (DEBUG_PARSER == 4) -#define CD_ASSERT_DL4(condition) if(!(condition)) CD_assert(__FILE__, __LINE__) -#define CD_POSTCODE_DL4(value) CD_postcode(value) -#define CD_TRACE_DL4(string) CD_print(string) -#define CD_TRACETAB_DL4(string) CD_print("\n\t\t");CD_print(string) -#define CD_TRACEDEC_DL4(value) CD_print_dec( (UINTN)(value)) -#define CD_TRACEHEX_DL4(value) CD_print_hex( (UINT32)(value), sizeof(value) ) -#define CD_TRACEBUF_DL4(pointer, len) CD_print_buf( (UINT8 *)(pointer), (UINTN) len) -#define CD_WAIT_DL4(what) CD_wait((INT32)what) -#define CD_BREAKPOINT_DL4() CD_breakpoint() -#else -#define CD_ASSERT_DL4(condition) -#define CD_POSTCODE_DL4(value) -#define CD_TRACE_DL4(string) -#define CD_TRACETAB_DL4(string) -#define CD_TRACEDEC_DL4(value) -#define CD_TRACEHEX_DL4(value) -#define CD_TRACEBUF_DL4(pointer, len) -#define CD_WAIT_DL4(what) -#define CD_BREAKPOINT_DL4() -#endif - -#if (DEBUG_PARSER >= 3) -#define CD_ASSERT_DL3(condition) if(!(condition)) CD_assert(__FILE__, __LINE__) -#define CD_POSTCODE_DL3(value) CD_postcode(value) -#define CD_TRACE_DL3(string) CD_print(string) -#define CD_TRACETAB_DL3(string) CD_print("\n\t\t");CD_print(string) -#define CD_TRACEDEC_DL3(value) CD_print_dec( (UINTN)(value)) -#define CD_TRACEHEX_DL3(value) CD_print_hex( (UINT32)(value), sizeof(value) ) -#define CD_TRACEBUF_DL3(pointer, len) CD_print_buf( (UINT8 *)(pointer), (UINTN) len) -#define CD_WAIT_DL3(what) CD_wait((INT32)what) -#define CD_BREAKPOINT_DL3() CD_breakpoint() -#else -#define CD_ASSERT_DL3(condition) -#define CD_POSTCODE_DL3(value) -#define CD_TRACE_DL3(string) -#define CD_TRACETAB_DL3(string) -#define CD_TRACEDEC_DL3(value) -#define CD_TRACEHEX_DL3(value) -#define CD_TRACEBUF_DL3(pointer, len) -#define CD_WAIT_DL3(what) -#define CD_BREAKPOINT_DL3() -#endif - - -#if (DEBUG_PARSER >= 2) -#define CD_ASSERT_DL2(condition) if(!(condition)) CD_assert(__FILE__, __LINE__) -#define CD_POSTCODE_DL2(value) CD_postcode(value) -#define CD_TRACE_DL2(string) CD_print(string) -#define CD_TRACETAB_DL2(string) CD_print("\n\t");CD_print(string) -#define CD_TRACEDEC_DL2(value) CD_print_dec( (UINTN)(value)) -#define CD_TRACEHEX_DL2(value) CD_print_hex( (UINT32)(value), sizeof(value) ) -#define CD_TRACEBUF_DL2(pointer, len) CD_print_buf( (UINT8 *)(pointer), (UINTN) len) -#define CD_WAIT_DL2(what) CD_wait((INT32)what) -#define CD_BREAKPOINT_DL2() CD_breakpoint() -#else -#define CD_ASSERT_DL2(condition) -#define CD_POSTCODE_DL2(value) -#define CD_TRACE_DL2(string) -#define CD_TRACETAB_DL2(string) -#define CD_TRACEDEC_DL2(value) -#define CD_TRACEHEX_DL2(value) -#define CD_TRACEBUF_DL2(pointer, len) -#define CD_WAIT_DL2(what) -#define CD_BREAKPOINT_DL2() -#endif - - -#if (DEBUG_PARSER >= 1) -#define CD_ASSERT_DL1(condition) if(!(condition)) CD_assert(__FILE__, __LINE__) -#define CD_POSTCODE_DL1(value) CD_postcode(value) -#define CD_TRACE_DL1(string) CD_print(string) -#define CD_TRACETAB_DL1(string) CD_print("\n");CD_print(string) -#define CD_TRACEDEC_DL1(value) CD_print_dec( (UINTN)(value)) -#define CD_TRACEHEX_DL1(value) CD_print_hex( (UINT32)(value), sizeof(value) ) -#define CD_TRACEBUF_DL1(pointer, len) CD_print_buf( (UINT8 *)(pointer), (UINTN) len) -#define CD_WAIT_DL1(what) CD_wait((INT32)what) -#define CD_BREAKPOINT_DL1() CD_breakpoint() -#else -#define CD_ASSERT_DL1(condition) -#define CD_POSTCODE_DL1(value) -#define CD_TRACE_DL1(string) -#define CD_TRACETAB_DL1(string) -#define CD_TRACEDEC_DL1(value) -#define CD_TRACEHEX_DL1(value) -#define CD_TRACEBUF_DL1(pointer, len) -#define CD_WAIT_DL1(what) -#define CD_BREAKPOINT_DL1() -#endif - -#endif //#ifdef DRIVER_PARSER - - -#else - -#define CD_ASSERT(condition) -#define CD_POSTCODE(value) -#define CD_TRACE(string) -#define CD_TRACEDEC(value) -#define CD_TRACEHEX(value) -#define CD_TRACEBUF(pointer, len) -#define CD_WAIT(what) -#define CD_BREAKPOINT() - -#define CD_ASSERT_DL4(condition) -#define CD_POSTCODE_DL4(value) -#define CD_TRACE_DL4(string) -#define CD_TRACETAB_DL4(string) -#define CD_TRACEDEC_DL4(value) -#define CD_TRACEHEX_DL4(value) -#define CD_TRACEBUF_DL4(pointer, len) -#define CD_WAIT_DL4(what) -#define CD_BREAKPOINT_DL4() - -#define CD_ASSERT_DL3(condition) -#define CD_POSTCODE_DL3(value) -#define CD_TRACE_DL3(string) -#define CD_TRACETAB_DL3(string) -#define CD_TRACEDEC_DL3(value) -#define CD_TRACEHEX_DL3(value) -#define CD_TRACEBUF_DL3(pointer, len) -#define CD_WAIT_DL3(what) -#define CD_BREAKPOINT_DL3() - -#define CD_ASSERT_DL2(condition) -#define CD_POSTCODE_DL2(value) -#define CD_TRACE_DL2(string) -#define CD_TRACETAB_DL2(string) -#define CD_TRACEDEC_DL2(value) -#define CD_TRACEHEX_DL2(value) -#define CD_TRACEBUF_DL2(pointer, len) -#define CD_WAIT_DL2(what) -#define CD_BREAKPOINT_DL2() - -#define CD_ASSERT_DL1(condition) -#define CD_POSTCODE_DL1(value) -#define CD_TRACE_DL1(string) -#define CD_TRACETAB_DL1(string) -#define CD_TRACEDEC_DL1(value) -#define CD_TRACEHEX_DL1(value) -#define CD_TRACEBUF_DL1(pointer, len) -#define CD_WAIT_DL1(what) -#define CD_BREAKPOINT_DL1() - - -#endif //#if (DEBUG_PARSER > 0) - - -#ifdef CHECKSTACK -VOID CD_fillstack(UINT16 size); -UINT16 CD_checkstack(UINT16 size); -#define CD_CHECKSTACK(stacksize) CD_checkstack(stacksize) -#define CD_FILLSTACK(stacksize) CD_fillstack(stacksize) -#else -#define CD_CHECKSTACK(stacksize) 0 -#define CD_FILLSTACK(stacksize) -#endif - - -#endif diff --git a/src/AtomBios/includes/Decoder.h b/src/AtomBios/includes/Decoder.h deleted file mode 100644 index cc533efb..00000000 --- a/src/AtomBios/includes/Decoder.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - * Copyright 2006-2007 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/*++ - -Module Name: - -Decoder.h - -Abstract: - -Includes all helper headers - -Revision History: - -NEG:27.08.2002 Initiated. ---*/ -#ifndef _DECODER_H_ -#define _DECODER_H_ -#define WS_QUOTIENT_C 64 -#define WS_REMINDER_C (WS_QUOTIENT_C+1) -#define WS_DATAPTR_C (WS_REMINDER_C+1) -#define WS_SHIFT_C (WS_DATAPTR_C+1) -#define WS_OR_MASK_C (WS_SHIFT_C+1) -#define WS_AND_MASK_C (WS_OR_MASK_C+1) -#define WS_FB_WINDOW_C (WS_AND_MASK_C+1) -#define WS_ATTRIBUTES_C (WS_FB_WINDOW_C+1) -#define WS_REGPTR_C (WS_ATTRIBUTES_C+1) -#define PARSER_VERSION_MAJOR 0x00000000 -#define PARSER_VERSION_MINOR 0x0000000E -#define PARSER_VERSION (PARSER_VERSION_MAJOR | PARSER_VERSION_MINOR) - -#include "CD_Common_Types.h" - -#include "atombios.h" - -/* these depends on some struct defined in atombios.h */ -#include "CD_binding.h" -#include "CD_hw_services.h" -#include "CD_Structs.h" -#include "CD_Opcodes.h" -#include "CD_Definitions.h" - -#if ATOM_BIG_ENDIAN -extern UINT16 ATOM_BSWAP16(UINT16 x); -extern UINT32 ATOM_BSWAP32(UINT32 x); - -#define CPU_TO_UINT16LE(x) ATOM_BSWAP16(x) -#define CPU_TO_UINT32LE(x) ATOM_BSWAP32(x) -#define UINT16LE_TO_CPU(x) ATOM_BSWAP16(x) -#define UINT32LE_TO_CPU(x) ATOM_BSWAP32(x) -#else -#define CPU_TO_UINT16LE(x) (x) -#define CPU_TO_UINT32LE(x) (x) -#define UINT16LE_TO_CPU(x) (x) -#define UINT32LE_TO_CPU(x) (x) -#endif - -#define SOURCE_ONLY_CMD_TYPE 0//0xFE -#define SOURCE_DESTINATION_CMD_TYPE 1//0xFD -#define DESTINATION_ONLY_CMD_TYPE 2//0xFC - -#define ACCESS_TYPE_BYTE 0//0xF9 -#define ACCESS_TYPE_WORD 1//0xF8 -#define ACCESS_TYPE_DWORD 2//0xF7 -#define SWITCH_TYPE_ACCESS 3//0xF6 - -#define CD_CONTINUE 0//0xFB -#define CD_STOP 1//0xFA - - -#define IS_END_OF_TABLE(cmd) ((cmd) == EOT_OPCODE) -#define IS_COMMAND_VALID(cmd) (((cmd)<=LastValidCommand)&&((cmd)>=FirstValidCommand)) -#define IS_IT_SHIFT_COMMAND(Opcode) ((Opcode<=SHIFT_RIGHT_MC_OPCODE)&&(Opcode>=SHIFT_LEFT_REG_OPCODE)) -#define IS_IT_XXXX_COMMAND(Group, Opcode) ((Opcode<=Group##_MC_OPCODE)&&(Opcode>=Group##_REG_OPCODE)) -#define CheckCaseAndAdjustIP_Macro(size) \ - if (pParserTempData->SourceData32==(UINT32)((CASE_OFFSET*)pParserTempData->pWorkingTableData->IP)->XX_Access.size##.Access.Value){\ - pParserTempData->CommandSpecific.ContinueSwitch = CD_STOP;\ - pParserTempData->pWorkingTableData->IP =(COMMAND_HEADER_POINTER *) RELATIVE_TO_TABLE(((CASE_OFFSET*)pParserTempData->pWorkingTableData->IP)->XX_Access.size##.Access.JumpOffset);\ - }else{\ - pParserTempData->pWorkingTableData->IP+=(sizeof (CASE_##size##ACCESS)\ - +sizeof(((CASE_OFFSET*)pParserTempData->pWorkingTableData->IP)->CaseSignature));\ - } - -#endif -/* pWorkingTableData->pCmd->Header.Attribute.SourceAlignment=alignmentLowerWord;\*/ - -// EOF diff --git a/src/AtomBios/includes/ObjectID.h b/src/AtomBios/includes/ObjectID.h deleted file mode 100644 index c714179d..00000000 --- a/src/AtomBios/includes/ObjectID.h +++ /dev/null @@ -1,643 +0,0 @@ -/* -* Copyright 2006-2007 Advanced Micro Devices, Inc. -* -* Permission is hereby granted, free of charge, to any person obtaining a -* copy of this software and associated documentation files (the "Software"), -* to deal in the Software without restriction, including without limitation -* the rights to use, copy, modify, merge, publish, distribute, sublicense, -* and/or sell copies of the Software, and to permit persons to whom the -* Software is furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR -* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, -* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -* OTHER DEALINGS IN THE SOFTWARE. -*/ -/* based on stg/asic_reg/drivers/inc/asic_reg/ObjectID.h ver 23 */ - -#ifndef _OBJECTID_H -#define _OBJECTID_H - -#if defined(_X86_) -#pragma pack(1) -#endif - -/****************************************************/ -/* Graphics Object Type Definition */ -/****************************************************/ -#define GRAPH_OBJECT_TYPE_NONE 0x0 -#define GRAPH_OBJECT_TYPE_GPU 0x1 -#define GRAPH_OBJECT_TYPE_ENCODER 0x2 -#define GRAPH_OBJECT_TYPE_CONNECTOR 0x3 -#define GRAPH_OBJECT_TYPE_ROUTER 0x4 -/* deleted */ - -/****************************************************/ -/* Encoder Object ID Definition */ -/****************************************************/ -#define ENCODER_OBJECT_ID_NONE 0x00 - -/* Radeon Class Display Hardware */ -#define ENCODER_OBJECT_ID_INTERNAL_LVDS 0x01 -#define ENCODER_OBJECT_ID_INTERNAL_TMDS1 0x02 -#define ENCODER_OBJECT_ID_INTERNAL_TMDS2 0x03 -#define ENCODER_OBJECT_ID_INTERNAL_DAC1 0x04 -#define ENCODER_OBJECT_ID_INTERNAL_DAC2 0x05 /* TV/CV DAC */ -#define ENCODER_OBJECT_ID_INTERNAL_SDVOA 0x06 -#define ENCODER_OBJECT_ID_INTERNAL_SDVOB 0x07 - -/* External Third Party Encoders */ -#define ENCODER_OBJECT_ID_SI170B 0x08 -#define ENCODER_OBJECT_ID_CH7303 0x09 -#define ENCODER_OBJECT_ID_CH7301 0x0A -#define ENCODER_OBJECT_ID_INTERNAL_DVO1 0x0B /* This belongs to Radeon Class Display Hardware */ -#define ENCODER_OBJECT_ID_EXTERNAL_SDVOA 0x0C -#define ENCODER_OBJECT_ID_EXTERNAL_SDVOB 0x0D -#define ENCODER_OBJECT_ID_TITFP513 0x0E -#define ENCODER_OBJECT_ID_INTERNAL_LVTM1 0x0F /* not used for Radeon */ -#define ENCODER_OBJECT_ID_VT1623 0x10 -#define ENCODER_OBJECT_ID_HDMI_SI1930 0x11 -#define ENCODER_OBJECT_ID_HDMI_INTERNAL 0x12 -/* Kaleidoscope (KLDSCP) Class Display Hardware (internal) */ -#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 0x13 -#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1 0x14 -#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1 0x15 -#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2 0x16 /* Shared with CV/TV and CRT */ -#define ENCODER_OBJECT_ID_SI178 0X17 /* External TMDS (dual link, no HDCP.) */ -#define ENCODER_OBJECT_ID_MVPU_FPGA 0x18 /* MVPU FPGA chip */ -#define ENCODER_OBJECT_ID_INTERNAL_DDI 0x19 -#define ENCODER_OBJECT_ID_VT1625 0x1A -#define ENCODER_OBJECT_ID_HDMI_SI1932 0x1B -#define ENCODER_OBJECT_ID_DP_AN9801 0x1C -#define ENCODER_OBJECT_ID_DP_DP501 0x1D -#define ENCODER_OBJECT_ID_INTERNAL_UNIPHY 0x1E -#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA 0x1F -#define ENCODER_OBJECT_ID_INTERNAL_UNIPHY1 0x20 -#define ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 0x21 - -#define ENCODER_OBJECT_ID_GENERAL_EXTERNAL_DVO 0xFF - -/****************************************************/ -/* Connector Object ID Definition */ -/****************************************************/ -#define CONNECTOR_OBJECT_ID_NONE 0x00 -#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I 0x01 -#define CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I 0x02 -#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D 0x03 -#define CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D 0x04 -#define CONNECTOR_OBJECT_ID_VGA 0x05 -#define CONNECTOR_OBJECT_ID_COMPOSITE 0x06 -#define CONNECTOR_OBJECT_ID_SVIDEO 0x07 -#define CONNECTOR_OBJECT_ID_YPbPr 0x08 -#define CONNECTOR_OBJECT_ID_D_CONNECTOR 0x09 -#define CONNECTOR_OBJECT_ID_9PIN_DIN 0x0A /* Supports both CV & TV */ -#define CONNECTOR_OBJECT_ID_SCART 0x0B -#define CONNECTOR_OBJECT_ID_HDMI_TYPE_A 0x0C -#define CONNECTOR_OBJECT_ID_HDMI_TYPE_B 0x0D -#define CONNECTOR_OBJECT_ID_LVDS 0x0E -#define CONNECTOR_OBJECT_ID_7PIN_DIN 0x0F -#define CONNECTOR_OBJECT_ID_PCIE_CONNECTOR 0x10 -#define CONNECTOR_OBJECT_ID_CROSSFIRE 0x11 -#define CONNECTOR_OBJECT_ID_HARDCODE_DVI 0x12 -#define CONNECTOR_OBJECT_ID_DISPLAYPORT 0x13 -#define CONNECTOR_OBJECT_ID_eDP 0x14 -#define CONNECTOR_OBJECT_ID_MXM 0x15 - -/* deleted */ - -/****************************************************/ -/* Router Object ID Definition */ -/****************************************************/ -#define ROUTER_OBJECT_ID_NONE 0x00 -#define ROUTER_OBJECT_ID_I2C_EXTENDER_CNTL 0x01 - -/****************************************************/ -/* Generic Object ID Definition */ -/****************************************************/ -#define GENERIC_OBJECT_ID_NONE 0x00 -#define GENERIC_OBJECT_ID_GLSYNC 0x01 -#define GENERIC_OBJECT_ID_PX2_NON_DRIVABLE 0x02 -#define GENERIC_OBJECT_ID_MXM_OPM 0x03 - -/****************************************************/ -/* Graphics Object ENUM ID Definition */ -/****************************************************/ -#define GRAPH_OBJECT_ENUM_ID1 0x01 -#define GRAPH_OBJECT_ENUM_ID2 0x02 -#define GRAPH_OBJECT_ENUM_ID3 0x03 -#define GRAPH_OBJECT_ENUM_ID4 0x04 -#define GRAPH_OBJECT_ENUM_ID5 0x05 -#define GRAPH_OBJECT_ENUM_ID6 0x06 -#define GRAPH_OBJECT_ENUM_ID7 0x07 - -/****************************************************/ -/* Graphics Object ID Bit definition */ -/****************************************************/ -#define OBJECT_ID_MASK 0x00FF -#define ENUM_ID_MASK 0x0700 -#define RESERVED1_ID_MASK 0x0800 -#define OBJECT_TYPE_MASK 0x7000 -#define RESERVED2_ID_MASK 0x8000 - -#define OBJECT_ID_SHIFT 0x00 -#define ENUM_ID_SHIFT 0x08 -#define OBJECT_TYPE_SHIFT 0x0C - - -/****************************************************/ -/* Graphics Object family definition */ -/****************************************************/ -#define CONSTRUCTOBJECTFAMILYID(GRAPHICS_OBJECT_TYPE, GRAPHICS_OBJECT_ID) (GRAPHICS_OBJECT_TYPE << OBJECT_TYPE_SHIFT | \ - GRAPHICS_OBJECT_ID << OBJECT_ID_SHIFT) -/****************************************************/ -/* GPU Object ID definition - Shared with BIOS */ -/****************************************************/ -#define GPU_ENUM_ID1 ( GRAPH_OBJECT_TYPE_GPU << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT) - -/****************************************************/ -/* Encoder Object ID definition - Shared with BIOS */ -/****************************************************/ -/* -#define ENCODER_INTERNAL_LVDS_ENUM_ID1 0x2101 -#define ENCODER_INTERNAL_TMDS1_ENUM_ID1 0x2102 -#define ENCODER_INTERNAL_TMDS2_ENUM_ID1 0x2103 -#define ENCODER_INTERNAL_DAC1_ENUM_ID1 0x2104 -#define ENCODER_INTERNAL_DAC2_ENUM_ID1 0x2105 -#define ENCODER_INTERNAL_SDVOA_ENUM_ID1 0x2106 -#define ENCODER_INTERNAL_SDVOB_ENUM_ID1 0x2107 -#define ENCODER_SIL170B_ENUM_ID1 0x2108 -#define ENCODER_CH7303_ENUM_ID1 0x2109 -#define ENCODER_CH7301_ENUM_ID1 0x210A -#define ENCODER_INTERNAL_DVO1_ENUM_ID1 0x210B -#define ENCODER_EXTERNAL_SDVOA_ENUM_ID1 0x210C -#define ENCODER_EXTERNAL_SDVOB_ENUM_ID1 0x210D -#define ENCODER_TITFP513_ENUM_ID1 0x210E -#define ENCODER_INTERNAL_LVTM1_ENUM_ID1 0x210F -#define ENCODER_VT1623_ENUM_ID1 0x2110 -#define ENCODER_HDMI_SI1930_ENUM_ID1 0x2111 -#define ENCODER_HDMI_INTERNAL_ENUM_ID1 0x2112 -#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1 0x2113 -#define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1 0x2114 -#define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1 0x2115 -#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 0x2116 -#define ENCODER_SI178_ENUM_ID1 0x2117 -#define ENCODER_MVPU_FPGA_ENUM_ID1 0x2118 -#define ENCODER_INTERNAL_DDI_ENUM_ID1 0x2119 -#define ENCODER_VT1625_ENUM_ID1 0x211A -#define ENCODER_HDMI_SI1932_ENUM_ID1 0x211B -#define ENCODER_ENCODER_DP_AN9801_ENUM_ID1 0x211C -#define ENCODER_DP_DP501_ENUM_ID1 0x211D -#define ENCODER_INTERNAL_UNIPHY_ENUM_ID1 0x211E -*/ -#define ENCODER_INTERNAL_LVDS_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - ENCODER_OBJECT_ID_INTERNAL_LVDS << OBJECT_ID_SHIFT) - -#define ENCODER_INTERNAL_TMDS1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - ENCODER_OBJECT_ID_INTERNAL_TMDS1 << OBJECT_ID_SHIFT) - -#define ENCODER_INTERNAL_TMDS2_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - ENCODER_OBJECT_ID_INTERNAL_TMDS2 << OBJECT_ID_SHIFT) - -#define ENCODER_INTERNAL_DAC1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - ENCODER_OBJECT_ID_INTERNAL_DAC1 << OBJECT_ID_SHIFT) - -#define ENCODER_INTERNAL_DAC2_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - ENCODER_OBJECT_ID_INTERNAL_DAC2 << OBJECT_ID_SHIFT) - -#define ENCODER_INTERNAL_SDVOA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - ENCODER_OBJECT_ID_INTERNAL_SDVOA << OBJECT_ID_SHIFT) - -#define ENCODER_INTERNAL_SDVOA_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ - ENCODER_OBJECT_ID_INTERNAL_SDVOA << OBJECT_ID_SHIFT) - -#define ENCODER_INTERNAL_SDVOB_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - ENCODER_OBJECT_ID_INTERNAL_SDVOB << OBJECT_ID_SHIFT) - -#define ENCODER_SIL170B_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - ENCODER_OBJECT_ID_SI170B << OBJECT_ID_SHIFT) - -#define ENCODER_CH7303_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - ENCODER_OBJECT_ID_CH7303 << OBJECT_ID_SHIFT) - -#define ENCODER_CH7301_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - ENCODER_OBJECT_ID_CH7301 << OBJECT_ID_SHIFT) - -#define ENCODER_INTERNAL_DVO1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - ENCODER_OBJECT_ID_INTERNAL_DVO1 << OBJECT_ID_SHIFT) - -#define ENCODER_EXTERNAL_SDVOA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - ENCODER_OBJECT_ID_EXTERNAL_SDVOA << OBJECT_ID_SHIFT) - -#define ENCODER_EXTERNAL_SDVOA_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ - ENCODER_OBJECT_ID_EXTERNAL_SDVOA << OBJECT_ID_SHIFT) - - -#define ENCODER_EXTERNAL_SDVOB_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - ENCODER_OBJECT_ID_EXTERNAL_SDVOB << OBJECT_ID_SHIFT) - - -#define ENCODER_TITFP513_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - ENCODER_OBJECT_ID_TITFP513 << OBJECT_ID_SHIFT) - -#define ENCODER_INTERNAL_LVTM1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - ENCODER_OBJECT_ID_INTERNAL_LVTM1 << OBJECT_ID_SHIFT) - -#define ENCODER_VT1623_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - ENCODER_OBJECT_ID_VT1623 << OBJECT_ID_SHIFT) - -#define ENCODER_HDMI_SI1930_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - ENCODER_OBJECT_ID_HDMI_SI1930 << OBJECT_ID_SHIFT) - -#define ENCODER_HDMI_INTERNAL_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - ENCODER_OBJECT_ID_HDMI_INTERNAL << OBJECT_ID_SHIFT) - -#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 << OBJECT_ID_SHIFT) - - -#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ - ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 << OBJECT_ID_SHIFT) - - -#define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1 << OBJECT_ID_SHIFT) - -#define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1 << OBJECT_ID_SHIFT) - -#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2 << OBJECT_ID_SHIFT) // Shared with CV/TV and CRT - -#define ENCODER_SI178_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - ENCODER_OBJECT_ID_SI178 << OBJECT_ID_SHIFT) - -#define ENCODER_MVPU_FPGA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - ENCODER_OBJECT_ID_MVPU_FPGA << OBJECT_ID_SHIFT) - -#define ENCODER_INTERNAL_DDI_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - ENCODER_OBJECT_ID_INTERNAL_DDI << OBJECT_ID_SHIFT) - -#define ENCODER_VT1625_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - ENCODER_OBJECT_ID_VT1625 << OBJECT_ID_SHIFT) - -#define ENCODER_HDMI_SI1932_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - ENCODER_OBJECT_ID_HDMI_SI1932 << OBJECT_ID_SHIFT) - -#define ENCODER_DP_DP501_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - ENCODER_OBJECT_ID_DP_DP501 << OBJECT_ID_SHIFT) - -#define ENCODER_DP_AN9801_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - ENCODER_OBJECT_ID_DP_AN9801 << OBJECT_ID_SHIFT) - -#define ENCODER_INTERNAL_UNIPHY_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - ENCODER_OBJECT_ID_INTERNAL_UNIPHY << OBJECT_ID_SHIFT) - -#define ENCODER_INTERNAL_UNIPHY_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ - ENCODER_OBJECT_ID_INTERNAL_UNIPHY << OBJECT_ID_SHIFT) - -#define ENCODER_INTERNAL_KLDSCP_LVTMA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA << OBJECT_ID_SHIFT) - -#define ENCODER_INTERNAL_UNIPHY1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - ENCODER_OBJECT_ID_INTERNAL_UNIPHY1 << OBJECT_ID_SHIFT) - -#define ENCODER_INTERNAL_UNIPHY1_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ - ENCODER_OBJECT_ID_INTERNAL_UNIPHY1 << OBJECT_ID_SHIFT) - -#define ENCODER_INTERNAL_UNIPHY2_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 << OBJECT_ID_SHIFT) - -#define ENCODER_INTERNAL_UNIPHY2_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ - ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 << OBJECT_ID_SHIFT) - -#define ENCODER_GENERAL_EXTERNAL_DVO_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - ENCODER_OBJECT_ID_GENERAL_EXTERNAL_DVO << OBJECT_ID_SHIFT) - -/****************************************************/ -/* Connector Object ID definition - Shared with BIOS */ -/****************************************************/ -/* -#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID1 0x3101 -#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID1 0x3102 -#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID1 0x3103 -#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID1 0x3104 -#define CONNECTOR_VGA_ENUM_ID1 0x3105 -#define CONNECTOR_COMPOSITE_ENUM_ID1 0x3106 -#define CONNECTOR_SVIDEO_ENUM_ID1 0x3107 -#define CONNECTOR_YPbPr_ENUM_ID1 0x3108 -#define CONNECTOR_D_CONNECTORE_ENUM_ID1 0x3109 -#define CONNECTOR_9PIN_DIN_ENUM_ID1 0x310A -#define CONNECTOR_SCART_ENUM_ID1 0x310B -#define CONNECTOR_HDMI_TYPE_A_ENUM_ID1 0x310C -#define CONNECTOR_HDMI_TYPE_B_ENUM_ID1 0x310D -#define CONNECTOR_LVDS_ENUM_ID1 0x310E -#define CONNECTOR_7PIN_DIN_ENUM_ID1 0x310F -#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID1 0x3110 -*/ -#define CONNECTOR_LVDS_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_LVDS << OBJECT_ID_SHIFT) - -#define CONNECTOR_LVDS_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_LVDS << OBJECT_ID_SHIFT) - -#define CONNECTOR_eDP_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_eDP << OBJECT_ID_SHIFT) - -#define CONNECTOR_eDP_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_eDP << OBJECT_ID_SHIFT) - -#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I << OBJECT_ID_SHIFT) - -#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I << OBJECT_ID_SHIFT) - -#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I << OBJECT_ID_SHIFT) - -#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I << OBJECT_ID_SHIFT) - -#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT) - -#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT) - -#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT) - -#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT) - -#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID3 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT) - -#define CONNECTOR_VGA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_VGA << OBJECT_ID_SHIFT) - -#define CONNECTOR_VGA_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_VGA << OBJECT_ID_SHIFT) - -#define CONNECTOR_COMPOSITE_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_COMPOSITE << OBJECT_ID_SHIFT) - -#define CONNECTOR_COMPOSITE_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_COMPOSITE << OBJECT_ID_SHIFT) - -#define CONNECTOR_SVIDEO_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_SVIDEO << OBJECT_ID_SHIFT) - -#define CONNECTOR_SVIDEO_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_SVIDEO << OBJECT_ID_SHIFT) - -#define CONNECTOR_YPbPr_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_YPbPr << OBJECT_ID_SHIFT) - -#define CONNECTOR_YPbPr_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_YPbPr << OBJECT_ID_SHIFT) - -#define CONNECTOR_D_CONNECTOR_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_D_CONNECTOR << OBJECT_ID_SHIFT) - -#define CONNECTOR_D_CONNECTOR_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_D_CONNECTOR << OBJECT_ID_SHIFT) - -#define CONNECTOR_9PIN_DIN_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_9PIN_DIN << OBJECT_ID_SHIFT) - -#define CONNECTOR_9PIN_DIN_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_9PIN_DIN << OBJECT_ID_SHIFT) - -#define CONNECTOR_SCART_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_SCART << OBJECT_ID_SHIFT) - -#define CONNECTOR_SCART_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_SCART << OBJECT_ID_SHIFT) - -#define CONNECTOR_HDMI_TYPE_A_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT) - -#define CONNECTOR_HDMI_TYPE_A_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT) - -#define CONNECTOR_HDMI_TYPE_A_ENUM_ID3 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT) - -#define CONNECTOR_HDMI_TYPE_B_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_HDMI_TYPE_B << OBJECT_ID_SHIFT) - -#define CONNECTOR_HDMI_TYPE_B_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_HDMI_TYPE_B << OBJECT_ID_SHIFT) - -#define CONNECTOR_7PIN_DIN_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_7PIN_DIN << OBJECT_ID_SHIFT) -#define CONNECTOR_7PIN_DIN_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_7PIN_DIN << OBJECT_ID_SHIFT) - -#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_PCIE_CONNECTOR << OBJECT_ID_SHIFT) - -#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_PCIE_CONNECTOR << OBJECT_ID_SHIFT) - -#define CONNECTOR_CROSSFIRE_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_CROSSFIRE << OBJECT_ID_SHIFT) - -#define CONNECTOR_CROSSFIRE_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_CROSSFIRE << OBJECT_ID_SHIFT) - - -#define CONNECTOR_HARDCODE_DVI_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_HARDCODE_DVI << OBJECT_ID_SHIFT) - -#define CONNECTOR_HARDCODE_DVI_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_HARDCODE_DVI << OBJECT_ID_SHIFT) - -#define CONNECTOR_DISPLAYPORT_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT) - -#define CONNECTOR_DISPLAYPORT_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT) - -#define CONNECTOR_DISPLAYPORT_ENUM_ID3 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT) - -#define CONNECTOR_DISPLAYPORT_ENUM_ID4 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID4 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT) - -#define CONNECTOR_DISPLAYPORT_ENUM_ID5 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID5 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT) - -#define CONNECTOR_DISPLAYPORT_ENUM_ID6 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID6 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT) - -#define CONNECTOR_MXM_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT) //Mapping to MXM_DP_A - -#define CONNECTOR_MXM_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT) //Mapping to MXM_DP_B - -#define CONNECTOR_MXM_ENUM_ID3 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT) //Mapping to MXM_DP_C - -#define CONNECTOR_MXM_ENUM_ID4 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID4 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT) //Mapping to MXM_DP_D - -#define CONNECTOR_MXM_ENUM_ID5 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID5 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT) //Mapping to MXM_LVDS_TXxx - -#define CONNECTOR_MXM_ENUM_ID6 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID6 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT) //Mapping to MXM_LVDS_UXxx - -#define CONNECTOR_MXM_ENUM_ID7 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID7 << ENUM_ID_SHIFT |\ - CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT) //Mapping to MXM_DAC - -/****************************************************/ -/* Router Object ID definition - Shared with BIOS */ -/****************************************************/ -#define ROUTER_I2C_EXTENDER_CNTL_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ROUTER << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - ROUTER_OBJECT_ID_I2C_EXTENDER_CNTL << OBJECT_ID_SHIFT) - -/* deleted */ - -/****************************************************/ -/* Generic Object ID definition - Shared with BIOS */ -/****************************************************/ -#define GENERICOBJECT_GLSYNC_ENUM_ID1 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - GENERIC_OBJECT_ID_GLSYNC << OBJECT_ID_SHIFT) - -#define GENERICOBJECT_PX2_NON_DRIVABLE_ID1 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - GENERIC_OBJECT_ID_PX2_NON_DRIVABLE<< OBJECT_ID_SHIFT) - -#define GENERICOBJECT_PX2_NON_DRIVABLE_ID2 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ - GENERIC_OBJECT_ID_PX2_NON_DRIVABLE<< OBJECT_ID_SHIFT) - -#define GENERICOBJECT_MXM_OPM_ENUM_ID1 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - GENERIC_OBJECT_ID_MXM_OPM << OBJECT_ID_SHIFT) - -/****************************************************/ -/* Object Cap definition - Shared with BIOS */ -/****************************************************/ -#define GRAPHICS_OBJECT_CAP_I2C 0x00000001L -#define GRAPHICS_OBJECT_CAP_TABLE_ID 0x00000002L - - -#define GRAPHICS_OBJECT_I2CCOMMAND_TABLE_ID 0x01 -#define GRAPHICS_OBJECT_HOTPLUGDETECTIONINTERUPT_TABLE_ID 0x02 -#define GRAPHICS_OBJECT_ENCODER_OUTPUT_PROTECTION_TABLE_ID 0x03 - -#if defined(_X86_) -#pragma pack() -#endif - -#endif /*GRAPHICTYPE */ - - - - diff --git a/src/AtomBios/includes/atombios.h b/src/AtomBios/includes/atombios.h deleted file mode 100644 index 1bc72c31..00000000 --- a/src/AtomBios/includes/atombios.h +++ /dev/null @@ -1,6137 +0,0 @@ -/* - * Copyright 2006-2007 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - - -/****************************************************************************/ -/*Portion I: Definitions shared between VBIOS and Driver */ -/****************************************************************************/ - - -#ifndef _ATOMBIOS_H -#define _ATOMBIOS_H - -#define ATOM_VERSION_MAJOR 0x00020000 -#define ATOM_VERSION_MINOR 0x00000002 - -#define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR | ATOM_VERSION_MINOR) - -/* Endianness should be specified before inclusion, - * default to little endian - */ -#ifndef ATOM_BIG_ENDIAN -#error Endian not specified -#endif - -#ifdef _H2INC - #ifndef ULONG - typedef unsigned long ULONG; - #endif - - #ifndef UCHAR - typedef unsigned char UCHAR; - #endif - - #ifndef USHORT - typedef unsigned short USHORT; - #endif -#endif - -#define ATOM_DAC_A 0 -#define ATOM_DAC_B 1 -#define ATOM_EXT_DAC 2 - -#define ATOM_CRTC1 0 -#define ATOM_CRTC2 1 -#define ATOM_CRTC3 2 -#define ATOM_CRTC4 3 -#define ATOM_CRTC5 4 -#define ATOM_CRTC6 5 -#define ATOM_CRTC_INVALID 0xFF - -#define ATOM_DIGA 0 -#define ATOM_DIGB 1 - -#define ATOM_PPLL1 0 -#define ATOM_PPLL2 1 -#define ATOM_DCPLL 2 -#define ATOM_PPLL_INVALID 0xFF - -#define ATOM_SCALER1 0 -#define ATOM_SCALER2 1 - -#define ATOM_SCALER_DISABLE 0 -#define ATOM_SCALER_CENTER 1 -#define ATOM_SCALER_EXPANSION 2 -#define ATOM_SCALER_MULTI_EX 3 - -#define ATOM_DISABLE 0 -#define ATOM_ENABLE 1 -#define ATOM_LCD_BLOFF (ATOM_DISABLE+2) -#define ATOM_LCD_BLON (ATOM_ENABLE+2) -#define ATOM_LCD_BL_BRIGHTNESS_CONTROL (ATOM_ENABLE+3) -#define ATOM_LCD_SELFTEST_START (ATOM_DISABLE+5) -#define ATOM_LCD_SELFTEST_STOP (ATOM_ENABLE+5) -#define ATOM_ENCODER_INIT (ATOM_DISABLE+7) -#define ATOM_GET_STATUS (ATOM_DISABLE+8) - -#define ATOM_BLANKING 1 -#define ATOM_BLANKING_OFF 0 - -#define ATOM_CURSOR1 0 -#define ATOM_CURSOR2 1 - -#define ATOM_ICON1 0 -#define ATOM_ICON2 1 - -#define ATOM_CRT1 0 -#define ATOM_CRT2 1 - -#define ATOM_TV_NTSC 1 -#define ATOM_TV_NTSCJ 2 -#define ATOM_TV_PAL 3 -#define ATOM_TV_PALM 4 -#define ATOM_TV_PALCN 5 -#define ATOM_TV_PALN 6 -#define ATOM_TV_PAL60 7 -#define ATOM_TV_SECAM 8 -#define ATOM_TV_CV 16 - -#define ATOM_DAC1_PS2 1 -#define ATOM_DAC1_CV 2 -#define ATOM_DAC1_NTSC 3 -#define ATOM_DAC1_PAL 4 - -#define ATOM_DAC2_PS2 ATOM_DAC1_PS2 -#define ATOM_DAC2_CV ATOM_DAC1_CV -#define ATOM_DAC2_NTSC ATOM_DAC1_NTSC -#define ATOM_DAC2_PAL ATOM_DAC1_PAL - -#define ATOM_PM_ON 0 -#define ATOM_PM_STANDBY 1 -#define ATOM_PM_SUSPEND 2 -#define ATOM_PM_OFF 3 - -/* Bit0:{=0:single, =1:dual}, - Bit1 {=0:666RGB, =1:888RGB}, - Bit2:3:{Grey level} - Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}*/ - -#define ATOM_PANEL_MISC_DUAL 0x00000001 -#define ATOM_PANEL_MISC_888RGB 0x00000002 -#define ATOM_PANEL_MISC_GREY_LEVEL 0x0000000C -#define ATOM_PANEL_MISC_FPDI 0x00000010 -#define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT 2 -#define ATOM_PANEL_MISC_SPATIAL 0x00000020 -#define ATOM_PANEL_MISC_TEMPORAL 0x00000040 -#define ATOM_PANEL_MISC_API_ENABLED 0x00000080 - - -#define MEMTYPE_DDR1 "DDR1" -#define MEMTYPE_DDR2 "DDR2" -#define MEMTYPE_DDR3 "DDR3" -#define MEMTYPE_DDR4 "DDR4" - -#define ASIC_BUS_TYPE_PCI "PCI" -#define ASIC_BUS_TYPE_AGP "AGP" -#define ASIC_BUS_TYPE_PCIE "PCI_EXPRESS" - -/* Maximum size of that FireGL flag string */ - -#define ATOM_FIREGL_FLAG_STRING "FGL" //Flag used to enable FireGL Support -#define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 3 //sizeof( ATOM_FIREGL_FLAG_STRING ) - -#define ATOM_FAKE_DESKTOP_STRING "DSK" //Flag used to enable mobile ASIC on Desktop -#define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING - -#define ATOM_M54T_FLAG_STRING "M54T" //Flag used to enable M54T Support -#define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING 4 //sizeof( ATOM_M54T_FLAG_STRING ) - -#define HW_ASSISTED_I2C_STATUS_FAILURE 2 -#define HW_ASSISTED_I2C_STATUS_SUCCESS 1 - -#pragma pack(1) /* BIOS data must use byte aligment */ - -/* Define offset to location of ROM header. */ - -#define OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER 0x00000048L -#define OFFSET_TO_ATOM_ROM_IMAGE_SIZE 0x00000002L - -#define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE 0x94 -#define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE 20 /* including the terminator 0x0! */ -#define OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER 0x002f -#define OFFSET_TO_GET_ATOMBIOS_STRINGS_START 0x006e - -/* Common header for all ROM Data tables. - Every table pointed _ATOM_MASTER_DATA_TABLE has this common header. - And the pointer actually points to this header. */ - -typedef struct _ATOM_COMMON_TABLE_HEADER -{ - USHORT usStructureSize; - UCHAR ucTableFormatRevision; /*Change it when the Parser is not backward compatible */ - UCHAR ucTableContentRevision; /*Change it only when the table needs to change but the firmware */ - /*Image can't be updated, while Driver needs to carry the new table! */ -}ATOM_COMMON_TABLE_HEADER; - -typedef struct _ATOM_ROM_HEADER -{ - ATOM_COMMON_TABLE_HEADER sHeader; - UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios, - atombios should init it as "ATOM", don't change the position */ - USHORT usBiosRuntimeSegmentAddress; - USHORT usProtectedModeInfoOffset; - USHORT usConfigFilenameOffset; - USHORT usCRC_BlockOffset; - USHORT usBIOS_BootupMessageOffset; - USHORT usInt10Offset; - USHORT usPciBusDevInitCode; - USHORT usIoBaseAddress; - USHORT usSubsystemVendorID; - USHORT usSubsystemID; - USHORT usPCI_InfoOffset; - USHORT usMasterCommandTableOffset; /*Offset for SW to get all command table offsets, Don't change the position */ - USHORT usMasterDataTableOffset; /*Offset for SW to get all data table offsets, Don't change the position */ - UCHAR ucExtendedFunctionCode; - UCHAR ucReserved; -}ATOM_ROM_HEADER; - -/*==============================Command Table Portion==================================== */ - -#ifdef UEFI_BUILD - #define UTEMP USHORT - #define USHORT void* -#endif - -typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{ - USHORT ASIC_Init; //Function Table, used by various SW components,latest version 1.1 - USHORT GetDisplaySurfaceSize; //Atomic Table, Used by Bios when enabling HW ICON - USHORT ASIC_RegistersInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init - USHORT VRAM_BlockVenderDetection; //Atomic Table, used only by Bios - USHORT DIGxEncoderControl; //Only used by Bios - USHORT MemoryControllerInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init - USHORT EnableCRTCMemReq; //Function Table,directly used by various SW components,latest version 2.1 - USHORT MemoryParamAdjust; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock if needed - USHORT DVOEncoderControl; //Function Table,directly used by various SW components,latest version 1.2 - USHORT GPIOPinControl; //Atomic Table, only used by Bios - USHORT SetEngineClock; //Function Table,directly used by various SW components,latest version 1.1 - USHORT SetMemoryClock; //Function Table,directly used by various SW components,latest version 1.1 - USHORT SetPixelClock; //Function Table,directly used by various SW components,latest version 1.2 - USHORT DynamicClockGating; //Atomic Table, indirectly used by various SW components,called from ASIC_Init - USHORT ResetMemoryDLL; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock - USHORT ResetMemoryDevice; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock - USHORT MemoryPLLInit; - USHORT AdjustDisplayPll; //only used by Bios - USHORT AdjustMemoryController; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock - USHORT EnableASIC_StaticPwrMgt; //Atomic Table, only used by Bios - USHORT ASIC_StaticPwrMgtStatusChange; //Obsolete , only used by Bios - USHORT DAC_LoadDetection; //Atomic Table, directly used by various SW components,latest version 1.2 - USHORT LVTMAEncoderControl; //Atomic Table,directly used by various SW components,latest version 1.3 - USHORT LCD1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT DAC1EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT DAC2EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT DVOOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT CV1OutputControl; //Atomic Table, Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead - USHORT GetConditionalGoldenSetting; //only used by Bios - USHORT TVEncoderControl; //Function Table,directly used by various SW components,latest version 1.1 - USHORT TMDSAEncoderControl; //Atomic Table, directly used by various SW components,latest version 1.3 - USHORT LVDSEncoderControl; //Atomic Table, directly used by various SW components,latest version 1.3 - USHORT TV1OutputControl; //Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead - USHORT EnableScaler; //Atomic Table, used only by Bios - USHORT BlankCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT EnableCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT GetPixelClock; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT EnableVGA_Render; //Function Table,directly used by various SW components,latest version 1.1 - USHORT GetSCLKOverMCLKRatio; //Atomic Table, only used by Bios - USHORT SetCRTC_Timing; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT SetCRTC_OverScan; //Atomic Table, used by various SW components,latest version 1.1 - USHORT SetCRTC_Replication; //Atomic Table, used only by Bios - USHORT SelectCRTC_Source; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT EnableGraphSurfaces; //Atomic Table, used only by Bios - USHORT UpdateCRTC_DoubleBufferRegisters; - USHORT LUT_AutoFill; //Atomic Table, only used by Bios - USHORT EnableHW_IconCursor; //Atomic Table, only used by Bios - USHORT GetMemoryClock; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT GetEngineClock; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT SetCRTC_UsingDTDTiming; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT ExternalEncoderControl; //Atomic Table, directly used by various SW components,latest version 2.1 - USHORT LVTMAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT VRAM_BlockDetectionByStrap; //Atomic Table, used only by Bios - USHORT MemoryCleanUp; //Atomic Table, only used by Bios - USHORT ProcessI2cChannelTransaction; //Function Table,only used by Bios - USHORT WriteOneByteToHWAssistedI2C; //Function Table,indirectly used by various SW components - USHORT ReadHWAssistedI2CStatus; //Atomic Table, indirectly used by various SW components - USHORT SpeedFanControl; //Function Table,indirectly used by various SW components,called from ASIC_Init - USHORT PowerConnectorDetection; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT MC_Synchronization; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock - USHORT ComputeMemoryEnginePLL; //Atomic Table, indirectly used by various SW components,called from SetMemory/EngineClock - USHORT MemoryRefreshConversion; //Atomic Table, indirectly used by various SW components,called from SetMemory or SetEngineClock - USHORT VRAM_GetCurrentInfoBlock; //Atomic Table, used only by Bios - USHORT DynamicMemorySettings; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock - USHORT MemoryTraining; //Atomic Table, used only by Bios - USHORT EnableSpreadSpectrumOnPPLL; //Atomic Table, directly used by various SW components,latest version 1.2 - USHORT TMDSAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT SetVoltage; //Function Table,directly and/or indirectly used by various SW components,latest version 1.1 - USHORT DAC1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT DAC2OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT SetupHWAssistedI2CStatus; //Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C" - USHORT ClockSource; //Atomic Table, indirectly used by various SW components,called from ASIC_Init - USHORT MemoryDeviceInit; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock - USHORT EnableYUV; //Atomic Table, indirectly used by various SW components,called from EnableVGARender - USHORT DIG1EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1 - USHORT DIG2EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1 - USHORT DIG1TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 - USHORT DIG2TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 - USHORT ProcessAuxChannelTransaction; //Function Table,only used by Bios - USHORT DPEncoderService; //Function Table,only used by Bios -}ATOM_MASTER_LIST_OF_COMMAND_TABLES; - -// For backward compatible -#define ReadEDIDFromHWAssistedI2C ProcessI2cChannelTransaction -#define UNIPHYTransmitterControl DIG1TransmitterControl -#define LVTMATransmitterControl DIG2TransmitterControl -#define SetCRTC_DPM_State GetConditionalGoldenSetting -#define SetUniphyInstance ASIC_StaticPwrMgtStatusChange -#define HPDInterruptService ReadHWAssistedI2CStatus -#define EnableVGA_Access GetSCLKOverMCLKRatio - -typedef struct _ATOM_MASTER_COMMAND_TABLE -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables; -}ATOM_MASTER_COMMAND_TABLE; - -/****************************************************************************/ -// Structures used in every command table -/****************************************************************************/ -typedef struct _ATOM_TABLE_ATTRIBUTE -{ -#if ATOM_BIG_ENDIAN - USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag - USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), - USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), -#else - USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), - USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), - USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag -#endif -}ATOM_TABLE_ATTRIBUTE; - -typedef union _ATOM_TABLE_ATTRIBUTE_ACCESS -{ - ATOM_TABLE_ATTRIBUTE sbfAccess; - USHORT susAccess; -}ATOM_TABLE_ATTRIBUTE_ACCESS; - -/****************************************************************************/ -// Common header for all command tables. -// Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header. -// And the pointer actually points to this header. -/****************************************************************************/ -typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER -{ - ATOM_COMMON_TABLE_HEADER CommonHeader; - ATOM_TABLE_ATTRIBUTE TableAttribute; -}ATOM_COMMON_ROM_COMMAND_TABLE_HEADER; - -/****************************************************************************/ -// Structures used by ComputeMemoryEnginePLLTable -/****************************************************************************/ -#define COMPUTE_MEMORY_PLL_PARAM 1 -#define COMPUTE_ENGINE_PLL_PARAM 2 - -typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS -{ - ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div - UCHAR ucAction; //0:reserved //1:Memory //2:Engine - UCHAR ucReserved; //may expand to return larger Fbdiv later - UCHAR ucFbDiv; //return value - UCHAR ucPostDiv; //return value -}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS; - -typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 -{ - ULONG ulClock; //When return, [23:0] return real clock - UCHAR ucAction; //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register - USHORT usFbDiv; //return Feedback value to be written to register - UCHAR ucPostDiv; //return post div to be written to register -}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2; -#define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS - - -#define SET_CLOCK_FREQ_MASK 0x00FFFFFF //Clock change tables only take bit [23:0] as the requested clock value -#define USE_NON_BUS_CLOCK_MASK 0x01000000 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) -#define USE_MEMORY_SELF_REFRESH_MASK 0x02000000 //Only applicable to memory clock change, when set, using memory self refresh during clock transition -#define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04000000 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change -#define FIRST_TIME_CHANGE_CLOCK 0x08000000 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup -#define SKIP_SW_PROGRAM_PLL 0x10000000 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL -#define USE_SS_ENABLED_PIXEL_CLOCK USE_NON_BUS_CLOCK_MASK - -#define b3USE_NON_BUS_CLOCK_MASK 0x01 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) -#define b3USE_MEMORY_SELF_REFRESH 0x02 //Only applicable to memory clock change, when set, using memory self refresh during clock transition -#define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change -#define b3FIRST_TIME_CHANGE_CLOCK 0x08 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup -#define b3SKIP_SW_PROGRAM_PLL 0x10 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL - -typedef struct _ATOM_COMPUTE_CLOCK_FREQ -{ -#if ATOM_BIG_ENDIAN - ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM - ULONG ulClockFreq:24; // in unit of 10kHz -#else - ULONG ulClockFreq:24; // in unit of 10kHz - ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM -#endif -}ATOM_COMPUTE_CLOCK_FREQ; - -typedef struct _ATOM_S_MPLL_FB_DIVIDER -{ - USHORT usFbDivFrac; - USHORT usFbDiv; -}ATOM_S_MPLL_FB_DIVIDER; - -typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 -{ - union - { - ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter - ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter - }; - UCHAR ucRefDiv; //Output Parameter - UCHAR ucPostDiv; //Output Parameter - UCHAR ucCntlFlag; //Output Parameter - UCHAR ucReserved; -}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3; - -// ucCntlFlag -#define ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN 1 -#define ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE 2 -#define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE 4 -#define ATOM_PLL_CNTL_FLAG_SPLL_ISPARE_9 8 - - -// V4 are only used for APU which PLL outside GPU -typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 -{ -#if ATOM_BIG_ENDIAN - ULONG ucPostDiv; //return parameter: post divider which is used to program to register directly - ULONG ulClock:24; //Input= target clock, output = actual clock -#else - ULONG ulClock:24; //Input= target clock, output = actual clock - ULONG ucPostDiv; //return parameter: post divider which is used to program to register directly -#endif -}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4; - -typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER -{ - ATOM_COMPUTE_CLOCK_FREQ ulClock; - ULONG ulReserved[2]; -}DYNAMICE_MEMORY_SETTINGS_PARAMETER; - -typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER -{ - ATOM_COMPUTE_CLOCK_FREQ ulClock; - ULONG ulMemoryClock; - ULONG ulReserved; -}DYNAMICE_ENGINE_SETTINGS_PARAMETER; - -/****************************************************************************/ -// Structures used by SetEngineClockTable -/****************************************************************************/ -typedef struct _SET_ENGINE_CLOCK_PARAMETERS -{ - ULONG ulTargetEngineClock; //In 10Khz unit -}SET_ENGINE_CLOCK_PARAMETERS; - -typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION -{ - ULONG ulTargetEngineClock; //In 10Khz unit - COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; -}SET_ENGINE_CLOCK_PS_ALLOCATION; - -/****************************************************************************/ -// Structures used by SetMemoryClockTable -/****************************************************************************/ -typedef struct _SET_MEMORY_CLOCK_PARAMETERS -{ - ULONG ulTargetMemoryClock; //In 10Khz unit -}SET_MEMORY_CLOCK_PARAMETERS; - -typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION -{ - ULONG ulTargetMemoryClock; //In 10Khz unit - COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; -}SET_MEMORY_CLOCK_PS_ALLOCATION; - -/****************************************************************************/ -// Structures used by ASIC_Init.ctb -/****************************************************************************/ -typedef struct _ASIC_INIT_PARAMETERS -{ - ULONG ulDefaultEngineClock; //In 10Khz unit - ULONG ulDefaultMemoryClock; //In 10Khz unit -}ASIC_INIT_PARAMETERS; - -typedef struct _ASIC_INIT_PS_ALLOCATION -{ - ASIC_INIT_PARAMETERS sASICInitClocks; - SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; //Caller doesn't need to init this structure -}ASIC_INIT_PS_ALLOCATION; - -/****************************************************************************/ -// Structure used by DynamicClockGatingTable.ctb -/****************************************************************************/ -typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS -{ - UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE - UCHAR ucPadding[3]; -}DYNAMIC_CLOCK_GATING_PARAMETERS; -#define DYNAMIC_CLOCK_GATING_PS_ALLOCATION DYNAMIC_CLOCK_GATING_PARAMETERS - -/****************************************************************************/ -// Structure used by EnableASIC_StaticPwrMgtTable.ctb -/****************************************************************************/ -typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS -{ - UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE - UCHAR ucPadding[3]; -}ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS; -#define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS - -/****************************************************************************/ -// Structures used by DAC_LoadDetectionTable.ctb -/****************************************************************************/ -typedef struct _DAC_LOAD_DETECTION_PARAMETERS -{ - USHORT usDeviceID; //{ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT} - UCHAR ucDacType; //{ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC} - UCHAR ucMisc; //Valid only when table revision =1.3 and above -}DAC_LOAD_DETECTION_PARAMETERS; - -// DAC_LOAD_DETECTION_PARAMETERS.ucMisc -#define DAC_LOAD_MISC_YPrPb 0x01 - -typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION -{ - DAC_LOAD_DETECTION_PARAMETERS sDacload; - ULONG Reserved[2];// Don't set this one, allocation for EXT DAC -}DAC_LOAD_DETECTION_PS_ALLOCATION; - -/****************************************************************************/ -// Structures used by DAC1EncoderControlTable.ctb and DAC2EncoderControlTable.ctb -/****************************************************************************/ -typedef struct _DAC_ENCODER_CONTROL_PARAMETERS -{ - USHORT usPixelClock; // in 10KHz; for bios convenient - UCHAR ucDacStandard; // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0) - UCHAR ucAction; // 0: turn off encoder - // 1: setup and turn on encoder - // 7: ATOM_ENCODER_INIT Initialize DAC -}DAC_ENCODER_CONTROL_PARAMETERS; - -#define DAC_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PARAMETERS - -/****************************************************************************/ -// Structures used by DIG1EncoderControlTable -// DIG2EncoderControlTable -// ExternalEncoderControlTable -/****************************************************************************/ -typedef struct _DIG_ENCODER_CONTROL_PARAMETERS -{ - USHORT usPixelClock; // in 10KHz; for bios convenient - UCHAR ucConfig; - // [2] Link Select: - // =0: PHY linkA if bfLane<3 - // =1: PHY linkB if bfLanes<3 - // =0: PHY linkA+B if bfLanes=3 - // [3] Transmitter Sel - // =0: UNIPHY or PCIEPHY - // =1: LVTMA - UCHAR ucAction; // =0: turn off encoder - // =1: turn on encoder - UCHAR ucEncoderMode; - // =0: DP encoder - // =1: LVDS encoder - // =2: DVI encoder - // =3: HDMI encoder - // =4: SDVO encoder - UCHAR ucLaneNum; // how many lanes to enable - UCHAR ucReserved[2]; -}DIG_ENCODER_CONTROL_PARAMETERS; -#define DIG_ENCODER_CONTROL_PS_ALLOCATION DIG_ENCODER_CONTROL_PARAMETERS -#define EXTERNAL_ENCODER_CONTROL_PARAMETER DIG_ENCODER_CONTROL_PARAMETERS - -//ucConfig -#define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK 0x01 -#define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ 0x00 -#define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ 0x01 -#define ATOM_ENCODER_CONFIG_LINK_SEL_MASK 0x04 -#define ATOM_ENCODER_CONFIG_LINKA 0x00 -#define ATOM_ENCODER_CONFIG_LINKB 0x04 -#define ATOM_ENCODER_CONFIG_LINKA_B ATOM_TRANSMITTER_CONFIG_LINKA -#define ATOM_ENCODER_CONFIG_LINKB_A ATOM_ENCODER_CONFIG_LINKB -#define ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK 0x08 -#define ATOM_ENCODER_CONFIG_UNIPHY 0x00 -#define ATOM_ENCODER_CONFIG_LVTMA 0x08 -#define ATOM_ENCODER_CONFIG_TRANSMITTER1 0x00 -#define ATOM_ENCODER_CONFIG_TRANSMITTER2 0x08 -#define ATOM_ENCODER_CONFIG_DIGB 0x80 // VBIOS Internal use, outside SW should set this bit=0 -// ucAction -// ATOM_ENABLE: Enable Encoder -// ATOM_DISABLE: Disable Encoder - -//ucEncoderMode -#define ATOM_ENCODER_MODE_DP 0 -#define ATOM_ENCODER_MODE_LVDS 1 -#define ATOM_ENCODER_MODE_DVI 2 -#define ATOM_ENCODER_MODE_HDMI 3 -#define ATOM_ENCODER_MODE_SDVO 4 -#define ATOM_ENCODER_MODE_DP_AUDIO 5 -#define ATOM_ENCODER_MODE_TV 13 -#define ATOM_ENCODER_MODE_CV 14 -#define ATOM_ENCODER_MODE_CRT 15 - -typedef struct _ATOM_DIG_ENCODER_CONFIG_V2 -{ -#if ATOM_BIG_ENDIAN - UCHAR ucReserved1:2; - UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF - UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F - UCHAR ucReserved:1; - UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz -#else - UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz - UCHAR ucReserved:1; - UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F - UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF - UCHAR ucReserved1:2; -#endif -}ATOM_DIG_ENCODER_CONFIG_V2; - - -typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2 -{ - USHORT usPixelClock; // in 10KHz; for bios convenient - ATOM_DIG_ENCODER_CONFIG_V2 acConfig; - UCHAR ucAction; - UCHAR ucEncoderMode; - // =0: DP encoder - // =1: LVDS encoder - // =2: DVI encoder - // =3: HDMI encoder - // =4: SDVO encoder - UCHAR ucLaneNum; // how many lanes to enable - UCHAR ucStatus; // = DP_LINK_TRAINING_COMPLETE or DP_LINK_TRAINING_INCOMPLETE, only used by VBIOS with command ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS - UCHAR ucReserved; -}DIG_ENCODER_CONTROL_PARAMETERS_V2; - -//ucConfig -#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_MASK 0x01 -#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_1_62GHZ 0x00 -#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_2_70GHZ 0x01 -#define ATOM_ENCODER_CONFIG_V2_LINK_SEL_MASK 0x04 -#define ATOM_ENCODER_CONFIG_V2_LINKA 0x00 -#define ATOM_ENCODER_CONFIG_V2_LINKB 0x04 -#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER_SEL_MASK 0x18 -#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER1 0x00 -#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER2 0x08 -#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER3 0x10 - -// ucAction: -// ATOM_DISABLE -// ATOM_ENABLE -#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_START 0x08 -#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 0x09 -#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 0x0a -#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE 0x0b -#define ATOM_ENCODER_CMD_DP_VIDEO_OFF 0x0c -#define ATOM_ENCODER_CMD_DP_VIDEO_ON 0x0d -#define ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS 0x0e -#define ATOM_ENCODER_CMD_SETUP 0x0f - -// ucStatus -#define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE 0x10 -#define ATOM_ENCODER_STATUS_LINK_TRAINING_INCOMPLETE 0x00 - -// Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver -typedef struct _ATOM_DIG_ENCODER_CONFIG_V3 -{ -#if ATOM_BIG_ENDIAN - UCHAR ucReserved1:1; - UCHAR ucDigSel:3; // =0: DIGA/B/C/D/E/F - UCHAR ucReserved:3; - UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz -#else - UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz - UCHAR ucReserved:3; - UCHAR ucDigSel:3; // =0: DIGA/B/C/D/E/F - UCHAR ucReserved1:1; -#endif -}ATOM_DIG_ENCODER_CONFIG_V3; - -#define ATOM_ENCODER_CONFIG_V3_ENCODER_SEL 0x70 - - -typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3 -{ - USHORT usPixelClock; // in 10KHz; for bios convenient - ATOM_DIG_ENCODER_CONFIG_V3 acConfig; - UCHAR ucAction; - UCHAR ucEncoderMode; - // =0: DP encoder - // =1: LVDS encoder - // =2: DVI encoder - // =3: HDMI encoder - // =4: SDVO encoder - // =5: DP audio - UCHAR ucLaneNum; // how many lanes to enable - UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP - UCHAR ucReserved; -}DIG_ENCODER_CONTROL_PARAMETERS_V3; - - -// define ucBitPerColor: -#define PANEL_BPC_UNDEFINE 0x00 -#define PANEL_6BIT_PER_COLOR 0x01 -#define PANEL_8BIT_PER_COLOR 0x02 -#define PANEL_10BIT_PER_COLOR 0x03 -#define PANEL_12BIT_PER_COLOR 0x04 -#define PANEL_16BIT_PER_COLOR 0x05 - -/****************************************************************************/ -// Structures used by UNIPHYTransmitterControlTable -// LVTMATransmitterControlTable -// DVOOutputControlTable -/****************************************************************************/ -typedef struct _ATOM_DP_VS_MODE -{ - UCHAR ucLaneSel; - UCHAR ucLaneSet; -}ATOM_DP_VS_MODE; - -typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS -{ - union - { - USHORT usPixelClock; // in 10KHz; for bios convenient - USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h - ATOM_DP_VS_MODE asMode; // DP Voltage swing mode - }; - UCHAR ucConfig; - // [0]=0: 4 lane Link, - // =1: 8 lane Link ( Dual Links TMDS ) - // [1]=0: InCoherent mode - // =1: Coherent Mode - // [2] Link Select: - // =0: PHY linkA if bfLane<3 - // =1: PHY linkB if bfLanes<3 - // =0: PHY linkA+B if bfLanes=3 - // [5:4]PCIE lane Sel - // =0: lane 0~3 or 0~7 - // =1: lane 4~7 - // =2: lane 8~11 or 8~15 - // =3: lane 12~15 - UCHAR ucAction; // =0: turn off encoder - // =1: turn on encoder - UCHAR ucReserved[4]; -}DIG_TRANSMITTER_CONTROL_PARAMETERS; - -#define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PARAMETERS - -//ucInitInfo -#define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK 0x00ff - -//ucConfig -#define ATOM_TRANSMITTER_CONFIG_8LANE_LINK 0x01 -#define ATOM_TRANSMITTER_CONFIG_COHERENT 0x02 -#define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK 0x04 -#define ATOM_TRANSMITTER_CONFIG_LINKA 0x00 -#define ATOM_TRANSMITTER_CONFIG_LINKB 0x04 -#define ATOM_TRANSMITTER_CONFIG_LINKA_B 0x00 -#define ATOM_TRANSMITTER_CONFIG_LINKB_A 0x04 - -#define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE -#define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER 0x00 // only used when ATOM_TRANSMITTER_ACTION_ENABLE -#define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE - -#define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK 0x30 -#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL 0x00 -#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE 0x20 -#define ATOM_TRANSMITTER_CONFIG_CLKSRC_XTALIN 0x30 -#define ATOM_TRANSMITTER_CONFIG_LANE_SEL_MASK 0xc0 -#define ATOM_TRANSMITTER_CONFIG_LANE_0_3 0x00 -#define ATOM_TRANSMITTER_CONFIG_LANE_0_7 0x00 -#define ATOM_TRANSMITTER_CONFIG_LANE_4_7 0x40 -#define ATOM_TRANSMITTER_CONFIG_LANE_8_11 0x80 -#define ATOM_TRANSMITTER_CONFIG_LANE_8_15 0x80 -#define ATOM_TRANSMITTER_CONFIG_LANE_12_15 0xc0 - -//ucAction -#define ATOM_TRANSMITTER_ACTION_DISABLE 0 -#define ATOM_TRANSMITTER_ACTION_ENABLE 1 -#define ATOM_TRANSMITTER_ACTION_LCD_BLOFF 2 -#define ATOM_TRANSMITTER_ACTION_LCD_BLON 3 -#define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL 4 -#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START 5 -#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP 6 -#define ATOM_TRANSMITTER_ACTION_INIT 7 -#define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT 8 -#define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT 9 -#define ATOM_TRANSMITTER_ACTION_SETUP 10 -#define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH 11 -#define ATOM_TRANSMITTER_ACTION_POWER_ON 12 -#define ATOM_TRANSMITTER_ACTION_POWER_OFF 13 - -// Following are used for DigTransmitterControlTable ver1.2 -typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V2 -{ -#if ATOM_BIG_ENDIAN - UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) - // =1 Dig Transmitter 2 ( Uniphy CD ) - // =2 Dig Transmitter 3 ( Uniphy EF ) - UCHAR ucReserved:1; - UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector - UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) - UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E - // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F - - UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) - UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector -#else - UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector - UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) - UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E - // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F - UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) - UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector - UCHAR ucReserved:1; - UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) - // =1 Dig Transmitter 2 ( Uniphy CD ) - // =2 Dig Transmitter 3 ( Uniphy EF ) -#endif -}ATOM_DIG_TRANSMITTER_CONFIG_V2; - -//ucConfig -//Bit0 -#define ATOM_TRANSMITTER_CONFIG_V2_DUAL_LINK_CONNECTOR 0x01 - -//Bit1 -#define ATOM_TRANSMITTER_CONFIG_V2_COHERENT 0x02 - -//Bit2 -#define ATOM_TRANSMITTER_CONFIG_V2_LINK_SEL_MASK 0x04 -#define ATOM_TRANSMITTER_CONFIG_V2_LINKA 0x00 -#define ATOM_TRANSMITTER_CONFIG_V2_LINKB 0x04 - -// Bit3 -#define ATOM_TRANSMITTER_CONFIG_V2_ENCODER_SEL_MASK 0x08 -#define ATOM_TRANSMITTER_CONFIG_V2_DIG1_ENCODER 0x00 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP -#define ATOM_TRANSMITTER_CONFIG_V2_DIG2_ENCODER 0x08 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP - -// Bit4 -#define ATOM_TRASMITTER_CONFIG_V2_DP_CONNECTOR 0x10 - -// Bit7:6 -#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER_SEL_MASK 0xC0 -#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER1 0x00 //AB -#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER2 0x40 //CD -#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER3 0x80 //EF - -typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 -{ - union - { - USHORT usPixelClock; // in 10KHz; for bios convenient - USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h - ATOM_DP_VS_MODE asMode; // DP Voltage swing mode - }; - ATOM_DIG_TRANSMITTER_CONFIG_V2 acConfig; - UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX - UCHAR ucReserved[4]; -}DIG_TRANSMITTER_CONTROL_PARAMETERS_V2; - -typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V3 -{ -#if ATOM_BIG_ENDIAN - UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) - // =1 Dig Transmitter 2 ( Uniphy CD ) - // =2 Dig Transmitter 3 ( Uniphy EF ) - UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2 - UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F - UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E - // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F - UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) - UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector -#else - UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector - UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) - UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E - // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F - UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F - UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2 - UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) - // =1 Dig Transmitter 2 ( Uniphy CD ) - // =2 Dig Transmitter 3 ( Uniphy EF ) -#endif -}ATOM_DIG_TRANSMITTER_CONFIG_V3; - -typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 -{ - union - { - USHORT usPixelClock; // in 10KHz; for bios convenient - USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h - ATOM_DP_VS_MODE asMode; // DP Voltage swing mode - }; - ATOM_DIG_TRANSMITTER_CONFIG_V3 acConfig; - UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX - UCHAR ucLaneNum; - UCHAR ucReserved[3]; -}DIG_TRANSMITTER_CONTROL_PARAMETERS_V3; - -//ucConfig -//Bit0 -#define ATOM_TRANSMITTER_CONFIG_V3_DUAL_LINK_CONNECTOR 0x01 - -//Bit1 -#define ATOM_TRANSMITTER_CONFIG_V3_COHERENT 0x02 - -//Bit2 -#define ATOM_TRANSMITTER_CONFIG_V3_LINK_SEL_MASK 0x04 -#define ATOM_TRANSMITTER_CONFIG_V3_LINKA 0x00 -#define ATOM_TRANSMITTER_CONFIG_V3_LINKB 0x04 - -// Bit3 -#define ATOM_TRANSMITTER_CONFIG_V3_ENCODER_SEL_MASK 0x08 -#define ATOM_TRANSMITTER_CONFIG_V3_DIG1_ENCODER 0x00 -#define ATOM_TRANSMITTER_CONFIG_V3_DIG2_ENCODER 0x08 - -// Bit5:4 -#define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SEL_MASK 0x30 -#define ATOM_TRASMITTER_CONFIG_V3_P1PLL 0x00 -#define ATOM_TRASMITTER_CONFIG_V3_P2PLL 0x10 -#define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SRC_EXT 0x20 - -// Bit7:6 -#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER_SEL_MASK 0xC0 -#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER1 0x00 //AB -#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER2 0x40 //CD -#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER3 0x80 //EF - -/****************************************************************************/ -// Structures used by DAC1OuputControlTable -// DAC2OuputControlTable -// LVTMAOutputControlTable (Before DEC30) -// TMDSAOutputControlTable (Before DEC30) -/****************************************************************************/ -typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS -{ - UCHAR ucAction; // Possible input:ATOM_ENABLE||ATOMDISABLE - // When the display is LCD, in addition to above: - // ATOM_LCD_BLOFF|| ATOM_LCD_BLON ||ATOM_LCD_BL_BRIGHTNESS_CONTROL||ATOM_LCD_SELFTEST_START|| - // ATOM_LCD_SELFTEST_STOP - - UCHAR aucPadding[3]; // padding to DWORD aligned -}DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS; - -#define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS - - -#define CRT1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS -#define CRT1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION - -#define CRT2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS -#define CRT2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION - -#define CV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS -#define CV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION - -#define TV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS -#define TV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION - -#define DFP1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS -#define DFP1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION - -#define DFP2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS -#define DFP2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION - -#define LCD1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS -#define LCD1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION - -#define DVO_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS -#define DVO_OUTPUT_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PS_ALLOCATION -#define DVO_OUTPUT_CONTROL_PARAMETERS_V3 DIG_TRANSMITTER_CONTROL_PARAMETERS - -/****************************************************************************/ -// Structures used by BlankCRTCTable -/****************************************************************************/ -typedef struct _BLANK_CRTC_PARAMETERS -{ - UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 - UCHAR ucBlanking; // ATOM_BLANKING or ATOM_BLANKINGOFF - USHORT usBlackColorRCr; - USHORT usBlackColorGY; - USHORT usBlackColorBCb; -}BLANK_CRTC_PARAMETERS; -#define BLANK_CRTC_PS_ALLOCATION BLANK_CRTC_PARAMETERS - -/****************************************************************************/ -// Structures used by EnableCRTCTable -// EnableCRTCMemReqTable -// UpdateCRTC_DoubleBufferRegistersTable -/****************************************************************************/ -typedef struct _ENABLE_CRTC_PARAMETERS -{ - UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 - UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE - UCHAR ucPadding[2]; -}ENABLE_CRTC_PARAMETERS; -#define ENABLE_CRTC_PS_ALLOCATION ENABLE_CRTC_PARAMETERS - -/****************************************************************************/ -// Structures used by SetCRTC_OverScanTable -/****************************************************************************/ -typedef struct _SET_CRTC_OVERSCAN_PARAMETERS -{ - USHORT usOverscanRight; // right - USHORT usOverscanLeft; // left - USHORT usOverscanBottom; // bottom - USHORT usOverscanTop; // top - UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 - UCHAR ucPadding[3]; -}SET_CRTC_OVERSCAN_PARAMETERS; -#define SET_CRTC_OVERSCAN_PS_ALLOCATION SET_CRTC_OVERSCAN_PARAMETERS - -/****************************************************************************/ -// Structures used by SetCRTC_ReplicationTable -/****************************************************************************/ -typedef struct _SET_CRTC_REPLICATION_PARAMETERS -{ - UCHAR ucH_Replication; // horizontal replication - UCHAR ucV_Replication; // vertical replication - UCHAR usCRTC; // ATOM_CRTC1 or ATOM_CRTC2 - UCHAR ucPadding; -}SET_CRTC_REPLICATION_PARAMETERS; -#define SET_CRTC_REPLICATION_PS_ALLOCATION SET_CRTC_REPLICATION_PARAMETERS - -/****************************************************************************/ -// Structures used by SelectCRTC_SourceTable -/****************************************************************************/ -typedef struct _SELECT_CRTC_SOURCE_PARAMETERS -{ - UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 - UCHAR ucDevice; // ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|.... - UCHAR ucPadding[2]; -}SELECT_CRTC_SOURCE_PARAMETERS; -#define SELECT_CRTC_SOURCE_PS_ALLOCATION SELECT_CRTC_SOURCE_PARAMETERS - -typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2 -{ - UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 - UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO - UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO - UCHAR ucPadding; -}SELECT_CRTC_SOURCE_PARAMETERS_V2; - -//ucEncoderID -//#define ASIC_INT_DAC1_ENCODER_ID 0x00 -//#define ASIC_INT_TV_ENCODER_ID 0x02 -//#define ASIC_INT_DIG1_ENCODER_ID 0x03 -//#define ASIC_INT_DAC2_ENCODER_ID 0x04 -//#define ASIC_EXT_TV_ENCODER_ID 0x06 -//#define ASIC_INT_DVO_ENCODER_ID 0x07 -//#define ASIC_INT_DIG2_ENCODER_ID 0x09 -//#define ASIC_EXT_DIG_ENCODER_ID 0x05 - -//ucEncodeMode -//#define ATOM_ENCODER_MODE_DP 0 -//#define ATOM_ENCODER_MODE_LVDS 1 -//#define ATOM_ENCODER_MODE_DVI 2 -//#define ATOM_ENCODER_MODE_HDMI 3 -//#define ATOM_ENCODER_MODE_SDVO 4 -//#define ATOM_ENCODER_MODE_TV 13 -//#define ATOM_ENCODER_MODE_CV 14 -//#define ATOM_ENCODER_MODE_CRT 15 - -/****************************************************************************/ -// Structures used by SetPixelClockTable -// GetPixelClockTable -/****************************************************************************/ -//Major revision=1., Minor revision=1 -typedef struct _PIXEL_CLOCK_PARAMETERS -{ - USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) - // 0 means disable PPLL - USHORT usRefDiv; // Reference divider - USHORT usFbDiv; // feedback divider - UCHAR ucPostDiv; // post divider - UCHAR ucFracFbDiv; // fractional feedback divider - UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 - UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER - UCHAR ucCRTC; // Which CRTC uses this Ppll - UCHAR ucPadding; -}PIXEL_CLOCK_PARAMETERS; - -//Major revision=1., Minor revision=2, add ucMiscIfno -//ucMiscInfo: -#define MISC_FORCE_REPROG_PIXEL_CLOCK 0x1 -#define MISC_DEVICE_INDEX_MASK 0xF0 -#define MISC_DEVICE_INDEX_SHIFT 4 - -typedef struct _PIXEL_CLOCK_PARAMETERS_V2 -{ - USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) - // 0 means disable PPLL - USHORT usRefDiv; // Reference divider - USHORT usFbDiv; // feedback divider - UCHAR ucPostDiv; // post divider - UCHAR ucFracFbDiv; // fractional feedback divider - UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 - UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER - UCHAR ucCRTC; // Which CRTC uses this Ppll - UCHAR ucMiscInfo; // Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog -}PIXEL_CLOCK_PARAMETERS_V2; - -//Major revision=1., Minor revision=3, structure/definition change -//ucEncoderMode: -//ATOM_ENCODER_MODE_DP -//ATOM_ENOCDER_MODE_LVDS -//ATOM_ENOCDER_MODE_DVI -//ATOM_ENOCDER_MODE_HDMI -//ATOM_ENOCDER_MODE_SDVO -//ATOM_ENCODER_MODE_TV 13 -//ATOM_ENCODER_MODE_CV 14 -//ATOM_ENCODER_MODE_CRT 15 - -//ucDVOConfig -//#define DVO_ENCODER_CONFIG_RATE_SEL 0x01 -//#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00 -//#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01 -//#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c -//#define DVO_ENCODER_CONFIG_LOW12BIT 0x00 -//#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04 -//#define DVO_ENCODER_CONFIG_24BIT 0x08 - -//ucMiscInfo: also changed, see below -#define PIXEL_CLOCK_MISC_FORCE_PROG_PPLL 0x01 -#define PIXEL_CLOCK_MISC_VGA_MODE 0x02 -#define PIXEL_CLOCK_MISC_CRTC_SEL_MASK 0x04 -#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1 0x00 -#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2 0x04 -#define PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK 0x08 -#define PIXEL_CLOCK_MISC_REF_DIV_SRC 0x10 -// V1.4 for RoadRunner -#define PIXEL_CLOCK_V4_MISC_SS_ENABLE 0x10 -#define PIXEL_CLOCK_V4_MISC_COHERENT_MODE 0x20 - -typedef struct _PIXEL_CLOCK_PARAMETERS_V3 -{ - USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) - // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0. - USHORT usRefDiv; // Reference divider - USHORT usFbDiv; // feedback divider - UCHAR ucPostDiv; // post divider - UCHAR ucFracFbDiv; // fractional feedback divider - UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 - UCHAR ucTransmitterId; // graphic encoder id defined in objectId.h - union - { - UCHAR ucEncoderMode; // encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/ - UCHAR ucDVOConfig; // when use DVO, need to know SDR/DDR, 12bit or 24bit - }; - UCHAR ucMiscInfo; // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel - // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source - // bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the source of reference divider -}PIXEL_CLOCK_PARAMETERS_V3; - -#define PIXEL_CLOCK_PARAMETERS_LAST PIXEL_CLOCK_PARAMETERS_V2 -#define GET_PIXEL_CLOCK_PS_ALLOCATION PIXEL_CLOCK_PARAMETERS_LAST - -typedef struct _PIXEL_CLOCK_PARAMETERS_V5 -{ - UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to - // drive the pixel clock. not used for DCPLL case. - union{ - UCHAR ucReserved; - UCHAR ucFracFbDiv; // [gphan] temporary to prevent build problem. remove it after driver code is changed. - }; - USHORT usPixelClock; // target the pixel clock to drive the CRTC timing - // 0 means disable PPLL/DCPLL. - USHORT usFbDiv; // feedback divider integer part. - UCHAR ucPostDiv; // post divider. - UCHAR ucRefDiv; // Reference divider - UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL - UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, - // indicate which graphic encoder will be used. - UCHAR ucEncoderMode; // Encoder mode: - UCHAR ucMiscInfo; // bit[0]= Force program PPLL - // bit[1]= when VGA timing is used. - // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp - // bit[4]= RefClock source for PPLL. - // =0: XTLAIN( default mode ) - // =1: other external clock source, which is pre-defined - // by VBIOS depend on the feature required. - // bit[7:5]: reserved. - ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 ) - -}PIXEL_CLOCK_PARAMETERS_V5; - -#define PIXEL_CLOCK_V5_MISC_FORCE_PROG_PPLL 0x01 -#define PIXEL_CLOCK_V5_MISC_VGA_MODE 0x02 -#define PIXEL_CLOCK_V5_MISC_HDMI_BPP_MASK 0x0c -#define PIXEL_CLOCK_V5_MISC_HDMI_24BPP 0x00 -#define PIXEL_CLOCK_V5_MISC_HDMI_30BPP 0x04 -#define PIXEL_CLOCK_V5_MISC_HDMI_32BPP 0x08 -#define PIXEL_CLOCK_V5_MISC_REF_DIV_SRC 0x10 - -typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2 -{ - PIXEL_CLOCK_PARAMETERS_V3 sDispClkInput; -}GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2; - -typedef struct _GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2 -{ - UCHAR ucStatus; - UCHAR ucRefDivSrc; // =1: reference clock source from XTALIN, =0: source from PCIE ref clock - UCHAR ucReserved[2]; -}GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2; - -typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3 -{ - PIXEL_CLOCK_PARAMETERS_V5 sDispClkInput; -}GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3; - -/****************************************************************************/ -// Structures used by AdjustDisplayPllTable -/****************************************************************************/ -typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS -{ - USHORT usPixelClock; - UCHAR ucTransmitterID; - UCHAR ucEncodeMode; - union - { - UCHAR ucDVOConfig; //if DVO, need passing link rate and output 12bitlow or 24bit - UCHAR ucConfig; //if none DVO, not defined yet - }; - UCHAR ucReserved[3]; -}ADJUST_DISPLAY_PLL_PARAMETERS; - -#define ADJUST_DISPLAY_CONFIG_SS_ENABLE 0x10 -#define ADJUST_DISPLAY_PLL_PS_ALLOCATION ADJUST_DISPLAY_PLL_PARAMETERS - -typedef struct _ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 -{ - USHORT usPixelClock; // target pixel clock - UCHAR ucTransmitterID; // transmitter id defined in objectid.h - UCHAR ucEncodeMode; // encoder mode: CRT, LVDS, DP, TMDS or HDMI - UCHAR ucDispPllConfig; // display pll configure parameter defined as following DISPPLL_CONFIG_XXXX - UCHAR ucReserved[3]; -}ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3; - -// usDispPllConfig v1.2 for RoadRunner -#define DISPPLL_CONFIG_DVO_RATE_SEL 0x0001 // need only when ucTransmitterID = DVO -#define DISPPLL_CONFIG_DVO_DDR_SPEED 0x0000 // need only when ucTransmitterID = DVO -#define DISPPLL_CONFIG_DVO_SDR_SPEED 0x0001 // need only when ucTransmitterID = DVO -#define DISPPLL_CONFIG_DVO_OUTPUT_SEL 0x000c // need only when ucTransmitterID = DVO -#define DISPPLL_CONFIG_DVO_LOW12BIT 0x0000 // need only when ucTransmitterID = DVO -#define DISPPLL_CONFIG_DVO_UPPER12BIT 0x0004 // need only when ucTransmitterID = DVO -#define DISPPLL_CONFIG_DVO_24BIT 0x0008 // need only when ucTransmitterID = DVO -#define DISPPLL_CONFIG_SS_ENABLE 0x0010 // Only used when ucEncoderMode = DP or LVDS -#define DISPPLL_CONFIG_COHERENT_MODE 0x0020 // Only used when ucEncoderMode = TMDS or HDMI -#define DISPPLL_CONFIG_DUAL_LINK 0x0040 // Only used when ucEncoderMode = TMDS or LVDS - - -typedef struct _ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 -{ - ULONG ulDispPllFreq; // return display PPLL freq which is used to generate the pixclock, and related idclk, symclk etc - UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider and post_div ( if it is not given ) - UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider - UCHAR ucReserved[2]; -}ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3; - -typedef struct _ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 -{ - union - { - ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 sInput; - ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 sOutput; - }; -} ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3; - -/****************************************************************************/ -// Structures used by EnableYUVTable -/****************************************************************************/ -typedef struct _ENABLE_YUV_PARAMETERS -{ - UCHAR ucEnable; // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB) - UCHAR ucCRTC; // Which CRTC needs this YUV or RGB format - UCHAR ucPadding[2]; -}ENABLE_YUV_PARAMETERS; -#define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS - -/****************************************************************************/ -// Structures used by GetMemoryClockTable -/****************************************************************************/ -typedef struct _GET_MEMORY_CLOCK_PARAMETERS -{ - ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit -} GET_MEMORY_CLOCK_PARAMETERS; -#define GET_MEMORY_CLOCK_PS_ALLOCATION GET_MEMORY_CLOCK_PARAMETERS - -/****************************************************************************/ -// Structures used by GetEngineClockTable -/****************************************************************************/ -typedef struct _GET_ENGINE_CLOCK_PARAMETERS -{ - ULONG ulReturnEngineClock; // current engine speed in 10KHz unit -} GET_ENGINE_CLOCK_PARAMETERS; -#define GET_ENGINE_CLOCK_PS_ALLOCATION GET_ENGINE_CLOCK_PARAMETERS - -/****************************************************************************/ -// Following Structures and constant may be obsolete -/****************************************************************************/ -//Maxium 8 bytes,the data read in will be placed in the parameter space. -//Read operaion successeful when the paramter space is non-zero, otherwise read operation failed -typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS -{ - USHORT usPrescale; //Ratio between Engine clock and I2C clock - USHORT usVRAMAddress; //Adress in Frame Buffer where to pace raw EDID - USHORT usStatus; //When use output: lower byte EDID checksum, high byte hardware status - //WHen use input: lower byte as 'byte to read':currently limited to 128byte or 1byte - UCHAR ucSlaveAddr; //Read from which slave - UCHAR ucLineNumber; //Read from which HW assisted line -}READ_EDID_FROM_HW_I2C_DATA_PARAMETERS; -#define READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION READ_EDID_FROM_HW_I2C_DATA_PARAMETERS - - -#define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSDATABYTE 0 -#define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES 1 -#define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK 2 -#define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_IDOFFSET_PLUS_IDDATABLOCK 3 -#define ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK 4 - -typedef struct _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS -{ - USHORT usPrescale; //Ratio between Engine clock and I2C clock - USHORT usByteOffset; //Write to which byte - //Upper portion of usByteOffset is Format of data - //1bytePS+offsetPS - //2bytesPS+offsetPS - //blockID+offsetPS - //blockID+offsetID - //blockID+counterID+offsetID - UCHAR ucData; //PS data1 - UCHAR ucStatus; //Status byte 1=success, 2=failure, Also is used as PS data2 - UCHAR ucSlaveAddr; //Write to which slave - UCHAR ucLineNumber; //Write from which HW assisted line -}WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS; - -#define WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS - -typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS -{ - USHORT usPrescale; //Ratio between Engine clock and I2C clock - UCHAR ucSlaveAddr; //Write to which slave - UCHAR ucLineNumber; //Write from which HW assisted line -}SET_UP_HW_I2C_DATA_PARAMETERS; - - -/**************************************************************************/ -#define SPEED_FAN_CONTROL_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS - -/****************************************************************************/ -// Structures used by PowerConnectorDetectionTable -/****************************************************************************/ -typedef struct _POWER_CONNECTOR_DETECTION_PARAMETERS -{ - UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected - UCHAR ucPwrBehaviorId; - USHORT usPwrBudget; //how much power currently boot to in unit of watt -}POWER_CONNECTOR_DETECTION_PARAMETERS; - -typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION -{ - UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected - UCHAR ucReserved; - USHORT usPwrBudget; //how much power currently boot to in unit of watt - WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; -}POWER_CONNECTOR_DETECTION_PS_ALLOCATION; - -/****************************LVDS SS Command Table Definitions**********************/ - -/****************************************************************************/ -// Structures used by EnableSpreadSpectrumOnPPLLTable -/****************************************************************************/ -typedef struct _ENABLE_LVDS_SS_PARAMETERS -{ - USHORT usSpreadSpectrumPercentage; - UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD - UCHAR ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY - UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE - UCHAR ucPadding[3]; -}ENABLE_LVDS_SS_PARAMETERS; - -//ucTableFormatRevision=1,ucTableContentRevision=2 -typedef struct _ENABLE_LVDS_SS_PARAMETERS_V2 -{ - USHORT usSpreadSpectrumPercentage; - UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD - UCHAR ucSpreadSpectrumStep; // - UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE - UCHAR ucSpreadSpectrumDelay; - UCHAR ucSpreadSpectrumRange; - UCHAR ucPadding; -}ENABLE_LVDS_SS_PARAMETERS_V2; - -//This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS. -typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL -{ - USHORT usSpreadSpectrumPercentage; - UCHAR ucSpreadSpectrumType; // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD - UCHAR ucSpreadSpectrumStep; // - UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE - UCHAR ucSpreadSpectrumDelay; - UCHAR ucSpreadSpectrumRange; - UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2 -}ENABLE_SPREAD_SPECTRUM_ON_PPLL; - -typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 -{ - USHORT usSpreadSpectrumPercentage; - UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread. - // Bit[1]: 1-Ext. 0-Int. - // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL - // Bits[7:4] reserved - UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE - USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8] - USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC -}ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2; - -#define ATOM_PPLL_SS_TYPE_V2_DOWN_SPREAD 0x00 -#define ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD 0x01 -#define ATOM_PPLL_SS_TYPE_V2_EXT_SPREAD 0x02 -#define ATOM_PPLL_SS_TYPE_V2_PPLL_SEL_MASK 0x0c -#define ATOM_PPLL_SS_TYPE_V2_P1PLL 0x00 -#define ATOM_PPLL_SS_TYPE_V2_P2PLL 0x04 -#define ATOM_PPLL_SS_TYPE_V2_DCPLL 0x08 -#define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK 0x00FF -#define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_SHIFT 0 -#define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK 0x0F00 -#define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT 8 - -#define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION ENABLE_SPREAD_SPECTRUM_ON_PPLL - -/**************************************************************************/ - -typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION -{ - PIXEL_CLOCK_PARAMETERS sPCLKInput; - ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;//Caller doesn't need to init this portion -}SET_PIXEL_CLOCK_PS_ALLOCATION; - -#define ENABLE_VGA_RENDER_PS_ALLOCATION SET_PIXEL_CLOCK_PS_ALLOCATION - -/****************************************************************************/ -// Structures used by ### -/****************************************************************************/ -typedef struct _MEMORY_TRAINING_PARAMETERS -{ - ULONG ulTargetMemoryClock; //In 10Khz unit -}MEMORY_TRAINING_PARAMETERS; -#define MEMORY_TRAINING_PS_ALLOCATION MEMORY_TRAINING_PARAMETERS - - -/****************************LVDS and other encoder command table definitions **********************/ - - -/****************************************************************************/ -// Structures used by LVDSEncoderControlTable (Before DCE30) -// LVTMAEncoderControlTable (Before DCE30) -// TMDSAEncoderControlTable (Before DCE30) -/****************************************************************************/ -typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS -{ - USHORT usPixelClock; // in 10KHz; for bios convenient - UCHAR ucMisc; // bit0=0: Enable single link - // =1: Enable dual link - // Bit1=0: 666RGB - // =1: 888RGB - UCHAR ucAction; // 0: turn off encoder - // 1: setup and turn on encoder -}LVDS_ENCODER_CONTROL_PARAMETERS; - -#define LVDS_ENCODER_CONTROL_PS_ALLOCATION LVDS_ENCODER_CONTROL_PARAMETERS - -#define TMDS1_ENCODER_CONTROL_PARAMETERS LVDS_ENCODER_CONTROL_PARAMETERS -#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION TMDS1_ENCODER_CONTROL_PARAMETERS - -#define TMDS2_ENCODER_CONTROL_PARAMETERS TMDS1_ENCODER_CONTROL_PARAMETERS -#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION TMDS2_ENCODER_CONTROL_PARAMETERS - - -//ucTableFormatRevision=1,ucTableContentRevision=2 -typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2 -{ - USHORT usPixelClock; // in 10KHz; for bios convenient - UCHAR ucMisc; // see PANEL_ENCODER_MISC_xx defintions below - UCHAR ucAction; // 0: turn off encoder - // 1: setup and turn on encoder - UCHAR ucTruncate; // bit0=0: Disable truncate - // =1: Enable truncate - // bit4=0: 666RGB - // =1: 888RGB - UCHAR ucSpatial; // bit0=0: Disable spatial dithering - // =1: Enable spatial dithering - // bit4=0: 666RGB - // =1: 888RGB - UCHAR ucTemporal; // bit0=0: Disable temporal dithering - // =1: Enable temporal dithering - // bit4=0: 666RGB - // =1: 888RGB - // bit5=0: Gray level 2 - // =1: Gray level 4 - UCHAR ucFRC; // bit4=0: 25FRC_SEL pattern E - // =1: 25FRC_SEL pattern F - // bit6:5=0: 50FRC_SEL pattern A - // =1: 50FRC_SEL pattern B - // =2: 50FRC_SEL pattern C - // =3: 50FRC_SEL pattern D - // bit7=0: 75FRC_SEL pattern E - // =1: 75FRC_SEL pattern F -}LVDS_ENCODER_CONTROL_PARAMETERS_V2; - -#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 - -#define TMDS1_ENCODER_CONTROL_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 -#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 - -#define TMDS2_ENCODER_CONTROL_PARAMETERS_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 -#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS2_ENCODER_CONTROL_PARAMETERS_V2 - -#define LVDS_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V2 -#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 - -#define TMDS1_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 -#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS1_ENCODER_CONTROL_PARAMETERS_V3 - -#define TMDS2_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 -#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V3 - -/****************************************************************************/ -// Structures used by ### -/****************************************************************************/ -typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS -{ - UCHAR ucEnable; // Enable or Disable External TMDS encoder - UCHAR ucMisc; // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB} - UCHAR ucPadding[2]; -}ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS; - -typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION -{ - ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS sXTmdsEncoder; - WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion -}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION; - -#define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 - -typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2 -{ - ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 sXTmdsEncoder; - WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion -}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2; - -typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION -{ - DIG_ENCODER_CONTROL_PARAMETERS sDigEncoder; - WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; -}EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION; - -/****************************************************************************/ -// Structures used by DVOEncoderControlTable -/****************************************************************************/ -//ucTableFormatRevision=1,ucTableContentRevision=3 - -//ucDVOConfig: -#define DVO_ENCODER_CONFIG_RATE_SEL 0x01 -#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00 -#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01 -#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c -#define DVO_ENCODER_CONFIG_LOW12BIT 0x00 -#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04 -#define DVO_ENCODER_CONFIG_24BIT 0x08 - -typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3 -{ - USHORT usPixelClock; - UCHAR ucDVOConfig; - UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT - UCHAR ucReseved[4]; -}DVO_ENCODER_CONTROL_PARAMETERS_V3; -#define DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 DVO_ENCODER_CONTROL_PARAMETERS_V3 - -//ucTableFormatRevision=1 -//ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for -// bit1=0: non-coherent mode -// =1: coherent mode - -//========================================================================================== -//Only change is here next time when changing encoder parameter definitions again! -#define LVDS_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 -#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_LAST LVDS_ENCODER_CONTROL_PARAMETERS_LAST - -#define TMDS1_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 -#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS1_ENCODER_CONTROL_PARAMETERS_LAST - -#define TMDS2_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 -#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS2_ENCODER_CONTROL_PARAMETERS_LAST - -#define DVO_ENCODER_CONTROL_PARAMETERS_LAST DVO_ENCODER_CONTROL_PARAMETERS -#define DVO_ENCODER_CONTROL_PS_ALLOCATION_LAST DVO_ENCODER_CONTROL_PS_ALLOCATION - -//========================================================================================== -#define PANEL_ENCODER_MISC_DUAL 0x01 -#define PANEL_ENCODER_MISC_COHERENT 0x02 -#define PANEL_ENCODER_MISC_TMDS_LINKB 0x04 -#define PANEL_ENCODER_MISC_HDMI_TYPE 0x08 - -#define PANEL_ENCODER_ACTION_DISABLE ATOM_DISABLE -#define PANEL_ENCODER_ACTION_ENABLE ATOM_ENABLE -#define PANEL_ENCODER_ACTION_COHERENTSEQ (ATOM_ENABLE+1) - -#define PANEL_ENCODER_TRUNCATE_EN 0x01 -#define PANEL_ENCODER_TRUNCATE_DEPTH 0x10 -#define PANEL_ENCODER_SPATIAL_DITHER_EN 0x01 -#define PANEL_ENCODER_SPATIAL_DITHER_DEPTH 0x10 -#define PANEL_ENCODER_TEMPORAL_DITHER_EN 0x01 -#define PANEL_ENCODER_TEMPORAL_DITHER_DEPTH 0x10 -#define PANEL_ENCODER_TEMPORAL_LEVEL_4 0x20 -#define PANEL_ENCODER_25FRC_MASK 0x10 -#define PANEL_ENCODER_25FRC_E 0x00 -#define PANEL_ENCODER_25FRC_F 0x10 -#define PANEL_ENCODER_50FRC_MASK 0x60 -#define PANEL_ENCODER_50FRC_A 0x00 -#define PANEL_ENCODER_50FRC_B 0x20 -#define PANEL_ENCODER_50FRC_C 0x40 -#define PANEL_ENCODER_50FRC_D 0x60 -#define PANEL_ENCODER_75FRC_MASK 0x80 -#define PANEL_ENCODER_75FRC_E 0x00 -#define PANEL_ENCODER_75FRC_F 0x80 - -/****************************************************************************/ -// Structures used by SetVoltageTable -/****************************************************************************/ -#define SET_VOLTAGE_TYPE_ASIC_VDDC 1 -#define SET_VOLTAGE_TYPE_ASIC_MVDDC 2 -#define SET_VOLTAGE_TYPE_ASIC_MVDDQ 3 -#define SET_VOLTAGE_TYPE_ASIC_VDDCI 4 -#define SET_VOLTAGE_INIT_MODE 5 -#define SET_VOLTAGE_GET_MAX_VOLTAGE 6 //Gets the Max. voltage for the soldered Asic - -#define SET_ASIC_VOLTAGE_MODE_ALL_SOURCE 0x1 -#define SET_ASIC_VOLTAGE_MODE_SOURCE_A 0x2 -#define SET_ASIC_VOLTAGE_MODE_SOURCE_B 0x4 - -#define SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE 0x0 -#define SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL 0x1 -#define SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK 0x2 - -typedef struct _SET_VOLTAGE_PARAMETERS -{ - UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ - UCHAR ucVoltageMode; // To set all, to set source A or source B or ... - UCHAR ucVoltageIndex; // An index to tell which voltage level - UCHAR ucReserved; -}SET_VOLTAGE_PARAMETERS; - -typedef struct _SET_VOLTAGE_PARAMETERS_V2 -{ - UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ - UCHAR ucVoltageMode; // Not used, maybe use for state machine for differen power mode - USHORT usVoltageLevel; // real voltage level -}SET_VOLTAGE_PARAMETERS_V2; - -typedef struct _SET_VOLTAGE_PS_ALLOCATION -{ - SET_VOLTAGE_PARAMETERS sASICSetVoltage; - WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; -}SET_VOLTAGE_PS_ALLOCATION; - -/****************************************************************************/ -// Structures used by TVEncoderControlTable -/****************************************************************************/ -typedef struct _TV_ENCODER_CONTROL_PARAMETERS -{ - USHORT usPixelClock; // in 10KHz; for bios convenient - UCHAR ucTvStandard; // See definition "ATOM_TV_NTSC ..." - UCHAR ucAction; // 0: turn off encoder - // 1: setup and turn on encoder -}TV_ENCODER_CONTROL_PARAMETERS; - -typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION -{ - TV_ENCODER_CONTROL_PARAMETERS sTVEncoder; - WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; // Don't set this one -}TV_ENCODER_CONTROL_PS_ALLOCATION; - -//==============================Data Table Portion==================================== - -/****************************************************************************/ -// Structure used in Data.mtb -/****************************************************************************/ -typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES -{ - USHORT UtilityPipeLine; // Offest for the utility to get parser info,Don't change this position! - USHORT MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios - USHORT MultimediaConfigInfo; // Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios - USHORT StandardVESA_Timing; // Only used by Bios - USHORT FirmwareInfo; // Shared by various SW components,latest version 1.4 - USHORT DAC_Info; // Will be obsolete from R600 - USHORT LVDS_Info; // Shared by various SW components,latest version 1.1 - USHORT TMDS_Info; // Will be obsolete from R600 - USHORT AnalogTV_Info; // Shared by various SW components,latest version 1.1 - USHORT SupportedDevicesInfo; // Will be obsolete from R600 - USHORT GPIO_I2C_Info; // Shared by various SW components,latest version 1.2 will be used from R600 - USHORT VRAM_UsageByFirmware; // Shared by various SW components,latest version 1.3 will be used from R600 - USHORT GPIO_Pin_LUT; // Shared by various SW components,latest version 1.1 - USHORT VESA_ToInternalModeLUT; // Only used by Bios - USHORT ComponentVideoInfo; // Shared by various SW components,latest version 2.1 will be used from R600 - USHORT PowerPlayInfo; // Shared by various SW components,latest version 2.1,new design from R600 - USHORT CompassionateData; // Will be obsolete from R600 - USHORT SaveRestoreInfo; // Only used by Bios - USHORT PPLL_SS_Info; // Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info - USHORT OemInfo; // Defined and used by external SW, should be obsolete soon - USHORT XTMDS_Info; // Will be obsolete from R600 - USHORT MclkSS_Info; // Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used - USHORT Object_Header; // Shared by various SW components,latest version 1.1 - USHORT IndirectIOAccess; // Only used by Bios,this table position can't change at all!! - USHORT MC_InitParameter; // Only used by command table - USHORT ASIC_VDDC_Info; // Will be obsolete from R600 - USHORT ASIC_InternalSS_Info; // New tabel name from R600, used to be called "ASIC_MVDDC_Info" - USHORT TV_VideoMode; // Only used by command table - USHORT VRAM_Info; // Only used by command table, latest version 1.3 - USHORT MemoryTrainingInfo; // Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1 - USHORT IntegratedSystemInfo; // Shared by various SW components - USHORT ASIC_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600 - USHORT VoltageObjectInfo; // Shared by various SW components, latest version 1.1 - USHORT PowerSourceInfo; // Shared by various SW components, latest versoin 1.1 -}ATOM_MASTER_LIST_OF_DATA_TABLES; - -typedef struct _ATOM_MASTER_DATA_TABLE -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_MASTER_LIST_OF_DATA_TABLES ListOfDataTables; -}ATOM_MASTER_DATA_TABLE; - -/****************************************************************************/ -// Structure used in MultimediaCapabilityInfoTable -/****************************************************************************/ -typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ULONG ulSignature; // HW info table signature string "$ATI" - UCHAR ucI2C_Type; // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc) - UCHAR ucTV_OutInfo; // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7) - UCHAR ucVideoPortInfo; // Provides the video port capabilities - UCHAR ucHostPortInfo; // Provides host port configuration information -}ATOM_MULTIMEDIA_CAPABILITY_INFO; - -/****************************************************************************/ -// Structure used in MultimediaConfigInfoTable -/****************************************************************************/ -typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ULONG ulSignature; // MM info table signature sting "$MMT" - UCHAR ucTunerInfo; // Type of tuner installed on the adapter (4:0) and video input for tuner (7:5) - UCHAR ucAudioChipInfo; // List the audio chip type (3:0) product type (4) and OEM revision (7:5) - UCHAR ucProductID; // Defines as OEM ID or ATI board ID dependent on product type setting - UCHAR ucMiscInfo1; // Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7) - UCHAR ucMiscInfo2; // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6) - UCHAR ucMiscInfo3; // Video Decoder Type (3:0) Video In Standard/Crystal (7:4) - UCHAR ucMiscInfo4; // Video Decoder Host Config (2:0) reserved (7:3) - UCHAR ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) - UCHAR ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) - UCHAR ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) - UCHAR ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) - UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) -}ATOM_MULTIMEDIA_CONFIG_INFO; - -/****************************************************************************/ -// Structures used in FirmwareInfoTable -/****************************************************************************/ - -// usBIOSCapability Defintion: -// Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted; -// Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported; -// Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported; -// Others: Reserved -#define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED 0x0001 -#define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT 0x0002 -#define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT 0x0004 -#define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008 // (valid from v1.1 ~v1.4):=1: memclk SS enable, =0 memclk SS disable. -#define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010 // (valid from v1.1 ~v1.4):=1: engclk SS enable, =0 engclk SS disable. -#define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU 0x0020 -#define ATOM_BIOS_INFO_WMI_SUPPORT 0x0040 -#define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM 0x0080 -#define ATOM_BIOS_INFO_HYPERMEMORY_SUPPORT 0x0100 -#define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK 0x1E00 -#define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET 0x2000 -#define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE 0x4000 -#define ATOM_BIOS_INFO_MEMORY_CLOCK_EXT_SS_SUPPORT 0x0008 // (valid from v2.1 ): =1: memclk ss enable with external ss chip -#define ATOM_BIOS_INFO_ENGINE_CLOCK_EXT_SS_SUPPORT 0x0010 // (valid from v2.1 ): =1: engclk ss enable with external ss chip - -#ifndef _H2INC - -//Please don't add or expand this bitfield structure below, this one will retire soon.! -typedef struct _ATOM_FIRMWARE_CAPABILITY -{ -#if ATOM_BIG_ENDIAN - USHORT Reserved:3; - USHORT HyperMemory_Size:4; - USHORT HyperMemory_Support:1; - USHORT PPMode_Assigned:1; - USHORT WMI_SUPPORT:1; - USHORT GPUControlsBL:1; - USHORT EngineClockSS_Support:1; - USHORT MemoryClockSS_Support:1; - USHORT ExtendedDesktopSupport:1; - USHORT DualCRTC_Support:1; - USHORT FirmwarePosted:1; -#else - USHORT FirmwarePosted:1; - USHORT DualCRTC_Support:1; - USHORT ExtendedDesktopSupport:1; - USHORT MemoryClockSS_Support:1; - USHORT EngineClockSS_Support:1; - USHORT GPUControlsBL:1; - USHORT WMI_SUPPORT:1; - USHORT PPMode_Assigned:1; - USHORT HyperMemory_Support:1; - USHORT HyperMemory_Size:4; - USHORT Reserved:3; -#endif -}ATOM_FIRMWARE_CAPABILITY; - -typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS -{ - ATOM_FIRMWARE_CAPABILITY sbfAccess; - USHORT susAccess; -}ATOM_FIRMWARE_CAPABILITY_ACCESS; - -#else - -typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS -{ - USHORT susAccess; -}ATOM_FIRMWARE_CAPABILITY_ACCESS; - -#endif - -typedef struct _ATOM_FIRMWARE_INFO -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ULONG ulFirmwareRevision; - ULONG ulDefaultEngineClock; //In 10Khz unit - ULONG ulDefaultMemoryClock; //In 10Khz unit - ULONG ulDriverTargetEngineClock; //In 10Khz unit - ULONG ulDriverTargetMemoryClock; //In 10Khz unit - ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit - ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit - ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit - ULONG ulASICMaxEngineClock; //In 10Khz unit - ULONG ulASICMaxMemoryClock; //In 10Khz unit - UCHAR ucASICMaxTemperature; - UCHAR ucPadding[3]; //Don't use them - ULONG aulReservedForBIOS[3]; //Don't use them - USHORT usMinEngineClockPLL_Input; //In 10Khz unit - USHORT usMaxEngineClockPLL_Input; //In 10Khz unit - USHORT usMinEngineClockPLL_Output; //In 10Khz unit - USHORT usMinMemoryClockPLL_Input; //In 10Khz unit - USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit - USHORT usMinMemoryClockPLL_Output; //In 10Khz unit - USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk - USHORT usMinPixelClockPLL_Input; //In 10Khz unit - USHORT usMaxPixelClockPLL_Input; //In 10Khz unit - USHORT usMinPixelClockPLL_Output; //In 10Khz unit, the definitions above can't change!!! - ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; - USHORT usReferenceClock; //In 10Khz unit - USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit - UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit - UCHAR ucDesign_ID; //Indicate what is the board design - UCHAR ucMemoryModule_ID; //Indicate what is the board design -}ATOM_FIRMWARE_INFO; - -typedef struct _ATOM_FIRMWARE_INFO_V1_2 -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ULONG ulFirmwareRevision; - ULONG ulDefaultEngineClock; //In 10Khz unit - ULONG ulDefaultMemoryClock; //In 10Khz unit - ULONG ulDriverTargetEngineClock; //In 10Khz unit - ULONG ulDriverTargetMemoryClock; //In 10Khz unit - ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit - ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit - ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit - ULONG ulASICMaxEngineClock; //In 10Khz unit - ULONG ulASICMaxMemoryClock; //In 10Khz unit - UCHAR ucASICMaxTemperature; - UCHAR ucMinAllowedBL_Level; - UCHAR ucPadding[2]; //Don't use them - ULONG aulReservedForBIOS[2]; //Don't use them - ULONG ulMinPixelClockPLL_Output; //In 10Khz unit - USHORT usMinEngineClockPLL_Input; //In 10Khz unit - USHORT usMaxEngineClockPLL_Input; //In 10Khz unit - USHORT usMinEngineClockPLL_Output; //In 10Khz unit - USHORT usMinMemoryClockPLL_Input; //In 10Khz unit - USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit - USHORT usMinMemoryClockPLL_Output; //In 10Khz unit - USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk - USHORT usMinPixelClockPLL_Input; //In 10Khz unit - USHORT usMaxPixelClockPLL_Input; //In 10Khz unit - USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output - ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; - USHORT usReferenceClock; //In 10Khz unit - USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit - UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit - UCHAR ucDesign_ID; //Indicate what is the board design - UCHAR ucMemoryModule_ID; //Indicate what is the board design -}ATOM_FIRMWARE_INFO_V1_2; - -typedef struct _ATOM_FIRMWARE_INFO_V1_3 -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ULONG ulFirmwareRevision; - ULONG ulDefaultEngineClock; //In 10Khz unit - ULONG ulDefaultMemoryClock; //In 10Khz unit - ULONG ulDriverTargetEngineClock; //In 10Khz unit - ULONG ulDriverTargetMemoryClock; //In 10Khz unit - ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit - ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit - ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit - ULONG ulASICMaxEngineClock; //In 10Khz unit - ULONG ulASICMaxMemoryClock; //In 10Khz unit - UCHAR ucASICMaxTemperature; - UCHAR ucMinAllowedBL_Level; - UCHAR ucPadding[2]; //Don't use them - ULONG aulReservedForBIOS; //Don't use them - ULONG ul3DAccelerationEngineClock;//In 10Khz unit - ULONG ulMinPixelClockPLL_Output; //In 10Khz unit - USHORT usMinEngineClockPLL_Input; //In 10Khz unit - USHORT usMaxEngineClockPLL_Input; //In 10Khz unit - USHORT usMinEngineClockPLL_Output; //In 10Khz unit - USHORT usMinMemoryClockPLL_Input; //In 10Khz unit - USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit - USHORT usMinMemoryClockPLL_Output; //In 10Khz unit - USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk - USHORT usMinPixelClockPLL_Input; //In 10Khz unit - USHORT usMaxPixelClockPLL_Input; //In 10Khz unit - USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output - ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; - USHORT usReferenceClock; //In 10Khz unit - USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit - UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit - UCHAR ucDesign_ID; //Indicate what is the board design - UCHAR ucMemoryModule_ID; //Indicate what is the board design -}ATOM_FIRMWARE_INFO_V1_3; - -typedef struct _ATOM_FIRMWARE_INFO_V1_4 -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ULONG ulFirmwareRevision; - ULONG ulDefaultEngineClock; //In 10Khz unit - ULONG ulDefaultMemoryClock; //In 10Khz unit - ULONG ulDriverTargetEngineClock; //In 10Khz unit - ULONG ulDriverTargetMemoryClock; //In 10Khz unit - ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit - ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit - ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit - ULONG ulASICMaxEngineClock; //In 10Khz unit - ULONG ulASICMaxMemoryClock; //In 10Khz unit - UCHAR ucASICMaxTemperature; - UCHAR ucMinAllowedBL_Level; - USHORT usBootUpVDDCVoltage; //In MV unit - USHORT usLcdMinPixelClockPLL_Output; // In MHz unit - USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit - ULONG ul3DAccelerationEngineClock;//In 10Khz unit - ULONG ulMinPixelClockPLL_Output; //In 10Khz unit - USHORT usMinEngineClockPLL_Input; //In 10Khz unit - USHORT usMaxEngineClockPLL_Input; //In 10Khz unit - USHORT usMinEngineClockPLL_Output; //In 10Khz unit - USHORT usMinMemoryClockPLL_Input; //In 10Khz unit - USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit - USHORT usMinMemoryClockPLL_Output; //In 10Khz unit - USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk - USHORT usMinPixelClockPLL_Input; //In 10Khz unit - USHORT usMaxPixelClockPLL_Input; //In 10Khz unit - USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output - ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; - USHORT usReferenceClock; //In 10Khz unit - USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit - UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit - UCHAR ucDesign_ID; //Indicate what is the board design - UCHAR ucMemoryModule_ID; //Indicate what is the board design -}ATOM_FIRMWARE_INFO_V1_4; - -//the structure below to be used from Cypress -typedef struct _ATOM_FIRMWARE_INFO_V2_1 -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ULONG ulFirmwareRevision; - ULONG ulDefaultEngineClock; //In 10Khz unit - ULONG ulDefaultMemoryClock; //In 10Khz unit - ULONG ulReserved1; - ULONG ulReserved2; - ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit - ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit - ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit - ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock - ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit - UCHAR ucReserved1; //Was ucASICMaxTemperature; - UCHAR ucMinAllowedBL_Level; - USHORT usBootUpVDDCVoltage; //In MV unit - USHORT usLcdMinPixelClockPLL_Output; // In MHz unit - USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit - ULONG ulReserved4; //Was ulAsicMaximumVoltage - ULONG ulMinPixelClockPLL_Output; //In 10Khz unit - USHORT usMinEngineClockPLL_Input; //In 10Khz unit - USHORT usMaxEngineClockPLL_Input; //In 10Khz unit - USHORT usMinEngineClockPLL_Output; //In 10Khz unit - USHORT usMinMemoryClockPLL_Input; //In 10Khz unit - USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit - USHORT usMinMemoryClockPLL_Output; //In 10Khz unit - USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk - USHORT usMinPixelClockPLL_Input; //In 10Khz unit - USHORT usMaxPixelClockPLL_Input; //In 10Khz unit - USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output - ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; - USHORT usCoreReferenceClock; //In 10Khz unit - USHORT usMemoryReferenceClock; //In 10Khz unit - USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock - UCHAR ucMemoryModule_ID; //Indicate what is the board design - UCHAR ucReserved4[3]; -}ATOM_FIRMWARE_INFO_V2_1; - - -#define ATOM_FIRMWARE_INFO_LAST ATOM_FIRMWARE_INFO_V2_1 - -/****************************************************************************/ -// Structures used in IntegratedSystemInfoTable -/****************************************************************************/ -#define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN 0x2 -#define IGP_CAP_FLAG_AC_CARD 0x4 -#define IGP_CAP_FLAG_SDVO_CARD 0x8 -#define IGP_CAP_FLAG_POSTDIV_BY_2_MODE 0x10 - -typedef struct _ATOM_INTEGRATED_SYSTEM_INFO -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ULONG ulBootUpEngineClock; //in 10kHz unit - ULONG ulBootUpMemoryClock; //in 10kHz unit - ULONG ulMaxSystemMemoryClock; //in 10kHz unit - ULONG ulMinSystemMemoryClock; //in 10kHz unit - UCHAR ucNumberOfCyclesInPeriodHi; - UCHAR ucLCDTimingSel; //=0:not valid.!=0 sel this timing descriptor from LCD EDID. - USHORT usReserved1; - USHORT usInterNBVoltageLow; //An intermidiate PMW value to set the voltage - USHORT usInterNBVoltageHigh; //Another intermidiate PMW value to set the voltage - ULONG ulReserved[2]; - - USHORT usFSBClock; //In MHz unit - USHORT usCapabilityFlag; //Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable - //Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card - //Bit[4]==1: P/2 mode, ==0: P/1 mode - USHORT usPCIENBCfgReg7; //bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal - USHORT usK8MemoryClock; //in MHz unit - USHORT usK8SyncStartDelay; //in 0.01 us unit - USHORT usK8DataReturnTime; //in 0.01 us unit - UCHAR ucMaxNBVoltage; - UCHAR ucMinNBVoltage; - UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved - UCHAR ucNumberOfCyclesInPeriod; //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod - UCHAR ucStartingPWM_HighTime; //CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime - UCHAR ucHTLinkWidth; //16 bit vs. 8 bit - UCHAR ucMaxNBVoltageHigh; - UCHAR ucMinNBVoltageHigh; -}ATOM_INTEGRATED_SYSTEM_INFO; - -/* Explanation on entries in ATOM_INTEGRATED_SYSTEM_INFO -ulBootUpMemoryClock: For Intel IGP,it's the UMA system memory clock - For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock -ulMaxSystemMemoryClock: For Intel IGP,it's the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 - For AMD IGP,for now this can be 0 -ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 - For AMD IGP,for now this can be 0 - -usFSBClock: For Intel IGP,it's FSB Freq - For AMD IGP,it's HT Link Speed - -usK8MemoryClock: For AMD IGP only. For RevF CPU, set it to 200 -usK8SyncStartDelay: For AMD IGP only. Memory access latency in K8, required for watermark calculation -usK8DataReturnTime: For AMD IGP only. Memory access latency in K8, required for watermark calculation - -VC:Voltage Control -ucMaxNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. -ucMinNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. - -ucNumberOfCyclesInPeriod: Indicate how many cycles when PWM duty is 100%. low 8 bits of the value. -ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0 - -ucMaxNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. -ucMinNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. - - -usInterNBVoltageLow: Voltage regulator dependent PWM value. The value makes the the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all. -usInterNBVoltageHigh: Voltage regulator dependent PWM value. The value makes the the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all. -*/ - - -/* -The following IGP table is introduced from RS780, which is supposed to be put by SBIOS in FB before IGP VBIOS starts VPOST; -Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need. -The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries. - -SW components can access the IGP system infor structure in the same way as before -*/ - - -typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ULONG ulBootUpEngineClock; //in 10kHz unit - ULONG ulReserved1[2]; //must be 0x0 for the reserved - ULONG ulBootUpUMAClock; //in 10kHz unit - ULONG ulBootUpSidePortClock; //in 10kHz unit - ULONG ulMinSidePortClock; //in 10kHz unit - ULONG ulReserved2[6]; //must be 0x0 for the reserved - ULONG ulSystemConfig; //see explanation below - ULONG ulBootUpReqDisplayVector; - ULONG ulOtherDisplayMisc; - ULONG ulDDISlot1Config; - ULONG ulDDISlot2Config; - UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved - UCHAR ucUMAChannelNumber; - UCHAR ucDockingPinBit; - UCHAR ucDockingPinPolarity; - ULONG ulDockingPinCFGInfo; - ULONG ulCPUCapInfo; - USHORT usNumberOfCyclesInPeriod; - USHORT usMaxNBVoltage; - USHORT usMinNBVoltage; - USHORT usBootUpNBVoltage; - ULONG ulHTLinkFreq; //in 10Khz - USHORT usMinHTLinkWidth; - USHORT usMaxHTLinkWidth; - USHORT usUMASyncStartDelay; - USHORT usUMADataReturnTime; - USHORT usLinkStatusZeroTime; - USHORT usDACEfuse; //for storing badgap value (for RS880 only) - ULONG ulHighVoltageHTLinkFreq; // in 10Khz - ULONG ulLowVoltageHTLinkFreq; // in 10Khz - USHORT usMaxUpStreamHTLinkWidth; - USHORT usMaxDownStreamHTLinkWidth; - USHORT usMinUpStreamHTLinkWidth; - USHORT usMinDownStreamHTLinkWidth; - USHORT usFirmwareVersion; //0 means FW is not supported. Otherwise it's the FW version loaded by SBIOS and driver should enable FW. - USHORT usFullT0Time; // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us. - ULONG ulReserved3[96]; //must be 0x0 -}ATOM_INTEGRATED_SYSTEM_INFO_V2; - -/* -ulBootUpEngineClock: Boot-up Engine Clock in 10Khz; -ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present -ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present,this could be equal to or less than maximum supported Sideport memory clock - -ulSystemConfig: -Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode; -Bit[1]=1: system boots up at AMD overdrived state or user customized mode. In this case, driver will just stick to this boot-up mode. No other PowerPlay state - =0: system boots up at driver control state. Power state depends on PowerPlay table. -Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used. -Bit[3]=1: Only one power state(Performance) will be supported. - =0: Multiple power states supported from PowerPlay table. -Bit[4]=1: CLMC is supported and enabled on current system. - =0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface. -Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement. - =0: CDLW is disabled. If CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max HT width will be applied. -Bit[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v and powerplay table voltage drop/throttling request will be ignored. - =0: Voltage settings is determined by powerplay table. -Bit[7]=1: Enable CLMC as hybrid Mode. CDLD and CILR will be disabled in this case and we're using legacy C1E. This is workaround for CPU(Griffin) performance issue. - =0: Enable CLMC as regular mode, CDLD and CILR will be enabled. -Bit[8]=1: CDLF is supported and enabled on current system. - =0: CDLF is not supported or enabled on current system. -Bit[9]=1: DLL Shut Down feature is enabled on current system. - =0: DLL Shut Down feature is not enabled or supported on current system. - -ulBootUpReqDisplayVector: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEVICE_xxx_SUPPORT for the bit vector definitions. - -ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion; - [7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are supported by the system. Refer to ucTVSupportedStd definition; - -ulDDISlot1Config: Describes the PCIE lane configuration on this DDI PCIE slot (ADD2 card) or connector (Mobile design). - [3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12) - [7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 4=1 lane 3:0; bit 5=1 lane 7:4; bit 6=1 lane 11:8; bit 7=1 lane 15:12) - When a DDI connector is not "paired" (meaming two connections mutualexclusive on chassis or docking, only one of them can be connected at one time. - in both chassis and docking, SBIOS has to duplicate the same PCIE lane info from chassis to docking or vice versa. For example: - one DDI connector is only populated in docking with PCIE lane 8-11, but there is no paired connection on chassis, SBIOS has to copy bit 6 to bit 2. - - [15:8] - Lane configuration attribute; - [23:16]- Connector type, possible value: - CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D - CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D - CONNECTOR_OBJECT_ID_HDMI_TYPE_A - CONNECTOR_OBJECT_ID_DISPLAYPORT - CONNECTOR_OBJECT_ID_eDP - [31:24]- Reserved - -ulDDISlot2Config: Same as Slot1. -ucMemoryType: SidePort memory type, set it to 0x0 when Sideport memory is not installed. Driver needs this info to change sideport memory clock. Not for display in CCC. -For IGP, Hypermemory is the only memory type showed in CCC. - -ucUMAChannelNumber: how many channels for the UMA; - -ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin -ucDockingPinBit: which bit in this register to read the pin status; -ucDockingPinPolarity:Polarity of the pin when docked; - -ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, other bits reserved for now and must be 0x0 - -usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%. - -usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode. -usMinNBVoltage:Min. voltage control value in either PWM or GPIO mode. - GPIO mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=0 - PWM mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=1 - GPU SW don't control mode: usMaxNBVoltage & usMinNBVoltage=0 and no care about ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE - -usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value. - -ulHTLinkFreq: Bootup HT link Frequency in 10Khz. -usMinHTLinkWidth: Bootup minimum HT link width. If CDLW disabled, this is equal to usMaxHTLinkWidth. - If CDLW enabled, both upstream and downstream width should be the same during bootup. -usMaxHTLinkWidth: Bootup maximum HT link width. If CDLW disabled, this is equal to usMinHTLinkWidth. - If CDLW enabled, both upstream and downstream width should be the same during bootup. - -usUMASyncStartDelay: Memory access latency, required for watermark calculation -usUMADataReturnTime: Memory access latency, required for watermark calculation -usLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us -for Griffin or Greyhound. SBIOS needs to convert to actual time by: - if T0Ttime [5:4]=00b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.1us (0.0 to 1.5us) - if T0Ttime [5:4]=01b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.5us (0.0 to 7.5us) - if T0Ttime [5:4]=10b, then usLinkStatusZeroTime=T0Ttime [3:0]*2.0us (0.0 to 30us) - if T0Ttime [5:4]=11b, and T0Ttime [3:0]=0x0 to 0xa, then usLinkStatusZeroTime=T0Ttime [3:0]*20us (0.0 to 200us) - -ulHighVoltageHTLinkFreq: HT link frequency for power state with low voltage. If boot up runs in HT1, this must be 0. - This must be less than or equal to ulHTLinkFreq(bootup frequency). -ulLowVoltageHTLinkFreq: HT link frequency for power state with low voltage or voltage scaling 1.0v~1.1v. If boot up runs in HT1, this must be 0. - This must be less than or equal to ulHighVoltageHTLinkFreq. - -usMaxUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMaxHTLinkWidth. Not used for now. -usMaxDownStreamHTLinkWidth: same as above. -usMinUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMinHTLinkWidth. Not used for now. -usMinDownStreamHTLinkWidth: same as above. -*/ - - -#define SYSTEM_CONFIG_POWEREXPRESS_ENABLE 0x00000001 -#define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE 0x00000002 -#define SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE 0x00000004 -#define SYSTEM_CONFIG_PERFORMANCE_POWERSTATE_ONLY 0x00000008 -#define SYSTEM_CONFIG_CLMC_ENABLED 0x00000010 -#define SYSTEM_CONFIG_CDLW_ENABLED 0x00000020 -#define SYSTEM_CONFIG_HIGH_VOLTAGE_REQUESTED 0x00000040 -#define SYSTEM_CONFIG_CLMC_HYBRID_MODE_ENABLED 0x00000080 -#define SYSTEM_CONFIG_CDLF_ENABLED 0x00000100 -#define SYSTEM_CONFIG_DLL_SHUTDOWN_ENABLED 0x00000200 - -#define IGP_DDI_SLOT_LANE_CONFIG_MASK 0x000000FF - -#define b0IGP_DDI_SLOT_LANE_MAP_MASK 0x0F -#define b0IGP_DDI_SLOT_DOCKING_LANE_MAP_MASK 0xF0 -#define b0IGP_DDI_SLOT_CONFIG_LANE_0_3 0x01 -#define b0IGP_DDI_SLOT_CONFIG_LANE_4_7 0x02 -#define b0IGP_DDI_SLOT_CONFIG_LANE_8_11 0x04 -#define b0IGP_DDI_SLOT_CONFIG_LANE_12_15 0x08 - -#define IGP_DDI_SLOT_ATTRIBUTE_MASK 0x0000FF00 -#define IGP_DDI_SLOT_CONFIG_REVERSED 0x00000100 -#define b1IGP_DDI_SLOT_CONFIG_REVERSED 0x01 - -#define IGP_DDI_SLOT_CONNECTOR_TYPE_MASK 0x00FF0000 - -// IntegratedSystemInfoTable new Rev is V5 after V2, because of the real rev of V2 is v1.4. This rev is used for RR -typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ULONG ulBootUpEngineClock; //in 10kHz unit - ULONG ulDentistVCOFreq; //Dentist VCO clock in 10kHz unit, the source of GPU SCLK, LCLK, UCLK and VCLK. - ULONG ulLClockFreq; //GPU Lclk freq in 10kHz unit, have relationship with NCLK in NorthBridge - ULONG ulBootUpUMAClock; //in 10kHz unit - ULONG ulReserved1[8]; //must be 0x0 for the reserved - ULONG ulBootUpReqDisplayVector; - ULONG ulOtherDisplayMisc; - ULONG ulReserved2[4]; //must be 0x0 for the reserved - ULONG ulSystemConfig; //TBD - ULONG ulCPUCapInfo; //TBD - USHORT usMaxNBVoltage; //high NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; - USHORT usMinNBVoltage; //low NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; - USHORT usBootUpNBVoltage; //boot up NB voltage - UCHAR ucHtcTmpLmt; //bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD - UCHAR ucTjOffset; //bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD - ULONG ulReserved3[4]; //must be 0x0 for the reserved - ULONG ulDDISlot1Config; //see above ulDDISlot1Config definition - ULONG ulDDISlot2Config; - ULONG ulDDISlot3Config; - ULONG ulDDISlot4Config; - ULONG ulReserved4[4]; //must be 0x0 for the reserved - UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved - UCHAR ucUMAChannelNumber; - USHORT usReserved; - ULONG ulReserved5[4]; //must be 0x0 for the reserved - ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];//arrays with values for CSR M3 arbiter for default - ULONG ulCSR_M3_ARB_CNTL_UVD[10]; //arrays with values for CSR M3 arbiter for UVD playback - ULONG ulCSR_M3_ARB_CNTL_FS3D[10];//arrays with values for CSR M3 arbiter for Full Screen 3D applications - ULONG ulReserved6[61]; //must be 0x0 -}ATOM_INTEGRATED_SYSTEM_INFO_V5; - -#define ATOM_CRT_INT_ENCODER1_INDEX 0x00000000 -#define ATOM_LCD_INT_ENCODER1_INDEX 0x00000001 -#define ATOM_TV_INT_ENCODER1_INDEX 0x00000002 -#define ATOM_DFP_INT_ENCODER1_INDEX 0x00000003 -#define ATOM_CRT_INT_ENCODER2_INDEX 0x00000004 -#define ATOM_LCD_EXT_ENCODER1_INDEX 0x00000005 -#define ATOM_TV_EXT_ENCODER1_INDEX 0x00000006 -#define ATOM_DFP_EXT_ENCODER1_INDEX 0x00000007 -#define ATOM_CV_INT_ENCODER1_INDEX 0x00000008 -#define ATOM_DFP_INT_ENCODER2_INDEX 0x00000009 -#define ATOM_CRT_EXT_ENCODER1_INDEX 0x0000000A -#define ATOM_CV_EXT_ENCODER1_INDEX 0x0000000B -#define ATOM_DFP_INT_ENCODER3_INDEX 0x0000000C -#define ATOM_DFP_INT_ENCODER4_INDEX 0x0000000D - -// define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSelTable -#define ASIC_INT_DAC1_ENCODER_ID 0x00 -#define ASIC_INT_TV_ENCODER_ID 0x02 -#define ASIC_INT_DIG1_ENCODER_ID 0x03 -#define ASIC_INT_DAC2_ENCODER_ID 0x04 -#define ASIC_EXT_TV_ENCODER_ID 0x06 -#define ASIC_INT_DVO_ENCODER_ID 0x07 -#define ASIC_INT_DIG2_ENCODER_ID 0x09 -#define ASIC_EXT_DIG_ENCODER_ID 0x05 -#define ASIC_EXT_DIG2_ENCODER_ID 0x08 -#define ASIC_INT_DIG3_ENCODER_ID 0x0a -#define ASIC_INT_DIG4_ENCODER_ID 0x0b -#define ASIC_INT_DIG5_ENCODER_ID 0x0c -#define ASIC_INT_DIG6_ENCODER_ID 0x0d - -//define Encoder attribute -#define ATOM_ANALOG_ENCODER 0 -#define ATOM_DIGITAL_ENCODER 1 -#define ATOM_DP_ENCODER 2 - -#define ATOM_ENCODER_ENUM_MASK 0x70 -#define ATOM_ENCODER_ENUM_ID1 0x00 -#define ATOM_ENCODER_ENUM_ID2 0x10 -#define ATOM_ENCODER_ENUM_ID3 0x20 -#define ATOM_ENCODER_ENUM_ID4 0x30 -#define ATOM_ENCODER_ENUM_ID5 0x40 -#define ATOM_ENCODER_ENUM_ID6 0x50 - -#define ATOM_DEVICE_CRT1_INDEX 0x00000000 -#define ATOM_DEVICE_LCD1_INDEX 0x00000001 -#define ATOM_DEVICE_TV1_INDEX 0x00000002 -#define ATOM_DEVICE_DFP1_INDEX 0x00000003 -#define ATOM_DEVICE_CRT2_INDEX 0x00000004 -#define ATOM_DEVICE_LCD2_INDEX 0x00000005 -#define ATOM_DEVICE_DFP6_INDEX 0x00000006 -#define ATOM_DEVICE_DFP2_INDEX 0x00000007 -#define ATOM_DEVICE_CV_INDEX 0x00000008 -#define ATOM_DEVICE_DFP3_INDEX 0x00000009 -#define ATOM_DEVICE_DFP4_INDEX 0x0000000A -#define ATOM_DEVICE_DFP5_INDEX 0x0000000B - -#define ATOM_DEVICE_RESERVEDC_INDEX 0x0000000C -#define ATOM_DEVICE_RESERVEDD_INDEX 0x0000000D -#define ATOM_DEVICE_RESERVEDE_INDEX 0x0000000E -#define ATOM_DEVICE_RESERVEDF_INDEX 0x0000000F -#define ATOM_MAX_SUPPORTED_DEVICE_INFO (ATOM_DEVICE_DFP3_INDEX+1) -#define ATOM_MAX_SUPPORTED_DEVICE_INFO_2 ATOM_MAX_SUPPORTED_DEVICE_INFO -#define ATOM_MAX_SUPPORTED_DEVICE_INFO_3 (ATOM_DEVICE_DFP5_INDEX + 1 ) - -#define ATOM_MAX_SUPPORTED_DEVICE (ATOM_DEVICE_RESERVEDF_INDEX+1) - -#define ATOM_DEVICE_CRT1_SUPPORT (0x1L << ATOM_DEVICE_CRT1_INDEX ) -#define ATOM_DEVICE_LCD1_SUPPORT (0x1L << ATOM_DEVICE_LCD1_INDEX ) -#define ATOM_DEVICE_TV1_SUPPORT (0x1L << ATOM_DEVICE_TV1_INDEX ) -#define ATOM_DEVICE_DFP1_SUPPORT (0x1L << ATOM_DEVICE_DFP1_INDEX ) -#define ATOM_DEVICE_CRT2_SUPPORT (0x1L << ATOM_DEVICE_CRT2_INDEX ) -#define ATOM_DEVICE_LCD2_SUPPORT (0x1L << ATOM_DEVICE_LCD2_INDEX ) -#define ATOM_DEVICE_DFP6_SUPPORT (0x1L << ATOM_DEVICE_DFP6_INDEX ) -#define ATOM_DEVICE_DFP2_SUPPORT (0x1L << ATOM_DEVICE_DFP2_INDEX ) -#define ATOM_DEVICE_CV_SUPPORT (0x1L << ATOM_DEVICE_CV_INDEX ) -#define ATOM_DEVICE_DFP3_SUPPORT (0x1L << ATOM_DEVICE_DFP3_INDEX ) -#define ATOM_DEVICE_DFP4_SUPPORT (0x1L << ATOM_DEVICE_DFP4_INDEX ) -#define ATOM_DEVICE_DFP5_SUPPORT (0x1L << ATOM_DEVICE_DFP5_INDEX ) - -#define ATOM_DEVICE_CRT_SUPPORT (ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_CRT2_SUPPORT) -#define ATOM_DEVICE_DFP_SUPPORT (ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT | ATOM_DEVICE_DFP3_SUPPORT | ATOM_DEVICE_DFP4_SUPPORT | ATOM_DEVICE_DFP5_SUPPORT | ATOM_DEVICE_DFP6_SUPPORT) -#define ATOM_DEVICE_TV_SUPPORT (ATOM_DEVICE_TV1_SUPPORT) -#define ATOM_DEVICE_LCD_SUPPORT (ATOM_DEVICE_LCD1_SUPPORT | ATOM_DEVICE_LCD2_SUPPORT) - -#define ATOM_DEVICE_CONNECTOR_TYPE_MASK 0x000000F0 -#define ATOM_DEVICE_CONNECTOR_TYPE_SHIFT 0x00000004 -#define ATOM_DEVICE_CONNECTOR_VGA 0x00000001 -#define ATOM_DEVICE_CONNECTOR_DVI_I 0x00000002 -#define ATOM_DEVICE_CONNECTOR_DVI_D 0x00000003 -#define ATOM_DEVICE_CONNECTOR_DVI_A 0x00000004 -#define ATOM_DEVICE_CONNECTOR_SVIDEO 0x00000005 -#define ATOM_DEVICE_CONNECTOR_COMPOSITE 0x00000006 -#define ATOM_DEVICE_CONNECTOR_LVDS 0x00000007 -#define ATOM_DEVICE_CONNECTOR_DIGI_LINK 0x00000008 -#define ATOM_DEVICE_CONNECTOR_SCART 0x00000009 -#define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_A 0x0000000A -#define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_B 0x0000000B -#define ATOM_DEVICE_CONNECTOR_CASE_1 0x0000000E -#define ATOM_DEVICE_CONNECTOR_DISPLAYPORT 0x0000000F - - -#define ATOM_DEVICE_DAC_INFO_MASK 0x0000000F -#define ATOM_DEVICE_DAC_INFO_SHIFT 0x00000000 -#define ATOM_DEVICE_DAC_INFO_NODAC 0x00000000 -#define ATOM_DEVICE_DAC_INFO_DACA 0x00000001 -#define ATOM_DEVICE_DAC_INFO_DACB 0x00000002 -#define ATOM_DEVICE_DAC_INFO_EXDAC 0x00000003 - -#define ATOM_DEVICE_I2C_ID_NOI2C 0x00000000 - -#define ATOM_DEVICE_I2C_LINEMUX_MASK 0x0000000F -#define ATOM_DEVICE_I2C_LINEMUX_SHIFT 0x00000000 - -#define ATOM_DEVICE_I2C_ID_MASK 0x00000070 -#define ATOM_DEVICE_I2C_ID_SHIFT 0x00000004 -#define ATOM_DEVICE_I2C_ID_IS_FOR_NON_MM_USE 0x00000001 -#define ATOM_DEVICE_I2C_ID_IS_FOR_MM_USE 0x00000002 -#define ATOM_DEVICE_I2C_ID_IS_FOR_SDVO_USE 0x00000003 //For IGP RS600 -#define ATOM_DEVICE_I2C_ID_IS_FOR_DAC_SCL 0x00000004 //For IGP RS690 - -#define ATOM_DEVICE_I2C_HARDWARE_CAP_MASK 0x00000080 -#define ATOM_DEVICE_I2C_HARDWARE_CAP_SHIFT 0x00000007 -#define ATOM_DEVICE_USES_SOFTWARE_ASSISTED_I2C 0x00000000 -#define ATOM_DEVICE_USES_HARDWARE_ASSISTED_I2C 0x00000001 - -// usDeviceSupport: -// Bits0 = 0 - no CRT1 support= 1- CRT1 is supported -// Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported -// Bit 2 = 0 - no TV1 support= 1- TV1 is supported -// Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported -// Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported -// Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported -// Bit 6 = 0 - no DFP6 support= 1- DFP6 is supported -// Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported -// Bit 8 = 0 - no CV support= 1- CV is supported -// Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported -// Bit 10 = 0 - no DFP4 support= 1- DFP4 is supported -// Bit 11 = 0 - no DFP5 support= 1- DFP5 is supported -// -// - -/****************************************************************************/ -/* Structure used in MclkSS_InfoTable */ -/****************************************************************************/ -// ucI2C_ConfigID -// [7:0] - I2C LINE Associate ID -// = 0 - no I2C -// [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection) -// = 0, [6:0]=SW assisted I2C ID -// [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use -// = 2, HW engine for Multimedia use -// = 3-7 Reserved for future I2C engines -// [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C - -typedef struct _ATOM_I2C_ID_CONFIG -{ -#if ATOM_BIG_ENDIAN - UCHAR bfHW_Capable:1; - UCHAR bfHW_EngineID:3; - UCHAR bfI2C_LineMux:4; -#else - UCHAR bfI2C_LineMux:4; - UCHAR bfHW_EngineID:3; - UCHAR bfHW_Capable:1; -#endif -}ATOM_I2C_ID_CONFIG; - -typedef union _ATOM_I2C_ID_CONFIG_ACCESS -{ - ATOM_I2C_ID_CONFIG sbfAccess; - UCHAR ucAccess; -}ATOM_I2C_ID_CONFIG_ACCESS; - - -/****************************************************************************/ -// Structure used in GPIO_I2C_InfoTable -/****************************************************************************/ -typedef struct _ATOM_GPIO_I2C_ASSIGMENT -{ - USHORT usClkMaskRegisterIndex; - USHORT usClkEnRegisterIndex; - USHORT usClkY_RegisterIndex; - USHORT usClkA_RegisterIndex; - USHORT usDataMaskRegisterIndex; - USHORT usDataEnRegisterIndex; - USHORT usDataY_RegisterIndex; - USHORT usDataA_RegisterIndex; - ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; - UCHAR ucClkMaskShift; - UCHAR ucClkEnShift; - UCHAR ucClkY_Shift; - UCHAR ucClkA_Shift; - UCHAR ucDataMaskShift; - UCHAR ucDataEnShift; - UCHAR ucDataY_Shift; - UCHAR ucDataA_Shift; - UCHAR ucReserved1; - UCHAR ucReserved2; -}ATOM_GPIO_I2C_ASSIGMENT; - -typedef struct _ATOM_GPIO_I2C_INFO -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_GPIO_I2C_ASSIGMENT asGPIO_Info[ATOM_MAX_SUPPORTED_DEVICE]; -}ATOM_GPIO_I2C_INFO; - -/****************************************************************************/ -// Common Structure used in other structures -/****************************************************************************/ - -#ifndef _H2INC - -//Please don't add or expand this bitfield structure below, this one will retire soon.! -typedef struct _ATOM_MODE_MISC_INFO -{ -#if ATOM_BIG_ENDIAN - USHORT Reserved:6; - USHORT RGB888:1; - USHORT DoubleClock:1; - USHORT Interlace:1; - USHORT CompositeSync:1; - USHORT V_ReplicationBy2:1; - USHORT H_ReplicationBy2:1; - USHORT VerticalCutOff:1; - USHORT VSyncPolarity:1; //0=Active High, 1=Active Low - USHORT HSyncPolarity:1; //0=Active High, 1=Active Low - USHORT HorizontalCutOff:1; -#else - USHORT HorizontalCutOff:1; - USHORT HSyncPolarity:1; //0=Active High, 1=Active Low - USHORT VSyncPolarity:1; //0=Active High, 1=Active Low - USHORT VerticalCutOff:1; - USHORT H_ReplicationBy2:1; - USHORT V_ReplicationBy2:1; - USHORT CompositeSync:1; - USHORT Interlace:1; - USHORT DoubleClock:1; - USHORT RGB888:1; - USHORT Reserved:6; -#endif -}ATOM_MODE_MISC_INFO; - -typedef union _ATOM_MODE_MISC_INFO_ACCESS -{ - ATOM_MODE_MISC_INFO sbfAccess; - USHORT usAccess; -}ATOM_MODE_MISC_INFO_ACCESS; - -#else - -typedef union _ATOM_MODE_MISC_INFO_ACCESS -{ - USHORT usAccess; -}ATOM_MODE_MISC_INFO_ACCESS; - -#endif - -// usModeMiscInfo- -#define ATOM_H_CUTOFF 0x01 -#define ATOM_HSYNC_POLARITY 0x02 //0=Active High, 1=Active Low -#define ATOM_VSYNC_POLARITY 0x04 //0=Active High, 1=Active Low -#define ATOM_V_CUTOFF 0x08 -#define ATOM_H_REPLICATIONBY2 0x10 -#define ATOM_V_REPLICATIONBY2 0x20 -#define ATOM_COMPOSITESYNC 0x40 -#define ATOM_INTERLACE 0x80 -#define ATOM_DOUBLE_CLOCK_MODE 0x100 -#define ATOM_RGB888_MODE 0x200 - -//usRefreshRate- -#define ATOM_REFRESH_43 43 -#define ATOM_REFRESH_47 47 -#define ATOM_REFRESH_56 56 -#define ATOM_REFRESH_60 60 -#define ATOM_REFRESH_65 65 -#define ATOM_REFRESH_70 70 -#define ATOM_REFRESH_72 72 -#define ATOM_REFRESH_75 75 -#define ATOM_REFRESH_85 85 - -// ATOM_MODE_TIMING data are exactly the same as VESA timing data. -// Translation from EDID to ATOM_MODE_TIMING, use the following formula. -// -// VESA_HTOTAL = VESA_ACTIVE + 2* VESA_BORDER + VESA_BLANK -// = EDID_HA + EDID_HBL -// VESA_HDISP = VESA_ACTIVE = EDID_HA -// VESA_HSYNC_START = VESA_ACTIVE + VESA_BORDER + VESA_FRONT_PORCH -// = EDID_HA + EDID_HSO -// VESA_HSYNC_WIDTH = VESA_HSYNC_TIME = EDID_HSPW -// VESA_BORDER = EDID_BORDER - -/****************************************************************************/ -// Structure used in SetCRTC_UsingDTDTimingTable -/****************************************************************************/ -typedef struct _SET_CRTC_USING_DTD_TIMING_PARAMETERS -{ - USHORT usH_Size; - USHORT usH_Blanking_Time; - USHORT usV_Size; - USHORT usV_Blanking_Time; - USHORT usH_SyncOffset; - USHORT usH_SyncWidth; - USHORT usV_SyncOffset; - USHORT usV_SyncWidth; - ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; - UCHAR ucH_Border; // From DFP EDID - UCHAR ucV_Border; - UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 - UCHAR ucPadding[3]; -}SET_CRTC_USING_DTD_TIMING_PARAMETERS; - -/****************************************************************************/ -// Structure used in SetCRTC_TimingTable -/****************************************************************************/ -typedef struct _SET_CRTC_TIMING_PARAMETERS -{ - USHORT usH_Total; // horizontal total - USHORT usH_Disp; // horizontal display - USHORT usH_SyncStart; // horozontal Sync start - USHORT usH_SyncWidth; // horizontal Sync width - USHORT usV_Total; // vertical total - USHORT usV_Disp; // vertical display - USHORT usV_SyncStart; // vertical Sync start - USHORT usV_SyncWidth; // vertical Sync width - ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; - UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 - UCHAR ucOverscanRight; // right - UCHAR ucOverscanLeft; // left - UCHAR ucOverscanBottom; // bottom - UCHAR ucOverscanTop; // top - UCHAR ucReserved; -}SET_CRTC_TIMING_PARAMETERS; -#define SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION SET_CRTC_TIMING_PARAMETERS - -/****************************************************************************/ -// Structure used in StandardVESA_TimingTable -// AnalogTV_InfoTable -// ComponentVideoInfoTable -/****************************************************************************/ -typedef struct _ATOM_MODE_TIMING -{ - USHORT usCRTC_H_Total; - USHORT usCRTC_H_Disp; - USHORT usCRTC_H_SyncStart; - USHORT usCRTC_H_SyncWidth; - USHORT usCRTC_V_Total; - USHORT usCRTC_V_Disp; - USHORT usCRTC_V_SyncStart; - USHORT usCRTC_V_SyncWidth; - USHORT usPixelClock; //in 10Khz unit - ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; - USHORT usCRTC_OverscanRight; - USHORT usCRTC_OverscanLeft; - USHORT usCRTC_OverscanBottom; - USHORT usCRTC_OverscanTop; - USHORT usReserve; - UCHAR ucInternalModeNumber; - UCHAR ucRefreshRate; -}ATOM_MODE_TIMING; - -typedef struct _ATOM_DTD_FORMAT -{ - USHORT usPixClk; - USHORT usHActive; - USHORT usHBlanking_Time; - USHORT usVActive; - USHORT usVBlanking_Time; - USHORT usHSyncOffset; - USHORT usHSyncWidth; - USHORT usVSyncOffset; - USHORT usVSyncWidth; - USHORT usImageHSize; - USHORT usImageVSize; - UCHAR ucHBorder; - UCHAR ucVBorder; - ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; - UCHAR ucInternalModeNumber; - UCHAR ucRefreshRate; -}ATOM_DTD_FORMAT; - -/****************************************************************************/ -// Structure used in LVDS_InfoTable -// * Need a document to describe this table -/****************************************************************************/ -#define SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 -#define SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 -#define SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 -#define SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 - -//ucTableFormatRevision=1 -//ucTableContentRevision=1 -typedef struct _ATOM_LVDS_INFO -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_DTD_FORMAT sLCDTiming; - USHORT usModePatchTableOffset; - USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. - USHORT usOffDelayInMs; - UCHAR ucPowerSequenceDigOntoDEin10Ms; - UCHAR ucPowerSequenceDEtoBLOnin10Ms; - UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} - // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} - // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} - // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} - UCHAR ucPanelDefaultRefreshRate; - UCHAR ucPanelIdentification; - UCHAR ucSS_Id; -}ATOM_LVDS_INFO; - -//ucTableFormatRevision=1 -//ucTableContentRevision=2 -typedef struct _ATOM_LVDS_INFO_V12 -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_DTD_FORMAT sLCDTiming; - USHORT usExtInfoTableOffset; - USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. - USHORT usOffDelayInMs; - UCHAR ucPowerSequenceDigOntoDEin10Ms; - UCHAR ucPowerSequenceDEtoBLOnin10Ms; - UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} - // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} - // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} - // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} - UCHAR ucPanelDefaultRefreshRate; - UCHAR ucPanelIdentification; - UCHAR ucSS_Id; - USHORT usLCDVenderID; - USHORT usLCDProductID; - UCHAR ucLCDPanel_SpecialHandlingCap; - UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable - UCHAR ucReserved[2]; -}ATOM_LVDS_INFO_V12; - -//Definitions for ucLCDPanel_SpecialHandlingCap: - -//Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. -//Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL -#define LCDPANEL_CAP_READ_EDID 0x1 - -//If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together -//with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static -//refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12 -#define LCDPANEL_CAP_DRR_SUPPORTED 0x2 - -//Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP. -#define LCDPANEL_CAP_eDP 0x4 - - -//Color Bit Depth definition in EDID V1.4 @BYTE 14h -//Bit 6 5 4 - // 0 0 0 - Color bit depth is undefined - // 0 0 1 - 6 Bits per Primary Color - // 0 1 0 - 8 Bits per Primary Color - // 0 1 1 - 10 Bits per Primary Color - // 1 0 0 - 12 Bits per Primary Color - // 1 0 1 - 14 Bits per Primary Color - // 1 1 0 - 16 Bits per Primary Color - // 1 1 1 - Reserved - -#define PANEL_COLOR_BIT_DEPTH_MASK 0x70 - -// Bit7:{=0:Random Dithering disabled;1 Random Dithering enabled} -#define PANEL_RANDOM_DITHER 0x80 -#define PANEL_RANDOM_DITHER_MASK 0x80 - - -#define ATOM_LVDS_INFO_LAST ATOM_LVDS_INFO_V12 - -typedef struct _ATOM_PATCH_RECORD_MODE -{ - UCHAR ucRecordType; - USHORT usHDisp; - USHORT usVDisp; -}ATOM_PATCH_RECORD_MODE; - -typedef struct _ATOM_LCD_RTS_RECORD -{ - UCHAR ucRecordType; - UCHAR ucRTSValue; -}ATOM_LCD_RTS_RECORD; - -//!! If the record below exits, it shoud always be the first record for easy use in command table!!! -// The record below is only used when LVDS_Info is present. From ATOM_LVDS_INFO_V12, use ucLCDPanel_SpecialHandlingCap instead. -typedef struct _ATOM_LCD_MODE_CONTROL_CAP -{ - UCHAR ucRecordType; - USHORT usLCDCap; -}ATOM_LCD_MODE_CONTROL_CAP; - -#define LCD_MODE_CAP_BL_OFF 1 -#define LCD_MODE_CAP_CRTC_OFF 2 -#define LCD_MODE_CAP_PANEL_OFF 4 - -typedef struct _ATOM_FAKE_EDID_PATCH_RECORD -{ - UCHAR ucRecordType; - UCHAR ucFakeEDIDLength; - UCHAR ucFakeEDIDString[1]; // This actually has ucFakeEdidLength elements. -} ATOM_FAKE_EDID_PATCH_RECORD; - -typedef struct _ATOM_PANEL_RESOLUTION_PATCH_RECORD -{ - UCHAR ucRecordType; - USHORT usHSize; - USHORT usVSize; -}ATOM_PANEL_RESOLUTION_PATCH_RECORD; - -#define LCD_MODE_PATCH_RECORD_MODE_TYPE 1 -#define LCD_RTS_RECORD_TYPE 2 -#define LCD_CAP_RECORD_TYPE 3 -#define LCD_FAKE_EDID_PATCH_RECORD_TYPE 4 -#define LCD_PANEL_RESOLUTION_RECORD_TYPE 5 -#define ATOM_RECORD_END_TYPE 0xFF - -/****************************Spread Spectrum Info Table Definitions **********************/ - -//ucTableFormatRevision=1 -//ucTableContentRevision=2 -typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT -{ - USHORT usSpreadSpectrumPercentage; - UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Bit2=1: PCIE REFCLK SS =0 iternal PPLL SS Others:TBD - UCHAR ucSS_Step; - UCHAR ucSS_Delay; - UCHAR ucSS_Id; - UCHAR ucRecommendedRef_Div; - UCHAR ucSS_Range; //it was reserved for V11 -}ATOM_SPREAD_SPECTRUM_ASSIGNMENT; - -#define ATOM_MAX_SS_ENTRY 16 -#define ATOM_DP_SS_ID1 0x0f1 // SS ID for internal DP stream at 2.7Ghz. if ATOM_DP_SS_ID2 does not exist in SS_InfoTable, it is used for internal DP stream at 1.62Ghz as well. -#define ATOM_DP_SS_ID2 0x0f2 // SS ID for internal DP stream at 1.62Ghz, if it exists in SS_InfoTable. -#define ATOM_LVLINK_2700MHz_SS_ID 0x0f3 // SS ID for LV link translator chip at 2.7Ghz -#define ATOM_LVLINK_1620MHz_SS_ID 0x0f4 // SS ID for LV link translator chip at 1.62Ghz - - -#define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000 -#define ATOM_SS_DOWN_SPREAD_MODE 0x00000000 -#define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001 -#define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001 -#define ATOM_INTERNAL_SS_MASK 0x00000000 -#define ATOM_EXTERNAL_SS_MASK 0x00000002 -#define EXEC_SS_STEP_SIZE_SHIFT 2 -#define EXEC_SS_DELAY_SHIFT 4 -#define ACTIVEDATA_TO_BLON_DELAY_SHIFT 4 - -typedef struct _ATOM_SPREAD_SPECTRUM_INFO -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_SPREAD_SPECTRUM_ASSIGNMENT asSS_Info[ATOM_MAX_SS_ENTRY]; -}ATOM_SPREAD_SPECTRUM_INFO; - -/****************************************************************************/ -// Structure used in AnalogTV_InfoTable (Top level) -/****************************************************************************/ -//ucTVBootUpDefaultStd definiton: - -//ATOM_TV_NTSC 1 -//ATOM_TV_NTSCJ 2 -//ATOM_TV_PAL 3 -//ATOM_TV_PALM 4 -//ATOM_TV_PALCN 5 -//ATOM_TV_PALN 6 -//ATOM_TV_PAL60 7 -//ATOM_TV_SECAM 8 - -//ucTVSupportedStd definition: -#define NTSC_SUPPORT 0x1 -#define NTSCJ_SUPPORT 0x2 - -#define PAL_SUPPORT 0x4 -#define PALM_SUPPORT 0x8 -#define PALCN_SUPPORT 0x10 -#define PALN_SUPPORT 0x20 -#define PAL60_SUPPORT 0x40 -#define SECAM_SUPPORT 0x80 - -#define MAX_SUPPORTED_TV_TIMING 2 - -typedef struct _ATOM_ANALOG_TV_INFO -{ - ATOM_COMMON_TABLE_HEADER sHeader; - UCHAR ucTV_SupportedStandard; - UCHAR ucTV_BootUpDefaultStandard; - UCHAR ucExt_TV_ASIC_ID; - UCHAR ucExt_TV_ASIC_SlaveAddr; - /*ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING];*/ - ATOM_MODE_TIMING aModeTimings[MAX_SUPPORTED_TV_TIMING]; -}ATOM_ANALOG_TV_INFO; - -#define MAX_SUPPORTED_TV_TIMING_V1_2 3 - -typedef struct _ATOM_ANALOG_TV_INFO_V1_2 -{ - ATOM_COMMON_TABLE_HEADER sHeader; - UCHAR ucTV_SupportedStandard; - UCHAR ucTV_BootUpDefaultStandard; - UCHAR ucExt_TV_ASIC_ID; - UCHAR ucExt_TV_ASIC_SlaveAddr; - ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING_V1_2]; -}ATOM_ANALOG_TV_INFO_V1_2; - -typedef struct _ATOM_DPCD_INFO -{ - UCHAR ucRevisionNumber; //10h : Revision 1.0; 11h : Revision 1.1 - UCHAR ucMaxLinkRate; //06h : 1.62Gbps per lane; 0Ah = 2.7Gbps per lane - UCHAR ucMaxLane; //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP - UCHAR ucMaxDownSpread; //Bit0 = 0: No Down spread; Bit0 = 1: 0.5% (Subject to change according to DP spec) -}ATOM_DPCD_INFO; - -#define ATOM_DPCD_MAX_LANE_MASK 0x1F - -/**************************************************************************/ -// VRAM usage and their defintions - -// One chunk of VRAM used by Bios are for HWICON surfaces,EDID data. -// Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below. -// All the addresses below are the offsets from the frame buffer start.They all MUST be Dword aligned! -// To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR -// To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX - -#ifndef VESA_MEMORY_IN_64K_BLOCK -#define VESA_MEMORY_IN_64K_BLOCK 0x100 //256*64K=16Mb (Max. VESA memory is 16Mb!) -#endif - -#define ATOM_EDID_RAW_DATASIZE 256 //In Bytes -#define ATOM_HWICON_SURFACE_SIZE 4096 //In Bytes -#define ATOM_HWICON_INFOTABLE_SIZE 32 -#define MAX_DTD_MODE_IN_VRAM 6 -#define ATOM_DTD_MODE_SUPPORT_TBL_SIZE (MAX_DTD_MODE_IN_VRAM*28) //28= (SIZEOF ATOM_DTD_FORMAT) -#define ATOM_STD_MODE_SUPPORT_TBL_SIZE 32*8 //32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT) -#define DFP_ENCODER_TYPE_OFFSET 0x80 -#define DP_ENCODER_LANE_NUM_OFFSET 0x84 -#define DP_ENCODER_LINK_RATE_OFFSET 0x88 - -#define ATOM_HWICON1_SURFACE_ADDR 0 -#define ATOM_HWICON2_SURFACE_ADDR (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) -#define ATOM_HWICON_INFOTABLE_ADDR (ATOM_HWICON2_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) -#define ATOM_CRT1_EDID_ADDR (ATOM_HWICON_INFOTABLE_ADDR + ATOM_HWICON_INFOTABLE_SIZE) -#define ATOM_CRT1_DTD_MODE_TBL_ADDR (ATOM_CRT1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) -#define ATOM_CRT1_STD_MODE_TBL_ADDR (ATOM_CRT1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) - -#define ATOM_LCD1_EDID_ADDR (ATOM_CRT1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) -#define ATOM_LCD1_DTD_MODE_TBL_ADDR (ATOM_LCD1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) -#define ATOM_LCD1_STD_MODE_TBL_ADDR (ATOM_LCD1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) - -#define ATOM_TV1_DTD_MODE_TBL_ADDR (ATOM_LCD1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) - -#define ATOM_DFP1_EDID_ADDR (ATOM_TV1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) -#define ATOM_DFP1_DTD_MODE_TBL_ADDR (ATOM_DFP1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) -#define ATOM_DFP1_STD_MODE_TBL_ADDR (ATOM_DFP1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) - -#define ATOM_CRT2_EDID_ADDR (ATOM_DFP1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) -#define ATOM_CRT2_DTD_MODE_TBL_ADDR (ATOM_CRT2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) -#define ATOM_CRT2_STD_MODE_TBL_ADDR (ATOM_CRT2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) - -#define ATOM_LCD2_EDID_ADDR (ATOM_CRT2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) -#define ATOM_LCD2_DTD_MODE_TBL_ADDR (ATOM_LCD2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) -#define ATOM_LCD2_STD_MODE_TBL_ADDR (ATOM_LCD2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) - -#define ATOM_DFP6_EDID_ADDR (ATOM_LCD2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) -#define ATOM_DFP6_DTD_MODE_TBL_ADDR (ATOM_DFP6_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) -#define ATOM_DFP6_STD_MODE_TBL_ADDR (ATOM_DFP6_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) - -#define ATOM_DFP2_EDID_ADDR (ATOM_DFP6_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) -#define ATOM_DFP2_DTD_MODE_TBL_ADDR (ATOM_DFP2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) -#define ATOM_DFP2_STD_MODE_TBL_ADDR (ATOM_DFP2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) - -#define ATOM_CV_EDID_ADDR (ATOM_DFP2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) -#define ATOM_CV_DTD_MODE_TBL_ADDR (ATOM_CV_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) -#define ATOM_CV_STD_MODE_TBL_ADDR (ATOM_CV_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) - -#define ATOM_DFP3_EDID_ADDR (ATOM_CV_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) -#define ATOM_DFP3_DTD_MODE_TBL_ADDR (ATOM_DFP3_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) -#define ATOM_DFP3_STD_MODE_TBL_ADDR (ATOM_DFP3_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) - -#define ATOM_DFP4_EDID_ADDR (ATOM_DFP3_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) -#define ATOM_DFP4_DTD_MODE_TBL_ADDR (ATOM_DFP4_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) -#define ATOM_DFP4_STD_MODE_TBL_ADDR (ATOM_DFP4_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) - -#define ATOM_DFP5_EDID_ADDR (ATOM_DFP4_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) -#define ATOM_DFP5_DTD_MODE_TBL_ADDR (ATOM_DFP5_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) -#define ATOM_DFP5_STD_MODE_TBL_ADDR (ATOM_DFP5_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) - -#define ATOM_DP_TRAINING_TBL_ADDR (ATOM_DFP5_STD_MODE_TBL_ADDR+ATOM_STD_MODE_SUPPORT_TBL_SIZE) - -#define ATOM_STACK_STORAGE_START (ATOM_DP_TRAINING_TBL_ADDR+256) -#define ATOM_STACK_STORAGE_END ATOM_STACK_STORAGE_START+512 - -//The size below is in Kb! -#define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC) - -#define ATOM_VRAM_OPERATION_FLAGS_MASK 0xC0000000L -#define ATOM_VRAM_OPERATION_FLAGS_SHIFT 30 -#define ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION 0x1 -#define ATOM_VRAM_BLOCK_NEEDS_RESERVATION 0x0 - -/***********************************************************************************/ -// Structure used in VRAM_UsageByFirmwareTable -// Note1: This table is filled by SetBiosReservationStartInFB in CoreCommSubs.asm -// at running time. -// note2: From RV770, the memory is more than 32bit addressable, so we will change -// ucTableFormatRevision=1,ucTableContentRevision=4, the strcuture remains -// exactly same as 1.1 and 1.2 (1.3 is never in use), but ulStartAddrUsedByFirmware -// (in offset to start of memory address) is KB aligned instead of byte aligend. -/***********************************************************************************/ -// Note3: -/* If we change usReserved to "usFBUsedbyDrvInKB", then to VBIOS this usFBUsedbyDrvInKB is a predefined, unchanged constant across VGA or non VGA adapter, -for CAIL, The size of FB access area is known, only thing missing is the Offset of FB Access area, so we can have: - -If (ulStartAddrUsedByFirmware!=0) -FBAccessAreaOffset= ulStartAddrUsedByFirmware - usFBUsedbyDrvInKB; -Reserved area has been claimed by VBIOS including this FB access area; CAIL doesn't need to reserve any extra area for this purpose -else //Non VGA case - if (FB_Size<=2Gb) - FBAccessAreaOffset= FB_Size - usFBUsedbyDrvInKB; - else - FBAccessAreaOffset= Aper_Size - usFBUsedbyDrvInKB - -CAIL needs to claim an reserved area defined by FBAccessAreaOffset and usFBUsedbyDrvInKB in non VGA case.*/ - -#define ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO 1 - -typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO -{ - ULONG ulStartAddrUsedByFirmware; - USHORT usFirmwareUseInKb; - USHORT usReserved; -}ATOM_FIRMWARE_VRAM_RESERVE_INFO; - -typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_FIRMWARE_VRAM_RESERVE_INFO asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO]; -}ATOM_VRAM_USAGE_BY_FIRMWARE; - -// change verion to 1.5, when allow driver to allocate the vram area for command table access. -typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 -{ - ULONG ulStartAddrUsedByFirmware; - USHORT usFirmwareUseInKb; - USHORT usFBUsedByDrvInKb; -}ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5; - -typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5 -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO]; -}ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5; - -/****************************************************************************/ -// Structure used in GPIO_Pin_LUTTable -/****************************************************************************/ -typedef struct _ATOM_GPIO_PIN_ASSIGNMENT -{ - USHORT usGpioPin_AIndex; - UCHAR ucGpioPinBitShift; - UCHAR ucGPIO_ID; -}ATOM_GPIO_PIN_ASSIGNMENT; - -typedef struct _ATOM_GPIO_PIN_LUT -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_GPIO_PIN_ASSIGNMENT asGPIO_Pin[1]; -}ATOM_GPIO_PIN_LUT; - -/****************************************************************************/ -// Structure used in ComponentVideoInfoTable -/****************************************************************************/ -#define GPIO_PIN_ACTIVE_HIGH 0x1 - -#define MAX_SUPPORTED_CV_STANDARDS 5 - -// definitions for ATOM_D_INFO.ucSettings -#define ATOM_GPIO_SETTINGS_BITSHIFT_MASK 0x1F // [4:0] -#define ATOM_GPIO_SETTINGS_RESERVED_MASK 0x60 // [6:5] = must be zeroed out -#define ATOM_GPIO_SETTINGS_ACTIVE_MASK 0x80 // [7] - -typedef struct _ATOM_GPIO_INFO -{ - USHORT usAOffset; - UCHAR ucSettings; - UCHAR ucReserved; -}ATOM_GPIO_INFO; - -// definitions for ATOM_COMPONENT_VIDEO_INFO.ucMiscInfo (bit vector) -#define ATOM_CV_RESTRICT_FORMAT_SELECTION 0x2 - -// definitions for ATOM_COMPONENT_VIDEO_INFO.uc480i/uc480p/uc720p/uc1080i -#define ATOM_GPIO_DEFAULT_MODE_EN 0x80 //[7]; -#define ATOM_GPIO_SETTING_PERMODE_MASK 0x7F //[6:0] - -// definitions for ATOM_COMPONENT_VIDEO_INFO.ucLetterBoxMode -//Line 3 out put 5V. -#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A 0x01 //represent gpio 3 state for 16:9 -#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B 0x02 //represent gpio 4 state for 16:9 -#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT 0x0 - -//Line 3 out put 2.2V -#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A 0x04 //represent gpio 3 state for 4:3 Letter box -#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B 0x08 //represent gpio 4 state for 4:3 Letter box -#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT 0x2 - -//Line 3 out put 0V -#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A 0x10 //represent gpio 3 state for 4:3 -#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B 0x20 //represent gpio 4 state for 4:3 -#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT 0x4 - -#define ATOM_CV_LINE3_ASPECTRATIO_MASK 0x3F // bit [5:0] - -#define ATOM_CV_LINE3_ASPECTRATIO_EXIST 0x80 //bit 7 - -//GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks. -#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A 3 //bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. -#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B 4 //bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. - - -typedef struct _ATOM_COMPONENT_VIDEO_INFO -{ - ATOM_COMMON_TABLE_HEADER sHeader; - USHORT usMask_PinRegisterIndex; - USHORT usEN_PinRegisterIndex; - USHORT usY_PinRegisterIndex; - USHORT usA_PinRegisterIndex; - UCHAR ucBitShift; - UCHAR ucPinActiveState; //ucPinActiveState: Bit0=1 active high, =0 active low - ATOM_DTD_FORMAT sReserved; // must be zeroed out - UCHAR ucMiscInfo; - UCHAR uc480i; - UCHAR uc480p; - UCHAR uc720p; - UCHAR uc1080i; - UCHAR ucLetterBoxMode; - UCHAR ucReserved[3]; - UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector - ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; - ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; -}ATOM_COMPONENT_VIDEO_INFO; - -//ucTableFormatRevision=2 -//ucTableContentRevision=1 -typedef struct _ATOM_COMPONENT_VIDEO_INFO_V21 -{ - ATOM_COMMON_TABLE_HEADER sHeader; - UCHAR ucMiscInfo; - UCHAR uc480i; - UCHAR uc480p; - UCHAR uc720p; - UCHAR uc1080i; - UCHAR ucReserved; - UCHAR ucLetterBoxMode; - UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector - ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; - ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; -}ATOM_COMPONENT_VIDEO_INFO_V21; - -#define ATOM_COMPONENT_VIDEO_INFO_LAST ATOM_COMPONENT_VIDEO_INFO_V21 - -/****************************************************************************/ -// Structure used in object_InfoTable -/****************************************************************************/ -typedef struct _ATOM_OBJECT_HEADER -{ - ATOM_COMMON_TABLE_HEADER sHeader; - USHORT usDeviceSupport; - USHORT usConnectorObjectTableOffset; - USHORT usRouterObjectTableOffset; - USHORT usEncoderObjectTableOffset; - USHORT usProtectionObjectTableOffset; //only available when Protection block is independent. - USHORT usDisplayPathTableOffset; -}ATOM_OBJECT_HEADER; - -typedef struct _ATOM_OBJECT_HEADER_V3 -{ - ATOM_COMMON_TABLE_HEADER sHeader; - USHORT usDeviceSupport; - USHORT usConnectorObjectTableOffset; - USHORT usRouterObjectTableOffset; - USHORT usEncoderObjectTableOffset; - USHORT usProtectionObjectTableOffset; //only available when Protection block is independent. - USHORT usDisplayPathTableOffset; - USHORT usMiscObjectTableOffset; -}ATOM_OBJECT_HEADER_V3; - -typedef struct _ATOM_DISPLAY_OBJECT_PATH -{ - USHORT usDeviceTag; //supported device - USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH - USHORT usConnObjectId; //Connector Object ID - USHORT usGPUObjectId; //GPU ID - USHORT usGraphicObjIds[1]; //1st Encoder Obj source from GPU to last Graphic Obj destinate to connector. -}ATOM_DISPLAY_OBJECT_PATH; - -typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE -{ - UCHAR ucNumOfDispPath; - UCHAR ucVersion; - UCHAR ucPadding[2]; - ATOM_DISPLAY_OBJECT_PATH asDispPath[1]; -}ATOM_DISPLAY_OBJECT_PATH_TABLE; - - -typedef struct _ATOM_OBJECT //each object has this structure -{ - USHORT usObjectID; - USHORT usSrcDstTableOffset; - USHORT usRecordOffset; //this pointing to a bunch of records defined below - USHORT usReserved; -}ATOM_OBJECT; - -typedef struct _ATOM_OBJECT_TABLE //Above 4 object table offset pointing to a bunch of objects all have this structure -{ - UCHAR ucNumberOfObjects; - UCHAR ucPadding[3]; - ATOM_OBJECT asObjects[1]; -}ATOM_OBJECT_TABLE; - -typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT //usSrcDstTableOffset pointing to this structure -{ - UCHAR ucNumberOfSrc; - USHORT usSrcObjectID[1]; - UCHAR ucNumberOfDst; - USHORT usDstObjectID[1]; -}ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT; - - -//Two definitions below are for OPM on MXM module designs - -#define EXT_HPDPIN_LUTINDEX_0 0 -#define EXT_HPDPIN_LUTINDEX_1 1 -#define EXT_HPDPIN_LUTINDEX_2 2 -#define EXT_HPDPIN_LUTINDEX_3 3 -#define EXT_HPDPIN_LUTINDEX_4 4 -#define EXT_HPDPIN_LUTINDEX_5 5 -#define EXT_HPDPIN_LUTINDEX_6 6 -#define EXT_HPDPIN_LUTINDEX_7 7 -#define MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES (EXT_HPDPIN_LUTINDEX_7+1) - -#define EXT_AUXDDC_LUTINDEX_0 0 -#define EXT_AUXDDC_LUTINDEX_1 1 -#define EXT_AUXDDC_LUTINDEX_2 2 -#define EXT_AUXDDC_LUTINDEX_3 3 -#define EXT_AUXDDC_LUTINDEX_4 4 -#define EXT_AUXDDC_LUTINDEX_5 5 -#define EXT_AUXDDC_LUTINDEX_6 6 -#define EXT_AUXDDC_LUTINDEX_7 7 -#define MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES (EXT_AUXDDC_LUTINDEX_7+1) - -typedef struct _EXT_DISPLAY_PATH -{ - USHORT usDeviceTag; //A bit vector to show what devices are supported - USHORT usDeviceACPIEnum; //16bit device ACPI id. - USHORT usDeviceConnector; //A physical connector for displays to plug in, using object connector definitions - UCHAR ucExtAUXDDCLutIndex; //An index into external AUX/DDC channel LUT - UCHAR ucExtHPDPINLutIndex; //An index into external HPD pin LUT - USHORT usExtEncoderObjId; //external encoder object id - USHORT usReserved[3]; -}EXT_DISPLAY_PATH; - -#define NUMBER_OF_UCHAR_FOR_GUID 16 -#define MAX_NUMBER_OF_EXT_DISPLAY_PATH 7 - -typedef struct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO -{ - ATOM_COMMON_TABLE_HEADER sHeader; - UCHAR ucGuid [NUMBER_OF_UCHAR_FOR_GUID]; // a GUID is a 16 byte long string - EXT_DISPLAY_PATH sPath[MAX_NUMBER_OF_EXT_DISPLAY_PATH]; // total of fixed 7 entries. - UCHAR ucChecksum; // a simple Checksum of the sum of whole structure equal to 0x0. - UCHAR Reserved [7]; // for potential expansion -}ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO; - -//Related definitions, all records are differnt but they have a commond header -typedef struct _ATOM_COMMON_RECORD_HEADER -{ - UCHAR ucRecordType; //An emun to indicate the record type - UCHAR ucRecordSize; //The size of the whole record in byte -}ATOM_COMMON_RECORD_HEADER; - - -#define ATOM_I2C_RECORD_TYPE 1 -#define ATOM_HPD_INT_RECORD_TYPE 2 -#define ATOM_OUTPUT_PROTECTION_RECORD_TYPE 3 -#define ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE 4 -#define ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD_TYPE 5 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE -#define ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE 6 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE -#define ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE 7 -#define ATOM_JTAG_RECORD_TYPE 8 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE -#define ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE 9 -#define ATOM_ENCODER_DVO_CF_RECORD_TYPE 10 -#define ATOM_CONNECTOR_CF_RECORD_TYPE 11 -#define ATOM_CONNECTOR_HARDCODE_DTD_RECORD_TYPE 12 -#define ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE 13 -#define ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE 14 -#define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE 15 -#define ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 16 //This is for the case when connectors are not known to object table -#define ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 17 //This is for the case when connectors are not known to object table -#define ATOM_OBJECT_LINK_RECORD_TYPE 18 //Once this record is present under one object, it indicats the oobject is linked to another obj described by the record -#define ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE 19 - - -//Must be updated when new record type is added,equal to that record definition! -#define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE - -typedef struct _ATOM_I2C_RECORD -{ - ATOM_COMMON_RECORD_HEADER sheader; - ATOM_I2C_ID_CONFIG sucI2cId; - UCHAR ucI2CAddr; //The slave address, it's 0 when the record is attached to connector for DDC -}ATOM_I2C_RECORD; - -typedef struct _ATOM_HPD_INT_RECORD -{ - ATOM_COMMON_RECORD_HEADER sheader; - UCHAR ucHPDIntGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info - UCHAR ucPlugged_PinState; -}ATOM_HPD_INT_RECORD; - - -typedef struct _ATOM_OUTPUT_PROTECTION_RECORD -{ - ATOM_COMMON_RECORD_HEADER sheader; - UCHAR ucProtectionFlag; - UCHAR ucReserved; -}ATOM_OUTPUT_PROTECTION_RECORD; - -typedef struct _ATOM_CONNECTOR_DEVICE_TAG -{ - ULONG ulACPIDeviceEnum; //Reserved for now - USHORT usDeviceID; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT" - USHORT usPadding; -}ATOM_CONNECTOR_DEVICE_TAG; - -typedef struct _ATOM_CONNECTOR_DEVICE_TAG_RECORD -{ - ATOM_COMMON_RECORD_HEADER sheader; - UCHAR ucNumberOfDevice; - UCHAR ucReserved; - ATOM_CONNECTOR_DEVICE_TAG asDeviceTag[1]; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT", 1 is only for allocation -}ATOM_CONNECTOR_DEVICE_TAG_RECORD; - - -typedef struct _ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD -{ - ATOM_COMMON_RECORD_HEADER sheader; - UCHAR ucConfigGPIOID; - UCHAR ucConfigGPIOState; //Set to 1 when it's active high to enable external flow in - UCHAR ucFlowinGPIPID; - UCHAR ucExtInGPIPID; -}ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD; - -typedef struct _ATOM_ENCODER_FPGA_CONTROL_RECORD -{ - ATOM_COMMON_RECORD_HEADER sheader; - UCHAR ucCTL1GPIO_ID; - UCHAR ucCTL1GPIOState; //Set to 1 when it's active high - UCHAR ucCTL2GPIO_ID; - UCHAR ucCTL2GPIOState; //Set to 1 when it's active high - UCHAR ucCTL3GPIO_ID; - UCHAR ucCTL3GPIOState; //Set to 1 when it's active high - UCHAR ucCTLFPGA_IN_ID; - UCHAR ucPadding[3]; -}ATOM_ENCODER_FPGA_CONTROL_RECORD; - -typedef struct _ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD -{ - ATOM_COMMON_RECORD_HEADER sheader; - UCHAR ucGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info - UCHAR ucTVActiveState; //Indicating when the pin==0 or 1 when TV is connected -}ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD; - -typedef struct _ATOM_JTAG_RECORD -{ - ATOM_COMMON_RECORD_HEADER sheader; - UCHAR ucTMSGPIO_ID; - UCHAR ucTMSGPIOState; //Set to 1 when it's active high - UCHAR ucTCKGPIO_ID; - UCHAR ucTCKGPIOState; //Set to 1 when it's active high - UCHAR ucTDOGPIO_ID; - UCHAR ucTDOGPIOState; //Set to 1 when it's active high - UCHAR ucTDIGPIO_ID; - UCHAR ucTDIGPIOState; //Set to 1 when it's active high - UCHAR ucPadding[2]; -}ATOM_JTAG_RECORD; - - -//The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually -typedef struct _ATOM_GPIO_PIN_CONTROL_PAIR -{ - UCHAR ucGPIOID; // GPIO_ID, find the corresponding ID in GPIO_LUT table - UCHAR ucGPIO_PinState; // Pin state showing how to set-up the pin -}ATOM_GPIO_PIN_CONTROL_PAIR; - -typedef struct _ATOM_OBJECT_GPIO_CNTL_RECORD -{ - ATOM_COMMON_RECORD_HEADER sheader; - UCHAR ucFlags; // Future expnadibility - UCHAR ucNumberOfPins; // Number of GPIO pins used to control the object - ATOM_GPIO_PIN_CONTROL_PAIR asGpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins -}ATOM_OBJECT_GPIO_CNTL_RECORD; - -//Definitions for GPIO pin state -#define GPIO_PIN_TYPE_INPUT 0x00 -#define GPIO_PIN_TYPE_OUTPUT 0x10 -#define GPIO_PIN_TYPE_HW_CONTROL 0x20 - -//For GPIO_PIN_TYPE_OUTPUT the following is defined -#define GPIO_PIN_OUTPUT_STATE_MASK 0x01 -#define GPIO_PIN_OUTPUT_STATE_SHIFT 0 -#define GPIO_PIN_STATE_ACTIVE_LOW 0x0 -#define GPIO_PIN_STATE_ACTIVE_HIGH 0x1 - -// Indexes to GPIO array in GLSync record -#define ATOM_GPIO_INDEX_GLSYNC_REFCLK 0 -#define ATOM_GPIO_INDEX_GLSYNC_HSYNC 1 -#define ATOM_GPIO_INDEX_GLSYNC_VSYNC 2 -#define ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ 3 -#define ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT 4 -#define ATOM_GPIO_INDEX_GLSYNC_INTERRUPT 5 -#define ATOM_GPIO_INDEX_GLSYNC_V_RESET 6 -#define ATOM_GPIO_INDEX_GLSYNC_MAX 7 - -typedef struct _ATOM_ENCODER_DVO_CF_RECORD -{ - ATOM_COMMON_RECORD_HEADER sheader; - ULONG ulStrengthControl; // DVOA strength control for CF - UCHAR ucPadding[2]; -}ATOM_ENCODER_DVO_CF_RECORD; - -// value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle -#define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA 1 -#define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB 2 - -typedef struct _ATOM_CONNECTOR_CF_RECORD -{ - ATOM_COMMON_RECORD_HEADER sheader; - USHORT usMaxPixClk; - UCHAR ucFlowCntlGpioId; - UCHAR ucSwapCntlGpioId; - UCHAR ucConnectedDvoBundle; - UCHAR ucPadding; -}ATOM_CONNECTOR_CF_RECORD; - -typedef struct _ATOM_CONNECTOR_HARDCODE_DTD_RECORD -{ - ATOM_COMMON_RECORD_HEADER sheader; - ATOM_DTD_FORMAT asTiming; -}ATOM_CONNECTOR_HARDCODE_DTD_RECORD; - -typedef struct _ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD -{ - ATOM_COMMON_RECORD_HEADER sheader; //ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE - UCHAR ucSubConnectorType; //CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D|X_ID_DUAL_LINK_DVI_D|HDMI_TYPE_A - UCHAR ucReserved; -}ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD; - - -typedef struct _ATOM_ROUTER_DDC_PATH_SELECT_RECORD -{ - ATOM_COMMON_RECORD_HEADER sheader; - UCHAR ucMuxType; //decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: multiple state - UCHAR ucMuxControlPin; - UCHAR ucMuxState[2]; //for alligment purpose -}ATOM_ROUTER_DDC_PATH_SELECT_RECORD; - -typedef struct _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD -{ - ATOM_COMMON_RECORD_HEADER sheader; - UCHAR ucMuxType; - UCHAR ucMuxControlPin; - UCHAR ucMuxState[2]; //for alligment purpose -}ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD; - -// define ucMuxType -#define ATOM_ROUTER_MUX_PIN_STATE_MASK 0x0f -#define ATOM_ROUTER_MUX_PIN_SINGLE_STATE_COMPLEMENT 0x01 - -typedef struct _ATOM_CONNECTOR_HPDPIN_LUT_RECORD //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE -{ - ATOM_COMMON_RECORD_HEADER sheader; - UCHAR ucHPDPINMap[MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES]; //An fixed size array which maps external pins to internal GPIO_PIN_INFO table -}ATOM_CONNECTOR_HPDPIN_LUT_RECORD; - -typedef struct _ATOM_CONNECTOR_AUXDDC_LUT_RECORD //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE -{ - ATOM_COMMON_RECORD_HEADER sheader; - ATOM_I2C_ID_CONFIG ucAUXDDCMap[MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES]; //An fixed size array which maps external pins to internal DDC ID -}ATOM_CONNECTOR_AUXDDC_LUT_RECORD; - -typedef struct _ATOM_OBJECT_LINK_RECORD -{ - ATOM_COMMON_RECORD_HEADER sheader; - USHORT usObjectID; //could be connector, encorder or other object in object.h -}ATOM_OBJECT_LINK_RECORD; - -typedef struct _ATOM_CONNECTOR_REMOTE_CAP_RECORD -{ - ATOM_COMMON_RECORD_HEADER sheader; - USHORT usReserved; -}ATOM_CONNECTOR_REMOTE_CAP_RECORD; - -/****************************************************************************/ -// ASIC voltage data table -/****************************************************************************/ -typedef struct _ATOM_VOLTAGE_INFO_HEADER -{ - USHORT usVDDCBaseLevel; //In number of 50mv unit - USHORT usReserved; //For possible extension table offset - UCHAR ucNumOfVoltageEntries; - UCHAR ucBytesPerVoltageEntry; - UCHAR ucVoltageStep; //Indicating in how many mv increament is one step, 0.5mv unit - UCHAR ucDefaultVoltageEntry; - UCHAR ucVoltageControlI2cLine; - UCHAR ucVoltageControlAddress; - UCHAR ucVoltageControlOffset; -}ATOM_VOLTAGE_INFO_HEADER; - -typedef struct _ATOM_VOLTAGE_INFO -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_VOLTAGE_INFO_HEADER viHeader; - UCHAR ucVoltageEntries[64]; //64 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries*ucBytesPerVoltageEntry -}ATOM_VOLTAGE_INFO; - - -typedef struct _ATOM_VOLTAGE_FORMULA -{ - USHORT usVoltageBaseLevel; // In number of 1mv unit - USHORT usVoltageStep; // Indicating in how many mv increament is one step, 1mv unit - UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage - UCHAR ucFlag; // bit0=0 :step is 1mv =1 0.5mv - UCHAR ucBaseVID; // if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /VoltageStep - UCHAR ucReserved; - UCHAR ucVIDAdjustEntries[32]; // 32 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries -}ATOM_VOLTAGE_FORMULA; - -typedef struct _VOLTAGE_LUT_ENTRY -{ - USHORT usVoltageCode; // The Voltage ID, either GPIO or I2C code - USHORT usVoltageValue; // The corresponding Voltage Value, in mV -}VOLTAGE_LUT_ENTRY; - -typedef struct _ATOM_VOLTAGE_FORMULA_V2 -{ - UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage - UCHAR ucReserved[3]; - VOLTAGE_LUT_ENTRY asVIDAdjustEntries[32];// 32 is for allocation, the actual number of entries is in ucNumOfVoltageEntries -}ATOM_VOLTAGE_FORMULA_V2; - -typedef struct _ATOM_VOLTAGE_CONTROL -{ - UCHAR ucVoltageControlId; //Indicate it is controlled by I2C or GPIO or HW state machine - UCHAR ucVoltageControlI2cLine; - UCHAR ucVoltageControlAddress; - UCHAR ucVoltageControlOffset; - USHORT usGpioPin_AIndex; //GPIO_PAD register index - UCHAR ucGpioPinBitShift[9]; //at most 8 pin support 255 VIDs, termintate with 0xff - UCHAR ucReserved; -}ATOM_VOLTAGE_CONTROL; - -// Define ucVoltageControlId -#define VOLTAGE_CONTROLLED_BY_HW 0x00 -#define VOLTAGE_CONTROLLED_BY_I2C_MASK 0x7F -#define VOLTAGE_CONTROLLED_BY_GPIO 0x80 -#define VOLTAGE_CONTROL_ID_LM64 0x01 //I2C control, used for R5xx Core Voltage -#define VOLTAGE_CONTROL_ID_DAC 0x02 //I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI -#define VOLTAGE_CONTROL_ID_VT116xM 0x03 //I2C control, used for R6xx Core Voltage -#define VOLTAGE_CONTROL_ID_DS4402 0x04 - -typedef struct _ATOM_VOLTAGE_OBJECT -{ - UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI - UCHAR ucSize; //Size of Object - ATOM_VOLTAGE_CONTROL asControl; //describ how to control - ATOM_VOLTAGE_FORMULA asFormula; //Indicate How to convert real Voltage to VID -}ATOM_VOLTAGE_OBJECT; - -typedef struct _ATOM_VOLTAGE_OBJECT_V2 -{ - UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI - UCHAR ucSize; //Size of Object - ATOM_VOLTAGE_CONTROL asControl; //describ how to control - ATOM_VOLTAGE_FORMULA_V2 asFormula; //Indicate How to convert real Voltage to VID -}ATOM_VOLTAGE_OBJECT_V2; - -typedef struct _ATOM_VOLTAGE_OBJECT_INFO -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_VOLTAGE_OBJECT asVoltageObj[3]; //Info for Voltage control -}ATOM_VOLTAGE_OBJECT_INFO; - -typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V2 -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_VOLTAGE_OBJECT_V2 asVoltageObj[3]; //Info for Voltage control -}ATOM_VOLTAGE_OBJECT_INFO_V2; - -typedef struct _ATOM_LEAKID_VOLTAGE -{ - UCHAR ucLeakageId; - UCHAR ucReserved; - USHORT usVoltage; -}ATOM_LEAKID_VOLTAGE; - -typedef struct _ATOM_ASIC_PROFILE_VOLTAGE -{ - UCHAR ucProfileId; - UCHAR ucReserved; - USHORT usSize; - USHORT usEfuseSpareStartAddr; - USHORT usFuseIndex[8]; //from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse id, - ATOM_LEAKID_VOLTAGE asLeakVol[2]; //Leakid and relatd voltage -}ATOM_ASIC_PROFILE_VOLTAGE; - -//ucProfileId -#define ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE 1 -#define ATOM_ASIC_PROFILE_ID_EFUSE_PERFORMANCE_VOLTAGE 1 -#define ATOM_ASIC_PROFILE_ID_EFUSE_THERMAL_VOLTAGE 2 - -typedef struct _ATOM_ASIC_PROFILING_INFO -{ - ATOM_COMMON_TABLE_HEADER asHeader; - ATOM_ASIC_PROFILE_VOLTAGE asVoltage; -}ATOM_ASIC_PROFILING_INFO; - -typedef struct _ATOM_POWER_SOURCE_OBJECT -{ - UCHAR ucPwrSrcId; // Power source - UCHAR ucPwrSensorType; // GPIO, I2C or none - UCHAR ucPwrSensId; // if GPIO detect, it is GPIO id, if I2C detect, it is I2C id - UCHAR ucPwrSensSlaveAddr; // Slave address if I2C detect - UCHAR ucPwrSensRegIndex; // I2C register Index if I2C detect - UCHAR ucPwrSensRegBitMask; // detect which bit is used if I2C detect - UCHAR ucPwrSensActiveState; // high active or low active - UCHAR ucReserve[3]; // reserve - USHORT usSensPwr; // in unit of watt -}ATOM_POWER_SOURCE_OBJECT; - -typedef struct _ATOM_POWER_SOURCE_INFO -{ - ATOM_COMMON_TABLE_HEADER asHeader; - UCHAR asPwrbehave[16]; - ATOM_POWER_SOURCE_OBJECT asPwrObj[1]; -}ATOM_POWER_SOURCE_INFO; - - -//Define ucPwrSrcId -#define POWERSOURCE_PCIE_ID1 0x00 -#define POWERSOURCE_6PIN_CONNECTOR_ID1 0x01 -#define POWERSOURCE_8PIN_CONNECTOR_ID1 0x02 -#define POWERSOURCE_6PIN_CONNECTOR_ID2 0x04 -#define POWERSOURCE_8PIN_CONNECTOR_ID2 0x08 - -//define ucPwrSensorId -#define POWER_SENSOR_ALWAYS 0x00 -#define POWER_SENSOR_GPIO 0x01 -#define POWER_SENSOR_I2C 0x02 - -typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ULONG ulBootUpEngineClock; - ULONG ulDentistVCOFreq; - ULONG ulBootUpUMAClock; - ULONG ulReserved1[8]; - ULONG ulBootUpReqDisplayVector; - ULONG ulOtherDisplayMisc; - ULONG ulGPUCapInfo; - ULONG ulReserved2[3]; - ULONG ulSystemConfig; - ULONG ulCPUCapInfo; - USHORT usMaxNBVoltage; - USHORT usMinNBVoltage; - USHORT usBootUpNBVoltage; - USHORT usExtDispConnInfoOffset; - UCHAR ucHtcTmpLmt; - UCHAR ucTjOffset; - UCHAR ucMemoryType; - UCHAR ucUMAChannelNumber; - ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10]; - ULONG ulCSR_M3_ARB_CNTL_UVD[10]; - ULONG ulCSR_M3_ARB_CNTL_FS3D[10]; - ULONG ulReserved3[42]; - ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; -}ATOM_INTEGRATED_SYSTEM_INFO_V6; - -/********************************************************************************************************************** -// ATOM_INTEGRATED_SYSTEM_INFO_V6 Description -//ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. -//ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. -//ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. -//ulReserved1[8] Reserved by now, must be 0x0. -//ulBootUpReqDisplayVector VBIOS boot up display IDs -// ATOM_DEVICE_CRT1_SUPPORT 0x0001 -// ATOM_DEVICE_CRT2_SUPPORT 0x0010 -// ATOM_DEVICE_DFP1_SUPPORT 0x0008 -// ATOM_DEVICE_DFP6_SUPPORT 0x0040 -// ATOM_DEVICE_DFP2_SUPPORT 0x0080 -// ATOM_DEVICE_DFP3_SUPPORT 0x0200 -// ATOM_DEVICE_DFP4_SUPPORT 0x0400 -// ATOM_DEVICE_DFP5_SUPPORT 0x0800 -// ATOM_DEVICE_LCD1_SUPPORT 0x0002 -//ulOtherDisplayMisc Other display related flags, not defined yet. -//ulGPUCapInfo TBD -//ulReserved2[3] must be 0x0 for the reserved. -//ulSystemConfig TBD -//ulCPUCapInfo TBD -//usMaxNBVoltage High NB voltage in unit of mv, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse. -//usMinNBVoltage Low NB voltage in unit of mv, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse. -//usBootUpNBVoltage Boot up NB voltage in unit of mv. -//ucHtcTmpLmt Bit [22:16] of D24F3x64 Thermal Control (HTC) Register. -//ucTjOffset Bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed. -//ucMemoryType [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved. -//ucUMAChannelNumber System memory channel numbers. -//usExtDispConnectionInfoOffset ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO offset relative to beginning of this table. -//ulCSR_M3_ARB_CNTL_DEFAULT[10] Arrays with values for CSR M3 arbiter for default -//ulCSR_M3_ARB_CNTL_UVD[10] Arrays with values for CSR M3 arbiter for UVD playback. -//ulCSR_M3_ARB_CNTL_FS3D[10] Arrays with values for CSR M3 arbiter for Full Screen 3D applications. -**********************************************************************************************************************/ - -/**************************************************************************/ -// This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design -//Memory SS Info Table -//Define Memory Clock SS chip ID -#define ICS91719 1 -#define ICS91720 2 - -//Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol -typedef struct _ATOM_I2C_DATA_RECORD -{ - UCHAR ucNunberOfBytes; //Indicates how many bytes SW needs to write to the external ASIC for one block, besides to "Start" and "Stop" - UCHAR ucI2CData[1]; //I2C data in bytes, should be less than 16 bytes usually -}ATOM_I2C_DATA_RECORD; - - -//Define one structure to inform SW how many blocks of data writing to external SS chip via I2C protocol, in addition to other information -typedef struct _ATOM_I2C_DEVICE_SETUP_INFO -{ - ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //I2C line and HW/SW assisted cap. - UCHAR ucSSChipID; //SS chip being used - UCHAR ucSSChipSlaveAddr; //Slave Address to set up this SS chip - UCHAR ucNumOfI2CDataRecords; //number of data block - ATOM_I2C_DATA_RECORD asI2CData[1]; -}ATOM_I2C_DEVICE_SETUP_INFO; - -//========================================================================================== -typedef struct _ATOM_ASIC_MVDD_INFO -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_I2C_DEVICE_SETUP_INFO asI2CSetup[1]; -}ATOM_ASIC_MVDD_INFO; - -//========================================================================================== -#define ATOM_MCLK_SS_INFO ATOM_ASIC_MVDD_INFO - -//========================================================================================== -/**************************************************************************/ - -typedef struct _ATOM_ASIC_SS_ASSIGNMENT -{ - ULONG ulTargetClockRange; //Clock Out frequence (VCO ), in unit of 10Khz - USHORT usSpreadSpectrumPercentage; //in unit of 0.01% - USHORT usSpreadRateInKhz; //in unit of kHz, modulation freq - UCHAR ucClockIndication; //Indicate which clock source needs SS - UCHAR ucSpreadSpectrumMode; //Bit1=0 Down Spread,=1 Center Spread. - UCHAR ucReserved[2]; -}ATOM_ASIC_SS_ASSIGNMENT; - -//Define ucClockIndication, SW uses the IDs below to search if the SS is required/enabled on a clock branch/signal type. -//SS is not required or enabled if a match is not found. -#define ASIC_INTERNAL_MEMORY_SS 1 -#define ASIC_INTERNAL_ENGINE_SS 2 -#define ASIC_INTERNAL_UVD_SS 3 -#define ASIC_INTERNAL_SS_ON_TMDS 4 -#define ASIC_INTERNAL_SS_ON_HDMI 5 -#define ASIC_INTERNAL_SS_ON_LVDS 6 -#define ASIC_INTERNAL_SS_ON_DP 7 -#define ASIC_INTERNAL_SS_ON_DCPLL 8 - -typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V2 -{ - ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz - //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 ) - USHORT usSpreadSpectrumPercentage; //in unit of 0.01% - USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq - UCHAR ucClockIndication; //Indicate which clock source needs SS - UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS - UCHAR ucReserved[2]; -}ATOM_ASIC_SS_ASSIGNMENT_V2; - -//ucSpreadSpectrumMode -//#define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000 -//#define ATOM_SS_DOWN_SPREAD_MODE 0x00000000 -//#define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001 -//#define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001 -//#define ATOM_INTERNAL_SS_MASK 0x00000000 -//#define ATOM_EXTERNAL_SS_MASK 0x00000002 - -typedef struct _ATOM_ASIC_INTERNAL_SS_INFO -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_ASIC_SS_ASSIGNMENT asSpreadSpectrum[4]; -}ATOM_ASIC_INTERNAL_SS_INFO; - -typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_ASIC_SS_ASSIGNMENT_V2 asSpreadSpectrum[1]; //this is point only. -}ATOM_ASIC_INTERNAL_SS_INFO_V2; - -typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V3 -{ - ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz - //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 ) - USHORT usSpreadSpectrumPercentage; //in unit of 0.01% - USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq - UCHAR ucClockIndication; //Indicate which clock source needs SS - UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS - UCHAR ucReserved[2]; -}ATOM_ASIC_SS_ASSIGNMENT_V3; - -typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_ASIC_SS_ASSIGNMENT_V3 asSpreadSpectrum[1]; //this is pointer only. -}ATOM_ASIC_INTERNAL_SS_INFO_V3; - - -//==============================Scratch Pad Definition Portion=============================== -#define ATOM_DEVICE_CONNECT_INFO_DEF 0 -#define ATOM_ROM_LOCATION_DEF 1 -#define ATOM_TV_STANDARD_DEF 2 -#define ATOM_ACTIVE_INFO_DEF 3 -#define ATOM_LCD_INFO_DEF 4 -#define ATOM_DOS_REQ_INFO_DEF 5 -#define ATOM_ACC_CHANGE_INFO_DEF 6 -#define ATOM_DOS_MODE_INFO_DEF 7 -#define ATOM_I2C_CHANNEL_STATUS_DEF 8 -#define ATOM_I2C_CHANNEL_STATUS1_DEF 9 - - -// BIOS_0_SCRATCH Definition -#define ATOM_S0_CRT1_MONO 0x00000001L -#define ATOM_S0_CRT1_COLOR 0x00000002L -#define ATOM_S0_CRT1_MASK (ATOM_S0_CRT1_MONO+ATOM_S0_CRT1_COLOR) - -#define ATOM_S0_TV1_COMPOSITE_A 0x00000004L -#define ATOM_S0_TV1_SVIDEO_A 0x00000008L -#define ATOM_S0_TV1_MASK_A (ATOM_S0_TV1_COMPOSITE_A+ATOM_S0_TV1_SVIDEO_A) - -#define ATOM_S0_CV_A 0x00000010L -#define ATOM_S0_CV_DIN_A 0x00000020L -#define ATOM_S0_CV_MASK_A (ATOM_S0_CV_A+ATOM_S0_CV_DIN_A) - - -#define ATOM_S0_CRT2_MONO 0x00000100L -#define ATOM_S0_CRT2_COLOR 0x00000200L -#define ATOM_S0_CRT2_MASK (ATOM_S0_CRT2_MONO+ATOM_S0_CRT2_COLOR) - -#define ATOM_S0_TV1_COMPOSITE 0x00000400L -#define ATOM_S0_TV1_SVIDEO 0x00000800L -#define ATOM_S0_TV1_SCART 0x00004000L -#define ATOM_S0_TV1_MASK (ATOM_S0_TV1_COMPOSITE+ATOM_S0_TV1_SVIDEO+ATOM_S0_TV1_SCART) - -#define ATOM_S0_CV 0x00001000L -#define ATOM_S0_CV_DIN 0x00002000L -#define ATOM_S0_CV_MASK (ATOM_S0_CV+ATOM_S0_CV_DIN) - -#define ATOM_S0_DFP1 0x00010000L -#define ATOM_S0_DFP2 0x00020000L -#define ATOM_S0_LCD1 0x00040000L -#define ATOM_S0_LCD2 0x00080000L -#define ATOM_S0_DFP6 0x00100000L -#define ATOM_S0_DFP3 0x00200000L -#define ATOM_S0_DFP4 0x00400000L -#define ATOM_S0_DFP5 0x00800000L - -#define ATOM_S0_DFP_MASK ATOM_S0_DFP1 | ATOM_S0_DFP2 | ATOM_S0_DFP3 | ATOM_S0_DFP4 | ATOM_S0_DFP5 | ATOM_S0_DFP6 - -#define ATOM_S0_FAD_REGISTER_BUG 0x02000000L // If set, indicates we are running a PCIE asic with - // the FAD/HDP reg access bug. Bit is read by DAL, this is obsolete from RV5xx - -#define ATOM_S0_THERMAL_STATE_MASK 0x1C000000L -#define ATOM_S0_THERMAL_STATE_SHIFT 26 - -#define ATOM_S0_SYSTEM_POWER_STATE_MASK 0xE0000000L -#define ATOM_S0_SYSTEM_POWER_STATE_SHIFT 29 - -#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC 1 -#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC 2 -#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3 - -//Byte aligned defintion for BIOS usage -#define ATOM_S0_CRT1_MONOb0 0x01 -#define ATOM_S0_CRT1_COLORb0 0x02 -#define ATOM_S0_CRT1_MASKb0 (ATOM_S0_CRT1_MONOb0+ATOM_S0_CRT1_COLORb0) - -#define ATOM_S0_TV1_COMPOSITEb0 0x04 -#define ATOM_S0_TV1_SVIDEOb0 0x08 -#define ATOM_S0_TV1_MASKb0 (ATOM_S0_TV1_COMPOSITEb0+ATOM_S0_TV1_SVIDEOb0) - -#define ATOM_S0_CVb0 0x10 -#define ATOM_S0_CV_DINb0 0x20 -#define ATOM_S0_CV_MASKb0 (ATOM_S0_CVb0+ATOM_S0_CV_DINb0) - -#define ATOM_S0_CRT2_MONOb1 0x01 -#define ATOM_S0_CRT2_COLORb1 0x02 -#define ATOM_S0_CRT2_MASKb1 (ATOM_S0_CRT2_MONOb1+ATOM_S0_CRT2_COLORb1) - -#define ATOM_S0_TV1_COMPOSITEb1 0x04 -#define ATOM_S0_TV1_SVIDEOb1 0x08 -#define ATOM_S0_TV1_SCARTb1 0x40 -#define ATOM_S0_TV1_MASKb1 (ATOM_S0_TV1_COMPOSITEb1+ATOM_S0_TV1_SVIDEOb1+ATOM_S0_TV1_SCARTb1) - -#define ATOM_S0_CVb1 0x10 -#define ATOM_S0_CV_DINb1 0x20 -#define ATOM_S0_CV_MASKb1 (ATOM_S0_CVb1+ATOM_S0_CV_DINb1) - -#define ATOM_S0_DFP1b2 0x01 -#define ATOM_S0_DFP2b2 0x02 -#define ATOM_S0_LCD1b2 0x04 -#define ATOM_S0_LCD2b2 0x08 -#define ATOM_S0_DFP6b2 0x10 -#define ATOM_S0_DFP3b2 0x20 -#define ATOM_S0_DFP4b2 0x40 -#define ATOM_S0_DFP5b2 0x80 - - -#define ATOM_S0_THERMAL_STATE_MASKb3 0x1C -#define ATOM_S0_THERMAL_STATE_SHIFTb3 2 - -#define ATOM_S0_SYSTEM_POWER_STATE_MASKb3 0xE0 -#define ATOM_S0_LCD1_SHIFT 18 - -// BIOS_1_SCRATCH Definition -#define ATOM_S1_ROM_LOCATION_MASK 0x0000FFFFL -#define ATOM_S1_PCI_BUS_DEV_MASK 0xFFFF0000L - -// BIOS_2_SCRATCH Definition -#define ATOM_S2_TV1_STANDARD_MASK 0x0000000FL -#define ATOM_S2_CURRENT_BL_LEVEL_MASK 0x0000FF00L -#define ATOM_S2_CURRENT_BL_LEVEL_SHIFT 8 - -#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK 0x0C000000L -#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK_SHIFT 26 -#define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGE 0x10000000L - -#define ATOM_S2_DEVICE_DPMS_STATE 0x00010000L -#define ATOM_S2_VRI_BRIGHT_ENABLE 0x20000000L - -#define ATOM_S2_DISPLAY_ROTATION_0_DEGREE 0x0 -#define ATOM_S2_DISPLAY_ROTATION_90_DEGREE 0x1 -#define ATOM_S2_DISPLAY_ROTATION_180_DEGREE 0x2 -#define ATOM_S2_DISPLAY_ROTATION_270_DEGREE 0x3 -#define ATOM_S2_DISPLAY_ROTATION_DEGREE_SHIFT 30 -#define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK 0xC0000000L - - -//Byte aligned defintion for BIOS usage -#define ATOM_S2_TV1_STANDARD_MASKb0 0x0F -#define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF -#define ATOM_S2_DEVICE_DPMS_STATEb2 0x01 - -#define ATOM_S2_DEVICE_DPMS_MASKw1 0x3FF -#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASKb3 0x0C -#define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGEb3 0x10 -#define ATOM_S2_VRI_BRIGHT_ENABLEb3 0x20 -#define ATOM_S2_ROTATION_STATE_MASKb3 0xC0 - - -// BIOS_3_SCRATCH Definition -#define ATOM_S3_CRT1_ACTIVE 0x00000001L -#define ATOM_S3_LCD1_ACTIVE 0x00000002L -#define ATOM_S3_TV1_ACTIVE 0x00000004L -#define ATOM_S3_DFP1_ACTIVE 0x00000008L -#define ATOM_S3_CRT2_ACTIVE 0x00000010L -#define ATOM_S3_LCD2_ACTIVE 0x00000020L -#define ATOM_S3_DFP6_ACTIVE 0x00000040L -#define ATOM_S3_DFP2_ACTIVE 0x00000080L -#define ATOM_S3_CV_ACTIVE 0x00000100L -#define ATOM_S3_DFP3_ACTIVE 0x00000200L -#define ATOM_S3_DFP4_ACTIVE 0x00000400L -#define ATOM_S3_DFP5_ACTIVE 0x00000800L - -#define ATOM_S3_DEVICE_ACTIVE_MASK 0x00000FFFL - -#define ATOM_S3_LCD_FULLEXPANSION_ACTIVE 0x00001000L -#define ATOM_S3_LCD_EXPANSION_ASPEC_RATIO_ACTIVE 0x00002000L - -#define ATOM_S3_CRT1_CRTC_ACTIVE 0x00010000L -#define ATOM_S3_LCD1_CRTC_ACTIVE 0x00020000L -#define ATOM_S3_TV1_CRTC_ACTIVE 0x00040000L -#define ATOM_S3_DFP1_CRTC_ACTIVE 0x00080000L -#define ATOM_S3_CRT2_CRTC_ACTIVE 0x00100000L -#define ATOM_S3_LCD2_CRTC_ACTIVE 0x00200000L -#define ATOM_S3_DFP6_CRTC_ACTIVE 0x00400000L -#define ATOM_S3_DFP2_CRTC_ACTIVE 0x00800000L -#define ATOM_S3_CV_CRTC_ACTIVE 0x01000000L -#define ATOM_S3_DFP3_CRTC_ACTIVE 0x02000000L -#define ATOM_S3_DFP4_CRTC_ACTIVE 0x04000000L -#define ATOM_S3_DFP5_CRTC_ACTIVE 0x08000000L - -#define ATOM_S3_DEVICE_CRTC_ACTIVE_MASK 0x0FFF0000L -#define ATOM_S3_ASIC_GUI_ENGINE_HUNG 0x20000000L -//Below two definitions are not supported in pplib, but in the old powerplay in DAL -#define ATOM_S3_ALLOW_FAST_PWR_SWITCH 0x40000000L -#define ATOM_S3_RQST_GPU_USE_MIN_PWR 0x80000000L - -//Byte aligned defintion for BIOS usage -#define ATOM_S3_CRT1_ACTIVEb0 0x01 -#define ATOM_S3_LCD1_ACTIVEb0 0x02 -#define ATOM_S3_TV1_ACTIVEb0 0x04 -#define ATOM_S3_DFP1_ACTIVEb0 0x08 -#define ATOM_S3_CRT2_ACTIVEb0 0x10 -#define ATOM_S3_LCD2_ACTIVEb0 0x20 -#define ATOM_S3_DFP6_ACTIVEb0 0x40 -#define ATOM_S3_DFP2_ACTIVEb0 0x80 -#define ATOM_S3_CV_ACTIVEb1 0x01 -#define ATOM_S3_DFP3_ACTIVEb1 0x02 -#define ATOM_S3_DFP4_ACTIVEb1 0x04 -#define ATOM_S3_DFP5_ACTIVEb1 0x08 - -#define ATOM_S3_ACTIVE_CRTC1w0 0xFFF - -#define ATOM_S3_CRT1_CRTC_ACTIVEb2 0x01 -#define ATOM_S3_LCD1_CRTC_ACTIVEb2 0x02 -#define ATOM_S3_TV1_CRTC_ACTIVEb2 0x04 -#define ATOM_S3_DFP1_CRTC_ACTIVEb2 0x08 -#define ATOM_S3_CRT2_CRTC_ACTIVEb2 0x10 -#define ATOM_S3_LCD2_CRTC_ACTIVEb2 0x20 -#define ATOM_S3_DFP6_CRTC_ACTIVEb2 0x40 -#define ATOM_S3_DFP2_CRTC_ACTIVEb2 0x80 -#define ATOM_S3_CV_CRTC_ACTIVEb3 0x01 -#define ATOM_S3_DFP3_CRTC_ACTIVEb3 0x02 -#define ATOM_S3_DFP4_CRTC_ACTIVEb3 0x04 -#define ATOM_S3_DFP5_CRTC_ACTIVEb3 0x08 - -#define ATOM_S3_ACTIVE_CRTC2w1 0xFFF - -// BIOS_4_SCRATCH Definition -#define ATOM_S4_LCD1_PANEL_ID_MASK 0x000000FFL -#define ATOM_S4_LCD1_REFRESH_MASK 0x0000FF00L -#define ATOM_S4_LCD1_REFRESH_SHIFT 8 - -//Byte aligned defintion for BIOS usage -#define ATOM_S4_LCD1_PANEL_ID_MASKb0 0x0FF -#define ATOM_S4_LCD1_REFRESH_MASKb1 ATOM_S4_LCD1_PANEL_ID_MASKb0 -#define ATOM_S4_VRAM_INFO_MASKb2 ATOM_S4_LCD1_PANEL_ID_MASKb0 - -// BIOS_5_SCRATCH Definition, BIOS_5_SCRATCH is used by Firmware only !!!! -#define ATOM_S5_DOS_REQ_CRT1b0 0x01 -#define ATOM_S5_DOS_REQ_LCD1b0 0x02 -#define ATOM_S5_DOS_REQ_TV1b0 0x04 -#define ATOM_S5_DOS_REQ_DFP1b0 0x08 -#define ATOM_S5_DOS_REQ_CRT2b0 0x10 -#define ATOM_S5_DOS_REQ_LCD2b0 0x20 -#define ATOM_S5_DOS_REQ_DFP6b0 0x40 -#define ATOM_S5_DOS_REQ_DFP2b0 0x80 -#define ATOM_S5_DOS_REQ_CVb1 0x01 -#define ATOM_S5_DOS_REQ_DFP3b1 0x02 -#define ATOM_S5_DOS_REQ_DFP4b1 0x04 -#define ATOM_S5_DOS_REQ_DFP5b1 0x08 - -#define ATOM_S5_DOS_REQ_DEVICEw0 0x0FFF - -#define ATOM_S5_DOS_REQ_CRT1 0x0001 -#define ATOM_S5_DOS_REQ_LCD1 0x0002 -#define ATOM_S5_DOS_REQ_TV1 0x0004 -#define ATOM_S5_DOS_REQ_DFP1 0x0008 -#define ATOM_S5_DOS_REQ_CRT2 0x0010 -#define ATOM_S5_DOS_REQ_LCD2 0x0020 -#define ATOM_S5_DOS_REQ_DFP6 0x0040 -#define ATOM_S5_DOS_REQ_DFP2 0x0080 -#define ATOM_S5_DOS_REQ_CV 0x0100 -#define ATOM_S5_DOS_REQ_DFP3 0x0200 -#define ATOM_S5_DOS_REQ_DFP4 0x0400 -#define ATOM_S5_DOS_REQ_DFP5 0x0800 - -#define ATOM_S5_DOS_FORCE_CRT1b2 ATOM_S5_DOS_REQ_CRT1b0 -#define ATOM_S5_DOS_FORCE_TV1b2 ATOM_S5_DOS_REQ_TV1b0 -#define ATOM_S5_DOS_FORCE_CRT2b2 ATOM_S5_DOS_REQ_CRT2b0 -#define ATOM_S5_DOS_FORCE_CVb3 ATOM_S5_DOS_REQ_CVb1 -#define ATOM_S5_DOS_FORCE_DEVICEw1 (ATOM_S5_DOS_FORCE_CRT1b2+ATOM_S5_DOS_FORCE_TV1b2+ATOM_S5_DOS_FORCE_CRT2b2+\ - (ATOM_S5_DOS_FORCE_CVb3<<8)) - -// BIOS_6_SCRATCH Definition -#define ATOM_S6_DEVICE_CHANGE 0x00000001L -#define ATOM_S6_SCALER_CHANGE 0x00000002L -#define ATOM_S6_LID_CHANGE 0x00000004L -#define ATOM_S6_DOCKING_CHANGE 0x00000008L -#define ATOM_S6_ACC_MODE 0x00000010L -#define ATOM_S6_EXT_DESKTOP_MODE 0x00000020L -#define ATOM_S6_LID_STATE 0x00000040L -#define ATOM_S6_DOCK_STATE 0x00000080L -#define ATOM_S6_CRITICAL_STATE 0x00000100L -#define ATOM_S6_HW_I2C_BUSY_STATE 0x00000200L -#define ATOM_S6_THERMAL_STATE_CHANGE 0x00000400L -#define ATOM_S6_INTERRUPT_SET_BY_BIOS 0x00000800L -#define ATOM_S6_REQ_LCD_EXPANSION_FULL 0x00001000L //Normal expansion Request bit for LCD -#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO 0x00002000L //Aspect ratio expansion Request bit for LCD - -#define ATOM_S6_DISPLAY_STATE_CHANGE 0x00004000L //This bit is recycled when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_H_expansion -#define ATOM_S6_I2C_STATE_CHANGE 0x00008000L //This bit is recycled,when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_V_expansion - -#define ATOM_S6_ACC_REQ_CRT1 0x00010000L -#define ATOM_S6_ACC_REQ_LCD1 0x00020000L -#define ATOM_S6_ACC_REQ_TV1 0x00040000L -#define ATOM_S6_ACC_REQ_DFP1 0x00080000L -#define ATOM_S6_ACC_REQ_CRT2 0x00100000L -#define ATOM_S6_ACC_REQ_LCD2 0x00200000L -#define ATOM_S6_ACC_REQ_DFP6 0x00400000L -#define ATOM_S6_ACC_REQ_DFP2 0x00800000L -#define ATOM_S6_ACC_REQ_CV 0x01000000L -#define ATOM_S6_ACC_REQ_DFP3 0x02000000L -#define ATOM_S6_ACC_REQ_DFP4 0x04000000L -#define ATOM_S6_ACC_REQ_DFP5 0x08000000L - -#define ATOM_S6_ACC_REQ_MASK 0x0FFF0000L -#define ATOM_S6_SYSTEM_POWER_MODE_CHANGE 0x10000000L -#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH 0x20000000L -#define ATOM_S6_VRI_BRIGHTNESS_CHANGE 0x40000000L -#define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK 0x80000000L - -//Byte aligned defintion for BIOS usage -#define ATOM_S6_DEVICE_CHANGEb0 0x01 -#define ATOM_S6_SCALER_CHANGEb0 0x02 -#define ATOM_S6_LID_CHANGEb0 0x04 -#define ATOM_S6_DOCKING_CHANGEb0 0x08 -#define ATOM_S6_ACC_MODEb0 0x10 -#define ATOM_S6_EXT_DESKTOP_MODEb0 0x20 -#define ATOM_S6_LID_STATEb0 0x40 -#define ATOM_S6_DOCK_STATEb0 0x80 -#define ATOM_S6_CRITICAL_STATEb1 0x01 -#define ATOM_S6_HW_I2C_BUSY_STATEb1 0x02 -#define ATOM_S6_THERMAL_STATE_CHANGEb1 0x04 -#define ATOM_S6_INTERRUPT_SET_BY_BIOSb1 0x08 -#define ATOM_S6_REQ_LCD_EXPANSION_FULLb1 0x10 -#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIOb1 0x20 - -#define ATOM_S6_ACC_REQ_CRT1b2 0x01 -#define ATOM_S6_ACC_REQ_LCD1b2 0x02 -#define ATOM_S6_ACC_REQ_TV1b2 0x04 -#define ATOM_S6_ACC_REQ_DFP1b2 0x08 -#define ATOM_S6_ACC_REQ_CRT2b2 0x10 -#define ATOM_S6_ACC_REQ_LCD2b2 0x20 -#define ATOM_S6_ACC_REQ_DFP6b2 0x40 -#define ATOM_S6_ACC_REQ_DFP2b2 0x80 -#define ATOM_S6_ACC_REQ_CVb3 0x01 -#define ATOM_S6_ACC_REQ_DFP3b3 0x02 -#define ATOM_S6_ACC_REQ_DFP4b3 0x04 -#define ATOM_S6_ACC_REQ_DFP5b3 0x08 - -#define ATOM_S6_ACC_REQ_DEVICEw1 ATOM_S5_DOS_REQ_DEVICEw0 -#define ATOM_S6_SYSTEM_POWER_MODE_CHANGEb3 0x10 -#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCHb3 0x20 -#define ATOM_S6_VRI_BRIGHTNESS_CHANGEb3 0x40 -#define ATOM_S6_CONFIG_DISPLAY_CHANGEb3 0x80 - -#define ATOM_S6_DEVICE_CHANGE_SHIFT 0 -#define ATOM_S6_SCALER_CHANGE_SHIFT 1 -#define ATOM_S6_LID_CHANGE_SHIFT 2 -#define ATOM_S6_DOCKING_CHANGE_SHIFT 3 -#define ATOM_S6_ACC_MODE_SHIFT 4 -#define ATOM_S6_EXT_DESKTOP_MODE_SHIFT 5 -#define ATOM_S6_LID_STATE_SHIFT 6 -#define ATOM_S6_DOCK_STATE_SHIFT 7 -#define ATOM_S6_CRITICAL_STATE_SHIFT 8 -#define ATOM_S6_HW_I2C_BUSY_STATE_SHIFT 9 -#define ATOM_S6_THERMAL_STATE_CHANGE_SHIFT 10 -#define ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT 11 -#define ATOM_S6_REQ_SCALER_SHIFT 12 -#define ATOM_S6_REQ_SCALER_ARATIO_SHIFT 13 -#define ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT 14 -#define ATOM_S6_I2C_STATE_CHANGE_SHIFT 15 -#define ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT 28 -#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH_SHIFT 29 -#define ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT 30 -#define ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT 31 - -// BIOS_7_SCRATCH Definition, BIOS_7_SCRATCH is used by Firmware only !!!! -#define ATOM_S7_DOS_MODE_TYPEb0 0x03 -#define ATOM_S7_DOS_MODE_VGAb0 0x00 -#define ATOM_S7_DOS_MODE_VESAb0 0x01 -#define ATOM_S7_DOS_MODE_EXTb0 0x02 -#define ATOM_S7_DOS_MODE_PIXEL_DEPTHb0 0x0C -#define ATOM_S7_DOS_MODE_PIXEL_FORMATb0 0xF0 -#define ATOM_S7_DOS_8BIT_DAC_ENb1 0x01 -#define ATOM_S7_DOS_MODE_NUMBERw1 0x0FFFF - -#define ATOM_S7_DOS_8BIT_DAC_EN_SHIFT 8 - -// BIOS_8_SCRATCH Definition -#define ATOM_S8_I2C_CHANNEL_BUSY_MASK 0x00000FFFF -#define ATOM_S8_I2C_HW_ENGINE_BUSY_MASK 0x0FFFF0000 - -#define ATOM_S8_I2C_CHANNEL_BUSY_SHIFT 0 -#define ATOM_S8_I2C_ENGINE_BUSY_SHIFT 16 - -// BIOS_9_SCRATCH Definition -#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_MASK -#define ATOM_S9_I2C_CHANNEL_COMPLETED_MASK 0x0000FFFF -#endif -#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_MASK -#define ATOM_S9_I2C_CHANNEL_ABORTED_MASK 0xFFFF0000 -#endif -#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT -#define ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 0 -#endif -#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT -#define ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT 16 -#endif - - -#define ATOM_FLAG_SET 0x20 -#define ATOM_FLAG_CLEAR 0 -#define CLEAR_ATOM_S6_ACC_MODE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_ACC_MODE_SHIFT | ATOM_FLAG_CLEAR) -#define SET_ATOM_S6_DEVICE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DEVICE_CHANGE_SHIFT | ATOM_FLAG_SET) -#define SET_ATOM_S6_VRI_BRIGHTNESS_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT | ATOM_FLAG_SET) -#define SET_ATOM_S6_SCALER_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SCALER_CHANGE_SHIFT | ATOM_FLAG_SET) -#define SET_ATOM_S6_LID_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_CHANGE_SHIFT | ATOM_FLAG_SET) - -#define SET_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_SET) -#define CLEAR_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_CLEAR) - -#define SET_ATOM_S6_DOCK_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCKING_CHANGE_SHIFT | ATOM_FLAG_SET) -#define SET_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_SET) -#define CLEAR_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_CLEAR) - -#define SET_ATOM_S6_THERMAL_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_THERMAL_STATE_CHANGE_SHIFT | ATOM_FLAG_SET) -#define SET_ATOM_S6_SYSTEM_POWER_MODE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT | ATOM_FLAG_SET) -#define SET_ATOM_S6_INTERRUPT_SET_BY_BIOS ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT | ATOM_FLAG_SET) - -#define SET_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_SET) -#define CLEAR_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_CLEAR) - -#define SET_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_SET) -#define CLEAR_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_CLEAR ) - -#define SET_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_SET ) -#define CLEAR_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_CLEAR ) - -#define SET_ATOM_S6_I2C_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_I2C_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) - -#define SET_ATOM_S6_DISPLAY_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) - -#define SET_ATOM_S6_DEVICE_RECONFIG ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT | ATOM_FLAG_SET) -#define CLEAR_ATOM_S0_LCD1 ((ATOM_DEVICE_CONNECT_INFO_DEF << 8 )| ATOM_S0_LCD1_SHIFT | ATOM_FLAG_CLEAR ) -#define SET_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_SET ) -#define CLEAR_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_CLEAR ) - -/****************************************************************************/ -//Portion II: Definitinos only used in Driver -/****************************************************************************/ - -// Macros used by driver -#ifdef __cplusplus -#define GetIndexIntoMasterTable(MasterOrData, FieldName) ((reinterpret_cast<char*>(&(static_cast<ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*>(0))->FieldName)-static_cast<char*>(0))/sizeof(USHORT)) - -#define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableFormatRevision )&0x3F) -#define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableContentRevision)&0x3F) -#else // not __cplusplus -#define GetIndexIntoMasterTable(MasterOrData, FieldName) (((char*)(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*)0)->FieldName)-(char*)0)/sizeof(USHORT)) - -#define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevision)&0x3F) -#define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevision)&0x3F) -#endif // __cplusplus - -#define GET_DATA_TABLE_MAJOR_REVISION GET_COMMAND_TABLE_COMMANDSET_REVISION -#define GET_DATA_TABLE_MINOR_REVISION GET_COMMAND_TABLE_PARAMETER_REVISION - -/****************************************************************************/ -//Portion III: Definitinos only used in VBIOS -/****************************************************************************/ -#define ATOM_DAC_SRC 0x80 -#define ATOM_SRC_DAC1 0 -#define ATOM_SRC_DAC2 0x80 - -typedef struct _MEMORY_PLLINIT_PARAMETERS -{ - ULONG ulTargetMemoryClock; //In 10Khz unit - UCHAR ucAction; //not define yet - UCHAR ucFbDiv_Hi; //Fbdiv Hi byte - UCHAR ucFbDiv; //FB value - UCHAR ucPostDiv; //Post div -}MEMORY_PLLINIT_PARAMETERS; - -#define MEMORY_PLLINIT_PS_ALLOCATION MEMORY_PLLINIT_PARAMETERS - - -#define GPIO_PIN_WRITE 0x01 -#define GPIO_PIN_READ 0x00 - -typedef struct _GPIO_PIN_CONTROL_PARAMETERS -{ - UCHAR ucGPIO_ID; //return value, read from GPIO pins - UCHAR ucGPIOBitShift; //define which bit in uGPIOBitVal need to be update - UCHAR ucGPIOBitVal; //Set/Reset corresponding bit defined in ucGPIOBitMask - UCHAR ucAction; //=GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write -}GPIO_PIN_CONTROL_PARAMETERS; - -typedef struct _ENABLE_SCALER_PARAMETERS -{ - UCHAR ucScaler; // ATOM_SCALER1, ATOM_SCALER2 - UCHAR ucEnable; // ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION - UCHAR ucTVStandard; // - UCHAR ucPadding[1]; -}ENABLE_SCALER_PARAMETERS; -#define ENABLE_SCALER_PS_ALLOCATION ENABLE_SCALER_PARAMETERS - -//ucEnable: -#define SCALER_BYPASS_AUTO_CENTER_NO_REPLICATION 0 -#define SCALER_BYPASS_AUTO_CENTER_AUTO_REPLICATION 1 -#define SCALER_ENABLE_2TAP_ALPHA_MODE 2 -#define SCALER_ENABLE_MULTITAP_MODE 3 - -typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS -{ - ULONG usHWIconHorzVertPosn; // Hardware Icon Vertical position - UCHAR ucHWIconVertOffset; // Hardware Icon Vertical offset - UCHAR ucHWIconHorzOffset; // Hardware Icon Horizontal offset - UCHAR ucSelection; // ATOM_CURSOR1 or ATOM_ICON1 or ATOM_CURSOR2 or ATOM_ICON2 - UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE -}ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS; - -typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION -{ - ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS sEnableIcon; - ENABLE_CRTC_PARAMETERS sReserved; -}ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION; - -typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS -{ - USHORT usHight; // Image Hight - USHORT usWidth; // Image Width - UCHAR ucSurface; // Surface 1 or 2 - UCHAR ucPadding[3]; -}ENABLE_GRAPH_SURFACE_PARAMETERS; - -typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2 -{ - USHORT usHight; // Image Hight - USHORT usWidth; // Image Width - UCHAR ucSurface; // Surface 1 or 2 - UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE - UCHAR ucPadding[2]; -}ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2; - -typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3 -{ - USHORT usHight; // Image Hight - USHORT usWidth; // Image Width - UCHAR ucSurface; // Surface 1 or 2 - UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE - USHORT usDeviceId; // Active Device Id for this surface. If no device, set to 0. -}ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3; - -typedef struct _ENABLE_GRAPH_SURFACE_PS_ALLOCATION -{ - ENABLE_GRAPH_SURFACE_PARAMETERS sSetSurface; - ENABLE_YUV_PS_ALLOCATION sReserved; // Don't set this one -}ENABLE_GRAPH_SURFACE_PS_ALLOCATION; - -typedef struct _MEMORY_CLEAN_UP_PARAMETERS -{ - USHORT usMemoryStart; //in 8Kb boundry, offset from memory base address - USHORT usMemorySize; //8Kb blocks aligned -}MEMORY_CLEAN_UP_PARAMETERS; -#define MEMORY_CLEAN_UP_PS_ALLOCATION MEMORY_CLEAN_UP_PARAMETERS - -typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS -{ - USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC - USHORT usY_Size; -}GET_DISPLAY_SURFACE_SIZE_PARAMETERS; - -typedef struct _INDIRECT_IO_ACCESS -{ - ATOM_COMMON_TABLE_HEADER sHeader; - UCHAR IOAccessSequence[256]; -} INDIRECT_IO_ACCESS; - -#define INDIRECT_READ 0x00 -#define INDIRECT_WRITE 0x80 - -#define INDIRECT_IO_MM 0 -#define INDIRECT_IO_PLL 1 -#define INDIRECT_IO_MC 2 -#define INDIRECT_IO_PCIE 3 -#define INDIRECT_IO_PCIEP 4 -#define INDIRECT_IO_NBMISC 5 - -#define INDIRECT_IO_PLL_READ INDIRECT_IO_PLL | INDIRECT_READ -#define INDIRECT_IO_PLL_WRITE INDIRECT_IO_PLL | INDIRECT_WRITE -#define INDIRECT_IO_MC_READ INDIRECT_IO_MC | INDIRECT_READ -#define INDIRECT_IO_MC_WRITE INDIRECT_IO_MC | INDIRECT_WRITE -#define INDIRECT_IO_PCIE_READ INDIRECT_IO_PCIE | INDIRECT_READ -#define INDIRECT_IO_PCIE_WRITE INDIRECT_IO_PCIE | INDIRECT_WRITE -#define INDIRECT_IO_PCIEP_READ INDIRECT_IO_PCIEP | INDIRECT_READ -#define INDIRECT_IO_PCIEP_WRITE INDIRECT_IO_PCIEP | INDIRECT_WRITE -#define INDIRECT_IO_NBMISC_READ INDIRECT_IO_NBMISC | INDIRECT_READ -#define INDIRECT_IO_NBMISC_WRITE INDIRECT_IO_NBMISC | INDIRECT_WRITE - -typedef struct _ATOM_OEM_INFO -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; -}ATOM_OEM_INFO; - -typedef struct _ATOM_TV_MODE -{ - UCHAR ucVMode_Num; //Video mode number - UCHAR ucTV_Mode_Num; //Internal TV mode number -}ATOM_TV_MODE; - -typedef struct _ATOM_BIOS_INT_TVSTD_MODE -{ - ATOM_COMMON_TABLE_HEADER sHeader; - USHORT usTV_Mode_LUT_Offset; // Pointer to standard to internal number conversion table - USHORT usTV_FIFO_Offset; // Pointer to FIFO entry table - USHORT usNTSC_Tbl_Offset; // Pointer to SDTV_Mode_NTSC table - USHORT usPAL_Tbl_Offset; // Pointer to SDTV_Mode_PAL table - USHORT usCV_Tbl_Offset; // Pointer to SDTV_Mode_PAL table -}ATOM_BIOS_INT_TVSTD_MODE; - - -typedef struct _ATOM_TV_MODE_SCALER_PTR -{ - USHORT ucFilter0_Offset; //Pointer to filter format 0 coefficients - USHORT usFilter1_Offset; //Pointer to filter format 0 coefficients - UCHAR ucTV_Mode_Num; -}ATOM_TV_MODE_SCALER_PTR; - -typedef struct _ATOM_STANDARD_VESA_TIMING -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_DTD_FORMAT aModeTimings[16]; // 16 is not the real array number, just for initial allocation -}ATOM_STANDARD_VESA_TIMING; - - -typedef struct _ATOM_STD_FORMAT -{ - USHORT usSTD_HDisp; - USHORT usSTD_VDisp; - USHORT usSTD_RefreshRate; - USHORT usReserved; -}ATOM_STD_FORMAT; - -typedef struct _ATOM_VESA_TO_EXTENDED_MODE -{ - USHORT usVESA_ModeNumber; - USHORT usExtendedModeNumber; -}ATOM_VESA_TO_EXTENDED_MODE; - -typedef struct _ATOM_VESA_TO_INTENAL_MODE_LUT -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_VESA_TO_EXTENDED_MODE asVESA_ToExtendedModeInfo[76]; -}ATOM_VESA_TO_INTENAL_MODE_LUT; - -/*************** ATOM Memory Related Data Structure ***********************/ -typedef struct _ATOM_MEMORY_VENDOR_BLOCK{ - UCHAR ucMemoryType; - UCHAR ucMemoryVendor; - UCHAR ucAdjMCId; - UCHAR ucDynClkId; - ULONG ulDllResetClkRange; -}ATOM_MEMORY_VENDOR_BLOCK; - - -typedef struct _ATOM_MEMORY_SETTING_ID_CONFIG{ -#if ATOM_BIG_ENDIAN - ULONG ucMemBlkId:8; - ULONG ulMemClockRange:24; -#else - ULONG ulMemClockRange:24; - ULONG ucMemBlkId:8; -#endif -}ATOM_MEMORY_SETTING_ID_CONFIG; - -typedef union _ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS -{ - ATOM_MEMORY_SETTING_ID_CONFIG slAccess; - ULONG ulAccess; -}ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS; - - -typedef struct _ATOM_MEMORY_SETTING_DATA_BLOCK{ - ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS ulMemoryID; - ULONG aulMemData[1]; -}ATOM_MEMORY_SETTING_DATA_BLOCK; - - -typedef struct _ATOM_INIT_REG_INDEX_FORMAT{ - USHORT usRegIndex; // MC register index - UCHAR ucPreRegDataLength; // offset in ATOM_INIT_REG_DATA_BLOCK.saRegDataBuf -}ATOM_INIT_REG_INDEX_FORMAT; - - -typedef struct _ATOM_INIT_REG_BLOCK{ - USHORT usRegIndexTblSize; //size of asRegIndexBuf - USHORT usRegDataBlkSize; //size of ATOM_MEMORY_SETTING_DATA_BLOCK - ATOM_INIT_REG_INDEX_FORMAT asRegIndexBuf[1]; - ATOM_MEMORY_SETTING_DATA_BLOCK asRegDataBuf[1]; -}ATOM_INIT_REG_BLOCK; - -#define END_OF_REG_INDEX_BLOCK 0x0ffff -#define END_OF_REG_DATA_BLOCK 0x00000000 -#define ATOM_INIT_REG_MASK_FLAG 0x80 -#define CLOCK_RANGE_HIGHEST 0x00ffffff - -#define VALUE_DWORD SIZEOF ULONG -#define VALUE_SAME_AS_ABOVE 0 -#define VALUE_MASK_DWORD 0x84 - -#define INDEX_ACCESS_RANGE_BEGIN (VALUE_DWORD + 1) -#define INDEX_ACCESS_RANGE_END (INDEX_ACCESS_RANGE_BEGIN + 1) -#define VALUE_INDEX_ACCESS_SINGLE (INDEX_ACCESS_RANGE_END + 1) - - -typedef struct _ATOM_MC_INIT_PARAM_TABLE -{ - ATOM_COMMON_TABLE_HEADER sHeader; - USHORT usAdjustARB_SEQDataOffset; - USHORT usMCInitMemTypeTblOffset; - USHORT usMCInitCommonTblOffset; - USHORT usMCInitPowerDownTblOffset; - ULONG ulARB_SEQDataBuf[32]; - ATOM_INIT_REG_BLOCK asMCInitMemType; - ATOM_INIT_REG_BLOCK asMCInitCommon; -}ATOM_MC_INIT_PARAM_TABLE; - - -#define _4Mx16 0x2 -#define _4Mx32 0x3 -#define _8Mx16 0x12 -#define _8Mx32 0x13 -#define _16Mx16 0x22 -#define _16Mx32 0x23 -#define _32Mx16 0x32 -#define _32Mx32 0x33 -#define _64Mx8 0x41 -#define _64Mx16 0x42 - -#define SAMSUNG 0x1 -#define INFINEON 0x2 -#define ELPIDA 0x3 -#define ETRON 0x4 -#define NANYA 0x5 -#define HYNIX 0x6 -#define MOSEL 0x7 -#define WINBOND 0x8 -#define ESMT 0x9 -#define MICRON 0xF - -#define QIMONDA INFINEON -#define PROMOS MOSEL -#define KRETON INFINEON - -/////////////Support for GDDR5 MC uCode to reside in upper 64K of ROM///////////// - -#define UCODE_ROM_START_ADDRESS 0x1c000 -#define UCODE_SIGNATURE 0x4375434d // 'MCuC' - MC uCode - -//uCode block header for reference - -typedef struct _MCuCodeHeader -{ - ULONG ulSignature; - UCHAR ucRevision; - UCHAR ucChecksum; - UCHAR ucReserved1; - UCHAR ucReserved2; - USHORT usParametersLength; - USHORT usUCodeLength; - USHORT usReserved1; - USHORT usReserved2; -} MCuCodeHeader; - -////////////////////////////////////////////////////////////////////////////////// - -#define ATOM_MAX_NUMBER_OF_VRAM_MODULE 16 - -#define ATOM_VRAM_MODULE_MEMORY_VENDOR_ID_MASK 0xF -typedef struct _ATOM_VRAM_MODULE_V1 -{ - ULONG ulReserved; - USHORT usEMRSValue; - USHORT usMRSValue; - USHORT usReserved; - UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module - UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] reserved; - UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender - UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... - UCHAR ucRow; // Number of Row,in power of 2; - UCHAR ucColumn; // Number of Column,in power of 2; - UCHAR ucBank; // Nunber of Bank; - UCHAR ucRank; // Number of Rank, in power of 2 - UCHAR ucChannelNum; // Number of channel; - UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 - UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; - UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; - UCHAR ucReserved[2]; -}ATOM_VRAM_MODULE_V1; - - -typedef struct _ATOM_VRAM_MODULE_V2 -{ - ULONG ulReserved; - ULONG ulFlags; // To enable/disable functionalities based on memory type - ULONG ulEngineClock; // Override of default engine clock for particular memory type - ULONG ulMemoryClock; // Override of default memory clock for particular memory type - USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type - USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type - USHORT usEMRSValue; - USHORT usMRSValue; - USHORT usReserved; - UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module - UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; - UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed - UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... - UCHAR ucRow; // Number of Row,in power of 2; - UCHAR ucColumn; // Number of Column,in power of 2; - UCHAR ucBank; // Nunber of Bank; - UCHAR ucRank; // Number of Rank, in power of 2 - UCHAR ucChannelNum; // Number of channel; - UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 - UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; - UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; - UCHAR ucRefreshRateFactor; - UCHAR ucReserved[3]; -}ATOM_VRAM_MODULE_V2; - - -typedef struct _ATOM_MEMORY_TIMING_FORMAT -{ - ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing - union{ - USHORT usMRS; // mode register - USHORT usDDR3_MR0; - }; - union{ - USHORT usEMRS; // extended mode register - USHORT usDDR3_MR1; - }; - UCHAR ucCL; // CAS latency - UCHAR ucWL; // WRITE Latency - UCHAR uctRAS; // tRAS - UCHAR uctRC; // tRC - UCHAR uctRFC; // tRFC - UCHAR uctRCDR; // tRCDR - UCHAR uctRCDW; // tRCDW - UCHAR uctRP; // tRP - UCHAR uctRRD; // tRRD - UCHAR uctWR; // tWR - UCHAR uctWTR; // tWTR - UCHAR uctPDIX; // tPDIX - UCHAR uctFAW; // tFAW - UCHAR uctAOND; // tAOND - union - { - struct { - UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon - UCHAR ucReserved; - }; - USHORT usDDR3_MR2; - }; -}ATOM_MEMORY_TIMING_FORMAT; - - -typedef struct _ATOM_MEMORY_TIMING_FORMAT_V1 -{ - ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing - USHORT usMRS; // mode register - USHORT usEMRS; // extended mode register - UCHAR ucCL; // CAS latency - UCHAR ucWL; // WRITE Latency - UCHAR uctRAS; // tRAS - UCHAR uctRC; // tRC - UCHAR uctRFC; // tRFC - UCHAR uctRCDR; // tRCDR - UCHAR uctRCDW; // tRCDW - UCHAR uctRP; // tRP - UCHAR uctRRD; // tRRD - UCHAR uctWR; // tWR - UCHAR uctWTR; // tWTR - UCHAR uctPDIX; // tPDIX - UCHAR uctFAW; // tFAW - UCHAR uctAOND; // tAOND - UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon -////////////////////////////////////GDDR parameters/////////////////////////////////// - UCHAR uctCCDL; // - UCHAR uctCRCRL; // - UCHAR uctCRCWL; // - UCHAR uctCKE; // - UCHAR uctCKRSE; // - UCHAR uctCKRSX; // - UCHAR uctFAW32; // - UCHAR ucMR5lo; // - UCHAR ucMR5hi; // - UCHAR ucTerminator; -}ATOM_MEMORY_TIMING_FORMAT_V1; - -typedef struct _ATOM_MEMORY_TIMING_FORMAT_V2 -{ - ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing - USHORT usMRS; // mode register - USHORT usEMRS; // extended mode register - UCHAR ucCL; // CAS latency - UCHAR ucWL; // WRITE Latency - UCHAR uctRAS; // tRAS - UCHAR uctRC; // tRC - UCHAR uctRFC; // tRFC - UCHAR uctRCDR; // tRCDR - UCHAR uctRCDW; // tRCDW - UCHAR uctRP; // tRP - UCHAR uctRRD; // tRRD - UCHAR uctWR; // tWR - UCHAR uctWTR; // tWTR - UCHAR uctPDIX; // tPDIX - UCHAR uctFAW; // tFAW - UCHAR uctAOND; // tAOND - UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon -////////////////////////////////////GDDR parameters/////////////////////////////////// - UCHAR uctCCDL; // - UCHAR uctCRCRL; // - UCHAR uctCRCWL; // - UCHAR uctCKE; // - UCHAR uctCKRSE; // - UCHAR uctCKRSX; // - UCHAR uctFAW32; // - UCHAR ucMR4lo; // - UCHAR ucMR4hi; // - UCHAR ucMR5lo; // - UCHAR ucMR5hi; // - UCHAR ucTerminator; - UCHAR ucReserved; -}ATOM_MEMORY_TIMING_FORMAT_V2; - -typedef struct _ATOM_MEMORY_FORMAT -{ - ULONG ulDllDisClock; // memory DLL will be disable when target memory clock is below this clock - union{ - USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type - USHORT usDDR3_Reserved; // Not used for DDR3 memory - }; - union{ - USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type - USHORT usDDR3_MR3; // Used for DDR3 memory - }; - UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; - UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed - UCHAR ucRow; // Number of Row,in power of 2; - UCHAR ucColumn; // Number of Column,in power of 2; - UCHAR ucBank; // Nunber of Bank; - UCHAR ucRank; // Number of Rank, in power of 2 - UCHAR ucBurstSize; // burst size, 0= burst size=4 1= burst size=8 - UCHAR ucDllDisBit; // position of DLL Enable/Disable bit in EMRS ( Extended Mode Register ) - UCHAR ucRefreshRateFactor; // memory refresh rate in unit of ms - UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 - UCHAR ucPreamble; //[7:4] Write Preamble, [3:0] Read Preamble - UCHAR ucMemAttrib; // Memory Device Addribute, like RDBI/WDBI etc - ATOM_MEMORY_TIMING_FORMAT asMemTiming[5]; //Memory Timing block sort from lower clock to higher clock -}ATOM_MEMORY_FORMAT; - - -typedef struct _ATOM_VRAM_MODULE_V3 -{ - ULONG ulChannelMapCfg; // board dependent paramenter:Channel combination - USHORT usSize; // size of ATOM_VRAM_MODULE_V3 - USHORT usDefaultMVDDQ; // board dependent parameter:Default Memory Core Voltage - USHORT usDefaultMVDDC; // board dependent parameter:Default Memory IO Voltage - UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module - UCHAR ucChannelNum; // board dependent parameter:Number of channel; - UCHAR ucChannelSize; // board dependent parameter:32bit or 64bit - UCHAR ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv - UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters - UCHAR ucFlag; // To enable/disable functionalities based on memory type - ATOM_MEMORY_FORMAT asMemory; // describ all of video memory parameters from memory spec -}ATOM_VRAM_MODULE_V3; - - -//ATOM_VRAM_MODULE_V3.ucNPL_RT -#define NPL_RT_MASK 0x0f -#define BATTERY_ODT_MASK 0xc0 - -#define ATOM_VRAM_MODULE ATOM_VRAM_MODULE_V3 - -typedef struct _ATOM_VRAM_MODULE_V4 -{ - ULONG ulChannelMapCfg; // board dependent parameter: Channel combination - USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE - USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! - // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) - USHORT usReserved; - UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module - UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; - UCHAR ucChannelNum; // Number of channels present in this module config - UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits - UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 - UCHAR ucFlag; // To enable/disable functionalities based on memory type - UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 - UCHAR ucVREFI; // board dependent parameter - UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters - UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble - UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! - // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros - UCHAR ucReserved[3]; - -//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level - union{ - USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type - USHORT usDDR3_Reserved; - }; - union{ - USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type - USHORT usDDR3_MR3; // Used for DDR3 memory - }; - UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed - UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) - UCHAR ucReserved2[2]; - ATOM_MEMORY_TIMING_FORMAT asMemTiming[5];//Memory Timing block sort from lower clock to higher clock -}ATOM_VRAM_MODULE_V4; - -#define VRAM_MODULE_V4_MISC_RANK_MASK 0x3 -#define VRAM_MODULE_V4_MISC_DUAL_RANK 0x1 -#define VRAM_MODULE_V4_MISC_BL_MASK 0x4 -#define VRAM_MODULE_V4_MISC_BL8 0x4 -#define VRAM_MODULE_V4_MISC_DUAL_CS 0x10 - -typedef struct _ATOM_VRAM_MODULE_V5 -{ - ULONG ulChannelMapCfg; // board dependent parameter: Channel combination - USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE - USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! - // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) - USHORT usReserved; - UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module - UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; - UCHAR ucChannelNum; // Number of channels present in this module config - UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits - UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 - UCHAR ucFlag; // To enable/disable functionalities based on memory type - UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 - UCHAR ucVREFI; // board dependent parameter - UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters - UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble - UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! - // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros - UCHAR ucReserved[3]; - -//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level - USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type - USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type - UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed - UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) - UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth - UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth - ATOM_MEMORY_TIMING_FORMAT_V1 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock -}ATOM_VRAM_MODULE_V5; - -typedef struct _ATOM_VRAM_MODULE_V6 -{ - ULONG ulChannelMapCfg; // board dependent parameter: Channel combination - USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE - USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! - // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) - USHORT usReserved; - UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module - UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; - UCHAR ucChannelNum; // Number of channels present in this module config - UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits - UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 - UCHAR ucFlag; // To enable/disable functionalities based on memory type - UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 - UCHAR ucVREFI; // board dependent parameter - UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters - UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble - UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! - // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros - UCHAR ucReserved[3]; - -//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level - USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type - USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type - UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed - UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) - UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth - UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth - ATOM_MEMORY_TIMING_FORMAT_V2 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock -}ATOM_VRAM_MODULE_V6; - - - -typedef struct _ATOM_VRAM_INFO_V2 -{ - ATOM_COMMON_TABLE_HEADER sHeader; - UCHAR ucNumOfVRAMModule; - ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; -}ATOM_VRAM_INFO_V2; - -typedef struct _ATOM_VRAM_INFO_V3 -{ - ATOM_COMMON_TABLE_HEADER sHeader; - USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting - USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting - USHORT usRerseved; - UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator - UCHAR ucNumOfVRAMModule; - ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; - ATOM_INIT_REG_BLOCK asMemPatch; // for allocation - // ATOM_INIT_REG_BLOCK aMemAdjust; -}ATOM_VRAM_INFO_V3; - -#define ATOM_VRAM_INFO_LAST ATOM_VRAM_INFO_V3 - -typedef struct _ATOM_VRAM_INFO_V4 -{ - ATOM_COMMON_TABLE_HEADER sHeader; - USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting - USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting - USHORT usRerseved; - UCHAR ucMemDQ7_0ByteRemap; // DQ line byte remap, =0: Memory Data line BYTE0, =1: BYTE1, =2: BYTE2, =3: BYTE3 - ULONG ulMemDQ7_0BitRemap; // each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0], DQ1:[5:3], ... DQ7:[23:21] - UCHAR ucReservde[4]; - UCHAR ucNumOfVRAMModule; - ATOM_VRAM_MODULE_V4 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; - ATOM_INIT_REG_BLOCK asMemPatch; // for allocation - // ATOM_INIT_REG_BLOCK aMemAdjust; -}ATOM_VRAM_INFO_V4; - -typedef struct _ATOM_VRAM_GPIO_DETECTION_INFO -{ - ATOM_COMMON_TABLE_HEADER sHeader; - UCHAR aVID_PinsShift[9]; //8 bit strap maximum+terminator -}ATOM_VRAM_GPIO_DETECTION_INFO; - - -typedef struct _ATOM_MEMORY_TRAINING_INFO -{ - ATOM_COMMON_TABLE_HEADER sHeader; - UCHAR ucTrainingLoop; - UCHAR ucReserved[3]; - ATOM_INIT_REG_BLOCK asMemTrainingSetting; -}ATOM_MEMORY_TRAINING_INFO; - - -typedef struct SW_I2C_CNTL_DATA_PARAMETERS -{ - UCHAR ucControl; - UCHAR ucData; - UCHAR ucSatus; - UCHAR ucTemp; -} SW_I2C_CNTL_DATA_PARAMETERS; - -#define SW_I2C_CNTL_DATA_PS_ALLOCATION SW_I2C_CNTL_DATA_PARAMETERS - -typedef struct _SW_I2C_IO_DATA_PARAMETERS -{ - USHORT GPIO_Info; - UCHAR ucAct; - UCHAR ucData; - } SW_I2C_IO_DATA_PARAMETERS; - -#define SW_I2C_IO_DATA_PS_ALLOCATION SW_I2C_IO_DATA_PARAMETERS - -/****************************SW I2C CNTL DEFINITIONS**********************/ -#define SW_I2C_IO_RESET 0 -#define SW_I2C_IO_GET 1 -#define SW_I2C_IO_DRIVE 2 -#define SW_I2C_IO_SET 3 -#define SW_I2C_IO_START 4 - -#define SW_I2C_IO_CLOCK 0 -#define SW_I2C_IO_DATA 0x80 - -#define SW_I2C_IO_ZERO 0 -#define SW_I2C_IO_ONE 0x100 - -#define SW_I2C_CNTL_READ 0 -#define SW_I2C_CNTL_WRITE 1 -#define SW_I2C_CNTL_START 2 -#define SW_I2C_CNTL_STOP 3 -#define SW_I2C_CNTL_OPEN 4 -#define SW_I2C_CNTL_CLOSE 5 -#define SW_I2C_CNTL_WRITE1BIT 6 - -//==============================VESA definition Portion=============================== -#define VESA_OEM_PRODUCT_REV '01.00' -#define VESA_MODE_ATTRIBUTE_MODE_SUPPORT 0xBB //refer to VBE spec p.32, no TTY support -#define VESA_MODE_WIN_ATTRIBUTE 7 -#define VESA_WIN_SIZE 64 - -typedef struct _PTR_32_BIT_STRUCTURE -{ - USHORT Offset16; - USHORT Segment16; -} PTR_32_BIT_STRUCTURE; - -typedef union _PTR_32_BIT_UNION -{ - PTR_32_BIT_STRUCTURE SegmentOffset; - ULONG Ptr32_Bit; -} PTR_32_BIT_UNION; - -typedef struct _VBE_1_2_INFO_BLOCK_UPDATABLE -{ - UCHAR VbeSignature[4]; - USHORT VbeVersion; - PTR_32_BIT_UNION OemStringPtr; - UCHAR Capabilities[4]; - PTR_32_BIT_UNION VideoModePtr; - USHORT TotalMemory; -} VBE_1_2_INFO_BLOCK_UPDATABLE; - - -typedef struct _VBE_2_0_INFO_BLOCK_UPDATABLE -{ - VBE_1_2_INFO_BLOCK_UPDATABLE CommonBlock; - USHORT OemSoftRev; - PTR_32_BIT_UNION OemVendorNamePtr; - PTR_32_BIT_UNION OemProductNamePtr; - PTR_32_BIT_UNION OemProductRevPtr; -} VBE_2_0_INFO_BLOCK_UPDATABLE; - -typedef union _VBE_VERSION_UNION -{ - VBE_2_0_INFO_BLOCK_UPDATABLE VBE_2_0_InfoBlock; - VBE_1_2_INFO_BLOCK_UPDATABLE VBE_1_2_InfoBlock; -} VBE_VERSION_UNION; - -typedef struct _VBE_INFO_BLOCK -{ - VBE_VERSION_UNION UpdatableVBE_Info; - UCHAR Reserved[222]; - UCHAR OemData[256]; -} VBE_INFO_BLOCK; - -typedef struct _VBE_FP_INFO -{ - USHORT HSize; - USHORT VSize; - USHORT FPType; - UCHAR RedBPP; - UCHAR GreenBPP; - UCHAR BlueBPP; - UCHAR ReservedBPP; - ULONG RsvdOffScrnMemSize; - ULONG RsvdOffScrnMEmPtr; - UCHAR Reserved[14]; -} VBE_FP_INFO; - -typedef struct _VESA_MODE_INFO_BLOCK -{ -// Mandatory information for all VBE revisions - USHORT ModeAttributes; // dw ? ; mode attributes - UCHAR WinAAttributes; // db ? ; window A attributes - UCHAR WinBAttributes; // db ? ; window B attributes - USHORT WinGranularity; // dw ? ; window granularity - USHORT WinSize; // dw ? ; window size - USHORT WinASegment; // dw ? ; window A start segment - USHORT WinBSegment; // dw ? ; window B start segment - ULONG WinFuncPtr; // dd ? ; real mode pointer to window function - USHORT BytesPerScanLine;// dw ? ; bytes per scan line - -//; Mandatory information for VBE 1.2 and above - USHORT XResolution; // dw ? ; horizontal resolution in pixels or characters - USHORT YResolution; // dw ? ; vertical resolution in pixels or characters - UCHAR XCharSize; // db ? ; character cell width in pixels - UCHAR YCharSize; // db ? ; character cell height in pixels - UCHAR NumberOfPlanes; // db ? ; number of memory planes - UCHAR BitsPerPixel; // db ? ; bits per pixel - UCHAR NumberOfBanks; // db ? ; number of banks - UCHAR MemoryModel; // db ? ; memory model type - UCHAR BankSize; // db ? ; bank size in KB - UCHAR NumberOfImagePages;// db ? ; number of images - UCHAR ReservedForPageFunction;//db 1 ; reserved for page function - -//; Direct Color fields(required for direct/6 and YUV/7 memory models) - UCHAR RedMaskSize; // db ? ; size of direct color red mask in bits - UCHAR RedFieldPosition; // db ? ; bit position of lsb of red mask - UCHAR GreenMaskSize; // db ? ; size of direct color green mask in bits - UCHAR GreenFieldPosition; // db ? ; bit position of lsb of green mask - UCHAR BlueMaskSize; // db ? ; size of direct color blue mask in bits - UCHAR BlueFieldPosition; // db ? ; bit position of lsb of blue mask - UCHAR RsvdMaskSize; // db ? ; size of direct color reserved mask in bits - UCHAR RsvdFieldPosition; // db ? ; bit position of lsb of reserved mask - UCHAR DirectColorModeInfo;// db ? ; direct color mode attributes - -//; Mandatory information for VBE 2.0 and above - ULONG PhysBasePtr; // dd ? ; physical address for flat memory frame buffer - ULONG Reserved_1; // dd 0 ; reserved - always set to 0 - USHORT Reserved_2; // dw 0 ; reserved - always set to 0 - -//; Mandatory information for VBE 3.0 and above - USHORT LinBytesPerScanLine; // dw ? ; bytes per scan line for linear modes - UCHAR BnkNumberOfImagePages;// db ? ; number of images for banked modes - UCHAR LinNumberOfImagPages; // db ? ; number of images for linear modes - UCHAR LinRedMaskSize; // db ? ; size of direct color red mask(linear modes) - UCHAR LinRedFieldPosition; // db ? ; bit position of lsb of red mask(linear modes) - UCHAR LinGreenMaskSize; // db ? ; size of direct color green mask(linear modes) - UCHAR LinGreenFieldPosition;// db ? ; bit position of lsb of green mask(linear modes) - UCHAR LinBlueMaskSize; // db ? ; size of direct color blue mask(linear modes) - UCHAR LinBlueFieldPosition; // db ? ; bit position of lsb of blue mask(linear modes) - UCHAR LinRsvdMaskSize; // db ? ; size of direct color reserved mask(linear modes) - UCHAR LinRsvdFieldPosition; // db ? ; bit position of lsb of reserved mask(linear modes) - ULONG MaxPixelClock; // dd ? ; maximum pixel clock(in Hz) for graphics mode - UCHAR Reserved; // db 190 dup (0) -} VESA_MODE_INFO_BLOCK; - -// BIOS function CALLS -#define ATOM_BIOS_EXTENDED_FUNCTION_CODE 0xA0 // ATI Extended Function code -#define ATOM_BIOS_FUNCTION_COP_MODE 0x00 -#define ATOM_BIOS_FUNCTION_SHORT_QUERY1 0x04 -#define ATOM_BIOS_FUNCTION_SHORT_QUERY2 0x05 -#define ATOM_BIOS_FUNCTION_SHORT_QUERY3 0x06 -#define ATOM_BIOS_FUNCTION_GET_DDC 0x0B -#define ATOM_BIOS_FUNCTION_ASIC_DSTATE 0x0E -#define ATOM_BIOS_FUNCTION_DEBUG_PLAY 0x0F -#define ATOM_BIOS_FUNCTION_STV_STD 0x16 -#define ATOM_BIOS_FUNCTION_DEVICE_DET 0x17 -#define ATOM_BIOS_FUNCTION_DEVICE_SWITCH 0x18 - -#define ATOM_BIOS_FUNCTION_PANEL_CONTROL 0x82 -#define ATOM_BIOS_FUNCTION_OLD_DEVICE_DET 0x83 -#define ATOM_BIOS_FUNCTION_OLD_DEVICE_SWITCH 0x84 -#define ATOM_BIOS_FUNCTION_HW_ICON 0x8A -#define ATOM_BIOS_FUNCTION_SET_CMOS 0x8B -#define SUB_FUNCTION_UPDATE_DISPLAY_INFO 0x8000 // Sub function 80 -#define SUB_FUNCTION_UPDATE_EXPANSION_INFO 0x8100 // Sub function 80 - -#define ATOM_BIOS_FUNCTION_DISPLAY_INFO 0x8D -#define ATOM_BIOS_FUNCTION_DEVICE_ON_OFF 0x8E -#define ATOM_BIOS_FUNCTION_VIDEO_STATE 0x8F -#define ATOM_SUB_FUNCTION_GET_CRITICAL_STATE 0x0300 // Sub function 03 -#define ATOM_SUB_FUNCTION_GET_LIDSTATE 0x0700 // Sub function 7 -#define ATOM_SUB_FUNCTION_THERMAL_STATE_NOTICE 0x1400 // Notify caller the current thermal state -#define ATOM_SUB_FUNCTION_CRITICAL_STATE_NOTICE 0x8300 // Notify caller the current critical state -#define ATOM_SUB_FUNCTION_SET_LIDSTATE 0x8500 // Sub function 85 -#define ATOM_SUB_FUNCTION_GET_REQ_DISPLAY_FROM_SBIOS_MODE 0x8900// Sub function 89 -#define ATOM_SUB_FUNCTION_INFORM_ADC_SUPPORT 0x9400 // Notify caller that ADC is supported - - -#define ATOM_BIOS_FUNCTION_VESA_DPMS 0x4F10 // Set DPMS -#define ATOM_SUB_FUNCTION_SET_DPMS 0x0001 // BL: Sub function 01 -#define ATOM_SUB_FUNCTION_GET_DPMS 0x0002 // BL: Sub function 02 -#define ATOM_PARAMETER_VESA_DPMS_ON 0x0000 // BH Parameter for DPMS ON. -#define ATOM_PARAMETER_VESA_DPMS_STANDBY 0x0100 // BH Parameter for DPMS STANDBY -#define ATOM_PARAMETER_VESA_DPMS_SUSPEND 0x0200 // BH Parameter for DPMS SUSPEND -#define ATOM_PARAMETER_VESA_DPMS_OFF 0x0400 // BH Parameter for DPMS OFF -#define ATOM_PARAMETER_VESA_DPMS_REDUCE_ON 0x0800 // BH Parameter for DPMS REDUCE ON (NOT SUPPORTED) - -#define ATOM_BIOS_RETURN_CODE_MASK 0x0000FF00L -#define ATOM_BIOS_REG_HIGH_MASK 0x0000FF00L -#define ATOM_BIOS_REG_LOW_MASK 0x000000FFL - -// structure used for VBIOS only - -//DispOutInfoTable -typedef struct _ASIC_TRANSMITTER_INFO -{ - USHORT usTransmitterObjId; - USHORT usSupportDevice; - UCHAR ucTransmitterCmdTblId; - UCHAR ucConfig; - UCHAR ucEncoderID; //available 1st encoder ( default ) - UCHAR ucOptionEncoderID; //available 2nd encoder ( optional ) - UCHAR uc2ndEncoderID; - UCHAR ucReserved; -}ASIC_TRANSMITTER_INFO; - -typedef struct _ASIC_ENCODER_INFO -{ - UCHAR ucEncoderID; - UCHAR ucEncoderConfig; - USHORT usEncoderCmdTblId; -}ASIC_ENCODER_INFO; - -typedef struct _ATOM_DISP_OUT_INFO -{ - ATOM_COMMON_TABLE_HEADER sHeader; - USHORT ptrTransmitterInfo; - USHORT ptrEncoderInfo; - ASIC_TRANSMITTER_INFO asTransmitterInfo[1]; - ASIC_ENCODER_INFO asEncoderInfo[1]; -}ATOM_DISP_OUT_INFO; - -typedef struct _ATOM_DISP_OUT_INFO_V2 -{ - ATOM_COMMON_TABLE_HEADER sHeader; - USHORT ptrTransmitterInfo; - USHORT ptrEncoderInfo; - USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary. - ASIC_TRANSMITTER_INFO asTransmitterInfo[1]; - ASIC_ENCODER_INFO asEncoderInfo[1]; -}ATOM_DISP_OUT_INFO_V2; - -// DispDevicePriorityInfo -typedef struct _ATOM_DISPLAY_DEVICE_PRIORITY_INFO -{ - ATOM_COMMON_TABLE_HEADER sHeader; - USHORT asDevicePriority[16]; -}ATOM_DISPLAY_DEVICE_PRIORITY_INFO; - -//ProcessAuxChannelTransactionTable -typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS -{ - USHORT lpAuxRequest; - USHORT lpDataOut; - UCHAR ucChannelID; - union - { - UCHAR ucReplyStatus; - UCHAR ucDelay; - }; - UCHAR ucDataOutLen; - UCHAR ucReserved; -}PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS; - -//ProcessAuxChannelTransactionTable -typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 -{ - USHORT lpAuxRequest; - USHORT lpDataOut; - UCHAR ucChannelID; - union - { - UCHAR ucReplyStatus; - UCHAR ucDelay; - }; - UCHAR ucDataOutLen; - UCHAR ucHPD_ID; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6 -}PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2; - -#define PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS - -//GetSinkType - -typedef struct _DP_ENCODER_SERVICE_PARAMETERS -{ - USHORT ucLinkClock; - union - { - UCHAR ucConfig; // for DP training command - UCHAR ucI2cId; // use for GET_SINK_TYPE command - }; - UCHAR ucAction; - UCHAR ucStatus; - UCHAR ucLaneNum; - UCHAR ucReserved[2]; -}DP_ENCODER_SERVICE_PARAMETERS; - -// ucAction -#define ATOM_DP_ACTION_GET_SINK_TYPE 0x01 -/* obselete */ -#define ATOM_DP_ACTION_TRAINING_START 0x02 -#define ATOM_DP_ACTION_TRAINING_COMPLETE 0x03 -#define ATOM_DP_ACTION_TRAINING_PATTERN_SEL 0x04 -#define ATOM_DP_ACTION_SET_VSWING_PREEMP 0x05 -#define ATOM_DP_ACTION_GET_VSWING_PREEMP 0x06 -#define ATOM_DP_ACTION_BLANKING 0x07 - -// ucConfig -#define ATOM_DP_CONFIG_ENCODER_SEL_MASK 0x03 -#define ATOM_DP_CONFIG_DIG1_ENCODER 0x00 -#define ATOM_DP_CONFIG_DIG2_ENCODER 0x01 -#define ATOM_DP_CONFIG_EXTERNAL_ENCODER 0x02 -#define ATOM_DP_CONFIG_LINK_SEL_MASK 0x04 -#define ATOM_DP_CONFIG_LINK_A 0x00 -#define ATOM_DP_CONFIG_LINK_B 0x04 -/* /obselete */ -#define DP_ENCODER_SERVICE_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS - -// DP_TRAINING_TABLE -#define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR ATOM_DP_TRAINING_TBL_ADDR -#define DPCD_SET_SS_CNTL_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 8 ) -#define DPCD_SET_LANE_VSWING_PREEMP_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 16 ) -#define DPCD_SET_TRAINING_PATTERN0_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 24 ) -#define DPCD_SET_TRAINING_PATTERN2_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 32) -#define DPCD_GET_LINKRATE_LANENUM_SS_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 40) -#define DPCD_GET_LANE_STATUS_ADJUST_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 48) -#define DP_I2C_AUX_DDC_WRITE_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 60) -#define DP_I2C_AUX_DDC_WRITE_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 64) -#define DP_I2C_AUX_DDC_READ_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 72) -#define DP_I2C_AUX_DDC_READ_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 76) -#define DP_I2C_AUX_DDC_WRITE_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 80) -#define DP_I2C_AUX_DDC_READ_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 84) - -typedef struct _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS -{ - UCHAR ucI2CSpeed; - union - { - UCHAR ucRegIndex; - UCHAR ucStatus; - }; - USHORT lpI2CDataOut; - UCHAR ucFlag; - UCHAR ucTransBytes; - UCHAR ucSlaveAddr; - UCHAR ucLineNumber; -}PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS; - -#define PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS - -//ucFlag -#define HW_I2C_WRITE 1 -#define HW_I2C_READ 0 -#define I2C_2BYTE_ADDR 0x02 - -typedef struct _SET_HWBLOCK_INSTANCE_PARAMETER_V2 -{ - UCHAR ucHWBlkInst; // HW block instance, 0, 1, 2, ... - UCHAR ucReserved[3]; -}SET_HWBLOCK_INSTANCE_PARAMETER_V2; - -#define HWBLKINST_INSTANCE_MASK 0x07 -#define HWBLKINST_HWBLK_MASK 0xF0 -#define HWBLKINST_HWBLK_SHIFT 0x04 - -//ucHWBlock -#define SELECT_DISP_ENGINE 0 -#define SELECT_DISP_PLL 1 -#define SELECT_DCIO_UNIPHY_LINK0 2 -#define SELECT_DCIO_UNIPHY_LINK1 3 -#define SELECT_DCIO_IMPCAL 4 -#define SELECT_DCIO_DIG 6 -#define SELECT_CRTC_PIXEL_RATE 7 - -/****************************************************************************/ -//Portion VI: Definitinos for vbios MC scratch registers that driver used -/****************************************************************************/ - -#define MC_MISC0__MEMORY_TYPE_MASK 0xF0000000 -#define MC_MISC0__MEMORY_TYPE__GDDR1 0x10000000 -#define MC_MISC0__MEMORY_TYPE__DDR2 0x20000000 -#define MC_MISC0__MEMORY_TYPE__GDDR3 0x30000000 -#define MC_MISC0__MEMORY_TYPE__GDDR4 0x40000000 -#define MC_MISC0__MEMORY_TYPE__GDDR5 0x50000000 -#define MC_MISC0__MEMORY_TYPE__DDR3 0xB0000000 - -/****************************************************************************/ -//Portion VI: Definitinos being oboselete -/****************************************************************************/ - -//========================================================================================== -//Remove the definitions below when driver is ready! -typedef struct _ATOM_DAC_INFO -{ - ATOM_COMMON_TABLE_HEADER sHeader; - USHORT usMaxFrequency; // in 10kHz unit - USHORT usReserved; -}ATOM_DAC_INFO; - - -typedef struct _COMPASSIONATE_DATA -{ - ATOM_COMMON_TABLE_HEADER sHeader; - - //============================== DAC1 portion - UCHAR ucDAC1_BG_Adjustment; - UCHAR ucDAC1_DAC_Adjustment; - USHORT usDAC1_FORCE_Data; - //============================== DAC2 portion - UCHAR ucDAC2_CRT2_BG_Adjustment; - UCHAR ucDAC2_CRT2_DAC_Adjustment; - USHORT usDAC2_CRT2_FORCE_Data; - USHORT usDAC2_CRT2_MUX_RegisterIndex; - UCHAR ucDAC2_CRT2_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low - UCHAR ucDAC2_NTSC_BG_Adjustment; - UCHAR ucDAC2_NTSC_DAC_Adjustment; - USHORT usDAC2_TV1_FORCE_Data; - USHORT usDAC2_TV1_MUX_RegisterIndex; - UCHAR ucDAC2_TV1_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low - UCHAR ucDAC2_CV_BG_Adjustment; - UCHAR ucDAC2_CV_DAC_Adjustment; - USHORT usDAC2_CV_FORCE_Data; - USHORT usDAC2_CV_MUX_RegisterIndex; - UCHAR ucDAC2_CV_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low - UCHAR ucDAC2_PAL_BG_Adjustment; - UCHAR ucDAC2_PAL_DAC_Adjustment; - USHORT usDAC2_TV2_FORCE_Data; -}COMPASSIONATE_DATA; - -/****************************Supported Device Info Table Definitions**********************/ -// ucConnectInfo: -// [7:4] - connector type -// = 1 - VGA connector -// = 2 - DVI-I -// = 3 - DVI-D -// = 4 - DVI-A -// = 5 - SVIDEO -// = 6 - COMPOSITE -// = 7 - LVDS -// = 8 - DIGITAL LINK -// = 9 - SCART -// = 0xA - HDMI_type A -// = 0xB - HDMI_type B -// = 0xE - Special case1 (DVI+DIN) -// Others=TBD -// [3:0] - DAC Associated -// = 0 - no DAC -// = 1 - DACA -// = 2 - DACB -// = 3 - External DAC -// Others=TBD -// - -typedef struct _ATOM_CONNECTOR_INFO -{ -#if ATOM_BIG_ENDIAN - UCHAR bfConnectorType:4; - UCHAR bfAssociatedDAC:4; -#else - UCHAR bfAssociatedDAC:4; - UCHAR bfConnectorType:4; -#endif -}ATOM_CONNECTOR_INFO; - -typedef union _ATOM_CONNECTOR_INFO_ACCESS -{ - ATOM_CONNECTOR_INFO sbfAccess; - UCHAR ucAccess; -}ATOM_CONNECTOR_INFO_ACCESS; - -typedef struct _ATOM_CONNECTOR_INFO_I2C -{ - ATOM_CONNECTOR_INFO_ACCESS sucConnectorInfo; - ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; -}ATOM_CONNECTOR_INFO_I2C; - - -typedef struct _ATOM_SUPPORTED_DEVICES_INFO -{ - ATOM_COMMON_TABLE_HEADER sHeader; - USHORT usDeviceSupport; - ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO]; -}ATOM_SUPPORTED_DEVICES_INFO; - -#define NO_INT_SRC_MAPPED 0xFF - -typedef struct _ATOM_CONNECTOR_INC_SRC_BITMAP -{ - UCHAR ucIntSrcBitmap; -}ATOM_CONNECTOR_INC_SRC_BITMAP; - -typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2 -{ - ATOM_COMMON_TABLE_HEADER sHeader; - USHORT usDeviceSupport; - ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; - ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; -}ATOM_SUPPORTED_DEVICES_INFO_2; - -typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 -{ - ATOM_COMMON_TABLE_HEADER sHeader; - USHORT usDeviceSupport; - ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE]; - ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE]; -}ATOM_SUPPORTED_DEVICES_INFO_2d1; - -#define ATOM_SUPPORTED_DEVICES_INFO_LAST ATOM_SUPPORTED_DEVICES_INFO_2d1 - - - -typedef struct _ATOM_MISC_CONTROL_INFO -{ - USHORT usFrequency; - UCHAR ucPLL_ChargePump; // PLL charge-pump gain control - UCHAR ucPLL_DutyCycle; // PLL duty cycle control - UCHAR ucPLL_VCO_Gain; // PLL VCO gain control - UCHAR ucPLL_VoltageSwing; // PLL driver voltage swing control -}ATOM_MISC_CONTROL_INFO; - - -#define ATOM_MAX_MISC_INFO 4 - -typedef struct _ATOM_TMDS_INFO -{ - ATOM_COMMON_TABLE_HEADER sHeader; - USHORT usMaxFrequency; // in 10Khz - ATOM_MISC_CONTROL_INFO asMiscInfo[ATOM_MAX_MISC_INFO]; -}ATOM_TMDS_INFO; - - -typedef struct _ATOM_ENCODER_ANALOG_ATTRIBUTE -{ - UCHAR ucTVStandard; //Same as TV standards defined above, - UCHAR ucPadding[1]; -}ATOM_ENCODER_ANALOG_ATTRIBUTE; - -typedef struct _ATOM_ENCODER_DIGITAL_ATTRIBUTE -{ - UCHAR ucAttribute; //Same as other digital encoder attributes defined above - UCHAR ucPadding[1]; -}ATOM_ENCODER_DIGITAL_ATTRIBUTE; - -typedef union _ATOM_ENCODER_ATTRIBUTE -{ - ATOM_ENCODER_ANALOG_ATTRIBUTE sAlgAttrib; - ATOM_ENCODER_DIGITAL_ATTRIBUTE sDigAttrib; -}ATOM_ENCODER_ATTRIBUTE; - - -typedef struct _DVO_ENCODER_CONTROL_PARAMETERS -{ - USHORT usPixelClock; - USHORT usEncoderID; - UCHAR ucDeviceType; //Use ATOM_DEVICE_xxx1_Index to indicate device type only. - UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT - ATOM_ENCODER_ATTRIBUTE usDevAttr; -}DVO_ENCODER_CONTROL_PARAMETERS; - -typedef struct _DVO_ENCODER_CONTROL_PS_ALLOCATION -{ - DVO_ENCODER_CONTROL_PARAMETERS sDVOEncoder; - WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion -}DVO_ENCODER_CONTROL_PS_ALLOCATION; - - -#define ATOM_XTMDS_ASIC_SI164_ID 1 -#define ATOM_XTMDS_ASIC_SI178_ID 2 -#define ATOM_XTMDS_ASIC_TFP513_ID 3 -#define ATOM_XTMDS_SUPPORTED_SINGLELINK 0x00000001 -#define ATOM_XTMDS_SUPPORTED_DUALLINK 0x00000002 -#define ATOM_XTMDS_MVPU_FPGA 0x00000004 - - -typedef struct _ATOM_XTMDS_INFO -{ - ATOM_COMMON_TABLE_HEADER sHeader; - USHORT usSingleLinkMaxFrequency; - ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //Point the ID on which I2C is used to control external chip - UCHAR ucXtransimitterID; - UCHAR ucSupportedLink; // Bit field, bit0=1, single link supported;bit1=1,dual link supported - UCHAR ucSequnceAlterID; // Even with the same external TMDS asic, it's possible that the program seqence alters - // due to design. This ID is used to alert driver that the sequence is not "standard"! - UCHAR ucMasterAddress; // Address to control Master xTMDS Chip - UCHAR ucSlaveAddress; // Address to control Slave xTMDS Chip -}ATOM_XTMDS_INFO; - -typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS -{ - UCHAR ucEnable; // ATOM_ENABLE=On or ATOM_DISABLE=Off - UCHAR ucDevice; // ATOM_DEVICE_DFP1_INDEX.... - UCHAR ucPadding[2]; -}DFP_DPMS_STATUS_CHANGE_PARAMETERS; - -/****************************Legacy Power Play Table Definitions **********************/ - -//Definitions for ulPowerPlayMiscInfo -#define ATOM_PM_MISCINFO_SPLIT_CLOCK 0x00000000L -#define ATOM_PM_MISCINFO_USING_MCLK_SRC 0x00000001L -#define ATOM_PM_MISCINFO_USING_SCLK_SRC 0x00000002L - -#define ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT 0x00000004L -#define ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH 0x00000008L - -#define ATOM_PM_MISCINFO_LOAD_PERFORMANCE_EN 0x00000010L - -#define ATOM_PM_MISCINFO_ENGINE_CLOCK_CONTRL_EN 0x00000020L -#define ATOM_PM_MISCINFO_MEMORY_CLOCK_CONTRL_EN 0x00000040L -#define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE 0x00000080L //When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program - -#define ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN 0x00000100L -#define ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN 0x00000200L -#define ATOM_PM_MISCINFO_ASIC_SLEEP_MODE_EN 0x00000400L -#define ATOM_PM_MISCINFO_LOAD_BALANCE_EN 0x00000800L -#define ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE 0x00001000L -#define ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE 0x00002000L -#define ATOM_PM_MISCINFO_LOW_LCD_REFRESH_RATE 0x00004000L - -#define ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE 0x00008000L -#define ATOM_PM_MISCINFO_OVER_CLOCK_MODE 0x00010000L -#define ATOM_PM_MISCINFO_OVER_DRIVE_MODE 0x00020000L -#define ATOM_PM_MISCINFO_POWER_SAVING_MODE 0x00040000L -#define ATOM_PM_MISCINFO_THERMAL_DIODE_MODE 0x00080000L - -#define ATOM_PM_MISCINFO_FRAME_MODULATION_MASK 0x00300000L //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-Reserved -#define ATOM_PM_MISCINFO_FRAME_MODULATION_SHIFT 20 - -#define ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE 0x00400000L -#define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2 0x00800000L -#define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4 0x01000000L -#define ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN 0x02000000L //When set, Dynamic -#define ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN 0x04000000L //When set, Dynamic -#define ATOM_PM_MISCINFO_3D_ACCELERATION_EN 0x08000000L //When set, This mode is for acceleated 3D mode - -#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-High Performance, 5- Optimal Performance (Default state with Default clocks) -#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_SHIFT 28 -#define ATOM_PM_MISCINFO_ENABLE_BACK_BIAS 0x80000000L - -#define ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE 0x00000001L -#define ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT 0x00000002L -#define ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN 0x00000004L -#define ATOM_PM_MISCINFO2_FS3D_OVERDRIVE_INFO 0x00000008L -#define ATOM_PM_MISCINFO2_FORCEDLOWPWR_MODE 0x00000010L -#define ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN 0x00000020L -#define ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE 0x00000040L //If this bit is set in multi-pp mode, then driver will pack up one with the minior power consumption. - //If it's not set in any pp mode, driver will use its default logic to pick a pp mode in video playback -#define ATOM_PM_MISCINFO2_NOT_VALID_ON_DC 0x00000080L -#define ATOM_PM_MISCINFO2_STUTTER_MODE_EN 0x00000100L -#define ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE 0x00000200L - -//ucTableFormatRevision=1 -//ucTableContentRevision=1 -typedef struct _ATOM_POWERMODE_INFO -{ - ULONG ulMiscInfo; //The power level should be arranged in ascending order - ULONG ulReserved1; // must set to 0 - ULONG ulReserved2; // must set to 0 - USHORT usEngineClock; - USHORT usMemoryClock; - UCHAR ucVoltageDropIndex; // index to GPIO table - UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate - UCHAR ucMinTemperature; - UCHAR ucMaxTemperature; - UCHAR ucNumPciELanes; // number of PCIE lanes -}ATOM_POWERMODE_INFO; - -//ucTableFormatRevision=2 -//ucTableContentRevision=1 -typedef struct _ATOM_POWERMODE_INFO_V2 -{ - ULONG ulMiscInfo; //The power level should be arranged in ascending order - ULONG ulMiscInfo2; - ULONG ulEngineClock; - ULONG ulMemoryClock; - UCHAR ucVoltageDropIndex; // index to GPIO table - UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate - UCHAR ucMinTemperature; - UCHAR ucMaxTemperature; - UCHAR ucNumPciELanes; // number of PCIE lanes -}ATOM_POWERMODE_INFO_V2; - -//ucTableFormatRevision=2 -//ucTableContentRevision=2 -typedef struct _ATOM_POWERMODE_INFO_V3 -{ - ULONG ulMiscInfo; //The power level should be arranged in ascending order - ULONG ulMiscInfo2; - ULONG ulEngineClock; - ULONG ulMemoryClock; - UCHAR ucVoltageDropIndex; // index to Core (VDDC) votage table - UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate - UCHAR ucMinTemperature; - UCHAR ucMaxTemperature; - UCHAR ucNumPciELanes; // number of PCIE lanes - UCHAR ucVDDCI_VoltageDropIndex; // index to VDDCI votage table -}ATOM_POWERMODE_INFO_V3; - - -#define ATOM_MAX_NUMBEROF_POWER_BLOCK 8 - -#define ATOM_PP_OVERDRIVE_INTBITMAP_AUXWIN 0x01 -#define ATOM_PP_OVERDRIVE_INTBITMAP_OVERDRIVE 0x02 - -#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM63 0x01 -#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1032 0x02 -#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1030 0x03 -#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_MUA6649 0x04 -#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM64 0x05 -#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_F75375 0x06 -#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ASC7512 0x07 // Andigilog - - -typedef struct _ATOM_POWERPLAY_INFO -{ - ATOM_COMMON_TABLE_HEADER sHeader; - UCHAR ucOverdriveThermalController; - UCHAR ucOverdriveI2cLine; - UCHAR ucOverdriveIntBitmap; - UCHAR ucOverdriveControllerAddress; - UCHAR ucSizeOfPowerModeEntry; - UCHAR ucNumOfPowerModeEntries; - ATOM_POWERMODE_INFO asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; -}ATOM_POWERPLAY_INFO; - -typedef struct _ATOM_POWERPLAY_INFO_V2 -{ - ATOM_COMMON_TABLE_HEADER sHeader; - UCHAR ucOverdriveThermalController; - UCHAR ucOverdriveI2cLine; - UCHAR ucOverdriveIntBitmap; - UCHAR ucOverdriveControllerAddress; - UCHAR ucSizeOfPowerModeEntry; - UCHAR ucNumOfPowerModeEntries; - ATOM_POWERMODE_INFO_V2 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; -}ATOM_POWERPLAY_INFO_V2; - -typedef struct _ATOM_POWERPLAY_INFO_V3 -{ - ATOM_COMMON_TABLE_HEADER sHeader; - UCHAR ucOverdriveThermalController; - UCHAR ucOverdriveI2cLine; - UCHAR ucOverdriveIntBitmap; - UCHAR ucOverdriveControllerAddress; - UCHAR ucSizeOfPowerModeEntry; - UCHAR ucNumOfPowerModeEntries; - ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; -}ATOM_POWERPLAY_INFO_V3; - -/* New PPlib */ -/**************************************************************************/ -typedef struct _ATOM_PPLIB_THERMALCONTROLLER - -{ - UCHAR ucType; // one of ATOM_PP_THERMALCONTROLLER_* - UCHAR ucI2cLine; // as interpreted by DAL I2C - UCHAR ucI2cAddress; - UCHAR ucFanParameters; // Fan Control Parameters. - UCHAR ucFanMinRPM; // Fan Minimum RPM (hundreds) -- for display purposes only. - UCHAR ucFanMaxRPM; // Fan Maximum RPM (hundreds) -- for display purposes only. - UCHAR ucReserved; // ---- - UCHAR ucFlags; // to be defined -} ATOM_PPLIB_THERMALCONTROLLER; - -#define ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK 0x0f -#define ATOM_PP_FANPARAMETERS_NOFAN 0x80 // No fan is connected to this controller. - -#define ATOM_PP_THERMALCONTROLLER_NONE 0 -#define ATOM_PP_THERMALCONTROLLER_LM63 1 // Not used by PPLib -#define ATOM_PP_THERMALCONTROLLER_ADM1032 2 // Not used by PPLib -#define ATOM_PP_THERMALCONTROLLER_ADM1030 3 // Not used by PPLib -#define ATOM_PP_THERMALCONTROLLER_MUA6649 4 // Not used by PPLib -#define ATOM_PP_THERMALCONTROLLER_LM64 5 -#define ATOM_PP_THERMALCONTROLLER_F75375 6 // Not used by PPLib -#define ATOM_PP_THERMALCONTROLLER_RV6xx 7 -#define ATOM_PP_THERMALCONTROLLER_RV770 8 -#define ATOM_PP_THERMALCONTROLLER_ADT7473 9 -#define ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO 11 -#define ATOM_PP_THERMALCONTROLLER_EVERGREEN 12 -#define ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL 0x89 // ADT7473 Fan Control + Internal Thermal Controller - -typedef struct _ATOM_PPLIB_STATE -{ - UCHAR ucNonClockStateIndex; - UCHAR ucClockStateIndices[1]; // variable-sized -} ATOM_PPLIB_STATE; - -typedef struct _ATOM_PPLIB_FANTABLE -{ - UCHAR ucFanTableFormat; // Change this if the table format changes or version changes so that the other fields are not the same. - UCHAR ucTHyst; // Temperature hysteresis. Integer. - USHORT usTMin; // The temperature, in 0.01 centigrades, below which we just run at a minimal PWM. - USHORT usTMed; // The middle temperature where we change slopes. - USHORT usTHigh; // The high point above TMed for adjusting the second slope. - USHORT usPWMMin; // The minimum PWM value in percent (0.01% increments). - USHORT usPWMMed; // The PWM value (in percent) at TMed. - USHORT usPWMHigh; // The PWM value at THigh. -} ATOM_PPLIB_FANTABLE; - -typedef struct _ATOM_PPLIB_EXTENDEDHEADER -{ - USHORT usSize; - ULONG ulMaxEngineClock; // For Overdrive. - ULONG ulMaxMemoryClock; // For Overdrive. - // Add extra system parameters here, always adjust size to include all fields. -} ATOM_PPLIB_EXTENDEDHEADER; - -//// ATOM_PPLIB_POWERPLAYTABLE::ulPlatformCaps -#define ATOM_PP_PLATFORM_CAP_BACKBIAS 1 -#define ATOM_PP_PLATFORM_CAP_POWERPLAY 2 -#define ATOM_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 4 -#define ATOM_PP_PLATFORM_CAP_ASPM_L0s 8 -#define ATOM_PP_PLATFORM_CAP_ASPM_L1 16 -#define ATOM_PP_PLATFORM_CAP_HARDWAREDC 32 -#define ATOM_PP_PLATFORM_CAP_GEMINIPRIMARY 64 -#define ATOM_PP_PLATFORM_CAP_STEPVDDC 128 -#define ATOM_PP_PLATFORM_CAP_VOLTAGECONTROL 256 -#define ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL 512 -#define ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1 1024 -#define ATOM_PP_PLATFORM_CAP_HTLINKCONTROL 2048 -#define ATOM_PP_PLATFORM_CAP_MVDDCONTROL 4096 -#define ATOM_PP_PLATFORM_CAP_GOTO_BOOT_ON_ALERT 0x2000 // Go to boot state on alerts, e.g. on an AC->DC transition. -#define ATOM_PP_PLATFORM_CAP_DONT_WAIT_FOR_VBLANK_ON_ALERT 0x4000 // Do NOT wait for VBLANK during an alert (e.g. AC->DC transition). -#define ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL 0x8000 // Does the driver control VDDCI independently from VDDC. -#define ATOM_PP_PLATFORM_CAP_REGULATOR_HOT 0x00010000 // Enable the 'regulator hot' feature. -#define ATOM_PP_PLATFORM_CAP_BACO 0x00020000 // Does the driver supports BACO state. - -typedef struct _ATOM_PPLIB_POWERPLAYTABLE -{ - ATOM_COMMON_TABLE_HEADER sHeader; - - UCHAR ucDataRevision; - - UCHAR ucNumStates; - UCHAR ucStateEntrySize; - UCHAR ucClockInfoSize; - UCHAR ucNonClockSize; - - // offset from start of this table to array of ucNumStates ATOM_PPLIB_STATE structures - USHORT usStateArrayOffset; - - // offset from start of this table to array of ASIC-specific structures, - // currently ATOM_PPLIB_CLOCK_INFO. - USHORT usClockInfoArrayOffset; - - // offset from start of this table to array of ATOM_PPLIB_NONCLOCK_INFO - USHORT usNonClockInfoArrayOffset; - - USHORT usBackbiasTime; // in microseconds - USHORT usVoltageTime; // in microseconds - USHORT usTableSize; //the size of this structure, or the extended structure - - ULONG ulPlatformCaps; // See ATOM_PPLIB_CAPS_* - - ATOM_PPLIB_THERMALCONTROLLER sThermalController; - - USHORT usBootClockInfoOffset; - USHORT usBootNonClockInfoOffset; - -} ATOM_PPLIB_POWERPLAYTABLE; - -typedef struct _ATOM_PPLIB_POWERPLAYTABLE2 -{ - ATOM_PPLIB_POWERPLAYTABLE basicTable; - UCHAR ucNumCustomThermalPolicy; - USHORT usCustomThermalPolicyArrayOffset; -}ATOM_PPLIB_POWERPLAYTABLE2, *LPATOM_PPLIB_POWERPLAYTABLE2; - -typedef struct _ATOM_PPLIB_POWERPLAYTABLE3 -{ - ATOM_PPLIB_POWERPLAYTABLE2 basicTable2; - USHORT usFormatID; // To be used ONLY by PPGen. - USHORT usFanTableOffset; - USHORT usExtendendedHeaderOffset; -} ATOM_PPLIB_POWERPLAYTABLE3, *LPATOM_PPLIB_POWERPLAYTABLE3; - -//// ATOM_PPLIB_NONCLOCK_INFO::usClassification -#define ATOM_PPLIB_CLASSIFICATION_UI_MASK 0x0007 -#define ATOM_PPLIB_CLASSIFICATION_UI_SHIFT 0 -#define ATOM_PPLIB_CLASSIFICATION_UI_NONE 0 -#define ATOM_PPLIB_CLASSIFICATION_UI_BATTERY 1 -#define ATOM_PPLIB_CLASSIFICATION_UI_BALANCED 3 -#define ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE 5 -// 2, 4, 6, 7 are reserved - -#define ATOM_PPLIB_CLASSIFICATION_BOOT 0x0008 -#define ATOM_PPLIB_CLASSIFICATION_THERMAL 0x0010 -#define ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE 0x0020 -#define ATOM_PPLIB_CLASSIFICATION_REST 0x0040 -#define ATOM_PPLIB_CLASSIFICATION_FORCED 0x0080 -#define ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE 0x0100 -#define ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE 0x0200 -#define ATOM_PPLIB_CLASSIFICATION_UVDSTATE 0x0400 -#define ATOM_PPLIB_CLASSIFICATION_3DLOW 0x0800 -#define ATOM_PPLIB_CLASSIFICATION_ACPI 0x1000 -#define ATOM_PPLIB_CLASSIFICATION_HD2STATE 0x2000 -#define ATOM_PPLIB_CLASSIFICATION_HDSTATE 0x4000 -#define ATOM_PPLIB_CLASSIFICATION_SDSTATE 0x8000 - -//// ATOM_PPLIB_NONCLOCK_INFO::ulCapsAndSettings -#define ATOM_PPLIB_SINGLE_DISPLAY_ONLY 0x00000001 -#define ATOM_PPLIB_SUPPORTS_VIDEO_PLAYBACK 0x00000002 - -// 0 is 2.5Gb/s, 1 is 5Gb/s -#define ATOM_PPLIB_PCIE_LINK_SPEED_MASK 0x00000004 -#define ATOM_PPLIB_PCIE_LINK_SPEED_SHIFT 2 - -// lanes - 1: 1, 2, 4, 8, 12, 16 permitted by PCIE spec -#define ATOM_PPLIB_PCIE_LINK_WIDTH_MASK 0x000000F8 -#define ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT 3 - -// lookup into reduced refresh-rate table -#define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_MASK 0x00000F00 -#define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_SHIFT 8 - -#define ATOM_PPLIB_LIMITED_REFRESHRATE_UNLIMITED 0 -#define ATOM_PPLIB_LIMITED_REFRESHRATE_50HZ 1 -// 2-15 TBD as needed. - -#define ATOM_PPLIB_SOFTWARE_DISABLE_LOADBALANCING 0x00001000 -#define ATOM_PPLIB_SOFTWARE_ENABLE_SLEEP_FOR_TIMESTAMPS 0x00002000 -#define ATOM_PPLIB_DISALLOW_ON_DC 0x00004000 -#define ATOM_PPLIB_ENABLE_VARIBRIGHT 0x00008000 - -//memory related flags -#define ATOM_PPLIB_SWSTATE_MEMORY_DLL_OFF 0x000010000 - -//M3 Arb //2bits, current 3 sets of parameters in total -#define ATOM_PPLIB_M3ARB_MASK 0x00060000 -#define ATOM_PPLIB_M3ARB_SHIFT 17 - -// Contained in an array starting at the offset -// in ATOM_PPLIB_POWERPLAYTABLE::usNonClockInfoArrayOffset. -// referenced from ATOM_PPLIB_STATE_INFO::ucNonClockStateIndex -typedef struct _ATOM_PPLIB_NONCLOCK_INFO -{ - USHORT usClassification; - UCHAR ucMinTemperature; - UCHAR ucMaxTemperature; - ULONG ulCapsAndSettings; - UCHAR ucRequiredPower; - UCHAR ucUnused1[3]; -} ATOM_PPLIB_NONCLOCK_INFO; - -// Contained in an array starting at the offset -// in ATOM_PPLIB_POWERPLAYTABLE::usClockInfoArrayOffset. -// referenced from ATOM_PPLIB_STATE::ucClockStateIndices -#define ATOM_PPLIB_NONCLOCKINFO_VER1 12 -#define ATOM_PPLIB_NONCLOCKINFO_VER2 24 - -typedef struct _ATOM_PPLIB_R600_CLOCK_INFO -{ - USHORT usEngineClockLow; - UCHAR ucEngineClockHigh; - - USHORT usMemoryClockLow; - UCHAR ucMemoryClockHigh; - - USHORT usVDDC; - USHORT usUnused1; - USHORT usUnused2; - - ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_* - -} ATOM_PPLIB_R600_CLOCK_INFO; - -// ulFlags in ATOM_PPLIB_R600_CLOCK_INFO -#define ATOM_PPLIB_R600_FLAGS_PCIEGEN2 1 -#define ATOM_PPLIB_R600_FLAGS_UVDSAFE 2 -#define ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE 4 -#define ATOM_PPLIB_R600_FLAGS_MEMORY_ODT_OFF 8 -#define ATOM_PPLIB_R600_FLAGS_MEMORY_DLL_OFF 16 -#define ATOM_PPLIB_R600_FLAGS_LOWPOWER 32 // On the RV770 use 'low power' setting (sequencer S0). - -typedef struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO -{ - USHORT usEngineClockLow; - UCHAR ucEngineClockHigh; - - USHORT usMemoryClockLow; - UCHAR ucMemoryClockHigh; - - USHORT usVDDC; - USHORT usVDDCI; - USHORT usUnused; - - ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_* - -} ATOM_PPLIB_EVERGREEN_CLOCK_INFO; - -typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO - -{ - USHORT usLowEngineClockLow; // Low Engine clock in MHz (the same way as on the R600). - UCHAR ucLowEngineClockHigh; - USHORT usHighEngineClockLow; // High Engine clock in MHz. - UCHAR ucHighEngineClockHigh; - USHORT usMemoryClockLow; // For now one of the ATOM_PPLIB_RS780_SPMCLK_XXXX constants. - UCHAR ucMemoryClockHigh; // Currentyl unused. - UCHAR ucPadding; // For proper alignment and size. - USHORT usVDDC; // For the 780, use: None, Low, High, Variable - UCHAR ucMaxHTLinkWidth; // From SBIOS - {2, 4, 8, 16} - UCHAR ucMinHTLinkWidth; // From SBIOS - {2, 4, 8, 16}. Effective only if CDLW enabled. Minimum down stream width could be bigger as display BW requirement. - USHORT usHTLinkFreq; // See definition ATOM_PPLIB_RS780_HTLINKFREQ_xxx or in MHz(>=200). - ULONG ulFlags; -} ATOM_PPLIB_RS780_CLOCK_INFO; - -#define ATOM_PPLIB_RS780_VOLTAGE_NONE 0 -#define ATOM_PPLIB_RS780_VOLTAGE_LOW 1 -#define ATOM_PPLIB_RS780_VOLTAGE_HIGH 2 -#define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE 3 - -#define ATOM_PPLIB_RS780_SPMCLK_NONE 0 // We cannot change the side port memory clock, leave it as it is. -#define ATOM_PPLIB_RS780_SPMCLK_LOW 1 -#define ATOM_PPLIB_RS780_SPMCLK_HIGH 2 - -#define ATOM_PPLIB_RS780_HTLINKFREQ_NONE 0 -#define ATOM_PPLIB_RS780_HTLINKFREQ_LOW 1 -#define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH 2 - -/**************************************************************************/ - - -// Following definitions are for compatiblity issue in different SW components. -#define ATOM_MASTER_DATA_TABLE_REVISION 0x01 -#define Object_Info Object_Header -#define AdjustARB_SEQ MC_InitParameter -#define VRAM_GPIO_DetectionInfo VoltageObjectInfo -#define ASIC_VDDCI_Info ASIC_ProfilingInfo -#define ASIC_MVDDQ_Info MemoryTrainingInfo -#define SS_Info PPLL_SS_Info -#define ASIC_MVDDC_Info ASIC_InternalSS_Info -#define DispDevicePriorityInfo SaveRestoreInfo -#define DispOutInfo TV_VideoMode - - -#define ATOM_ENCODER_OBJECT_TABLE ATOM_OBJECT_TABLE -#define ATOM_CONNECTOR_OBJECT_TABLE ATOM_OBJECT_TABLE - -//New device naming, remove them when both DAL/VBIOS is ready -#define DFP2I_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS -#define DFP2I_OUTPUT_CONTROL_PS_ALLOCATION DFP2I_OUTPUT_CONTROL_PARAMETERS - -#define DFP1X_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS -#define DFP1X_OUTPUT_CONTROL_PS_ALLOCATION DFP1X_OUTPUT_CONTROL_PARAMETERS - -#define DFP1I_OUTPUT_CONTROL_PARAMETERS DFP1_OUTPUT_CONTROL_PARAMETERS -#define DFP1I_OUTPUT_CONTROL_PS_ALLOCATION DFP1_OUTPUT_CONTROL_PS_ALLOCATION - -#define ATOM_DEVICE_DFP1I_SUPPORT ATOM_DEVICE_DFP1_SUPPORT -#define ATOM_DEVICE_DFP1X_SUPPORT ATOM_DEVICE_DFP2_SUPPORT - -#define ATOM_DEVICE_DFP1I_INDEX ATOM_DEVICE_DFP1_INDEX -#define ATOM_DEVICE_DFP1X_INDEX ATOM_DEVICE_DFP2_INDEX - -#define ATOM_DEVICE_DFP2I_INDEX 0x00000009 -#define ATOM_DEVICE_DFP2I_SUPPORT (0x1L << ATOM_DEVICE_DFP2I_INDEX) - -#define ATOM_S0_DFP1I ATOM_S0_DFP1 -#define ATOM_S0_DFP1X ATOM_S0_DFP2 - -#define ATOM_S0_DFP2I 0x00200000L -#define ATOM_S0_DFP2Ib2 0x20 - -#define ATOM_S2_DFP1I_DPMS_STATE ATOM_S2_DFP1_DPMS_STATE -#define ATOM_S2_DFP1X_DPMS_STATE ATOM_S2_DFP2_DPMS_STATE - -#define ATOM_S2_DFP2I_DPMS_STATE 0x02000000L -#define ATOM_S2_DFP2I_DPMS_STATEb3 0x02 - -#define ATOM_S3_DFP2I_ACTIVEb1 0x02 - -#define ATOM_S3_DFP1I_ACTIVE ATOM_S3_DFP1_ACTIVE -#define ATOM_S3_DFP1X_ACTIVE ATOM_S3_DFP2_ACTIVE - -#define ATOM_S3_DFP2I_ACTIVE 0x00000200L - -#define ATOM_S3_DFP1I_CRTC_ACTIVE ATOM_S3_DFP1_CRTC_ACTIVE -#define ATOM_S3_DFP1X_CRTC_ACTIVE ATOM_S3_DFP2_CRTC_ACTIVE -#define ATOM_S3_DFP2I_CRTC_ACTIVE 0x02000000L - -#define ATOM_S3_DFP2I_CRTC_ACTIVEb3 0x02 -#define ATOM_S5_DOS_REQ_DFP2Ib1 0x02 - -#define ATOM_S5_DOS_REQ_DFP2I 0x0200 -#define ATOM_S6_ACC_REQ_DFP1I ATOM_S6_ACC_REQ_DFP1 -#define ATOM_S6_ACC_REQ_DFP1X ATOM_S6_ACC_REQ_DFP2 - -#define ATOM_S6_ACC_REQ_DFP2Ib3 0x02 -#define ATOM_S6_ACC_REQ_DFP2I 0x02000000L - -#define TMDS1XEncoderControl DVOEncoderControl -#define DFP1XOutputControl DVOOutputControl - -#define ExternalDFPOutputControl DFP1XOutputControl -#define EnableExternalTMDS_Encoder TMDS1XEncoderControl - -#define DFP1IOutputControl TMDSAOutputControl -#define DFP2IOutputControl LVTMAOutputControl - -#define DAC1_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS -#define DAC1_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION - -#define DAC2_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS -#define DAC2_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION - -#define ucDac1Standard ucDacStandard -#define ucDac2Standard ucDacStandard - -#define TMDS1EncoderControl TMDSAEncoderControl -#define TMDS2EncoderControl LVTMAEncoderControl - -#define DFP1OutputControl TMDSAOutputControl -#define DFP2OutputControl LVTMAOutputControl -#define CRT1OutputControl DAC1OutputControl -#define CRT2OutputControl DAC2OutputControl - -//These two lines will be removed for sure in a few days, will follow up with Michael V. -#define EnableLVDS_SS EnableSpreadSpectrumOnPPLL -#define ENABLE_LVDS_SS_PARAMETERS_V3 ENABLE_SPREAD_SPECTRUM_ON_PPLL - -//#define ATOM_S2_CRT1_DPMS_STATE 0x00010000L -//#define ATOM_S2_LCD1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE -//#define ATOM_S2_TV1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE -//#define ATOM_S2_DFP1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE -//#define ATOM_S2_CRT2_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE - -#define ATOM_S6_ACC_REQ_TV2 0x00400000L -#define ATOM_DEVICE_TV2_INDEX 0x00000006 -#define ATOM_DEVICE_TV2_SUPPORT (0x1L << ATOM_DEVICE_TV2_INDEX) -#define ATOM_S0_TV2 0x00100000L -#define ATOM_S3_TV2_ACTIVE ATOM_S3_DFP6_ACTIVE -#define ATOM_S3_TV2_CRTC_ACTIVE ATOM_S3_DFP6_CRTC_ACTIVE - -// -#define ATOM_S2_CRT1_DPMS_STATE 0x00010000L -#define ATOM_S2_LCD1_DPMS_STATE 0x00020000L -#define ATOM_S2_TV1_DPMS_STATE 0x00040000L -#define ATOM_S2_DFP1_DPMS_STATE 0x00080000L -#define ATOM_S2_CRT2_DPMS_STATE 0x00100000L -#define ATOM_S2_LCD2_DPMS_STATE 0x00200000L -#define ATOM_S2_TV2_DPMS_STATE 0x00400000L -#define ATOM_S2_DFP2_DPMS_STATE 0x00800000L -#define ATOM_S2_CV_DPMS_STATE 0x01000000L -#define ATOM_S2_DFP3_DPMS_STATE 0x02000000L -#define ATOM_S2_DFP4_DPMS_STATE 0x04000000L -#define ATOM_S2_DFP5_DPMS_STATE 0x08000000L - -#define ATOM_S2_CRT1_DPMS_STATEb2 0x01 -#define ATOM_S2_LCD1_DPMS_STATEb2 0x02 -#define ATOM_S2_TV1_DPMS_STATEb2 0x04 -#define ATOM_S2_DFP1_DPMS_STATEb2 0x08 -#define ATOM_S2_CRT2_DPMS_STATEb2 0x10 -#define ATOM_S2_LCD2_DPMS_STATEb2 0x20 -#define ATOM_S2_TV2_DPMS_STATEb2 0x40 -#define ATOM_S2_DFP2_DPMS_STATEb2 0x80 -#define ATOM_S2_CV_DPMS_STATEb3 0x01 -#define ATOM_S2_DFP3_DPMS_STATEb3 0x02 -#define ATOM_S2_DFP4_DPMS_STATEb3 0x04 -#define ATOM_S2_DFP5_DPMS_STATEb3 0x08 - -#define ATOM_S3_ASIC_GUI_ENGINE_HUNGb3 0x20 -#define ATOM_S3_ALLOW_FAST_PWR_SWITCHb3 0x40 -#define ATOM_S3_RQST_GPU_USE_MIN_PWRb3 0x80 - -/*********************************************************************************/ - -#pragma pack() // BIOS data must use byte aligment - -#endif /* _ATOMBIOS_H */ diff --git a/src/AtomBios/includes/regsdef.h b/src/AtomBios/includes/regsdef.h deleted file mode 100644 index e557ac04..00000000 --- a/src/AtomBios/includes/regsdef.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright 2006-2007 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -//This is a dummy file used by driver-parser during compilation. -//Without this file, compatibility will be broken among ASICs and BIOs vs. driver -//James H. Apr. 22/03 diff --git a/src/Makefile.am b/src/Makefile.am index 26ceda7f..20d65513 100644 --- a/src/Makefile.am +++ b/src/Makefile.am @@ -28,47 +28,15 @@ radeon_drv_la_LIBADD = $(LIBDRM_RADEON_LIBS) -if DRI -RADEON_DRI_SRCS = radeon_dri.c -radeon_drv_la_LIBADD += $(DRI_LIBS) -endif - -RADEON_ATOMBIOS_SOURCES = \ - AtomBios/CD_Operations.c \ - AtomBios/Decoder.c \ - AtomBios/hwserv_drv.c \ - AtomBios/includes/atombios.h \ - AtomBios/includes/CD_binding.h \ - AtomBios/includes/CD_Common_Types.h \ - AtomBios/includes/CD_Definitions.h \ - AtomBios/includes/CD_hw_services.h \ - AtomBios/includes/CD_Opcodes.h \ - AtomBios/includes/CD_Structs.h \ - AtomBios/includes/Decoder.h \ - AtomBios/includes/ObjectID.h \ - AtomBios/includes/regsdef.h - -if XF86DRM_MODE RADEON_KMS_SRCS=radeon_dri2.c radeon_kms.c drmmode_display.c radeon_vbo.c -endif -if USE_EXA RADEON_EXA_SOURCES = radeon_exa.c r600_exa.c r6xx_accel.c r600_textured_videofuncs.c r600_shader.c radeon_exa_shared.c \ evergreen_exa.c evergreen_accel.c evergreen_shader.c evergreen_textured_videofuncs.c cayman_accel.c cayman_shader.c -endif AM_CFLAGS = \ @LIBDRM_RADEON_CFLAGS@ \ @XORG_CFLAGS@ \ - @DRI_CFLAGS@ \ - @LIBUDEV_CFLAGS@ \ - -DDISABLE_EASF \ - -DENABLE_ALL_SERVICE_FUNCTIONS \ - -DATOM_BIOS \ - -DATOM_BIOS_PARSER \ - -DDRIVER_PARSER - -INCLUDES = -I$(srcdir)/AtomBios/includes + @LIBUDEV_CFLAGS@ if XSERVER_LIBPCIACCESS ati_drv_la_LIBADD = $(PCIACCESS_LIBS) @@ -89,40 +57,14 @@ radeon_drv_la_LTLIBRARIES = radeon_drv.la radeon_drv_la_LDFLAGS = -module -avoid-version radeon_drv_ladir = @moduledir@/drivers radeon_drv_la_SOURCES = \ - radeon_accel.c radeon_cursor.c radeon_legacy_memory.c \ - radeon_driver.c radeon_video.c radeon_bios.c radeon_mm_i2c.c \ - radeon_vip.c radeon_misc.c radeon_probe.c \ - legacy_crtc.c legacy_output.c \ - radeon_textured_video.c radeon_xvmc.c radeon_pm.c \ - radeon_crtc.c radeon_output.c radeon_modes.c radeon_tv.c \ - $(RADEON_ATOMBIOS_SOURCES) radeon_atombios.c radeon_atomwrapper.c \ - $(RADEON_DRI_SRCS) $(RADEON_EXA_SOURCES) atombios_output.c atombios_crtc.c \ + radeon_accel.c radeon_legacy_memory.c \ + radeon_driver.c radeon_video.c \ + radeon_misc.c radeon_probe.c \ + radeon_textured_video.c radeon_xvmc.c \ + $(RADEON_EXA_SOURCES) \ $(RADEON_KMS_SRCS) -theatre_detect_drv_la_LTLIBRARIES = theatre_detect_drv.la -theatre_detect_drv_la_LDFLAGS = -module -avoid-version -theatre_detect_drv_ladir = @moduledir@/multimedia -theatre_detect_drv_la_SOURCES = \ - theatre_detect.c theatre_detect_module.c - -theatre_drv_la_LTLIBRARIES = theatre_drv.la -theatre_drv_la_LDFLAGS = -module -avoid-version -theatre_drv_ladir = @moduledir@/multimedia - -theatre_drv_la_SOURCES = \ - theatre.c theatre_module.c - -theatre200_drv_la_LTLIBRARIES = theatre200_drv.la -theatre200_drv_la_LDFLAGS = -module -avoid-version -theatre200_drv_ladir = @moduledir@/multimedia -theatre200_drv_la_CFLAGS = \ - $(AM_CFLAGS) -DMICROC_DIR=\"$(theatre200_drv_ladir)\" -theatre200_drv_la_SOURCES = \ - theatre200.c theatre200_module.c - EXTRA_DIST = \ - radeon_render.c \ - radeon_accelfuncs.c \ radeon_textured_videofuncs.c \ r600_reg.h \ r600_reg_auto_r6xx.h \ @@ -141,11 +83,8 @@ EXTRA_DIST = \ ati.h \ ativersion.h \ bicubic_table.h \ - generic_bus.h \ radeon_commonfuncs.c \ - radeon_dri.h \ radeon_drm.h \ - radeon_dummy_bufmgr.h \ radeon_exa_render.c \ radeon_exa_funcs.c \ radeon_exa_shared.h \ @@ -156,13 +95,7 @@ EXTRA_DIST = \ radeon_version.h \ radeon_vbo.h \ radeon_video.h \ - radeon_tv.h \ - radeon_atomwrapper.h \ simple_list.h \ - theatre200.h \ - theatre_detect.h \ - theatre.h \ - theatre_reg.h \ atipciids.h \ atipcirename.h \ ati_pciids_gen.h \ @@ -172,6 +105,5 @@ EXTRA_DIST = \ radeon_pci_device_match_gen.h \ pcidb/ati_pciids.csv \ pcidb/parse_pci_ids.pl \ - radeon_atombios.h \ radeon_dri2.h \ drmmode_display.h diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c deleted file mode 100644 index d0eefa5f..00000000 --- a/src/atombios_crtc.c +++ /dev/null @@ -1,1541 +0,0 @@ -/* - * Copyright © 2007 Red Hat, Inc. - * Copyright 2007 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - * - * Authors: - * Dave Airlie <airlied@redhat.com> - * Alex Deucher <alexander.deucher@amd.com> - * - */ -/* - * avivo crtc handling functions. - */ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif -/* DPMS */ -#ifdef HAVE_XEXTPROTO_71 -#include <X11/extensions/dpmsconst.h> -#else -#define DPMS_SERVER -#include <X11/extensions/dpms.h> -#endif - -#include <math.h> -#include "radeon.h" -#include "radeon_reg.h" -#include "radeon_macros.h" -#include "radeon_atombios.h" - -#ifdef XF86DRI -#define _XF86DRI_SERVER_ -#include "radeon_drm.h" -#include "sarea.h" -#endif - -extern int -atombios_get_encoder_mode(xf86OutputPtr output); - -extern void -RADEONInitCrtcBase(xf86CrtcPtr crtc, RADEONSavePtr save, - int x, int y); -extern void -RADEONInitCrtc2Base(xf86CrtcPtr crtc, RADEONSavePtr save, - int x, int y); -extern void -RADEONRestoreCrtcBase(ScrnInfoPtr pScrn, - RADEONSavePtr restore); -extern void -RADEONRestoreCrtc2Base(ScrnInfoPtr pScrn, - RADEONSavePtr restore); -extern void -RADEONInitCommonRegisters(RADEONSavePtr save, RADEONInfoPtr info); -extern void -RADEONInitSurfaceCntl(xf86CrtcPtr crtc, RADEONSavePtr save); - -AtomBiosResult -atombios_lock_crtc(atomBiosHandlePtr atomBIOS, int crtc, int lock) -{ - ENABLE_CRTC_PS_ALLOCATION crtc_data; - AtomBiosArgRec data; - unsigned char *space; - - crtc_data.ucCRTC = crtc; - crtc_data.ucEnable = lock; - - data.exec.index = GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters); - data.exec.dataSpace = (void *)&space; - data.exec.pspace = &crtc_data; - - if (RHDAtomBiosFunc(atomBIOS->pScrn, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { - ErrorF("%s CRTC %d success\n", lock? "Lock":"Unlock", crtc); - return ATOM_SUCCESS ; - } - - ErrorF("Lock CRTC failed\n"); - return ATOM_NOT_IMPLEMENTED; -} - -static AtomBiosResult -atombios_enable_crtc(atomBiosHandlePtr atomBIOS, int crtc, int state) -{ - ENABLE_CRTC_PS_ALLOCATION crtc_data; - AtomBiosArgRec data; - unsigned char *space; - - crtc_data.ucCRTC = crtc; - crtc_data.ucEnable = state; - - data.exec.index = GetIndexIntoMasterTable(COMMAND, EnableCRTC); - data.exec.dataSpace = (void *)&space; - data.exec.pspace = &crtc_data; - - if (RHDAtomBiosFunc(atomBIOS->pScrn, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { - ErrorF("%s CRTC %d success\n", state? "Enable":"Disable", crtc); - return ATOM_SUCCESS ; - } - - ErrorF("Enable CRTC failed\n"); - return ATOM_NOT_IMPLEMENTED; -} - -static AtomBiosResult -atombios_enable_crtc_memreq(atomBiosHandlePtr atomBIOS, int crtc, int state) -{ - ENABLE_CRTC_PS_ALLOCATION crtc_data; - AtomBiosArgRec data; - unsigned char *space; - - crtc_data.ucCRTC = crtc; - crtc_data.ucEnable = state; - - data.exec.index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq); - data.exec.dataSpace = (void *)&space; - data.exec.pspace = &crtc_data; - - if (RHDAtomBiosFunc(atomBIOS->pScrn, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { - ErrorF("%s CRTC memreq %d success\n", state? "Enable":"Disable", crtc); - return ATOM_SUCCESS ; - } - - ErrorF("Enable CRTC memreq failed\n"); - return ATOM_NOT_IMPLEMENTED; -} - -static AtomBiosResult -atombios_blank_crtc(atomBiosHandlePtr atomBIOS, int crtc, int state) -{ - BLANK_CRTC_PS_ALLOCATION crtc_data; - unsigned char *space; - AtomBiosArgRec data; - - memset(&crtc_data, 0, sizeof(crtc_data)); - crtc_data.ucCRTC = crtc; - crtc_data.ucBlanking = state; - - data.exec.index = GetIndexIntoMasterTable(COMMAND, BlankCRTC); - data.exec.dataSpace = (void *)&space; - data.exec.pspace = &crtc_data; - - if (RHDAtomBiosFunc(atomBIOS->pScrn, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { - ErrorF("%s CRTC %d success\n", state? "Blank":"Unblank", crtc); - return ATOM_SUCCESS ; - } - - ErrorF("Blank CRTC failed\n"); - return ATOM_NOT_IMPLEMENTED; -} - -void -atombios_crtc_dpms(xf86CrtcPtr crtc, int mode) -{ - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - RADEONInfoPtr info = RADEONPTR(crtc->scrn); - switch (mode) { - case DPMSModeOn: - atombios_enable_crtc(info->atomBIOS, radeon_crtc->crtc_id, 1); - if (IS_DCE3_VARIANT) - atombios_enable_crtc_memreq(info->atomBIOS, radeon_crtc->crtc_id, 1); - atombios_blank_crtc(info->atomBIOS, radeon_crtc->crtc_id, 0); - break; - case DPMSModeStandby: - case DPMSModeSuspend: - case DPMSModeOff: - atombios_blank_crtc(info->atomBIOS, radeon_crtc->crtc_id, 1); - if (IS_DCE3_VARIANT) - atombios_enable_crtc_memreq(info->atomBIOS, radeon_crtc->crtc_id, 0); - atombios_enable_crtc(info->atomBIOS, radeon_crtc->crtc_id, 0); - break; - } -} - -static AtomBiosResult -atombios_set_crtc_timing(xf86CrtcPtr crtc, DisplayModePtr mode) -{ - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - RADEONInfoPtr info = RADEONPTR(crtc->scrn); - AtomBiosArgRec data; - unsigned char *space; - uint16_t misc = 0; - SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION param; - memset(¶m, 0, sizeof(param)); - - param.usH_Total = cpu_to_le16(mode->CrtcHTotal); - param.usH_Disp = cpu_to_le16(mode->CrtcHDisplay); - param.usH_SyncStart = cpu_to_le16(mode->CrtcHSyncStart); - param.usH_SyncWidth = cpu_to_le16(mode->CrtcHSyncEnd - mode->CrtcHSyncStart); - param.usV_Total = cpu_to_le16(mode->CrtcVTotal); - param.usV_Disp = cpu_to_le16(mode->CrtcVDisplay); - param.usV_SyncStart = cpu_to_le16(mode->CrtcVSyncStart); - param.usV_SyncWidth = cpu_to_le16(mode->CrtcVSyncEnd - mode->CrtcVSyncStart); - - if (mode->Flags & V_NVSYNC) - misc |= ATOM_VSYNC_POLARITY; - - if (mode->Flags & V_NHSYNC) - misc |= ATOM_HSYNC_POLARITY; - - if (mode->Flags & V_CSYNC) - misc |= ATOM_COMPOSITESYNC; - - if (mode->Flags & V_INTERLACE) - misc |= ATOM_INTERLACE; - - if (mode->Flags & V_DBLSCAN) - misc |= ATOM_DOUBLE_CLOCK_MODE; - - param.susModeMiscInfo.usAccess = cpu_to_le16(misc); - param.ucCRTC = radeon_crtc->crtc_id; - - data.exec.index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing); - data.exec.dataSpace = (void *)&space; - data.exec.pspace = ¶m; - - if (RHDAtomBiosFunc(info->atomBIOS->pScrn, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { - ErrorF("Set CRTC Timing success\n"); - return ATOM_SUCCESS ; - } - - ErrorF("Set CRTC Timing failed\n"); - return ATOM_NOT_IMPLEMENTED; -} - -static AtomBiosResult -atombios_set_crtc_dtd_timing(xf86CrtcPtr crtc, DisplayModePtr mode) -{ - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - RADEONInfoPtr info = RADEONPTR(crtc->scrn); - AtomBiosArgRec data; - unsigned char *space; - uint16_t misc = 0; - SET_CRTC_USING_DTD_TIMING_PARAMETERS param; - memset(¶m, 0, sizeof(param)); - - param.usH_Size = cpu_to_le16(mode->CrtcHDisplay); - param.usH_Blanking_Time = cpu_to_le16(mode->CrtcHBlankEnd - mode->CrtcHDisplay); - param.usV_Size = cpu_to_le16(mode->CrtcVDisplay); - param.usV_Blanking_Time = cpu_to_le16(mode->CrtcVBlankEnd - mode->CrtcVDisplay); - param.usH_SyncOffset = cpu_to_le16(mode->CrtcHSyncStart - mode->CrtcHDisplay); - param.usH_SyncWidth = cpu_to_le16(mode->CrtcHSyncEnd - mode->CrtcHSyncStart); - param.usV_SyncOffset = cpu_to_le16(mode->CrtcVSyncStart - mode->CrtcVDisplay); - param.usV_SyncWidth = cpu_to_le16(mode->CrtcVSyncEnd - mode->CrtcVSyncStart); - - if (mode->Flags & V_NVSYNC) - misc |= ATOM_VSYNC_POLARITY; - - if (mode->Flags & V_NHSYNC) - misc |= ATOM_HSYNC_POLARITY; - - if (mode->Flags & V_CSYNC) - misc |= ATOM_COMPOSITESYNC; - - if (mode->Flags & V_INTERLACE) - misc |= ATOM_INTERLACE; - - if (mode->Flags & V_DBLSCAN) - misc |= ATOM_DOUBLE_CLOCK_MODE; - - param.susModeMiscInfo.usAccess = cpu_to_le16(misc); - param.ucCRTC= radeon_crtc->crtc_id; - - data.exec.index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming); - data.exec.dataSpace = (void *)&space; - data.exec.pspace = ¶m; - - if (RHDAtomBiosFunc(info->atomBIOS->pScrn, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { - ErrorF("Set DTD CRTC Timing success\n"); - return ATOM_SUCCESS ; - } - - ErrorF("Set DTD CRTC Timing failed\n"); - return ATOM_NOT_IMPLEMENTED; -} - -static void -atombios_pick_pll(xf86CrtcPtr crtc) -{ - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - RADEONInfoPtr info = RADEONPTR(crtc->scrn); - xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(crtc->scrn); - xf86OutputPtr output; - RADEONOutputPrivatePtr radeon_output; - int o, c; - uint32_t pll_use_mask = 0; - Bool is_dp = FALSE; - - if (IS_DCE4_VARIANT) { - for (o = 0; o < xf86_config->num_output; o++) { - output = xf86_config->output[o]; - if (output->crtc == crtc) { - int mode = atombios_get_encoder_mode(output); - radeon_output = output->driver_private; - - if (mode == ATOM_ENCODER_MODE_DP) { - is_dp = TRUE; - break; - } else { - for (c = 0; c < xf86_config->num_crtc; c++) { - xf86CrtcPtr test_crtc = xf86_config->crtc[c]; - RADEONCrtcPrivatePtr radeon_test_crtc = test_crtc->driver_private; - - if (crtc != test_crtc && (radeon_test_crtc->pll_id >= 0)) - pll_use_mask |= (1 << radeon_test_crtc->pll_id); - - } - } - } - } - /* DP clock comes from DCPLL, DP PHY CLK comes from ext source - * setting ATOM_PPLL_INVALID skips the PPLL programming for DP - */ - if (is_dp) - radeon_crtc->pll_id = ATOM_PPLL_INVALID; - else if (!(pll_use_mask & 1)) - radeon_crtc->pll_id = ATOM_PPLL1; - else - radeon_crtc->pll_id = ATOM_PPLL2; - } else - radeon_crtc->pll_id = radeon_crtc->crtc_id; - - ErrorF("Picked PLL %d\n", radeon_crtc->pll_id); - - for (o = 0; o < xf86_config->num_output; o++) { - output = xf86_config->output[o]; - if (output->crtc == crtc) { - radeon_output = output->driver_private; - radeon_output->pll_id = radeon_crtc->pll_id; - } - } -} - -union adjust_pixel_clock { - ADJUST_DISPLAY_PLL_PS_ALLOCATION v1; - ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3; -}; - -static uint32_t atombios_adjust_pll(xf86CrtcPtr crtc, DisplayModePtr mode, int *pll_flags_p) -{ - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - ScrnInfoPtr pScrn = crtc->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(crtc->scrn); - uint32_t adjusted_clock = mode->Clock; - RADEONOutputPrivatePtr radeon_output = NULL; - radeon_encoder_ptr radeon_encoder = NULL; - xf86OutputPtr output; - int pll_flags = 0; - int i; - - if (IS_AVIVO_VARIANT) { - if (xf86ReturnOptValBool(info->Options, OPTION_NEW_PLL, TRUE)) - radeon_crtc->pll_algo = RADEON_PLL_NEW; - else - radeon_crtc->pll_algo = RADEON_PLL_OLD; - } else { - if (xf86ReturnOptValBool(info->Options, OPTION_NEW_PLL, FALSE)) - radeon_crtc->pll_algo = RADEON_PLL_NEW; - else - radeon_crtc->pll_algo = RADEON_PLL_OLD; - } - - if (IS_AVIVO_VARIANT) { - if ((info->ChipFamily == CHIP_FAMILY_RS600) || - (info->ChipFamily == CHIP_FAMILY_RS690) || - (info->ChipFamily == CHIP_FAMILY_RS740)) - pll_flags |= /*RADEON_PLL_USE_FRAC_FB_DIV |*/ - RADEON_PLL_PREFER_CLOSEST_LOWER; - if (IS_DCE32_VARIANT && mode->Clock > 200000) /* range limits??? */ - pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; - else - pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; - } else { - pll_flags |= RADEON_PLL_LEGACY; - - if (mode->Clock > 200000) /* range limits??? */ - pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; - else - pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; - } - - for (i = 0; i < xf86_config->num_output; i++) { - output = xf86_config->output[i]; - if (output->crtc == crtc) { - radeon_output = output->driver_private; - radeon_encoder = radeon_get_encoder(output); - if (IS_AVIVO_VARIANT) { - /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ - if (radeon_encoder && - (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) && - !IS_DCE3_VARIANT) - adjusted_clock *= 2; - if (radeon_output->active_device & - (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) { - pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER; - radeon_crtc->pll_algo = RADEON_PLL_OLD; - } - } else { - if (radeon_output->active_device & (ATOM_DEVICE_LCD_SUPPORT | - ATOM_DEVICE_DFP_SUPPORT)) - pll_flags |= RADEON_PLL_NO_ODD_POST_DIV; - if (radeon_output->active_device & (ATOM_DEVICE_LCD_SUPPORT)) - pll_flags |= (RADEON_PLL_USE_BIOS_DIVS | RADEON_PLL_USE_REF_DIV); - } - if (IS_DCE3_VARIANT) - break; - } - } - - if (IS_DCE3_VARIANT) { - union adjust_pixel_clock args; - int major, minor, index; - AtomBiosArgRec data; - unsigned char *space; - - memset(&args, 0, sizeof(args)); - - index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll); - - atombios_get_command_table_version(info->atomBIOS, index, &major, &minor); - - data.exec.index = index; - data.exec.dataSpace = (void *)&space; - data.exec.pspace = &args; - - switch(major) { - case 1: - switch(minor) { - case 1: - case 2: - args.v1.usPixelClock = cpu_to_le16(adjusted_clock / 10); - args.v1.ucTransmitterID = radeon_encoder->encoder_id; - args.v1.ucEncodeMode = atombios_get_encoder_mode(output); - - ErrorF("before %d\n", args.v1.usPixelClock); - if (RHDAtomBiosFunc(info->atomBIOS->pScrn, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { - adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10; - } - ErrorF("after %d\n", args.v1.usPixelClock); - break; - case 3: - args.v3.sInput.usPixelClock = cpu_to_le16(adjusted_clock / 10); - args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id; - args.v3.sInput.ucEncodeMode = atombios_get_encoder_mode(output); - args.v3.sInput.ucDispPllConfig = 0; - if (radeon_output->coherent_mode || (args.v3.sInput.ucEncodeMode == ATOM_ENCODER_MODE_DP)) - args.v3.sInput.ucDispPllConfig |= DISPPLL_CONFIG_COHERENT_MODE; - if (adjusted_clock > 165000) - args.v3.sInput.ucDispPllConfig |= DISPPLL_CONFIG_DUAL_LINK; - // if SS - // args.v3.sInput.ucDispPllConfig |= DISPPLL_CONFIG_SS_ENABLE; - - ErrorF("before %d 0x%x\n", args.v3.sInput.usPixelClock, args.v3.sInput.ucDispPllConfig); - if (RHDAtomBiosFunc(info->atomBIOS->pScrn, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { - adjusted_clock = args.v3.sOutput.ulDispPllFreq * 10; - if (args.v3.sOutput.ucRefDiv) { - pll_flags |= RADEON_PLL_USE_REF_DIV; - info->pll.reference_div = args.v3.sOutput.ucRefDiv; - } - if (args.v3.sOutput.ucPostDiv) { - pll_flags |= RADEON_PLL_USE_POST_DIV; - info->pll.post_div = args.v3.sOutput.ucPostDiv; - } - ErrorF("after %d %d %d\n", args.v3.sOutput.ulDispPllFreq, - args.v3.sOutput.ucRefDiv, args.v3.sOutput.ucPostDiv); - } - break; - default: - ErrorF("%s: Unknown table version %d %d\n", __func__, major, minor); - goto out; - } - break; - default: - ErrorF("%s: Unknown table version %d %d\n", __func__, major, minor); - goto out; - } - } -out: - *pll_flags_p = pll_flags; - return adjusted_clock; -} - -union set_pixel_clock { - SET_PIXEL_CLOCK_PS_ALLOCATION base; - PIXEL_CLOCK_PARAMETERS v1; - PIXEL_CLOCK_PARAMETERS_V2 v2; - PIXEL_CLOCK_PARAMETERS_V3 v3; - PIXEL_CLOCK_PARAMETERS_V5 v5; -}; - -static void -atombios_crtc_set_dcpll(xf86CrtcPtr crtc) -{ - RADEONInfoPtr info = RADEONPTR(crtc->scrn); - xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(crtc->scrn); - xf86OutputPtr output = NULL; - RADEONOutputPrivatePtr radeon_output = NULL; - radeon_encoder_ptr radeon_encoder = NULL; - int index; - int major, minor, i; - union set_pixel_clock args; - AtomBiosArgRec data; - unsigned char *space; - - memset(&args, 0, sizeof(args)); - - for (i = 0; i < xf86_config->num_output; i++) { - output = xf86_config->output[i]; - if (output->crtc == crtc) { - radeon_output = output->driver_private; - radeon_encoder = radeon_get_encoder(output); - break; - } - } - - if (radeon_output == NULL) { - xf86DrvMsg(crtc->scrn->scrnIndex, X_ERROR, "No output assigned to crtc!\n"); - return; - } - - if (radeon_encoder == NULL) { - xf86DrvMsg(crtc->scrn->scrnIndex, X_ERROR, "No encoder assigned to output!\n"); - return; - } - - index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); - atombios_get_command_table_version(info->atomBIOS, index, &major, &minor); - - /*ErrorF("table is %d %d\n", major, minor);*/ - switch(major) { - case 1: - switch(minor) { - case 5: - args.v5.ucCRTC = ATOM_CRTC_INVALID; - /* XXX: get this from the firmwareinfo table */ - args.v5.usPixelClock = info->default_dispclk; - args.v5.ucPpll = ATOM_DCPLL; - break; - default: - ErrorF("Unknown table version\n"); - exit(-1); - } - break; - default: - ErrorF("Unknown table version\n"); - exit(-1); - } - - data.exec.index = index; - data.exec.dataSpace = (void *)&space; - data.exec.pspace = &args; - - if (RHDAtomBiosFunc(info->atomBIOS->pScrn, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { - ErrorF("Set DCPLL success\n"); - return; - } - - ErrorF("Set DCPLL failed\n"); - return; -} - -static void -atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode) -{ - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - ScrnInfoPtr pScrn = crtc->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - int index; - uint32_t sclock; - uint32_t ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; - int major, minor; - union set_pixel_clock args; - xf86OutputPtr output = NULL; - xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(crtc->scrn); - radeon_encoder_ptr radeon_encoder = NULL; - int pll_flags = 0; - uint32_t temp; - AtomBiosArgRec data; - unsigned char *space; - int i; - - memset(&args, 0, sizeof(args)); - - if (IS_DCE4_VARIANT) { - /* XXX 6 crtcs, but only 2 plls */ - switch (radeon_crtc->pll_id) { - case ATOM_PPLL1: - temp = INREG(EVERGREEN_P1PLL_SS_CNTL); - OUTREG(EVERGREEN_P1PLL_SS_CNTL, temp & ~EVERGREEN_PxPLL_SS_EN); - break; - case ATOM_PPLL2: - temp = INREG(EVERGREEN_P2PLL_SS_CNTL); - OUTREG(EVERGREEN_P2PLL_SS_CNTL, temp & ~EVERGREEN_PxPLL_SS_EN); - break; - } - } else { - if (radeon_crtc->crtc_id == 0) { - temp = INREG(AVIVO_P1PLL_INT_SS_CNTL); - OUTREG(AVIVO_P1PLL_INT_SS_CNTL, temp & ~1); - } else { - temp = INREG(AVIVO_P2PLL_INT_SS_CNTL); - OUTREG(AVIVO_P2PLL_INT_SS_CNTL, temp & ~1); - } - } - - if (IS_DCE3_VARIANT) { - for (i = 0; i < xf86_config->num_output; i++) { - output = xf86_config->output[i]; - if (output->crtc == crtc) { - radeon_encoder = radeon_get_encoder(output); - break; - } - } - - if (output->driver_private == NULL) { - xf86DrvMsg(crtc->scrn->scrnIndex, X_ERROR, "No output assigned to crtc!\n"); - return; - } - if (radeon_encoder == NULL) { - xf86DrvMsg(crtc->scrn->scrnIndex, X_ERROR, "No encoder assigned to output!\n"); - return; - } - } - - sclock = atombios_adjust_pll(crtc, mode, &pll_flags); - - RADEONComputePLL(crtc, &info->pll, sclock, &temp, - &fb_div, &frac_fb_div, &ref_div, &post_div, pll_flags); - sclock = temp; /* 10 khz */ - - xf86DrvMsg(crtc->scrn->scrnIndex, X_INFO, - "crtc(%d) Clock: mode %d, PLL %lu\n", - radeon_crtc->crtc_id, mode->Clock, (long unsigned int)sclock * 10); - xf86DrvMsg(crtc->scrn->scrnIndex, X_INFO, - "crtc(%d) PLL : refdiv %u, fbdiv 0x%X(%u), fracfbdiv %u, pdiv %u\n", - radeon_crtc->crtc_id, (unsigned int)ref_div, (unsigned int)fb_div, - (unsigned int)fb_div, (unsigned int)frac_fb_div, (unsigned int)post_div); - - index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); - atombios_get_command_table_version(info->atomBIOS, index, &major, &minor); - - /*ErrorF("table is %d %d\n", major, minor);*/ - switch(major) { - case 1: - switch(minor) { - case 1: - case 2: - args.v2.usPixelClock = cpu_to_le16(mode->Clock / 10); - args.v2.usRefDiv = cpu_to_le16(ref_div); - args.v2.usFbDiv = cpu_to_le16(fb_div); - args.v2.ucFracFbDiv = frac_fb_div; - args.v2.ucPostDiv = post_div; - args.v2.ucPpll = radeon_crtc->pll_id; - args.v2.ucCRTC = radeon_crtc->crtc_id; - args.v2.ucRefDivSrc = 1; - break; - case 3: - args.v3.usPixelClock = cpu_to_le16(mode->Clock / 10); - args.v3.usRefDiv = cpu_to_le16(ref_div); - args.v3.usFbDiv = cpu_to_le16(fb_div); - args.v3.ucFracFbDiv = frac_fb_div; - args.v3.ucPostDiv = post_div; - args.v3.ucPpll = radeon_crtc->pll_id; - args.v3.ucMiscInfo = (radeon_crtc->crtc_id << 2); - args.v3.ucTransmitterId = radeon_encoder->encoder_id; - args.v3.ucEncoderMode = atombios_get_encoder_mode(output); - break; - case 5: - args.v5.ucCRTC = radeon_crtc->crtc_id; - args.v5.usPixelClock = cpu_to_le16(mode->Clock / 10); - args.v5.ucRefDiv = ref_div; - args.v5.usFbDiv = cpu_to_le16(fb_div); - args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); - args.v5.ucPostDiv = post_div; - args.v5.ucPpll = radeon_crtc->pll_id; - args.v5.ucMiscInfo = 0; //HDMI depth - args.v5.ucTransmitterID = radeon_encoder->encoder_id; - args.v5.ucEncoderMode = atombios_get_encoder_mode(output); - break; - default: - ErrorF("Unknown table version\n"); - exit(-1); - } - break; - default: - ErrorF("Unknown table version\n"); - exit(-1); - } - - data.exec.index = index; - data.exec.dataSpace = (void *)&space; - data.exec.pspace = &args; - - if (RHDAtomBiosFunc(info->atomBIOS->pScrn, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { - ErrorF("Set CRTC %d PLL success\n", radeon_crtc->crtc_id); - return; - } - - ErrorF("Set CRTC %d PLL failed\n", radeon_crtc->crtc_id); - return; -} - -static void evergreen_set_base_format(xf86CrtcPtr crtc, - DisplayModePtr mode, - DisplayModePtr adjusted_mode, - int x, int y) -{ - ScrnInfoPtr pScrn = crtc->scrn; - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - uint64_t fb_location = crtc->scrn->fbOffset + info->fbLocation; - uint32_t fb_format; - uint32_t fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE); - - switch (crtc->scrn->bitsPerPixel) { - case 15: - fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | - EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555)); - break; - case 16: - fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | - EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565)); -#if X_BYTE_ORDER == X_BIG_ENDIAN - fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); -#endif - break; - case 24: - case 32: - fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | - EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888)); -#if X_BYTE_ORDER == X_BIG_ENDIAN - fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); -#endif - break; - default: - FatalError("Unsupported screen depth: %d\n", xf86GetDepth()); - } - - switch (radeon_crtc->crtc_id) { - case 0: - default: - OUTREG(AVIVO_D1VGA_CONTROL, 0); - break; - case 1: - OUTREG(AVIVO_D2VGA_CONTROL, 0); - break; - case 2: - OUTREG(EVERGREEN_D3VGA_CONTROL, 0); - break; - case 3: - OUTREG(EVERGREEN_D4VGA_CONTROL, 0); - break; - case 4: - OUTREG(EVERGREEN_D5VGA_CONTROL, 0); - break; - case 5: - OUTREG(EVERGREEN_D6VGA_CONTROL, 0); - break; - } - - /* setup fb format and location - */ - if (crtc->rotatedData != NULL) { - /* x/y offset is already included */ - x = 0; - y = 0; - fb_location = fb_location + (char *)crtc->rotatedData - (char *)info->FB; - } - - - OUTREG(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, - (fb_location >> 32) & 0xf); - OUTREG(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, - (fb_location >> 32) & 0xf); - OUTREG(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, - fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); - OUTREG(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, - fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); - OUTREG(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); - OUTREG(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); - - OUTREG(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); - OUTREG(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); - OUTREG(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0); - OUTREG(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0); - OUTREG(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, info->virtualX); - OUTREG(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, info->virtualY); - OUTREG(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, - crtc->scrn->displayWidth); - OUTREG(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1); - - OUTREG(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, mode->VDisplay); - x &= ~3; - y &= ~1; - OUTREG(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset, (x << 16) | y); - OUTREG(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset, (mode->HDisplay << 16) | mode->VDisplay); - - if (adjusted_mode->Flags & V_INTERLACE) - OUTREG(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, EVERGREEN_INTERLEAVE_EN); - else - OUTREG(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0); - -} - -static void avivo_set_base_format(xf86CrtcPtr crtc, - DisplayModePtr mode, - DisplayModePtr adjusted_mode, - int x, int y) -{ - ScrnInfoPtr pScrn = crtc->scrn; - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - uint64_t fb_location = crtc->scrn->fbOffset + info->fbLocation; - uint32_t fb_format; -#if X_BYTE_ORDER == X_BIG_ENDIAN - uint32_t fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE; -#endif - - switch (crtc->scrn->bitsPerPixel) { - case 15: - fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555; - break; - case 16: - fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | AVIVO_D1GRPH_CONTROL_16BPP_RGB565; -#if X_BYTE_ORDER == X_BIG_ENDIAN - fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT; -#endif - break; - case 24: - case 32: - fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888; -#if X_BYTE_ORDER == X_BIG_ENDIAN - fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT; -#endif - break; - default: - FatalError("Unsupported screen depth: %d\n", xf86GetDepth()); - } - - if (info->tilingEnabled && (crtc->rotatedData == NULL)) { - fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE; - } - - if (radeon_crtc->crtc_id == 0) - OUTREG(AVIVO_D1VGA_CONTROL, 0); - else - OUTREG(AVIVO_D2VGA_CONTROL, 0); - - /* setup fb format and location - */ - if (crtc->rotatedData != NULL) { - /* x/y offset is already included */ - x = 0; - y = 0; - fb_location = fb_location + (char *)crtc->rotatedData - (char *)info->FB; - } - - if (info->ChipFamily >= CHIP_FAMILY_RV770) { - if (radeon_crtc->crtc_id) { - OUTREG(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, (fb_location >> 32) & 0xf); - OUTREG(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, (fb_location >> 32) & 0xf); - } else { - OUTREG(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, (fb_location >> 32) & 0xf); - OUTREG(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, (fb_location >> 32) & 0xf); - } - } - OUTREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, - fb_location & 0xffffffff); - OUTREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, - fb_location & 0xffffffff); - OUTREG(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); - -#if X_BYTE_ORDER == X_BIG_ENDIAN - if (info->ChipFamily >= CHIP_FAMILY_R600) - OUTREG(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); -#endif - - OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); - OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); - OUTREG(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); - OUTREG(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0); - OUTREG(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, info->virtualX); - OUTREG(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, info->virtualY); - OUTREG(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, - crtc->scrn->displayWidth); - OUTREG(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); - - OUTREG(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, mode->VDisplay); - x &= ~3; - y &= ~1; - OUTREG(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, (x << 16) | y); - OUTREG(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, - (mode->HDisplay << 16) | mode->VDisplay); - - if (mode->Flags & V_INTERLACE) - OUTREG(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, - AVIVO_D1MODE_INTERLEAVE_EN); - else - OUTREG(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0); -} - -static void legacy_set_base_format(xf86CrtcPtr crtc, - DisplayModePtr mode, - DisplayModePtr adjusted_mode, - int x, int y) -{ - ScrnInfoPtr pScrn = crtc->scrn; - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - int format = 0; - uint32_t crtc_gen_cntl, crtc2_gen_cntl, crtc_pitch; - - RADEONInitCommonRegisters(info->ModeReg, info); - RADEONInitSurfaceCntl(crtc, info->ModeReg); - RADEONRestoreCommonRegisters(pScrn, info->ModeReg); - - switch (info->CurrentLayout.pixel_code) { - case 4: format = 1; break; - case 8: format = 2; break; - case 15: format = 3; break; /* 555 */ - case 16: format = 4; break; /* 565 */ - case 24: format = 5; break; /* RGB */ - case 32: format = 6; break; /* xRGB */ - default: - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Unsupported pixel depth (%d)\n", - info->CurrentLayout.bitsPerPixel); - } - - crtc_pitch = (((pScrn->displayWidth * pScrn->bitsPerPixel) + - ((pScrn->bitsPerPixel * 8) -1)) / - (pScrn->bitsPerPixel * 8)); - crtc_pitch |= crtc_pitch << 16; - - switch (radeon_crtc->crtc_id) { - case 0: - crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL) & 0xfffff0ff; - crtc_gen_cntl |= (format << 8); - OUTREG(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); - OUTREG(RADEON_CRTC_PITCH, crtc_pitch); - RADEONInitCrtcBase(crtc, info->ModeReg, x, y); - RADEONRestoreCrtcBase(pScrn, info->ModeReg); - break; - case 1: - crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL) & 0xfffff0ff; - crtc2_gen_cntl |= (format << 8); - OUTREG(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); - OUTREG(RADEON_CRTC2_PITCH, crtc_pitch); - RADEONInitCrtc2Base(crtc, info->ModeReg, x, y); - RADEONRestoreCrtc2Base(pScrn, info->ModeReg); - OUTREG(RADEON_FP_H2_SYNC_STRT_WID, INREG(RADEON_CRTC2_H_SYNC_STRT_WID)); - OUTREG(RADEON_FP_V2_SYNC_STRT_WID, INREG(RADEON_CRTC2_V_SYNC_STRT_WID)); - break; - } -} - -void -atombios_crtc_mode_set(xf86CrtcPtr crtc, - DisplayModePtr mode, - DisplayModePtr adjusted_mode, - int x, int y) -{ - ScrnInfoPtr pScrn = crtc->scrn; - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - RADEONInfoPtr info = RADEONPTR(pScrn); - Bool tilingChanged = FALSE; - - if (info->allowColorTiling) { - radeon_crtc->can_tile = (mode->Flags & (V_DBLSCAN | V_INTERLACE)) ? FALSE : TRUE; - tilingChanged = RADEONSetTiling(pScrn); - } - - ErrorF("Mode %dx%d - %d %d %d\n", adjusted_mode->CrtcHDisplay, adjusted_mode->CrtcVDisplay, - adjusted_mode->CrtcHTotal, adjusted_mode->CrtcVTotal, adjusted_mode->Flags); - - RADEONInitMemMapRegisters(pScrn, info->ModeReg, info); - RADEONRestoreMemMapRegisters(pScrn, info->ModeReg); - - if (IS_DCE4_VARIANT) - atombios_crtc_set_dcpll(crtc); - atombios_pick_pll(crtc); - atombios_crtc_set_pll(crtc, adjusted_mode); - if (IS_DCE4_VARIANT) - atombios_set_crtc_dtd_timing(crtc, adjusted_mode); - else { - atombios_set_crtc_timing(crtc, adjusted_mode); - if (!IS_AVIVO_VARIANT && (radeon_crtc->crtc_id == 0)) - atombios_set_crtc_dtd_timing(crtc, adjusted_mode); - } - - if (IS_DCE4_VARIANT) - evergreen_set_base_format(crtc, mode, adjusted_mode, x, y); - else if (IS_AVIVO_VARIANT) - avivo_set_base_format(crtc, mode, adjusted_mode, x, y); - else - legacy_set_base_format(crtc, mode, adjusted_mode, x, y); - - if (info->DispPriority) - RADEONInitDispBandwidth(pScrn); - - radeon_crtc->initialized = TRUE; - - if (tilingChanged) { - /* need to redraw front buffer, I guess this can be considered a hack ? */ - /* if this is called during ScreenInit() we don't have pScrn->pScreen yet */ - if (pScrn->pScreen) - xf86EnableDisableFBAccess(XF86_ENABLEDISABLEFB_ARG(pScrn), FALSE); - RADEONChangeSurfaces(pScrn); - if (pScrn->pScreen) - xf86EnableDisableFBAccess(XF86_ENABLEDISABLEFB_ARG(pScrn), TRUE); - /* xf86SetRootClip would do, but can't access that here */ - } - -} - -/* Calculate display buffer watermark to prevent buffer underflow */ -void -RADEONInitDispBandwidthAVIVO(ScrnInfoPtr pScrn, - DisplayModePtr mode1, int pixel_bytes1, - DisplayModePtr mode2, int pixel_bytes2) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - uint32_t dc_lb_memory_split; - float available_bandwidth = 0; - float read_delay_latency = 1000; - int i; - Bool sideport = FALSE; - - /* - * Set display0/1 priority up in the memory controller for - * modes if the user specifies HIGH for displaypriority - * option. - */ - if (info->DispPriority == 2) { - uint32_t mc_init_misc_lat_timer = 0; - if (info->ChipFamily == CHIP_FAMILY_RV515) - mc_init_misc_lat_timer = INMC(pScrn, RV515_MC_INIT_MISC_LAT_TIMER); - else if ((info->ChipFamily == CHIP_FAMILY_RS690) || - (info->ChipFamily == CHIP_FAMILY_RS740)) - mc_init_misc_lat_timer = INMC(pScrn, RS690_MC_INIT_MISC_LAT_TIMER); - - mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT); - mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT); - - if (pRADEONEnt->pCrtc[1]->enabled) - mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT); /* display 1 */ - if (pRADEONEnt->pCrtc[0]->enabled) - mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT); /* display 0 */ - - if (info->ChipFamily == CHIP_FAMILY_RV515) - OUTMC(pScrn, RV515_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer); - else if ((info->ChipFamily == CHIP_FAMILY_RS690) || - (info->ChipFamily == CHIP_FAMILY_RS740)) - OUTMC(pScrn, RS690_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer); - } - - /* - * Line Buffer Setup - * There is a single line buffer shared by both display controllers. - * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between the display - * controllers. The paritioning can either be done manually or via one of four - * preset allocations specified in bits 1:0: - * 0 - line buffer is divided in half and shared between each display controller - * 1 - D1 gets 3/4 of the line buffer, D2 gets 1/4 - * 2 - D1 gets the whole buffer - * 3 - D1 gets 1/4 of the line buffer, D2 gets 3/4 - * Setting bit 2 of DC_LB_MEMORY_SPLIT controls switches to manual allocation mode. - * In manual allocation mode, D1 always starts at 0, D1 end/2 is specified in bits - * 14:4; D2 allocation follows D1. - */ - - dc_lb_memory_split = INREG(AVIVO_DC_LB_MEMORY_SPLIT) & ~AVIVO_DC_LB_MEMORY_SPLIT_MASK; - dc_lb_memory_split &= ~AVIVO_DC_LB_MEMORY_SPLIT_SHIFT_MODE; - /* auto */ - if (mode1 && mode2) { - if (mode1->HDisplay > mode2->HDisplay) { - if (mode1->HDisplay > 2560) - dc_lb_memory_split |= AVIVO_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q; - else - dc_lb_memory_split |= AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; - } else if (mode2->HDisplay > mode1->HDisplay) { - if (mode2->HDisplay > 2560) - dc_lb_memory_split |= AVIVO_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q; - else - dc_lb_memory_split |= AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; - } else - dc_lb_memory_split |= AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; - } else if (mode1) { - dc_lb_memory_split |= AVIVO_DC_LB_MEMORY_SPLIT_D1_ONLY; - } else if (mode2) { - dc_lb_memory_split |= AVIVO_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q; - } - OUTREG(AVIVO_DC_LB_MEMORY_SPLIT, dc_lb_memory_split); -#if 0 - /* manual */ - dc_lb_memory_split |= AVIVO_DC_LB_MEMORY_SPLIT_SHIFT_MODE; - dc_lb_memory_split &= ~(AVIVO_DC_LB_DISP1_END_ADR_MASK << AVIVO_DC_LB_DISP1_END_ADR_SHIFT); - if (mode1) { - dc_lb_memory_split |= ((((mode1->HDisplay / 2) + 64 /*???*/) & AVIVO_DC_LB_DISP1_END_ADR_MASK) - << AVIVO_DC_LB_DISP1_END_ADR_SHIFT); - } else if (mode2) { - dc_lb_memory_split |= (0 << AVIVO_DC_LB_DISP1_END_ADR_SHIFT); - } - OUTREG(AVIVO_DC_LB_MEMORY_SPLIT, dc_lb_memory_split); -#endif - - /* fixme - * Still need to implement the actual watermark calculation - * for rs600. This just allows us to force high display - * priority. - */ - if (info->ChipFamily == CHIP_FAMILY_RS600) { - if (info->DispPriority == 2) { - uint32_t priority_cnt; - - if (mode1) { - priority_cnt = INREG(AVIVO_D1MODE_PRIORITY_A_CNT); - priority_cnt |= AVIVO_DxMODE_PRIORITY_ALWAYS_ON; - OUTREG(AVIVO_D1MODE_PRIORITY_A_CNT, priority_cnt); - - priority_cnt = INREG(AVIVO_D1MODE_PRIORITY_B_CNT); - priority_cnt |= AVIVO_DxMODE_PRIORITY_ALWAYS_ON; - OUTREG(AVIVO_D1MODE_PRIORITY_B_CNT, priority_cnt); - } - - if (mode2) { - priority_cnt = INREG(AVIVO_D2MODE_PRIORITY_A_CNT); - priority_cnt |= AVIVO_DxMODE_PRIORITY_ALWAYS_ON; - OUTREG(AVIVO_D2MODE_PRIORITY_A_CNT, priority_cnt); - - priority_cnt = INREG(AVIVO_D2MODE_PRIORITY_B_CNT); - priority_cnt |= AVIVO_DxMODE_PRIORITY_ALWAYS_ON; - OUTREG(AVIVO_D2MODE_PRIORITY_B_CNT, priority_cnt); - } - } - return; - } - - /* IGP bandwidth - get from integrated systems table - * SYSTEM_MEMORY_BANDWIDTH (Mbyte/s) = SYSTEM_MEMORY_CLOCK (MHz) * (1+DDR) * 8 * EFF * Num of channels - * SIDEPORT_MEMORY_BANDWIDTH = SIDEPORT_MEMORY_CLOCK * 2(byte) * 2(DDR) * 0.7(Eff) - * CORE_CLOCK_BANDWIDTH (Mbyte/s) = SCLK (MHz) * 16 / Dynamic Engine clock Divider - * HT_LINK_BANDWIDTH = HT_LINK_CLOCK * 2 * HT_LINK_WIDTH/8 * HT_LINK_EFF - * system read delay - * READ_DLY_MAX_LATENCY: 5000 ns - * sideport read delay - * READ_DLY_MAX_LATENCY: 370 * MCLK + 800 ns - * MCLK is the sideport memory clock period in ns (MCLK = 1000 / MCLKfreq MHz) - */ - - if (info->IsIGP) { - float core_clock_bandwidth = ((float)info->pm.mode[info->pm.current_mode].sclk / 100) * 16 / 1; - - if (sideport) { - float sideport_memory_bandwidth = (info->igp_sideport_mclk / 2) * 2 * 2 * 0.7; - float mclk = 1000 / info->igp_sideport_mclk; - read_delay_latency = 370 * mclk * 800; - available_bandwidth = MIN(sideport_memory_bandwidth, core_clock_bandwidth); - } else { - float system_memory_bandwidth = (info->igp_system_mclk / 2) * (1 + 1) * 8 * 0.5 * 1; - float ht_link_bandwidth = info->igp_ht_link_clk * 2 * (info->igp_ht_link_width / 8) * 0.8; - read_delay_latency = 5000; - available_bandwidth = MIN(system_memory_bandwidth, MIN(ht_link_bandwidth, core_clock_bandwidth)); - } - } - - /* calculate for each display */ - for (i = 0; i < 2; i++) { - DisplayModePtr current = NULL; - //RADEONCrtcPrivatePtr radeon_crtc = pRADEONEnt->Controller[i]; - float pclk, sclk, sclkfreq = 0; - float consumption_time, consumption_rate; - int num_line_pair, request_fifo_depth, lb_request_fifo_depth; - int max_req; - uint32_t lb_max_req_outstanding, priority_cnt; - float line_time, active_time, chunk_time; - float worst_case_latency, tolerable_latency; - float fill_rate; - int priority_mark_max, priority_mark, priority_mark2; - int width, estimated_width; - /* FIXME: handle the scalers better */ - Bool d1_scale_en = pRADEONEnt->Controller[0]->scaler_enabled; - Bool d2_scale_en = pRADEONEnt->Controller[1]->scaler_enabled; - float vtaps1 = 2; /* XXX */ - float vsc1 = pRADEONEnt->Controller[0]->vsc; - float hsc1 = pRADEONEnt->Controller[0]->hsc; - float vtaps2 = 2; /* XXX */ - float vsc2 = pRADEONEnt->Controller[1]->vsc; - float hsc2 = pRADEONEnt->Controller[1]->hsc; - - if (i == 0) - current = mode1; - else - current = mode2; - - if (current == NULL) - continue; - - /* Determine consumption rate - pclk = pixel clock period(ns) - vtaps = number of vertical taps, - vsc = vertical scaling ratio, defined as source/destination - hsc = horizontal scaling ration, defined as source/destination - */ - - pclk = 1000 / ((float)current->Clock / 1000); - - if (i == 0) { - if (d1_scale_en) - consumption_time = pclk / ((MAX(vtaps1, vsc1) * hsc1) / vtaps1); - else - consumption_time = pclk; - } else { - if (d2_scale_en) - consumption_time = pclk / ((MAX(vtaps2, vsc2) * hsc2) / vtaps2); - else - consumption_time = pclk; - } - - consumption_rate = 1 / consumption_time; - - /* Determine request line buffer fifo depth - NumLinePair = Number of line pairs to request(1 = 2 lines, 2 = 4 lines) - LBRequestFifoDepth = Number of chunk requests the LB can put into the request FIFO for a display - width = viewport width in pixels - */ - if (i == 0) { - if (vsc1 > 2) - num_line_pair = 2; - else - num_line_pair = 1; - } else { - if (vsc2 > 2) - num_line_pair = 2; - else - num_line_pair = 1; - } - - width = current->CrtcHDisplay; - request_fifo_depth = ceil(width/256) * num_line_pair; - if (request_fifo_depth < 4) - lb_request_fifo_depth = 4; - else - lb_request_fifo_depth = request_fifo_depth; - - if (info->IsIGP) { - if ((info->ChipFamily == CHIP_FAMILY_RS690) || - (info->ChipFamily == CHIP_FAMILY_RS740)) - OUTREG(RS690_DCP_CONTROL, 0); - else if ((info->ChipFamily == CHIP_FAMILY_RS780) || - (info->ChipFamily == CHIP_FAMILY_RS880)) - OUTREG(RS690_DCP_CONTROL, 2); - max_req = lb_request_fifo_depth - 1; - } else - max_req = lb_request_fifo_depth; - - /*ErrorF("max_req %d: 0x%x\n", i, max_req);*/ - - lb_max_req_outstanding = INREG(AVIVO_LB_MAX_REQ_OUTSTANDING); - if (i == 0) { - lb_max_req_outstanding &= ~(AVIVO_LB_D1_MAX_REQ_OUTSTANDING_MASK << AVIVO_LB_D1_MAX_REQ_OUTSTANDING_SHIFT); - lb_max_req_outstanding |= (max_req & AVIVO_LB_D1_MAX_REQ_OUTSTANDING_MASK) << AVIVO_LB_D1_MAX_REQ_OUTSTANDING_SHIFT; - } else { - lb_max_req_outstanding &= ~(AVIVO_LB_D2_MAX_REQ_OUTSTANDING_MASK << AVIVO_LB_D2_MAX_REQ_OUTSTANDING_SHIFT); - lb_max_req_outstanding |= (max_req & AVIVO_LB_D2_MAX_REQ_OUTSTANDING_MASK) << AVIVO_LB_D2_MAX_REQ_OUTSTANDING_SHIFT; - } - OUTREG(AVIVO_LB_MAX_REQ_OUTSTANDING, lb_max_req_outstanding); - - /* Determine line time - LineTime = total time for one line of displayhtotal = total number of horizontal pixels - pclk = pixel clock period(ns) - */ - line_time = current->CrtcHTotal * pclk; - - /* Determine active time - ActiveTime = time of active region of display within one line, - hactive = total number of horizontal active pixels - htotal = total number of horizontal pixels - */ - active_time = line_time * current->CrtcHDisplay / current->CrtcHTotal; - - /* Determine chunk time - ChunkTime = the time it takes the DCP to send one chunk of data - to the LB which consists of pipeline delay and inter chunk gap - sclk = system clock(ns) - */ - if (info->IsIGP) { - sclk = 1000 / (available_bandwidth / 16); - /* Sclkfreq = sclk in MHz = 1000/sclk (because sclk is in ns). */ - sclkfreq = 1000 / sclk; - chunk_time = sclk * 256 * 1.3; - } else { - sclk = 1000 / ((float)info->pm.mode[info->pm.current_mode].sclk / 100); - chunk_time = sclk * 600; - } - - /* Determine the worst case latency - NumLinePair = Number of line pairs to request(1 = 2 lines, 2 = 4 lines) - WorstCaseLatency = The worst case time from urgent to when the MC starts - to return data - READ_DELAY_IDLE_MAX = constant of 1us - ChunkTime = the time it takes the DCP to send one chunk of data to the LB - which consists of pipeline delay and - inter chunk gap - */ - if (info->IsIGP) { - if (num_line_pair > 1) - worst_case_latency = read_delay_latency + 3 * chunk_time; - else - worst_case_latency = read_delay_latency + 2 * chunk_time; - } else { - if (num_line_pair > 1) - worst_case_latency = read_delay_latency + 3 * chunk_time; - else - worst_case_latency = read_delay_latency + chunk_time; - } - - /* Determine the tolerable latency - TolerableLatency = Any given request has only 1 line time for the data to be returned - LBRequestFifoDepth = Number of chunk requests the LB can put into the request FIFO for a display - LineTime = total time for one line of display - ChunkTime = the time it takes the DCP to send one chunk of data to the LB which consists of - pipeline delay and inter chunk gap - */ - if ((2 + lb_request_fifo_depth) >= request_fifo_depth) - tolerable_latency = line_time; - else - tolerable_latency = line_time - (request_fifo_depth - lb_request_fifo_depth - 2) * chunk_time; - - if (mode1 && mode2) { - int d1bpp, d2bpp; - int d1_graph_enable = 1; - int d2_graph_enable = 1; - int d1_ovl_enable = 0; - int d2_ovl_enable = 0; - int d1grph_depth, d2grph_depth; - int d1ovl_depth = 0; - int d2ovl_depth = 0; - int d1_num_line_pair, d2_num_line_pair; - float d1_fill_rate_coeff, d2_fill_rate_coeff; - - switch (pixel_bytes1) { - case 2: - d1grph_depth = 1; - break; - case 4: - d1grph_depth = 2; - break; - default: - d1grph_depth = 0; - break; - } - - switch (pixel_bytes2) { - case 2: - d2grph_depth = 1; - break; - case 4: - d2grph_depth = 2; - break; - default: - d2grph_depth = 0; - break; - } - - /* If both displays are active, determine line buffer fill rate */ - if (d1_scale_en && (vsc1 > 2)) - d1_num_line_pair = 2; - else - d1_num_line_pair = 1; - - if (d2_scale_en && (vsc2 > 2)) - d2_num_line_pair = 2; - else - d2_num_line_pair = 1; - - if (info->IsIGP) { - d1bpp = (d1_graph_enable * pow(2, d1grph_depth) * 8) + (d1_ovl_enable * pow(2, d1ovl_depth) * 8); - d2bpp = (d2_graph_enable * pow(2, d2grph_depth) * 8) + (d2_ovl_enable * pow(2, d2ovl_depth) * 8); - - if (d1bpp > 64) - d1_fill_rate_coeff = d1bpp * d1_num_line_pair; - else - d1_fill_rate_coeff = d1_num_line_pair; - - if (d2bpp > 64) - d2_fill_rate_coeff = d2bpp * d2_num_line_pair; - else - d2_fill_rate_coeff = d2_num_line_pair; - - fill_rate = sclkfreq / (d1_fill_rate_coeff + d2_fill_rate_coeff); - } else { - d1bpp = (d1grph_depth + d1ovl_depth) * 16; - d2bpp = (d2grph_depth + d2ovl_depth) * 16; - - if (d1bpp > 64) - d1_fill_rate_coeff = d1bpp / d1_num_line_pair; - else - d1_fill_rate_coeff = d1_num_line_pair; - - if (d2bpp > 64) - d2_fill_rate_coeff = d2bpp / d2_num_line_pair; - else - d2_fill_rate_coeff = d2_num_line_pair; - - fill_rate = sclk / (d1_fill_rate_coeff + d2_fill_rate_coeff); - - /* Convert line buffer fill rate from period to frequency */ - fill_rate = 1 / fill_rate; - } - } else { - int dxbpp; - int dx_grph_enable = 1; - int dx_ovl_enable = 0; - int dxgrph_depth; - int dxovl_depth = 0; - int cpp; - - if (i == 0) - cpp = pixel_bytes1; - else - cpp = pixel_bytes2; - - switch (cpp) { - case 2: - dxgrph_depth = 1; - break; - case 4: - dxgrph_depth = 2; - break; - default: - dxgrph_depth = 0; - break; - } - - /* If only one display active, the line buffer fill rate becomes */ - if (info->IsIGP) { - dxbpp = (dx_grph_enable * pow(2, dxgrph_depth) * 8) + (dx_ovl_enable * pow(2, dxovl_depth) * 8); - if (dxbpp > 64) - fill_rate = sclkfreq / dxbpp / num_line_pair; - else - fill_rate = sclkfreq / num_line_pair; - } else { - dxbpp = (dxgrph_depth + dxovl_depth) * 16; - - if (dxbpp > 64) - fill_rate = sclk / dxbpp / num_line_pair; - else - fill_rate = sclk / num_line_pair; - - /* Convert line buffer fill rate from period to frequency */ - fill_rate = 1 / fill_rate; - } - } - - /* Determine the maximum priority mark - width = viewport width in pixels - */ - priority_mark_max = ceil(width/16); - - /* Determine estimated width */ - estimated_width = (tolerable_latency - worst_case_latency) / consumption_time; - - /* Determine priority mark based on active time */ - if (info->IsIGP) { - if (estimated_width > width) - priority_mark = 10; - else - priority_mark = priority_mark_max - ceil(estimated_width / 16); - } else { - if (estimated_width > width) - priority_mark = priority_mark_max; - else - priority_mark = priority_mark_max - ceil(estimated_width / 16); - } - - /* Determine priority mark 2 based on worst case latency, - consumption rate, fill rate and active time - */ - if (info->IsIGP) { - if (consumption_rate > fill_rate) - priority_mark2 = ceil((worst_case_latency * consumption_rate + (consumption_rate - fill_rate) * active_time) / 1000 / 16); - else - priority_mark2 = ceil(worst_case_latency * consumption_rate / 1000 / 16); - } else { - if (consumption_rate > fill_rate) - priority_mark2 = ceil(worst_case_latency * consumption_rate + (consumption_rate - fill_rate) * active_time / 16); - else - priority_mark2 = ceil(worst_case_latency * consumption_rate / 16); - } - - /* Determine final priority mark and clamp if necessary */ - priority_mark = max(priority_mark, priority_mark2); - if (priority_mark < 0) - priority_mark = 0; - else if (priority_mark > priority_mark_max) - priority_mark = priority_mark_max; - - priority_cnt = priority_mark & AVIVO_DxMODE_PRIORITY_MARK_MASK; - - if (info->DispPriority == 2) - priority_cnt |= AVIVO_DxMODE_PRIORITY_ALWAYS_ON; - - /*ErrorF("priority_mark %d: 0x%x\n", i, priority_mark);*/ - - /* Determine which display to program priority mark for */ - /* FIXME: program DxMODE_PRIORITY_B_CNT for slower sclk */ - if (i == 0) { - OUTREG(AVIVO_D1MODE_PRIORITY_A_CNT, priority_cnt); - OUTREG(AVIVO_D1MODE_PRIORITY_B_CNT, priority_cnt); - } else { - OUTREG(AVIVO_D2MODE_PRIORITY_A_CNT, priority_cnt); - OUTREG(AVIVO_D2MODE_PRIORITY_B_CNT, priority_cnt); - } - } - -} diff --git a/src/atombios_output.c b/src/atombios_output.c deleted file mode 100644 index 6c908870..00000000 --- a/src/atombios_output.c +++ /dev/null @@ -1,2775 +0,0 @@ -/* - * Copyright © 2007 Red Hat, Inc. - * Copyright 2007 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - * - * Authors: - * Dave Airlie <airlied@redhat.com> - * Alex Deucher <alexdeucher@gmail.com> - * - */ - -/* - * avivo output handling functions. - */ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif -/* DPMS */ -#ifdef HAVE_XEXTPROTO_71 -#include <X11/extensions/dpmsconst.h> -#else -#define DPMS_SERVER -#include <X11/extensions/dpms.h> -#endif - -#include <unistd.h> - -#include "radeon.h" -#include "radeon_reg.h" -#include "radeon_macros.h" -#include "radeon_atombios.h" - -#include "ati_pciids_gen.h" - -const char *device_name[12] = { - "CRT1", - "LCD1", - "TV1", - "DFP1", - "CRT2", - "LCD2", - "TV2", - "DFP2", - "CV", - "DFP3", - "DFP4", - "DFP5", -}; - -#define AUX_NATIVE_WRITE 0x8 -#define AUX_NATIVE_READ 0x9 - -#define AUX_I2C_WRITE 0x0 -#define AUX_I2C_READ 0x1 -#define AUX_I2C_STATUS 0x2 -#define AUX_I2C_MOT 0x4 - -#define DP_DPCD_REV 0x0 -#define DP_MAX_LINK_RATE 0x1 -#define DP_MAX_LANE_COUNT 0x2 -#define DP_MAX_DOWNSPREAD 0x3 -#define DP_NORP 0x4 -#define DP_DOWNSTREAMPORT_PRESENT 0x5 -#define DP_MAIN_LINK_CHANNEL_CONFIG 0x6 -#define DP_DP11_DOWNSTREAM_PORT_COUNT 0x7 - -/* from intel i830_dp.h */ -#define DP_LINK_BW_SET 0x100 -//# define DP_LINK_BW_1_62 0x06 -//# define DP_LINK_BW_2_7 0x0a -#define DP_LANE_COUNT_SET 0x101 -# define DP_LANE_COUNT_MASK 0x0f -# define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7) - -#define DP_TRAINING_PATTERN_SET 0x102 - -# define DP_TRAINING_PATTERN_DISABLE 0 -# define DP_TRAINING_PATTERN_1 1 -# define DP_TRAINING_PATTERN_2 2 -# define DP_TRAINING_PATTERN_MASK 0x3 - -# define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2) -# define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2) -# define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2) -# define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2) -# define DP_LINK_QUAL_PATTERN_MASK (3 << 2) -# define DP_RECOVERED_CLOCK_OUT_EN (1 << 4) -# define DP_LINK_SCRAMBLING_DISABLE (1 << 5) - -# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6) -# define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6) -# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6) -# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6) - -#define DP_TRAINING_LANE0_SET 0x103 -#define DP_TRAINING_LANE1_SET 0x104 -#define DP_TRAINING_LANE2_SET 0x105 -#define DP_TRAINING_LANE3_SET 0x106 -# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 -# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 -# define DP_TRAIN_MAX_SWING_REACHED (1 << 2) -# define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0) -# define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0) -# define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0) -# define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0) - -# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) -# define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3) -# define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3) -# define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3) -# define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3) - -# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 -# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5) -#define DP_DOWNSPREAD_CTRL 0x107 -# define DP_SPREAD_AMP_0_5 (1 << 4) - -#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 -# define DP_SET_ANSI_8B10B (1 << 0) - -#define DP_LANE0_1_STATUS 0x202 -#define DP_LANE2_3_STATUS 0x203 - -# define DP_LANE_CR_DONE (1 << 0) -# define DP_LANE_CHANNEL_EQ_DONE (1 << 1) -# define DP_LANE_SYMBOL_LOCKED (1 << 2) - -#define DP_LANE_ALIGN_STATUS_UPDATED 0x204 -#define DP_INTERLANE_ALIGN_DONE (1 << 0) -#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) -#define DP_LINK_STATUS_UPDATED (1 << 7) - -#define DP_SINK_STATUS 0x205 - -#define DP_RECEIVE_PORT_0_STATUS (1 << 0) -#define DP_RECEIVE_PORT_1_STATUS (1 << 1) - -#define DP_ADJUST_REQUEST_LANE0_1 0x206 -#define DP_ADJUST_REQUEST_LANE2_3 0x207 - -#define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03 -#define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0 -#define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c -#define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2 -#define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30 -#define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4 -#define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 -#define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 - -#define DP_LINK_STATUS_SIZE 6 -#define DP_LINK_CONFIGURATION_SIZE 9 - -#define DP_SET_POWER_D0 0x1 -#define DP_SET_POWER_D3 0x2 - -static void do_displayport_link_train(xf86OutputPtr output); - -static int -atombios_output_dac_setup(xf86OutputPtr output, int action) -{ - RADEONOutputPrivatePtr radeon_output = output->driver_private; - RADEONInfoPtr info = RADEONPTR(output->scrn); - radeon_encoder_ptr radeon_encoder = radeon_get_encoder(output); - radeon_tvout_ptr tvout = &radeon_output->tvout; - DAC_ENCODER_CONTROL_PS_ALLOCATION disp_data; - AtomBiosArgRec data; - unsigned char *space; - int index = 0, num = 0; - int clock = radeon_output->pixel_clock; - - if (radeon_encoder == NULL) - return ATOM_NOT_IMPLEMENTED; - - memset(&disp_data,0, sizeof(disp_data)); - - switch (radeon_encoder->encoder_id) { - case ENCODER_OBJECT_ID_INTERNAL_DAC1: - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: - index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl); - num = 1; - break; - case ENCODER_OBJECT_ID_INTERNAL_DAC2: - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: - index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl); - num = 2; - break; - } - - disp_data.ucAction =action; - - if (radeon_output->active_device & (ATOM_DEVICE_CRT_SUPPORT)) - disp_data.ucDacStandard = ATOM_DAC1_PS2; - else if (radeon_output->active_device & (ATOM_DEVICE_CV_SUPPORT)) - disp_data.ucDacStandard = ATOM_DAC1_CV; - else { - switch (tvout->tvStd) { - case TV_STD_PAL: - case TV_STD_PAL_M: - case TV_STD_SCART_PAL: - case TV_STD_SECAM: - case TV_STD_PAL_CN: - disp_data.ucDacStandard = ATOM_DAC1_PAL; - break; - case TV_STD_NTSC: - case TV_STD_NTSC_J: - case TV_STD_PAL_60: - default: - disp_data.ucDacStandard = ATOM_DAC1_NTSC; - break; - } - } - disp_data.usPixelClock = cpu_to_le16(clock / 10); - - data.exec.index = index; - data.exec.dataSpace = (void *)&space; - data.exec.pspace = &disp_data; - - if (RHDAtomBiosFunc(info->atomBIOS->pScrn, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { - ErrorF("Output DAC%d setup success\n", num); - return ATOM_SUCCESS; - } - - ErrorF("Output DAC%d setup failed\n", num); - return ATOM_NOT_IMPLEMENTED; - -} - -static int -atombios_output_tv_setup(xf86OutputPtr output, int action) -{ - RADEONOutputPrivatePtr radeon_output = output->driver_private; - radeon_tvout_ptr tvout = &radeon_output->tvout; - RADEONInfoPtr info = RADEONPTR(output->scrn); - TV_ENCODER_CONTROL_PS_ALLOCATION disp_data; - AtomBiosArgRec data; - unsigned char *space; - int clock = radeon_output->pixel_clock; - - memset(&disp_data,0, sizeof(disp_data)); - - disp_data.sTVEncoder.ucAction = action; - - if (radeon_output->active_device & (ATOM_DEVICE_CV_SUPPORT)) - disp_data.sTVEncoder.ucTvStandard = ATOM_TV_CV; - else { - switch (tvout->tvStd) { - case TV_STD_NTSC: - disp_data.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; - break; - case TV_STD_PAL: - disp_data.sTVEncoder.ucTvStandard = ATOM_TV_PAL; - break; - case TV_STD_PAL_M: - disp_data.sTVEncoder.ucTvStandard = ATOM_TV_PALM; - break; - case TV_STD_PAL_60: - disp_data.sTVEncoder.ucTvStandard = ATOM_TV_PAL60; - break; - case TV_STD_NTSC_J: - disp_data.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ; - break; - case TV_STD_SCART_PAL: - disp_data.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */ - break; - case TV_STD_SECAM: - disp_data.sTVEncoder.ucTvStandard = ATOM_TV_SECAM; - break; - case TV_STD_PAL_CN: - disp_data.sTVEncoder.ucTvStandard = ATOM_TV_PALCN; - break; - default: - disp_data.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; - break; - } - } - - disp_data.sTVEncoder.usPixelClock = cpu_to_le16(clock / 10); - data.exec.index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); - data.exec.dataSpace = (void *)&space; - data.exec.pspace = &disp_data; - - if (RHDAtomBiosFunc(info->atomBIOS->pScrn, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { - ErrorF("Output TV setup success\n"); - return ATOM_SUCCESS; - } - - ErrorF("Output TV setup failed\n"); - return ATOM_NOT_IMPLEMENTED; - -} - -int -atombios_external_tmds_setup(xf86OutputPtr output, int action) -{ - RADEONOutputPrivatePtr radeon_output = output->driver_private; - ScrnInfoPtr pScrn = output->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION disp_data; - AtomBiosArgRec data; - unsigned char *space; - int clock = radeon_output->pixel_clock; - - memset(&disp_data,0, sizeof(disp_data)); - - disp_data.sXTmdsEncoder.ucEnable = action; - - if (clock > 165000) - disp_data.sXTmdsEncoder.ucMisc = PANEL_ENCODER_MISC_DUAL; - - if (pScrn->rgbBits == 8) - disp_data.sXTmdsEncoder.ucMisc |= (1 << 1); - - data.exec.index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); - data.exec.dataSpace = (void *)&space; - data.exec.pspace = &disp_data; - - if (RHDAtomBiosFunc(info->atomBIOS->pScrn, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { - ErrorF("External TMDS setup success\n"); - return ATOM_SUCCESS; - } - - ErrorF("External TMDS setup failed\n"); - return ATOM_NOT_IMPLEMENTED; -} - -static int -atombios_output_ddia_setup(xf86OutputPtr output, int action) -{ - RADEONOutputPrivatePtr radeon_output = output->driver_private; - RADEONInfoPtr info = RADEONPTR(output->scrn); - DVO_ENCODER_CONTROL_PS_ALLOCATION disp_data; - AtomBiosArgRec data; - unsigned char *space; - int clock = radeon_output->pixel_clock; - - memset(&disp_data,0, sizeof(disp_data)); - - disp_data.sDVOEncoder.ucAction = action; - disp_data.sDVOEncoder.usPixelClock = cpu_to_le16(clock / 10); - - if (clock > 165000) - disp_data.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL; - - data.exec.index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); - data.exec.dataSpace = (void *)&space; - data.exec.pspace = &disp_data; - - if (RHDAtomBiosFunc(info->atomBIOS->pScrn, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { - ErrorF("DDIA setup success\n"); - return ATOM_SUCCESS; - } - - ErrorF("DDIA setup failed\n"); - return ATOM_NOT_IMPLEMENTED; -} - -static int -atombios_output_digital_setup(xf86OutputPtr output, int action) -{ - RADEONOutputPrivatePtr radeon_output = output->driver_private; - ScrnInfoPtr pScrn = output->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - radeon_encoder_ptr radeon_encoder = radeon_get_encoder(output); - LVDS_ENCODER_CONTROL_PS_ALLOCATION disp_data; - LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 disp_data2; - AtomBiosArgRec data; - unsigned char *space; - int index = 0; - int major, minor; - int lvds_misc = 0; - int clock = radeon_output->pixel_clock; - - if (radeon_encoder == NULL) - return ATOM_NOT_IMPLEMENTED; - - if (radeon_output->active_device & (ATOM_DEVICE_LCD_SUPPORT)) { - radeon_lvds_ptr lvds = (radeon_lvds_ptr)radeon_encoder->dev_priv; - if (lvds == NULL) - return ATOM_NOT_IMPLEMENTED; - lvds_misc = lvds->lvds_misc; - } - - memset(&disp_data,0, sizeof(disp_data)); - memset(&disp_data2,0, sizeof(disp_data2)); - - switch (radeon_encoder->encoder_id) { - case ENCODER_OBJECT_ID_INTERNAL_LVDS: - index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); - break; - case ENCODER_OBJECT_ID_INTERNAL_TMDS1: - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: - index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl); - break; - case ENCODER_OBJECT_ID_INTERNAL_LVTM1: - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: - if (radeon_output->active_device & (ATOM_DEVICE_LCD_SUPPORT)) - index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); - else - index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl); - break; - } - - atombios_get_command_table_version(info->atomBIOS, index, &major, &minor); - - /*ErrorF("table is %d %d\n", major, minor);*/ - switch (major) { - case 0: - case 1: - case 2: - switch (minor) { - case 1: - disp_data.ucMisc = 0; - disp_data.ucAction = action; - if ((radeon_output->ConnectorType == CONNECTOR_HDMI_TYPE_A) || - (radeon_output->ConnectorType == CONNECTOR_HDMI_TYPE_B)) - disp_data.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; - disp_data.usPixelClock = cpu_to_le16(clock / 10); - if (radeon_output->active_device & (ATOM_DEVICE_LCD_SUPPORT)) { - if (lvds_misc & (1 << 0)) - disp_data.ucMisc |= PANEL_ENCODER_MISC_DUAL; - if (lvds_misc & (1 << 1)) - disp_data.ucMisc |= (1 << 1); - } else { - if (radeon_output->linkb) - disp_data.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; - if (clock > 165000) - disp_data.ucMisc |= PANEL_ENCODER_MISC_DUAL; - if (pScrn->rgbBits == 8) - disp_data.ucMisc |= (1 << 1); - } - data.exec.pspace = &disp_data; - break; - case 2: - case 3: - disp_data2.ucMisc = 0; - disp_data2.ucAction = action; - if (minor == 3) { - if (radeon_output->coherent_mode) { - disp_data2.ucMisc |= PANEL_ENCODER_MISC_COHERENT; - xf86DrvMsg(output->scrn->scrnIndex, X_INFO, "Coherent Mode enabled\n"); - } - } - if ((radeon_output->ConnectorType == CONNECTOR_HDMI_TYPE_A) || - (radeon_output->ConnectorType == CONNECTOR_HDMI_TYPE_B)) - disp_data2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; - disp_data2.usPixelClock = cpu_to_le16(clock / 10); - disp_data2.ucTruncate = 0; - disp_data2.ucSpatial = 0; - disp_data2.ucTemporal = 0; - disp_data2.ucFRC = 0; - if (radeon_output->active_device & (ATOM_DEVICE_LCD_SUPPORT)) { - if (lvds_misc & (1 << 0)) - disp_data2.ucMisc |= PANEL_ENCODER_MISC_DUAL; - if (lvds_misc & (1 << 5)) { - disp_data2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN; - if (lvds_misc & (1 << 1)) - disp_data2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH; - } - if (lvds_misc & (1 << 6)) { - disp_data2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN; - if (lvds_misc & (1 << 1)) - disp_data2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH; - if (((lvds_misc >> 2) & 0x3) == 2) - disp_data2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4; - } - } else { - if (radeon_output->linkb) - disp_data2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; - if (clock > 165000) - disp_data2.ucMisc |= PANEL_ENCODER_MISC_DUAL; - } - data.exec.pspace = &disp_data2; - break; - default: - ErrorF("Unknown table version\n"); - exit(-1); - } - break; - default: - ErrorF("Unknown table version\n"); - exit(-1); - } - - data.exec.index = index; - data.exec.dataSpace = (void *)&space; - - if (RHDAtomBiosFunc(info->atomBIOS->pScrn, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { - ErrorF("Output digital setup success\n"); - return ATOM_SUCCESS; - } - - ErrorF("Output digital setup failed\n"); - return ATOM_NOT_IMPLEMENTED; -} - -static int -atombios_maybe_hdmi_mode(xf86OutputPtr output) -{ -#ifndef EDID_COMPLETE_RAWDATA - /* there's no getting this right unless we have complete EDID */ - return ATOM_ENCODER_MODE_DVI; -#else - if (output && xf86MonitorIsHDMI(output->MonInfo)) - return ATOM_ENCODER_MODE_HDMI; - - return ATOM_ENCODER_MODE_DVI; -#endif -} - -int -atombios_get_encoder_mode(xf86OutputPtr output) -{ - ScrnInfoPtr pScrn = output->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONOutputPrivatePtr radeon_output = output->driver_private; - - /* DVI should really be atombios_maybe_hdmi_mode() as well */ - switch (radeon_output->ConnectorType) { - case CONNECTOR_DVI_I: - if (radeon_output->active_device & (ATOM_DEVICE_DFP_SUPPORT)) - return ATOM_ENCODER_MODE_DVI; - else - return ATOM_ENCODER_MODE_CRT; - break; - case CONNECTOR_DVI_D: - default: - return ATOM_ENCODER_MODE_DVI; - break; - case CONNECTOR_HDMI_TYPE_A: - case CONNECTOR_HDMI_TYPE_B: - if (IS_DCE4_VARIANT) - return ATOM_ENCODER_MODE_DVI; - else - return atombios_maybe_hdmi_mode(output); - break; - case CONNECTOR_LVDS: - return ATOM_ENCODER_MODE_LVDS; - break; - case CONNECTOR_DISPLAY_PORT: - case CONNECTOR_EDP: - if (radeon_output->MonType == MT_DP) - return ATOM_ENCODER_MODE_DP; - else { - if (IS_DCE4_VARIANT) - return ATOM_ENCODER_MODE_DVI; - else - return atombios_maybe_hdmi_mode(output); - } - break; - case CONNECTOR_DVI_A: - case CONNECTOR_VGA: - case CONNECTOR_STV: - case CONNECTOR_CTV: - case CONNECTOR_DIN: - if (radeon_output->active_device & (ATOM_DEVICE_TV_SUPPORT)) - return ATOM_ENCODER_MODE_TV; - else if (radeon_output->active_device & (ATOM_DEVICE_CV_SUPPORT)) - return ATOM_ENCODER_MODE_CV; - else - return ATOM_ENCODER_MODE_CRT; - break; - } - -} - -static const int dp_clocks[] = { - 5400, // 1 lane, 1.62 Ghz - 9000, // 1 lane, 2.70 Ghz - 10800, // 2 lane, 1.62 Ghz - 18000, // 2 lane, 2.70 Ghz - 21600, // 4 lane, 1.62 Ghz - 36000, // 4 lane, 2.70 Ghz -}; -static const int num_dp_clocks = sizeof(dp_clocks) / sizeof(int); - -# define DP_LINK_BW_1_62 0x06 -# define DP_LINK_BW_2_7 0x0a -static int radeon_dp_max_lane_count(xf86OutputPtr output); - -static int -dp_lanes_for_mode_clock(xf86OutputPtr output, int mode_clock) -{ - RADEONOutputPrivatePtr radeon_output = output->driver_private; - int i; - int max_link_bw = radeon_output->dpcd[1]; - int max_lane_count = radeon_dp_max_lane_count(output); - - switch (max_link_bw) { - case DP_LINK_BW_1_62: - default: - for (i = 0; i < num_dp_clocks; i++) { - if (i % 2) - continue; - switch (max_lane_count) { - case 1: - if (i > 1) - return 0; - break; - case 2: - if (i > 3) - return 0; - break; - case 4: - default: - break; - } - if (dp_clocks[i] > (mode_clock/10)) { - if (i < 2) - return 1; - else if (i < 4) - return 2; - else - return 4; - } - } - break; - case DP_LINK_BW_2_7: - for (i = 0; i < num_dp_clocks; i++) { - switch (max_lane_count) { - case 1: - if (i > 1) - return 0; - break; - case 2: - if (i > 3) - return 0; - break; - case 4: - default: - break; - } - if (dp_clocks[i] > (mode_clock/10)) { - if (i < 2) - return 1; - else if (i < 4) - return 2; - else - return 4; - } - } - break; - } - - return 0; -} - -static int -dp_link_clock_for_mode_clock(xf86OutputPtr output, int mode_clock) -{ - RADEONOutputPrivatePtr radeon_output = output->driver_private; - int i; - int max_link_bw = radeon_output->dpcd[1]; - int max_lane_count = radeon_dp_max_lane_count(output); - - switch (max_link_bw) { - case DP_LINK_BW_1_62: - default: - for (i = 0; i < num_dp_clocks; i++) { - if (i % 2) - continue; - switch (max_lane_count) { - case 1: - if (i > 1) - return 0; - break; - case 2: - if (i > 3) - return 0; - break; - case 4: - default: - break; - } - if (dp_clocks[i] > (mode_clock/10)) - return 16200; - } - break; - case DP_LINK_BW_2_7: - for (i = 0; i < num_dp_clocks; i++) { - switch (max_lane_count) { - case 1: - if (i > 1) - return 0; - break; - case 2: - if (i > 3) - return 0; - break; - case 4: - default: - break; - } - if (dp_clocks[i] > (mode_clock/10)) - return (i % 2) ? 27000 : 16200; - } - break; - } - - return 0; -} - -/* - * DIG Encoder/Transmitter Setup - * - * DCE 3.0/3.1 - * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA. - * Supports up to 3 digital outputs - * - 2 DIG encoder blocks. - * DIG1 can drive UNIPHY link A or link B - * DIG2 can drive UNIPHY link B or LVTMA - * - * DCE 3.2 - * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B). - * Supports up to 5 digital outputs - * - 2 DIG encoder blocks. - * DIG1/2 can drive UNIPHY0/1/2 link A or link B - * - * DCE 4.0 - * - 3 DIG transmitter blocks UNPHY0/1/2 (links A and B). - * Supports up to 6 digital outputs - * - 6 DIG encoder blocks. - * - DIG to PHY mapping is hardcoded - * DIG1 drives UNIPHY0 link A, A+B - * DIG2 drives UNIPHY0 link B - * DIG3 drives UNIPHY1 link A, A+B - * DIG4 drives UNIPHY1 link B - * DIG5 drives UNIPHY2 link A, A+B - * DIG6 drives UNIPHY2 link B - * - * Routing - * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links) - * Examples: - * crtc0 -> dig2 -> LVTMA links A+B - * crtc1 -> dig1 -> UNIPHY0 link B - * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS - * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI - */ - -union dig_encoder_control { - DIG_ENCODER_CONTROL_PS_ALLOCATION v1; - DIG_ENCODER_CONTROL_PARAMETERS_V2 v2; - DIG_ENCODER_CONTROL_PARAMETERS_V3 v3; -}; - -static int -atombios_output_dig_encoder_setup(xf86OutputPtr output, int action) -{ - RADEONOutputPrivatePtr radeon_output = output->driver_private; - RADEONInfoPtr info = RADEONPTR(output->scrn); - radeon_encoder_ptr radeon_encoder = radeon_get_encoder(output); - union dig_encoder_control disp_data; - AtomBiosArgRec data; - unsigned char *space; - int index = 0, major, minor; - int clock = radeon_output->pixel_clock; - - if (radeon_encoder == NULL) - return ATOM_NOT_IMPLEMENTED; - - memset(&disp_data,0, sizeof(disp_data)); - - if (IS_DCE4_VARIANT) - index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl); - else if (radeon_output->dig_encoder) - index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); - else - index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); - - atombios_get_command_table_version(info->atomBIOS, index, &major, &minor); - - disp_data.v1.ucAction = action; - disp_data.v1.usPixelClock = cpu_to_le16(clock / 10); - disp_data.v1.ucEncoderMode = atombios_get_encoder_mode(output); - - if (disp_data.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) { - if (dp_link_clock_for_mode_clock(output, clock) == 27000) - disp_data.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; - disp_data.v1.ucLaneNum = dp_lanes_for_mode_clock(output, clock); - } else if (clock > 165000) - disp_data.v1.ucLaneNum = 8; - else - disp_data.v1.ucLaneNum = 4; - - if (IS_DCE4_VARIANT) { - disp_data.v3.acConfig.ucDigSel = radeon_output->dig_encoder; - disp_data.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR; - } else { - switch (radeon_encoder->encoder_id) { - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: - disp_data.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; - break; - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: - disp_data.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2; - break; - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: - disp_data.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; - break; - } - if (radeon_output->linkb) - disp_data.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; - else - disp_data.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; - } - - data.exec.index = index; - data.exec.dataSpace = (void *)&space; - data.exec.pspace = &disp_data; - - if (RHDAtomBiosFunc(info->atomBIOS->pScrn, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { - ErrorF("Output DIG%d encoder setup success\n", radeon_output->dig_encoder); - return ATOM_SUCCESS; - } - - ErrorF("Output DIG%d setup failed\n", radeon_output->dig_encoder); - return ATOM_NOT_IMPLEMENTED; - -} - -union dig_transmitter_control { - DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; - DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2; - DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3; -}; - -static int -atombios_output_dig_transmitter_setup(xf86OutputPtr output, int action, uint8_t lane_num, uint8_t lane_set) -{ - RADEONOutputPrivatePtr radeon_output = output->driver_private; - RADEONInfoPtr info = RADEONPTR(output->scrn); - radeon_encoder_ptr radeon_encoder = radeon_get_encoder(output); - union dig_transmitter_control disp_data; - AtomBiosArgRec data; - unsigned char *space; - int index = 0, num = 0; - int major, minor; - int clock = radeon_output->pixel_clock; - - if (radeon_encoder == NULL) - return ATOM_NOT_IMPLEMENTED; - - memset(&disp_data,0, sizeof(disp_data)); - - if (IS_DCE32_VARIANT || IS_DCE4_VARIANT) - index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); - else { - switch (radeon_encoder->encoder_id) { - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: - index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl); - break; - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: - index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl); - break; - } - } - - atombios_get_command_table_version(info->atomBIOS, index, &major, &minor); - - disp_data.v1.ucAction = action; - if (action == ATOM_TRANSMITTER_ACTION_INIT) { - disp_data.v1.usInitInfo = radeon_output->connector_object_id; - } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { - disp_data.v1.asMode.ucLaneSel = lane_num; - disp_data.v1.asMode.ucLaneSet = lane_set; - } else { - if (radeon_output->MonType == MT_DP) - disp_data.v1.usPixelClock = - cpu_to_le16(dp_link_clock_for_mode_clock(output, clock)); - else if (clock > 165000) - disp_data.v1.usPixelClock = cpu_to_le16((clock / 2) / 10); - else - disp_data.v1.usPixelClock = cpu_to_le16(clock / 10); - } - - if (IS_DCE4_VARIANT) { - if (radeon_output->MonType == MT_DP) - disp_data.v3.ucLaneNum = dp_lanes_for_mode_clock(output, clock); - else if (clock > 165000) - disp_data.v3.ucLaneNum = 8; - else - disp_data.v3.ucLaneNum = 4; - - if (radeon_output->linkb) { - disp_data.v3.acConfig.ucLinkSel = 1; - disp_data.v2.acConfig.ucEncoderSel = 1; - } - - // select the PLL for the UNIPHY - if (radeon_output->MonType == MT_DP && info->dp_extclk) - disp_data.v3.acConfig.ucRefClkSource = 2; /* ext clk */ - else - disp_data.v3.acConfig.ucRefClkSource = radeon_output->pll_id; - - switch (radeon_encoder->encoder_id) { - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: - disp_data.v3.acConfig.ucTransmitterSel = 0; - num = 0; - break; - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: - disp_data.v3.acConfig.ucTransmitterSel = 1; - num = 1; - break; - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: - disp_data.v3.acConfig.ucTransmitterSel = 2; - num = 2; - break; - } - - if (radeon_output->MonType == MT_DP) - disp_data.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */ - else if (radeon_output->active_device & (ATOM_DEVICE_DFP_SUPPORT)) { - if (radeon_output->coherent_mode) - disp_data.v3.acConfig.fCoherentMode = 1; - if (clock > 165000) - disp_data.v3.acConfig.fDualLinkConnector = 1; - } - } else if (IS_DCE32_VARIANT) { - if (radeon_output->dig_encoder) - disp_data.v2.acConfig.ucEncoderSel = 1; - - if (radeon_output->linkb) - disp_data.v2.acConfig.ucLinkSel = 1; - - switch (radeon_encoder->encoder_id) { - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: - disp_data.v2.acConfig.ucTransmitterSel = 0; - num = 0; - break; - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: - disp_data.v2.acConfig.ucTransmitterSel = 1; - num = 1; - break; - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: - disp_data.v2.acConfig.ucTransmitterSel = 2; - num = 2; - break; - } - - if (radeon_output->MonType == MT_DP) - disp_data.v2.acConfig.fCoherentMode = 1; /* DP requires coherent */ - else if (radeon_output->active_device & (ATOM_DEVICE_DFP_SUPPORT)) { - if (radeon_output->coherent_mode) - disp_data.v2.acConfig.fCoherentMode = 1; - if (clock > 165000) - disp_data.v2.acConfig.fDualLinkConnector = 1; - } - } else { - disp_data.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; - - if (radeon_output->dig_encoder) - disp_data.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER; - else - disp_data.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER; - - switch (radeon_encoder->encoder_id) { - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: - if (info->IsIGP) { - if (clock > 165000) { - if (radeon_output->igp_lane_info & 0x3) - disp_data.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; - else if (radeon_output->igp_lane_info & 0xc) - disp_data.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; - } else { - if (radeon_output->igp_lane_info & 0x1) - disp_data.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; - else if (radeon_output->igp_lane_info & 0x2) - disp_data.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; - else if (radeon_output->igp_lane_info & 0x4) - disp_data.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; - else if (radeon_output->igp_lane_info & 0x8) - disp_data.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; - } - } - break; - } - if (radeon_output->linkb) - disp_data.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB; - else - disp_data.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; - - if (radeon_output->MonType == MT_DP) - disp_data.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; /* DP requires coherent */ - else if (radeon_output->active_device & (ATOM_DEVICE_DFP_SUPPORT)) { - if (radeon_output->coherent_mode) - disp_data.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; - if (clock > 165000) - disp_data.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK; - } - } - - data.exec.index = index; - data.exec.dataSpace = (void *)&space; - data.exec.pspace = &disp_data; - - if (RHDAtomBiosFunc(info->atomBIOS->pScrn, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { - if (IS_DCE32_VARIANT) - ErrorF("Output UNIPHY%d transmitter setup success\n", num); - else - ErrorF("Output DIG%d transmitter setup success\n", num); - return ATOM_SUCCESS; - } - - ErrorF("Output DIG%d transmitter setup failed\n", num); - return ATOM_NOT_IMPLEMENTED; - -} - -static void atom_rv515_force_tv_scaler(ScrnInfoPtr pScrn, RADEONCrtcPrivatePtr radeon_crtc) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - int index_reg = 0x6578, data_reg = 0x657c; - - index_reg += radeon_crtc->crtc_offset; - data_reg += radeon_crtc->crtc_offset; - - OUTREG(0x659C + radeon_crtc->crtc_offset, 0x0); - OUTREG(0x6594 + radeon_crtc->crtc_offset, 0x705); - OUTREG(0x65A4 + radeon_crtc->crtc_offset, 0x10001); - OUTREG(0x65D8 + radeon_crtc->crtc_offset, 0x0); - OUTREG(0x65B0 + radeon_crtc->crtc_offset, 0x0); - OUTREG(0x65C0 + radeon_crtc->crtc_offset, 0x0); - OUTREG(0x65D4 + radeon_crtc->crtc_offset, 0x0); - OUTREG(index_reg,0x0); - OUTREG(data_reg,0x841880A8); - OUTREG(index_reg,0x1); - OUTREG(data_reg,0x84208680); - OUTREG(index_reg,0x2); - OUTREG(data_reg,0xBFF880B0); - OUTREG(index_reg,0x100); - OUTREG(data_reg,0x83D88088); - OUTREG(index_reg,0x101); - OUTREG(data_reg,0x84608680); - OUTREG(index_reg,0x102); - OUTREG(data_reg,0xBFF080D0); - OUTREG(index_reg,0x200); - OUTREG(data_reg,0x83988068); - OUTREG(index_reg,0x201); - OUTREG(data_reg,0x84A08680); - OUTREG(index_reg,0x202); - OUTREG(data_reg,0xBFF080F8); - OUTREG(index_reg,0x300); - OUTREG(data_reg,0x83588058); - OUTREG(index_reg,0x301); - OUTREG(data_reg,0x84E08660); - OUTREG(index_reg,0x302); - OUTREG(data_reg,0xBFF88120); - OUTREG(index_reg,0x400); - OUTREG(data_reg,0x83188040); - OUTREG(index_reg,0x401); - OUTREG(data_reg,0x85008660); - OUTREG(index_reg,0x402); - OUTREG(data_reg,0xBFF88150); - OUTREG(index_reg,0x500); - OUTREG(data_reg,0x82D88030); - OUTREG(index_reg,0x501); - OUTREG(data_reg,0x85408640); - OUTREG(index_reg,0x502); - OUTREG(data_reg,0xBFF88180); - OUTREG(index_reg,0x600); - OUTREG(data_reg,0x82A08018); - OUTREG(index_reg,0x601); - OUTREG(data_reg,0x85808620); - OUTREG(index_reg,0x602); - OUTREG(data_reg,0xBFF081B8); - OUTREG(index_reg,0x700); - OUTREG(data_reg,0x82608010); - OUTREG(index_reg,0x701); - OUTREG(data_reg,0x85A08600); - OUTREG(index_reg,0x702); - OUTREG(data_reg,0x800081F0); - OUTREG(index_reg,0x800); - OUTREG(data_reg,0x8228BFF8); - OUTREG(index_reg,0x801); - OUTREG(data_reg,0x85E085E0); - OUTREG(index_reg,0x802); - OUTREG(data_reg,0xBFF88228); - OUTREG(index_reg,0x10000); - OUTREG(data_reg,0x82A8BF00); - OUTREG(index_reg,0x10001); - OUTREG(data_reg,0x82A08CC0); - OUTREG(index_reg,0x10002); - OUTREG(data_reg,0x8008BEF8); - OUTREG(index_reg,0x10100); - OUTREG(data_reg,0x81F0BF28); - OUTREG(index_reg,0x10101); - OUTREG(data_reg,0x83608CA0); - OUTREG(index_reg,0x10102); - OUTREG(data_reg,0x8018BED0); - OUTREG(index_reg,0x10200); - OUTREG(data_reg,0x8148BF38); - OUTREG(index_reg,0x10201); - OUTREG(data_reg,0x84408C80); - OUTREG(index_reg,0x10202); - OUTREG(data_reg,0x8008BEB8); - OUTREG(index_reg,0x10300); - OUTREG(data_reg,0x80B0BF78); - OUTREG(index_reg,0x10301); - OUTREG(data_reg,0x85008C20); - OUTREG(index_reg,0x10302); - OUTREG(data_reg,0x8020BEA0); - OUTREG(index_reg,0x10400); - OUTREG(data_reg,0x8028BF90); - OUTREG(index_reg,0x10401); - OUTREG(data_reg,0x85E08BC0); - OUTREG(index_reg,0x10402); - OUTREG(data_reg,0x8018BE90); - OUTREG(index_reg,0x10500); - OUTREG(data_reg,0xBFB8BFB0); - OUTREG(index_reg,0x10501); - OUTREG(data_reg,0x86C08B40); - OUTREG(index_reg,0x10502); - OUTREG(data_reg,0x8010BE90); - OUTREG(index_reg,0x10600); - OUTREG(data_reg,0xBF58BFC8); - OUTREG(index_reg,0x10601); - OUTREG(data_reg,0x87A08AA0); - OUTREG(index_reg,0x10602); - OUTREG(data_reg,0x8010BE98); - OUTREG(index_reg,0x10700); - OUTREG(data_reg,0xBF10BFF0); - OUTREG(index_reg,0x10701); - OUTREG(data_reg,0x886089E0); - OUTREG(index_reg,0x10702); - OUTREG(data_reg,0x8018BEB0); - OUTREG(index_reg,0x10800); - OUTREG(data_reg,0xBED8BFE8); - OUTREG(index_reg,0x10801); - OUTREG(data_reg,0x89408940); - OUTREG(index_reg,0x10802); - OUTREG(data_reg,0xBFE8BED8); - OUTREG(index_reg,0x20000); - OUTREG(data_reg,0x80008000); - OUTREG(index_reg,0x20001); - OUTREG(data_reg,0x90008000); - OUTREG(index_reg,0x20002); - OUTREG(data_reg,0x80008000); - OUTREG(index_reg,0x20003); - OUTREG(data_reg,0x80008000); - OUTREG(index_reg,0x20100); - OUTREG(data_reg,0x80108000); - OUTREG(index_reg,0x20101); - OUTREG(data_reg,0x8FE0BF70); - OUTREG(index_reg,0x20102); - OUTREG(data_reg,0xBFE880C0); - OUTREG(index_reg,0x20103); - OUTREG(data_reg,0x80008000); - OUTREG(index_reg,0x20200); - OUTREG(data_reg,0x8018BFF8); - OUTREG(index_reg,0x20201); - OUTREG(data_reg,0x8F80BF08); - OUTREG(index_reg,0x20202); - OUTREG(data_reg,0xBFD081A0); - OUTREG(index_reg,0x20203); - OUTREG(data_reg,0xBFF88000); - OUTREG(index_reg,0x20300); - OUTREG(data_reg,0x80188000); - OUTREG(index_reg,0x20301); - OUTREG(data_reg,0x8EE0BEC0); - OUTREG(index_reg,0x20302); - OUTREG(data_reg,0xBFB082A0); - OUTREG(index_reg,0x20303); - OUTREG(data_reg,0x80008000); - OUTREG(index_reg,0x20400); - OUTREG(data_reg,0x80188000); - OUTREG(index_reg,0x20401); - OUTREG(data_reg,0x8E00BEA0); - OUTREG(index_reg,0x20402); - OUTREG(data_reg,0xBF8883C0); - OUTREG(index_reg,0x20403); - OUTREG(data_reg,0x80008000); - OUTREG(index_reg,0x20500); - OUTREG(data_reg,0x80188000); - OUTREG(index_reg,0x20501); - OUTREG(data_reg,0x8D00BE90); - OUTREG(index_reg,0x20502); - OUTREG(data_reg,0xBF588500); - OUTREG(index_reg,0x20503); - OUTREG(data_reg,0x80008008); - OUTREG(index_reg,0x20600); - OUTREG(data_reg,0x80188000); - OUTREG(index_reg,0x20601); - OUTREG(data_reg,0x8BC0BE98); - OUTREG(index_reg,0x20602); - OUTREG(data_reg,0xBF308660); - OUTREG(index_reg,0x20603); - OUTREG(data_reg,0x80008008); - OUTREG(index_reg,0x20700); - OUTREG(data_reg,0x80108000); - OUTREG(index_reg,0x20701); - OUTREG(data_reg,0x8A80BEB0); - OUTREG(index_reg,0x20702); - OUTREG(data_reg,0xBF0087C0); - OUTREG(index_reg,0x20703); - OUTREG(data_reg,0x80008008); - OUTREG(index_reg,0x20800); - OUTREG(data_reg,0x80108000); - OUTREG(index_reg,0x20801); - OUTREG(data_reg,0x8920BED0); - OUTREG(index_reg,0x20802); - OUTREG(data_reg,0xBED08920); - OUTREG(index_reg,0x20803); - OUTREG(data_reg,0x80008010); - OUTREG(index_reg,0x30000); - OUTREG(data_reg,0x90008000); - OUTREG(index_reg,0x30001); - OUTREG(data_reg,0x80008000); - OUTREG(index_reg,0x30100); - OUTREG(data_reg,0x8FE0BF90); - OUTREG(index_reg,0x30101); - OUTREG(data_reg,0xBFF880A0); - OUTREG(index_reg,0x30200); - OUTREG(data_reg,0x8F60BF40); - OUTREG(index_reg,0x30201); - OUTREG(data_reg,0xBFE88180); - OUTREG(index_reg,0x30300); - OUTREG(data_reg,0x8EC0BF00); - OUTREG(index_reg,0x30301); - OUTREG(data_reg,0xBFC88280); - OUTREG(index_reg,0x30400); - OUTREG(data_reg,0x8DE0BEE0); - OUTREG(index_reg,0x30401); - OUTREG(data_reg,0xBFA083A0); - OUTREG(index_reg,0x30500); - OUTREG(data_reg,0x8CE0BED0); - OUTREG(index_reg,0x30501); - OUTREG(data_reg,0xBF7884E0); - OUTREG(index_reg,0x30600); - OUTREG(data_reg,0x8BA0BED8); - OUTREG(index_reg,0x30601); - OUTREG(data_reg,0xBF508640); - OUTREG(index_reg,0x30700); - OUTREG(data_reg,0x8A60BEE8); - OUTREG(index_reg,0x30701); - OUTREG(data_reg,0xBF2087A0); - OUTREG(index_reg,0x30800); - OUTREG(data_reg,0x8900BF00); - OUTREG(index_reg,0x30801); - OUTREG(data_reg,0xBF008900); -} - -static int -atombios_output_yuv_setup(xf86OutputPtr output, Bool enable) -{ - RADEONOutputPrivatePtr radeon_output = output->driver_private; - RADEONInfoPtr info = RADEONPTR(output->scrn); - RADEONCrtcPrivatePtr radeon_crtc = output->crtc->driver_private; - ENABLE_YUV_PS_ALLOCATION disp_data; - AtomBiosArgRec data; - unsigned char *space; - unsigned char *RADEONMMIO = info->MMIO; - uint32_t temp, reg; - - if (info->ChipFamily >= CHIP_FAMILY_R600) - reg = R600_BIOS_3_SCRATCH; - else - reg = RADEON_BIOS_3_SCRATCH; - - //fix up scratch reg handling - temp = INREG(reg); - if (radeon_output->active_device & (ATOM_DEVICE_TV_SUPPORT)) - OUTREG(reg, (ATOM_S3_TV1_ACTIVE | - (radeon_crtc->crtc_id << 18))); - else if (radeon_output->active_device & (ATOM_DEVICE_CV_SUPPORT)) - OUTREG(reg, (ATOM_S3_CV_ACTIVE | - (radeon_crtc->crtc_id << 24))); - else - OUTREG(reg, 0); - - memset(&disp_data, 0, sizeof(disp_data)); - - if (enable) - disp_data.ucEnable = ATOM_ENABLE; - disp_data.ucCRTC = radeon_crtc->crtc_id; - - data.exec.index = GetIndexIntoMasterTable(COMMAND, EnableYUV); - data.exec.dataSpace = (void *)&space; - data.exec.pspace = &disp_data; - - if (RHDAtomBiosFunc(info->atomBIOS->pScrn, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { - - OUTREG(reg, temp); - - ErrorF("crtc %d YUV %s setup success\n", radeon_crtc->crtc_id, enable ? "enable" : "disable"); - return ATOM_SUCCESS; - } - - OUTREG(reg, temp); - - ErrorF("crtc %d YUV %s setup failed\n", radeon_crtc->crtc_id, enable ? "enable" : "disable"); - return ATOM_NOT_IMPLEMENTED; - -} - -static int -atombios_output_overscan_setup(xf86OutputPtr output, DisplayModePtr mode, DisplayModePtr adjusted_mode) -{ - RADEONOutputPrivatePtr radeon_output = output->driver_private; - RADEONCrtcPrivatePtr radeon_crtc = output->crtc->driver_private; - RADEONInfoPtr info = RADEONPTR(output->scrn); - SET_CRTC_OVERSCAN_PS_ALLOCATION overscan_param; - AtomBiosArgRec data; - unsigned char *space; - memset(&overscan_param, 0, sizeof(overscan_param)); - - overscan_param.usOverscanRight = 0; - overscan_param.usOverscanLeft = 0; - overscan_param.usOverscanBottom = 0; - overscan_param.usOverscanTop = 0; - overscan_param.ucCRTC = radeon_crtc->crtc_id; - - if (radeon_output->Flags & RADEON_USE_RMX) { - if (radeon_output->rmx_type == RMX_FULL) { - overscan_param.usOverscanRight = 0; - overscan_param.usOverscanLeft = 0; - overscan_param.usOverscanBottom = 0; - overscan_param.usOverscanTop = 0; - } else if (radeon_output->rmx_type == RMX_CENTER) { - overscan_param.usOverscanTop = (adjusted_mode->CrtcVDisplay - mode->CrtcVDisplay) / 2; - overscan_param.usOverscanBottom = (adjusted_mode->CrtcVDisplay - mode->CrtcVDisplay) / 2; - overscan_param.usOverscanLeft = (adjusted_mode->CrtcHDisplay - mode->CrtcHDisplay) / 2; - overscan_param.usOverscanRight = (adjusted_mode->CrtcHDisplay - mode->CrtcHDisplay) / 2; - } else if (radeon_output->rmx_type == RMX_ASPECT) { - int a1 = mode->CrtcVDisplay * adjusted_mode->CrtcHDisplay; - int a2 = adjusted_mode->CrtcVDisplay * mode->CrtcHDisplay; - - if (a1 > a2) { - overscan_param.usOverscanLeft = (adjusted_mode->CrtcHDisplay - (a2 / mode->CrtcVDisplay)) / 2; - overscan_param.usOverscanRight = (adjusted_mode->CrtcHDisplay - (a2 / mode->CrtcVDisplay)) / 2; - } else if (a2 > a1) { - overscan_param.usOverscanLeft = (adjusted_mode->CrtcVDisplay - (a1 / mode->CrtcHDisplay)) / 2; - overscan_param.usOverscanRight = (adjusted_mode->CrtcVDisplay - (a1 / mode->CrtcHDisplay)) / 2; - } - } - } - - data.exec.index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan); - data.exec.dataSpace = (void *)&space; - data.exec.pspace = &overscan_param; - - if (RHDAtomBiosFunc(info->atomBIOS->pScrn, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { - ErrorF("Set CRTC %d Overscan success\n", radeon_crtc->crtc_id); - return ATOM_SUCCESS ; - } - - ErrorF("Set CRTC %d Overscan failed\n", radeon_crtc->crtc_id); - return ATOM_NOT_IMPLEMENTED; -} - -static int -atombios_output_scaler_setup(xf86OutputPtr output) -{ - RADEONInfoPtr info = RADEONPTR(output->scrn); - RADEONOutputPrivatePtr radeon_output = output->driver_private; - radeon_tvout_ptr tvout = &radeon_output->tvout; - RADEONCrtcPrivatePtr radeon_crtc = output->crtc->driver_private; - ENABLE_SCALER_PS_ALLOCATION disp_data; - AtomBiosArgRec data; - unsigned char *space; - - if (!IS_AVIVO_VARIANT && radeon_crtc->crtc_id) - return ATOM_SUCCESS; - - memset(&disp_data, 0, sizeof(disp_data)); - - disp_data.ucScaler = radeon_crtc->crtc_id; - - if (radeon_output->active_device & (ATOM_DEVICE_TV_SUPPORT)) { - switch (tvout->tvStd) { - case TV_STD_NTSC: - disp_data.ucTVStandard = ATOM_TV_NTSC; - break; - case TV_STD_PAL: - disp_data.ucTVStandard = ATOM_TV_PAL; - break; - case TV_STD_PAL_M: - disp_data.ucTVStandard = ATOM_TV_PALM; - break; - case TV_STD_PAL_60: - disp_data.ucTVStandard = ATOM_TV_PAL60; - break; - case TV_STD_NTSC_J: - disp_data.ucTVStandard = ATOM_TV_NTSCJ; - break; - case TV_STD_SCART_PAL: - disp_data.ucTVStandard = ATOM_TV_PAL; /* ??? */ - break; - case TV_STD_SECAM: - disp_data.ucTVStandard = ATOM_TV_SECAM; - break; - case TV_STD_PAL_CN: - disp_data.ucTVStandard = ATOM_TV_PALCN; - break; - default: - disp_data.ucTVStandard = ATOM_TV_NTSC; - break; - } - disp_data.ucEnable = SCALER_ENABLE_MULTITAP_MODE; - ErrorF("Using TV scaler %x %x\n", disp_data.ucTVStandard, disp_data.ucEnable); - } else if (radeon_output->active_device & (ATOM_DEVICE_CV_SUPPORT)) { - disp_data.ucTVStandard = ATOM_TV_CV; - disp_data.ucEnable = SCALER_ENABLE_MULTITAP_MODE; - ErrorF("Using CV scaler %x %x\n", disp_data.ucTVStandard, disp_data.ucEnable); - } else if (radeon_output->Flags & RADEON_USE_RMX) { - ErrorF("Using RMX\n"); - if (radeon_output->rmx_type == RMX_FULL) - disp_data.ucEnable = ATOM_SCALER_EXPANSION; - else if (radeon_output->rmx_type == RMX_CENTER) - disp_data.ucEnable = ATOM_SCALER_CENTER; - else if (radeon_output->rmx_type == RMX_ASPECT) - disp_data.ucEnable = ATOM_SCALER_EXPANSION; - } else { - ErrorF("Not using RMX\n"); - if (IS_AVIVO_VARIANT) - disp_data.ucEnable = ATOM_SCALER_DISABLE; - else - disp_data.ucEnable = ATOM_SCALER_CENTER; - } - - data.exec.index = GetIndexIntoMasterTable(COMMAND, EnableScaler); - data.exec.dataSpace = (void *)&space; - data.exec.pspace = &disp_data; - - if (RHDAtomBiosFunc(info->atomBIOS->pScrn, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { - if (radeon_output->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT) - && info->ChipFamily >= CHIP_FAMILY_RV515 && info->ChipFamily <= CHIP_FAMILY_RV570) { - ErrorF("forcing TV scaler\n"); - atom_rv515_force_tv_scaler(output->scrn, radeon_crtc); - } - ErrorF("scaler %d setup success\n", radeon_crtc->crtc_id); - return ATOM_SUCCESS; - } - - ErrorF("scaler %d setup failed\n", radeon_crtc->crtc_id); - return ATOM_NOT_IMPLEMENTED; - -} - -void -atombios_output_dpms(xf86OutputPtr output, int mode) -{ - RADEONOutputPrivatePtr radeon_output = output->driver_private; - radeon_encoder_ptr radeon_encoder = radeon_get_encoder(output); - RADEONInfoPtr info = RADEONPTR(output->scrn); - DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION disp_data; - AtomBiosArgRec data; - unsigned char *space; - int index = 0; - Bool is_dig = FALSE; - unsigned char *RADEONMMIO = info->MMIO; - uint32_t reg = 0; - - if (radeon_encoder == NULL) - return; - - switch (radeon_encoder->encoder_id) { - case ENCODER_OBJECT_ID_INTERNAL_TMDS1: - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: - index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl); - break; - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: - is_dig = TRUE; - break; - case ENCODER_OBJECT_ID_INTERNAL_DVO1: - case ENCODER_OBJECT_ID_INTERNAL_DDI: - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: - index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); - break; - case ENCODER_OBJECT_ID_INTERNAL_LVDS: - index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); - break; - case ENCODER_OBJECT_ID_INTERNAL_LVTM1: - if (radeon_output->active_device & (ATOM_DEVICE_LCD_SUPPORT)) - index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); - else - index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl); - break; - case ENCODER_OBJECT_ID_INTERNAL_DAC1: - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: - if (IS_DCE32_VARIANT) - index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); - else { - if (radeon_output->active_device & (ATOM_DEVICE_TV_SUPPORT)) - index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); - else if (radeon_output->active_device & (ATOM_DEVICE_CV_SUPPORT)) - index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); - else - index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); - } - break; - case ENCODER_OBJECT_ID_INTERNAL_DAC2: - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: - if (IS_DCE32_VARIANT) - index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); - else { - if (radeon_output->active_device & (ATOM_DEVICE_TV_SUPPORT)) - index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); - else if (radeon_output->active_device & (ATOM_DEVICE_CV_SUPPORT)) - index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); - else - index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); - } - break; - } - - switch (mode) { - case DPMSModeOn: - radeon_encoder->devices |= radeon_output->active_device; - if (is_dig) { - atombios_output_dig_transmitter_setup(output, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); - if (((radeon_output->ConnectorType == CONNECTOR_DISPLAY_PORT) || - (radeon_output->ConnectorType == CONNECTOR_EDP)) && - (radeon_output->MonType == MT_DP)) { - do_displayport_link_train(output); - if (IS_DCE4_VARIANT) - atombios_output_dig_encoder_setup(output, ATOM_ENCODER_CMD_DP_VIDEO_ON); - } - } - else { - disp_data.ucAction = ATOM_ENABLE; - data.exec.index = index; - data.exec.dataSpace = (void *)&space; - data.exec.pspace = &disp_data; - - /* workaround for DVOOutputControl on some RS690 systems */ - if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) { - reg = INREG(RADEON_BIOS_3_SCRATCH); - OUTREG(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE); - } - if (RHDAtomBiosFunc(info->atomBIOS->pScrn, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) - ErrorF("Output %s enable success\n", - device_name[radeon_get_device_index(radeon_output->active_device)]); - else - ErrorF("Output %s enable failed\n", - device_name[radeon_get_device_index(radeon_output->active_device)]); - if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) - OUTREG(RADEON_BIOS_3_SCRATCH, reg); - } - /* at least for TV atom fails to reassociate the correct crtc source at dpms on */ - if (radeon_output->active_device & (ATOM_DEVICE_TV_SUPPORT)) - atombios_set_output_crtc_source(output); - break; - case DPMSModeStandby: - case DPMSModeSuspend: - case DPMSModeOff: - radeon_encoder->devices &= ~(radeon_output->active_device); - if (!radeon_encoder->devices) { - if (is_dig) { - atombios_output_dig_transmitter_setup(output, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0); - if (((radeon_output->ConnectorType == CONNECTOR_DISPLAY_PORT) || - (radeon_output->ConnectorType == CONNECTOR_EDP)) && - (radeon_output->MonType == MT_DP)) { - if (IS_DCE4_VARIANT) - atombios_output_dig_encoder_setup(output, ATOM_ENCODER_CMD_DP_VIDEO_OFF); - } - } else { - disp_data.ucAction = ATOM_DISABLE; - data.exec.index = index; - data.exec.dataSpace = (void *)&space; - data.exec.pspace = &disp_data; - - if (RHDAtomBiosFunc(info->atomBIOS->pScrn, info->atomBIOS, ATOMBIOS_EXEC, &data) - == ATOM_SUCCESS) - ErrorF("Output %s disable success\n", - device_name[radeon_get_device_index(radeon_output->active_device)]); - else - ErrorF("Output %s disable failed\n", - device_name[radeon_get_device_index(radeon_output->active_device)]); - } - } - break; - } -} - -union crtc_source_param { - SELECT_CRTC_SOURCE_PS_ALLOCATION v1; - SELECT_CRTC_SOURCE_PARAMETERS_V2 v2; -}; - -void -atombios_set_output_crtc_source(xf86OutputPtr output) -{ - RADEONOutputPrivatePtr radeon_output = output->driver_private; - RADEONCrtcPrivatePtr radeon_crtc = output->crtc->driver_private; - RADEONInfoPtr info = RADEONPTR(output->scrn); - radeon_encoder_ptr radeon_encoder = radeon_get_encoder(output); - AtomBiosArgRec data; - unsigned char *space; - union crtc_source_param args; - int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); - int major, minor; - - if (radeon_encoder == NULL) - return; - - memset(&args, 0, sizeof(args)); - - atombios_get_command_table_version(info->atomBIOS, index, &major, &minor); - - /*ErrorF("select crtc source table is %d %d\n", major, minor);*/ - - switch(major) { - case 1: - switch(minor) { - case 0: - case 1: - default: - if (IS_AVIVO_VARIANT) - args.v1.ucCRTC = radeon_crtc->crtc_id; - else { - if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) - args.v1.ucCRTC = radeon_crtc->crtc_id; - else - args.v1.ucCRTC = radeon_crtc->crtc_id << 2; - } - switch (radeon_encoder->encoder_id) { - case ENCODER_OBJECT_ID_INTERNAL_TMDS1: - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: - args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX; - break; - case ENCODER_OBJECT_ID_INTERNAL_LVDS: - case ENCODER_OBJECT_ID_INTERNAL_LVTM1: - if (radeon_output->active_device & ATOM_DEVICE_LCD1_SUPPORT) - args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX; - else - args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX; - break; - case ENCODER_OBJECT_ID_INTERNAL_DVO1: - case ENCODER_OBJECT_ID_INTERNAL_DDI: - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: - args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX; - break; - case ENCODER_OBJECT_ID_INTERNAL_DAC1: - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: - if (radeon_output->active_device & (ATOM_DEVICE_TV_SUPPORT)) - args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; - else if (radeon_output->active_device & (ATOM_DEVICE_CV_SUPPORT)) - args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; - else - args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX; - break; - case ENCODER_OBJECT_ID_INTERNAL_DAC2: - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: - if (radeon_output->active_device & (ATOM_DEVICE_TV_SUPPORT)) - args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; - else if (radeon_output->active_device & (ATOM_DEVICE_CV_SUPPORT)) - args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; - else - args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX; - break; - } - /*ErrorF("device sourced: 0x%x\n", args.v1.ucDevice);*/ - break; - case 2: - args.v2.ucCRTC = radeon_crtc->crtc_id; - args.v2.ucEncodeMode = atombios_get_encoder_mode(output); - switch (radeon_encoder->encoder_id) { - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: - switch (radeon_output->dig_encoder) { - case 0: - args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; - break; - case 1: - args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; - break; - case 2: - args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID; - break; - case 3: - args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID; - break; - case 4: - args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID; - break; - case 5: - args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; - break; - } - break; - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: - args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; - break; - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: - if (radeon_output->active_device & (ATOM_DEVICE_TV_SUPPORT)) - args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; - else if (radeon_output->active_device & (ATOM_DEVICE_CV_SUPPORT)) - args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; - else - args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; - break; - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: - if (radeon_output->active_device & (ATOM_DEVICE_TV_SUPPORT)) - args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; - else if (radeon_output->active_device & (ATOM_DEVICE_CV_SUPPORT)) - args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; - else - args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; - break; - } - /*ErrorF("device sourced: 0x%x\n", args.v2.ucEncoderID);*/ - break; - } - break; - default: - ErrorF("Unknown table version\n"); - exit(-1); - } - - data.exec.pspace = &args; - data.exec.index = index; - data.exec.dataSpace = (void *)&space; - - if (RHDAtomBiosFunc(info->atomBIOS->pScrn, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { - ErrorF("Set CRTC %d Source success\n", radeon_crtc->crtc_id); - return; - } - - ErrorF("Set CRTC Source failed\n"); - return; -} - -static void -atombios_apply_output_quirks(xf86OutputPtr output, DisplayModePtr mode) -{ - RADEONOutputPrivatePtr radeon_output = output->driver_private; - RADEONCrtcPrivatePtr radeon_crtc = output->crtc->driver_private; - RADEONInfoPtr info = RADEONPTR(output->scrn); - unsigned char *RADEONMMIO = info->MMIO; - - /* Funky macbooks */ - if ((info->Chipset == PCI_CHIP_RV530_71C5) && - (PCI_SUB_VENDOR_ID(info->PciInfo) == 0x106b) && - (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x0080)) { - if (radeon_output->MonType == MT_LCD) { - if (radeon_output->devices & ATOM_DEVICE_LCD1_SUPPORT) { - uint32_t lvtma_bit_depth_control = INREG(AVIVO_LVTMA_BIT_DEPTH_CONTROL); - - lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN; - lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; - - OUTREG(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control); - } - } - } - - /* set scaler clears this on some chips */ - if (!(radeon_output->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))) { - if (IS_AVIVO_VARIANT && (mode->Flags & V_INTERLACE)) - OUTREG(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, AVIVO_D1MODE_INTERLEAVE_EN); - } - - if (IS_DCE32_VARIANT && - (!IS_DCE4_VARIANT) && - (radeon_output->active_device & (ATOM_DEVICE_DFP_SUPPORT))) { - radeon_encoder_ptr radeon_encoder = radeon_get_encoder(output); - if (radeon_encoder == NULL) - return; - /* XXX: need to sort out why transmitter control table sometimes sets this to a - * different golden value. - */ - if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY2) { - OUTREG(0x7ec4, 0x00824002); - } - } -} - -void -atombios_pick_dig_encoder(xf86OutputPtr output) -{ - xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(output->scrn); - RADEONOutputPrivatePtr radeon_output = output->driver_private; - RADEONInfoPtr info = RADEONPTR(output->scrn); - radeon_encoder_ptr radeon_encoder = NULL; - Bool is_lvtma = FALSE; - int i, mode; - uint32_t dig_enc_use_mask = 0; - - /* non digital encoders don't need a dig block */ - mode = atombios_get_encoder_mode(output); - if (mode == ATOM_ENCODER_MODE_CRT || - mode == ATOM_ENCODER_MODE_TV || - mode == ATOM_ENCODER_MODE_CV) - return; - - if (IS_DCE4_VARIANT) { - radeon_encoder = radeon_get_encoder(output); - - if (IS_DCE41_VARIANT) { - if (radeon_output->linkb) - radeon_output->dig_encoder = 1; - else - radeon_output->dig_encoder = 0; - } else { - switch (radeon_encoder->encoder_id) { - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: - if (radeon_output->linkb) - radeon_output->dig_encoder = 1; - else - radeon_output->dig_encoder = 0; - break; - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: - if (radeon_output->linkb) - radeon_output->dig_encoder = 3; - else - radeon_output->dig_encoder = 2; - break; - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: - if (radeon_output->linkb) - radeon_output->dig_encoder = 5; - else - radeon_output->dig_encoder = 4; - break; - default: - ErrorF("Unknown encoder\n"); - break; - } - } - return; - } - - if (IS_DCE32_VARIANT) { - RADEONCrtcPrivatePtr radeon_crtc = output->crtc->driver_private; - radeon_output->dig_encoder = radeon_crtc->crtc_id; - return; - } - - for (i = 0; i < xf86_config->num_output; i++) { - xf86OutputPtr test = xf86_config->output[i]; - RADEONOutputPrivatePtr radeon_test = test->driver_private; - radeon_encoder = radeon_get_encoder(test); - - if (!radeon_encoder || !test->crtc) - continue; - - if (output == test && radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) - is_lvtma = TRUE; - if (output != test && (radeon_test->dig_encoder >= 0)) - dig_enc_use_mask |= (1 << radeon_test->dig_encoder); - - } - if (is_lvtma) { - if (dig_enc_use_mask & 0x2) - ErrorF("Need digital encoder 2 for LVTMA and it isn't free - stealing\n"); - radeon_output->dig_encoder = 1; - return; - } - if (!(dig_enc_use_mask & 1)) - radeon_output->dig_encoder = 0; - else - radeon_output->dig_encoder = 1; -} -void -atombios_output_mode_set(xf86OutputPtr output, - DisplayModePtr mode, - DisplayModePtr adjusted_mode) -{ - RADEONOutputPrivatePtr radeon_output = output->driver_private; - radeon_encoder_ptr radeon_encoder = radeon_get_encoder(output); - RADEONInfoPtr info = RADEONPTR(output->scrn); - if (radeon_encoder == NULL) - return; - - radeon_output->pixel_clock = adjusted_mode->Clock; - atombios_output_overscan_setup(output, mode, adjusted_mode); - atombios_output_scaler_setup(output); - atombios_set_output_crtc_source(output); - - if (IS_AVIVO_VARIANT && !IS_DCE4_VARIANT) { - if (radeon_output->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) - atombios_output_yuv_setup(output, TRUE); - else - atombios_output_yuv_setup(output, FALSE); - } - - switch (radeon_encoder->encoder_id) { - case ENCODER_OBJECT_ID_INTERNAL_TMDS1: - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: - case ENCODER_OBJECT_ID_INTERNAL_LVDS: - case ENCODER_OBJECT_ID_INTERNAL_LVTM1: - atombios_output_digital_setup(output, PANEL_ENCODER_ACTION_ENABLE); - break; - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: - /* disable encoder and transmitter */ - /* setup and enable the encoder and transmitter */ - if (IS_DCE4_VARIANT) { - atombios_output_dig_transmitter_setup(output, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); - atombios_output_dig_encoder_setup(output, ATOM_ENCODER_CMD_SETUP); - atombios_output_dig_transmitter_setup(output, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); - atombios_output_dig_transmitter_setup(output, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); - } else { - atombios_output_dig_transmitter_setup(output, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); - atombios_output_dig_encoder_setup(output, ATOM_DISABLE); - atombios_output_dig_encoder_setup(output, ATOM_ENABLE); - - atombios_output_dig_transmitter_setup(output, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); - atombios_output_dig_transmitter_setup(output, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); - atombios_output_dig_transmitter_setup(output, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); - } - break; - case ENCODER_OBJECT_ID_INTERNAL_DDI: - atombios_output_ddia_setup(output, ATOM_ENABLE); - break; - case ENCODER_OBJECT_ID_INTERNAL_DVO1: - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: - atombios_external_tmds_setup(output, ATOM_ENABLE); - break; - case ENCODER_OBJECT_ID_INTERNAL_DAC1: - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: - case ENCODER_OBJECT_ID_INTERNAL_DAC2: - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: - atombios_output_dac_setup(output, ATOM_ENABLE); - if (radeon_output->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) { - if (radeon_output->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) - atombios_output_tv_setup(output, ATOM_ENABLE); - else - atombios_output_tv_setup(output, ATOM_DISABLE); - } - break; - } - atombios_apply_output_quirks(output, adjusted_mode); -} - -static AtomBiosResult -atom_bios_dac_load_detect(atomBiosHandlePtr atomBIOS, xf86OutputPtr output) -{ - RADEONOutputPrivatePtr radeon_output = output->driver_private; - RADEONInfoPtr info = RADEONPTR(output->scrn); - DAC_LOAD_DETECTION_PS_ALLOCATION dac_data; - AtomBiosArgRec data; - unsigned char *space; - int major, minor; - int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection); - - atombios_get_command_table_version(info->atomBIOS, index, &major, &minor); - - dac_data.sDacload.ucMisc = 0; - - if (radeon_output->devices & ATOM_DEVICE_CRT1_SUPPORT) { - dac_data.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT); - if (info->encoders[ATOM_DEVICE_CRT1_INDEX] && - ((info->encoders[ATOM_DEVICE_CRT1_INDEX]->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) || - (info->encoders[ATOM_DEVICE_CRT1_INDEX]->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))) - dac_data.sDacload.ucDacType = ATOM_DAC_A; - else - dac_data.sDacload.ucDacType = ATOM_DAC_B; - } else if (radeon_output->devices & ATOM_DEVICE_CRT2_SUPPORT) { - dac_data.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT); - if (info->encoders[ATOM_DEVICE_CRT2_INDEX] && - ((info->encoders[ATOM_DEVICE_CRT2_INDEX]->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) || - (info->encoders[ATOM_DEVICE_CRT2_INDEX]->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))) - dac_data.sDacload.ucDacType = ATOM_DAC_A; - else - dac_data.sDacload.ucDacType = ATOM_DAC_B; - } else if (radeon_output->devices & ATOM_DEVICE_CV_SUPPORT) { - dac_data.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT); - if (info->encoders[ATOM_DEVICE_CV_INDEX] && - ((info->encoders[ATOM_DEVICE_CV_INDEX]->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) || - (info->encoders[ATOM_DEVICE_CV_INDEX]->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))) - dac_data.sDacload.ucDacType = ATOM_DAC_A; - else - dac_data.sDacload.ucDacType = ATOM_DAC_B; - if (minor >= 3) - dac_data.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; - } else if (radeon_output->devices & ATOM_DEVICE_TV1_SUPPORT) { - dac_data.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT); - if (info->encoders[ATOM_DEVICE_TV1_INDEX] && - ((info->encoders[ATOM_DEVICE_TV1_INDEX]->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) || - (info->encoders[ATOM_DEVICE_TV1_INDEX]->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))) - dac_data.sDacload.ucDacType = ATOM_DAC_A; - else - dac_data.sDacload.ucDacType = ATOM_DAC_B; - if (minor >= 3) - dac_data.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; - } else - return ATOM_NOT_IMPLEMENTED; - - data.exec.index = index; - data.exec.dataSpace = (void *)&space; - data.exec.pspace = &dac_data; - - if (RHDAtomBiosFunc(atomBIOS->pScrn, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { - ErrorF("Dac detection success\n"); - return ATOM_SUCCESS ; - } - - ErrorF("DAC detection failed\n"); - return ATOM_NOT_IMPLEMENTED; -} - -RADEONMonitorType -atombios_dac_detect(xf86OutputPtr output) -{ - ScrnInfoPtr pScrn = output->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - RADEONOutputPrivatePtr radeon_output = output->driver_private; - RADEONMonitorType MonType = MT_NONE; - AtomBiosResult ret; - RADEONSavePtr save = info->ModeReg; - - if (radeon_output->devices & ATOM_DEVICE_TV1_SUPPORT) { - if (xf86ReturnOptValBool(info->Options, OPTION_FORCE_TVOUT, FALSE)) { - if (radeon_output->ConnectorType == CONNECTOR_STV) - return MT_STV; - else - return MT_CTV; - } - } - - ret = atom_bios_dac_load_detect(info->atomBIOS, output); - if (ret == ATOM_SUCCESS) { - if (info->ChipFamily >= CHIP_FAMILY_R600) - save->bios_0_scratch = INREG(R600_BIOS_0_SCRATCH); - else - save->bios_0_scratch = INREG(RADEON_BIOS_0_SCRATCH); - /*ErrorF("DAC connect %08X\n", (unsigned int)save->bios_0_scratch);*/ - - if (radeon_output->devices & ATOM_DEVICE_CRT1_SUPPORT) { - if (save->bios_0_scratch & ATOM_S0_CRT1_MASK) - MonType = MT_CRT; - } else if (radeon_output->devices & ATOM_DEVICE_CRT2_SUPPORT) { - if (save->bios_0_scratch & ATOM_S0_CRT2_MASK) - MonType = MT_CRT; - } else if (radeon_output->devices & ATOM_DEVICE_CV_SUPPORT) { - if (save->bios_0_scratch & (ATOM_S0_CV_MASK | ATOM_S0_CV_MASK_A)) - MonType = MT_CV; - } else if (radeon_output->devices & ATOM_DEVICE_TV1_SUPPORT) { - if (save->bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) - MonType = MT_CTV; - else if (save->bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) - MonType = MT_STV; - } - } - - return MonType; -} - - -static inline int atom_dp_get_encoder_id(xf86OutputPtr output) -{ - RADEONOutputPrivatePtr radeon_output = output->driver_private; - int ret = 0; - if (radeon_output->dig_encoder) - ret |= ATOM_DP_CONFIG_DIG2_ENCODER; - else - ret |= ATOM_DP_CONFIG_DIG1_ENCODER; - if (radeon_output->linkb) - ret |= ATOM_DP_CONFIG_LINK_B; - else - ret |= ATOM_DP_CONFIG_LINK_A; - return ret; -} - -union aux_channel_transaction { - PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1; - PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2; -}; - -Bool -RADEONProcessAuxCH(xf86OutputPtr output, uint8_t *req_bytes, uint8_t num_bytes, - uint8_t *read_byte, uint8_t read_buf_len, uint8_t delay) -{ - RADEONOutputPrivatePtr radeon_output = output->driver_private; - RADEONInfoPtr info = RADEONPTR(output->scrn); - union aux_channel_transaction args; - AtomBiosArgRec data; - unsigned char *space; - unsigned char *base; - int retry_count = 0; - - memset(&args, 0, sizeof(args)); - if (info->atomBIOS->fbBase) - base = info->FB + info->atomBIOS->fbBase; - else if (info->atomBIOS->scratchBase) - base = (unsigned char *)info->atomBIOS->scratchBase; - else - return FALSE; - -retry: - memcpy(base, req_bytes, num_bytes); - - args.v1.lpAuxRequest = 0; - args.v1.lpDataOut = 16; - args.v1.ucDataOutLen = 0; - args.v1.ucChannelID = radeon_output->ucI2cId; - args.v1.ucDelay = delay / 10; /* 10 usec */ - if (IS_DCE4_VARIANT) - args.v2.ucHPD_ID = radeon_output->hpd_id; - - data.exec.index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction); - data.exec.dataSpace = (void *)&space; - data.exec.pspace = &args; - - RHDAtomBiosFunc(info->atomBIOS->pScrn, info->atomBIOS, ATOMBIOS_EXEC, &data); - if (args.v1.ucReplyStatus && !args.v1.ucDataOutLen) { - if (args.v1.ucReplyStatus == 0x20 && retry_count++ < 10) - goto retry; - ErrorF("failed to get auxch %02x%02x %02x %02x %02x after %d retries\n", - req_bytes[1], req_bytes[0], req_bytes[2], req_bytes[3], args.v1.ucReplyStatus, retry_count); - return FALSE; - } - if (args.v1.ucDataOutLen && read_byte && read_buf_len) { - if (read_buf_len < args.v1.ucDataOutLen) { - ErrorF("%s: Buffer too small for return answer %d %d\n", __func__, read_buf_len, args.v1.ucDataOutLen); - return FALSE; - } - { - int len = read_buf_len < args.v1.ucDataOutLen ? read_buf_len : args.v1.ucDataOutLen; - memcpy(read_byte, base+16, len); - } - } - return TRUE; -} - -static int -RADEONDPEncoderService(xf86OutputPtr output, int action, uint8_t ucconfig, uint8_t lane_num) -{ - RADEONInfoPtr info = RADEONPTR(output->scrn); - DP_ENCODER_SERVICE_PARAMETERS args; - AtomBiosArgRec data; - unsigned char *space; - - memset(&args, 0, sizeof(args)); - - args.ucLinkClock = 0; - args.ucConfig = ucconfig; - args.ucAction = action; - args.ucLaneNum = lane_num; - args.ucStatus = 0; - - data.exec.index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); - data.exec.dataSpace = (void *)&space; - data.exec.pspace = &args; - - RHDAtomBiosFunc(info->atomBIOS->pScrn, info->atomBIOS, ATOMBIOS_EXEC, &data); - - ErrorF("%s: %d %d\n", __func__, action, args.ucStatus); - return args.ucStatus; -} - -int RADEON_DP_GetSinkType(xf86OutputPtr output) -{ - RADEONOutputPrivatePtr radeon_output = output->driver_private; - - return RADEONDPEncoderService(output, ATOM_DP_ACTION_GET_SINK_TYPE, radeon_output->ucI2cId, 0); -} - -static Bool atom_dp_aux_native_write(xf86OutputPtr output, uint16_t address, - uint8_t send_bytes, uint8_t *send) -{ - uint8_t msg[20]; - uint8_t msg_len, dp_msg_len; - int ret; - - dp_msg_len = 4; - msg[0] = address; - msg[1] = address >> 8; - msg[2] = AUX_NATIVE_WRITE << 4; - dp_msg_len += send_bytes; - msg[3] = (dp_msg_len << 4)| (send_bytes - 1); - - if (0) - ErrorF("writing %02x %02x %02x, %d, %d\n", msg[0], msg[1], msg[3], send_bytes, dp_msg_len); - if (send_bytes > 16) - return FALSE; - - memcpy(&msg[4], send, send_bytes); - msg_len = 4 + send_bytes; - ret = RADEONProcessAuxCH(output, msg, msg_len, NULL, 0, 0); - return ret; -} - -static Bool atom_dp_aux_native_read(xf86OutputPtr output, uint16_t address, - uint8_t delay, - uint8_t expected_bytes, uint8_t *read_p) -{ - uint8_t msg[20]; - uint8_t msg_len, dp_msg_len; - int ret; - - msg_len = 4; - dp_msg_len = 4; - msg[0] = address; - msg[1] = address >> 8; - msg[2] = AUX_NATIVE_READ << 4; - msg[3] = (dp_msg_len) << 4; - msg[3] |= expected_bytes - 1; - - if (0) - ErrorF("reading %02x %02x %02x, %d, %d\n", msg[0], msg[1], msg[3], expected_bytes, dp_msg_len); - ret = RADEONProcessAuxCH(output, msg, msg_len, read_p, expected_bytes, delay); - return ret; -} - -/* fill out the DPCD structure */ -void RADEON_DP_GetDPCD(xf86OutputPtr output) -{ - RADEONOutputPrivatePtr radeon_output = output->driver_private; - uint8_t msg[25]; - int ret; - - ret = atom_dp_aux_native_read(output, DP_DPCD_REV, 0, 8, msg); - if (ret) { - memcpy(radeon_output->dpcd, msg, 8); - if (0) { - int i; - ErrorF("DPCD: "); - for (i = 0; i < 8; i++) - ErrorF("%02x ", radeon_output->dpcd[i]); - ErrorF("\n"); - } - ret = atom_dp_aux_native_read(output, DP_LINK_BW_SET, 0, 2, msg); - if (0) { - ErrorF("0x200: %02x %02x\n", msg[0], msg[1]); - } - return; - } - radeon_output->dpcd[0] = 0; - return; -} - - -enum dp_aux_i2c_mode { - dp_aux_i2c_start, - dp_aux_i2c_write, - dp_aux_i2c_read, - dp_aux_i2c_stop, -}; - - -static Bool atom_dp_aux_i2c_transaction(xf86OutputPtr output, uint16_t address, - enum dp_aux_i2c_mode mode, - uint8_t write_byte, uint8_t *read_byte) -{ - uint8_t msg[8], msg_len, dp_msg_len; - int ret; - int auxch_cmd = 0; - - memset(msg, 0, 8); - - if (mode != dp_aux_i2c_stop) - auxch_cmd = AUX_I2C_MOT; - - if (address & 1) - auxch_cmd |= AUX_I2C_READ; - else - auxch_cmd |= AUX_I2C_WRITE; - - msg[2] = auxch_cmd << 4; - - msg[4] = 0; - msg[0] = (address >> 1); - msg[1] = (address >> 9); - - msg_len = 4; - dp_msg_len = 3; - switch (mode) { - case dp_aux_i2c_read: - /* bottom bits is byte count - 1 so for 1 byte == 0 */ - dp_msg_len += 1; - break; - case dp_aux_i2c_write: - dp_msg_len += 2; - msg[4] = write_byte; - msg_len++; - break; - default: - break; - } - msg[3] = dp_msg_len << 4; - - ret = RADEONProcessAuxCH(output, msg, msg_len, read_byte, 1, 0); - return ret; -} - -static Bool -atom_dp_i2c_address(I2CDevPtr dev, I2CSlaveAddr addr) -{ - I2CBusPtr bus = dev->pI2CBus; - xf86OutputPtr output = bus->DriverPrivate.ptr; - RADEONOutputPrivatePtr radeon_output = output->driver_private; - int ret; - - radeon_output->dp_i2c_addr = addr; - radeon_output->dp_i2c_running = TRUE; - - /* call i2c start */ - ret = atom_dp_aux_i2c_transaction(output, radeon_output->dp_i2c_addr, - dp_aux_i2c_start, 0, NULL); - - return ret; -} -static Bool -atom_dp_i2c_start(I2CBusPtr bus, int timeout) -{ - ErrorF("%s\n", __func__); - return TRUE; -} - -static void -atom_dp_i2c_stop(I2CDevPtr dev) -{ - I2CBusPtr bus = dev->pI2CBus; - xf86OutputPtr output = bus->DriverPrivate.ptr; - RADEONOutputPrivatePtr radeon_output = output->driver_private; - - if (radeon_output->dp_i2c_running) - atom_dp_aux_i2c_transaction(output, radeon_output->dp_i2c_addr, - dp_aux_i2c_stop, 0, NULL); - radeon_output->dp_i2c_running = FALSE; -} - - -static Bool -atom_dp_i2c_put_byte(I2CDevPtr dev, I2CByte byte) -{ - I2CBusPtr bus = dev->pI2CBus; - xf86OutputPtr output = bus->DriverPrivate.ptr; - RADEONOutputPrivatePtr radeon_output = output->driver_private; - Bool ret; - - ret = (atom_dp_aux_i2c_transaction(output, radeon_output->dp_i2c_addr, - dp_aux_i2c_write, byte, NULL)); - return ret; -} - -static Bool -atom_dp_i2c_get_byte(I2CDevPtr dev, I2CByte *byte_ret, Bool last) -{ - I2CBusPtr bus = dev->pI2CBus; - xf86OutputPtr output = bus->DriverPrivate.ptr; - RADEONOutputPrivatePtr radeon_output = output->driver_private; - Bool ret; - - ret = (atom_dp_aux_i2c_transaction(output, radeon_output->dp_i2c_addr, - dp_aux_i2c_read, 0, byte_ret)); - return ret; -} - -Bool -RADEON_DP_I2CInit(ScrnInfoPtr pScrn, I2CBusPtr *bus_ptr, char *name, xf86OutputPtr output) -{ - I2CBusPtr pI2CBus; - - pI2CBus = xf86CreateI2CBusRec(); - if (!pI2CBus) return FALSE; - - pI2CBus->BusName = name; - pI2CBus->scrnIndex = pScrn->scrnIndex; - pI2CBus->I2CGetByte = atom_dp_i2c_get_byte; - pI2CBus->I2CPutByte = atom_dp_i2c_put_byte; - pI2CBus->I2CAddress = atom_dp_i2c_address; - pI2CBus->I2CStart = atom_dp_i2c_start; - pI2CBus->I2CStop = atom_dp_i2c_stop; - pI2CBus->DriverPrivate.ptr = output; - - /* - * These were set incorrectly in the server pre-1.3, Having - * duplicate settings is sub-optimal, but this lets the driver - * work with older servers - */ - pI2CBus->ByteTimeout = 2200; /* VESA DDC spec 3 p. 43 (+10 %) */ - pI2CBus->StartTimeout = 550; - pI2CBus->BitTimeout = 40; - pI2CBus->AcknTimeout = 40; - pI2CBus->RiseFallTime = 20; - - if (!xf86I2CBusInit(pI2CBus)) - return FALSE; - - *bus_ptr = pI2CBus; - return TRUE; -} - - -static uint8_t dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE], int r) -{ - return link_status[r - DP_LANE0_1_STATUS]; -} - -static uint8_t dp_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane) -{ - int i = DP_LANE0_1_STATUS + (lane >> 1); - int s = (lane & 1) * 4; - uint8_t l = dp_link_status(link_status, i); - return (l >> s) & 0xf; -} - -static Bool dp_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count) -{ - int lane; - - uint8_t lane_status; - - for (lane = 0; lane < lane_count; lane++) { - lane_status = dp_get_lane_status(link_status, lane); - if ((lane_status & DP_LANE_CR_DONE) == 0) - return FALSE; - } - return TRUE; -} - - -/* Check to see if channel eq is done on all channels */ -#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\ - DP_LANE_CHANNEL_EQ_DONE|\ - DP_LANE_SYMBOL_LOCKED) -static Bool -dp_channel_eq_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count) -{ - uint8_t lane_align; - uint8_t lane_status; - int lane; - - lane_align = dp_link_status(link_status, - DP_LANE_ALIGN_STATUS_UPDATED); - if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) - return FALSE; - for (lane = 0; lane < lane_count; lane++) { - lane_status = dp_get_lane_status(link_status, lane); - if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS) - return FALSE; - } - return TRUE; -} - -/* - * Fetch AUX CH registers 0x202 - 0x207 which contain - * link status information - */ -static Bool -atom_dp_get_link_status(xf86OutputPtr output, - uint8_t link_status[DP_LINK_STATUS_SIZE]) -{ - ScrnInfoPtr pScrn = output->scrn; - int ret; - ret = atom_dp_aux_native_read(output, DP_LANE0_1_STATUS, 100, - DP_LINK_STATUS_SIZE, link_status); - if (!ret) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "dp link status failed\n"); - return FALSE; - } - ErrorF("link status %02x %02x %02x %02x %02x %02x\n", link_status[0], link_status[1], - link_status[2], link_status[3], link_status[4], link_status[5]); - - return TRUE; -} - -static uint8_t -dp_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE], - int lane) - -{ - int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); - int s = ((lane & 1) ? - DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : - DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); - uint8_t l = dp_link_status(link_status, i); - - return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; -} - -static uint8_t -dp_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE], - int lane) -{ - int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); - int s = ((lane & 1) ? - DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : - DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); - uint8_t l = dp_link_status(link_status, i); - - return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; -} - -static char *voltage_names[] = { - "0.4V", "0.6V", "0.8V", "1.2V" -}; -static char *pre_emph_names[] = { - "0dB", "3.5dB", "6dB", "9.5dB" -}; - -/* - * These are source-specific values; current Intel hardware supports - * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB - */ -#define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200 - -static uint8_t -dp_pre_emphasis_max(uint8_t voltage_swing) -{ - switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { - case DP_TRAIN_VOLTAGE_SWING_400: - return DP_TRAIN_PRE_EMPHASIS_6; - case DP_TRAIN_VOLTAGE_SWING_600: - return DP_TRAIN_PRE_EMPHASIS_6; - case DP_TRAIN_VOLTAGE_SWING_800: - return DP_TRAIN_PRE_EMPHASIS_3_5; - case DP_TRAIN_VOLTAGE_SWING_1200: - default: - return DP_TRAIN_PRE_EMPHASIS_0; - } -} - -static void dp_set_training(xf86OutputPtr output, uint8_t training) -{ - atom_dp_aux_native_write(output, DP_TRAINING_PATTERN_SET, 1, &training); -} - -static void dp_set_power(xf86OutputPtr output, uint8_t power_state) -{ - RADEONOutputPrivatePtr radeon_output = output->driver_private; - - if (radeon_output->dpcd[0] >= 0x11) { - atom_dp_aux_native_write(output, 0x600, 1, &power_state); - } -} - -static void -dp_get_adjust_train(xf86OutputPtr output, - uint8_t link_status[DP_LINK_STATUS_SIZE], - int lane_count, - uint8_t train_set[4]) -{ - ScrnInfoPtr pScrn = output->scrn; - uint8_t v = 0; - uint8_t p = 0; - int lane; - - for (lane = 0; lane < lane_count; lane++) { - uint8_t this_v = dp_get_adjust_request_voltage(link_status, lane); - uint8_t this_p = dp_get_adjust_request_pre_emphasis(link_status, lane); - - if (0) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "requested signal parameters: lane %d voltage %s pre_emph %s\n", - lane, - voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT], - pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); - } - if (this_v > v) - v = this_v; - if (this_p > p) - p = this_p; - } - - if (v >= DP_VOLTAGE_MAX) - v = DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED; - - if (p >= dp_pre_emphasis_max(v)) - p = dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; - - if (0) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "using signal parameters: voltage %s pre_emph %s\n", - voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT], - pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); - } - for (lane = 0; lane < 4; lane++) - train_set[lane] = v | p; -} - -static int radeon_dp_max_lane_count(xf86OutputPtr output) -{ - RADEONOutputPrivatePtr radeon_output = output->driver_private; - int max_lane_count = 4; - - if (radeon_output->dpcd[0] >= 0x11) { - max_lane_count = radeon_output->dpcd[2] & 0x1f; - switch(max_lane_count) { - case 1: case 2: case 4: - break; - default: - max_lane_count = 4; - } - } - return max_lane_count; -} - -Bool radeon_dp_mode_fixup(xf86OutputPtr output, DisplayModePtr mode, DisplayModePtr adjusted_mode) -{ - RADEONOutputPrivatePtr radeon_output = output->driver_private; - int clock = adjusted_mode->Clock; - - radeon_output->dp_lane_count = dp_lanes_for_mode_clock(output, clock); - radeon_output->dp_clock = dp_link_clock_for_mode_clock(output, clock); - if (!radeon_output->dp_lane_count || !radeon_output->dp_clock) - return FALSE; - return TRUE; -} - -static void dp_update_dpvs_emph(xf86OutputPtr output, uint8_t train_set[4]) -{ - RADEONOutputPrivatePtr radeon_output = output->driver_private; - int i; - for (i = 0; i < radeon_output->dp_lane_count; i++) - atombios_output_dig_transmitter_setup(output, ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH, i, train_set[i]); - - atom_dp_aux_native_write(output, DP_TRAINING_LANE0_SET, radeon_output->dp_lane_count, train_set); -} - -static void do_displayport_link_train(xf86OutputPtr output) -{ - ScrnInfoPtr pScrn = output->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONOutputPrivatePtr radeon_output = output->driver_private; - int enc_id = atom_dp_get_encoder_id(output); - Bool clock_recovery; - uint8_t link_status[DP_LINK_STATUS_SIZE]; - uint8_t tries, voltage, ss_cntl; - uint8_t train_set[4]; - int i; - Bool channel_eq; - uint8_t dp_link_configuration[DP_LINK_CONFIGURATION_SIZE]; - - memset(train_set, 0, 4); - - /* set up link configuration */ - memset(dp_link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); - - if (radeon_output->dp_clock == 27000) - dp_link_configuration[0] = DP_LINK_BW_2_7; - else - dp_link_configuration[0] = DP_LINK_BW_1_62; - dp_link_configuration[1] = radeon_output->dp_lane_count; - - if (radeon_output->dpcd[0] >= 0x11) { - dp_link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; - } - - /* power up to D0 */ - dp_set_power(output, DP_SET_POWER_D0); - - /* disable training */ - dp_set_training(output, DP_TRAINING_PATTERN_DISABLE); - - /* write link rate / num / eh framing */ - atom_dp_aux_native_write(output, DP_LINK_BW_SET, 2, - dp_link_configuration); - - /* write ss cntl */ - ss_cntl = 0; - atom_dp_aux_native_write(output, DP_DOWNSPREAD_CTRL, 1, - &ss_cntl); - - /* start local training start */ - if (IS_DCE4_VARIANT) { - atombios_output_dig_encoder_setup(output, ATOM_ENCODER_CMD_DP_LINK_TRAINING_START); - atombios_output_dig_encoder_setup(output, ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1); - } else { - RADEONDPEncoderService(output, ATOM_DP_ACTION_TRAINING_START, enc_id, 0); - RADEONDPEncoderService(output, ATOM_DP_ACTION_TRAINING_PATTERN_SEL, enc_id, 0); - } - - usleep(400); - dp_set_training(output, DP_TRAINING_PATTERN_1); - dp_update_dpvs_emph(output, train_set); - - /* loop around doing configuration reads and DP encoder setups */ - clock_recovery = FALSE; - tries = 0; - voltage = 0xff; - for (;;) { - usleep(100); - if (!atom_dp_get_link_status(output, link_status)) - break; - - if (dp_clock_recovery_ok(link_status, radeon_output->dp_lane_count)) { - clock_recovery = TRUE; - break; - } - - for (i = 0; i < radeon_output->dp_lane_count; i++) - if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) - break; - if (i == radeon_output->dp_lane_count) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "clock recovery reached max voltage\n"); - break; - } - - /* Check to see if we've tried the same voltage 5 times */ - if ((train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { - ++tries; - if (tries == 5) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "clock recovery tried 5 times\n"); - break; - } - } else - tries = 0; - - voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; - - dp_get_adjust_train(output, link_status, radeon_output->dp_lane_count, train_set); - dp_update_dpvs_emph(output, train_set); - - } - - if (!clock_recovery) - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "clock recovery failed\n"); - - /* channel equalization */ - tries = 0; - channel_eq = FALSE; - dp_set_training(output, DP_TRAINING_PATTERN_2); - if (IS_DCE4_VARIANT) - atombios_output_dig_encoder_setup(output, ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2); - else - RADEONDPEncoderService(output, ATOM_DP_ACTION_TRAINING_PATTERN_SEL, enc_id, 1); - - for (;;) { - usleep(400); - if (!atom_dp_get_link_status(output, link_status)) - break; - - if (dp_channel_eq_ok(link_status, radeon_output->dp_lane_count)) { - channel_eq = TRUE; - break; - } - - /* Try 5 times */ - if (tries > 5) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "channel eq failed: 5 tries\n"); - break; - } - - /* Compute new train_set as requested by target */ - dp_get_adjust_train(output, link_status, radeon_output->dp_lane_count, train_set); - dp_update_dpvs_emph(output, train_set); - - ++tries; - } - - if (!channel_eq) - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "channel eq failed\n"); - - dp_set_training(output, DP_TRAINING_PATTERN_DISABLE); - if (IS_DCE4_VARIANT) - atombios_output_dig_encoder_setup(output, ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE); - else - RADEONDPEncoderService(output, ATOM_DP_ACTION_TRAINING_COMPLETE, enc_id, 0); - -} - diff --git a/src/cayman_accel.c b/src/cayman_accel.c index 1dfaeceb..c1f74cbd 100644 --- a/src/cayman_accel.c +++ b/src/cayman_accel.c @@ -27,8 +27,6 @@ #include "config.h" #endif -#ifdef XF86DRM_MODE - #include "xf86.h" #include <errno.h> @@ -304,4 +302,3 @@ cayman_set_default_state(ScrnInfoPtr pScrn) END_BATCH(); } -#endif diff --git a/src/cayman_shader.c b/src/cayman_shader.c index 18e9f507..2a6d6b1b 100644 --- a/src/cayman_shader.c +++ b/src/cayman_shader.c @@ -28,8 +28,6 @@ #include "config.h" #endif -#ifdef XF86DRM_MODE - #include "xf86.h" #include "cayman_shader.h" @@ -3131,5 +3129,3 @@ int cayman_comp_ps(RADEONChipFamily ChipSet, uint32_t* shader) return i; } - -#endif diff --git a/src/drmmode_display.c b/src/drmmode_display.c index 3a08d8a2..0cd461df 100644 --- a/src/drmmode_display.c +++ b/src/drmmode_display.c @@ -30,7 +30,6 @@ #endif #include <errno.h> -#ifdef XF86DRM_MODE #include <sys/ioctl.h> #include "micmap.h" #include "xf86cmap.h" @@ -636,7 +635,7 @@ void drmmode_crtc_hw_id(xf86CrtcPtr crtc) ginfo.request = 0x4; tmp = drmmode_crtc->mode_crtc->crtc_id; ginfo.value = (uintptr_t)&tmp; - r = drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_INFO, &ginfo, sizeof(ginfo)); + r = drmCommandWriteRead(info->dri2.drm_fd, DRM_RADEON_INFO, &ginfo, sizeof(ginfo)); if (r) { drmmode_crtc->hw_id = -1; return; @@ -1528,7 +1527,7 @@ void drmmode_init(ScrnInfoPtr pScrn, drmmode_ptr drmmode) RADEONInfoPtr info = RADEONPTR(pScrn); if (pRADEONEnt->fd_wakeup_registered != serverGeneration && - info->dri->pKernelDRMVersion->version_minor >= 4) { + info->dri2.pKernelDRMVersion->version_minor >= 4) { AddGeneralSocket(drmmode->fd); RegisterBlockAndWakeupHandlers((BlockHandlerProcPtr)NoopDDA, drm_wakeup_handler, drmmode); @@ -1868,4 +1867,3 @@ error_out: return FALSE; } -#endif diff --git a/src/drmmode_display.h b/src/drmmode_display.h index 04a86882..45c33cb3 100644 --- a/src/drmmode_display.h +++ b/src/drmmode_display.h @@ -27,8 +27,6 @@ #ifndef DRMMODE_DISPLAY_H #define DRMMODE_DISPLAY_H -#ifdef XF86DRM_MODE - #include "xf86drmMode.h" #ifdef HAVE_LIBUDEV #include "libudev.h" @@ -119,4 +117,3 @@ Bool radeon_do_pageflip(ScrnInfoPtr scrn, struct radeon_bo *new_front, void *dat #endif -#endif diff --git a/src/evergreen_accel.c b/src/evergreen_accel.c index 581aaf6e..249eff8b 100644 --- a/src/evergreen_accel.c +++ b/src/evergreen_accel.c @@ -27,8 +27,6 @@ #include "config.h" #endif -#ifdef XF86DRM_MODE - #include "xf86.h" #include <errno.h> @@ -209,7 +207,6 @@ evergreen_set_render_target(ScrnInfoPtr pScrn, cb_config_t *cb_conf, uint32_t do uint32_t tile_split, macro_aspect, bankw, bankh; RADEONInfoPtr info = RADEONPTR(pScrn); -#if defined(XF86DRM_MODE) if (cb_conf->surface) { switch (cb_conf->surface->level[0].mode) { case RADEON_SURF_MODE_1D: @@ -234,9 +231,7 @@ evergreen_set_render_target(ScrnInfoPtr pScrn, cb_config_t *cb_conf, uint32_t do macro_aspect = eg_macro_tile_aspect(macro_aspect); bankw = eg_bank_wh(bankw); bankh = eg_bank_wh(bankh); - } else -#endif - { + } else { pitch = (cb_conf->w / 8) - 1; h = RADEON_ALIGN(cb_conf->h, 8); slice = ((cb_conf->w * h) / 64) - 1; @@ -371,7 +366,6 @@ void evergreen_cp_wait_vline_sync(ScrnInfoPtr pScrn, PixmapPtr pPix, { RADEONInfoPtr info = RADEONPTR(pScrn); drmmode_crtc_private_ptr drmmode_crtc; - uint32_t offset; if (!crtc) return; @@ -381,21 +375,8 @@ void evergreen_cp_wait_vline_sync(ScrnInfoPtr pScrn, PixmapPtr pPix, if (!crtc->enabled) return; - if (info->cs) { - if (pPix != pScrn->pScreen->GetScreenPixmap(pScrn->pScreen)) - return; - } else { -#ifdef USE_EXA - if (info->useEXA) - offset = exaGetPixmapOffset(pPix); - else -#endif - offset = pPix->devPrivate.ptr - info->FB; - - /* if drawing to front buffer */ - if (offset != 0) - return; - } + if (pPix != pScrn->pScreen->GetScreenPixmap(pScrn->pScreen)) + return; start = max(start, crtc->y); stop = min(stop, crtc->y + crtc->mode.VDisplay); @@ -698,7 +679,6 @@ evergreen_set_tex_resource(ScrnInfoPtr pScrn, tex_resource_t *tex_res, uint32_t uint32_t sq_tex_resource_word5, sq_tex_resource_word6, sq_tex_resource_word7; uint32_t array_mode, pitch, tile_split, macro_aspect, bankw, bankh, nbanks; -#if defined(XF86DRM_MODE) if (tex_res->surface) { switch (tex_res->surface->level[0].mode) { case RADEON_SURF_MODE_1D: @@ -720,9 +700,7 @@ evergreen_set_tex_resource(ScrnInfoPtr pScrn, tex_resource_t *tex_res, uint32_t macro_aspect = eg_macro_tile_aspect(macro_aspect); bankw = eg_bank_wh(bankw); bankh = eg_bank_wh(bankh); - } else -#endif - { + } else { array_mode = tex_res->array_mode; pitch = (tex_res->pitch + 7) >> 3; tile_split = 4; @@ -1503,4 +1481,3 @@ void evergreen_finish_op(ScrnInfoPtr pScrn, int vtx_size) } -#endif diff --git a/src/evergreen_exa.c b/src/evergreen_exa.c index 1e829bfd..247ba98c 100644 --- a/src/evergreen_exa.c +++ b/src/evergreen_exa.c @@ -28,8 +28,6 @@ #include "config.h" #endif -#ifdef XF86DRM_MODE - #include "xf86.h" #include "exa.h" @@ -1769,8 +1767,6 @@ EVERGREENAllocShaders(ScrnInfoPtr pScrn, ScreenPtr pScreen) /* 512 bytes per shader for now */ int size = 512 * 9; - accel_state->shaders = NULL; - accel_state->shaders_bo = radeon_bo_open(info->bufmgr, 0, size, 0, RADEON_GEM_DOMAIN_VRAM, 0); if (accel_state->shaders_bo == NULL) { @@ -1897,10 +1893,6 @@ EVERGREENDrawInit(ScreenPtr pScreen) return FALSE; } - /* accel requires kms */ - if (!info->cs) - return FALSE; - info->accel_state->exa->exa_major = EXA_VERSION_MAJOR; info->accel_state->exa->exa_minor = EXA_VERSION_MINOR; @@ -1998,5 +1990,3 @@ EVERGREENDrawInit(ScreenPtr pScreen) return TRUE; } - -#endif diff --git a/src/evergreen_shader.c b/src/evergreen_shader.c index a6faba05..ebc58f21 100644 --- a/src/evergreen_shader.c +++ b/src/evergreen_shader.c @@ -28,8 +28,6 @@ #include "config.h" #endif -#ifdef XF86DRM_MODE - #include "xf86.h" #include "evergreen_shader.h" @@ -3130,5 +3128,3 @@ int evergreen_comp_ps(RADEONChipFamily ChipSet, uint32_t* shader) return i; } - -#endif diff --git a/src/evergreen_state.h b/src/evergreen_state.h index 5a29f8fc..c92393ec 100644 --- a/src/evergreen_state.h +++ b/src/evergreen_state.h @@ -93,9 +93,7 @@ typedef struct { int blend_enable; uint32_t blendcntl; struct radeon_bo *bo; -#ifdef XF86DRM_MODE struct radeon_surface *surface; -#endif } cb_config_t; /* Shader */ @@ -182,9 +180,7 @@ typedef struct { int min_lod; struct radeon_bo *bo; struct radeon_bo *mip_bo; -#ifdef XF86DRM_MODE struct radeon_surface *surface; -#endif } tex_resource_t; /* Texture sampler */ diff --git a/src/evergreen_textured_videofuncs.c b/src/evergreen_textured_videofuncs.c index 0643ac62..2ffcdbed 100644 --- a/src/evergreen_textured_videofuncs.c +++ b/src/evergreen_textured_videofuncs.c @@ -28,8 +28,6 @@ #include "config.h" #endif -#ifdef XF86DRM_MODE - #include "xf86.h" #include "exa.h" @@ -527,5 +525,3 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) DamageDamageRegion(pPriv->pDraw, &pPriv->clip); } - -#endif diff --git a/src/generic_bus.h b/src/generic_bus.h deleted file mode 100644 index 553d3f28..00000000 --- a/src/generic_bus.h +++ /dev/null @@ -1,36 +0,0 @@ -#ifndef __GENERIC_BUS_H__ -#define __GENERIC_BUS_H__ - -/* this is meant to be used for proprietary buses where abstraction is needed - but they don't occur often enough to warrant a separate helper library */ - -#include <stdint.h> - -#define GB_IOCTL_GET_NAME 1 - /* third argument is size of the buffer, fourth argument is pointer - to the buffer. Returns the name of the bus */ -#define GB_IOCTL_GET_TYPE 2 - /* third argument is size of the buffer, fourth argument is pointer - to the buffer. Returns the type of the bus, driver should check - this at initialization time to find out whether they are compatible - */ - - -typedef struct _GENERIC_BUS_Rec *GENERIC_BUS_Ptr; - -typedef struct _GENERIC_BUS_Rec{ - ScrnInfoPtr pScrn; - DevUnion DriverPrivate; - Bool (*ioctl)(GENERIC_BUS_Ptr, long, long, char *); - Bool (*read)(GENERIC_BUS_Ptr, uint32_t, uint32_t, uint8_t *); - Bool (*write)(GENERIC_BUS_Ptr, uint32_t, uint32_t, uint8_t *); - Bool (*fifo_read)(GENERIC_BUS_Ptr, uint32_t, uint32_t, uint8_t *); - Bool (*fifo_write)(GENERIC_BUS_Ptr, uint32_t, uint32_t, uint8_t *); - - } GENERIC_BUS_Rec; - - - - - -#endif diff --git a/src/legacy_crtc.c b/src/legacy_crtc.c deleted file mode 100644 index 30119f5e..00000000 --- a/src/legacy_crtc.c +++ /dev/null @@ -1,1898 +0,0 @@ -/* - * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and - * VA Linux Systems Inc., Fremont, California. - * - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation on the rights to use, copy, modify, merge, - * publish, distribute, sublicense, and/or sell copies of the Software, - * and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR - * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include <string.h> -#include <stdio.h> - -/* X and server generic header files */ -#include "xf86.h" -#include "xf86_OSproc.h" -#include "vgaHW.h" -#include "xf86Modes.h" - -/* Driver data structures */ -#include "radeon.h" -#include "radeon_reg.h" -#include "radeon_macros.h" -#include "radeon_probe.h" -#include "radeon_version.h" -#include "radeon_atombios.h" - -#ifdef XF86DRI -#define _XF86DRI_SERVER_ -#include "radeon_drm.h" -#include "sarea.h" -#ifdef DRM_IOCTL_MODESET_CTL -#include <sys/ioctl.h> -#endif -#endif - -/* Write common registers */ -void -RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn, - RADEONSavePtr restore) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - if (info->IsSecondary) - return; - - OUTREG(RADEON_OVR_CLR, restore->ovr_clr); - OUTREG(RADEON_OVR_WID_LEFT_RIGHT, restore->ovr_wid_left_right); - OUTREG(RADEON_OVR_WID_TOP_BOTTOM, restore->ovr_wid_top_bottom); - OUTREG(RADEON_OV0_SCALE_CNTL, restore->ov0_scale_cntl); - OUTREG(RADEON_SUBPIC_CNTL, restore->subpic_cntl); - OUTREG(RADEON_VIPH_CONTROL, restore->viph_control); - OUTREG(RADEON_I2C_CNTL_1, restore->i2c_cntl_1); - OUTREG(RADEON_GEN_INT_CNTL, restore->gen_int_cntl); - OUTREG(RADEON_CAP0_TRIG_CNTL, restore->cap0_trig_cntl); - OUTREG(RADEON_CAP1_TRIG_CNTL, restore->cap1_trig_cntl); - OUTREG(RADEON_BUS_CNTL, restore->bus_cntl); - OUTREG(RADEON_SURFACE_CNTL, restore->surface_cntl); - - if ((info->ChipFamily == CHIP_FAMILY_RS400) || - (info->ChipFamily == CHIP_FAMILY_RS480)) { - OUTREG(RS400_DISP2_REQ_CNTL1, restore->disp2_req_cntl1); - OUTREG(RS400_DISP2_REQ_CNTL2, restore->disp2_req_cntl2); - OUTREG(RS400_DMIF_MEM_CNTL1, restore->dmif_mem_cntl1); - OUTREG(RS400_DISP1_REQ_CNTL1, restore->disp1_req_cntl1); - } - - /* Workaround for the VT switching problem in dual-head mode. This - * problem only occurs on RV style chips, typically when a FP and - * CRT are connected. - */ - if (pRADEONEnt->HasCRTC2 && - info->ChipFamily != CHIP_FAMILY_R200 && - !IS_R300_VARIANT) { - uint32_t tmp; - - tmp = INREG(RADEON_DAC_CNTL2); - OUTREG(RADEON_DAC_CNTL2, tmp & ~RADEON_DAC2_DAC_CLK_SEL); - usleep(100000); - } -} - -void -RADEONRestoreCrtcBase(ScrnInfoPtr pScrn, - RADEONSavePtr restore) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - if (IS_R300_VARIANT) - OUTREG(R300_CRTC_TILE_X0_Y0, restore->crtc_tile_x0_y0); - OUTREG(RADEON_CRTC_OFFSET_CNTL, restore->crtc_offset_cntl); - OUTREG(RADEON_CRTC_OFFSET, restore->crtc_offset); -} - -void -RADEONRestoreCrtc2Base(ScrnInfoPtr pScrn, - RADEONSavePtr restore) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - if (IS_R300_VARIANT) - OUTREG(R300_CRTC2_TILE_X0_Y0, restore->crtc2_tile_x0_y0); - OUTREG(RADEON_CRTC2_OFFSET_CNTL, restore->crtc2_offset_cntl); - OUTREG(RADEON_CRTC2_OFFSET, restore->crtc2_offset); -} - -/* Write CRTC registers */ -void -RADEONRestoreCrtcRegisters(ScrnInfoPtr pScrn, - RADEONSavePtr restore) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "Programming CRTC1, offset: 0x%08x\n", - (unsigned)restore->crtc_offset); - - /* We prevent the CRTC from hitting the memory controller until - * fully programmed - */ - OUTREG(RADEON_CRTC_GEN_CNTL, restore->crtc_gen_cntl | - RADEON_CRTC_DISP_REQ_EN_B); - - OUTREGP(RADEON_CRTC_EXT_CNTL, - restore->crtc_ext_cntl, - RADEON_CRTC_VSYNC_DIS | - RADEON_CRTC_HSYNC_DIS | - RADEON_CRTC_DISPLAY_DIS); - - OUTREG(RADEON_CRTC_H_TOTAL_DISP, restore->crtc_h_total_disp); - OUTREG(RADEON_CRTC_H_SYNC_STRT_WID, restore->crtc_h_sync_strt_wid); - OUTREG(RADEON_CRTC_V_TOTAL_DISP, restore->crtc_v_total_disp); - OUTREG(RADEON_CRTC_V_SYNC_STRT_WID, restore->crtc_v_sync_strt_wid); - - RADEONRestoreCrtcBase(pScrn, restore); - - OUTREG(RADEON_CRTC_PITCH, restore->crtc_pitch); - OUTREG(RADEON_DISP_MERGE_CNTL, restore->disp_merge_cntl); - - if (info->IsDellServer) { - OUTREG(RADEON_TV_DAC_CNTL, restore->tv_dac_cntl); - OUTREG(RADEON_DISP_HW_DEBUG, restore->disp_hw_debug); - OUTREG(RADEON_DAC_CNTL2, restore->dac2_cntl); - OUTREG(RADEON_CRTC2_GEN_CNTL, restore->crtc2_gen_cntl); - } - - OUTREG(RADEON_CRTC_GEN_CNTL, restore->crtc_gen_cntl); -} - -/* Write CRTC2 registers */ -void -RADEONRestoreCrtc2Registers(ScrnInfoPtr pScrn, - RADEONSavePtr restore) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - /* uint32_t crtc2_gen_cntl;*/ - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "Programming CRTC2, offset: 0x%08x\n", - (unsigned)restore->crtc2_offset); - - /* We prevent the CRTC from hitting the memory controller until - * fully programmed - */ - OUTREG(RADEON_CRTC2_GEN_CNTL, - restore->crtc2_gen_cntl | RADEON_CRTC2_VSYNC_DIS | - RADEON_CRTC2_HSYNC_DIS | RADEON_CRTC2_DISP_DIS | - RADEON_CRTC2_DISP_REQ_EN_B); - - OUTREG(RADEON_CRTC2_H_TOTAL_DISP, restore->crtc2_h_total_disp); - OUTREG(RADEON_CRTC2_H_SYNC_STRT_WID, restore->crtc2_h_sync_strt_wid); - OUTREG(RADEON_CRTC2_V_TOTAL_DISP, restore->crtc2_v_total_disp); - OUTREG(RADEON_CRTC2_V_SYNC_STRT_WID, restore->crtc2_v_sync_strt_wid); - - OUTREG(RADEON_FP_H2_SYNC_STRT_WID, restore->fp_h2_sync_strt_wid); - OUTREG(RADEON_FP_V2_SYNC_STRT_WID, restore->fp_v2_sync_strt_wid); - - RADEONRestoreCrtc2Base(pScrn, restore); - - OUTREG(RADEON_CRTC2_PITCH, restore->crtc2_pitch); - OUTREG(RADEON_DISP2_MERGE_CNTL, restore->disp2_merge_cntl); - - OUTREG(RADEON_CRTC2_GEN_CNTL, restore->crtc2_gen_cntl); - -} - -static void -RADEONPLLWaitForReadUpdateComplete(ScrnInfoPtr pScrn) -{ - int i = 0; - - /* FIXME: Certain revisions of R300 can't recover here. Not sure of - the cause yet, but this workaround will mask the problem for now. - Other chips usually will pass at the very first test, so the - workaround shouldn't have any effect on them. */ - for (i = 0; - (i < 10000 && - INPLL(pScrn, RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); - i++); -} - -static void -RADEONPLLWriteUpdate(ScrnInfoPtr pScrn) -{ - while (INPLL(pScrn, RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); - - OUTPLLP(pScrn, RADEON_PPLL_REF_DIV, - RADEON_PPLL_ATOMIC_UPDATE_W, - ~(RADEON_PPLL_ATOMIC_UPDATE_W)); -} - -static void -RADEONPLL2WaitForReadUpdateComplete(ScrnInfoPtr pScrn) -{ - int i = 0; - - /* FIXME: Certain revisions of R300 can't recover here. Not sure of - the cause yet, but this workaround will mask the problem for now. - Other chips usually will pass at the very first test, so the - workaround shouldn't have any effect on them. */ - for (i = 0; - (i < 10000 && - INPLL(pScrn, RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R); - i++); -} - -static void -RADEONPLL2WriteUpdate(ScrnInfoPtr pScrn) -{ - while (INPLL(pScrn, RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R); - - OUTPLLP(pScrn, RADEON_P2PLL_REF_DIV, - RADEON_P2PLL_ATOMIC_UPDATE_W, - ~(RADEON_P2PLL_ATOMIC_UPDATE_W)); -} - -static uint8_t -RADEONComputePLLGain(uint16_t reference_freq, uint16_t ref_div, - uint16_t fb_div) -{ - unsigned vcoFreq; - - if (!ref_div) - return 1; - - vcoFreq = ((unsigned)reference_freq * fb_div) / ref_div; - - /* - * This is horribly crude: the VCO frequency range is divided into - * 3 parts, each part having a fixed PLL gain value. - */ - if (vcoFreq >= 30000) - /* - * [300..max] MHz : 7 - */ - return 7; - else if (vcoFreq >= 18000) - /* - * [180..300) MHz : 4 - */ - return 4; - else - /* - * [0..180) MHz : 1 - */ - return 1; -} - -/* Write PLL registers */ -void -RADEONRestorePLLRegisters(ScrnInfoPtr pScrn, - RADEONSavePtr restore) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - uint8_t pllGain; - -#if defined(__powerpc__) - /* apparently restoring the pll causes a hang??? */ - if (info->MacModel == RADEON_MAC_IBOOK) - return; -#endif - - pllGain = RADEONComputePLLGain(info->pll.reference_freq, - restore->ppll_ref_div & RADEON_PPLL_REF_DIV_MASK, - restore->ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK); - - if (info->IsMobility) { - /* A temporal workaround for the occational blanking on certain laptop panels. - This appears to related to the PLL divider registers (fail to lock?). - It occurs even when all dividers are the same with their old settings. - In this case we really don't need to fiddle with PLL registers. - By doing this we can avoid the blanking problem with some panels. - */ - if ((restore->ppll_ref_div == (INPLL(pScrn, RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) && - (restore->ppll_div_3 == (INPLL(pScrn, RADEON_PPLL_DIV_3) & - (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) { - OUTREGP(RADEON_CLOCK_CNTL_INDEX, - RADEON_PLL_DIV_SEL, - ~(RADEON_PLL_DIV_SEL)); - RADEONPllErrataAfterIndex(info); - return; - } - } - - OUTPLLP(pScrn, RADEON_VCLK_ECP_CNTL, - RADEON_VCLK_SRC_SEL_CPUCLK, - ~(RADEON_VCLK_SRC_SEL_MASK)); - - OUTPLLP(pScrn, - RADEON_PPLL_CNTL, - RADEON_PPLL_RESET - | RADEON_PPLL_ATOMIC_UPDATE_EN - | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN - | ((uint32_t)pllGain << RADEON_PPLL_PVG_SHIFT), - ~(RADEON_PPLL_RESET - | RADEON_PPLL_ATOMIC_UPDATE_EN - | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN - | RADEON_PPLL_PVG_MASK)); - - OUTREGP(RADEON_CLOCK_CNTL_INDEX, - RADEON_PLL_DIV_SEL, - ~(RADEON_PLL_DIV_SEL)); - RADEONPllErrataAfterIndex(info); - - if (IS_R300_VARIANT || - (info->ChipFamily == CHIP_FAMILY_RS300) || - (info->ChipFamily == CHIP_FAMILY_RS400) || - (info->ChipFamily == CHIP_FAMILY_RS480)) { - if (restore->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { - /* When restoring console mode, use saved PPLL_REF_DIV - * setting. - */ - OUTPLLP(pScrn, RADEON_PPLL_REF_DIV, - restore->ppll_ref_div, - 0); - } else { - /* R300 uses ref_div_acc field as real ref divider */ - OUTPLLP(pScrn, RADEON_PPLL_REF_DIV, - (restore->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT), - ~R300_PPLL_REF_DIV_ACC_MASK); - } - } else { - OUTPLLP(pScrn, RADEON_PPLL_REF_DIV, - restore->ppll_ref_div, - ~RADEON_PPLL_REF_DIV_MASK); - } - - OUTPLLP(pScrn, RADEON_PPLL_DIV_3, - restore->ppll_div_3, - ~RADEON_PPLL_FB3_DIV_MASK); - - OUTPLLP(pScrn, RADEON_PPLL_DIV_3, - restore->ppll_div_3, - ~RADEON_PPLL_POST3_DIV_MASK); - - RADEONPLLWriteUpdate(pScrn); - RADEONPLLWaitForReadUpdateComplete(pScrn); - - OUTPLL(pScrn, RADEON_HTOTAL_CNTL, restore->htotal_cntl); - - OUTPLLP(pScrn, RADEON_PPLL_CNTL, - 0, - ~(RADEON_PPLL_RESET - | RADEON_PPLL_SLEEP - | RADEON_PPLL_ATOMIC_UPDATE_EN - | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN)); - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n", - restore->ppll_ref_div, - restore->ppll_div_3, - (unsigned)restore->htotal_cntl, - INPLL(pScrn, RADEON_PPLL_CNTL)); - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "Wrote: rd=%d, fd=%d, pd=%d\n", - restore->ppll_ref_div & RADEON_PPLL_REF_DIV_MASK, - restore->ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK, - (restore->ppll_div_3 & RADEON_PPLL_POST3_DIV_MASK) >> 16); - - usleep(50000); /* Let the clock to lock */ - - OUTPLLP(pScrn, RADEON_VCLK_ECP_CNTL, - RADEON_VCLK_SRC_SEL_PPLLCLK, - ~(RADEON_VCLK_SRC_SEL_MASK)); - - /*OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, restore->vclk_ecp_cntl);*/ - - ErrorF("finished PLL1\n"); - -} - -/* Write PLL2 registers */ -void -RADEONRestorePLL2Registers(ScrnInfoPtr pScrn, - RADEONSavePtr restore) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - uint8_t pllGain; - - pllGain = RADEONComputePLLGain(info->pll.reference_freq, - restore->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK, - restore->p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK); - - - OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, - RADEON_PIX2CLK_SRC_SEL_CPUCLK, - ~(RADEON_PIX2CLK_SRC_SEL_MASK)); - - OUTPLLP(pScrn, - RADEON_P2PLL_CNTL, - RADEON_P2PLL_RESET - | RADEON_P2PLL_ATOMIC_UPDATE_EN - | ((uint32_t)pllGain << RADEON_P2PLL_PVG_SHIFT), - ~(RADEON_P2PLL_RESET - | RADEON_P2PLL_ATOMIC_UPDATE_EN - | RADEON_P2PLL_PVG_MASK)); - - - OUTPLLP(pScrn, RADEON_P2PLL_REF_DIV, - restore->p2pll_ref_div, - ~RADEON_P2PLL_REF_DIV_MASK); - - OUTPLLP(pScrn, RADEON_P2PLL_DIV_0, - restore->p2pll_div_0, - ~RADEON_P2PLL_FB0_DIV_MASK); - - OUTPLLP(pScrn, RADEON_P2PLL_DIV_0, - restore->p2pll_div_0, - ~RADEON_P2PLL_POST0_DIV_MASK); - - RADEONPLL2WriteUpdate(pScrn); - RADEONPLL2WaitForReadUpdateComplete(pScrn); - - OUTPLL(pScrn, RADEON_HTOTAL2_CNTL, restore->htotal_cntl2); - - OUTPLLP(pScrn, RADEON_P2PLL_CNTL, - 0, - ~(RADEON_P2PLL_RESET - | RADEON_P2PLL_SLEEP - | RADEON_P2PLL_ATOMIC_UPDATE_EN)); - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n", - (unsigned)restore->p2pll_ref_div, - (unsigned)restore->p2pll_div_0, - (unsigned)restore->htotal_cntl2, - INPLL(pScrn, RADEON_P2PLL_CNTL)); - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "Wrote2: rd=%u, fd=%u, pd=%u\n", - (unsigned)restore->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK, - (unsigned)restore->p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK, - (unsigned)((restore->p2pll_div_0 & - RADEON_P2PLL_POST0_DIV_MASK) >>16)); - - usleep(5000); /* Let the clock to lock */ - - OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, - RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, - ~(RADEON_PIX2CLK_SRC_SEL_MASK)); - - OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, restore->pixclks_cntl); - - ErrorF("finished PLL2\n"); - -} - -/* Read common registers */ -void -RADEONSaveCommonRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - save->ovr_clr = INREG(RADEON_OVR_CLR); - save->ovr_wid_left_right = INREG(RADEON_OVR_WID_LEFT_RIGHT); - save->ovr_wid_top_bottom = INREG(RADEON_OVR_WID_TOP_BOTTOM); - save->ov0_scale_cntl = INREG(RADEON_OV0_SCALE_CNTL); - save->subpic_cntl = INREG(RADEON_SUBPIC_CNTL); - save->viph_control = INREG(RADEON_VIPH_CONTROL); - save->i2c_cntl_1 = INREG(RADEON_I2C_CNTL_1); - save->gen_int_cntl = INREG(RADEON_GEN_INT_CNTL); - save->cap0_trig_cntl = INREG(RADEON_CAP0_TRIG_CNTL); - save->cap1_trig_cntl = INREG(RADEON_CAP1_TRIG_CNTL); - save->bus_cntl = INREG(RADEON_BUS_CNTL); - save->surface_cntl = INREG(RADEON_SURFACE_CNTL); - save->grph_buffer_cntl = INREG(RADEON_GRPH_BUFFER_CNTL); - save->grph2_buffer_cntl = INREG(RADEON_GRPH2_BUFFER_CNTL); - - if ((info->ChipFamily == CHIP_FAMILY_RS400) || - (info->ChipFamily == CHIP_FAMILY_RS480)) { - save->disp2_req_cntl1 = INREG(RS400_DISP2_REQ_CNTL1); - save->disp2_req_cntl2 = INREG(RS400_DISP2_REQ_CNTL2); - save->dmif_mem_cntl1 = INREG(RS400_DMIF_MEM_CNTL1); - save->disp1_req_cntl1 = INREG(RS400_DISP1_REQ_CNTL1); - } -} - -/* Read CRTC registers */ -void -RADEONSaveCrtcRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - save->crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL); - save->crtc_ext_cntl = INREG(RADEON_CRTC_EXT_CNTL); - save->crtc_h_total_disp = INREG(RADEON_CRTC_H_TOTAL_DISP); - save->crtc_h_sync_strt_wid = INREG(RADEON_CRTC_H_SYNC_STRT_WID); - save->crtc_v_total_disp = INREG(RADEON_CRTC_V_TOTAL_DISP); - save->crtc_v_sync_strt_wid = INREG(RADEON_CRTC_V_SYNC_STRT_WID); - - save->crtc_offset = INREG(RADEON_CRTC_OFFSET); - save->crtc_offset_cntl = INREG(RADEON_CRTC_OFFSET_CNTL); - save->crtc_pitch = INREG(RADEON_CRTC_PITCH); - save->disp_merge_cntl = INREG(RADEON_DISP_MERGE_CNTL); - - if (IS_R300_VARIANT) - save->crtc_tile_x0_y0 = INREG(R300_CRTC_TILE_X0_Y0); - - if (info->IsDellServer) { - save->tv_dac_cntl = INREG(RADEON_TV_DAC_CNTL); - save->dac2_cntl = INREG(RADEON_DAC_CNTL2); - save->disp_hw_debug = INREG (RADEON_DISP_HW_DEBUG); - save->crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL); - } - - /* track if the crtc is enabled for text restore */ - if (save->crtc_ext_cntl & RADEON_CRTC_DISPLAY_DIS) - info->crtc_on = FALSE; - else - info->crtc_on = TRUE; - -} - -/* Read CRTC2 registers */ -void -RADEONSaveCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - save->crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL); - save->crtc2_h_total_disp = INREG(RADEON_CRTC2_H_TOTAL_DISP); - save->crtc2_h_sync_strt_wid = INREG(RADEON_CRTC2_H_SYNC_STRT_WID); - save->crtc2_v_total_disp = INREG(RADEON_CRTC2_V_TOTAL_DISP); - save->crtc2_v_sync_strt_wid = INREG(RADEON_CRTC2_V_SYNC_STRT_WID); - - save->crtc2_offset = INREG(RADEON_CRTC2_OFFSET); - save->crtc2_offset_cntl = INREG(RADEON_CRTC2_OFFSET_CNTL); - save->crtc2_pitch = INREG(RADEON_CRTC2_PITCH); - - if (IS_R300_VARIANT) - save->crtc2_tile_x0_y0 = INREG(R300_CRTC2_TILE_X0_Y0); - - save->fp_h2_sync_strt_wid = INREG (RADEON_FP_H2_SYNC_STRT_WID); - save->fp_v2_sync_strt_wid = INREG (RADEON_FP_V2_SYNC_STRT_WID); - - save->disp2_merge_cntl = INREG(RADEON_DISP2_MERGE_CNTL); - - /* track if the crtc is enabled for text restore */ - if (save->crtc2_gen_cntl & RADEON_CRTC2_DISP_DIS) - info->crtc2_on = FALSE; - else - info->crtc2_on = TRUE; - -} - -/* Read PLL registers */ -void -RADEONSavePLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) -{ - save->ppll_ref_div = INPLL(pScrn, RADEON_PPLL_REF_DIV); - save->ppll_div_3 = INPLL(pScrn, RADEON_PPLL_DIV_3); - save->htotal_cntl = INPLL(pScrn, RADEON_HTOTAL_CNTL); - save->vclk_ecp_cntl = INPLL(pScrn, RADEON_VCLK_ECP_CNTL); - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "Read: 0x%08x 0x%08x 0x%08x\n", - save->ppll_ref_div, - save->ppll_div_3, - (unsigned)save->htotal_cntl); - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "Read: rd=%d, fd=%d, pd=%d\n", - save->ppll_ref_div & RADEON_PPLL_REF_DIV_MASK, - save->ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK, - (save->ppll_div_3 & RADEON_PPLL_POST3_DIV_MASK) >> 16); -} - -/* Read PLL registers */ -void -RADEONSavePLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save) -{ - save->p2pll_ref_div = INPLL(pScrn, RADEON_P2PLL_REF_DIV); - save->p2pll_div_0 = INPLL(pScrn, RADEON_P2PLL_DIV_0); - save->htotal_cntl2 = INPLL(pScrn, RADEON_HTOTAL2_CNTL); - save->pixclks_cntl = INPLL(pScrn, RADEON_PIXCLKS_CNTL); - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "Read: 0x%08x 0x%08x 0x%08x\n", - (unsigned)save->p2pll_ref_div, - (unsigned)save->p2pll_div_0, - (unsigned)save->htotal_cntl2); - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "Read: rd=%u, fd=%u, pd=%u\n", - (unsigned)(save->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK), - (unsigned)(save->p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK), - (unsigned)((save->p2pll_div_0 & RADEON_P2PLL_POST0_DIV_MASK) - >> 16)); -} - -void -radeon_crtc_modeset_ioctl(xf86CrtcPtr crtc, Bool post) -{ -#if defined(XF86DRI) && defined(DRM_IOCTL_MODESET_CTL) - RADEONInfoPtr info = RADEONPTR(crtc->scrn); - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - struct drm_modeset_ctl modeset; - unsigned char *RADEONMMIO = info->MMIO; - - if (!info->directRenderingEnabled) - return; - - if (info->ChipFamily >= CHIP_FAMILY_R600) - return; - - modeset.crtc = radeon_crtc->crtc_id; - modeset.cmd = post ? _DRM_POST_MODESET : _DRM_PRE_MODESET; - - ioctl(info->dri->drmFD, DRM_IOCTL_MODESET_CTL, &modeset); - - info->ModeReg->gen_int_cntl = INREG( RADEON_GEN_INT_CNTL ); -#endif -} - -void -legacy_crtc_dpms(xf86CrtcPtr crtc, int mode) -{ - uint32_t mask; - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - RADEONEntPtr pRADEONEnt = RADEONEntPriv(crtc->scrn); - unsigned char *RADEONMMIO = pRADEONEnt->MMIO; - - if (radeon_crtc->crtc_id) - mask = (RADEON_CRTC2_DISP_DIS | - RADEON_CRTC2_VSYNC_DIS | - RADEON_CRTC2_HSYNC_DIS | - RADEON_CRTC2_DISP_REQ_EN_B); - else - mask = (RADEON_CRTC_DISPLAY_DIS | - RADEON_CRTC_HSYNC_DIS | - RADEON_CRTC_VSYNC_DIS); - - switch(mode) { - case DPMSModeOn: - if (radeon_crtc->crtc_id) { - OUTREGP(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask)); - } else { - OUTREGP(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN | RADEON_CRTC_DISP_REQ_EN_B)); - OUTREGP(RADEON_CRTC_EXT_CNTL, 0, ~mask); - } - break; - case DPMSModeStandby: - case DPMSModeSuspend: - case DPMSModeOff: - if (radeon_crtc->crtc_id) { - OUTREGP(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask)); - } else { - OUTREGP(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN | RADEON_CRTC_DISP_REQ_EN_B)); - OUTREGP(RADEON_CRTC_EXT_CNTL, mask, ~mask); - } - break; - } -} - - -/* Define common registers for requested video mode */ -void -RADEONInitCommonRegisters(RADEONSavePtr save, RADEONInfoPtr info) -{ - save->ovr_clr = 0; - save->ovr_wid_left_right = 0; - save->ovr_wid_top_bottom = 0; - save->ov0_scale_cntl = 0; - save->subpic_cntl = 0; - save->viph_control = 0; - save->i2c_cntl_1 = 0; - save->rbbm_soft_reset = 0; - save->cap0_trig_cntl = 0; - save->cap1_trig_cntl = 0; - save->bus_cntl = info->BusCntl; - - if ((info->ChipFamily == CHIP_FAMILY_RS400) || - (info->ChipFamily == CHIP_FAMILY_RS480)) { - save->disp2_req_cntl1 = info->SavedReg->disp2_req_cntl1; - save->disp2_req_cntl2 = info->SavedReg->disp2_req_cntl2; - save->dmif_mem_cntl1 = info->SavedReg->dmif_mem_cntl1; - save->disp1_req_cntl1 = info->SavedReg->disp1_req_cntl1; - } - - /* - * If bursts are enabled, turn on discards - * Radeon doesn't have write bursts - */ - if (save->bus_cntl & (RADEON_BUS_READ_BURST)) - save->bus_cntl |= RADEON_BUS_RD_DISCARD_EN; -} - -void -RADEONInitSurfaceCntl(xf86CrtcPtr crtc, RADEONSavePtr save) -{ - save->surface_cntl = 0; - -#if X_BYTE_ORDER == X_BIG_ENDIAN - /* We must set both apertures as they can be both used to map the entire - * video memory. -BenH. - */ - switch (crtc->scrn->bitsPerPixel) { - case 16: - save->surface_cntl |= RADEON_NONSURF_AP0_SWP_16BPP; - save->surface_cntl |= RADEON_NONSURF_AP1_SWP_16BPP; - break; - - case 32: - save->surface_cntl |= RADEON_NONSURF_AP0_SWP_32BPP; - save->surface_cntl |= RADEON_NONSURF_AP1_SWP_32BPP; - break; - } -#endif - -} - -void -RADEONInitCrtcBase(xf86CrtcPtr crtc, RADEONSavePtr save, - int x, int y) -{ - ScrnInfoPtr pScrn = crtc->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - int Base; -#ifdef XF86DRI - drm_radeon_sarea_t *pSAREAPriv; - XF86DRISAREAPtr pSAREA; -#endif - - save->crtc_offset = pScrn->fbOffset; -#ifdef XF86DRI - if (info->dri && info->dri->allowPageFlip) - save->crtc_offset_cntl = RADEON_CRTC_OFFSET_FLIP_CNTL; - else -#endif - save->crtc_offset_cntl = 0; - - if (info->tilingEnabled && (crtc->rotatedData == NULL)) { - if (IS_R300_VARIANT) - save->crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN | - R300_CRTC_MICRO_TILE_BUFFER_DIS | - R300_CRTC_MACRO_TILE_EN); - else - save->crtc_offset_cntl |= RADEON_CRTC_TILE_EN; - } - else { - if (IS_R300_VARIANT) - save->crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN | - R300_CRTC_MICRO_TILE_BUFFER_DIS | - R300_CRTC_MACRO_TILE_EN); - else - save->crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN; - } - - Base = pScrn->fbOffset; - - if (info->tilingEnabled && (crtc->rotatedData == NULL)) { - if (IS_R300_VARIANT) { - /* On r300/r400 when tiling is enabled crtc_offset is set to the address of - * the surface. the x/y offsets are handled by the X_Y tile reg for each crtc - * Makes tiling MUCH easier. - */ - save->crtc_tile_x0_y0 = x | (y << 16); - Base &= ~0x7ff; - } else { - /* note we cannot really simply use the info->ModeReg.crtc_offset_cntl value, since the - drm might have set FLIP_CNTL since we wrote that. Unfortunately FLIP_CNTL causes - flickering when scrolling vertically in a virtual screen, possibly because crtc will - pick up the new offset value at the end of each scanline, but the new offset_cntl value - only after a vsync. We'd probably need to wait (in drm) for vsync and only then update - OFFSET and OFFSET_CNTL, if the y coord has changed. Seems hard to fix. */ - /*save->crtc_offset_cntl = INREG(RADEON_CRTC_OFFSET_CNTL) & ~0xf;*/ -#if 0 - /* try to get rid of flickering when scrolling at least for 2d */ -#ifdef XF86DRI - if (!info->have3DWindows) -#endif - save->crtc_offset_cntl &= ~RADEON_CRTC_OFFSET_FLIP_CNTL; -#endif - - int byteshift = info->CurrentLayout.bitsPerPixel >> 4; - /* crtc uses 256(bytes)x8 "half-tile" start addresses? */ - int tile_addr = (((y >> 3) * info->CurrentLayout.displayWidth + x) >> (8 - byteshift)) << 11; - Base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8); - save->crtc_offset_cntl = save->crtc_offset_cntl | (y % 16); - } - } - else { - int offset = y * info->CurrentLayout.displayWidth + x; - switch (info->CurrentLayout.pixel_code) { - case 15: - case 16: offset *= 2; break; - case 24: offset *= 3; break; - case 32: offset *= 4; break; - } - Base += offset; - } - - if (crtc->rotatedData != NULL) { - Base = pScrn->fbOffset + (char *)crtc->rotatedData - (char *)info->FB; - } - - Base &= ~7; /* 3 lower bits are always 0 */ - - -#ifdef XF86DRI - if (info->directRenderingInited) { - /* note cannot use pScrn->pScreen since this is unitialized when called from - RADEONScreenInit, and we need to call from there to get mergedfb + pageflip working */ - /*** NOTE: r3/4xx will need sarea and drm pageflip updates to handle the xytile regs for - *** pageflipping! - ***/ - pSAREAPriv = DRIGetSAREAPrivate(xf86ScrnToScreen(pScrn)); - /* can't get at sarea in a semi-sane way? */ - pSAREA = (void *)((char*)pSAREAPriv - sizeof(XF86DRISAREARec)); - - pSAREA->frame.x = (Base / info->CurrentLayout.pixel_bytes) - % info->CurrentLayout.displayWidth; - pSAREA->frame.y = (Base / info->CurrentLayout.pixel_bytes) - / info->CurrentLayout.displayWidth; - pSAREA->frame.width = pScrn->frameX1 - x + 1; - pSAREA->frame.height = pScrn->frameY1 - y + 1; - - if (pSAREAPriv->pfCurrentPage == 1) { - Base += info->dri->backOffset - info->dri->frontOffset; - } - } -#endif - save->crtc_offset = Base; - -} - -/* Define CRTC registers for requested video mode */ -static Bool -RADEONInitCrtcRegisters(xf86CrtcPtr crtc, RADEONSavePtr save, - DisplayModePtr mode) -{ - ScrnInfoPtr pScrn = crtc->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - int format; - int hsync_start; - int hsync_wid; - int vsync_wid; - - switch (info->CurrentLayout.pixel_code) { - case 4: format = 1; break; - case 8: format = 2; break; - case 15: format = 3; break; /* 555 */ - case 16: format = 4; break; /* 565 */ - case 24: format = 5; break; /* RGB */ - case 32: format = 6; break; /* xRGB */ - default: - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Unsupported pixel depth (%d)\n", - info->CurrentLayout.bitsPerPixel); - return FALSE; - } - - /*save->bios_4_scratch = info->SavedReg->bios_4_scratch;*/ - save->crtc_gen_cntl = (RADEON_CRTC_EXT_DISP_EN - | (format << 8) - | ((mode->Flags & V_DBLSCAN) - ? RADEON_CRTC_DBL_SCAN_EN - : 0) - | ((mode->Flags & V_CSYNC) - ? RADEON_CRTC_CSYNC_EN - : 0) - | ((mode->Flags & V_INTERLACE) - ? RADEON_CRTC_INTERLACE_EN - : 0)); - - /* 200M freezes on VT switch sometimes if CRTC is disabled */ - if ((info->ChipFamily == CHIP_FAMILY_RS400) || - (info->ChipFamily == CHIP_FAMILY_RS480)) - save->crtc_gen_cntl |= RADEON_CRTC_EN; - - save->crtc_ext_cntl |= (RADEON_XCRT_CNT_EN| - RADEON_CRTC_VSYNC_DIS | - RADEON_CRTC_HSYNC_DIS | - RADEON_CRTC_DISPLAY_DIS); - - save->disp_merge_cntl = info->SavedReg->disp_merge_cntl; - save->disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; - - save->crtc_h_total_disp = ((((mode->CrtcHTotal / 8) - 1) & 0x3ff) - | ((((mode->CrtcHDisplay / 8) - 1) & 0x1ff) - << 16)); - - hsync_wid = (mode->CrtcHSyncEnd - mode->CrtcHSyncStart) / 8; - if (!hsync_wid) hsync_wid = 1; - hsync_start = mode->CrtcHSyncStart - 8; - - save->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) - | ((hsync_wid & 0x3f) << 16) - | ((mode->Flags & V_NHSYNC) - ? RADEON_CRTC_H_SYNC_POL - : 0)); - - /* This works for double scan mode. */ - save->crtc_v_total_disp = (((mode->CrtcVTotal - 1) & 0xffff) - | ((mode->CrtcVDisplay - 1) << 16)); - - vsync_wid = mode->CrtcVSyncEnd - mode->CrtcVSyncStart; - if (!vsync_wid) vsync_wid = 1; - - save->crtc_v_sync_strt_wid = (((mode->CrtcVSyncStart - 1) & 0xfff) - | ((vsync_wid & 0x1f) << 16) - | ((mode->Flags & V_NVSYNC) - ? RADEON_CRTC_V_SYNC_POL - : 0)); - - save->crtc_pitch = (((pScrn->displayWidth * pScrn->bitsPerPixel) + - ((pScrn->bitsPerPixel * 8) -1)) / - (pScrn->bitsPerPixel * 8)); - save->crtc_pitch |= save->crtc_pitch << 16; - - if (info->IsDellServer) { - save->dac2_cntl = info->SavedReg->dac2_cntl; - save->tv_dac_cntl = info->SavedReg->tv_dac_cntl; - save->crtc2_gen_cntl = info->SavedReg->crtc2_gen_cntl; - save->disp_hw_debug = info->SavedReg->disp_hw_debug; - - save->dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL; - save->dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL; - - /* For CRT on DAC2, don't turn it on if BIOS didn't - enable it, even it's detected. - */ - save->disp_hw_debug |= RADEON_CRT2_DISP1_SEL; - save->tv_dac_cntl &= ~((1<<2) | (3<<8) | (7<<24) | (0xff<<16)); - save->tv_dac_cntl |= (0x03 | (2<<8) | (0x58<<16)); - } - - return TRUE; -} - - -void -RADEONInitCrtc2Base(xf86CrtcPtr crtc, RADEONSavePtr save, - int x, int y) -{ - ScrnInfoPtr pScrn = crtc->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - int Base; -#ifdef XF86DRI - drm_radeon_sarea_t *pSAREAPriv; - XF86DRISAREAPtr pSAREA; -#endif - - /* It seems all fancy options apart from pflip can be safely disabled - */ - save->crtc2_offset = pScrn->fbOffset; -#ifdef XF86DRI - if (info->dri && info->dri->allowPageFlip) - save->crtc2_offset_cntl = RADEON_CRTC_OFFSET_FLIP_CNTL; - else -#endif - save->crtc2_offset_cntl = 0; - - if (info->tilingEnabled && (crtc->rotatedData == NULL)) { - if (IS_R300_VARIANT) - save->crtc2_offset_cntl |= (R300_CRTC_X_Y_MODE_EN | - R300_CRTC_MICRO_TILE_BUFFER_DIS | - R300_CRTC_MACRO_TILE_EN); - else - save->crtc2_offset_cntl |= RADEON_CRTC_TILE_EN; - } - else { - if (IS_R300_VARIANT) - save->crtc2_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN | - R300_CRTC_MICRO_TILE_BUFFER_DIS | - R300_CRTC_MACRO_TILE_EN); - else - save->crtc2_offset_cntl &= ~RADEON_CRTC_TILE_EN; - } - - Base = pScrn->fbOffset; - - if (info->tilingEnabled && (crtc->rotatedData == NULL)) { - if (IS_R300_VARIANT) { - /* On r300/r400 when tiling is enabled crtc_offset is set to the address of - * the surface. the x/y offsets are handled by the X_Y tile reg for each crtc - * Makes tiling MUCH easier. - */ - save->crtc2_tile_x0_y0 = x | (y << 16); - Base &= ~0x7ff; - } else { - /* note we cannot really simply use the info->ModeReg.crtc_offset_cntl value, since the - drm might have set FLIP_CNTL since we wrote that. Unfortunately FLIP_CNTL causes - flickering when scrolling vertically in a virtual screen, possibly because crtc will - pick up the new offset value at the end of each scanline, but the new offset_cntl value - only after a vsync. We'd probably need to wait (in drm) for vsync and only then update - OFFSET and OFFSET_CNTL, if the y coord has changed. Seems hard to fix. */ - /*save->crtc2_offset_cntl = INREG(RADEON_CRTC2_OFFSET_CNTL) & ~0xf;*/ -#if 0 - /* try to get rid of flickering when scrolling at least for 2d */ -#ifdef XF86DRI - if (!info->have3DWindows) -#endif - save->crtc2_offset_cntl &= ~RADEON_CRTC_OFFSET_FLIP_CNTL; -#endif - - int byteshift = info->CurrentLayout.bitsPerPixel >> 4; - /* crtc uses 256(bytes)x8 "half-tile" start addresses? */ - int tile_addr = (((y >> 3) * info->CurrentLayout.displayWidth + x) >> (8 - byteshift)) << 11; - Base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8); - save->crtc2_offset_cntl = save->crtc_offset_cntl | (y % 16); - } - } - else { - int offset = y * info->CurrentLayout.displayWidth + x; - switch (info->CurrentLayout.pixel_code) { - case 15: - case 16: offset *= 2; break; - case 24: offset *= 3; break; - case 32: offset *= 4; break; - } - Base += offset; - } - - if (crtc->rotatedData != NULL) { - Base = pScrn->fbOffset + (char *)crtc->rotatedData - (char *)info->FB; - } - - Base &= ~7; /* 3 lower bits are always 0 */ - -#ifdef XF86DRI - if (info->directRenderingInited) { - /* note cannot use pScrn->pScreen since this is unitialized when called from - RADEONScreenInit, and we need to call from there to get mergedfb + pageflip working */ - /*** NOTE: r3/4xx will need sarea and drm pageflip updates to handle the xytile regs for - *** pageflipping! - ***/ - pSAREAPriv = DRIGetSAREAPrivate(xf86ScrnToScreen(pScrn)); - /* can't get at sarea in a semi-sane way? */ - pSAREA = (void *)((char*)pSAREAPriv - sizeof(XF86DRISAREARec)); - - pSAREAPriv->crtc2_base = Base; - - if (pSAREAPriv->pfCurrentPage == 1) { - Base += info->dri->backOffset - info->dri->frontOffset; - } - } -#endif - save->crtc2_offset = Base; - -} - - -/* Define CRTC2 registers for requested video mode */ -static Bool -RADEONInitCrtc2Registers(xf86CrtcPtr crtc, RADEONSavePtr save, - DisplayModePtr mode) -{ - ScrnInfoPtr pScrn = crtc->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - int format; - int hsync_start; - int hsync_wid; - int vsync_wid; - - switch (info->CurrentLayout.pixel_code) { - case 4: format = 1; break; - case 8: format = 2; break; - case 15: format = 3; break; /* 555 */ - case 16: format = 4; break; /* 565 */ - case 24: format = 5; break; /* RGB */ - case 32: format = 6; break; /* xRGB */ - default: - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Unsupported pixel depth (%d)\n", - info->CurrentLayout.bitsPerPixel); - return FALSE; - } - - save->crtc2_h_total_disp = - ((((mode->CrtcHTotal / 8) - 1) & 0x3ff) - | ((((mode->CrtcHDisplay / 8) - 1) & 0x1ff) << 16)); - - hsync_wid = (mode->CrtcHSyncEnd - mode->CrtcHSyncStart) / 8; - if (!hsync_wid) hsync_wid = 1; - hsync_start = mode->CrtcHSyncStart - 8; - - save->crtc2_h_sync_strt_wid = ((hsync_start & 0x1fff) - | ((hsync_wid & 0x3f) << 16) - | ((mode->Flags & V_NHSYNC) - ? RADEON_CRTC_H_SYNC_POL - : 0)); - - /* This works for double scan mode. */ - save->crtc2_v_total_disp = (((mode->CrtcVTotal - 1) & 0xffff) - | ((mode->CrtcVDisplay - 1) << 16)); - - vsync_wid = mode->CrtcVSyncEnd - mode->CrtcVSyncStart; - if (!vsync_wid) vsync_wid = 1; - - save->crtc2_v_sync_strt_wid = (((mode->CrtcVSyncStart - 1) & 0xfff) - | ((vsync_wid & 0x1f) << 16) - | ((mode->Flags & V_NVSYNC) - ? RADEON_CRTC2_V_SYNC_POL - : 0)); - - save->crtc2_pitch = ((pScrn->displayWidth * pScrn->bitsPerPixel) + - ((pScrn->bitsPerPixel * 8) -1)) / (pScrn->bitsPerPixel * 8); - save->crtc2_pitch |= save->crtc2_pitch << 16; - - /* check to see if TV DAC is enabled for another crtc and keep it enabled */ - if (save->crtc2_gen_cntl & RADEON_CRTC2_CRT2_ON) - save->crtc2_gen_cntl = RADEON_CRTC2_CRT2_ON; - else - save->crtc2_gen_cntl = 0; - - save->crtc2_gen_cntl |= ((format << 8) - | RADEON_CRTC2_VSYNC_DIS - | RADEON_CRTC2_HSYNC_DIS - | RADEON_CRTC2_DISP_DIS - | ((mode->Flags & V_DBLSCAN) - ? RADEON_CRTC2_DBL_SCAN_EN - : 0) - | ((mode->Flags & V_CSYNC) - ? RADEON_CRTC2_CSYNC_EN - : 0) - | ((mode->Flags & V_INTERLACE) - ? RADEON_CRTC2_INTERLACE_EN - : 0)); - - /* 200M freezes on VT switch sometimes if CRTC is disabled */ - if ((info->ChipFamily == CHIP_FAMILY_RS400) || - (info->ChipFamily == CHIP_FAMILY_RS480)) - save->crtc2_gen_cntl |= RADEON_CRTC2_EN; - - save->disp2_merge_cntl = info->SavedReg->disp2_merge_cntl; - save->disp2_merge_cntl &= ~(RADEON_DISP2_RGB_OFFSET_EN); - - save->fp_h2_sync_strt_wid = save->crtc2_h_sync_strt_wid; - save->fp_v2_sync_strt_wid = save->crtc2_v_sync_strt_wid; - - return TRUE; -} - - -/* Define PLL registers for requested video mode */ -static void -RADEONInitPLLRegisters(xf86CrtcPtr crtc, RADEONSavePtr save, - RADEONPLLPtr pll, DisplayModePtr mode, - int flags) -{ - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - ScrnInfoPtr pScrn = crtc->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - uint32_t feedback_div = 0; - uint32_t frac_fb_div = 0; - uint32_t reference_div = 0; - uint32_t post_divider = 0; - uint32_t freq = 0; - - struct { - int divider; - int bitvalue; - } *post_div, post_divs[] = { - /* From RAGE 128 VR/RAGE 128 GL Register - * Reference Manual (Technical Reference - * Manual P/N RRG-G04100-C Rev. 0.04), page - * 3-17 (PLL_DIV_[3:0]). - */ - { 1, 0 }, /* VCLK_SRC */ - { 2, 1 }, /* VCLK_SRC/2 */ - { 4, 2 }, /* VCLK_SRC/4 */ - { 8, 3 }, /* VCLK_SRC/8 */ - { 3, 4 }, /* VCLK_SRC/3 */ - { 16, 5 }, /* VCLK_SRC/16 */ - { 6, 6 }, /* VCLK_SRC/6 */ - { 12, 7 }, /* VCLK_SRC/12 */ - { 0, 0 } - }; - - - if ((flags & RADEON_PLL_USE_BIOS_DIVS) && info->UseBiosDividers) { - save->ppll_ref_div = info->RefDivider; - save->ppll_div_3 = info->FeedbackDivider | (info->PostDivider << 16); - save->htotal_cntl = 0; - return; - } - - if (xf86ReturnOptValBool(info->Options, OPTION_NEW_PLL, FALSE)) - radeon_crtc->pll_algo = RADEON_PLL_NEW; - else - radeon_crtc->pll_algo = RADEON_PLL_OLD; - - RADEONComputePLL(crtc, pll, mode->Clock, &freq, - &feedback_div, &frac_fb_div, &reference_div, &post_divider, flags); - - for (post_div = &post_divs[0]; post_div->divider; ++post_div) { - if (post_div->divider == post_divider) - break; - } - - if (!post_div->divider) { - save->pll_output_freq = freq; - post_div = &post_divs[0]; - } - - save->dot_clock_freq = freq; - save->feedback_div = feedback_div; - save->reference_div = reference_div; - save->post_div = post_divider; - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "dc=%u, of=%u, fd=%d, rd=%d, pd=%d\n", - (unsigned)save->dot_clock_freq, - (unsigned)save->pll_output_freq, - save->feedback_div, - save->reference_div, - save->post_div); - - save->ppll_ref_div = save->reference_div; - -#if defined(__powerpc__) - /* apparently programming this otherwise causes a hang??? */ - if (info->MacModel == RADEON_MAC_IBOOK) - save->ppll_div_3 = 0x000600ad; - else -#endif - save->ppll_div_3 = (save->feedback_div | (post_div->bitvalue << 16)); - - save->htotal_cntl = mode->HTotal & 0x7; - - save->vclk_ecp_cntl = (info->SavedReg->vclk_ecp_cntl & - ~RADEON_VCLK_SRC_SEL_MASK) | RADEON_VCLK_SRC_SEL_PPLLCLK; -} - -/* Define PLL2 registers for requested video mode */ -static void -RADEONInitPLL2Registers(xf86CrtcPtr crtc, RADEONSavePtr save, - RADEONPLLPtr pll, DisplayModePtr mode, - int flags) -{ - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - ScrnInfoPtr pScrn = crtc->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - uint32_t feedback_div = 0; - uint32_t frac_fb_div = 0; - uint32_t reference_div = 0; - uint32_t post_divider = 0; - uint32_t freq = 0; - - struct { - int divider; - int bitvalue; - } *post_div, post_divs[] = { - /* From RAGE 128 VR/RAGE 128 GL Register - * Reference Manual (Technical Reference - * Manual P/N RRG-G04100-C Rev. 0.04), page - * 3-17 (PLL_DIV_[3:0]). - */ - { 1, 0 }, /* VCLK_SRC */ - { 2, 1 }, /* VCLK_SRC/2 */ - { 4, 2 }, /* VCLK_SRC/4 */ - { 8, 3 }, /* VCLK_SRC/8 */ - { 3, 4 }, /* VCLK_SRC/3 */ - { 6, 6 }, /* VCLK_SRC/6 */ - { 12, 7 }, /* VCLK_SRC/12 */ - { 0, 0 } - }; - - if ((flags & RADEON_PLL_USE_BIOS_DIVS) && info->UseBiosDividers) { - save->p2pll_ref_div = info->RefDivider; - save->p2pll_div_0 = info->FeedbackDivider | (info->PostDivider << 16); - save->htotal_cntl2 = 0; - return; - } - - if (xf86ReturnOptValBool(info->Options, OPTION_NEW_PLL, FALSE)) - radeon_crtc->pll_algo = RADEON_PLL_NEW; - else - radeon_crtc->pll_algo = RADEON_PLL_OLD; - - RADEONComputePLL(crtc, pll, mode->Clock, &freq, - &feedback_div, &frac_fb_div, &reference_div, &post_divider, flags); - - for (post_div = &post_divs[0]; post_div->divider; ++post_div) { - if (post_div->divider == post_divider) - break; - } - - if (!post_div->divider) { - save->pll_output_freq_2 = freq; - post_div = &post_divs[0]; - } - - save->dot_clock_freq_2 = freq; - save->feedback_div_2 = feedback_div; - save->reference_div_2 = reference_div; - save->post_div_2 = post_divider; - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "dc=%u, of=%u, fd=%d, rd=%d, pd=%d\n", - (unsigned)save->dot_clock_freq_2, - (unsigned)save->pll_output_freq_2, - save->feedback_div_2, - save->reference_div_2, - save->post_div_2); - - save->p2pll_ref_div = save->reference_div_2; - - save->p2pll_div_0 = (save->feedback_div_2 | - (post_div->bitvalue << 16)); - - save->htotal_cntl2 = mode->HTotal & 0x7; - - save->pixclks_cntl = ((info->SavedReg->pixclks_cntl & - ~(RADEON_PIX2CLK_SRC_SEL_MASK)) | - RADEON_PIX2CLK_SRC_SEL_P2PLLCLK); -} - -static void -radeon_update_tv_routing(ScrnInfoPtr pScrn, RADEONSavePtr restore) -{ - /* pixclks_cntl controls tv clock routing */ - OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, restore->pixclks_cntl); -} - -/* Calculate display buffer watermark to prevent buffer underflow */ -void -RADEONInitDispBandwidthLegacy(ScrnInfoPtr pScrn, - DisplayModePtr mode1, int pixel_bytes1, - DisplayModePtr mode2, int pixel_bytes2) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - uint32_t temp, data, mem_trcd, mem_trp, mem_tras, mem_trbs=0; - float mem_tcas; - int k1, c; - - float MemTcas[8] = {0, 1, 2, 3, 0, 1.5, 2.5, 0.0}; - float MemTcas_rs480[8] = {0, 1, 2, 3, 0, 1.5, 2.5, 3.5}; - float MemTcas2[8] = {0, 1, 2, 3, 4, 5, 6, 7}; - float MemTrbs[8] = {1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5}; - float MemTrbs_r4xx[8] = {4, 5, 6, 7, 8, 9, 10, 11}; - - float mem_bw, peak_disp_bw; - float min_mem_eff = 0.8; - float sclk_eff, sclk_delay; - float mc_latency_mclk, mc_latency_sclk, cur_latency_mclk, cur_latency_sclk; - float disp_latency, disp_latency_overhead, disp_drain_rate = 0, disp_drain_rate2; - float pix_clk, pix_clk2; /* in MHz */ - int cur_size = 16; /* in octawords */ - int critical_point = 0, critical_point2; - int stop_req, max_stop_req; - float read_return_rate, time_disp1_drop_priority; - - /* - * Set display0/1 priority up on r3/4xx in the memory controller for - * high res modes if the user specifies HIGH for displaypriority - * option. - */ - if ((info->DispPriority == 2) && IS_R300_VARIANT) { - uint32_t mc_init_misc_lat_timer = INREG(R300_MC_INIT_MISC_LAT_TIMER); - mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT); - mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT); - if (pRADEONEnt->pCrtc[1]->enabled) - mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT); /* display 1 */ - if (pRADEONEnt->pCrtc[0]->enabled) - mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT); /* display 0 */ - OUTREG(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer); - } - - /* - * Determine if there is enough bandwidth for current display mode - */ - mem_bw = info->mclk * (info->RamWidth / 8) * (info->IsDDR ? 2 : 1); - - pix_clk = 0; - pix_clk2 = 0; - peak_disp_bw = 0; - if (mode1) { - pix_clk = mode1->Clock/1000.0; - peak_disp_bw += (pix_clk * pixel_bytes1); - } - if (mode2) { - pix_clk2 = mode2->Clock/1000.0; - peak_disp_bw += (pix_clk2 * pixel_bytes2); - } - - if (peak_disp_bw >= mem_bw * min_mem_eff) { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "You may not have enough display bandwidth for current mode\n" - "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"); - } - - /* Get values from the EXT_MEM_CNTL register...converting its contents. */ - temp = INREG(RADEON_MEM_TIMING_CNTL); - if ((info->ChipFamily == CHIP_FAMILY_RV100) || info->IsIGP) { /* RV100, M6, IGPs */ - mem_trcd = ((temp >> 2) & 0x3) + 1; - mem_trp = ((temp & 0x3)) + 1; - mem_tras = ((temp & 0x70) >> 4) + 1; - } else if (info->ChipFamily == CHIP_FAMILY_R300 || - info->ChipFamily == CHIP_FAMILY_R350) { /* r300, r350 */ - mem_trcd = (temp & 0x7) + 1; - mem_trp = ((temp >> 8) & 0x7) + 1; - mem_tras = ((temp >> 11) & 0xf) + 4; - } else if (info->ChipFamily == CHIP_FAMILY_RV350 || - info->ChipFamily <= CHIP_FAMILY_RV380) { - /* rv3x0 */ - mem_trcd = (temp & 0x7) + 3; - mem_trp = ((temp >> 8) & 0x7) + 3; - mem_tras = ((temp >> 11) & 0xf) + 6; - } else if (info->ChipFamily == CHIP_FAMILY_R420 || - info->ChipFamily == CHIP_FAMILY_RV410) { - /* r4xx */ - mem_trcd = (temp & 0xf) + 3; - if (mem_trcd > 15) - mem_trcd = 15; - mem_trp = ((temp >> 8) & 0xf) + 3; - if (mem_trp > 15) - mem_trp = 15; - mem_tras = ((temp >> 12) & 0x1f) + 6; - if (mem_tras > 31) - mem_tras = 31; - } else { /* RV200, R200 */ - mem_trcd = (temp & 0x7) + 1; - mem_trp = ((temp >> 8) & 0x7) + 1; - mem_tras = ((temp >> 12) & 0xf) + 4; - } - - /* Get values from the MEM_SDRAM_MODE_REG register...converting its */ - temp = INREG(RADEON_MEM_SDRAM_MODE_REG); - data = (temp & (7<<20)) >> 20; - if ((info->ChipFamily == CHIP_FAMILY_RV100) || info->IsIGP) { /* RV100, M6, IGPs */ - if (info->ChipFamily == CHIP_FAMILY_RS480) /* don't think rs400 */ - mem_tcas = MemTcas_rs480[data]; - else - mem_tcas = MemTcas[data]; - } else { - mem_tcas = MemTcas2 [data]; - } - if (info->ChipFamily == CHIP_FAMILY_RS400 || - info->ChipFamily == CHIP_FAMILY_RS480) { - /* extra cas latency stored in bits 23-25 0-4 clocks */ - data = (temp >> 23) & 0x7; - if (data < 5) - mem_tcas += data; - } - - if (IS_R300_VARIANT && !info->IsIGP) { - /* on the R300, Tcas is included in Trbs. - */ - temp = INREG(RADEON_MEM_CNTL); - data = (R300_MEM_NUM_CHANNELS_MASK & temp); - if (data == 1) { - if (R300_MEM_USE_CD_CH_ONLY & temp) { - temp = INREG(R300_MC_IND_INDEX); - temp &= ~R300_MC_IND_ADDR_MASK; - temp |= R300_MC_READ_CNTL_CD_mcind; - OUTREG(R300_MC_IND_INDEX, temp); - temp = INREG(R300_MC_IND_DATA); - data = (R300_MEM_RBS_POSITION_C_MASK & temp); - } else { - temp = INREG(R300_MC_READ_CNTL_AB); - data = (R300_MEM_RBS_POSITION_A_MASK & temp); - } - } else { - temp = INREG(R300_MC_READ_CNTL_AB); - data = (R300_MEM_RBS_POSITION_A_MASK & temp); - } - - if (info->ChipFamily == CHIP_FAMILY_RV410 || - info->ChipFamily == CHIP_FAMILY_R420) - mem_trbs = MemTrbs_r4xx[data]; - else - mem_trbs = MemTrbs[data]; - mem_tcas += mem_trbs; - } - - if ((info->ChipFamily == CHIP_FAMILY_RV100) || info->IsIGP) { /* RV100, M6, IGPs */ - /* DDR64 SCLK_EFF = SCLK for analysis */ - sclk_eff = info->sclk; - } else { -#ifdef XF86DRI - if (info->directRenderingEnabled) - sclk_eff = info->sclk - (info->dri->agpMode * 50.0 / 3.0); - else -#endif - sclk_eff = info->sclk; - } - - /* - Find the memory controller latency for the display client. - */ - if (IS_R300_VARIANT) { - /*not enough for R350 ???*/ - /* - if (!mode2) sclk_delay = 150; - else { - if (info->RamWidth == 256) sclk_delay = 87; - else sclk_delay = 97; - } - */ - sclk_delay = 250; - } else { - if ((info->ChipFamily == CHIP_FAMILY_RV100) || - info->IsIGP) { - if (info->IsDDR) sclk_delay = 41; - else sclk_delay = 33; - } else { - if (info->RamWidth == 128) sclk_delay = 57; - else sclk_delay = 41; - } - } - - mc_latency_sclk = sclk_delay / sclk_eff; - - if (info->IsDDR) { - if (info->RamWidth == 32) { - k1 = 40; - c = 3; - } else { - k1 = 20; - c = 1; - } - } else { - k1 = 40; - c = 3; - } - mc_latency_mclk = ((2.0*mem_trcd + mem_tcas*c + 4.0*mem_tras + 4.0*mem_trp + k1) / - info->mclk) + (4.0 / sclk_eff); - - /* - HW cursor time assuming worst case of full size colour cursor. - */ - cur_latency_mclk = (mem_trp + MAX(mem_tras, (mem_trcd + 2*(cur_size - (info->IsDDR+1))))) / info->mclk; - cur_latency_sclk = cur_size / sclk_eff; - - /* - Find the total latency for the display data. - */ - disp_latency_overhead = 8.0 / info->sclk; - mc_latency_mclk = mc_latency_mclk + disp_latency_overhead + cur_latency_mclk; - mc_latency_sclk = mc_latency_sclk + disp_latency_overhead + cur_latency_sclk; - disp_latency = MAX(mc_latency_mclk, mc_latency_sclk); - - /* setup Max GRPH_STOP_REQ default value */ - if (IS_RV100_VARIANT) - max_stop_req = 0x5c; - else - max_stop_req = 0x7c; - - if (mode1) { - /* CRTC1 - Set GRPH_BUFFER_CNTL register using h/w defined optimal values. - GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ] - */ - stop_req = mode1->HDisplay * pixel_bytes1 / 16; - - if (stop_req > max_stop_req) - stop_req = max_stop_req; - - /* - Find the drain rate of the display buffer. - */ - disp_drain_rate = pix_clk / (16.0/pixel_bytes1); - - /* - Find the critical point of the display buffer. - */ - critical_point= (uint32_t)(disp_drain_rate * disp_latency + 0.5); - - /* ???? */ - /* - temp = (info->SavedReg.grph_buffer_cntl & RADEON_GRPH_CRITICAL_POINT_MASK) >> RADEON_GRPH_CRITICAL_POINT_SHIFT; - if (critical_point < temp) critical_point = temp; - */ - if (info->DispPriority == 2) { - critical_point = 0; - } - - /* - The critical point should never be above max_stop_req-4. Setting - GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time. - */ - if (max_stop_req - critical_point < 4) critical_point = 0; - - if (critical_point == 0 && mode2 && info->ChipFamily == CHIP_FAMILY_R300) { - /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/ - critical_point = 0x10; - } - - temp = info->SavedReg->grph_buffer_cntl; - temp &= ~(RADEON_GRPH_STOP_REQ_MASK); - temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); - temp &= ~(RADEON_GRPH_START_REQ_MASK); - if ((info->ChipFamily == CHIP_FAMILY_R350) && - (stop_req > 0x15)) { - stop_req -= 0x10; - } - temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); - - temp |= RADEON_GRPH_BUFFER_SIZE; - temp &= ~(RADEON_GRPH_CRITICAL_CNTL | - RADEON_GRPH_CRITICAL_AT_SOF | - RADEON_GRPH_STOP_CNTL); - /* - Write the result into the register. - */ - OUTREG(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | - (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT))); - -#if 0 - if ((info->ChipFamily == CHIP_FAMILY_RS400) || - (info->ChipFamily == CHIP_FAMILY_RS480)) { - /* attempt to program RS400 disp regs correctly ??? */ - temp = info->SavedReg->disp1_req_cntl1; - temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK | - RS400_DISP1_STOP_REQ_LEVEL_MASK); - OUTREG(RS400_DISP1_REQ_CNTL1, (temp | - (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) | - (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); - temp = info->SavedReg->dmif_mem_cntl1; - temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK | - RS400_DISP1_CRITICAL_POINT_STOP_MASK); - OUTREG(RS400_DMIF_MEM_CNTL1, (temp | - (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) | - (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT))); - } -#endif - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "GRPH_BUFFER_CNTL from %x to %x\n", - (unsigned int)info->SavedReg->grph_buffer_cntl, - (unsigned int)INREG(RADEON_GRPH_BUFFER_CNTL)); - } - - if (mode2) { - stop_req = mode2->HDisplay * pixel_bytes2 / 16; - - if (stop_req > max_stop_req) stop_req = max_stop_req; - - /* - Find the drain rate of the display buffer. - */ - disp_drain_rate2 = pix_clk2 / (16.0/pixel_bytes2); - - temp = info->SavedReg->grph2_buffer_cntl; - temp &= ~(RADEON_GRPH_STOP_REQ_MASK); - temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); - temp &= ~(RADEON_GRPH_START_REQ_MASK); - if ((info->ChipFamily == CHIP_FAMILY_R350) && - (stop_req > 0x15)) { - stop_req -= 0x10; - } - temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); - temp |= RADEON_GRPH_BUFFER_SIZE; - temp &= ~(RADEON_GRPH_CRITICAL_CNTL | - RADEON_GRPH_CRITICAL_AT_SOF | - RADEON_GRPH_STOP_CNTL); - - if ((info->ChipFamily == CHIP_FAMILY_RS100) || - (info->ChipFamily == CHIP_FAMILY_RS200)) - critical_point2 = 0; - else { - read_return_rate = MIN(info->sclk, info->mclk*(info->RamWidth*(info->IsDDR+1)/128)); - if (mode1) - time_disp1_drop_priority = critical_point / (read_return_rate - disp_drain_rate); - else - time_disp1_drop_priority = 0; - - critical_point2 = (uint32_t)((disp_latency + time_disp1_drop_priority + - disp_latency) * disp_drain_rate2 + 0.5); - - if (info->DispPriority == 2) { - critical_point2 = 0; - } - - if (max_stop_req - critical_point2 < 4) critical_point2 = 0; - - } - - if (critical_point2 == 0 && info->ChipFamily == CHIP_FAMILY_R300) { - /* some R300 cards have problem with this set to 0 */ - critical_point2 = 0x10; - } - - OUTREG(RADEON_GRPH2_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | - (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT))); - - if ((info->ChipFamily == CHIP_FAMILY_RS400) || - (info->ChipFamily == CHIP_FAMILY_RS480)) { -#if 0 - /* attempt to program RS400 disp2 regs correctly ??? */ - temp = info->SavedReg->disp2_req_cntl1; - temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK | - RS400_DISP2_STOP_REQ_LEVEL_MASK); - OUTREG(RS400_DISP2_REQ_CNTL1, (temp | - (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) | - (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); - temp = info->SavedReg->disp2_req_cntl2; - temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK | - RS400_DISP2_CRITICAL_POINT_STOP_MASK); - OUTREG(RS400_DISP2_REQ_CNTL2, (temp | - (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) | - (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT))); -#endif - OUTREG(RS400_DISP2_REQ_CNTL1, 0x105DC1CC); - OUTREG(RS400_DISP2_REQ_CNTL2, 0x2749D000); - OUTREG(RS400_DMIF_MEM_CNTL1, 0x29CA71DC); - OUTREG(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC); - } - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "GRPH2_BUFFER_CNTL from %x to %x\n", - (unsigned int)info->SavedReg->grph2_buffer_cntl, - (unsigned int)INREG(RADEON_GRPH2_BUFFER_CNTL)); - } -} - -void -legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, - DisplayModePtr adjusted_mode, int x, int y) -{ - ScrnInfoPtr pScrn = crtc->scrn; - xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - RADEONInfoPtr info = RADEONPTR(pScrn); - int i = 0; - double dot_clock = 0; - int pll_flags = RADEON_PLL_LEGACY; - Bool update_tv_routing = FALSE; - Bool tilingChanged = FALSE; - - if (adjusted_mode->Clock > 200000) /* range limits??? */ - pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; - else - pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; - - if (info->allowColorTiling) { - radeon_crtc->can_tile = (adjusted_mode->Flags & (V_DBLSCAN | V_INTERLACE)) ? FALSE : TRUE; - tilingChanged = RADEONSetTiling(pScrn); - } - - for (i = 0; i < xf86_config->num_output; i++) { - xf86OutputPtr output = xf86_config->output[i]; - RADEONOutputPrivatePtr radeon_output = output->driver_private; - - if (output->crtc == crtc) { - if (radeon_output->active_device & (ATOM_DEVICE_LCD_SUPPORT | - ATOM_DEVICE_DFP_SUPPORT)) - pll_flags |= RADEON_PLL_NO_ODD_POST_DIV; - if (radeon_output->active_device & (ATOM_DEVICE_LCD_SUPPORT)) - pll_flags |= (RADEON_PLL_USE_BIOS_DIVS | RADEON_PLL_USE_REF_DIV); - } - } - - - ErrorF("init memmap\n"); - RADEONInitMemMapRegisters(pScrn, info->ModeReg, info); - ErrorF("init common\n"); - RADEONInitCommonRegisters(info->ModeReg, info); - - RADEONInitSurfaceCntl(crtc, info->ModeReg); - - switch (radeon_crtc->crtc_id) { - case 0: - ErrorF("init crtc1\n"); - RADEONInitCrtcRegisters(crtc, info->ModeReg, adjusted_mode); - RADEONInitCrtcBase(crtc, info->ModeReg, x, y); - dot_clock = adjusted_mode->Clock / 1000.0; - if (dot_clock) { - ErrorF("init pll1\n"); - RADEONInitPLLRegisters(crtc, info->ModeReg, &info->pll, adjusted_mode, pll_flags); - } else { - info->ModeReg->ppll_ref_div = info->SavedReg->ppll_ref_div; - info->ModeReg->ppll_div_3 = info->SavedReg->ppll_div_3; - info->ModeReg->htotal_cntl = info->SavedReg->htotal_cntl; - } - break; - case 1: - ErrorF("init crtc2\n"); - RADEONInitCrtc2Registers(crtc, info->ModeReg, adjusted_mode); - RADEONInitCrtc2Base(crtc, info->ModeReg, x, y); - dot_clock = adjusted_mode->Clock / 1000.0; - if (dot_clock) { - ErrorF("init pll2\n"); - RADEONInitPLL2Registers(crtc, info->ModeReg, &info->pll, adjusted_mode, pll_flags); - } - break; - } - - for (i = 0; i < xf86_config->num_output; i++) { - xf86OutputPtr output = xf86_config->output[i]; - RADEONOutputPrivatePtr radeon_output = output->driver_private; - - if (output->crtc == crtc) { - if (radeon_output->active_device & (ATOM_DEVICE_TV_SUPPORT)) { - switch (radeon_crtc->crtc_id) { - case 0: - RADEONAdjustCrtcRegistersForTV(pScrn, info->ModeReg, adjusted_mode, output); - RADEONAdjustPLLRegistersForTV(pScrn, info->ModeReg, adjusted_mode, output); - update_tv_routing = TRUE; - break; - case 1: - RADEONAdjustCrtc2RegistersForTV(pScrn, info->ModeReg, adjusted_mode, output); - RADEONAdjustPLL2RegistersForTV(pScrn, info->ModeReg, adjusted_mode, output); - break; - } - } - } - } - - ErrorF("restore memmap\n"); - RADEONRestoreMemMapRegisters(pScrn, info->ModeReg); - ErrorF("restore common\n"); - RADEONRestoreCommonRegisters(pScrn, info->ModeReg); - - switch (radeon_crtc->crtc_id) { - case 0: - ErrorF("restore crtc1\n"); - RADEONRestoreCrtcRegisters(pScrn, info->ModeReg); - ErrorF("restore pll1\n"); - RADEONRestorePLLRegisters(pScrn, info->ModeReg); - break; - case 1: - ErrorF("restore crtc2\n"); - RADEONRestoreCrtc2Registers(pScrn, info->ModeReg); - ErrorF("restore pll2\n"); - RADEONRestorePLL2Registers(pScrn, info->ModeReg); - break; - } - - /* pixclks_cntl handles tv-out clock routing */ - if (update_tv_routing) - radeon_update_tv_routing(pScrn, info->ModeReg); - - if (info->DispPriority) - RADEONInitDispBandwidth(pScrn); - - radeon_crtc->initialized = TRUE; - - if (tilingChanged) { - /* need to redraw front buffer, I guess this can be considered a hack ? */ - /* if this is called during ScreenInit() we don't have pScrn->pScreen yet */ - if (pScrn->pScreen) - xf86EnableDisableFBAccess(XF86_ENABLEDISABLEFB_ARG(pScrn), FALSE); - RADEONChangeSurfaces(pScrn); - if (pScrn->pScreen) - xf86EnableDisableFBAccess(XF86_ENABLEDISABLEFB_ARG(pScrn), TRUE); - /* xf86SetRootClip would do, but can't access that here */ - } - - /* reset ecp_div for Xv */ - info->ecp_div = -1; - -} - diff --git a/src/legacy_output.c b/src/legacy_output.c deleted file mode 100644 index d7b79e2e..00000000 --- a/src/legacy_output.c +++ /dev/null @@ -1,2102 +0,0 @@ -/* - * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and - * VA Linux Systems Inc., Fremont, California. - * - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation on the rights to use, copy, modify, merge, - * publish, distribute, sublicense, and/or sell copies of the Software, - * and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR - * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include <string.h> -#include <stdio.h> - -/* X and server generic header files */ -#include "xf86.h" -#include "xf86_OSproc.h" -#include "vgaHW.h" -#include "xf86Modes.h" - -/* Driver data structures */ -#include "radeon.h" -#include "radeon_reg.h" -#include "radeon_macros.h" -#include "radeon_probe.h" -#include "radeon_version.h" -#include "radeon_tv.h" -#include "radeon_atombios.h" - -#include "ati_pciids_gen.h" - -static RADEONMonitorType radeon_detect_tv(ScrnInfoPtr pScrn); -static RADEONMonitorType radeon_detect_primary_dac(ScrnInfoPtr pScrn, Bool color); -static RADEONMonitorType radeon_detect_tv_dac(ScrnInfoPtr pScrn, Bool color); -static RADEONMonitorType radeon_detect_ext_dac(ScrnInfoPtr pScrn); - -extern Bool -RADEONI2CInit(ScrnInfoPtr pScrn, I2CBusPtr *bus_ptr, char *name, RADEONI2CBusPtr pRADEONI2CBus); - -static const RADEONTMDSPll default_tmds_pll[CHIP_FAMILY_LAST][4] = -{ - {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_UNKNOW*/ - {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_LEGACY*/ - {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RADEON*/ - {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RV100*/ - {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RS100*/ - {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RV200*/ - {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RS200*/ - {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_R200*/ - {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RV250*/ - {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RS300*/ - {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /*CHIP_FAMILY_RV280*/ - {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_R300*/ - {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_R350*/ - {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RV350*/ - {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RV380*/ - {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_R420*/ - {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RV410*/ /* FIXME: just values from r420 used... */ - {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RS400*/ /* FIXME: just values from rv380 used... */ - {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RS480*/ /* FIXME: just values from rv380 used... */ -}; - -static const uint32_t default_tvdac_adj [CHIP_FAMILY_LAST] = -{ - 0x00000000, /* unknown */ - 0x00000000, /* legacy */ - 0x00000000, /* r100 */ - 0x00280000, /* rv100 */ - 0x00000000, /* rs100 */ - 0x00880000, /* rv200 */ - 0x00000000, /* rs200 */ - 0x00000000, /* r200 */ - 0x00770000, /* rv250 */ - 0x00290000, /* rs300 */ - 0x00560000, /* rv280 */ - 0x00780000, /* r300 */ - 0x00770000, /* r350 */ - 0x00780000, /* rv350 */ - 0x00780000, /* rv380 */ - 0x01080000, /* r420 */ - 0x01080000, /* rv410 */ /* FIXME: just values from r420 used... */ - 0x00780000, /* rs400 */ /* FIXME: just values from rv380 used... */ - 0x00780000, /* rs480 */ /* FIXME: just values from rv380 used... */ -}; - -void -RADEONGetTVDacAdjInfo(ScrnInfoPtr pScrn, radeon_tvdac_ptr tvdac) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - - if (!RADEONGetDAC2InfoFromBIOS(pScrn, tvdac)) { - tvdac->ps2_tvdac_adj = default_tvdac_adj[info->ChipFamily]; - if (info->IsMobility) { /* some mobility chips may different */ - if (info->ChipFamily == CHIP_FAMILY_RV250) - tvdac->ps2_tvdac_adj = 0x00880000; - } - tvdac->pal_tvdac_adj = tvdac->ps2_tvdac_adj; - tvdac->ntsc_tvdac_adj = tvdac->ps2_tvdac_adj; - } -} - -void -RADEONGetTMDSInfoFromTable(ScrnInfoPtr pScrn, radeon_tmds_ptr tmds) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - int i; - - for (i = 0; i < 4; i++) { - tmds->tmds_pll[i].value = default_tmds_pll[info->ChipFamily][i].value; - tmds->tmds_pll[i].freq = default_tmds_pll[info->ChipFamily][i].freq; - } -} - -void -RADEONGetTMDSInfo(ScrnInfoPtr pScrn, radeon_tmds_ptr tmds) -{ - int i; - - for (i = 0; i < 4; i++) { - tmds->tmds_pll[i].value = 0; - tmds->tmds_pll[i].freq = 0; - } - - if (!RADEONGetTMDSInfoFromBIOS(pScrn, tmds)) - RADEONGetTMDSInfoFromTable(pScrn, tmds); -} - -void -RADEONGetExtTMDSInfo(ScrnInfoPtr pScrn, radeon_dvo_ptr dvo) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - - if (!info->IsAtomBios) { -#if defined(__powerpc__) - dvo->dvo_i2c = legacy_setup_i2c_bus(RADEON_GPIO_MONID); - dvo->dvo_i2c_slave_addr = 0x70; -#else - if (!RADEONGetExtTMDSInfoFromBIOS(pScrn, dvo)) { - dvo->dvo_i2c = legacy_setup_i2c_bus(RADEON_GPIO_CRT2_DDC); - dvo->dvo_i2c_slave_addr = 0x70; - } -#endif - if (RADEONI2CInit(pScrn, &dvo->pI2CBus, "DVO", &dvo->dvo_i2c)) { - dvo->DVOChip = - RADEONDVODeviceInit(dvo->pI2CBus, dvo->dvo_i2c_slave_addr); - if (!dvo->DVOChip) - free(dvo->pI2CBus); - } - } -} - -static void -RADEONGetPanelInfoFromReg (ScrnInfoPtr pScrn, radeon_lvds_ptr lvds) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - radeon_native_mode_ptr native_mode = &lvds->native_mode; - uint32_t fp_vert_stretch = INREG(RADEON_FP_VERT_STRETCH); - uint32_t fp_horz_stretch = INREG(RADEON_FP_HORZ_STRETCH); - - lvds->PanelPwrDly = 200; - if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE) { - native_mode->PanelYRes = ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >> - RADEON_VERT_PANEL_SHIFT) + 1; - } else { - native_mode->PanelYRes = (INREG(RADEON_CRTC_V_TOTAL_DISP)>>16) + 1; - } - if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE) { - native_mode->PanelXRes = (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >> - RADEON_HORZ_PANEL_SHIFT) + 1) * 8; - } else { - native_mode->PanelXRes = ((INREG(RADEON_CRTC_H_TOTAL_DISP)>>16) + 1) * 8; - } - - if ((native_mode->PanelXRes < 640) || (native_mode->PanelYRes < 480)) { - native_mode->PanelXRes = 640; - native_mode->PanelYRes = 480; - } - - // move this to crtc function - if (xf86ReturnOptValBool(info->Options, OPTION_LVDS_PROBE_PLL, TRUE)) { - uint32_t ppll_div_sel, ppll_val; - - ppll_div_sel = INREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3; - RADEONPllErrataAfterIndex(info); - ppll_val = INPLL(pScrn, RADEON_PPLL_DIV_0 + ppll_div_sel); - if ((ppll_val & 0x000707ff) == 0x1bb) - goto noprobe; - info->FeedbackDivider = ppll_val & 0x7ff; - info->PostDivider = (ppll_val >> 16) & 0x7; - info->RefDivider = info->pll.reference_div; - info->UseBiosDividers = TRUE; - - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Existing panel PLL dividers will be used.\n"); - } - noprobe: - - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "Panel size %dx%d is derived, this may not be correct.\n" - "If not, use PanelSize option to overwrite this setting\n", - native_mode->PanelXRes, native_mode->PanelYRes); -} - -void -RADEONGetLVDSInfo (ScrnInfoPtr pScrn, radeon_lvds_ptr lvds) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - radeon_native_mode_ptr native_mode = &lvds->native_mode; - char* s; - - if (!RADEONGetLVDSInfoFromBIOS(pScrn, lvds)) - RADEONGetPanelInfoFromReg(pScrn, lvds); - - if ((s = xf86GetOptValString(info->Options, OPTION_PANEL_SIZE))) { - lvds->PanelPwrDly = 200; - if (sscanf (s, "%dx%d", &native_mode->PanelXRes, &native_mode->PanelYRes) != 2) { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Invalid PanelSize option: %s\n", s); - RADEONGetPanelInfoFromReg(pScrn, lvds); - } - } -} - -void -RADEONRestoreDACRegisters(ScrnInfoPtr pScrn, - RADEONSavePtr restore) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - if (IS_R300_VARIANT) - OUTREGP(RADEON_GPIOPAD_A, restore->gpiopad_a, ~1); - - OUTREGP(RADEON_DAC_CNTL, - restore->dac_cntl, - RADEON_DAC_RANGE_CNTL | - RADEON_DAC_BLANKING); - - OUTREG(RADEON_DAC_CNTL2, restore->dac2_cntl); - - if ((info->ChipFamily != CHIP_FAMILY_RADEON) && - (info->ChipFamily != CHIP_FAMILY_R200)) - OUTREG (RADEON_TV_DAC_CNTL, restore->tv_dac_cntl); - - OUTREG(RADEON_DISP_OUTPUT_CNTL, restore->disp_output_cntl); - - if ((info->ChipFamily == CHIP_FAMILY_R200) || - IS_R300_VARIANT) { - OUTREG(RADEON_DISP_TV_OUT_CNTL, restore->disp_tv_out_cntl); - } else { - OUTREG(RADEON_DISP_HW_DEBUG, restore->disp_hw_debug); - } - - OUTREG(RADEON_DAC_MACRO_CNTL, restore->dac_macro_cntl); - - /* R200 DAC connected via DVO */ - if (info->ChipFamily == CHIP_FAMILY_R200) - OUTREG(RADEON_FP2_GEN_CNTL, restore->fp2_gen_cntl); -} - - -/* Write TMDS registers */ -void -RADEONRestoreFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - OUTREG(RADEON_TMDS_PLL_CNTL, restore->tmds_pll_cntl); - OUTREG(RADEON_TMDS_TRANSMITTER_CNTL,restore->tmds_transmitter_cntl); - OUTREG(RADEON_FP_GEN_CNTL, restore->fp_gen_cntl); - - if ((info->ChipFamily == CHIP_FAMILY_RS400) || - (info->ChipFamily == CHIP_FAMILY_RS480)) { - OUTREG(RS400_FP_2ND_GEN_CNTL, restore->fp_2nd_gen_cntl); - /*OUTREG(RS400_TMDS2_CNTL, restore->tmds2_cntl);*/ - OUTREG(RS400_TMDS2_TRANSMITTER_CNTL, restore->tmds2_transmitter_cntl); - } - - /* old AIW Radeon has some BIOS initialization problem - * with display buffer underflow, only occurs to DFP - */ - if (!pRADEONEnt->HasCRTC2) - OUTREG(RADEON_GRPH_BUFFER_CNTL, - INREG(RADEON_GRPH_BUFFER_CNTL) & ~0x7f0000); - -} - -/* Write FP2 registers */ -void -RADEONRestoreFP2Registers(ScrnInfoPtr pScrn, RADEONSavePtr restore) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - OUTREG(RADEON_FP2_GEN_CNTL, restore->fp2_gen_cntl); - - if ((info->ChipFamily == CHIP_FAMILY_RS400) || - (info->ChipFamily == CHIP_FAMILY_RS480)) - OUTREG(RS400_FP2_2_GEN_CNTL, restore->fp2_2_gen_cntl); -} - -/* Write RMX registers */ -void -RADEONRestoreRMXRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - OUTREG(RADEON_FP_HORZ_STRETCH, restore->fp_horz_stretch); - OUTREG(RADEON_FP_VERT_STRETCH, restore->fp_vert_stretch); - OUTREG(RADEON_CRTC_MORE_CNTL, restore->crtc_more_cntl); - OUTREG(RADEON_FP_HORZ_VERT_ACTIVE, restore->fp_horz_vert_active); - OUTREG(RADEON_FP_H_SYNC_STRT_WID, restore->fp_h_sync_strt_wid); - OUTREG(RADEON_FP_V_SYNC_STRT_WID, restore->fp_v_sync_strt_wid); - OUTREG(RADEON_FP_CRTC_H_TOTAL_DISP, restore->fp_crtc_h_total_disp); - OUTREG(RADEON_FP_CRTC_V_TOTAL_DISP, restore->fp_crtc_v_total_disp); - -} - -/* Write LVDS registers */ -void -RADEONRestoreLVDSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - if (info->IsMobility) { - OUTREG(RADEON_LVDS_GEN_CNTL, restore->lvds_gen_cntl); - /*OUTREG(RADEON_LVDS_PLL_CNTL, restore->lvds_pll_cntl);*/ - - if (info->ChipFamily == CHIP_FAMILY_RV410) { - OUTREG(RADEON_CLOCK_CNTL_INDEX, 0); - } - } - -} - -void -RADEONSaveDACRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - save->dac_cntl = INREG(RADEON_DAC_CNTL); - save->dac2_cntl = INREG(RADEON_DAC_CNTL2); - save->tv_dac_cntl = INREG(RADEON_TV_DAC_CNTL); - save->disp_output_cntl = INREG(RADEON_DISP_OUTPUT_CNTL); - save->disp_tv_out_cntl = INREG(RADEON_DISP_TV_OUT_CNTL); - save->disp_hw_debug = INREG(RADEON_DISP_HW_DEBUG); - save->dac_macro_cntl = INREG(RADEON_DAC_MACRO_CNTL); - save->gpiopad_a = INREG(RADEON_GPIOPAD_A); - -} - -/* Read flat panel registers */ -void -RADEONSaveFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - save->fp_gen_cntl = INREG(RADEON_FP_GEN_CNTL); - save->fp2_gen_cntl = INREG (RADEON_FP2_GEN_CNTL); - save->fp_horz_stretch = INREG(RADEON_FP_HORZ_STRETCH); - save->fp_vert_stretch = INREG(RADEON_FP_VERT_STRETCH); - save->fp_horz_vert_active = INREG(RADEON_FP_HORZ_VERT_ACTIVE); - save->crtc_more_cntl = INREG(RADEON_CRTC_MORE_CNTL); - save->lvds_gen_cntl = INREG(RADEON_LVDS_GEN_CNTL); - save->lvds_pll_cntl = INREG(RADEON_LVDS_PLL_CNTL); - save->tmds_pll_cntl = INREG(RADEON_TMDS_PLL_CNTL); - save->tmds_transmitter_cntl= INREG(RADEON_TMDS_TRANSMITTER_CNTL); - - save->fp_h_sync_strt_wid = INREG(RADEON_FP_H_SYNC_STRT_WID); - save->fp_v_sync_strt_wid = INREG(RADEON_FP_V_SYNC_STRT_WID); - save->fp_crtc_h_total_disp = INREG(RADEON_FP_CRTC_H_TOTAL_DISP); - save->fp_crtc_v_total_disp = INREG(RADEON_FP_CRTC_V_TOTAL_DISP); - - if (info->ChipFamily == CHIP_FAMILY_RV280) { - /* bit 22 of TMDS_PLL_CNTL is read-back inverted */ - save->tmds_pll_cntl ^= (1 << 22); - } - - if ((info->ChipFamily == CHIP_FAMILY_RS400) || - (info->ChipFamily == CHIP_FAMILY_RS480)) { - save->fp_2nd_gen_cntl = INREG(RS400_FP_2ND_GEN_CNTL); - save->fp2_2_gen_cntl = INREG(RS400_FP2_2_GEN_CNTL); - save->tmds2_cntl = INREG(RS400_TMDS2_CNTL); - save->tmds2_transmitter_cntl = INREG(RS400_TMDS2_TRANSMITTER_CNTL); - } - -} - -Bool -RADEONDVOReadByte(I2CDevPtr dvo, int addr, uint8_t *ch) -{ - if (!xf86I2CReadByte(dvo, addr, ch)) { - xf86DrvMsg(dvo->pI2CBus->scrnIndex, X_ERROR, - "Unable to read from %s Slave %d.\n", - dvo->pI2CBus->BusName, dvo->SlaveAddr); - return FALSE; - } - return TRUE; -} - -Bool -RADEONDVOWriteByte(I2CDevPtr dvo, int addr, uint8_t ch) -{ - if (!xf86I2CWriteByte(dvo, addr, ch)) { - xf86DrvMsg(dvo->pI2CBus->scrnIndex, X_ERROR, - "Unable to write to %s Slave %d.\n", - dvo->pI2CBus->BusName, dvo->SlaveAddr); - return FALSE; - } - return TRUE; -} - -I2CDevPtr -RADEONDVODeviceInit(I2CBusPtr b, I2CSlaveAddr addr) -{ - I2CDevPtr dvo; - - dvo = calloc(1, sizeof(I2CDevRec)); - if (dvo == NULL) - return NULL; - - dvo->DevName = "RADEON DVO Controller"; - dvo->SlaveAddr = addr; - dvo->pI2CBus = b; - dvo->StartTimeout = b->StartTimeout; - dvo->BitTimeout = b->BitTimeout; - dvo->AcknTimeout = b->AcknTimeout; - dvo->ByteTimeout = b->ByteTimeout; - - if (xf86I2CDevInit(dvo)) { - return dvo; - } - - free(dvo); - return NULL; -} - -static void -RADEONRestoreDVOChip(ScrnInfoPtr pScrn, xf86OutputPtr output) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - radeon_encoder_ptr radeon_encoder = radeon_get_encoder(output); - radeon_dvo_ptr dvo = NULL; - - if (radeon_encoder == NULL) - return; - - dvo = (radeon_dvo_ptr)radeon_encoder->dev_priv; - - if (dvo == NULL) - return; - - if (!dvo->DVOChip) - return; - - RADEONI2CDoLock(output, dvo->pI2CBus, TRUE); - if (!RADEONInitExtTMDSInfoFromBIOS(output)) { - if (dvo->DVOChip) { - switch(info->ext_tmds_chip) { - case RADEON_SIL_164: - RADEONDVOWriteByte(dvo->DVOChip, 0x08, 0x30); - RADEONDVOWriteByte(dvo->DVOChip, 0x09, 0x00); - RADEONDVOWriteByte(dvo->DVOChip, 0x0a, 0x90); - RADEONDVOWriteByte(dvo->DVOChip, 0x0c, 0x89); - RADEONDVOWriteByte(dvo->DVOChip, 0x08, 0x3b); - break; -#if 0 - /* needs work see bug 10418 */ - case RADEON_SIL_1178: - RADEONDVOWriteByte(dvo->DVOChip, 0x0f, 0x44); - RADEONDVOWriteByte(dvo->DVOChip, 0x0f, 0x4c); - RADEONDVOWriteByte(dvo->DVOChip, 0x0e, 0x01); - RADEONDVOWriteByte(dvo->DVOChip, 0x0a, 0x80); - RADEONDVOWriteByte(dvo->DVOChip, 0x09, 0x30); - RADEONDVOWriteByte(dvo->DVOChip, 0x0c, 0xc9); - RADEONDVOWriteByte(dvo->DVOChip, 0x0d, 0x70); - RADEONDVOWriteByte(dvo->DVOChip, 0x08, 0x32); - RADEONDVOWriteByte(dvo->DVOChip, 0x08, 0x33); - break; -#endif - default: - break; - } - } - } - RADEONI2CDoLock(output, dvo->pI2CBus, FALSE); -} - -#if 0 -static RADEONMonitorType -RADEONCrtIsPhysicallyConnected(ScrnInfoPtr pScrn, int IsCrtDac) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - int bConnected = 0; - - /* the monitor either wasn't connected or it is a non-DDC CRT. - * try to probe it - */ - if(IsCrtDac) { - unsigned long ulOrigVCLK_ECP_CNTL; - unsigned long ulOrigDAC_CNTL; - unsigned long ulOrigDAC_MACRO_CNTL; - unsigned long ulOrigDAC_EXT_CNTL; - unsigned long ulOrigCRTC_EXT_CNTL; - unsigned long ulData; - unsigned long ulMask; - - ulOrigVCLK_ECP_CNTL = INPLL(pScrn, RADEON_VCLK_ECP_CNTL); - - ulData = ulOrigVCLK_ECP_CNTL; - ulData &= ~(RADEON_PIXCLK_ALWAYS_ONb - | RADEON_PIXCLK_DAC_ALWAYS_ONb); - ulMask = ~(RADEON_PIXCLK_ALWAYS_ONb - |RADEON_PIXCLK_DAC_ALWAYS_ONb); - OUTPLLP(pScrn, RADEON_VCLK_ECP_CNTL, ulData, ulMask); - - ulOrigCRTC_EXT_CNTL = INREG(RADEON_CRTC_EXT_CNTL); - ulData = ulOrigCRTC_EXT_CNTL; - ulData |= RADEON_CRTC_CRT_ON; - OUTREG(RADEON_CRTC_EXT_CNTL, ulData); - - ulOrigDAC_EXT_CNTL = INREG(RADEON_DAC_EXT_CNTL); - ulData = ulOrigDAC_EXT_CNTL; - ulData &= ~RADEON_DAC_FORCE_DATA_MASK; - ulData |= (RADEON_DAC_FORCE_BLANK_OFF_EN - |RADEON_DAC_FORCE_DATA_EN - |RADEON_DAC_FORCE_DATA_SEL_MASK); - if ((info->ChipFamily == CHIP_FAMILY_RV250) || - (info->ChipFamily == CHIP_FAMILY_RV280)) - ulData |= (0x01b6 << RADEON_DAC_FORCE_DATA_SHIFT); - else - ulData |= (0x01ac << RADEON_DAC_FORCE_DATA_SHIFT); - - OUTREG(RADEON_DAC_EXT_CNTL, ulData); - - /* turn on power so testing can go through */ - ulOrigDAC_CNTL = INREG(RADEON_DAC_CNTL); - ulOrigDAC_CNTL &= ~RADEON_DAC_PDWN; - OUTREG(RADEON_DAC_CNTL, ulOrigDAC_CNTL); - - ulOrigDAC_MACRO_CNTL = INREG(RADEON_DAC_MACRO_CNTL); - ulOrigDAC_MACRO_CNTL &= ~(RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G | - RADEON_DAC_PDWN_B); - OUTREG(RADEON_DAC_MACRO_CNTL, ulOrigDAC_MACRO_CNTL); - - /* Enable comparators and set DAC range to PS2 (VGA) output level */ - ulData = ulOrigDAC_CNTL; - ulData |= RADEON_DAC_CMP_EN; - ulData &= ~RADEON_DAC_RANGE_CNTL_MASK; - ulData |= 0x2; - OUTREG(RADEON_DAC_CNTL, ulData); - - /* Settle down */ - usleep(10000); - - /* Read comparators */ - ulData = INREG(RADEON_DAC_CNTL); - bConnected = (RADEON_DAC_CMP_OUTPUT & ulData)?1:0; - - /* Restore things */ - ulData = ulOrigVCLK_ECP_CNTL; - ulMask = 0xFFFFFFFFL; - OUTPLLP(pScrn, RADEON_VCLK_ECP_CNTL, ulData, ulMask); - - OUTREG(RADEON_DAC_CNTL, ulOrigDAC_CNTL ); - OUTREG(RADEON_DAC_EXT_CNTL, ulOrigDAC_EXT_CNTL ); - OUTREG(RADEON_CRTC_EXT_CNTL, ulOrigCRTC_EXT_CNTL); - - if (!bConnected) { - /* Power DAC down if CRT is not connected */ - ulOrigDAC_MACRO_CNTL = INREG(RADEON_DAC_MACRO_CNTL); - ulOrigDAC_MACRO_CNTL |= (RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G | - RADEON_DAC_PDWN_B); - OUTREG(RADEON_DAC_MACRO_CNTL, ulOrigDAC_MACRO_CNTL); - - ulData = INREG(RADEON_DAC_CNTL); - ulData |= RADEON_DAC_PDWN; - OUTREG(RADEON_DAC_CNTL, ulData); - } - } else { /* TV DAC */ - - /* This doesn't seem to work reliably (maybe worse on some OEM cards), - for now we always return false. If one wants to connected a - non-DDC monitor on the DVI port when CRT port is also connected, - he will need to explicitly tell the driver in the config file - with Option MonitorLayout. - */ - bConnected = FALSE; - -#if 0 - if (info->ChipFamily == CHIP_FAMILY_R200) { - unsigned long ulOrigGPIO_MONID; - unsigned long ulOrigFP2_GEN_CNTL; - unsigned long ulOrigDISP_OUTPUT_CNTL; - unsigned long ulOrigCRTC2_GEN_CNTL; - unsigned long ulOrigDISP_LIN_TRANS_GRPH_A; - unsigned long ulOrigDISP_LIN_TRANS_GRPH_B; - unsigned long ulOrigDISP_LIN_TRANS_GRPH_C; - unsigned long ulOrigDISP_LIN_TRANS_GRPH_D; - unsigned long ulOrigDISP_LIN_TRANS_GRPH_E; - unsigned long ulOrigDISP_LIN_TRANS_GRPH_F; - unsigned long ulOrigCRTC2_H_TOTAL_DISP; - unsigned long ulOrigCRTC2_V_TOTAL_DISP; - unsigned long ulOrigCRTC2_H_SYNC_STRT_WID; - unsigned long ulOrigCRTC2_V_SYNC_STRT_WID; - unsigned long ulData, i; - - ulOrigGPIO_MONID = INREG(RADEON_GPIO_MONID); - ulOrigFP2_GEN_CNTL = INREG(RADEON_FP2_GEN_CNTL); - ulOrigDISP_OUTPUT_CNTL = INREG(RADEON_DISP_OUTPUT_CNTL); - ulOrigCRTC2_GEN_CNTL = INREG(RADEON_CRTC2_GEN_CNTL); - ulOrigDISP_LIN_TRANS_GRPH_A = INREG(RADEON_DISP_LIN_TRANS_GRPH_A); - ulOrigDISP_LIN_TRANS_GRPH_B = INREG(RADEON_DISP_LIN_TRANS_GRPH_B); - ulOrigDISP_LIN_TRANS_GRPH_C = INREG(RADEON_DISP_LIN_TRANS_GRPH_C); - ulOrigDISP_LIN_TRANS_GRPH_D = INREG(RADEON_DISP_LIN_TRANS_GRPH_D); - ulOrigDISP_LIN_TRANS_GRPH_E = INREG(RADEON_DISP_LIN_TRANS_GRPH_E); - ulOrigDISP_LIN_TRANS_GRPH_F = INREG(RADEON_DISP_LIN_TRANS_GRPH_F); - - ulOrigCRTC2_H_TOTAL_DISP = INREG(RADEON_CRTC2_H_TOTAL_DISP); - ulOrigCRTC2_V_TOTAL_DISP = INREG(RADEON_CRTC2_V_TOTAL_DISP); - ulOrigCRTC2_H_SYNC_STRT_WID = INREG(RADEON_CRTC2_H_SYNC_STRT_WID); - ulOrigCRTC2_V_SYNC_STRT_WID = INREG(RADEON_CRTC2_V_SYNC_STRT_WID); - - ulData = INREG(RADEON_GPIO_MONID); - ulData &= ~RADEON_GPIO_A_0; - OUTREG(RADEON_GPIO_MONID, ulData); - - OUTREG(RADEON_FP2_GEN_CNTL, 0x0a000c0c); - - OUTREG(RADEON_DISP_OUTPUT_CNTL, 0x00000012); - - OUTREG(RADEON_CRTC2_GEN_CNTL, 0x06000000); - OUTREG(RADEON_DISP_LIN_TRANS_GRPH_A, 0x00000000); - OUTREG(RADEON_DISP_LIN_TRANS_GRPH_B, 0x000003f0); - OUTREG(RADEON_DISP_LIN_TRANS_GRPH_C, 0x00000000); - OUTREG(RADEON_DISP_LIN_TRANS_GRPH_D, 0x000003f0); - OUTREG(RADEON_DISP_LIN_TRANS_GRPH_E, 0x00000000); - OUTREG(RADEON_DISP_LIN_TRANS_GRPH_F, 0x000003f0); - OUTREG(RADEON_CRTC2_H_TOTAL_DISP, 0x01000008); - OUTREG(RADEON_CRTC2_H_SYNC_STRT_WID, 0x00000800); - OUTREG(RADEON_CRTC2_V_TOTAL_DISP, 0x00080001); - OUTREG(RADEON_CRTC2_V_SYNC_STRT_WID, 0x00000080); - - for (i = 0; i < 200; i++) { - ulData = INREG(RADEON_GPIO_MONID); - bConnected = (ulData & RADEON_GPIO_Y_0)?1:0; - if (!bConnected) break; - - usleep(1000); - } - - OUTREG(RADEON_DISP_LIN_TRANS_GRPH_A, ulOrigDISP_LIN_TRANS_GRPH_A); - OUTREG(RADEON_DISP_LIN_TRANS_GRPH_B, ulOrigDISP_LIN_TRANS_GRPH_B); - OUTREG(RADEON_DISP_LIN_TRANS_GRPH_C, ulOrigDISP_LIN_TRANS_GRPH_C); - OUTREG(RADEON_DISP_LIN_TRANS_GRPH_D, ulOrigDISP_LIN_TRANS_GRPH_D); - OUTREG(RADEON_DISP_LIN_TRANS_GRPH_E, ulOrigDISP_LIN_TRANS_GRPH_E); - OUTREG(RADEON_DISP_LIN_TRANS_GRPH_F, ulOrigDISP_LIN_TRANS_GRPH_F); - OUTREG(RADEON_CRTC2_H_TOTAL_DISP, ulOrigCRTC2_H_TOTAL_DISP); - OUTREG(RADEON_CRTC2_V_TOTAL_DISP, ulOrigCRTC2_V_TOTAL_DISP); - OUTREG(RADEON_CRTC2_H_SYNC_STRT_WID, ulOrigCRTC2_H_SYNC_STRT_WID); - OUTREG(RADEON_CRTC2_V_SYNC_STRT_WID, ulOrigCRTC2_V_SYNC_STRT_WID); - OUTREG(RADEON_CRTC2_GEN_CNTL, ulOrigCRTC2_GEN_CNTL); - OUTREG(RADEON_DISP_OUTPUT_CNTL, ulOrigDISP_OUTPUT_CNTL); - OUTREG(RADEON_FP2_GEN_CNTL, ulOrigFP2_GEN_CNTL); - OUTREG(RADEON_GPIO_MONID, ulOrigGPIO_MONID); - } else { - unsigned long ulOrigPIXCLKSDATA; - unsigned long ulOrigTV_MASTER_CNTL; - unsigned long ulOrigTV_DAC_CNTL; - unsigned long ulOrigTV_PRE_DAC_MUX_CNTL; - unsigned long ulOrigDAC_CNTL2; - unsigned long ulData; - unsigned long ulMask; - - ulOrigPIXCLKSDATA = INPLL(pScrn, RADEON_PIXCLKS_CNTL); - - ulData = ulOrigPIXCLKSDATA; - ulData &= ~(RADEON_PIX2CLK_ALWAYS_ONb - | RADEON_PIX2CLK_DAC_ALWAYS_ONb); - ulMask = ~(RADEON_PIX2CLK_ALWAYS_ONb - | RADEON_PIX2CLK_DAC_ALWAYS_ONb); - OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, ulData, ulMask); - - ulOrigTV_MASTER_CNTL = INREG(RADEON_TV_MASTER_CNTL); - ulData = ulOrigTV_MASTER_CNTL; - ulData &= ~RADEON_TVCLK_ALWAYS_ONb; - OUTREG(RADEON_TV_MASTER_CNTL, ulData); - - ulOrigDAC_CNTL2 = INREG(RADEON_DAC_CNTL2); - ulData = ulOrigDAC_CNTL2; - ulData &= ~RADEON_DAC2_DAC2_CLK_SEL; - OUTREG(RADEON_DAC_CNTL2, ulData); - - ulOrigTV_DAC_CNTL = INREG(RADEON_TV_DAC_CNTL); - - ulData = 0x00880213; - OUTREG(RADEON_TV_DAC_CNTL, ulData); - - ulOrigTV_PRE_DAC_MUX_CNTL = INREG(RADEON_TV_PRE_DAC_MUX_CNTL); - - ulData = (RADEON_Y_RED_EN - | RADEON_C_GRN_EN - | RADEON_CMP_BLU_EN - | RADEON_RED_MX_FORCE_DAC_DATA - | RADEON_GRN_MX_FORCE_DAC_DATA - | RADEON_BLU_MX_FORCE_DAC_DATA); - if (IS_R300_VARIANT) - ulData |= 0x180 << RADEON_TV_FORCE_DAC_DATA_SHIFT; - else - ulData |= 0x1f5 << RADEON_TV_FORCE_DAC_DATA_SHIFT; - OUTREG(RADEON_TV_PRE_DAC_MUX_CNTL, ulData); - - usleep(10000); - - ulData = INREG(RADEON_TV_DAC_CNTL); - bConnected = (ulData & RADEON_TV_DAC_CMPOUT)?1:0; - - ulData = ulOrigPIXCLKSDATA; - ulMask = 0xFFFFFFFFL; - OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, ulData, ulMask); - - OUTREG(RADEON_TV_MASTER_CNTL, ulOrigTV_MASTER_CNTL); - OUTREG(RADEON_DAC_CNTL2, ulOrigDAC_CNTL2); - OUTREG(RADEON_TV_DAC_CNTL, ulOrigTV_DAC_CNTL); - OUTREG(RADEON_TV_PRE_DAC_MUX_CNTL, ulOrigTV_PRE_DAC_MUX_CNTL); - } -#endif - return MT_UNKNOWN; - } - - return(bConnected ? MT_CRT : MT_NONE); -} -#endif - -RADEONMonitorType -legacy_dac_detect(xf86OutputPtr output) -{ - ScrnInfoPtr pScrn = output->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONOutputPrivatePtr radeon_output = output->driver_private; - RADEONMonitorType found = MT_NONE; - - if (radeon_output->devices & (ATOM_DEVICE_TV_SUPPORT)) { - if (xf86ReturnOptValBool(info->Options, OPTION_FORCE_TVOUT, FALSE)) { - if (radeon_output->ConnectorType == CONNECTOR_STV) - found = MT_STV; - else - found = MT_CTV; - } else { - if (radeon_output->load_detection) - found = radeon_detect_tv(pScrn); - } - } else if (radeon_output->devices & (ATOM_DEVICE_CRT2_SUPPORT)) { - if (info->encoders[ATOM_DEVICE_CRT2_INDEX] && - (info->encoders[ATOM_DEVICE_CRT2_INDEX]->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1)) { - if (radeon_output->load_detection) - found = radeon_detect_primary_dac(pScrn, TRUE); - } else { - if (radeon_output->load_detection) { - if (info->ChipFamily == CHIP_FAMILY_R200) - found = radeon_detect_ext_dac(pScrn); - else - found = radeon_detect_tv_dac(pScrn, TRUE); - } - } - } else if (radeon_output->devices & (ATOM_DEVICE_CRT1_SUPPORT)) { - if (info->encoders[ATOM_DEVICE_CRT1_INDEX] && - (info->encoders[ATOM_DEVICE_CRT1_INDEX]->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1)) { - if (radeon_output->load_detection) - found = radeon_detect_primary_dac(pScrn, TRUE); - } else { - if (radeon_output->load_detection) { - if (info->ChipFamily == CHIP_FAMILY_R200) - found = radeon_detect_ext_dac(pScrn); - else - found = radeon_detect_tv_dac(pScrn, TRUE); - } - } - } - - return found; -} - -/* - * Powering done DAC, needed for DPMS problem with ViewSonic P817 (or its variant). - * - */ -static void -RADEONDacPowerSet(ScrnInfoPtr pScrn, Bool IsOn, Bool IsPrimaryDAC) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - if (IsPrimaryDAC) { - uint32_t dac_cntl; - uint32_t dac_macro_cntl = 0; - dac_cntl = INREG(RADEON_DAC_CNTL); - dac_macro_cntl = INREG(RADEON_DAC_MACRO_CNTL); - if (IsOn) { - dac_cntl &= ~RADEON_DAC_PDWN; - dac_macro_cntl &= ~(RADEON_DAC_PDWN_R | - RADEON_DAC_PDWN_G | - RADEON_DAC_PDWN_B); - } else { - dac_cntl |= RADEON_DAC_PDWN; - dac_macro_cntl |= (RADEON_DAC_PDWN_R | - RADEON_DAC_PDWN_G | - RADEON_DAC_PDWN_B); - } - OUTREG(RADEON_DAC_CNTL, dac_cntl); - OUTREG(RADEON_DAC_MACRO_CNTL, dac_macro_cntl); - } else { - uint32_t tv_dac_cntl; - uint32_t fp2_gen_cntl; - - switch(info->ChipFamily) { - case CHIP_FAMILY_R420: - case CHIP_FAMILY_RV410: - tv_dac_cntl = INREG(RADEON_TV_DAC_CNTL); - if (IsOn) { - tv_dac_cntl &= ~(R420_TV_DAC_RDACPD | - R420_TV_DAC_GDACPD | - R420_TV_DAC_BDACPD | - RADEON_TV_DAC_BGSLEEP); - } else { - tv_dac_cntl |= (R420_TV_DAC_RDACPD | - R420_TV_DAC_GDACPD | - R420_TV_DAC_BDACPD | - RADEON_TV_DAC_BGSLEEP); - } - OUTREG(RADEON_TV_DAC_CNTL, tv_dac_cntl); - break; - case CHIP_FAMILY_R200: - fp2_gen_cntl = INREG(RADEON_FP2_GEN_CNTL); - if (IsOn) { - fp2_gen_cntl |= RADEON_FP2_DVO_EN; - } else { - fp2_gen_cntl &= ~RADEON_FP2_DVO_EN; - } - OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); - break; - default: - tv_dac_cntl = INREG(RADEON_TV_DAC_CNTL); - if (IsOn) { - tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD | - RADEON_TV_DAC_GDACPD | - RADEON_TV_DAC_BDACPD | - RADEON_TV_DAC_BGSLEEP); - } else { - tv_dac_cntl |= (RADEON_TV_DAC_RDACPD | - RADEON_TV_DAC_GDACPD | - RADEON_TV_DAC_BDACPD | - RADEON_TV_DAC_BGSLEEP); - } - OUTREG(RADEON_TV_DAC_CNTL, tv_dac_cntl); - break; - } - } -} - -void -legacy_output_dpms(xf86OutputPtr output, int mode) -{ - ScrnInfoPtr pScrn = output->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONSavePtr save = info->ModeReg; - unsigned char * RADEONMMIO = info->MMIO; - unsigned long tmp; - RADEONOutputPrivatePtr radeon_output = output->driver_private; - radeon_encoder_ptr radeon_encoder = radeon_get_encoder(output); - - if (radeon_encoder == NULL) - return; - - switch(mode) { - case DPMSModeOn: - radeon_encoder->devices |= radeon_output->active_device; - switch (radeon_encoder->encoder_id) { - case ENCODER_OBJECT_ID_INTERNAL_LVDS: - { - radeon_lvds_ptr lvds = (radeon_lvds_ptr)radeon_encoder->dev_priv; - if (lvds == NULL) - return; - ErrorF("enable LVDS\n"); - tmp = INREG(RADEON_LVDS_GEN_CNTL); - tmp |= (RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN); -#if defined(__powerpc__) - /* not sure if this is needed on non-Macs */ - if (info->MacModel) - tmp |= RADEON_LVDS_BL_MOD_EN; -#endif - tmp &= ~(RADEON_LVDS_DISPLAY_DIS); - usleep (lvds->PanelPwrDly * 1000); - OUTREG(RADEON_LVDS_GEN_CNTL, tmp); - save->lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN); - save->lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS); - } - break; - case ENCODER_OBJECT_ID_INTERNAL_TMDS1: - ErrorF("enable FP1\n"); - tmp = INREG(RADEON_FP_GEN_CNTL); - tmp |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN); - OUTREG(RADEON_FP_GEN_CNTL, tmp); - save->fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN); - if ((info->ChipFamily == CHIP_FAMILY_RS400) || - (info->ChipFamily == CHIP_FAMILY_RS480)) { - tmp = INREG(RS400_FP_2ND_GEN_CNTL); - tmp |= (RS400_FP_2ND_ON | RS400_TMDS_2ND_EN); - OUTREG(RS400_FP_2ND_GEN_CNTL, tmp); - save->fp_2nd_gen_cntl |= (RS400_FP_2ND_ON | - RS400_TMDS_2ND_EN); - } - break; - case ENCODER_OBJECT_ID_INTERNAL_DVO1: - ErrorF("enable FP2\n"); - tmp = INREG(RADEON_FP2_GEN_CNTL); - tmp &= ~RADEON_FP2_BLANK_EN; - tmp |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN); - OUTREG(RADEON_FP2_GEN_CNTL, tmp); - save->fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN); - save->fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN; - if ((info->ChipFamily == CHIP_FAMILY_RS400) || - (info->ChipFamily == CHIP_FAMILY_RS480)) { - tmp = INREG(RS400_FP2_2_GEN_CNTL); - tmp &= ~RS400_FP2_2_BLANK_EN; - tmp |= (RS400_FP2_2_ON | RS400_FP2_2_DVO2_EN); - OUTREG(RS400_FP2_2_GEN_CNTL, tmp); - save->fp2_2_gen_cntl |= (RS400_FP2_2_ON | RS400_FP2_2_DVO2_EN); - save->fp2_2_gen_cntl &= ~RS400_FP2_2_BLANK_EN; - } - break; - case ENCODER_OBJECT_ID_INTERNAL_DAC1: - ErrorF("enable primary dac\n"); - tmp = INREG(RADEON_CRTC_EXT_CNTL); - tmp |= RADEON_CRTC_CRT_ON; - OUTREG(RADEON_CRTC_EXT_CNTL, tmp); - save->crtc_ext_cntl |= RADEON_CRTC_CRT_ON; - RADEONDacPowerSet(pScrn, TRUE, TRUE); - break; - case ENCODER_OBJECT_ID_INTERNAL_DAC2: - if (radeon_output->active_device & (ATOM_DEVICE_TV_SUPPORT)) { - ErrorF("enable TV\n"); - tmp = INREG(RADEON_TV_MASTER_CNTL); - tmp |= RADEON_TV_ON; - OUTREG(RADEON_TV_MASTER_CNTL, tmp); - radeon_output->tvout.tv_on = TRUE; - } else { - ErrorF("enable TVDAC\n"); - if (info->ChipFamily == CHIP_FAMILY_R200) { - tmp = INREG(RADEON_FP2_GEN_CNTL); - tmp |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN); - OUTREG(RADEON_FP2_GEN_CNTL, tmp); - save->fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN); - } else { - tmp = INREG(RADEON_CRTC2_GEN_CNTL); - tmp |= RADEON_CRTC2_CRT2_ON; - OUTREG(RADEON_CRTC2_GEN_CNTL, tmp); - save->crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON; - } - } - RADEONDacPowerSet(pScrn, TRUE, FALSE); - break; - } - break; - case DPMSModeOff: - case DPMSModeSuspend: - case DPMSModeStandby: - radeon_encoder->devices &= ~(radeon_output->active_device); - if (!radeon_encoder->devices) { - switch (radeon_encoder->encoder_id) { - case ENCODER_OBJECT_ID_INTERNAL_LVDS: - { - unsigned long tmpPixclksCntl = INPLL(pScrn, RADEON_PIXCLKS_CNTL); - radeon_lvds_ptr lvds = (radeon_lvds_ptr)radeon_encoder->dev_priv; - if (lvds == NULL) - return; - if (info->IsMobility || info->IsIGP) { - /* Asic bug, when turning off LVDS_ON, we have to make sure - RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off - */ - OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb); - } -#if defined(__powerpc__) - /* not sure if this is needed on non-Macs */ - if (info->MacModel) { - tmp = INREG(RADEON_LVDS_GEN_CNTL); - tmp |= RADEON_LVDS_DISPLAY_DIS; - tmp &= ~RADEON_LVDS_BL_MOD_EN; - OUTREG(RADEON_LVDS_GEN_CNTL, tmp); - usleep(100); - tmp &= ~(RADEON_LVDS_ON | RADEON_LVDS_EN); - OUTREG(RADEON_LVDS_GEN_CNTL, tmp); - } else -#endif - { - tmp = INREG(RADEON_LVDS_GEN_CNTL); - tmp |= RADEON_LVDS_DISPLAY_DIS; - tmp &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN); - OUTREG(RADEON_LVDS_GEN_CNTL, tmp); - } - save->lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS; - save->lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN); - if (info->IsMobility || info->IsIGP) { - OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmpPixclksCntl); - } - usleep (lvds->PanelPwrDly * 1000); - } - break; - case ENCODER_OBJECT_ID_INTERNAL_TMDS1: - ErrorF("disable FP1\n"); - tmp = INREG(RADEON_FP_GEN_CNTL); - tmp &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); - OUTREG(RADEON_FP_GEN_CNTL, tmp); - save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); - if ((info->ChipFamily == CHIP_FAMILY_RS400) || - (info->ChipFamily == CHIP_FAMILY_RS480)) { - tmp = INREG(RS400_FP_2ND_GEN_CNTL); - tmp &= ~(RS400_FP_2ND_ON | RS400_TMDS_2ND_EN); - OUTREG(RS400_FP_2ND_GEN_CNTL, tmp); - save->fp_2nd_gen_cntl &= ~(RS400_FP_2ND_ON | - RS400_TMDS_2ND_EN); - } - break; - case ENCODER_OBJECT_ID_INTERNAL_DVO1: - ErrorF("disable FP2\n"); - tmp = INREG(RADEON_FP2_GEN_CNTL); - tmp |= RADEON_FP2_BLANK_EN; - tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); - OUTREG(RADEON_FP2_GEN_CNTL, tmp); - save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); - save->fp2_gen_cntl |= RADEON_FP2_BLANK_EN; - if ((info->ChipFamily == CHIP_FAMILY_RS400) || - (info->ChipFamily == CHIP_FAMILY_RS480)) { - tmp = INREG(RS400_FP2_2_GEN_CNTL); - tmp |= RS400_FP2_2_BLANK_EN; - tmp &= ~(RS400_FP2_2_ON | RS400_FP2_2_DVO2_EN); - OUTREG(RS400_FP2_2_GEN_CNTL, tmp); - save->fp2_2_gen_cntl &= ~(RS400_FP2_2_ON | RS400_FP2_2_DVO2_EN); - save->fp2_2_gen_cntl |= RS400_FP2_2_BLANK_EN; - } - break; - case ENCODER_OBJECT_ID_INTERNAL_DAC1: - ErrorF("disable primary dac\n"); - tmp = INREG(RADEON_CRTC_EXT_CNTL); - tmp &= ~RADEON_CRTC_CRT_ON; - OUTREG(RADEON_CRTC_EXT_CNTL, tmp); - save->crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON; - RADEONDacPowerSet(pScrn, FALSE, TRUE); - break; - case ENCODER_OBJECT_ID_INTERNAL_DAC2: - if (radeon_output->active_device & (ATOM_DEVICE_TV_SUPPORT)) { - ErrorF("disable TV\n"); - tmp = INREG(RADEON_TV_MASTER_CNTL); - tmp &= ~RADEON_TV_ON; - OUTREG(RADEON_TV_MASTER_CNTL, tmp); - radeon_output->tvout.tv_on = FALSE; - } else { - ErrorF("disable TVDAC\n"); - if (info->ChipFamily == CHIP_FAMILY_R200) { - tmp = INREG(RADEON_FP2_GEN_CNTL); - tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); - OUTREG(RADEON_FP2_GEN_CNTL, tmp); - save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); - } else { - tmp = INREG(RADEON_CRTC2_GEN_CNTL); - tmp &= ~RADEON_CRTC2_CRT2_ON; - OUTREG(RADEON_CRTC2_GEN_CNTL, tmp); - save->crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON; - } - } - RADEONDacPowerSet(pScrn, FALSE, FALSE); - break; - } - } - break; - } -} - -static void -RADEONInitFPRegisters(xf86OutputPtr output, RADEONSavePtr save, - DisplayModePtr mode, BOOL IsPrimary) -{ - ScrnInfoPtr pScrn = output->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); - RADEONOutputPrivatePtr radeon_output = output->driver_private; - radeon_encoder_ptr radeon_encoder = radeon_get_encoder(output); - radeon_tmds_ptr tmds = NULL; - int i; - uint32_t tmp = info->SavedReg->tmds_pll_cntl & 0xfffff; - - if (radeon_encoder == NULL) - return; - - tmds = (radeon_tmds_ptr)radeon_encoder->dev_priv; - - if (tmds == NULL) - return; - - for (i = 0; i < 4; i++) { - if (tmds->tmds_pll[i].freq == 0) - break; - if ((uint32_t)(mode->Clock / 10) < tmds->tmds_pll[i].freq) { - tmp = tmds->tmds_pll[i].value ; - break; - } - } - - if (IS_R300_VARIANT || (info->ChipFamily == CHIP_FAMILY_RV280)) { - if (tmp & 0xfff00000) - save->tmds_pll_cntl = tmp; - else { - save->tmds_pll_cntl = info->SavedReg->tmds_pll_cntl & 0xfff00000; - save->tmds_pll_cntl |= tmp; - } - } else save->tmds_pll_cntl = tmp; - - save->tmds_transmitter_cntl = info->SavedReg->tmds_transmitter_cntl & - ~(RADEON_TMDS_TRANSMITTER_PLLRST); - - if (IS_R300_VARIANT || (info->ChipFamily == CHIP_FAMILY_R200) || !pRADEONEnt->HasCRTC2) - save->tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN); - else /* weird, RV chips got this bit reversed? */ - save->tmds_transmitter_cntl |= (RADEON_TMDS_TRANSMITTER_PLLEN); - - save->fp_gen_cntl = info->SavedReg->fp_gen_cntl | - (RADEON_FP_CRTC_DONT_SHADOW_VPAR | - RADEON_FP_CRTC_DONT_SHADOW_HEND ); - - save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); - - save->fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN | - RADEON_FP_DFP_SYNC_SEL | - RADEON_FP_CRT_SYNC_SEL | - RADEON_FP_CRTC_LOCK_8DOT | - RADEON_FP_USE_SHADOW_EN | - RADEON_FP_CRTC_USE_SHADOW_VEND | - RADEON_FP_CRT_SYNC_ALT); - - if (pScrn->rgbBits == 8) - save->fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */ - else - save->fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */ - - if (IsPrimary) { - if ((IS_R300_VARIANT) || (info->ChipFamily == CHIP_FAMILY_R200)) { - save->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK; - if (radeon_output->Flags & RADEON_USE_RMX) - save->fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX; - else - save->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1; - } else - save->fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2; - } else { - if ((IS_R300_VARIANT) || (info->ChipFamily == CHIP_FAMILY_R200)) { - save->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK; - save->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2; - } else - save->fp_gen_cntl |= RADEON_FP_SEL_CRTC2; - } - - if ((info->ChipFamily == CHIP_FAMILY_RS400) || - (info->ChipFamily == CHIP_FAMILY_RS480)) { - save->tmds2_transmitter_cntl = info->SavedReg->tmds2_transmitter_cntl & - ~(RS400_TMDS2_PLLRST); - save->tmds2_transmitter_cntl &= ~(RS400_TMDS2_PLLEN); - - save->fp_2nd_gen_cntl = info->SavedReg->fp_2nd_gen_cntl; - - if (pScrn->rgbBits == 8) - save->fp_2nd_gen_cntl |= RS400_PANEL_FORMAT_2ND; /* 24 bit format */ - else - save->fp_2nd_gen_cntl &= ~RS400_PANEL_FORMAT_2ND;/* 18 bit format */ - - save->fp_2nd_gen_cntl &= ~RS400_FP_2ND_SOURCE_SEL_MASK; - - if (IsPrimary) { - if (radeon_output->Flags & RADEON_USE_RMX) - save->fp_2nd_gen_cntl |= RS400_FP_2ND_SOURCE_SEL_RMX; - else - save->fp_2nd_gen_cntl |= RS400_FP_2ND_SOURCE_SEL_CRTC1; - } else - save->fp_2nd_gen_cntl |= RS400_FP_2ND_SOURCE_SEL_CRTC2; - } - -} - -static void -RADEONInitFP2Registers(xf86OutputPtr output, RADEONSavePtr save, - DisplayModePtr mode, BOOL IsPrimary) -{ - ScrnInfoPtr pScrn = output->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONOutputPrivatePtr radeon_output = output->driver_private; - - if (pScrn->rgbBits == 8) - save->fp2_gen_cntl = info->SavedReg->fp2_gen_cntl | - RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */ - else - save->fp2_gen_cntl = info->SavedReg->fp2_gen_cntl & - ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */ - - save->fp2_gen_cntl &= ~(RADEON_FP2_ON | - RADEON_FP2_DVO_EN | - RADEON_FP2_DVO_RATE_SEL_SDR); - - - /* XXX: these are oem specific */ - if (IS_R300_VARIANT) { - if ((info->Chipset == PCI_CHIP_RV350_NP) && - (PCI_SUB_VENDOR_ID(info->PciInfo) == 0x1028) && - (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x2001)) - save->fp2_gen_cntl |= R200_FP2_DVO_CLOCK_MODE_SINGLE; /* Dell Inspiron 8600 */ - else - save->fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R200_FP2_DVO_CLOCK_MODE_SINGLE; - } - -#if 0 - /* DVO configurations: - * SDR single channel (data rate 165 Mhz, port width 12 bits) - * DDR single channel (data rate 330 Mhz, port width 12 bits) - * SDR dual channel (data rate 330 Mhz, port width 24 bits) - * - dual channel is only available on r3xx+ - */ - if (info->ChipFamily >= CHIP_FAMILY_R200) { - if (sdr) - save->fp2_gen_cntl |= R200_FP2_DVO_RATE_SEL_SDR; - if (IS_R300_VARIANT && dual channel) - save->fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN; - } -#endif - - if (IsPrimary) { - if ((info->ChipFamily == CHIP_FAMILY_R200) || IS_R300_VARIANT) { - save->fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK; - if (radeon_output->Flags & RADEON_USE_RMX) - save->fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX; - else - save->fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1; - } else - save->fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2; - } else { - if ((info->ChipFamily == CHIP_FAMILY_R200) || IS_R300_VARIANT) { - save->fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK; - save->fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2; - } else - save->fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2; - } - - if ((info->ChipFamily == CHIP_FAMILY_RS400) || - (info->ChipFamily == CHIP_FAMILY_RS480)) { - if (pScrn->rgbBits == 8) - save->fp2_2_gen_cntl = info->SavedReg->fp2_2_gen_cntl | - RS400_FP2_2_PANEL_FORMAT; /* 24 bit format, */ - else - save->fp2_2_gen_cntl = info->SavedReg->fp2_2_gen_cntl & - ~RS400_FP2_2_PANEL_FORMAT;/* 18 bit format, */ - - save->fp2_2_gen_cntl &= ~(RS400_FP2_2_ON | - RS400_FP2_2_DVO2_EN | - RS400_FP2_2_SOURCE_SEL_MASK); - - if (IsPrimary) { - if (radeon_output->Flags & RADEON_USE_RMX) - save->fp2_2_gen_cntl |= RS400_FP2_2_SOURCE_SEL_RMX; - else - save->fp2_2_gen_cntl |= RS400_FP2_2_SOURCE_SEL_CRTC1; - } else - save->fp2_2_gen_cntl |= RS400_FP2_2_SOURCE_SEL_CRTC2; - } - -} - -static void -RADEONInitLVDSRegisters(xf86OutputPtr output, RADEONSavePtr save, - DisplayModePtr mode, BOOL IsPrimary) -{ - ScrnInfoPtr pScrn = output->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONOutputPrivatePtr radeon_output = output->driver_private; - - save->lvds_pll_cntl = (info->SavedReg->lvds_pll_cntl | - RADEON_LVDS_PLL_EN); - - save->lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET; - - save->lvds_gen_cntl = info->SavedReg->lvds_gen_cntl; - save->lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS; - save->lvds_gen_cntl &= ~(RADEON_LVDS_ON | - RADEON_LVDS_BLON | - RADEON_LVDS_EN | - RADEON_LVDS_RST_FM); - - if (IS_R300_VARIANT) - save->lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK); - - if (IsPrimary) { - if (IS_R300_VARIANT) { - if (radeon_output->Flags & RADEON_USE_RMX) - save->lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX; - } else - save->lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2; - } else { - if (IS_R300_VARIANT) { - save->lvds_pll_cntl |= R300_LVDS_SRC_SEL_CRTC2; - } else - save->lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2; - } - -} - -static void -RADEONInitRMXRegisters(xf86OutputPtr output, RADEONSavePtr save, - DisplayModePtr mode) -{ - ScrnInfoPtr pScrn = output->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONOutputPrivatePtr radeon_output = output->driver_private; - radeon_native_mode_ptr native_mode = &radeon_output->native_mode; - int xres = mode->HDisplay; - int yres = mode->VDisplay; - Bool Hscale = TRUE, Vscale = TRUE; - int hsync_wid; - int vsync_wid; - int hsync_start; - - - save->fp_vert_stretch = info->SavedReg->fp_vert_stretch & - (RADEON_VERT_STRETCH_RESERVED | - RADEON_VERT_AUTO_RATIO_INC); - save->fp_horz_stretch = info->SavedReg->fp_horz_stretch & - (RADEON_HORZ_FP_LOOP_STRETCH | - RADEON_HORZ_AUTO_RATIO_INC); - - save->crtc_more_cntl = 0; - if ((info->ChipFamily == CHIP_FAMILY_RS100) || - (info->ChipFamily == CHIP_FAMILY_RS200)) { - /* This is to workaround the asic bug for RMX, some versions - of BIOS dosen't have this register initialized correctly. - */ - save->crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN; - } - - - save->fp_crtc_h_total_disp = ((((mode->CrtcHTotal / 8) - 1) & 0x3ff) - | ((((mode->CrtcHDisplay / 8) - 1) & 0x1ff) - << 16)); - - hsync_wid = (mode->CrtcHSyncEnd - mode->CrtcHSyncStart) / 8; - if (!hsync_wid) hsync_wid = 1; - hsync_start = mode->CrtcHSyncStart - 8; - - save->fp_h_sync_strt_wid = ((hsync_start & 0x1fff) - | ((hsync_wid & 0x3f) << 16) - | ((mode->Flags & V_NHSYNC) - ? RADEON_CRTC_H_SYNC_POL - : 0)); - - save->fp_crtc_v_total_disp = (((mode->CrtcVTotal - 1) & 0xffff) - | ((mode->CrtcVDisplay - 1) << 16)); - - vsync_wid = mode->CrtcVSyncEnd - mode->CrtcVSyncStart; - if (!vsync_wid) vsync_wid = 1; - - save->fp_v_sync_strt_wid = (((mode->CrtcVSyncStart - 1) & 0xfff) - | ((vsync_wid & 0x1f) << 16) - | ((mode->Flags & V_NVSYNC) - ? RADEON_CRTC_V_SYNC_POL - : 0)); - - save->fp_horz_vert_active = 0; - - if ((radeon_output->active_device & (ATOM_DEVICE_LCD_SUPPORT)) || - (radeon_output->active_device & (ATOM_DEVICE_DFP_SUPPORT))) { - - if (native_mode->PanelXRes == 0 || native_mode->PanelYRes == 0) { - Hscale = FALSE; - Vscale = FALSE; - } else { - if (xres > native_mode->PanelXRes) - xres = native_mode->PanelXRes; - if (yres > native_mode->PanelYRes) - yres = native_mode->PanelYRes; - - if (xres == native_mode->PanelXRes) - Hscale = FALSE; - if (yres == native_mode->PanelYRes) - Vscale = FALSE; - } - - if ((!Hscale) || (!(radeon_output->Flags & RADEON_USE_RMX)) || - (radeon_output->rmx_type == RMX_CENTER)) { - save->fp_horz_stretch |= ((xres/8-1)<<16); - } else { - uint32_t scale, inc; - inc = (save->fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0; - scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX) - / native_mode->PanelXRes + 1; - save->fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) | - RADEON_HORZ_STRETCH_BLEND | - RADEON_HORZ_STRETCH_ENABLE | - ((native_mode->PanelXRes/8-1)<<16)); - } - - if ((!Vscale) || (!(radeon_output->Flags & RADEON_USE_RMX)) || - (radeon_output->rmx_type == RMX_CENTER)) { - save->fp_vert_stretch |= ((yres-1)<<12); - } else { - uint32_t scale, inc; - inc = (save->fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0; - scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX) - / native_mode->PanelYRes + 1; - save->fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) | - RADEON_VERT_STRETCH_ENABLE | - RADEON_VERT_STRETCH_BLEND | - ((native_mode->PanelYRes-1)<<12)); - } - - if ((radeon_output->rmx_type == RMX_CENTER) && - (radeon_output->Flags & RADEON_USE_RMX)) { - int blank_width; - - save->crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN | - RADEON_CRTC_AUTO_VERT_CENTER_EN); - - blank_width = (mode->CrtcHBlankEnd - mode->CrtcHBlankStart) / 8; - if (blank_width > 110) - blank_width = 110; - - save->fp_crtc_h_total_disp = (((blank_width) & 0x3ff) - | ((((mode->CrtcHDisplay / 8) - 1) & 0x1ff) - << 16)); - - hsync_wid = (mode->CrtcHSyncEnd - mode->CrtcHSyncStart) / 8; - if (!hsync_wid) - hsync_wid = 1; - - save->fp_h_sync_strt_wid = ((((mode->CrtcHSyncStart - mode->CrtcHBlankStart) / 8) & 0x1fff) - | ((hsync_wid & 0x3f) << 16) - | ((mode->Flags & V_NHSYNC) - ? RADEON_CRTC_H_SYNC_POL - : 0)); - - save->fp_crtc_v_total_disp = (((mode->CrtcVBlankEnd - mode->CrtcVBlankStart) & 0xffff) - | ((mode->CrtcVDisplay - 1) << 16)); - - vsync_wid = mode->CrtcVSyncEnd - mode->CrtcVSyncStart; - if (!vsync_wid) - vsync_wid = 1; - - save->fp_v_sync_strt_wid = ((((mode->CrtcVSyncStart - mode->CrtcVBlankStart) & 0xfff) - | ((vsync_wid & 0x1f) << 16) - | ((mode->Flags & V_NVSYNC) - ? RADEON_CRTC_V_SYNC_POL - : 0))); - - save->fp_horz_vert_active = (((native_mode->PanelYRes) & 0xfff) | - (((native_mode->PanelXRes / 8) & 0x1ff) << 16)); - - } - } -} - -static void -RADEONInitDACRegisters(xf86OutputPtr output, RADEONSavePtr save, - DisplayModePtr mode, BOOL IsPrimary) -{ - ScrnInfoPtr pScrn = output->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - - if (IsPrimary) { - if ((info->ChipFamily == CHIP_FAMILY_R200) || IS_R300_VARIANT) { - save->disp_output_cntl = info->SavedReg->disp_output_cntl & - ~RADEON_DISP_DAC_SOURCE_MASK; - } else { - save->dac2_cntl = info->SavedReg->dac2_cntl & ~(RADEON_DAC2_DAC_CLK_SEL); - } - } else { - if ((info->ChipFamily == CHIP_FAMILY_R200) || IS_R300_VARIANT) { - save->disp_output_cntl = info->SavedReg->disp_output_cntl & - ~RADEON_DISP_DAC_SOURCE_MASK; - save->disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2; - } else { - save->dac2_cntl = info->SavedReg->dac2_cntl | RADEON_DAC2_DAC_CLK_SEL; - } - } - save->dac_cntl = (RADEON_DAC_MASK_ALL - | RADEON_DAC_VGA_ADR_EN - | (info->dac6bits ? 0 : RADEON_DAC_8BIT_EN)); - - save->dac_macro_cntl = info->SavedReg->dac_macro_cntl; -} - -static void -RADEONInitTvDacCntl(xf86OutputPtr output, RADEONSavePtr save) -{ - ScrnInfoPtr pScrn = output->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - radeon_encoder_ptr radeon_encoder = radeon_get_encoder(output); - radeon_tvdac_ptr tvdac = NULL; - - if (radeon_encoder == NULL) - return; - - tvdac = (radeon_tvdac_ptr)radeon_encoder->dev_priv; - - if (tvdac == NULL) - return; - - if (info->ChipFamily == CHIP_FAMILY_R420 || - info->ChipFamily == CHIP_FAMILY_RV410) { - save->tv_dac_cntl = info->SavedReg->tv_dac_cntl & - ~(RADEON_TV_DAC_STD_MASK | - RADEON_TV_DAC_BGADJ_MASK | - R420_TV_DAC_DACADJ_MASK | - R420_TV_DAC_RDACPD | - R420_TV_DAC_GDACPD | - R420_TV_DAC_BDACPD | - R420_TV_DAC_TVENABLE); - } else { - save->tv_dac_cntl = info->SavedReg->tv_dac_cntl & - ~(RADEON_TV_DAC_STD_MASK | - RADEON_TV_DAC_BGADJ_MASK | - RADEON_TV_DAC_DACADJ_MASK | - RADEON_TV_DAC_RDACPD | - RADEON_TV_DAC_GDACPD | - RADEON_TV_DAC_BDACPD); - } - - save->tv_dac_cntl |= (RADEON_TV_DAC_NBLANK | - RADEON_TV_DAC_NHOLD | - RADEON_TV_DAC_STD_PS2 | - tvdac->ps2_tvdac_adj); - -} - -static void -RADEONInitDAC2Registers(xf86OutputPtr output, RADEONSavePtr save, - DisplayModePtr mode, BOOL IsPrimary) -{ - ScrnInfoPtr pScrn = output->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - - /*0x0028023;*/ - RADEONInitTvDacCntl(output, save); - - if (IS_R300_VARIANT) - save->gpiopad_a = info->SavedReg->gpiopad_a | 1; - - save->dac2_cntl = info->SavedReg->dac2_cntl | RADEON_DAC2_DAC2_CLK_SEL; - - if (IsPrimary) { - if (IS_R300_VARIANT) { - save->disp_output_cntl = info->SavedReg->disp_output_cntl & - ~RADEON_DISP_TVDAC_SOURCE_MASK; - save->disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC; - } else if (info->ChipFamily == CHIP_FAMILY_R200) { - save->fp2_gen_cntl = info->SavedReg->fp2_gen_cntl & - ~(R200_FP2_SOURCE_SEL_MASK | - RADEON_FP2_DVO_RATE_SEL_SDR); - } else { - save->disp_hw_debug = info->SavedReg->disp_hw_debug | RADEON_CRT2_DISP1_SEL; - } - } else { - if (IS_R300_VARIANT) { - save->disp_output_cntl = info->SavedReg->disp_output_cntl & - ~RADEON_DISP_TVDAC_SOURCE_MASK; - save->disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2; - } else if (info->ChipFamily == CHIP_FAMILY_R200) { - save->fp2_gen_cntl = info->SavedReg->fp2_gen_cntl & - ~(R200_FP2_SOURCE_SEL_MASK | - RADEON_FP2_DVO_RATE_SEL_SDR); - save->fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2; - } else { - save->disp_hw_debug = info->SavedReg->disp_hw_debug & - ~RADEON_CRT2_DISP1_SEL; - } - } -} - -void -legacy_output_mode_set(xf86OutputPtr output, DisplayModePtr mode, - DisplayModePtr adjusted_mode) -{ - ScrnInfoPtr pScrn = output->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONOutputPrivatePtr radeon_output = output->driver_private; - xf86CrtcPtr crtc = output->crtc; - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - radeon_encoder_ptr radeon_encoder = radeon_get_encoder(output); - Bool is_primary = FALSE; - - if (radeon_encoder == NULL) - return; - - radeon_output->pixel_clock = adjusted_mode->Clock; - if (radeon_crtc->crtc_id == 0) { - ErrorF("set RMX\n"); - is_primary = TRUE; - RADEONInitRMXRegisters(output, info->ModeReg, adjusted_mode); - RADEONRestoreRMXRegisters(pScrn, info->ModeReg); - } - - switch (radeon_encoder->encoder_id) { - case ENCODER_OBJECT_ID_INTERNAL_LVDS: - ErrorF("set LVDS\n"); - RADEONInitLVDSRegisters(output, info->ModeReg, adjusted_mode, is_primary); - RADEONRestoreLVDSRegisters(pScrn, info->ModeReg); - break; - case ENCODER_OBJECT_ID_INTERNAL_TMDS1: - ErrorF("set FP1\n"); - RADEONInitFPRegisters(output, info->ModeReg, adjusted_mode, is_primary); - RADEONRestoreFPRegisters(pScrn, info->ModeReg); - break; - case ENCODER_OBJECT_ID_INTERNAL_DVO1: - ErrorF("set FP2\n"); - RADEONInitFP2Registers(output, info->ModeReg, adjusted_mode, is_primary); - if (info->IsAtomBios) { - unsigned char *RADEONMMIO = info->MMIO; - uint32_t fp2_gen_cntl; - - atombios_external_tmds_setup(output, ATOM_ENABLE); - fp2_gen_cntl = INREG(RADEON_FP2_GEN_CNTL) & ~R200_FP2_SOURCE_SEL_MASK; - if (radeon_crtc->crtc_id == 1) - fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2; - else { - if (radeon_output->Flags & RADEON_USE_RMX) - fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX; - else - fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1; - } - OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); - } else { - RADEONRestoreFP2Registers(pScrn, info->ModeReg); - RADEONRestoreDVOChip(pScrn, output); - } - break; - case ENCODER_OBJECT_ID_INTERNAL_DAC1: - ErrorF("set primary dac\n"); - RADEONInitDACRegisters(output, info->ModeReg, adjusted_mode, is_primary); - RADEONRestoreDACRegisters(pScrn, info->ModeReg); - break; - case ENCODER_OBJECT_ID_INTERNAL_DAC2: - if (radeon_output->active_device & (ATOM_DEVICE_TV_SUPPORT)) { - ErrorF("set TV\n"); - RADEONInitTVRegisters(output, info->ModeReg, adjusted_mode, is_primary); - RADEONRestoreDACRegisters(pScrn, info->ModeReg); - RADEONRestoreTVRegisters(pScrn, info->ModeReg); - } else { - ErrorF("set TVDAC\n"); - RADEONInitDAC2Registers(output, info->ModeReg, adjusted_mode, is_primary); - RADEONRestoreDACRegisters(pScrn, info->ModeReg); - } - break; - } - -} - -/* the following functions are based on the load detection code - * in the beos radeon driver by Thomas Kurschel and the existing - * load detection code in this driver. - */ -static RADEONMonitorType -radeon_detect_primary_dac(ScrnInfoPtr pScrn, Bool color) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - uint32_t vclk_ecp_cntl, crtc_ext_cntl; - uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp; - RADEONMonitorType found = MT_NONE; - - /* save the regs we need */ - vclk_ecp_cntl = INPLL(pScrn, RADEON_VCLK_ECP_CNTL); - crtc_ext_cntl = INREG(RADEON_CRTC_EXT_CNTL); - dac_ext_cntl = INREG(RADEON_DAC_EXT_CNTL); - dac_cntl = INREG(RADEON_DAC_CNTL); - dac_macro_cntl = INREG(RADEON_DAC_MACRO_CNTL); - - tmp = vclk_ecp_cntl & - ~(RADEON_PIXCLK_ALWAYS_ONb | RADEON_PIXCLK_DAC_ALWAYS_ONb); - OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, tmp); - - tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON; - OUTREG(RADEON_CRTC_EXT_CNTL, tmp); - - tmp = RADEON_DAC_FORCE_BLANK_OFF_EN | - RADEON_DAC_FORCE_DATA_EN; - - if (color) - tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB; - else - tmp |= RADEON_DAC_FORCE_DATA_SEL_G; - - if (IS_R300_VARIANT) - tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT); - else - tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT); - - OUTREG(RADEON_DAC_EXT_CNTL, tmp); - - tmp = dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_PDWN); - tmp |= RADEON_DAC_RANGE_CNTL_PS2 | RADEON_DAC_CMP_EN; - OUTREG(RADEON_DAC_CNTL, tmp); - - tmp &= ~(RADEON_DAC_PDWN_R | - RADEON_DAC_PDWN_G | - RADEON_DAC_PDWN_B); - - OUTREG(RADEON_DAC_MACRO_CNTL, tmp); - - usleep(2000); - - if (INREG(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT) { - found = MT_CRT; - xf86DrvMsg (pScrn->scrnIndex, X_INFO, - "Found %s CRT connected to primary DAC\n", - color ? "color" : "bw"); - } - - /* restore the regs we used */ - OUTREG(RADEON_DAC_CNTL, dac_cntl); - OUTREG(RADEON_DAC_MACRO_CNTL, dac_macro_cntl); - OUTREG(RADEON_DAC_EXT_CNTL, dac_ext_cntl); - OUTREG(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); - OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl); - - return found; -} - -static RADEONMonitorType -radeon_detect_ext_dac(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - uint32_t gpio_monid, fp2_gen_cntl, disp_output_cntl, crtc2_gen_cntl; - uint32_t disp_lin_trans_grph_a, disp_lin_trans_grph_b, disp_lin_trans_grph_c; - uint32_t disp_lin_trans_grph_d, disp_lin_trans_grph_e, disp_lin_trans_grph_f; - uint32_t tmp, crtc2_h_total_disp, crtc2_v_total_disp; - uint32_t crtc2_h_sync_strt_wid, crtc2_v_sync_strt_wid; - RADEONMonitorType found = MT_NONE; - int connected = 0; - int i = 0; - - /* save the regs we need */ - gpio_monid = INREG(RADEON_GPIO_MONID); - fp2_gen_cntl = INREG(RADEON_FP2_GEN_CNTL); - disp_output_cntl = INREG(RADEON_DISP_OUTPUT_CNTL); - crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL); - disp_lin_trans_grph_a = INREG(RADEON_DISP_LIN_TRANS_GRPH_A); - disp_lin_trans_grph_b = INREG(RADEON_DISP_LIN_TRANS_GRPH_B); - disp_lin_trans_grph_c = INREG(RADEON_DISP_LIN_TRANS_GRPH_C); - disp_lin_trans_grph_d = INREG(RADEON_DISP_LIN_TRANS_GRPH_D); - disp_lin_trans_grph_e = INREG(RADEON_DISP_LIN_TRANS_GRPH_E); - disp_lin_trans_grph_f = INREG(RADEON_DISP_LIN_TRANS_GRPH_F); - crtc2_h_total_disp = INREG(RADEON_CRTC2_H_TOTAL_DISP); - crtc2_v_total_disp = INREG(RADEON_CRTC2_V_TOTAL_DISP); - crtc2_h_sync_strt_wid = INREG(RADEON_CRTC2_H_SYNC_STRT_WID); - crtc2_v_sync_strt_wid = INREG(RADEON_CRTC2_V_SYNC_STRT_WID); - - tmp = INREG(RADEON_GPIO_MONID); - tmp &= ~RADEON_GPIO_A_0; - OUTREG(RADEON_GPIO_MONID, tmp); - - OUTREG(RADEON_FP2_GEN_CNTL, - RADEON_FP2_ON | - RADEON_FP2_PANEL_FORMAT | - R200_FP2_SOURCE_SEL_TRANS_UNIT | - RADEON_FP2_DVO_EN | - R200_FP2_DVO_RATE_SEL_SDR); - - OUTREG(RADEON_DISP_OUTPUT_CNTL, - RADEON_DISP_DAC_SOURCE_RMX | - RADEON_DISP_TRANS_MATRIX_GRAPHICS); - - OUTREG(RADEON_CRTC2_GEN_CNTL, - RADEON_CRTC2_EN | - RADEON_CRTC2_DISP_REQ_EN_B); - - OUTREG(RADEON_DISP_LIN_TRANS_GRPH_A, 0x00000000); - OUTREG(RADEON_DISP_LIN_TRANS_GRPH_B, 0x000003f0); - OUTREG(RADEON_DISP_LIN_TRANS_GRPH_C, 0x00000000); - OUTREG(RADEON_DISP_LIN_TRANS_GRPH_D, 0x000003f0); - OUTREG(RADEON_DISP_LIN_TRANS_GRPH_E, 0x00000000); - OUTREG(RADEON_DISP_LIN_TRANS_GRPH_F, 0x000003f0); - - OUTREG(RADEON_CRTC2_H_TOTAL_DISP, 0x01000008); - OUTREG(RADEON_CRTC2_H_SYNC_STRT_WID, 0x00000800); - OUTREG(RADEON_CRTC2_V_TOTAL_DISP, 0x00080001); - OUTREG(RADEON_CRTC2_V_SYNC_STRT_WID, 0x00000080); - - for (i = 0; i < 200; i++) { - tmp = INREG(RADEON_GPIO_MONID); - if (tmp & RADEON_GPIO_Y_0) - connected = 1; - else - connected = 0; - - if (!connected) - break; - - usleep(1000); - } - - if (connected) - found = MT_CRT; - - /* restore the regs we used */ - OUTREG(RADEON_DISP_LIN_TRANS_GRPH_A, disp_lin_trans_grph_a); - OUTREG(RADEON_DISP_LIN_TRANS_GRPH_B, disp_lin_trans_grph_b); - OUTREG(RADEON_DISP_LIN_TRANS_GRPH_C, disp_lin_trans_grph_c); - OUTREG(RADEON_DISP_LIN_TRANS_GRPH_D, disp_lin_trans_grph_d); - OUTREG(RADEON_DISP_LIN_TRANS_GRPH_E, disp_lin_trans_grph_e); - OUTREG(RADEON_DISP_LIN_TRANS_GRPH_F, disp_lin_trans_grph_f); - OUTREG(RADEON_CRTC2_H_TOTAL_DISP, crtc2_h_total_disp); - OUTREG(RADEON_CRTC2_V_TOTAL_DISP, crtc2_v_total_disp); - OUTREG(RADEON_CRTC2_H_SYNC_STRT_WID, crtc2_h_sync_strt_wid); - OUTREG(RADEON_CRTC2_V_SYNC_STRT_WID, crtc2_v_sync_strt_wid); - OUTREG(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); - OUTREG(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); - OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); - OUTREG(RADEON_GPIO_MONID, gpio_monid); - - return found; -} - -static RADEONMonitorType -radeon_detect_tv_dac(ScrnInfoPtr pScrn, Bool color) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl; - uint32_t disp_hw_debug, disp_output_cntl, gpiopad_a, pixclks_cntl, tmp; - RADEONMonitorType found = MT_NONE; - - /* save the regs we need */ - pixclks_cntl = INPLL(pScrn, RADEON_PIXCLKS_CNTL); - gpiopad_a = IS_R300_VARIANT ? INREG(RADEON_GPIOPAD_A) : 0; - disp_output_cntl = IS_R300_VARIANT ? INREG(RADEON_DISP_OUTPUT_CNTL) : 0; - disp_hw_debug = !IS_R300_VARIANT ? INREG(RADEON_DISP_HW_DEBUG) : 0; - crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL); - tv_dac_cntl = INREG(RADEON_TV_DAC_CNTL); - dac_ext_cntl = INREG(RADEON_DAC_EXT_CNTL); - dac_cntl2 = INREG(RADEON_DAC_CNTL2); - - tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb - | RADEON_PIX2CLK_DAC_ALWAYS_ONb); - OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp); - - if (IS_R300_VARIANT) { - OUTREGP(RADEON_GPIOPAD_A, 1, ~1 ); - } - - tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK; - tmp |= RADEON_CRTC2_CRT2_ON | - (2 << RADEON_CRTC2_PIX_WIDTH_SHIFT); - - OUTREG(RADEON_CRTC2_GEN_CNTL, tmp); - - if (IS_R300_VARIANT) { - tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK; - tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2; - OUTREG(RADEON_DISP_OUTPUT_CNTL, tmp); - } else { - tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL; - OUTREG(RADEON_DISP_HW_DEBUG, tmp); - } - - tmp = RADEON_TV_DAC_NBLANK | - RADEON_TV_DAC_NHOLD | - RADEON_TV_MONITOR_DETECT_EN | - RADEON_TV_DAC_STD_PS2; - - OUTREG(RADEON_TV_DAC_CNTL, tmp); - - tmp = RADEON_DAC2_FORCE_BLANK_OFF_EN | - RADEON_DAC2_FORCE_DATA_EN; - - if (color) - tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB; - else - tmp |= RADEON_DAC_FORCE_DATA_SEL_G; - - if (IS_R300_VARIANT) - tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT); - else - tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT); - - OUTREG(RADEON_DAC_EXT_CNTL, tmp); - - tmp = dac_cntl2 | RADEON_DAC2_DAC2_CLK_SEL | RADEON_DAC2_CMP_EN; - OUTREG(RADEON_DAC_CNTL2, tmp); - - usleep(10000); - - if (IS_R300_VARIANT) { - if (INREG(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B) { - found = MT_CRT; - xf86DrvMsg (pScrn->scrnIndex, X_INFO, - "Found %s CRT connected to TV DAC\n", - color ? "color" : "bw"); - } - } else { - if (INREG(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT) { - found = MT_CRT; - xf86DrvMsg (pScrn->scrnIndex, X_INFO, - "Found %s CRT connected to TV DAC\n", - color ? "color" : "bw"); - } - } - - /* restore regs we used */ - OUTREG(RADEON_DAC_CNTL2, dac_cntl2); - OUTREG(RADEON_DAC_EXT_CNTL, dac_ext_cntl); - OUTREG(RADEON_TV_DAC_CNTL, tv_dac_cntl); - OUTREG(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); - - if (IS_R300_VARIANT) { - OUTREG(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); - OUTREGP(RADEON_GPIOPAD_A, gpiopad_a, ~1 ); - } else { - OUTREG(RADEON_DISP_HW_DEBUG, disp_hw_debug); - } - OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, pixclks_cntl); - - return found; -} - -static RADEONMonitorType -r300_detect_tv(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - uint32_t tmp, dac_cntl2, crtc2_gen_cntl, dac_ext_cntl, tv_dac_cntl; - uint32_t gpiopad_a, disp_output_cntl; - RADEONMonitorType found = MT_NONE; - - /* save the regs we need */ - gpiopad_a = INREG(RADEON_GPIOPAD_A); - dac_cntl2 = INREG(RADEON_DAC_CNTL2); - crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL); - dac_ext_cntl = INREG(RADEON_DAC_EXT_CNTL); - tv_dac_cntl = INREG(RADEON_TV_DAC_CNTL); - disp_output_cntl = INREG(RADEON_DISP_OUTPUT_CNTL); - - OUTREGP(RADEON_GPIOPAD_A, 0, ~1 ); - - OUTREG(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL ); - - OUTREG(RADEON_CRTC2_GEN_CNTL, - RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_VSYNC_TRISTAT ); - - tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK; - tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2; - OUTREG(RADEON_DISP_OUTPUT_CNTL, tmp); - - OUTREG(RADEON_DAC_EXT_CNTL, - RADEON_DAC2_FORCE_BLANK_OFF_EN | - RADEON_DAC2_FORCE_DATA_EN | - RADEON_DAC_FORCE_DATA_SEL_RGB | - (0xec << RADEON_DAC_FORCE_DATA_SHIFT )); - - OUTREG(RADEON_TV_DAC_CNTL, - RADEON_TV_DAC_STD_NTSC | - (8 << RADEON_TV_DAC_BGADJ_SHIFT) | - (6 << RADEON_TV_DAC_DACADJ_SHIFT )); - - INREG(RADEON_TV_DAC_CNTL); - - usleep(4000); - - OUTREG(RADEON_TV_DAC_CNTL, - RADEON_TV_DAC_NBLANK | - RADEON_TV_DAC_NHOLD | - RADEON_TV_MONITOR_DETECT_EN | - RADEON_TV_DAC_STD_NTSC | - (8 << RADEON_TV_DAC_BGADJ_SHIFT) | - (6 << RADEON_TV_DAC_DACADJ_SHIFT )); - - INREG(RADEON_TV_DAC_CNTL); - - usleep(6000); - - tmp = INREG(RADEON_TV_DAC_CNTL); - if ( (tmp & RADEON_TV_DAC_GDACDET) != 0 ) { - found = MT_STV; - xf86DrvMsg (pScrn->scrnIndex, X_INFO, - "S-Video TV connection detected\n"); - } else if ( (tmp & RADEON_TV_DAC_BDACDET) != 0 ) { - found = MT_CTV; - xf86DrvMsg (pScrn->scrnIndex, X_INFO, - "Composite TV connection detected\n" ); - } - - OUTREG(RADEON_TV_DAC_CNTL, tv_dac_cntl ); - OUTREG(RADEON_DAC_EXT_CNTL, dac_ext_cntl); - OUTREG(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); - OUTREG(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); - OUTREG(RADEON_DAC_CNTL2, dac_cntl2); - OUTREGP(RADEON_GPIOPAD_A, gpiopad_a, ~1); - - return found; -} - -static RADEONMonitorType -radeon_detect_tv(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - uint32_t tmp, dac_cntl2, tv_master_cntl; - uint32_t tv_dac_cntl, tv_pre_dac_mux_cntl, config_cntl; - RADEONMonitorType found = MT_NONE; - - if (IS_R300_VARIANT) - return r300_detect_tv(pScrn); - - /* save the regs we need */ - dac_cntl2 = INREG(RADEON_DAC_CNTL2); - tv_master_cntl = INREG(RADEON_TV_MASTER_CNTL); - tv_dac_cntl = INREG(RADEON_TV_DAC_CNTL); - config_cntl = INREG(RADEON_CONFIG_CNTL); - tv_pre_dac_mux_cntl = INREG(RADEON_TV_PRE_DAC_MUX_CNTL); - - tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL; - OUTREG(RADEON_DAC_CNTL2, tmp); - - tmp = tv_master_cntl | RADEON_TV_ON; - tmp &= ~(RADEON_TV_ASYNC_RST | - RADEON_RESTART_PHASE_FIX | - RADEON_CRT_FIFO_CE_EN | - RADEON_TV_FIFO_CE_EN | - RADEON_RE_SYNC_NOW_SEL_MASK); - tmp |= RADEON_TV_FIFO_ASYNC_RST | RADEON_CRT_ASYNC_RST; - - OUTREG(RADEON_TV_MASTER_CNTL, tmp); - - tmp = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD | - RADEON_TV_MONITOR_DETECT_EN | RADEON_TV_DAC_STD_NTSC | - (8 << RADEON_TV_DAC_BGADJ_SHIFT); - - if (config_cntl & RADEON_CFG_ATI_REV_ID_MASK) - tmp |= (4 << RADEON_TV_DAC_DACADJ_SHIFT); - else - tmp |= (8 << RADEON_TV_DAC_DACADJ_SHIFT); - - OUTREG(RADEON_TV_DAC_CNTL, tmp); - - tmp = RADEON_C_GRN_EN | RADEON_CMP_BLU_EN | - RADEON_RED_MX_FORCE_DAC_DATA | - RADEON_GRN_MX_FORCE_DAC_DATA | - RADEON_BLU_MX_FORCE_DAC_DATA | - (0x109 << RADEON_TV_FORCE_DAC_DATA_SHIFT); - - OUTREG(RADEON_TV_PRE_DAC_MUX_CNTL, tmp); - - usleep(3000); - - tmp = INREG(RADEON_TV_DAC_CNTL); - if (tmp & RADEON_TV_DAC_GDACDET) { - found = MT_STV; - xf86DrvMsg (pScrn->scrnIndex, X_INFO, - "S-Video TV connection detected\n"); - } else if (tmp & RADEON_TV_DAC_BDACDET) { - found = MT_CTV; - xf86DrvMsg (pScrn->scrnIndex, X_INFO, - "Composite TV connection detected\n" ); - } - - OUTREG(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl); - OUTREG(RADEON_TV_DAC_CNTL, tv_dac_cntl); - OUTREG(RADEON_TV_MASTER_CNTL, tv_master_cntl); - OUTREG(RADEON_DAC_CNTL2, dac_cntl2); - - return found; -} diff --git a/src/r600_exa.c b/src/r600_exa.c index 470de010..f0fe62a4 100644 --- a/src/r600_exa.c +++ b/src/r600_exa.c @@ -54,18 +54,13 @@ R600SetAccelState(ScrnInfoPtr pScrn, RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; uint32_t pitch_align = 0x7, base_align = 0xff; -#if defined(XF86DRM_MODE) int ret; -#endif if (src0) { memcpy(&accel_state->src_obj[0], src0, sizeof(struct r600_accel_object)); accel_state->src_size[0] = src0->pitch * src0->height * (src0->bpp/8); -#if defined(XF86DRM_MODE) - if (info->cs && src0->surface) { + if (src0->surface) accel_state->src_size[0] = src0->surface->bo_size; - } -#endif /* bad pitch */ if (accel_state->src_obj[0].pitch & pitch_align) @@ -83,11 +78,9 @@ R600SetAccelState(ScrnInfoPtr pScrn, if (src1) { memcpy(&accel_state->src_obj[1], src1, sizeof(struct r600_accel_object)); accel_state->src_size[1] = src1->pitch * src1->height * (src1->bpp/8); -#if defined(XF86DRM_MODE) - if (info->cs && src1->surface) { + if (src1->surface) { accel_state->src_size[1] = src1->surface->bo_size; } -#endif /* bad pitch */ if (accel_state->src_obj[1].pitch & pitch_align) @@ -104,11 +97,9 @@ R600SetAccelState(ScrnInfoPtr pScrn, if (dst) { memcpy(&accel_state->dst_obj, dst, sizeof(struct r600_accel_object)); accel_state->dst_size = dst->pitch * dst->height * (dst->bpp/8); -#if defined(XF86DRM_MODE) - if (info->cs && dst->surface) { + if (dst->surface) { accel_state->dst_size = dst->surface->bo_size; } else -#endif { accel_state->dst_obj.tiling_flags = 0; } @@ -122,45 +113,32 @@ R600SetAccelState(ScrnInfoPtr pScrn, accel_state->dst_size = 0; } -#ifdef XF86DRM_MODE - if (info->cs && CS_FULL(info->cs)) + if (CS_FULL(info->cs)) radeon_cs_flush_indirect(pScrn); -#endif accel_state->rop = rop; accel_state->planemask = planemask; accel_state->vs_size = 512; accel_state->ps_size = 512; -#if defined(XF86DRM_MODE) - if (info->cs) { - accel_state->vs_mc_addr = vs_offset; - accel_state->ps_mc_addr = ps_offset; - - radeon_cs_space_reset_bos(info->cs); - radeon_cs_space_add_persistent_bo(info->cs, accel_state->shaders_bo, - RADEON_GEM_DOMAIN_VRAM, 0); - if (accel_state->src_obj[0].bo) - radeon_cs_space_add_persistent_bo(info->cs, accel_state->src_obj[0].bo, - accel_state->src_obj[0].domain, 0); - if (accel_state->src_obj[1].bo) - radeon_cs_space_add_persistent_bo(info->cs, accel_state->src_obj[1].bo, - accel_state->src_obj[1].domain, 0); - if (accel_state->dst_obj.bo) - radeon_cs_space_add_persistent_bo(info->cs, accel_state->dst_obj.bo, - 0, accel_state->dst_obj.domain); - ret = radeon_cs_space_check(info->cs); - if (ret) - RADEON_FALLBACK(("Not enough RAM to hw accel operation\n")); + accel_state->vs_mc_addr = vs_offset; + accel_state->ps_mc_addr = ps_offset; - } else -#endif - { - accel_state->vs_mc_addr = info->fbLocation + pScrn->fbOffset + accel_state->shaders->offset + - vs_offset; - accel_state->ps_mc_addr = info->fbLocation + pScrn->fbOffset + accel_state->shaders->offset + - ps_offset; - } + radeon_cs_space_reset_bos(info->cs); + radeon_cs_space_add_persistent_bo(info->cs, accel_state->shaders_bo, + RADEON_GEM_DOMAIN_VRAM, 0); + if (accel_state->src_obj[0].bo) + radeon_cs_space_add_persistent_bo(info->cs, accel_state->src_obj[0].bo, + accel_state->src_obj[0].domain, 0); + if (accel_state->src_obj[1].bo) + radeon_cs_space_add_persistent_bo(info->cs, accel_state->src_obj[1].bo, + accel_state->src_obj[1].domain, 0); + if (accel_state->dst_obj.bo) + radeon_cs_space_add_persistent_bo(info->cs, accel_state->dst_obj.bo, + 0, accel_state->dst_obj.domain); + ret = radeon_cs_space_check(info->cs); + if (ret) + RADEON_FALLBACK(("Not enough RAM to hw accel operation\n")); return TRUE; } @@ -182,18 +160,10 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg) if (!RADEONValidPM(pm, pPix->drawable.bitsPerPixel)) RADEON_FALLBACK(("invalid planemask\n")); -#if defined(XF86DRM_MODE) - if (info->cs) { - dst.offset = 0; - dst.bo = radeon_get_pixmap_bo(pPix); - dst.tiling_flags = radeon_get_pixmap_tiling(pPix); - dst.surface = radeon_get_pixmap_surface(pPix); - } else -#endif - { - dst.offset = exaGetPixmapOffset(pPix) + info->fbLocation + pScrn->fbOffset; - dst.bo = NULL; - } + dst.offset = 0; + dst.bo = radeon_get_pixmap_bo(pPix); + dst.tiling_flags = radeon_get_pixmap_tiling(pPix); + dst.surface = radeon_get_pixmap_surface(pPix); dst.pitch = exaGetPixmapPitch(pPix) / (pPix->drawable.bitsPerPixel / 8); dst.width = pPix->drawable.width; @@ -216,11 +186,11 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg) radeon_vbo_check(pScrn, &accel_state->vbo, 16); radeon_cp_start(pScrn); - r600_set_default_state(pScrn, accel_state->ib); + r600_set_default_state(pScrn); - r600_set_generic_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); - r600_set_screen_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); - r600_set_window_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); + r600_set_generic_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); + r600_set_screen_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); + r600_set_window_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); /* Shader */ vs_conf.shader_addr = accel_state->vs_mc_addr; @@ -228,7 +198,7 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg) vs_conf.num_gprs = 2; vs_conf.stack_size = 0; vs_conf.bo = accel_state->shaders_bo; - r600_vs_setup(pScrn, accel_state->ib, &vs_conf, RADEON_GEM_DOMAIN_VRAM); + r600_vs_setup(pScrn, &vs_conf, RADEON_GEM_DOMAIN_VRAM); ps_conf.shader_addr = accel_state->ps_mc_addr; ps_conf.shader_size = accel_state->ps_size; @@ -238,16 +208,14 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg) ps_conf.clamp_consts = 0; ps_conf.export_mode = 2; ps_conf.bo = accel_state->shaders_bo; - r600_ps_setup(pScrn, accel_state->ib, &ps_conf, RADEON_GEM_DOMAIN_VRAM); + r600_ps_setup(pScrn, &ps_conf, RADEON_GEM_DOMAIN_VRAM); cb_conf.id = 0; cb_conf.w = accel_state->dst_obj.pitch; cb_conf.h = accel_state->dst_obj.height; cb_conf.base = accel_state->dst_obj.offset; cb_conf.bo = accel_state->dst_obj.bo; -#ifdef XF86DRM_MODE cb_conf.surface = accel_state->dst_obj.surface; -#endif if (accel_state->dst_obj.bpp == 8) { cb_conf.format = COLOR_8; @@ -279,9 +247,9 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg) cb_conf.rop = accel_state->rop; if (accel_state->dst_obj.tiling_flags == 0) cb_conf.array_mode = 0; - r600_set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain); + r600_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain); - r600_set_spi(pScrn, accel_state->ib, 0, 0); + r600_set_spi(pScrn, 0, 0); /* PS alu constants */ if (accel_state->dst_obj.bpp == 16) { @@ -308,7 +276,7 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg) ps_alu_consts[2] = (float)b / 255; /* B */ ps_alu_consts[3] = (float)a / 255; /* A */ } - r600_set_alu_consts(pScrn, accel_state->ib, SQ_ALU_CONSTANT_ps, + r600_set_alu_consts(pScrn, SQ_ALU_CONSTANT_ps, sizeof(ps_alu_consts) / SQ_ALU_CONSTANT_offset, ps_alu_consts); if (accel_state->vsync) @@ -328,7 +296,7 @@ R600DoneSolid(PixmapPtr pPix) struct radeon_accel_state *accel_state = info->accel_state; if (accel_state->vsync) - r600_cp_wait_vline_sync(pScrn, accel_state->ib, pPix, + r600_cp_wait_vline_sync(pScrn, pPix, accel_state->vline_crtc, accel_state->vline_y1, accel_state->vline_y2); @@ -344,8 +312,7 @@ R600Solid(PixmapPtr pPix, int x1, int y1, int x2, int y2) struct radeon_accel_state *accel_state = info->accel_state; float *vb; -#ifdef XF86DRM_MODE - if (info->cs && CS_FULL(info->cs)) { + if (CS_FULL(info->cs)) { R600DoneSolid(info->accel_state->dst_pix); radeon_cs_flush_indirect(pScrn); R600PrepareSolid(accel_state->dst_pix, @@ -353,7 +320,6 @@ R600Solid(PixmapPtr pPix, int x1, int y1, int x2, int y2) accel_state->planemask, accel_state->fg); } -#endif if (accel_state->vsync) RADEONVlineHelperSet(pScrn, x1, y1, x2, y2); @@ -391,11 +357,11 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn) radeon_vbo_check(pScrn, &accel_state->vbo, 16); radeon_cp_start(pScrn); - r600_set_default_state(pScrn, accel_state->ib); + r600_set_default_state(pScrn); - r600_set_generic_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); - r600_set_screen_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); - r600_set_window_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); + r600_set_generic_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); + r600_set_screen_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); + r600_set_window_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); /* Shader */ vs_conf.shader_addr = accel_state->vs_mc_addr; @@ -403,7 +369,7 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn) vs_conf.num_gprs = 2; vs_conf.stack_size = 0; vs_conf.bo = accel_state->shaders_bo; - r600_vs_setup(pScrn, accel_state->ib, &vs_conf, RADEON_GEM_DOMAIN_VRAM); + r600_vs_setup(pScrn, &vs_conf, RADEON_GEM_DOMAIN_VRAM); ps_conf.shader_addr = accel_state->ps_mc_addr; ps_conf.shader_size = accel_state->ps_size; @@ -413,7 +379,7 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn) ps_conf.clamp_consts = 0; ps_conf.export_mode = 2; ps_conf.bo = accel_state->shaders_bo; - r600_ps_setup(pScrn, accel_state->ib, &ps_conf, RADEON_GEM_DOMAIN_VRAM); + r600_ps_setup(pScrn, &ps_conf, RADEON_GEM_DOMAIN_VRAM); /* Texture */ tex_res.id = 0; @@ -427,9 +393,7 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn) tex_res.size = accel_state->src_size[0]; tex_res.bo = accel_state->src_obj[0].bo; tex_res.mip_bo = accel_state->src_obj[0].bo; -#ifdef XF86DRM_MODE tex_res.surface = accel_state->src_obj[0].surface; -#endif if (accel_state->src_obj[0].bpp == 8) { tex_res.format = FMT_8; tex_res.dst_sel_x = SQ_SEL_1; /* R */ @@ -456,7 +420,7 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn) tex_res.perf_modulation = 0; if (accel_state->src_obj[0].tiling_flags == 0) tex_res.tile_mode = 1; - r600_set_tex_resource(pScrn, accel_state->ib, &tex_res, accel_state->src_obj[0].domain); + r600_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain); tex_samp.id = 0; tex_samp.clamp_x = SQ_TEX_CLAMP_LAST_TEXEL; @@ -467,16 +431,14 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn) tex_samp.mc_coord_truncate = 1; tex_samp.z_filter = SQ_TEX_Z_FILTER_NONE; tex_samp.mip_filter = 0; /* no mipmap */ - r600_set_tex_sampler(pScrn, accel_state->ib, &tex_samp); + r600_set_tex_sampler(pScrn, &tex_samp); cb_conf.id = 0; cb_conf.w = accel_state->dst_obj.pitch; cb_conf.h = accel_state->dst_obj.height; cb_conf.base = accel_state->dst_obj.offset; cb_conf.bo = accel_state->dst_obj.bo; -#ifdef XF86DRM_MODE cb_conf.surface = accel_state->dst_obj.surface; -#endif if (accel_state->dst_obj.bpp == 8) { cb_conf.format = COLOR_8; cb_conf.comp_swap = 3; /* A */ @@ -502,9 +464,9 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn) cb_conf.rop = accel_state->rop; if (accel_state->dst_obj.tiling_flags == 0) cb_conf.array_mode = 0; - r600_set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain); + r600_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain); - r600_set_spi(pScrn, accel_state->ib, (1 - 1), 1); + r600_set_spi(pScrn, (1 - 1), 1); } @@ -522,7 +484,7 @@ R600DoCopyVline(PixmapPtr pPix) struct radeon_accel_state *accel_state = info->accel_state; if (accel_state->vsync) - r600_cp_wait_vline_sync(pScrn, accel_state->ib, pPix, + r600_cp_wait_vline_sync(pScrn, pPix, accel_state->vline_crtc, accel_state->vline_y1, accel_state->vline_y2); @@ -583,28 +545,16 @@ R600PrepareCopy(PixmapPtr pSrc, PixmapPtr pDst, accel_state->same_surface = FALSE; -#if defined(XF86DRM_MODE) - if (info->cs) { - src_obj.offset = 0; - dst_obj.offset = 0; - src_obj.bo = radeon_get_pixmap_bo(pSrc); - dst_obj.bo = radeon_get_pixmap_bo(pDst); - dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst); - src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc); - src_obj.surface = radeon_get_pixmap_surface(pSrc); - dst_obj.surface = radeon_get_pixmap_surface(pDst); - if (radeon_get_pixmap_bo(pSrc) == radeon_get_pixmap_bo(pDst)) - accel_state->same_surface = TRUE; - } else -#endif - { - src_obj.offset = exaGetPixmapOffset(pSrc) + info->fbLocation + pScrn->fbOffset; - dst_obj.offset = exaGetPixmapOffset(pDst) + info->fbLocation + pScrn->fbOffset; - if (exaGetPixmapOffset(pSrc) == exaGetPixmapOffset(pDst)) - accel_state->same_surface = TRUE; - src_obj.bo = NULL; - dst_obj.bo = NULL; - } + src_obj.offset = 0; + dst_obj.offset = 0; + src_obj.bo = radeon_get_pixmap_bo(pSrc); + dst_obj.bo = radeon_get_pixmap_bo(pDst); + dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst); + src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc); + src_obj.surface = radeon_get_pixmap_surface(pSrc); + dst_obj.surface = radeon_get_pixmap_surface(pDst); + if (radeon_get_pixmap_bo(pSrc) == radeon_get_pixmap_bo(pDst)) + accel_state->same_surface = TRUE; src_obj.width = pSrc->drawable.width; src_obj.height = pSrc->drawable.height; @@ -625,45 +575,27 @@ R600PrepareCopy(PixmapPtr pSrc, PixmapPtr pDst, return FALSE; if (accel_state->same_surface == TRUE) { -#if defined(XF86DRM_MODE) unsigned long size = accel_state->dst_obj.surface->bo_size; unsigned long align = accel_state->dst_obj.surface->bo_alignment; -#else - unsigned height = pDst->drawable.height; - unsigned long size = height * accel_state->dst_obj.pitch * pDst->drawable.bitsPerPixel/8; -#endif -#if defined(XF86DRM_MODE) - if (info->cs) { - if (accel_state->copy_area_bo) { - radeon_bo_unref(accel_state->copy_area_bo); - accel_state->copy_area_bo = NULL; - } - accel_state->copy_area_bo = radeon_bo_open(info->bufmgr, 0, size, align, - RADEON_GEM_DOMAIN_VRAM, - 0); - if (accel_state->copy_area_bo == NULL) - RADEON_FALLBACK(("temp copy surface alloc failed\n")); - - radeon_cs_space_add_persistent_bo(info->cs, accel_state->copy_area_bo, - 0, RADEON_GEM_DOMAIN_VRAM); - if (radeon_cs_space_check(info->cs)) { - radeon_bo_unref(accel_state->copy_area_bo); - accel_state->copy_area_bo = NULL; - return FALSE; - } - accel_state->copy_area = (void*)accel_state->copy_area_bo; - } else -#endif - { - if (accel_state->copy_area) { - exaOffscreenFree(pDst->drawable.pScreen, accel_state->copy_area); - accel_state->copy_area = NULL; - } - accel_state->copy_area = exaOffscreenAlloc(pDst->drawable.pScreen, size, 256, TRUE, NULL, NULL); - if (!accel_state->copy_area) - RADEON_FALLBACK(("temp copy surface alloc failed\n")); + if (accel_state->copy_area_bo) { + radeon_bo_unref(accel_state->copy_area_bo); + accel_state->copy_area_bo = NULL; } + accel_state->copy_area_bo = radeon_bo_open(info->bufmgr, 0, size, align, + RADEON_GEM_DOMAIN_VRAM, + 0); + if (accel_state->copy_area_bo == NULL) + RADEON_FALLBACK(("temp copy surface alloc failed\n")); + + radeon_cs_space_add_persistent_bo(info->cs, accel_state->copy_area_bo, + 0, RADEON_GEM_DOMAIN_VRAM); + if (radeon_cs_space_check(info->cs)) { + radeon_bo_unref(accel_state->copy_area_bo); + accel_state->copy_area_bo = NULL; + return FALSE; + } + accel_state->copy_area = (void*)accel_state->copy_area_bo; } else R600DoPrepareCopy(pScrn); @@ -689,8 +621,6 @@ R600DoneCopy(PixmapPtr pDst) R600DoCopyVline(pDst); if (accel_state->copy_area) { - if (!info->cs) - exaOffscreenFree(pDst->drawable.pScreen, accel_state->copy_area); accel_state->copy_area = NULL; } @@ -709,8 +639,7 @@ R600Copy(PixmapPtr pDst, if (accel_state->same_surface && (srcX == dstX) && (srcY == dstY)) return; -#ifdef XF86DRM_MODE - if (info->cs && CS_FULL(info->cs)) { + if (CS_FULL(info->cs)) { R600DoneCopy(info->accel_state->dst_pix); radeon_cs_flush_indirect(pScrn); R600PrepareCopy(accel_state->src_pix, @@ -720,7 +649,6 @@ R600Copy(PixmapPtr pDst, accel_state->rop, accel_state->planemask); } -#endif if (accel_state->vsync) RADEONVlineHelperSet(pScrn, dstX, dstY, dstX + w, dstY + h); @@ -734,16 +662,8 @@ R600Copy(PixmapPtr pDst, struct radeon_bo *orig_bo = accel_state->dst_obj.bo; int orig_rop = accel_state->rop; -#if defined(XF86DRM_MODE) - if (info->cs) { - tmp_offset = 0; - orig_offset = 0; - } else -#endif - { - tmp_offset = accel_state->copy_area->offset + info->fbLocation + pScrn->fbOffset; - orig_offset = exaGetPixmapOffset(pDst) + info->fbLocation + pScrn->fbOffset; - } + tmp_offset = 0; + orig_offset = 0; /* src to tmp */ accel_state->dst_obj.domain = RADEON_GEM_DOMAIN_VRAM; @@ -977,9 +897,7 @@ static Bool R600TextureSetup(PicturePtr pPict, PixmapPtr pPix, tex_res.format = R600TexFormats[i].card_fmt; tex_res.bo = accel_state->src_obj[unit].bo; tex_res.mip_bo = accel_state->src_obj[unit].bo; -#ifdef XF86DRM_MODE tex_res.surface = accel_state->src_obj[unit].surface; -#endif tex_res.request_size = 1; #if X_BYTE_ORDER == X_BIG_ENDIAN @@ -1114,7 +1032,7 @@ static Bool R600TextureSetup(PicturePtr pPict, PixmapPtr pPix, tex_res.perf_modulation = 0; if (accel_state->src_obj[unit].tiling_flags == 0) tex_res.tile_mode = 1; - r600_set_tex_resource(pScrn, accel_state->ib, &tex_res, accel_state->src_obj[unit].domain); + r600_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[unit].domain); tex_samp.id = unit; tex_samp.border_color = SQ_TEX_BORDER_COLOR_TRANS_BLACK; @@ -1157,7 +1075,7 @@ static Bool R600TextureSetup(PicturePtr pPict, PixmapPtr pPix, tex_samp.clamp_z = SQ_TEX_WRAP; tex_samp.z_filter = SQ_TEX_Z_FILTER_NONE; tex_samp.mip_filter = 0; /* no mipmap */ - r600_set_tex_sampler(pScrn, accel_state->ib, &tex_samp); + r600_set_tex_sampler(pScrn, &tex_samp); if (pPict->transform != 0) { accel_state->is_transform[unit] = TRUE; @@ -1187,7 +1105,7 @@ static Bool R600TextureSetup(PicturePtr pPict, PixmapPtr pPix, } /* VS alu constants */ - r600_set_alu_consts(pScrn, accel_state->ib, SQ_ALU_CONSTANT_vs + (unit * 2), + r600_set_alu_consts(pScrn, SQ_ALU_CONSTANT_vs + (unit * 2), sizeof(vs_alu_consts) / SQ_ALU_CONSTANT_offset, vs_alu_consts); return TRUE; @@ -1288,24 +1206,15 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture, RADEON_FALLBACK("Failed to create solid scratch pixmap\n"); } -#if defined(XF86DRM_MODE) - if (info->cs) { - src_obj.offset = 0; - dst_obj.offset = 0; - dst_obj.bo = radeon_get_pixmap_bo(pDst); - src_obj.bo = radeon_get_pixmap_bo(pSrc); - dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst); - src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc); - dst_obj.surface = radeon_get_pixmap_surface(pDst); - src_obj.surface = radeon_get_pixmap_surface(pSrc); - } else -#endif - { - src_obj.offset = exaGetPixmapOffset(pSrc) + info->fbLocation + pScrn->fbOffset; - dst_obj.offset = exaGetPixmapOffset(pDst) + info->fbLocation + pScrn->fbOffset; - src_obj.bo = NULL; - dst_obj.bo = NULL; - } + src_obj.offset = 0; + dst_obj.offset = 0; + dst_obj.bo = radeon_get_pixmap_bo(pDst); + src_obj.bo = radeon_get_pixmap_bo(pSrc); + dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst); + src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc); + dst_obj.surface = radeon_get_pixmap_surface(pDst); + src_obj.surface = radeon_get_pixmap_surface(pSrc); + src_obj.pitch = exaGetPixmapPitch(pSrc) / (pSrc->drawable.bitsPerPixel / 8); dst_obj.pitch = exaGetPixmapPitch(pDst) / (pDst->drawable.bitsPerPixel / 8); @@ -1329,18 +1238,11 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture, } } -#if defined(XF86DRM_MODE) - if (info->cs) { - mask_obj.offset = 0; - mask_obj.bo = radeon_get_pixmap_bo(pMask); - mask_obj.tiling_flags = radeon_get_pixmap_tiling(pMask); - mask_obj.surface = radeon_get_pixmap_surface(pMask); - } else -#endif - { - mask_obj.offset = exaGetPixmapOffset(pMask) + info->fbLocation + pScrn->fbOffset; - mask_obj.bo = NULL; - } + mask_obj.offset = 0; + mask_obj.bo = radeon_get_pixmap_bo(pMask); + mask_obj.tiling_flags = radeon_get_pixmap_tiling(pMask); + mask_obj.surface = radeon_get_pixmap_surface(pMask); + mask_obj.pitch = exaGetPixmapPitch(pMask) / (pMask->drawable.bitsPerPixel / 8); mask_obj.width = pMask->drawable.width; @@ -1395,31 +1297,31 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture, radeon_cp_start(pScrn); - r600_set_default_state(pScrn, accel_state->ib); + r600_set_default_state(pScrn); - r600_set_generic_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); - r600_set_screen_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); - r600_set_window_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); + r600_set_generic_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); + r600_set_screen_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); + r600_set_window_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); if (!R600TextureSetup(pSrcPicture, pSrc, 0)) { - R600IBDiscard(pScrn, accel_state->ib); + R600IBDiscard(pScrn); return FALSE; } if (pMask) { if (!R600TextureSetup(pMaskPicture, pMask, 1)) { - R600IBDiscard(pScrn, accel_state->ib); + R600IBDiscard(pScrn); return FALSE; } } else accel_state->is_transform[1] = FALSE; if (pMask) { - r600_set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_vs, (1 << 0)); - r600_set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_ps, (1 << 0)); + r600_set_bool_consts(pScrn, SQ_BOOL_CONST_vs, (1 << 0)); + r600_set_bool_consts(pScrn, SQ_BOOL_CONST_ps, (1 << 0)); } else { - r600_set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_vs, (0 << 0)); - r600_set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_ps, (0 << 0)); + r600_set_bool_consts(pScrn, SQ_BOOL_CONST_vs, (0 << 0)); + r600_set_bool_consts(pScrn, SQ_BOOL_CONST_ps, (0 << 0)); } /* Shader */ @@ -1428,7 +1330,7 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture, vs_conf.num_gprs = 5; vs_conf.stack_size = 1; vs_conf.bo = accel_state->shaders_bo; - r600_vs_setup(pScrn, accel_state->ib, &vs_conf, RADEON_GEM_DOMAIN_VRAM); + r600_vs_setup(pScrn, &vs_conf, RADEON_GEM_DOMAIN_VRAM); ps_conf.shader_addr = accel_state->ps_mc_addr; ps_conf.shader_size = accel_state->ps_size; @@ -1438,7 +1340,7 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture, ps_conf.clamp_consts = 0; ps_conf.export_mode = 2; ps_conf.bo = accel_state->shaders_bo; - r600_ps_setup(pScrn, accel_state->ib, &ps_conf, RADEON_GEM_DOMAIN_VRAM); + r600_ps_setup(pScrn, &ps_conf, RADEON_GEM_DOMAIN_VRAM); cb_conf.id = 0; cb_conf.w = accel_state->dst_obj.pitch; @@ -1446,9 +1348,7 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture, cb_conf.base = accel_state->dst_obj.offset; cb_conf.format = dst_format; cb_conf.bo = accel_state->dst_obj.bo; -#ifdef XF86DRM_MODE cb_conf.surface = accel_state->dst_obj.surface; -#endif switch (pDstPicture->format) { case PICT_a8r8g8b8: @@ -1495,12 +1395,12 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture, break; } #endif - r600_set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain); + r600_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain); if (pMask) - r600_set_spi(pScrn, accel_state->ib, (2 - 1), 2); + r600_set_spi(pScrn, (2 - 1), 2); else - r600_set_spi(pScrn, accel_state->ib, (1 - 1), 1); + r600_set_spi(pScrn, (1 - 1), 1); if (accel_state->vsync) RADEONVlineHelperClear(pScrn); @@ -1521,7 +1421,7 @@ static void R600FinishComposite(ScrnInfoPtr pScrn, PixmapPtr pDst, int vtx_size; if (accel_state->vsync) - r600_cp_wait_vline_sync(pScrn, accel_state->ib, pDst, + r600_cp_wait_vline_sync(pScrn, pDst, accel_state->vline_crtc, accel_state->vline_y1, accel_state->vline_y2); @@ -1561,8 +1461,7 @@ static void R600Composite(PixmapPtr pDst, /* ErrorF("R600Composite (%d,%d) (%d,%d) (%d,%d) (%d,%d)\n", srcX, srcY, maskX, maskY,dstX, dstY, w, h); */ -#ifdef XF86DRM_MODE - if (info->cs && CS_FULL(info->cs)) { + if (CS_FULL(info->cs)) { R600FinishComposite(pScrn, pDst, info->accel_state); radeon_cs_flush_indirect(pScrn); R600PrepareComposite(info->accel_state->composite_op, @@ -1573,7 +1472,6 @@ static void R600Composite(PixmapPtr pDst, info->accel_state->msk_pix, info->accel_state->dst_pix); } -#endif if (accel_state->vsync) RADEONVlineHelperSet(pScrn, dstX, dstY, dstX + w, dstY + h); @@ -1630,216 +1528,6 @@ static void R600Composite(PixmapPtr pDst, } -Bool -R600CopyToVRAM(ScrnInfoPtr pScrn, - char *src, int src_pitch, - uint32_t dst_pitch, uint32_t dst_mc_addr, uint32_t dst_width, uint32_t dst_height, int bpp, - int x, int y, int w, int h) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - struct radeon_accel_state *accel_state = info->accel_state; - uint32_t scratch_mc_addr; - int wpass = w * (bpp/8); - int scratch_pitch_bytes = RADEON_ALIGN(wpass, 256); - uint32_t scratch_pitch = scratch_pitch_bytes / (bpp / 8); - int scratch_offset = 0, hpass, temph; - char *dst; - drmBufPtr scratch; - struct r600_accel_object scratch_obj, dst_obj; - - if (dst_pitch & 7) - return FALSE; - - if (dst_mc_addr & 0xff) - return FALSE; - - scratch = RADEONCPGetBuffer(pScrn); - if (scratch == NULL) - return FALSE; - - scratch_mc_addr = info->gartLocation + info->dri->bufStart + (scratch->idx * scratch->total); - temph = hpass = min(h, scratch->total/2 / scratch_pitch_bytes); - dst = (char *)scratch->address; - - scratch_obj.pitch = scratch_pitch; - scratch_obj.width = w; - scratch_obj.height = hpass; - scratch_obj.offset = scratch_mc_addr; - scratch_obj.bpp = bpp; - scratch_obj.domain = RADEON_GEM_DOMAIN_GTT; - scratch_obj.bo = NULL; - - dst_obj.pitch = dst_pitch; - dst_obj.width = dst_width; - dst_obj.height = dst_height; - dst_obj.offset = dst_mc_addr; - dst_obj.bo = NULL; - dst_obj.bpp = bpp; - dst_obj.domain = RADEON_GEM_DOMAIN_VRAM; - - if (!R600SetAccelState(pScrn, - &scratch_obj, - NULL, - &dst_obj, - accel_state->copy_vs_offset, accel_state->copy_ps_offset, - 3, 0xffffffff)) - return FALSE; - - /* memcopy from sys to scratch */ - while (temph--) { - memcpy (dst, src, wpass); - src += src_pitch; - dst += scratch_pitch_bytes; - } - - while (h) { - uint32_t offset = scratch_mc_addr + scratch_offset; - int oldhpass = hpass; - h -= oldhpass; - temph = hpass = min(h, scratch->total/2 / scratch_pitch_bytes); - - if (hpass) { - scratch_offset = scratch->total/2 - scratch_offset; - dst = (char *)scratch->address + scratch_offset; - /* wait for the engine to be idle */ - RADEONWaitForIdleCP(pScrn); - //memcopy from sys to scratch - while (temph--) { - memcpy (dst, src, wpass); - src += src_pitch; - dst += scratch_pitch_bytes; - } - } - /* blit from scratch to vram */ - info->accel_state->src_obj[0].height = oldhpass; - info->accel_state->src_obj[0].offset = offset; - R600DoPrepareCopy(pScrn); - R600AppendCopyVertex(pScrn, 0, 0, x, y, w, oldhpass); - R600DoCopy(pScrn); - y += oldhpass; - } - - R600IBDiscard(pScrn, scratch); - - return TRUE; -} - -static Bool -R600UploadToScreen(PixmapPtr pDst, int x, int y, int w, int h, - char *src, int src_pitch) -{ - ScrnInfoPtr pScrn = xf86ScreenToScrn(pDst->drawable.pScreen); - RADEONInfoPtr info = RADEONPTR(pScrn); - uint32_t dst_pitch = exaGetPixmapPitch(pDst) / (pDst->drawable.bitsPerPixel / 8); - uint32_t dst_mc_addr = exaGetPixmapOffset(pDst) + info->fbLocation + pScrn->fbOffset; - int bpp = pDst->drawable.bitsPerPixel; - - return R600CopyToVRAM(pScrn, - src, src_pitch, - dst_pitch, dst_mc_addr, pDst->drawable.width, pDst->drawable.height, bpp, - x, y, w, h); -} - -static Bool -R600DownloadFromScreen(PixmapPtr pSrc, int x, int y, int w, int h, - char *dst, int dst_pitch) -{ - ScrnInfoPtr pScrn = xf86ScreenToScrn(pSrc->drawable.pScreen); - RADEONInfoPtr info = RADEONPTR(pScrn); - struct radeon_accel_state *accel_state = info->accel_state; - uint32_t src_pitch = exaGetPixmapPitch(pSrc) / (pSrc->drawable.bitsPerPixel / 8); - uint32_t src_mc_addr = exaGetPixmapOffset(pSrc) + info->fbLocation + pScrn->fbOffset; - uint32_t src_width = pSrc->drawable.width; - uint32_t src_height = pSrc->drawable.height; - int bpp = pSrc->drawable.bitsPerPixel; - uint32_t scratch_mc_addr; - int scratch_pitch_bytes = RADEON_ALIGN(dst_pitch, 256); - int scratch_offset = 0, hpass; - uint32_t scratch_pitch = scratch_pitch_bytes / (bpp / 8); - int wpass = w * (bpp/8); - drmBufPtr scratch; - struct r600_accel_object scratch_obj, src_obj; - - /* bad pipe setup in drm prior to 1.32 */ - if (info->dri->pKernelDRMVersion->version_minor < 32) { - if ((info->ChipFamily == CHIP_FAMILY_RV740) && (w < 32 || h < 32)) - return FALSE; - } - - if (src_pitch & 7) - return FALSE; - - scratch = RADEONCPGetBuffer(pScrn); - if (scratch == NULL) - return FALSE; - - scratch_mc_addr = info->gartLocation + info->dri->bufStart + (scratch->idx * scratch->total); - hpass = min(h, scratch->total/2 / scratch_pitch_bytes); - - src_obj.pitch = src_pitch; - src_obj.width = src_width; - src_obj.height = src_height; - src_obj.offset = src_mc_addr; - src_obj.bo = NULL; - src_obj.bpp = bpp; - src_obj.domain = RADEON_GEM_DOMAIN_VRAM; - - scratch_obj.pitch = scratch_pitch; - scratch_obj.width = src_width; - scratch_obj.height = hpass; - scratch_obj.offset = scratch_mc_addr; - scratch_obj.bpp = bpp; - scratch_obj.domain = RADEON_GEM_DOMAIN_GTT; - scratch_obj.bo = NULL; - - if (!R600SetAccelState(pScrn, - &src_obj, - NULL, - &scratch_obj, - accel_state->copy_vs_offset, accel_state->copy_ps_offset, - 3, 0xffffffff)) - return FALSE; - - /* blit from vram to scratch */ - R600DoPrepareCopy(pScrn); - R600AppendCopyVertex(pScrn, x, y, 0, 0, w, hpass); - R600DoCopy(pScrn); - - while (h) { - char *src = (char *)scratch->address + scratch_offset; - int oldhpass = hpass; - h -= oldhpass; - y += oldhpass; - hpass = min(h, scratch->total/2 / scratch_pitch_bytes); - - if (hpass) { - scratch_offset = scratch->total/2 - scratch_offset; - /* blit from vram to scratch */ - info->accel_state->dst_obj.height = hpass; - info->accel_state->dst_obj.offset = scratch_mc_addr + scratch_offset; - R600DoPrepareCopy(pScrn); - R600AppendCopyVertex(pScrn, x, y, 0, 0, w, hpass); - R600DoCopy(pScrn); - } - - /* wait for the engine to be idle */ - RADEONWaitForIdleCP(pScrn); - /* memcopy from scratch to sys */ - while (oldhpass--) { - memcpy (dst, src, wpass); - dst += dst_pitch; - src += scratch_pitch_bytes; - } - } - - R600IBDiscard(pScrn, scratch); - - return TRUE; - -} - -#if defined(XF86DRM_MODE) - static Bool R600UploadToScreenCS(PixmapPtr pDst, int x, int y, int w, int h, char *src, int src_pitch) @@ -1899,9 +1587,7 @@ R600UploadToScreenCS(PixmapPtr pDst, int x, int y, int w, int h, src_obj.domain = RADEON_GEM_DOMAIN_GTT; src_obj.bo = scratch; src_obj.tiling_flags = 0; -#ifdef XF86DRM_MODE src_obj.surface = NULL; -#endif dst_obj.pitch = dst_pitch_hw; dst_obj.width = pDst->drawable.width; @@ -1911,9 +1597,7 @@ R600UploadToScreenCS(PixmapPtr pDst, int x, int y, int w, int h, dst_obj.domain = RADEON_GEM_DOMAIN_VRAM; dst_obj.bo = radeon_get_pixmap_bo(pDst); dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst); -#ifdef XF86DRM_MODE dst_obj.surface = radeon_get_pixmap_surface(pDst); -#endif if (!R600SetAccelState(pScrn, &src_obj, @@ -2040,9 +1724,7 @@ R600DownloadFromScreenCS(PixmapPtr pSrc, int x, int y, int w, src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT; src_obj.bo = radeon_get_pixmap_bo(pSrc); src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc); -#ifdef XF86DRM_MODE src_obj.surface = radeon_get_pixmap_surface(pSrc); -#endif dst_obj.pitch = scratch_pitch; dst_obj.width = w; @@ -2052,9 +1734,7 @@ R600DownloadFromScreenCS(PixmapPtr pSrc, int x, int y, int w, dst_obj.bpp = bpp; dst_obj.domain = RADEON_GEM_DOMAIN_GTT; dst_obj.tiling_flags = 0; -#ifdef XF86DRM_MODE dst_obj.surface = NULL; -#endif if (!R600SetAccelState(pScrn, &src_obj, @@ -2074,7 +1754,7 @@ R600DownloadFromScreenCS(PixmapPtr pSrc, int x, int y, int w, flush = TRUE; copy: - if (flush && info->cs) + if (flush) radeon_cs_flush_indirect(pScrn); ret = radeon_bo_map(copy_src, 0); @@ -2100,7 +1780,6 @@ out: radeon_bo_unref(scratch); return r; } -#endif static int R600MarkSync(ScreenPtr pScreen) @@ -2121,12 +1800,6 @@ R600Sync(ScreenPtr pScreen, int marker) struct radeon_accel_state *accel_state = info->accel_state; if (accel_state->exaMarkerSynced != marker) { -#ifdef XF86DRM_MODE -#if (EXA_VERSION_MAJOR == 2 && EXA_VERSION_MINOR >= 4) - if (!info->cs) -#endif -#endif - RADEONWaitForIdleCP(pScrn); accel_state->exaMarkerSynced = marker; } @@ -2141,29 +1814,12 @@ R600AllocShaders(ScrnInfoPtr pScrn, ScreenPtr pScreen) /* 512 bytes per shader for now */ int size = 512 * 9; - accel_state->shaders = NULL; - -#ifdef XF86DRM_MODE -#if (EXA_VERSION_MAJOR == 2 && EXA_VERSION_MINOR >= 4) - if (info->cs) { - accel_state->shaders_bo = radeon_bo_open(info->bufmgr, 0, size, 0, - RADEON_GEM_DOMAIN_VRAM, 0); - if (accel_state->shaders_bo == NULL) { - ErrorF("Allocating shader failed\n"); - return FALSE; - } - return TRUE; - } else -#endif -#endif - { - accel_state->shaders = exaOffscreenAlloc(pScreen, size, 256, - TRUE, NULL, NULL); - - if (accel_state->shaders == NULL) - return FALSE; + accel_state->shaders_bo = radeon_bo_open(info->bufmgr, 0, size, 0, + RADEON_GEM_DOMAIN_VRAM, 0); + if (accel_state->shaders_bo == NULL) { + ErrorF("Allocating shader failed\n"); + return FALSE; } - return TRUE; } @@ -2174,21 +1830,14 @@ R600LoadShaders(ScrnInfoPtr pScrn) struct radeon_accel_state *accel_state = info->accel_state; RADEONChipFamily ChipSet = info->ChipFamily; uint32_t *shader; -#ifdef XF86DRM_MODE -#if (EXA_VERSION_MAJOR == 2 && EXA_VERSION_MINOR >= 4) int ret; - if (info->cs) { - ret = radeon_bo_map(accel_state->shaders_bo, 1); - if (ret) { - FatalError("failed to map shader %d\n", ret); - return FALSE; - } - shader = accel_state->shaders_bo->ptr; - } else -#endif -#endif - shader = (pointer)((char *)info->FB + accel_state->shaders->offset); + ret = radeon_bo_map(accel_state->shaders_bo, 1); + if (ret) { + FatalError("failed to map shader %d\n", ret); + return FALSE; + } + shader = accel_state->shaders_bo->ptr; /* solid vs --------------------------------------- */ accel_state->solid_vs_offset = 0; @@ -2222,42 +1871,10 @@ R600LoadShaders(ScrnInfoPtr pScrn) accel_state->xv_ps_offset = 3584; R600_xv_ps(ChipSet, shader + accel_state->xv_ps_offset / 4); -#ifdef XF86DRM_MODE -#if (EXA_VERSION_MAJOR == 2 && EXA_VERSION_MINOR >= 4) - if (info->cs) { - radeon_bo_unmap(accel_state->shaders_bo); - } -#endif -#endif - + radeon_bo_unmap(accel_state->shaders_bo); return TRUE; } -static Bool -R600PrepareAccess(PixmapPtr pPix, int index) -{ - ScrnInfoPtr pScrn = xf86ScreenToScrn(pPix->drawable.pScreen); - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - /* flush HDP read/write caches */ - OUTREG(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); - - return TRUE; -} - -static void -R600FinishAccess(PixmapPtr pPix, int index) -{ - ScrnInfoPtr pScrn = xf86ScreenToScrn(pPix->drawable.pScreen); - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - /* flush HDP read/write caches */ - OUTREG(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); - -} - Bool R600DrawInit(ScreenPtr pScreen) { @@ -2283,46 +1900,28 @@ R600DrawInit(ScreenPtr pScreen) info->accel_state->exa->MarkSync = R600MarkSync; info->accel_state->exa->WaitMarker = R600Sync; -#ifdef XF86DRM_MODE #if (EXA_VERSION_MAJOR == 2 && EXA_VERSION_MINOR >= 4) - if (info->cs) { - info->accel_state->exa->CreatePixmap = RADEONEXACreatePixmap; - info->accel_state->exa->DestroyPixmap = RADEONEXADestroyPixmap; - info->accel_state->exa->PixmapIsOffscreen = RADEONEXAPixmapIsOffscreen; - info->accel_state->exa->PrepareAccess = RADEONPrepareAccess_CS; - info->accel_state->exa->FinishAccess = RADEONFinishAccess_CS; - info->accel_state->exa->UploadToScreen = R600UploadToScreenCS; - info->accel_state->exa->DownloadFromScreen = R600DownloadFromScreenCS; + info->accel_state->exa->CreatePixmap = RADEONEXACreatePixmap; + info->accel_state->exa->DestroyPixmap = RADEONEXADestroyPixmap; + info->accel_state->exa->PixmapIsOffscreen = RADEONEXAPixmapIsOffscreen; + info->accel_state->exa->PrepareAccess = RADEONPrepareAccess_CS; + info->accel_state->exa->FinishAccess = RADEONFinishAccess_CS; + info->accel_state->exa->UploadToScreen = R600UploadToScreenCS; + info->accel_state->exa->DownloadFromScreen = R600DownloadFromScreenCS; #if (EXA_VERSION_MAJOR == 2 && EXA_VERSION_MINOR >= 5) - info->accel_state->exa->CreatePixmap2 = RADEONEXACreatePixmap2; -#endif - } else + info->accel_state->exa->CreatePixmap2 = RADEONEXACreatePixmap2; #endif #endif - { - info->accel_state->exa->PrepareAccess = R600PrepareAccess; - info->accel_state->exa->FinishAccess = R600FinishAccess; - - /* AGP seems to have problems with gart transfers */ - if (info->accelDFS) { - info->accel_state->exa->UploadToScreen = R600UploadToScreen; - info->accel_state->exa->DownloadFromScreen = R600DownloadFromScreen; - } - } info->accel_state->exa->flags = EXA_OFFSCREEN_PIXMAPS; #ifdef EXA_SUPPORTS_PREPARE_AUX info->accel_state->exa->flags |= EXA_SUPPORTS_PREPARE_AUX; #endif -#ifdef XF86DRM_MODE #ifdef EXA_HANDLES_PIXMAPS - if (info->cs) { - info->accel_state->exa->flags |= EXA_HANDLES_PIXMAPS; + info->accel_state->exa->flags |= EXA_HANDLES_PIXMAPS; #ifdef EXA_MIXED_PIXMAPS - info->accel_state->exa->flags |= EXA_MIXED_PIXMAPS; -#endif - } + info->accel_state->exa->flags |= EXA_MIXED_PIXMAPS; #endif #endif info->accel_state->exa->pixmapOffsetAlign = 256; @@ -2355,16 +1954,7 @@ R600DrawInit(ScreenPtr pScreen) return FALSE; } -#ifdef XF86DRM_MODE -#if (EXA_VERSION_MAJOR == 2 && EXA_VERSION_MINOR >= 4) - if (!info->cs) -#endif -#endif - if (!info->gartLocation) - return FALSE; - info->accel_state->XInited3D = FALSE; - info->accel_state->copy_area = NULL; info->accel_state->src_obj[0].bo = NULL; info->accel_state->src_obj[1].bo = NULL; info->accel_state->dst_obj.bo = NULL; @@ -2374,9 +1964,7 @@ R600DrawInit(ScreenPtr pScreen) info->accel_state->vbo.verts_per_op = 3; RADEONVlineHelperClear(pScrn); -#ifdef XF86DRM_MODE radeon_vbo_init_lists(pScrn); -#endif if (!R600AllocShaders(pScrn, pScreen)) return FALSE; diff --git a/src/r600_state.h b/src/r600_state.h index f6d5a880..74b481cc 100644 --- a/src/r600_state.h +++ b/src/r600_state.h @@ -56,9 +56,7 @@ typedef struct { int blend_enable; uint32_t blendcntl; struct radeon_bo *bo; -#ifdef XF86DRM_MODE struct radeon_surface *surface; -#endif } cb_config_t; /* Depth buffer */ @@ -145,9 +143,7 @@ typedef struct { int interlaced; struct radeon_bo *bo; struct radeon_bo *mip_bo; -#ifdef XF86DRM_MODE struct radeon_surface *surface; -#endif } tex_resource_t; /* Texture sampler */ @@ -189,144 +185,122 @@ typedef struct { uint32_t num_indices; } draw_config_t; -#if defined(XF86DRM_MODE) #define BEGIN_BATCH(n) \ do { \ - if (info->cs) \ - radeon_ddx_cs_start(pScrn, (n), __FILE__, __func__, __LINE__); \ + radeon_ddx_cs_start(pScrn, (n), __FILE__, __func__, __LINE__); \ } while(0) #define END_BATCH() \ do { \ - if (info->cs) \ - radeon_cs_end(info->cs, __FILE__, __func__, __LINE__); \ + radeon_cs_end(info->cs, __FILE__, __func__, __LINE__); \ } while(0) #define RELOC_BATCH(bo, rd, wd) \ do { \ - if (info->cs) { \ - int _ret; \ - _ret = radeon_cs_write_reloc(info->cs, (bo), (rd), (wd), 0); \ - if (_ret) ErrorF("reloc emit failure %d (%s %d)\n", _ret, __func__, __LINE__); \ - } \ + int _ret; \ + _ret = radeon_cs_write_reloc(info->cs, (bo), (rd), (wd), 0); \ + if (_ret) ErrorF("reloc emit failure %d (%s %d)\n", _ret, __func__, __LINE__); \ } while(0) -#define E32(ib, dword) \ +#define E32(dword) \ do { \ - if (info->cs) \ - radeon_cs_write_dword(info->cs, (dword)); \ - else { \ - uint32_t *ib_head = (pointer)(char*)(ib)->address; \ - ib_head[(ib)->used >> 2] = (dword); \ - (ib)->used += 4; \ - } \ + radeon_cs_write_dword(info->cs, (dword)); \ } while (0) -#else -#define BEGIN_BATCH(n) do {(void)info;} while(0) -#define END_BATCH() do {} while(0) -#define RELOC_BATCH(bo, wd, rd) do {} while(0) -#define E32(ib, dword) \ -do { \ - uint32_t *ib_head = (pointer)(char*)(ib)->address; \ - ib_head[(ib)->used >> 2] = (dword); \ - (ib)->used += 4; \ -} while (0) -#endif -#define EFLOAT(ib, val) \ +#define EFLOAT(val) \ do { \ union { float f; uint32_t d; } a; \ a.f = (val); \ - E32((ib), a.d); \ + E32(a.d); \ } while (0) -#define PACK3(ib, cmd, num) \ +#define PACK3(cmd, num) \ do { \ - E32((ib), RADEON_CP_PACKET3 | ((cmd) << 8) | ((((num) - 1) & 0x3fff) << 16)); \ + E32(RADEON_CP_PACKET3 | ((cmd) << 8) | ((((num) - 1) & 0x3fff) << 16)); \ } while (0) /* write num registers, start at reg */ /* If register falls in a special area, special commands are issued */ -#define PACK0(ib, reg, num) \ +#define PACK0(reg, num) \ do { \ if ((reg) >= SET_CONFIG_REG_offset && (reg) < SET_CONFIG_REG_end) { \ - PACK3((ib), IT_SET_CONFIG_REG, (num) + 1); \ - E32((ib), ((reg) - SET_CONFIG_REG_offset) >> 2); \ + PACK3(IT_SET_CONFIG_REG, (num) + 1); \ + E32(((reg) - SET_CONFIG_REG_offset) >> 2); \ } else if ((reg) >= SET_CONTEXT_REG_offset && (reg) < SET_CONTEXT_REG_end) { \ - PACK3((ib), IT_SET_CONTEXT_REG, (num) + 1); \ - E32((ib), ((reg) - SET_CONTEXT_REG_offset) >> 2); \ + PACK3(IT_SET_CONTEXT_REG, (num) + 1); \ + E32(((reg) - SET_CONTEXT_REG_offset) >> 2); \ } else if ((reg) >= SET_ALU_CONST_offset && (reg) < SET_ALU_CONST_end) { \ - PACK3((ib), IT_SET_ALU_CONST, (num) + 1); \ - E32((ib), ((reg) - SET_ALU_CONST_offset) >> 2); \ + PACK3(IT_SET_ALU_CONST, (num) + 1); \ + E32(((reg) - SET_ALU_CONST_offset) >> 2); \ } else if ((reg) >= SET_RESOURCE_offset && (reg) < SET_RESOURCE_end) { \ - PACK3((ib), IT_SET_RESOURCE, num + 1); \ - E32((ib), ((reg) - SET_RESOURCE_offset) >> 2); \ + PACK3(IT_SET_RESOURCE, num + 1); \ + E32(((reg) - SET_RESOURCE_offset) >> 2); \ } else if ((reg) >= SET_SAMPLER_offset && (reg) < SET_SAMPLER_end) { \ - PACK3((ib), IT_SET_SAMPLER, (num) + 1); \ - E32((ib), (reg - SET_SAMPLER_offset) >> 2); \ + PACK3(IT_SET_SAMPLER, (num) + 1); \ + E32((reg - SET_SAMPLER_offset) >> 2); \ } else if ((reg) >= SET_CTL_CONST_offset && (reg) < SET_CTL_CONST_end) { \ - PACK3((ib), IT_SET_CTL_CONST, (num) + 1); \ - E32((ib), ((reg) - SET_CTL_CONST_offset) >> 2); \ + PACK3(IT_SET_CTL_CONST, (num) + 1); \ + E32(((reg) - SET_CTL_CONST_offset) >> 2); \ } else if ((reg) >= SET_LOOP_CONST_offset && (reg) < SET_LOOP_CONST_end) { \ - PACK3((ib), IT_SET_LOOP_CONST, (num) + 1); \ - E32((ib), ((reg) - SET_LOOP_CONST_offset) >> 2); \ + PACK3(IT_SET_LOOP_CONST, (num) + 1); \ + E32(((reg) - SET_LOOP_CONST_offset) >> 2); \ } else if ((reg) >= SET_BOOL_CONST_offset && (reg) < SET_BOOL_CONST_end) { \ - PACK3((ib), IT_SET_BOOL_CONST, (num) + 1); \ - E32((ib), ((reg) - SET_BOOL_CONST_offset) >> 2); \ + PACK3(IT_SET_BOOL_CONST, (num) + 1); \ + E32(((reg) - SET_BOOL_CONST_offset) >> 2); \ } else { \ - E32((ib), CP_PACKET0 ((reg), (num) - 1)); \ + E32(CP_PACKET0 ((reg), (num) - 1)); \ } \ } while (0) /* write a single register */ -#define EREG(ib, reg, val) \ +#define EREG(reg, val) \ do { \ - PACK0((ib), (reg), 1); \ - E32((ib), (val)); \ + PACK0((reg), 1); \ + E32((val)); \ } while (0) -void R600CPFlushIndirect(ScrnInfoPtr pScrn, drmBufPtr ib); -void R600IBDiscard(ScrnInfoPtr pScrn, drmBufPtr ib); +void R600CPFlushIndirect(ScrnInfoPtr pScrn); +void R600IBDiscard(ScrnInfoPtr pScrn); void -r600_wait_3d_idle_clean(ScrnInfoPtr pScrn, drmBufPtr ib); +r600_wait_3d_idle_clean(ScrnInfoPtr pScrn); void -r600_wait_3d_idle(ScrnInfoPtr pScrn, drmBufPtr ib); +r600_wait_3d_idle(ScrnInfoPtr pScrn); void -r600_start_3d(ScrnInfoPtr pScrn, drmBufPtr ib); +r600_start_3d(ScrnInfoPtr pScrn); void -r600_set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf, uint32_t domain); +r600_set_render_target(ScrnInfoPtr pScrn, cb_config_t *cb_conf, uint32_t domain); void -r600_cp_wait_vline_sync(ScrnInfoPtr pScrn, drmBufPtr ib, PixmapPtr pPix, xf86CrtcPtr crtc, int start, int stop); +r600_cp_wait_vline_sync(ScrnInfoPtr pScrn, PixmapPtr pPix, xf86CrtcPtr crtc, int start, int stop); void -r600_set_spi(ScrnInfoPtr pScrn, drmBufPtr ib, int vs_export_count, int num_interp); +r600_set_spi(ScrnInfoPtr pScrn, int vs_export_count, int num_interp); void -r600_fs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *fs_conf, uint32_t domain); +r600_fs_setup(ScrnInfoPtr pScrn, shader_config_t *fs_conf, uint32_t domain); void -r600_vs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *vs_conf, uint32_t domain); +r600_vs_setup(ScrnInfoPtr pScrn, shader_config_t *vs_conf, uint32_t domain); void -r600_ps_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *ps_conf, uint32_t domain); +r600_ps_setup(ScrnInfoPtr pScrn, shader_config_t *ps_conf, uint32_t domain); void -r600_set_alu_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, int count, float *const_buf); +r600_set_alu_consts(ScrnInfoPtr pScrn, int offset, int count, float *const_buf); void -r600_set_bool_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, uint32_t val); +r600_set_bool_consts(ScrnInfoPtr pScrn, int offset, uint32_t val); void -r600_set_tex_resource(ScrnInfoPtr pScrn, drmBufPtr ib, tex_resource_t *tex_res, uint32_t domain); +r600_set_tex_resource(ScrnInfoPtr pScrn, tex_resource_t *tex_res, uint32_t domain); void -r600_set_tex_sampler (ScrnInfoPtr pScrn, drmBufPtr ib, tex_sampler_t *s); +r600_set_tex_sampler (ScrnInfoPtr pScrn, tex_sampler_t *s); void -r600_set_screen_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2); +r600_set_screen_scissor(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2); void -r600_set_vport_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int id, int x1, int y1, int x2, int y2); +r600_set_vport_scissor(ScrnInfoPtr pScrn, int id, int x1, int y1, int x2, int y2); void -r600_set_generic_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2); +r600_set_generic_scissor(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2); void -r600_set_window_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2); +r600_set_window_scissor(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2); void -r600_set_clip_rect(ScrnInfoPtr pScrn, drmBufPtr ib, int id, int x1, int y1, int x2, int y2); +r600_set_clip_rect(ScrnInfoPtr pScrn, int id, int x1, int y1, int x2, int y2); void -r600_set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib); +r600_set_default_state(ScrnInfoPtr pScrn); void -r600_draw_immd(ScrnInfoPtr pScrn, drmBufPtr ib, draw_config_t *draw_conf, uint32_t *indices); +r600_draw_immd(ScrnInfoPtr pScrn, draw_config_t *draw_conf, uint32_t *indices); void -r600_draw_auto(ScrnInfoPtr pScrn, drmBufPtr ib, draw_config_t *draw_conf); +r600_draw_auto(ScrnInfoPtr pScrn, draw_config_t *draw_conf); void r600_finish_op(ScrnInfoPtr pScrn, int vtx_size); diff --git a/src/r600_textured_videofuncs.c b/src/r600_textured_videofuncs.c index 7610050a..a4a67f2a 100644 --- a/src/r600_textured_videofuncs.c +++ b/src/r600_textured_videofuncs.c @@ -164,20 +164,12 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) CLEAR (vs_conf); CLEAR (ps_conf); -#if defined(XF86DRM_MODE) - if (info->cs) { - dst_obj.offset = 0; - src_obj.offset = 0; - dst_obj.bo = radeon_get_pixmap_bo(pPixmap); - dst_obj.tiling_flags = radeon_get_pixmap_tiling(pPixmap); - dst_obj.surface = radeon_get_pixmap_surface(pPixmap); - } else -#endif - { - dst_obj.offset = exaGetPixmapOffset(pPixmap) + info->fbLocation + pScrn->fbOffset; - src_obj.offset = pPriv->src_offset + info->fbLocation + pScrn->fbOffset; - dst_obj.bo = src_obj.bo = NULL; - } + dst_obj.offset = 0; + src_obj.offset = 0; + dst_obj.bo = radeon_get_pixmap_bo(pPixmap); + dst_obj.tiling_flags = radeon_get_pixmap_tiling(pPixmap); + dst_obj.surface = radeon_get_pixmap_surface(pPixmap); + dst_obj.pitch = exaGetPixmapPitch(pPixmap) / (pPixmap->drawable.bitsPerPixel / 8); src_obj.pitch = pPriv->src_pitch; @@ -187,9 +179,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT; src_obj.bo = pPriv->src_bo[pPriv->currentBuffer]; src_obj.tiling_flags = 0; -#ifdef XF86DRM_MODE src_obj.surface = NULL; -#endif dst_obj.width = pPixmap->drawable.width; dst_obj.height = pPixmap->drawable.height; @@ -215,22 +205,22 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) radeon_vbo_check(pScrn, &accel_state->vbo, 16); radeon_cp_start(pScrn); - r600_set_default_state(pScrn, accel_state->ib); + r600_set_default_state(pScrn); - r600_set_generic_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); - r600_set_screen_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); - r600_set_window_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); + r600_set_generic_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); + r600_set_screen_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); + r600_set_window_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); /* PS bool constant */ switch(pPriv->id) { case FOURCC_YV12: case FOURCC_I420: - r600_set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_ps, (1 << 0)); + r600_set_bool_consts(pScrn, SQ_BOOL_CONST_ps, (1 << 0)); break; case FOURCC_UYVY: case FOURCC_YUY2: default: - r600_set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_ps, (0 << 0)); + r600_set_bool_consts(pScrn, SQ_BOOL_CONST_ps, (0 << 0)); break; } @@ -240,7 +230,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) vs_conf.num_gprs = 2; vs_conf.stack_size = 0; vs_conf.bo = accel_state->shaders_bo; - r600_vs_setup(pScrn, accel_state->ib, &vs_conf, RADEON_GEM_DOMAIN_VRAM); + r600_vs_setup(pScrn, &vs_conf, RADEON_GEM_DOMAIN_VRAM); ps_conf.shader_addr = accel_state->ps_mc_addr; ps_conf.shader_size = accel_state->ps_size; @@ -250,10 +240,10 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) ps_conf.clamp_consts = 0; ps_conf.export_mode = 2; ps_conf.bo = accel_state->shaders_bo; - r600_ps_setup(pScrn, accel_state->ib, &ps_conf, RADEON_GEM_DOMAIN_VRAM); + r600_ps_setup(pScrn, &ps_conf, RADEON_GEM_DOMAIN_VRAM); /* PS alu constants */ - r600_set_alu_consts(pScrn, accel_state->ib, SQ_ALU_CONSTANT_ps, + r600_set_alu_consts(pScrn, SQ_ALU_CONSTANT_ps, sizeof(ps_alu_consts) / SQ_ALU_CONSTANT_offset, ps_alu_consts); /* Texture */ @@ -274,9 +264,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) tex_res.size = accel_state->src_size[0]; tex_res.bo = accel_state->src_obj[0].bo; tex_res.mip_bo = accel_state->src_obj[0].bo; -#ifdef XF86DRM_MODE tex_res.surface = NULL; -#endif tex_res.format = FMT_8; tex_res.dst_sel_x = SQ_SEL_X; /* Y */ @@ -291,7 +279,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) tex_res.interlaced = 0; if (accel_state->src_obj[0].tiling_flags == 0) tex_res.tile_mode = 1; - r600_set_tex_resource(pScrn, accel_state->ib, &tex_res, accel_state->src_obj[0].domain); + r600_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain); /* Y sampler */ tex_samp.id = 0; @@ -305,7 +293,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) tex_samp.z_filter = SQ_TEX_Z_FILTER_NONE; tex_samp.mip_filter = 0; /* no mipmap */ - r600_set_tex_sampler(pScrn, accel_state->ib, &tex_samp); + r600_set_tex_sampler(pScrn, &tex_samp); /* U or V texture */ tex_res.id = 1; @@ -324,11 +312,11 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) tex_res.size = tex_res.pitch * (pPriv->h >> 1); if (accel_state->src_obj[0].tiling_flags == 0) tex_res.tile_mode = 1; - r600_set_tex_resource(pScrn, accel_state->ib, &tex_res, accel_state->src_obj[0].domain); + r600_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain); /* U or V sampler */ tex_samp.id = 1; - r600_set_tex_sampler(pScrn, accel_state->ib, &tex_samp); + r600_set_tex_sampler(pScrn, &tex_samp); /* U or V texture */ tex_res.id = 2; @@ -347,11 +335,11 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) tex_res.size = tex_res.pitch * (pPriv->h >> 1); if (accel_state->src_obj[0].tiling_flags == 0) tex_res.tile_mode = 1; - r600_set_tex_resource(pScrn, accel_state->ib, &tex_res, accel_state->src_obj[0].domain); + r600_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain); /* UV sampler */ tex_samp.id = 2; - r600_set_tex_sampler(pScrn, accel_state->ib, &tex_samp); + r600_set_tex_sampler(pScrn, &tex_samp); break; case FOURCC_UYVY: case FOURCC_YUY2: @@ -387,7 +375,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) tex_res.interlaced = 0; if (accel_state->src_obj[0].tiling_flags == 0) tex_res.tile_mode = 1; - r600_set_tex_resource(pScrn, accel_state->ib, &tex_res, accel_state->src_obj[0].domain); + r600_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain); /* YUV sampler */ tex_samp.id = 0; @@ -401,7 +389,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) tex_samp.z_filter = SQ_TEX_Z_FILTER_NONE; tex_samp.mip_filter = 0; /* no mipmap */ - r600_set_tex_sampler(pScrn, accel_state->ib, &tex_samp); + r600_set_tex_sampler(pScrn, &tex_samp); break; } @@ -411,9 +399,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) cb_conf.h = accel_state->dst_obj.height; cb_conf.base = accel_state->dst_obj.offset; cb_conf.bo = accel_state->dst_obj.bo; -#ifdef XF86DRM_MODE cb_conf.surface = accel_state->dst_obj.surface; -#endif switch (accel_state->dst_obj.bpp) { case 16: @@ -445,9 +431,9 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) cb_conf.rop = 3; if (accel_state->dst_obj.tiling_flags == 0) cb_conf.array_mode = 1; - r600_set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain); + r600_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain); - r600_set_spi(pScrn, accel_state->ib, (1 - 1), 1); + r600_set_spi(pScrn, (1 - 1), 1); vs_alu_consts[0] = 1.0 / pPriv->w; vs_alu_consts[1] = 1.0 / pPriv->h; @@ -455,7 +441,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) vs_alu_consts[3] = 0.0; /* VS alu constants */ - r600_set_alu_consts(pScrn, accel_state->ib, SQ_ALU_CONSTANT_vs, + r600_set_alu_consts(pScrn, SQ_ALU_CONSTANT_vs, sizeof(vs_alu_consts) / SQ_ALU_CONSTANT_offset, vs_alu_consts); if (pPriv->vsync) { @@ -469,7 +455,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) pPriv->drw_y, pPriv->drw_y + pPriv->dst_h); if (crtc) - r600_cp_wait_vline_sync(pScrn, accel_state->ib, pPixmap, + r600_cp_wait_vline_sync(pScrn, pPixmap, crtc, pPriv->drw_y - crtc->y, (pPriv->drw_y - crtc->y) + pPriv->dst_h); diff --git a/src/r6xx_accel.c b/src/r6xx_accel.c index 8d254241..5fe643dd 100644 --- a/src/r6xx_accel.c +++ b/src/r6xx_accel.c @@ -65,100 +65,56 @@ static const uint32_t R600_ROP[16] = { #define KMS_MULTI_OP 1 /* Flush the indirect buffer to the kernel for submission to the card */ -void R600CPFlushIndirect(ScrnInfoPtr pScrn, drmBufPtr ib) +void R600CPFlushIndirect(ScrnInfoPtr pScrn) { - RADEONInfoPtr info = RADEONPTR(pScrn); - drmBufPtr buffer = ib; - int start = 0; - drm_radeon_indirect_t indirect; - -#if defined(XF86DRM_MODE) - if (info->cs) { - radeon_cs_flush_indirect(pScrn); - return; - } -#endif - - if (!buffer) return; - - //xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Flushing buffer %d\n", - // buffer->idx); - - while (buffer->used & 0x3c){ - BEGIN_BATCH(1); - E32(buffer, CP_PACKET2()); /* fill up to multiple of 16 dwords */ - END_BATCH(); - } - - info->accel_state->vbo.vb_offset = 0; - info->accel_state->vbo.vb_start_op = -1; - - //ErrorF("buffer bytes: %d\n", buffer->used); - - indirect.idx = buffer->idx; - indirect.start = start; - indirect.end = buffer->used; - indirect.discard = 1; - - drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_INDIRECT, - &indirect, sizeof(drm_radeon_indirect_t)); - + radeon_cs_flush_indirect(pScrn); } -void R600IBDiscard(ScrnInfoPtr pScrn, drmBufPtr ib) +void R600IBDiscard(ScrnInfoPtr pScrn) { -#if defined(XF86DRM_MODE) - RADEONInfoPtr info = RADEONPTR(pScrn); - if (info->cs) { - radeon_ib_discard(pScrn); - } -#endif - if (!ib) return; - - ib->used = 0; - R600CPFlushIndirect(pScrn, ib); + radeon_ib_discard(pScrn); } void -r600_wait_3d_idle_clean(ScrnInfoPtr pScrn, drmBufPtr ib) +r600_wait_3d_idle_clean(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); //flush caches, don't generate timestamp BEGIN_BATCH(5); - PACK3(ib, IT_EVENT_WRITE, 1); - E32(ib, CACHE_FLUSH_AND_INV_EVENT); + PACK3(IT_EVENT_WRITE, 1); + E32(CACHE_FLUSH_AND_INV_EVENT); // wait for 3D idle clean - EREG(ib, WAIT_UNTIL, (WAIT_3D_IDLE_bit | + EREG(WAIT_UNTIL, (WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit)); END_BATCH(); } void -r600_wait_3d_idle(ScrnInfoPtr pScrn, drmBufPtr ib) +r600_wait_3d_idle(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); BEGIN_BATCH(3); - EREG(ib, WAIT_UNTIL, WAIT_3D_IDLE_bit); + EREG(WAIT_UNTIL, WAIT_3D_IDLE_bit); END_BATCH(); } void -r600_start_3d(ScrnInfoPtr pScrn, drmBufPtr ib) +r600_start_3d(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); if (info->ChipFamily < CHIP_FAMILY_RV770) { BEGIN_BATCH(5); - PACK3(ib, IT_START_3D_CMDBUF, 1); - E32(ib, 0); + PACK3(IT_START_3D_CMDBUF, 1); + E32(0); } else BEGIN_BATCH(3); - PACK3(ib, IT_CONTEXT_CONTROL, 2); - E32(ib, 0x80000000); - E32(ib, 0x80000000); + PACK3(IT_CONTEXT_CONTROL, 2); + E32(0x80000000); + E32(0x80000000); END_BATCH(); } @@ -169,7 +125,7 @@ r600_start_3d(ScrnInfoPtr pScrn, drmBufPtr ib) // asic stack/thread/gpr limits - need to query the drm static void -r600_sq_setup(ScrnInfoPtr pScrn, drmBufPtr ib, sq_config_t *sq_conf) +r600_sq_setup(ScrnInfoPtr pScrn, sq_config_t *sq_conf) { uint32_t sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2; uint32_t sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2; @@ -209,25 +165,24 @@ r600_sq_setup(ScrnInfoPtr pScrn, drmBufPtr ib, sq_config_t *sq_conf) (sq_conf->num_es_stack_entries << NUM_ES_STACK_ENTRIES_shift)); BEGIN_BATCH(8); - PACK0(ib, SQ_CONFIG, 6); - E32(ib, sq_config); - E32(ib, sq_gpr_resource_mgmt_1); - E32(ib, sq_gpr_resource_mgmt_2); - E32(ib, sq_thread_resource_mgmt); - E32(ib, sq_stack_resource_mgmt_1); - E32(ib, sq_stack_resource_mgmt_2); + PACK0(SQ_CONFIG, 6); + E32(sq_config); + E32(sq_gpr_resource_mgmt_1); + E32(sq_gpr_resource_mgmt_2); + E32(sq_thread_resource_mgmt); + E32(sq_stack_resource_mgmt_1); + E32(sq_stack_resource_mgmt_2); END_BATCH(); } void -r600_set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf, uint32_t domain) +r600_set_render_target(ScrnInfoPtr pScrn, cb_config_t *cb_conf, uint32_t domain) { uint32_t cb_color_info, cb_color_control; unsigned pitch, slice, h, array_mode; RADEONInfoPtr info = RADEONPTR(pScrn); -#if defined(XF86DRM_MODE) if (cb_conf->surface) { switch (cb_conf->surface->level[0].mode) { case RADEON_SURF_MODE_1D: @@ -243,7 +198,6 @@ r600_set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf, ui pitch = (cb_conf->surface->level[0].nblk_x >> 3) - 1; slice = ((cb_conf->surface->level[0].nblk_x * cb_conf->surface->level[0].nblk_y) / 64) - 1; } else -#endif { array_mode = cb_conf->array_mode; pitch = (cb_conf->w / 8) - 1; @@ -277,7 +231,7 @@ r600_set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf, ui cb_color_info |= SOURCE_FORMAT_bit; BEGIN_BATCH(3 + 2); - EREG(ib, (CB_COLOR0_BASE + (4 * cb_conf->id)), (cb_conf->base >> 8)); + EREG((CB_COLOR0_BASE + (4 * cb_conf->id)), (cb_conf->base >> 8)); RELOC_BATCH(cb_conf->bo, 0, domain); END_BATCH(); @@ -285,8 +239,8 @@ r600_set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf, ui if ((info->ChipFamily > CHIP_FAMILY_R600) && (info->ChipFamily < CHIP_FAMILY_RV770)) { BEGIN_BATCH(2); - PACK3(ib, IT_SURFACE_BASE_UPDATE, 1); - E32(ib, (2 << cb_conf->id)); + PACK3(IT_SURFACE_BASE_UPDATE, 1); + E32((2 << cb_conf->id)); END_BATCH(); } /* Set CMASK & TILE buffer to the offset of color buffer as @@ -294,47 +248,47 @@ r600_set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf, ui * then have a valid cmd stream */ BEGIN_BATCH(3 + 2); - EREG(ib, (CB_COLOR0_TILE + (4 * cb_conf->id)), (0 >> 8)); // CMASK per-tile data base/256 + EREG((CB_COLOR0_TILE + (4 * cb_conf->id)), (0 >> 8)); // CMASK per-tile data base/256 RELOC_BATCH(cb_conf->bo, 0, domain); END_BATCH(); BEGIN_BATCH(3 + 2); - EREG(ib, (CB_COLOR0_FRAG + (4 * cb_conf->id)), (0 >> 8)); // FMASK per-tile data base/256 + EREG((CB_COLOR0_FRAG + (4 * cb_conf->id)), (0 >> 8)); // FMASK per-tile data base/256 RELOC_BATCH(cb_conf->bo, 0, domain); END_BATCH(); BEGIN_BATCH(9); // pitch only for ARRAY_LINEAR_GENERAL, other tiling modes require addrlib - EREG(ib, (CB_COLOR0_SIZE + (4 * cb_conf->id)), ((pitch << PITCH_TILE_MAX_shift) | + EREG((CB_COLOR0_SIZE + (4 * cb_conf->id)), ((pitch << PITCH_TILE_MAX_shift) | (slice << SLICE_TILE_MAX_shift))); - EREG(ib, (CB_COLOR0_VIEW + (4 * cb_conf->id)), ((0 << SLICE_START_shift) | + EREG((CB_COLOR0_VIEW + (4 * cb_conf->id)), ((0 << SLICE_START_shift) | (0 << SLICE_MAX_shift))); - EREG(ib, (CB_COLOR0_MASK + (4 * cb_conf->id)), ((0 << CMASK_BLOCK_MAX_shift) | + EREG((CB_COLOR0_MASK + (4 * cb_conf->id)), ((0 << CMASK_BLOCK_MAX_shift) | (0 << FMASK_TILE_MAX_shift))); END_BATCH(); BEGIN_BATCH(3 + 2); - EREG(ib, (CB_COLOR0_INFO + (4 * cb_conf->id)), cb_color_info); + EREG((CB_COLOR0_INFO + (4 * cb_conf->id)), cb_color_info); RELOC_BATCH(cb_conf->bo, 0, domain); END_BATCH(); BEGIN_BATCH(9); - EREG(ib, CB_TARGET_MASK, (cb_conf->pmask << TARGET0_ENABLE_shift)); + EREG(CB_TARGET_MASK, (cb_conf->pmask << TARGET0_ENABLE_shift)); cb_color_control = R600_ROP[cb_conf->rop] | (cb_conf->blend_enable << TARGET_BLEND_ENABLE_shift); if (info->ChipFamily == CHIP_FAMILY_R600) { /* no per-MRT blend on R600 */ - EREG(ib, CB_COLOR_CONTROL, cb_color_control); - EREG(ib, CB_BLEND_CONTROL, cb_conf->blendcntl); + EREG(CB_COLOR_CONTROL, cb_color_control); + EREG(CB_BLEND_CONTROL, cb_conf->blendcntl); } else { if (cb_conf->blend_enable) cb_color_control |= PER_MRT_BLEND_bit; - EREG(ib, CB_COLOR_CONTROL, cb_color_control); - EREG(ib, CB_BLEND0_CONTROL, cb_conf->blendcntl); + EREG(CB_COLOR_CONTROL, cb_color_control); + EREG(CB_BLEND0_CONTROL, cb_conf->blendcntl); } END_BATCH(); } static void -r600_cp_set_surface_sync(ScrnInfoPtr pScrn, drmBufPtr ib, uint32_t sync_type, +r600_cp_set_surface_sync(ScrnInfoPtr pScrn, uint32_t sync_type, uint32_t size, uint64_t mc_addr, struct radeon_bo *bo, uint32_t rdomains, uint32_t wdomain) { @@ -346,22 +300,22 @@ r600_cp_set_surface_sync(ScrnInfoPtr pScrn, drmBufPtr ib, uint32_t sync_type, cp_coher_size = ((size + 255) >> 8); BEGIN_BATCH(5 + 2); - PACK3(ib, IT_SURFACE_SYNC, 4); - E32(ib, sync_type); - E32(ib, cp_coher_size); - E32(ib, (mc_addr >> 8)); - E32(ib, 10); /* poll interval */ + PACK3(IT_SURFACE_SYNC, 4); + E32(sync_type); + E32(cp_coher_size); + E32((mc_addr >> 8)); + E32(10); /* poll interval */ RELOC_BATCH(bo, rdomains, wdomain); END_BATCH(); } /* inserts a wait for vline in the command stream */ void -r600_cp_wait_vline_sync(ScrnInfoPtr pScrn, drmBufPtr ib, PixmapPtr pPix, +r600_cp_wait_vline_sync(ScrnInfoPtr pScrn, PixmapPtr pPix, xf86CrtcPtr crtc, int start, int stop) { RADEONInfoPtr info = RADEONPTR(pScrn); - uint32_t offset; + drmmode_crtc_private_ptr drmmode_crtc; if (!crtc) return; @@ -369,21 +323,8 @@ r600_cp_wait_vline_sync(ScrnInfoPtr pScrn, drmBufPtr ib, PixmapPtr pPix, if (!crtc->enabled) return; - if (info->cs) { - if (pPix != pScrn->pScreen->GetScreenPixmap(pScrn->pScreen)) - return; - } else { -#ifdef USE_EXA - if (info->useEXA) - offset = exaGetPixmapOffset(pPix); - else -#endif - offset = pPix->devPrivate.ptr - info->FB; - - /* if drawing to front buffer */ - if (offset != 0) - return; - } + if (pPix != pScrn->pScreen->GetScreenPixmap(pScrn->pScreen)) + return; start = max(start, crtc->y); stop = min(stop, crtc->y + crtc->mode.VDisplay); @@ -391,68 +332,45 @@ r600_cp_wait_vline_sync(ScrnInfoPtr pScrn, drmBufPtr ib, PixmapPtr pPix, if (start >= stop) return; -#if defined(XF86DRM_MODE) - if (info->cs) { - drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; - - BEGIN_BATCH(11); - /* set the VLINE range */ - EREG(ib, AVIVO_D1MODE_VLINE_START_END, /* this is just a marker */ - (start << AVIVO_D1MODE_VLINE_START_SHIFT) | - (stop << AVIVO_D1MODE_VLINE_END_SHIFT)); - - /* tell the CP to poll the VLINE state register */ - PACK3(ib, IT_WAIT_REG_MEM, 6); - E32(ib, IT_WAIT_REG | IT_WAIT_EQ); - E32(ib, IT_WAIT_ADDR(AVIVO_D1MODE_VLINE_STATUS)); - E32(ib, 0); - E32(ib, 0); // Ref value - E32(ib, AVIVO_D1MODE_VLINE_STAT); // Mask - E32(ib, 10); // Wait interval - /* add crtc reloc */ - PACK3(ib, IT_NOP, 1); - E32(ib, drmmode_crtc->mode_crtc->crtc_id); - END_BATCH(); - } else -#endif - { - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - - BEGIN_BATCH(9); - /* set the VLINE range */ - EREG(ib, AVIVO_D1MODE_VLINE_START_END + radeon_crtc->crtc_offset, - (start << AVIVO_D1MODE_VLINE_START_SHIFT) | - (stop << AVIVO_D1MODE_VLINE_END_SHIFT)); - - /* tell the CP to poll the VLINE state register */ - PACK3(ib, IT_WAIT_REG_MEM, 6); - E32(ib, IT_WAIT_REG | IT_WAIT_EQ); - E32(ib, IT_WAIT_ADDR(AVIVO_D1MODE_VLINE_STATUS + radeon_crtc->crtc_offset)); - E32(ib, 0); - E32(ib, 0); // Ref value - E32(ib, AVIVO_D1MODE_VLINE_STAT); // Mask - E32(ib, 10); // Wait interval - END_BATCH(); - } + drmmode_crtc = crtc->driver_private; + + BEGIN_BATCH(11); + /* set the VLINE range */ + EREG(AVIVO_D1MODE_VLINE_START_END, /* this is just a marker */ + (start << AVIVO_D1MODE_VLINE_START_SHIFT) | + (stop << AVIVO_D1MODE_VLINE_END_SHIFT)); + + /* tell the CP to poll the VLINE state register */ + PACK3(IT_WAIT_REG_MEM, 6); + E32(IT_WAIT_REG | IT_WAIT_EQ); + E32(IT_WAIT_ADDR(AVIVO_D1MODE_VLINE_STATUS)); + E32(0); + E32(0); // Ref value + E32(AVIVO_D1MODE_VLINE_STAT); // Mask + E32(10); // Wait interval + /* add crtc reloc */ + PACK3(IT_NOP, 1); + E32(drmmode_crtc->mode_crtc->crtc_id); + END_BATCH(); } void -r600_set_spi(ScrnInfoPtr pScrn, drmBufPtr ib, int vs_export_count, int num_interp) +r600_set_spi(ScrnInfoPtr pScrn, int vs_export_count, int num_interp) { RADEONInfoPtr info = RADEONPTR(pScrn); BEGIN_BATCH(8); /* Interpolator setup */ - EREG(ib, SPI_VS_OUT_CONFIG, (vs_export_count << VS_EXPORT_COUNT_shift)); - PACK0(ib, SPI_PS_IN_CONTROL_0, 3); - E32(ib, (num_interp << NUM_INTERP_shift)); - E32(ib, 0); - E32(ib, 0); + EREG(SPI_VS_OUT_CONFIG, (vs_export_count << VS_EXPORT_COUNT_shift)); + PACK0(SPI_PS_IN_CONTROL_0, 3); + E32((num_interp << NUM_INTERP_shift)); + E32(0); + E32(0); END_BATCH(); } void -r600_fs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *fs_conf, uint32_t domain) +r600_fs_setup(ScrnInfoPtr pScrn, shader_config_t *fs_conf, uint32_t domain) { RADEONInfoPtr info = RADEONPTR(pScrn); uint32_t sq_pgm_resources; @@ -464,18 +382,18 @@ r600_fs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *fs_conf, uint32_ sq_pgm_resources |= SQ_PGM_RESOURCES_FS__DX10_CLAMP_bit; BEGIN_BATCH(3 + 2); - EREG(ib, SQ_PGM_START_FS, fs_conf->shader_addr >> 8); + EREG(SQ_PGM_START_FS, fs_conf->shader_addr >> 8); RELOC_BATCH(fs_conf->bo, domain, 0); END_BATCH(); BEGIN_BATCH(6); - EREG(ib, SQ_PGM_RESOURCES_FS, sq_pgm_resources); - EREG(ib, SQ_PGM_CF_OFFSET_FS, 0); + EREG(SQ_PGM_RESOURCES_FS, sq_pgm_resources); + EREG(SQ_PGM_CF_OFFSET_FS, 0); END_BATCH(); } void -r600_vs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *vs_conf, uint32_t domain) +r600_vs_setup(ScrnInfoPtr pScrn, shader_config_t *vs_conf, uint32_t domain) { RADEONInfoPtr info = RADEONPTR(pScrn); uint32_t sq_pgm_resources; @@ -491,23 +409,23 @@ r600_vs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *vs_conf, uint32_ sq_pgm_resources |= UNCACHED_FIRST_INST_bit; /* flush SQ cache */ - r600_cp_set_surface_sync(pScrn, ib, SH_ACTION_ENA_bit, + r600_cp_set_surface_sync(pScrn, SH_ACTION_ENA_bit, vs_conf->shader_size, vs_conf->shader_addr, vs_conf->bo, domain, 0); BEGIN_BATCH(3 + 2); - EREG(ib, SQ_PGM_START_VS, vs_conf->shader_addr >> 8); + EREG(SQ_PGM_START_VS, vs_conf->shader_addr >> 8); RELOC_BATCH(vs_conf->bo, domain, 0); END_BATCH(); BEGIN_BATCH(6); - EREG(ib, SQ_PGM_RESOURCES_VS, sq_pgm_resources); - EREG(ib, SQ_PGM_CF_OFFSET_VS, 0); + EREG(SQ_PGM_RESOURCES_VS, sq_pgm_resources); + EREG(SQ_PGM_CF_OFFSET_VS, 0); END_BATCH(); } void -r600_ps_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *ps_conf, uint32_t domain) +r600_ps_setup(ScrnInfoPtr pScrn, shader_config_t *ps_conf, uint32_t domain) { RADEONInfoPtr info = RADEONPTR(pScrn); uint32_t sq_pgm_resources; @@ -525,50 +443,50 @@ r600_ps_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *ps_conf, uint32_ sq_pgm_resources |= CLAMP_CONSTS_bit; /* flush SQ cache */ - r600_cp_set_surface_sync(pScrn, ib, SH_ACTION_ENA_bit, + r600_cp_set_surface_sync(pScrn, SH_ACTION_ENA_bit, ps_conf->shader_size, ps_conf->shader_addr, ps_conf->bo, domain, 0); BEGIN_BATCH(3 + 2); - EREG(ib, SQ_PGM_START_PS, ps_conf->shader_addr >> 8); + EREG(SQ_PGM_START_PS, ps_conf->shader_addr >> 8); RELOC_BATCH(ps_conf->bo, domain, 0); END_BATCH(); BEGIN_BATCH(9); - EREG(ib, SQ_PGM_RESOURCES_PS, sq_pgm_resources); - EREG(ib, SQ_PGM_EXPORTS_PS, ps_conf->export_mode); - EREG(ib, SQ_PGM_CF_OFFSET_PS, 0); + EREG(SQ_PGM_RESOURCES_PS, sq_pgm_resources); + EREG(SQ_PGM_EXPORTS_PS, ps_conf->export_mode); + EREG(SQ_PGM_CF_OFFSET_PS, 0); END_BATCH(); } void -r600_set_alu_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, int count, float *const_buf) +r600_set_alu_consts(ScrnInfoPtr pScrn, int offset, int count, float *const_buf) { RADEONInfoPtr info = RADEONPTR(pScrn); int i; const int countreg = count * (SQ_ALU_CONSTANT_offset >> 2); BEGIN_BATCH(2 + countreg); - PACK0(ib, SQ_ALU_CONSTANT + offset * SQ_ALU_CONSTANT_offset, countreg); + PACK0(SQ_ALU_CONSTANT + offset * SQ_ALU_CONSTANT_offset, countreg); for (i = 0; i < countreg; i++) - EFLOAT(ib, const_buf[i]); + EFLOAT(const_buf[i]); END_BATCH(); } void -r600_set_bool_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, uint32_t val) +r600_set_bool_consts(ScrnInfoPtr pScrn, int offset, uint32_t val) { RADEONInfoPtr info = RADEONPTR(pScrn); /* bool register order is: ps, vs, gs; one register each * 1 bits per bool; 32 bools each for ps, vs, gs. */ BEGIN_BATCH(3); - EREG(ib, SQ_BOOL_CONST + offset * SQ_BOOL_CONST_offset, val); + EREG(SQ_BOOL_CONST + offset * SQ_BOOL_CONST_offset, val); END_BATCH(); } static void -r600_set_vtx_resource(ScrnInfoPtr pScrn, drmBufPtr ib, vtx_resource_t *res, uint32_t domain) +r600_set_vtx_resource(ScrnInfoPtr pScrn, vtx_resource_t *res, uint32_t domain) { RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; @@ -594,38 +512,37 @@ r600_set_vtx_resource(ScrnInfoPtr pScrn, drmBufPtr ib, vtx_resource_t *res, uint (info->ChipFamily == CHIP_FAMILY_RS780) || (info->ChipFamily == CHIP_FAMILY_RS880) || (info->ChipFamily == CHIP_FAMILY_RV710)) - r600_cp_set_surface_sync(pScrn, ib, TC_ACTION_ENA_bit, + r600_cp_set_surface_sync(pScrn, TC_ACTION_ENA_bit, accel_state->vbo.vb_offset, accel_state->vbo.vb_mc_addr, res->bo, domain, 0); else - r600_cp_set_surface_sync(pScrn, ib, VC_ACTION_ENA_bit, + r600_cp_set_surface_sync(pScrn, VC_ACTION_ENA_bit, accel_state->vbo.vb_offset, accel_state->vbo.vb_mc_addr, res->bo, domain, 0); BEGIN_BATCH(9 + 2); - PACK0(ib, SQ_VTX_RESOURCE + res->id * SQ_VTX_RESOURCE_offset, 7); - E32(ib, res->vb_addr & 0xffffffff); // 0: BASE_ADDRESS - E32(ib, (res->vtx_num_entries << 2) - 1); // 1: SIZE - E32(ib, sq_vtx_constant_word2); // 2: BASE_HI, STRIDE, CLAMP, FORMAT, ENDIAN - E32(ib, res->mem_req_size << MEM_REQUEST_SIZE_shift); // 3: MEM_REQUEST_SIZE ?!? - E32(ib, 0); // 4: n/a - E32(ib, 0); // 5: n/a - E32(ib, SQ_TEX_VTX_VALID_BUFFER << SQ_VTX_CONSTANT_WORD6_0__TYPE_shift); // 6: TYPE + PACK0(SQ_VTX_RESOURCE + res->id * SQ_VTX_RESOURCE_offset, 7); + E32(res->vb_addr & 0xffffffff); // 0: BASE_ADDRESS + E32((res->vtx_num_entries << 2) - 1); // 1: SIZE + E32(sq_vtx_constant_word2); // 2: BASE_HI, STRIDE, CLAMP, FORMAT, ENDIAN + E32(res->mem_req_size << MEM_REQUEST_SIZE_shift); // 3: MEM_REQUEST_SIZE ?!? + E32(0); // 4: n/a + E32(0); // 5: n/a + E32(SQ_TEX_VTX_VALID_BUFFER << SQ_VTX_CONSTANT_WORD6_0__TYPE_shift); // 6: TYPE RELOC_BATCH(res->bo, domain, 0); END_BATCH(); } void -r600_set_tex_resource(ScrnInfoPtr pScrn, drmBufPtr ib, tex_resource_t *tex_res, uint32_t domain) +r600_set_tex_resource(ScrnInfoPtr pScrn, tex_resource_t *tex_res, uint32_t domain) { RADEONInfoPtr info = RADEONPTR(pScrn); uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4; uint32_t sq_tex_resource_word5, sq_tex_resource_word6; uint32_t array_mode, pitch; -#if defined(XF86DRM_MODE) if (tex_res->surface) { switch (tex_res->surface->level[0].mode) { case RADEON_SURF_MODE_1D: @@ -640,7 +557,6 @@ r600_set_tex_resource(ScrnInfoPtr pScrn, drmBufPtr ib, tex_resource_t *tex_res, } pitch = tex_res->surface->level[0].nblk_x >> 3; } else -#endif { array_mode = tex_res->tile_mode; pitch = (tex_res->pitch + 7) >> 3; @@ -693,26 +609,26 @@ r600_set_tex_resource(ScrnInfoPtr pScrn, drmBufPtr ib, tex_resource_t *tex_res, sq_tex_resource_word6 |= INTERLACED_bit; /* flush texture cache */ - r600_cp_set_surface_sync(pScrn, ib, TC_ACTION_ENA_bit, + r600_cp_set_surface_sync(pScrn, TC_ACTION_ENA_bit, tex_res->size, tex_res->base, tex_res->bo, domain, 0); BEGIN_BATCH(9 + 4); - PACK0(ib, SQ_TEX_RESOURCE + tex_res->id * SQ_TEX_RESOURCE_offset, 7); - E32(ib, sq_tex_resource_word0); - E32(ib, sq_tex_resource_word1); - E32(ib, ((tex_res->base) >> 8)); - E32(ib, ((tex_res->mip_base) >> 8)); - E32(ib, sq_tex_resource_word4); - E32(ib, sq_tex_resource_word5); - E32(ib, sq_tex_resource_word6); + PACK0(SQ_TEX_RESOURCE + tex_res->id * SQ_TEX_RESOURCE_offset, 7); + E32(sq_tex_resource_word0); + E32(sq_tex_resource_word1); + E32(((tex_res->base) >> 8)); + E32(((tex_res->mip_base) >> 8)); + E32(sq_tex_resource_word4); + E32(sq_tex_resource_word5); + E32(sq_tex_resource_word6); RELOC_BATCH(tex_res->bo, domain, 0); RELOC_BATCH(tex_res->mip_bo, domain, 0); END_BATCH(); } void -r600_set_tex_sampler (ScrnInfoPtr pScrn, drmBufPtr ib, tex_sampler_t *s) +r600_set_tex_sampler (ScrnInfoPtr pScrn, tex_sampler_t *s) { RADEONInfoPtr info = RADEONPTR(pScrn); uint32_t sq_tex_sampler_word0, sq_tex_sampler_word1, sq_tex_sampler_word2; @@ -755,83 +671,83 @@ r600_set_tex_sampler (ScrnInfoPtr pScrn, drmBufPtr ib, tex_sampler_t *s) sq_tex_sampler_word2 |= SQ_TEX_SAMPLER_WORD2_0__TYPE_bit; BEGIN_BATCH(5); - PACK0(ib, SQ_TEX_SAMPLER_WORD + s->id * SQ_TEX_SAMPLER_WORD_offset, 3); - E32(ib, sq_tex_sampler_word0); - E32(ib, sq_tex_sampler_word1); - E32(ib, sq_tex_sampler_word2); + PACK0(SQ_TEX_SAMPLER_WORD + s->id * SQ_TEX_SAMPLER_WORD_offset, 3); + E32(sq_tex_sampler_word0); + E32(sq_tex_sampler_word1); + E32(sq_tex_sampler_word2); END_BATCH(); } //XXX deal with clip offsets in clip setup void -r600_set_screen_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2) +r600_set_screen_scissor(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2) { RADEONInfoPtr info = RADEONPTR(pScrn); BEGIN_BATCH(4); - PACK0(ib, PA_SC_SCREEN_SCISSOR_TL, 2); - E32(ib, ((x1 << PA_SC_SCREEN_SCISSOR_TL__TL_X_shift) | + PACK0(PA_SC_SCREEN_SCISSOR_TL, 2); + E32(((x1 << PA_SC_SCREEN_SCISSOR_TL__TL_X_shift) | (y1 << PA_SC_SCREEN_SCISSOR_TL__TL_Y_shift))); - E32(ib, ((x2 << PA_SC_SCREEN_SCISSOR_BR__BR_X_shift) | + E32(((x2 << PA_SC_SCREEN_SCISSOR_BR__BR_X_shift) | (y2 << PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift))); END_BATCH(); } void -r600_set_vport_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int id, int x1, int y1, int x2, int y2) +r600_set_vport_scissor(ScrnInfoPtr pScrn, int id, int x1, int y1, int x2, int y2) { RADEONInfoPtr info = RADEONPTR(pScrn); BEGIN_BATCH(4); - PACK0(ib, PA_SC_VPORT_SCISSOR_0_TL + id * PA_SC_VPORT_SCISSOR_0_TL_offset, 2); - E32(ib, ((x1 << PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift) | + PACK0(PA_SC_VPORT_SCISSOR_0_TL + id * PA_SC_VPORT_SCISSOR_0_TL_offset, 2); + E32(((x1 << PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift) | (y1 << PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift) | WINDOW_OFFSET_DISABLE_bit)); - E32(ib, ((x2 << PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift) | + E32(((x2 << PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift) | (y2 << PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift))); END_BATCH(); } void -r600_set_generic_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2) +r600_set_generic_scissor(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2) { RADEONInfoPtr info = RADEONPTR(pScrn); BEGIN_BATCH(4); - PACK0(ib, PA_SC_GENERIC_SCISSOR_TL, 2); - E32(ib, ((x1 << PA_SC_GENERIC_SCISSOR_TL__TL_X_shift) | + PACK0(PA_SC_GENERIC_SCISSOR_TL, 2); + E32(((x1 << PA_SC_GENERIC_SCISSOR_TL__TL_X_shift) | (y1 << PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift) | WINDOW_OFFSET_DISABLE_bit)); - E32(ib, ((x2 << PA_SC_GENERIC_SCISSOR_BR__BR_X_shift) | + E32(((x2 << PA_SC_GENERIC_SCISSOR_BR__BR_X_shift) | (y2 << PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift))); END_BATCH(); } void -r600_set_window_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2) +r600_set_window_scissor(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2) { RADEONInfoPtr info = RADEONPTR(pScrn); BEGIN_BATCH(4); - PACK0(ib, PA_SC_WINDOW_SCISSOR_TL, 2); - E32(ib, ((x1 << PA_SC_WINDOW_SCISSOR_TL__TL_X_shift) | + PACK0(PA_SC_WINDOW_SCISSOR_TL, 2); + E32(((x1 << PA_SC_WINDOW_SCISSOR_TL__TL_X_shift) | (y1 << PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift) | WINDOW_OFFSET_DISABLE_bit)); - E32(ib, ((x2 << PA_SC_WINDOW_SCISSOR_BR__BR_X_shift) | + E32(((x2 << PA_SC_WINDOW_SCISSOR_BR__BR_X_shift) | (y2 << PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift))); END_BATCH(); } void -r600_set_clip_rect(ScrnInfoPtr pScrn, drmBufPtr ib, int id, int x1, int y1, int x2, int y2) +r600_set_clip_rect(ScrnInfoPtr pScrn, int id, int x1, int y1, int x2, int y2) { RADEONInfoPtr info = RADEONPTR(pScrn); BEGIN_BATCH(4); - PACK0(ib, PA_SC_CLIPRECT_0_TL + id * PA_SC_CLIPRECT_0_TL_offset, 2); - E32(ib, ((x1 << PA_SC_CLIPRECT_0_TL__TL_X_shift) | + PACK0(PA_SC_CLIPRECT_0_TL + id * PA_SC_CLIPRECT_0_TL_offset, 2); + E32(((x1 << PA_SC_CLIPRECT_0_TL__TL_X_shift) | (y1 << PA_SC_CLIPRECT_0_TL__TL_Y_shift))); - E32(ib, ((x2 << PA_SC_CLIPRECT_0_BR__BR_X_shift) | + E32(((x2 << PA_SC_CLIPRECT_0_BR__BR_X_shift) | (y2 << PA_SC_CLIPRECT_0_BR__BR_Y_shift))); END_BATCH(); } @@ -841,7 +757,7 @@ r600_set_clip_rect(ScrnInfoPtr pScrn, drmBufPtr ib, int id, int x1, int y1, int */ void -r600_set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib) +r600_set_default_state(ScrnInfoPtr pScrn) { tex_resource_t tex_res; shader_config_t fs_conf; @@ -858,7 +774,7 @@ r600_set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib) accel_state->XInited3D = TRUE; - r600_start_3d(pScrn, accel_state->ib); + r600_start_3d(pScrn); // SQ sq_conf.ps_prio = 0; @@ -982,34 +898,34 @@ r600_set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib) break; } - r600_sq_setup(pScrn, ib, &sq_conf); + r600_sq_setup(pScrn, &sq_conf); /* set fake reloc for unused depth */ BEGIN_BATCH(3 + 2); - EREG(ib, DB_DEPTH_INFO, 0); + EREG(DB_DEPTH_INFO, 0); RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0); END_BATCH(); BEGIN_BATCH(80); if (info->ChipFamily < CHIP_FAMILY_RV770) { - EREG(ib, TA_CNTL_AUX, (( 3 << GRADIENT_CREDIT_shift) | + EREG(TA_CNTL_AUX, (( 3 << GRADIENT_CREDIT_shift) | (28 << TD_FIFO_CREDIT_shift))); - EREG(ib, VC_ENHANCE, 0); - EREG(ib, R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0); - EREG(ib, DB_DEBUG, 0x82000000); /* ? */ - EREG(ib, DB_WATERMARKS, ((4 << DEPTH_FREE_shift) | + EREG(VC_ENHANCE, 0); + EREG(R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0); + EREG(DB_DEBUG, 0x82000000); /* ? */ + EREG(DB_WATERMARKS, ((4 << DEPTH_FREE_shift) | (16 << DEPTH_FLUSH_shift) | (0 << FORCE_SUMMARIZE_shift) | (4 << DEPTH_PENDING_FREE_shift) | (16 << DEPTH_CACHELINE_FREE_shift) | 0)); } else { - EREG(ib, TA_CNTL_AUX, (( 2 << GRADIENT_CREDIT_shift) | + EREG(TA_CNTL_AUX, (( 2 << GRADIENT_CREDIT_shift) | (28 << TD_FIFO_CREDIT_shift))); - EREG(ib, VC_ENHANCE, 0); - EREG(ib, R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, VS_PC_LIMIT_ENABLE_bit); - EREG(ib, DB_DEBUG, 0); - EREG(ib, DB_WATERMARKS, ((4 << DEPTH_FREE_shift) | + EREG(VC_ENHANCE, 0); + EREG(R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, VS_PC_LIMIT_ENABLE_bit); + EREG(DB_DEBUG, 0); + EREG(DB_WATERMARKS, ((4 << DEPTH_FREE_shift) | (16 << DEPTH_FLUSH_shift) | (0 << FORCE_SUMMARIZE_shift) | (4 << DEPTH_PENDING_FREE_shift) | @@ -1017,190 +933,190 @@ r600_set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib) 0)); } - PACK0(ib, SQ_VTX_BASE_VTX_LOC, 2); - E32(ib, 0); - E32(ib, 0); - - PACK0(ib, SQ_ESGS_RING_ITEMSIZE, 9); - E32(ib, 0); // SQ_ESGS_RING_ITEMSIZE - E32(ib, 0); // SQ_GSVS_RING_ITEMSIZE - E32(ib, 0); // SQ_ESTMP_RING_ITEMSIZE - E32(ib, 0); // SQ_GSTMP_RING_ITEMSIZE - E32(ib, 0); // SQ_VSTMP_RING_ITEMSIZE - E32(ib, 0); // SQ_PSTMP_RING_ITEMSIZE - E32(ib, 0); // SQ_FBUF_RING_ITEMSIZE - E32(ib, 0); // SQ_REDUC_RING_ITEMSIZE - E32(ib, 0); // SQ_GS_VERT_ITEMSIZE + PACK0(SQ_VTX_BASE_VTX_LOC, 2); + E32(0); + E32(0); + + PACK0(SQ_ESGS_RING_ITEMSIZE, 9); + E32(0); // SQ_ESGS_RING_ITEMSIZE + E32(0); // SQ_GSVS_RING_ITEMSIZE + E32(0); // SQ_ESTMP_RING_ITEMSIZE + E32(0); // SQ_GSTMP_RING_ITEMSIZE + E32(0); // SQ_VSTMP_RING_ITEMSIZE + E32(0); // SQ_PSTMP_RING_ITEMSIZE + E32(0); // SQ_FBUF_RING_ITEMSIZE + E32(0); // SQ_REDUC_RING_ITEMSIZE + E32(0); // SQ_GS_VERT_ITEMSIZE // DB - EREG(ib, DB_DEPTH_CONTROL, 0); - PACK0(ib, DB_RENDER_CONTROL, 2); - E32(ib, STENCIL_COMPRESS_DISABLE_bit | DEPTH_COMPRESS_DISABLE_bit); + EREG(DB_DEPTH_CONTROL, 0); + PACK0(DB_RENDER_CONTROL, 2); + E32(STENCIL_COMPRESS_DISABLE_bit | DEPTH_COMPRESS_DISABLE_bit); if (info->ChipFamily < CHIP_FAMILY_RV770) - E32(ib, FORCE_SHADER_Z_ORDER_bit); + E32(FORCE_SHADER_Z_ORDER_bit); else - E32(ib, 0); - EREG(ib, DB_ALPHA_TO_MASK, ((2 << ALPHA_TO_MASK_OFFSET0_shift) | + E32(0); + EREG(DB_ALPHA_TO_MASK, ((2 << ALPHA_TO_MASK_OFFSET0_shift) | (2 << ALPHA_TO_MASK_OFFSET1_shift) | (2 << ALPHA_TO_MASK_OFFSET2_shift) | (2 << ALPHA_TO_MASK_OFFSET3_shift))); - EREG(ib, DB_SHADER_CONTROL, ((1 << Z_ORDER_shift) | /* EARLY_Z_THEN_LATE_Z */ + EREG(DB_SHADER_CONTROL, ((1 << Z_ORDER_shift) | /* EARLY_Z_THEN_LATE_Z */ DUAL_EXPORT_ENABLE_bit)); /* Only useful if no depth export */ - PACK0(ib, DB_STENCIL_CLEAR, 2); - E32(ib, 0); // DB_STENCIL_CLEAR - E32(ib, 0); // DB_DEPTH_CLEAR + PACK0(DB_STENCIL_CLEAR, 2); + E32(0); // DB_STENCIL_CLEAR + E32(0); // DB_DEPTH_CLEAR - PACK0(ib, DB_STENCILREFMASK, 3); - E32(ib, 0); // DB_STENCILREFMASK - E32(ib, 0); // DB_STENCILREFMASK_BF - E32(ib, 0); // SX_ALPHA_REF + PACK0(DB_STENCILREFMASK, 3); + E32(0); // DB_STENCILREFMASK + E32(0); // DB_STENCILREFMASK_BF + E32(0); // SX_ALPHA_REF - PACK0(ib, CB_CLRCMP_CONTROL, 4); - E32(ib, 1 << CLRCMP_FCN_SEL_shift); // CB_CLRCMP_CONTROL: use CLRCMP_FCN_SRC - E32(ib, 0); // CB_CLRCMP_SRC - E32(ib, 0); // CB_CLRCMP_DST - E32(ib, 0); // CB_CLRCMP_MSK + PACK0(CB_CLRCMP_CONTROL, 4); + E32(1 << CLRCMP_FCN_SEL_shift); // CB_CLRCMP_CONTROL: use CLRCMP_FCN_SRC + E32(0); // CB_CLRCMP_SRC + E32(0); // CB_CLRCMP_DST + E32(0); // CB_CLRCMP_MSK - EREG(ib, CB_SHADER_MASK, OUTPUT0_ENABLE_mask); - EREG(ib, R7xx_CB_SHADER_CONTROL, (RT0_ENABLE_bit)); + EREG(CB_SHADER_MASK, OUTPUT0_ENABLE_mask); + EREG(R7xx_CB_SHADER_CONTROL, (RT0_ENABLE_bit)); - PACK0(ib, SX_ALPHA_TEST_CONTROL, 5); - E32(ib, 0); // SX_ALPHA_TEST_CONTROL - E32(ib, 0x00000000); // CB_BLEND_RED - E32(ib, 0x00000000); // CB_BLEND_GREEN - E32(ib, 0x00000000); // CB_BLEND_BLUE - E32(ib, 0x00000000); // CB_BLEND_ALPHA + PACK0(SX_ALPHA_TEST_CONTROL, 5); + E32(0); // SX_ALPHA_TEST_CONTROL + E32(0x00000000); // CB_BLEND_RED + E32(0x00000000); // CB_BLEND_GREEN + E32(0x00000000); // CB_BLEND_BLUE + E32(0x00000000); // CB_BLEND_ALPHA - EREG(ib, PA_SC_WINDOW_OFFSET, ((0 << WINDOW_X_OFFSET_shift) | + EREG(PA_SC_WINDOW_OFFSET, ((0 << WINDOW_X_OFFSET_shift) | (0 << WINDOW_Y_OFFSET_shift))); if (info->ChipFamily < CHIP_FAMILY_RV770) - EREG(ib, R7xx_PA_SC_EDGERULE, 0x00000000); + EREG(R7xx_PA_SC_EDGERULE, 0x00000000); else - EREG(ib, R7xx_PA_SC_EDGERULE, 0xAAAAAAAA); + EREG(R7xx_PA_SC_EDGERULE, 0xAAAAAAAA); - EREG(ib, PA_SC_CLIPRECT_RULE, CLIP_RULE_mask); + EREG(PA_SC_CLIPRECT_RULE, CLIP_RULE_mask); END_BATCH(); /* clip boolean is set to always visible -> doesn't matter */ for (i = 0; i < PA_SC_CLIPRECT_0_TL_num; i++) - r600_set_clip_rect(pScrn, ib, i, 0, 0, 8192, 8192); + r600_set_clip_rect(pScrn, i, 0, 0, 8192, 8192); for (i = 0; i < PA_SC_VPORT_SCISSOR_0_TL_num; i++) - r600_set_vport_scissor(pScrn, ib, i, 0, 0, 8192, 8192); + r600_set_vport_scissor(pScrn, i, 0, 0, 8192, 8192); BEGIN_BATCH(49); - PACK0(ib, PA_SC_MPASS_PS_CNTL, 2); - E32(ib, 0); + PACK0(PA_SC_MPASS_PS_CNTL, 2); + E32(0); if (info->ChipFamily < CHIP_FAMILY_RV770) - E32(ib, (WALK_ORDER_ENABLE_bit | FORCE_EOV_CNTDWN_ENABLE_bit)); + E32((WALK_ORDER_ENABLE_bit | FORCE_EOV_CNTDWN_ENABLE_bit)); else - E32(ib, (FORCE_EOV_CNTDWN_ENABLE_bit | FORCE_EOV_REZ_ENABLE_bit | + E32((FORCE_EOV_CNTDWN_ENABLE_bit | FORCE_EOV_REZ_ENABLE_bit | 0x00500000)); /* ? */ - PACK0(ib, PA_SC_LINE_CNTL, 9); - E32(ib, 0); // PA_SC_LINE_CNTL - E32(ib, 0); // PA_SC_AA_CONFIG - E32(ib, ((2 << PA_SU_VTX_CNTL__ROUND_MODE_shift) | PIX_CENTER_bit | // PA_SU_VTX_CNTL + PACK0(PA_SC_LINE_CNTL, 9); + E32(0); // PA_SC_LINE_CNTL + E32(0); // PA_SC_AA_CONFIG + E32(((2 << PA_SU_VTX_CNTL__ROUND_MODE_shift) | PIX_CENTER_bit | // PA_SU_VTX_CNTL (5 << QUANT_MODE_shift))); /* Round to Even, fixed point 1/256 */ - EFLOAT(ib, 1.0); // PA_CL_GB_VERT_CLIP_ADJ - EFLOAT(ib, 1.0); // PA_CL_GB_VERT_DISC_ADJ - EFLOAT(ib, 1.0); // PA_CL_GB_HORZ_CLIP_ADJ - EFLOAT(ib, 1.0); // PA_CL_GB_HORZ_DISC_ADJ - E32(ib, 0); // PA_SC_AA_SAMPLE_LOCS_MCTX - E32(ib, 0); // PA_SC_AA_SAMPLE_LOCS_8S_WD1_M - - EREG(ib, PA_SC_AA_MASK, 0xFFFFFFFF); - - PACK0(ib, PA_CL_CLIP_CNTL, 5); - E32(ib, CLIP_DISABLE_bit); // PA_CL_CLIP_CNTL - E32(ib, FACE_bit); // PA_SU_SC_MODE_CNTL - E32(ib, VTX_XY_FMT_bit); // PA_CL_VTE_CNTL - E32(ib, 0); // PA_CL_VS_OUT_CNTL - E32(ib, 0); // PA_CL_NANINF_CNTL - - PACK0(ib, PA_SU_POLY_OFFSET_DB_FMT_CNTL, 6); - E32(ib, 0); // PA_SU_POLY_OFFSET_DB_FMT_CNTL - E32(ib, 0); // PA_SU_POLY_OFFSET_CLAMP - E32(ib, 0); // PA_SU_POLY_OFFSET_FRONT_SCALE - E32(ib, 0); // PA_SU_POLY_OFFSET_FRONT_OFFSET - E32(ib, 0); // PA_SU_POLY_OFFSET_BACK_SCALE - E32(ib, 0); // PA_SU_POLY_OFFSET_BACK_OFFSET + EFLOAT(1.0); // PA_CL_GB_VERT_CLIP_ADJ + EFLOAT(1.0); // PA_CL_GB_VERT_DISC_ADJ + EFLOAT(1.0); // PA_CL_GB_HORZ_CLIP_ADJ + EFLOAT(1.0); // PA_CL_GB_HORZ_DISC_ADJ + E32(0); // PA_SC_AA_SAMPLE_LOCS_MCTX + E32(0); // PA_SC_AA_SAMPLE_LOCS_8S_WD1_M + + EREG(PA_SC_AA_MASK, 0xFFFFFFFF); + + PACK0(PA_CL_CLIP_CNTL, 5); + E32(CLIP_DISABLE_bit); // PA_CL_CLIP_CNTL + E32(FACE_bit); // PA_SU_SC_MODE_CNTL + E32(VTX_XY_FMT_bit); // PA_CL_VTE_CNTL + E32(0); // PA_CL_VS_OUT_CNTL + E32(0); // PA_CL_NANINF_CNTL + + PACK0(PA_SU_POLY_OFFSET_DB_FMT_CNTL, 6); + E32(0); // PA_SU_POLY_OFFSET_DB_FMT_CNTL + E32(0); // PA_SU_POLY_OFFSET_CLAMP + E32(0); // PA_SU_POLY_OFFSET_FRONT_SCALE + E32(0); // PA_SU_POLY_OFFSET_FRONT_OFFSET + E32(0); // PA_SU_POLY_OFFSET_BACK_SCALE + E32(0); // PA_SU_POLY_OFFSET_BACK_OFFSET // SPI if (info->ChipFamily < CHIP_FAMILY_RV770) - EREG(ib, R7xx_SPI_THREAD_GROUPING, 0); + EREG(R7xx_SPI_THREAD_GROUPING, 0); else - EREG(ib, R7xx_SPI_THREAD_GROUPING, (1 << PS_GROUPING_shift)); + EREG(R7xx_SPI_THREAD_GROUPING, (1 << PS_GROUPING_shift)); /* default Interpolator setup */ - EREG(ib, SPI_VS_OUT_ID_0, ((0 << SEMANTIC_0_shift) | + EREG(SPI_VS_OUT_ID_0, ((0 << SEMANTIC_0_shift) | (1 << SEMANTIC_1_shift))); - PACK0(ib, SPI_PS_INPUT_CNTL_0 + (0 << 2), 2); + PACK0(SPI_PS_INPUT_CNTL_0 + (0 << 2), 2); /* SPI_PS_INPUT_CNTL_0 maps to GPR[0] - load with semantic id 0 */ - E32(ib, ((0 << SEMANTIC_shift) | + E32(((0 << SEMANTIC_shift) | (0x01 << DEFAULT_VAL_shift) | SEL_CENTROID_bit)); /* SPI_PS_INPUT_CNTL_1 maps to GPR[1] - load with semantic id 1 */ - E32(ib, ((1 << SEMANTIC_shift) | + E32(((1 << SEMANTIC_shift) | (0x01 << DEFAULT_VAL_shift) | SEL_CENTROID_bit)); - PACK0(ib, SPI_INPUT_Z, 4); - E32(ib, 0); // SPI_INPUT_Z - E32(ib, 0); // SPI_FOG_CNTL - E32(ib, 0); // SPI_FOG_FUNC_SCALE - E32(ib, 0); // SPI_FOG_FUNC_BIAS + PACK0(SPI_INPUT_Z, 4); + E32(0); // SPI_INPUT_Z + E32(0); // SPI_FOG_CNTL + E32(0); // SPI_FOG_FUNC_SCALE + E32(0); // SPI_FOG_FUNC_BIAS END_BATCH(); // clear FS fs_conf.bo = accel_state->shaders_bo; - r600_fs_setup(pScrn, ib, &fs_conf, RADEON_GEM_DOMAIN_VRAM); + r600_fs_setup(pScrn, &fs_conf, RADEON_GEM_DOMAIN_VRAM); // VGT BEGIN_BATCH(46); - PACK0(ib, VGT_MAX_VTX_INDX, 4); - E32(ib, 0xffffff); // VGT_MAX_VTX_INDX - E32(ib, 0); // VGT_MIN_VTX_INDX - E32(ib, 0); // VGT_INDX_OFFSET - E32(ib, 0); // VGT_MULTI_PRIM_IB_RESET_INDX - - EREG(ib, VGT_PRIMITIVEID_EN, 0); - EREG(ib, VGT_MULTI_PRIM_IB_RESET_EN, 0); - - PACK0(ib, VGT_INSTANCE_STEP_RATE_0, 2); - E32(ib, 0); // VGT_INSTANCE_STEP_RATE_0 - E32(ib, 0); // VGT_INSTANCE_STEP_RATE_1 - - PACK0(ib, PA_SU_POINT_SIZE, 17); - E32(ib, 0); // PA_SU_POINT_SIZE - E32(ib, 0); // PA_SU_POINT_MINMAX - E32(ib, (8 << PA_SU_LINE_CNTL__WIDTH_shift)); /* Line width 1 pixel */ // PA_SU_LINE_CNTL - E32(ib, 0); // PA_SC_LINE_STIPPLE - E32(ib, 0); // VGT_OUTPUT_PATH_CNTL - E32(ib, 0); // VGT_HOS_CNTL - E32(ib, 0); // VGT_HOS_MAX_TESS_LEVEL - E32(ib, 0); // VGT_HOS_MIN_TESS_LEVEL - E32(ib, 0); // VGT_HOS_REUSE_DEPTH - E32(ib, 0); // VGT_GROUP_PRIM_TYPE - E32(ib, 0); // VGT_GROUP_FIRST_DECR - E32(ib, 0); // VGT_GROUP_DECR - E32(ib, 0); // VGT_GROUP_VECT_0_CNTL - E32(ib, 0); // VGT_GROUP_VECT_1_CNTL - E32(ib, 0); // VGT_GROUP_VECT_0_FMT_CNTL - E32(ib, 0); // VGT_GROUP_VECT_1_FMT_CNTL - E32(ib, 0); // VGT_GS_MODE - - PACK0(ib, VGT_STRMOUT_EN, 3); - E32(ib, 0); // VGT_STRMOUT_EN - E32(ib, 0); // VGT_REUSE_OFF - E32(ib, 0); // VGT_VTX_CNT_EN - - EREG(ib, VGT_STRMOUT_BUFFER_EN, 0); - EREG(ib, SX_MISC, 0); + PACK0(VGT_MAX_VTX_INDX, 4); + E32(0xffffff); // VGT_MAX_VTX_INDX + E32(0); // VGT_MIN_VTX_INDX + E32(0); // VGT_INDX_OFFSET + E32(0); // VGT_MULTI_PRIM_IB_RESET_INDX + + EREG(VGT_PRIMITIVEID_EN, 0); + EREG(VGT_MULTI_PRIM_IB_RESET_EN, 0); + + PACK0(VGT_INSTANCE_STEP_RATE_0, 2); + E32(0); // VGT_INSTANCE_STEP_RATE_0 + E32(0); // VGT_INSTANCE_STEP_RATE_1 + + PACK0(PA_SU_POINT_SIZE, 17); + E32(0); // PA_SU_POINT_SIZE + E32(0); // PA_SU_POINT_MINMAX + E32((8 << PA_SU_LINE_CNTL__WIDTH_shift)); /* Line width 1 pixel */ // PA_SU_LINE_CNTL + E32(0); // PA_SC_LINE_STIPPLE + E32(0); // VGT_OUTPUT_PATH_CNTL + E32(0); // VGT_HOS_CNTL + E32(0); // VGT_HOS_MAX_TESS_LEVEL + E32(0); // VGT_HOS_MIN_TESS_LEVEL + E32(0); // VGT_HOS_REUSE_DEPTH + E32(0); // VGT_GROUP_PRIM_TYPE + E32(0); // VGT_GROUP_FIRST_DECR + E32(0); // VGT_GROUP_DECR + E32(0); // VGT_GROUP_VECT_0_CNTL + E32(0); // VGT_GROUP_VECT_1_CNTL + E32(0); // VGT_GROUP_VECT_0_FMT_CNTL + E32(0); // VGT_GROUP_VECT_1_FMT_CNTL + E32(0); // VGT_GS_MODE + + PACK0(VGT_STRMOUT_EN, 3); + E32(0); // VGT_STRMOUT_EN + E32(0); // VGT_REUSE_OFF + E32(0); // VGT_VTX_CNT_EN + + EREG(VGT_STRMOUT_BUFFER_EN, 0); + EREG(SX_MISC, 0); END_BATCH(); } @@ -1210,7 +1126,7 @@ r600_set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib) */ void -r600_draw_immd(ScrnInfoPtr pScrn, drmBufPtr ib, draw_config_t *draw_conf, uint32_t *indices) +r600_draw_immd(ScrnInfoPtr pScrn, draw_config_t *draw_conf, uint32_t *indices) { RADEONInfoPtr info = RADEONPTR(pScrn); uint32_t i, count; @@ -1223,52 +1139,52 @@ r600_draw_immd(ScrnInfoPtr pScrn, drmBufPtr ib, draw_config_t *draw_conf, uint32 count += draw_conf->num_indices; BEGIN_BATCH(8 + count); - EREG(ib, VGT_PRIMITIVE_TYPE, draw_conf->prim_type); - PACK3(ib, IT_INDEX_TYPE, 1); + EREG(VGT_PRIMITIVE_TYPE, draw_conf->prim_type); + PACK3(IT_INDEX_TYPE, 1); #if X_BYTE_ORDER == X_BIG_ENDIAN - E32(ib, IT_INDEX_TYPE_SWAP_MODE(ENDIAN_8IN32) | draw_conf->index_type); + E32(IT_INDEX_TYPE_SWAP_MODE(ENDIAN_8IN32) | draw_conf->index_type); #else - E32(ib, draw_conf->index_type); + E32(draw_conf->index_type); #endif - PACK3(ib, IT_NUM_INSTANCES, 1); - E32(ib, draw_conf->num_instances); + PACK3(IT_NUM_INSTANCES, 1); + E32(draw_conf->num_instances); - PACK3(ib, IT_DRAW_INDEX_IMMD, count); - E32(ib, draw_conf->num_indices); - E32(ib, draw_conf->vgt_draw_initiator); + PACK3(IT_DRAW_INDEX_IMMD, count); + E32(draw_conf->num_indices); + E32(draw_conf->vgt_draw_initiator); if (draw_conf->index_type == DI_INDEX_SIZE_16_BIT) { for (i = 0; i < draw_conf->num_indices; i += 2) { if ((i + 1) == draw_conf->num_indices) - E32(ib, indices[i]); + E32(indices[i]); else - E32(ib, (indices[i] | (indices[i + 1] << 16))); + E32((indices[i] | (indices[i + 1] << 16))); } } else { for (i = 0; i < draw_conf->num_indices; i++) - E32(ib, indices[i]); + E32(indices[i]); } END_BATCH(); } void -r600_draw_auto(ScrnInfoPtr pScrn, drmBufPtr ib, draw_config_t *draw_conf) +r600_draw_auto(ScrnInfoPtr pScrn, draw_config_t *draw_conf) { RADEONInfoPtr info = RADEONPTR(pScrn); BEGIN_BATCH(10); - EREG(ib, VGT_PRIMITIVE_TYPE, draw_conf->prim_type); - PACK3(ib, IT_INDEX_TYPE, 1); + EREG(VGT_PRIMITIVE_TYPE, draw_conf->prim_type); + PACK3(IT_INDEX_TYPE, 1); #if X_BYTE_ORDER == X_BIG_ENDIAN - E32(ib, IT_INDEX_TYPE_SWAP_MODE(ENDIAN_8IN32) | draw_conf->index_type); + E32(IT_INDEX_TYPE_SWAP_MODE(ENDIAN_8IN32) | draw_conf->index_type); #else - E32(ib, draw_conf->index_type); + E32(draw_conf->index_type); #endif - PACK3(ib, IT_NUM_INSTANCES, 1); - E32(ib, draw_conf->num_instances); - PACK3(ib, IT_DRAW_INDEX_AUTO, 2); - E32(ib, draw_conf->num_indices); - E32(ib, draw_conf->vgt_draw_initiator); + PACK3(IT_NUM_INSTANCES, 1); + E32(draw_conf->num_instances); + PACK3(IT_DRAW_INDEX_AUTO, 2); + E32(draw_conf->num_indices); + E32(draw_conf->vgt_draw_initiator); END_BATCH(); } @@ -1286,7 +1202,7 @@ void r600_finish_op(ScrnInfoPtr pScrn, int vtx_size) CLEAR (vtx_res); if (accel_state->vbo.vb_offset == accel_state->vbo.vb_start_op) { - R600IBDiscard(pScrn, accel_state->ib); + R600IBDiscard(pScrn); return; } @@ -1301,7 +1217,7 @@ void r600_finish_op(ScrnInfoPtr pScrn, int vtx_size) #if X_BYTE_ORDER == X_BIG_ENDIAN vtx_res.endian = SQ_ENDIAN_8IN32; #endif - r600_set_vtx_resource(pScrn, accel_state->ib, &vtx_res, RADEON_GEM_DOMAIN_GTT); + r600_set_vtx_resource(pScrn, &vtx_res, RADEON_GEM_DOMAIN_GTT); /* Draw */ draw_conf.prim_type = DI_PT_RECTLIST; @@ -1310,22 +1226,18 @@ void r600_finish_op(ScrnInfoPtr pScrn, int vtx_size) draw_conf.num_indices = vtx_res.vtx_num_entries / vtx_res.vtx_size_dw; draw_conf.index_type = DI_INDEX_SIZE_16_BIT; - r600_draw_auto(pScrn, accel_state->ib, &draw_conf); + r600_draw_auto(pScrn, &draw_conf); /* XXX drm should handle this in fence submit */ - r600_wait_3d_idle_clean(pScrn, accel_state->ib); + r600_wait_3d_idle_clean(pScrn); /* sync dst surface */ - r600_cp_set_surface_sync(pScrn, accel_state->ib, (CB_ACTION_ENA_bit | CB0_DEST_BASE_ENA_bit), + r600_cp_set_surface_sync(pScrn, (CB_ACTION_ENA_bit | CB0_DEST_BASE_ENA_bit), accel_state->dst_size, accel_state->dst_obj.offset, accel_state->dst_obj.bo, 0, accel_state->dst_obj.domain); accel_state->vbo.vb_start_op = -1; accel_state->ib_reset_op = 0; -#if KMS_MULTI_OP - if (!info->cs) -#endif - R600CPFlushIndirect(pScrn, accel_state->ib); } diff --git a/src/radeon.h b/src/radeon.h index 151ef43b..d45c4ccf 100644 --- a/src/radeon.h +++ b/src/radeon.h @@ -45,17 +45,12 @@ #include "xf86str.h" #include "compiler.h" -#include "xf86fbman.h" /* PCI support */ #include "xf86Pci.h" -#ifdef USE_EXA #include "exa.h" -#endif -#ifdef USE_XAA -#include "xaa.h" -#endif + /* Exa and Cursor Support */ #include "vbe.h" @@ -68,13 +63,8 @@ #include "xf86xv.h" #include "radeon_probe.h" -#include "radeon_tv.h" /* DRI support */ -#ifdef XF86DRI -#define _XF86DRI_SERVER_ -#include "dri.h" -#include "GL/glxint.h" #include "xf86drm.h" #include "radeon_drm.h" @@ -82,20 +72,15 @@ #include "damage.h" #include "globals.h" #endif -#endif #include "xf86Crtc.h" #include "X11/Xatom.h" -#ifdef XF86DRM_MODE #include "radeon_bo.h" #include "radeon_cs.h" #include "radeon_dri2.h" #include "drmmode_display.h" #include "radeon_surface.h" -#else -#include "radeon_dummy_bufmgr.h" -#endif /* Render support */ #ifdef RENDER @@ -157,96 +142,31 @@ extern unsigned int xf86ModeBandwidth(DisplayModePtr mode, int depth); typedef enum { OPTION_NOACCEL, OPTION_SW_CURSOR, - OPTION_DAC_6BIT, - OPTION_DAC_8BIT, -#ifdef XF86DRI - OPTION_BUS_TYPE, - OPTION_CP_PIO, - OPTION_USEC_TIMEOUT, - OPTION_AGP_MODE, - OPTION_AGP_FW, - OPTION_GART_SIZE, - OPTION_GART_SIZE_OLD, - OPTION_RING_SIZE, - OPTION_BUFFER_SIZE, - OPTION_DEPTH_MOVE, OPTION_PAGE_FLIP, - OPTION_NO_BACKBUFFER, - OPTION_XV_DMA, - OPTION_FBTEX_PERCENT, - OPTION_DEPTH_BITS, - OPTION_PCIAPER_SIZE, -#ifdef USE_EXA OPTION_ACCEL_DFS, OPTION_EXA_PIXMAPS, -#endif -#endif OPTION_IGNORE_EDID, - OPTION_CUSTOM_EDID, - OPTION_DISP_PRIORITY, - OPTION_PANEL_SIZE, - OPTION_MIN_DOTCLOCK, OPTION_COLOR_TILING, OPTION_COLOR_TILING_2D, -#ifdef XvExtension - OPTION_VIDEO_KEY, - OPTION_RAGE_THEATRE_CRYSTAL, - OPTION_RAGE_THEATRE_TUNER_PORT, - OPTION_RAGE_THEATRE_COMPOSITE_PORT, - OPTION_RAGE_THEATRE_SVIDEO_PORT, - OPTION_TUNER_TYPE, - OPTION_RAGE_THEATRE_MICROC_PATH, - OPTION_RAGE_THEATRE_MICROC_TYPE, - OPTION_SCALER_WIDTH, -#endif #ifdef RENDER OPTION_RENDER_ACCEL, OPTION_SUBPIXEL_ORDER, #endif - OPTION_SHOWCACHE, - OPTION_CLOCK_GATING, - OPTION_BIOS_HOTKEYS, - OPTION_VGA_ACCESS, - OPTION_REVERSE_DDC, - OPTION_LVDS_PROBE_PLL, OPTION_ACCELMETHOD, - OPTION_CONNECTORTABLE, OPTION_DRI, - OPTION_DEFAULT_CONNECTOR_TABLE, -#if defined(__powerpc__) - OPTION_MAC_MODEL, -#endif - OPTION_DEFAULT_TMDS_PLL, - OPTION_TVDAC_LOAD_DETECT, - OPTION_FORCE_TVOUT, OPTION_TVSTD, - OPTION_IGNORE_LID_STATUS, - OPTION_DEFAULT_TVDAC_ADJ, - OPTION_INT10, OPTION_EXA_VSYNC, - OPTION_ATOM_TVOUT, - OPTION_R4XX_ATOM, - OPTION_FORCE_LOW_POWER, - OPTION_DYNAMIC_PM, - OPTION_NEW_PLL, OPTION_ZAPHOD_HEADS, OPTION_SWAPBUFFERS_WAIT } RADEONOpts; -#define RADEON_IDLE_RETRY 16 /* Fall out of idle loops after this count */ -#define RADEON_TIMEOUT 2000000 /* Fall out of wait loops after this count */ - #define RADEON_VSYNC_TIMEOUT 20000 /* Maximum wait for VSYNC (in usecs) */ /* Buffer are aligned on 4096 byte boundaries */ #define RADEON_GPU_PAGE_SIZE 4096 #define RADEON_BUFFER_ALIGN (RADEON_GPU_PAGE_SIZE - 1) -#define RADEON_VBIOS_SIZE 0x00010000 -#define RADEON_USE_RMX 0x80000000 /* mode flag for using RMX - * Need to comfirm this is not used - * for something else. - */ + #define xFixedToFloat(f) (((float) (f)) / 65536) @@ -261,54 +181,6 @@ typedef enum { #define RADEONPTR(pScrn) ((RADEONInfoPtr)(pScrn)->driverPrivate) typedef struct { - int revision; - uint16_t rr1_offset; - uint16_t rr2_offset; - uint16_t dyn_clk_offset; - uint16_t pll_offset; - uint16_t mem_config_offset; - uint16_t mem_reset_offset; - uint16_t short_mem_offset; - uint16_t rr3_offset; - uint16_t rr4_offset; -} RADEONBIOSInitTable; - -#define RADEON_PLL_USE_BIOS_DIVS (1 << 0) -#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) -#define RADEON_PLL_USE_REF_DIV (1 << 2) -#define RADEON_PLL_LEGACY (1 << 3) -#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) -#define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) -#define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) -#define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) -#define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) -#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) -#define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) -#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) -#define RADEON_PLL_USE_POST_DIV (1 << 12) - -typedef struct { - uint32_t reference_freq; - uint32_t reference_div; - uint32_t post_div; - uint32_t pll_in_min; - uint32_t pll_in_max; - uint32_t pll_out_min; - uint32_t pll_out_max; - uint16_t xclk; - - uint32_t min_ref_div; - uint32_t max_ref_div; - uint32_t min_post_div; - uint32_t max_post_div; - uint32_t min_feedback_div; - uint32_t max_feedback_div; - uint32_t min_frac_feedback_div; - uint32_t max_frac_feedback_div; - uint32_t best_vco; -} RADEONPLLRec, *RADEONPLLPtr; - -typedef struct { int bitsPerPixel; int depth; int displayWidth; @@ -382,75 +254,16 @@ typedef struct { (info->ChipFamily == CHIP_FAMILY_RS300) || \ (info->ChipFamily == CHIP_FAMILY_R200)) -/* - * Errata workarounds - */ -typedef enum { - CHIP_ERRATA_R300_CG = 0x00000001, - CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, - CHIP_ERRATA_PLL_DELAY = 0x00000004 -} RADEONErrata; - -typedef enum { - RADEON_DVOCHIP_NONE, - RADEON_SIL_164, - RADEON_SIL_1178 -} RADEONExtTMDSChip; - -#if defined(__powerpc__) -typedef enum { - RADEON_MAC_NONE, - RADEON_MAC_IBOOK, - RADEON_MAC_POWERBOOK_EXTERNAL, - RADEON_MAC_POWERBOOK_INTERNAL, - RADEON_MAC_POWERBOOK_VGA, - RADEON_MAC_MINI_EXTERNAL, - RADEON_MAC_MINI_INTERNAL, - RADEON_MAC_IMAC_G5_ISIGHT, - RADEON_MAC_EMAC, - RADEON_MAC_SAM440EP -} RADEONMacModel; -#endif - typedef enum { CARD_PCI, CARD_AGP, CARD_PCIE } RADEONCardType; -typedef enum { - POWER_DEFAULT, - POWER_LOW, - POWER_HIGH -} RADEONPMType; - -typedef struct { - RADEONPMType type; - uint32_t sclk; - uint32_t mclk; - uint32_t pcie_lanes; - uint32_t flags; -} RADEONPowerMode; - -typedef struct { - /* power modes */ - int num_modes; - int current_mode; - RADEONPowerMode mode[3]; - - Bool clock_gating_enabled; - Bool dynamic_mode_enabled; - Bool force_low_power_enabled; -} RADEONPowerManagement; - -typedef struct _atomBiosHandle *atomBiosHandlePtr; - struct radeon_exa_pixmap_priv { struct radeon_bo *bo; uint32_t tiling_flags; -#ifdef XF86DRM_MODE struct radeon_surface surface; -#endif Bool bo_mapped; }; @@ -473,146 +286,6 @@ struct radeon_2d_state { struct radeon_bo *src_bo; }; -#ifdef XF86DRI -struct radeon_cp { - Bool CPRuns; /* CP is running */ - Bool CPInUse; /* CP has been used by X server */ - Bool CPStarted; /* CP has started */ - int CPMode; /* CP mode that server/clients use */ - int CPFifoSize; /* Size of the CP command FIFO */ - int CPusecTimeout; /* CP timeout in usecs */ - Bool needCacheFlush; - - /* CP accleration */ - drmBufPtr indirectBuffer; - int indirectStart; - - /* Debugging info for BEGIN_RING/ADVANCE_RING pairs. */ - int dma_begin_count; - char *dma_debug_func; - int dma_debug_lineno; - - }; - -typedef struct { - /* Nothing here yet */ - int dummy; -} RADEONConfigPrivRec, *RADEONConfigPrivPtr; - -typedef struct { - /* Nothing here yet */ - int dummy; -} RADEONDRIContextRec, *RADEONDRIContextPtr; - -struct radeon_dri { - Bool noBackBuffer; - - Bool newMemoryMap; - drmVersionPtr pLibDRMVersion; - drmVersionPtr pKernelDRMVersion; - DRIInfoPtr pDRIInfo; - int drmFD; - int numVisualConfigs; - __GLXvisualConfig *pVisualConfigs; - RADEONConfigPrivPtr pVisualConfigsPriv; - Bool (*DRICloseScreen)(CLOSE_SCREEN_ARGS_DECL); - - drm_handle_t fbHandle; - - drmSize registerSize; - drm_handle_t registerHandle; - - drmSize pciSize; - drm_handle_t pciMemHandle; - unsigned char *PCI; /* Map */ - - Bool depthMoves; /* Enable depth moves -- slow! */ - Bool allowPageFlip; /* Enable 3d page flipping */ -#ifdef DAMAGE - DamagePtr pDamage; - RegionRec driRegion; -#endif - Bool have3DWindows; /* Are there any 3d clients? */ - - int pciAperSize; - drmSize gartSize; - drm_handle_t agpMemHandle; /* Handle from drmAgpAlloc */ - unsigned long gartOffset; - unsigned char *AGP; /* Map */ - int agpMode; - - uint32_t pciCommand; - - /* CP ring buffer data */ - unsigned long ringStart; /* Offset into GART space */ - drm_handle_t ringHandle; /* Handle from drmAddMap */ - drmSize ringMapSize; /* Size of map */ - int ringSize; /* Size of ring (in MB) */ - drmAddress ring; /* Map */ - int ringSizeLog2QW; - - unsigned long ringReadOffset; /* Offset into GART space */ - drm_handle_t ringReadPtrHandle; /* Handle from drmAddMap */ - drmSize ringReadMapSize; /* Size of map */ - drmAddress ringReadPtr; /* Map */ - - /* CP vertex/indirect buffer data */ - unsigned long bufStart; /* Offset into GART space */ - drm_handle_t bufHandle; /* Handle from drmAddMap */ - drmSize bufMapSize; /* Size of map */ - int bufSize; /* Size of buffers (in MB) */ - drmAddress buf; /* Map */ - int bufNumBufs; /* Number of buffers */ - drmBufMapPtr buffers; /* Buffer map */ - - /* CP GART Texture data */ - unsigned long gartTexStart; /* Offset into GART space */ - drm_handle_t gartTexHandle; /* Handle from drmAddMap */ - drmSize gartTexMapSize; /* Size of map */ - int gartTexSize; /* Size of GART tex space (in MB) */ - drmAddress gartTex; /* Map */ - int log2GARTTexGran; - - /* DRI screen private data */ - int fbX; - int fbY; - int backX; - int backY; - int depthX; - int depthY; - - int frontOffset; - int frontPitch; - int backOffset; - int backPitch; - int depthOffset; - int depthPitch; - int depthBits; - int textureOffset; - int textureSize; - int log2TexGran; - - int pciGartSize; - uint32_t pciGartOffset; - void *pciGartBackup; - - int irq; - -#ifdef USE_XAA - uint32_t frontPitchOffset; - uint32_t backPitchOffset; - uint32_t depthPitchOffset; - - /* offscreen memory management */ - int backLines; - FBAreaPtr backArea; - int depthTexLines; - FBAreaPtr depthTexArea; -#endif - -}; -#endif - #define DMA_BO_FREE_TIME 1000 struct radeon_dma_bo { @@ -630,16 +303,13 @@ struct r600_accel_object { uint32_t domain; struct radeon_bo *bo; uint32_t tiling_flags; -#if defined(XF86DRM_MODE) struct radeon_surface *surface; -#endif }; struct radeon_vbo_object { int vb_offset; uint64_t vb_mc_addr; int vb_total; - void *vb_ptr; uint32_t vb_size; uint32_t vb_op_vert_size; int32_t vb_start_op; @@ -649,11 +319,10 @@ struct radeon_vbo_object { struct radeon_accel_state { /* common accel data */ - int fifo_slots; /* Free slots in the FIFO (64 max) */ /* Computed values for Radeon */ uint32_t dp_gui_master_cntl; uint32_t dp_gui_master_cntl_clip; - uint32_t trans_color; + /* Saved values for ScreenToScreenCopy */ int xdir; int ydir; @@ -667,7 +336,6 @@ struct radeon_accel_state { Bool has_tcl; Bool allowHWDFS; -#ifdef USE_EXA /* EXA */ ExaDriverPtr exa; int exaSyncMarker; @@ -697,22 +365,17 @@ struct radeon_accel_state { unsigned num_vtx; Bool vsync; - drmBufPtr ib; - struct radeon_vbo_object vbo; struct radeon_vbo_object cbuf; /* where to discard IB from if we cancel operation */ uint32_t ib_reset_op; -#ifdef XF86DRM_MODE struct radeon_dma_bo bo_free; struct radeon_dma_bo bo_wait; struct radeon_dma_bo bo_reserved; Bool use_vbos; -#endif void (*finish_op)(ScrnInfoPtr, int); // shader storage - ExaOffscreenArea *shaders; struct radeon_bo *shaders_bo; uint32_t solid_vs_offset; uint32_t solid_ps_offset; @@ -744,11 +407,8 @@ struct radeon_accel_state { uint32_t ps_size; uint64_t ps_mc_addr; - // UTS/DFS - drmBufPtr scratch; - // solid/copy - ExaOffscreenArea *copy_area; + void *copy_area; struct radeon_bo *copy_area_bo; Bool same_surface; int rop; @@ -762,42 +422,6 @@ struct radeon_accel_state { xf86CrtcPtr vline_crtc; int vline_y1; int vline_y2; -#endif - -#ifdef USE_XAA - /* XAA */ - XAAInfoRecPtr accel; - /* ScanlineScreenToScreenColorExpand support */ - unsigned char *scratch_buffer[1]; - unsigned char *scratch_save; - int scanline_x; - int scanline_y; - int scanline_w; - int scanline_h; - int scanline_h_w; - int scanline_words; - int scanline_direct; - int scanline_bpp; /* Only used for ImageWrite */ - int scanline_fg; - int scanline_bg; - int scanline_hpass; - int scanline_x1clip; - int scanline_x2clip; - /* Saved values for DashedTwoPointLine */ - int dashLen; - uint32_t dashPattern; - int dash_fg; - int dash_bg; - - FBLinearPtr RenderTex; - void (*RenderCallback)(ScrnInfoPtr); - Time RenderTimeout; - /* - * XAAForceTransBlit is used to change the behavior of the XAA - * SetupForScreenToScreenCopy function, to make it DGA-friendly. - */ - Bool XAAForceTransBlit; -#endif }; @@ -809,69 +433,13 @@ typedef struct { #endif int Chipset; RADEONChipFamily ChipFamily; - RADEONErrata ChipErrata; - - unsigned long long LinearAddr; /* Frame buffer physical address */ - unsigned long long MMIOAddr; /* MMIO region physical address */ - unsigned long long BIOSAddr; /* BIOS physical address */ - uint64_t fbLocation; - uint32_t gartLocation; - uint32_t mc_fb_location; - uint32_t mc_agp_location; - uint32_t mc_agp_location_hi; - - void *MMIO; /* Map of MMIO region */ - void *FB; /* Map of frame buffer */ - uint8_t *VBIOS; /* Video BIOS pointer */ - - Bool IsAtomBios; /* New BIOS used in R420 etc. */ - int ROMHeaderStart; /* Start of the ROM Info Table */ - int MasterDataStart; /* Offset for Master Data Table for ATOM BIOS */ - - uint32_t MemCntl; - uint32_t BusCntl; - unsigned long MMIOSize; /* MMIO region physical address */ - unsigned long FbMapSize; /* Size of frame buffer, in bytes */ - unsigned long FbSecureSize; /* Size of secured fb area at end of - framebuffer */ - - Bool IsMobility; /* Mobile chips for laptops */ + Bool IsIGP; /* IGP chips */ - Bool HasSingleDAC; /* only TVDAC on chip */ - Bool ddc_mode; /* Validate mode by matching exactly - * the modes supported in DDC data - */ - Bool R300CGWorkaround; - - /* EDID or BIOS values for FPs */ - int RefDivider; - int FeedbackDivider; - int PostDivider; - Bool UseBiosDividers; - /* EDID data using DDC interface */ - Bool ddc_bios; - Bool ddc1; - Bool ddc2; - - RADEONPLLRec pll; - int default_dispclk; - int dp_extclk; - - int RamWidth; - float sclk; /* in MHz */ - float mclk; /* in MHz */ - Bool IsDDR; - int DispPriority; - - RADEONSavePtr SavedReg; /* Original (text) mode */ - RADEONSavePtr ModeReg; /* Current mode */ + Bool (*CloseScreen)(CLOSE_SCREEN_ARGS_DECL); void (*BlockHandler)(BLOCKHANDLER_ARGS_DECL); - Bool PaletteSavedOnVT; /* Palette saved on last VT switch */ - - xf86CursorInfoPtr cursor; #ifdef ARGB_CURSOR Bool cursor_argb; #endif @@ -883,135 +451,40 @@ typedef struct { RADEONFBLayout CurrentLayout; -#ifdef XF86DRI Bool directRenderingEnabled; - Bool directRenderingInited; RADEONCardType cardType; /* Current card is a PCI card */ - struct radeon_cp *cp; - struct radeon_dri *dri; -#ifdef XF86DRM_MODE struct radeon_dri2 dri2; -#endif -#ifdef USE_EXA Bool accelDFS; -#endif - Bool DMAForXv; -#endif /* XF86DRI */ /* accel */ Bool RenderAccel; /* Render */ Bool allowColorTiling; Bool allowColorTiling2D; - Bool tilingEnabled; /* mirror of sarea->tiling_enabled */ struct radeon_accel_state *accel_state; Bool accelOn; - Bool useEXA; -#ifdef USE_EXA Bool exa_pixmaps; Bool exa_force_create; XF86ModReqInfo exaReq; -#endif -#ifdef USE_XAA - XF86ModReqInfo xaaReq; -#endif - /* XVideo */ - XF86VideoAdaptorPtr adaptor; - void (*VideoTimerCallback)(ScrnInfoPtr, Time); - int videoKey; - int RageTheatreCrystal; - int RageTheatreTunerPort; - int RageTheatreCompositePort; - int RageTheatreSVideoPort; - int tunerType; - char* RageTheatreMicrocPath; - char* RageTheatreMicrocType; - Bool MM_TABLE_valid; - struct { - uint8_t table_revision; - uint8_t table_size; - uint8_t tuner_type; - uint8_t audio_chip; - uint8_t product_id; - uint8_t tuner_voltage_teletext_fm; - uint8_t i2s_config; /* configuration of the sound chip */ - uint8_t video_decoder_type; - uint8_t video_decoder_host_config; - uint8_t input[5]; - } MM_TABLE; - uint16_t video_decoder_type; - int overlay_scaler_buffer_width; - int ecp_div; unsigned int xv_max_width; unsigned int xv_max_height; /* general */ OptionInfoPtr Options; - DisplayModePtr currentMode, savedCurrentMode; - - /* special handlings for DELL triple-head server */ - Bool IsDellServer; - - Bool VGAAccess; - - int MaxSurfaceWidth; - int MaxLines; - - Bool want_vblank_interrupts; - RADEONBIOSConnector BiosConnector[RADEON_MAX_BIOS_CONNECTOR]; - radeon_encoder_ptr encoders[RADEON_MAX_BIOS_CONNECTOR]; - RADEONBIOSInitTable BiosTable; - - /* save crtc state for console restore */ - Bool crtc_on; - Bool crtc2_on; - - Bool InternalTVOut; - -#if defined(__powerpc__) - RADEONMacModel MacModel; -#endif - RADEONExtTMDSChip ext_tmds_chip; - - atomBiosHandlePtr atomBIOS; - unsigned long FbFreeStart, FbFreeSize; - unsigned char* BIOSCopy; + DisplayModePtr currentMode; CreateScreenResourcesProcPtr CreateScreenResources; - /* if no devices are connected at server startup */ - Bool first_load_no_devices; - Bool IsSecondary; Bool IsPrimary; Bool r600_shadow_fb; void *fb_shadow; - /* some server chips have a hardcoded edid in the bios so that they work with KVMs */ - Bool get_hardcoded_edid_from_bios; - - int virtualX; - int virtualY; - - Bool r4xx_atom; - - /* pm */ - RADEONPowerManagement pm; - - /* igp info */ - float igp_sideport_mclk; - float igp_system_mclk; - float igp_ht_link_clk; - float igp_ht_link_width; - - int can_resize; void (*reemit_current2d)(ScrnInfoPtr pScrn, int op); // emit the current 2D state into the IB struct radeon_2d_state state_2d; - Bool kms_enabled; struct radeon_bo *front_bo; -#ifdef XF86DRM_MODE struct radeon_bo_manager *bufmgr; struct radeon_cs_manager *csm; struct radeon_cs *cs; @@ -1029,10 +502,7 @@ typedef struct { int r7xx_bank_op; struct radeon_surface_manager *surf_man; struct radeon_surface front_surface; -#else - /* fake bool */ - Bool cs; -#endif + /* Xv bicubic filtering */ struct radeon_bo *bicubic_bo; @@ -1045,185 +515,21 @@ typedef struct { Bool swapBuffersWait; } RADEONInfoRec, *RADEONInfoPtr; -#define RADEONWaitForFifo(pScrn, entries) \ -do { \ - if (info->accel_state->fifo_slots < entries) \ - RADEONWaitForFifoFunction(pScrn, entries); \ - info->accel_state->fifo_slots -= entries; \ -} while (0) - -/* legacy_crtc.c */ -extern void legacy_crtc_dpms(xf86CrtcPtr crtc, int mode); -extern void legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, - DisplayModePtr adjusted_mode, int x, int y); -extern void RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn, - RADEONSavePtr restore); -extern void RADEONRestoreCrtcRegisters(ScrnInfoPtr pScrn, - RADEONSavePtr restore); -extern void RADEONRestoreCrtc2Registers(ScrnInfoPtr pScrn, - RADEONSavePtr restore); -extern void RADEONRestorePLLRegisters(ScrnInfoPtr pScrn, - RADEONSavePtr restore); -extern void RADEONRestorePLL2Registers(ScrnInfoPtr pScrn, - RADEONSavePtr restore); -extern void RADEONSaveCommonRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); -extern void RADEONSaveCrtcRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); -extern void RADEONSaveCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save); -extern void RADEONSavePLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); -extern void RADEONSavePLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save); - -/* legacy_output.c */ -extern RADEONMonitorType legacy_dac_detect(xf86OutputPtr output); -extern void legacy_output_dpms(xf86OutputPtr output, int mode); -extern void legacy_output_mode_set(xf86OutputPtr output, DisplayModePtr mode, - DisplayModePtr adjusted_mode); -extern I2CDevPtr RADEONDVODeviceInit(I2CBusPtr b, I2CSlaveAddr addr); -extern Bool RADEONDVOReadByte(I2CDevPtr dvo, int addr, uint8_t *ch); -extern Bool RADEONDVOWriteByte(I2CDevPtr dvo, int addr, uint8_t ch); -extern void RADEONRestoreDACRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore); -extern void RADEONRestoreFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore); -extern void RADEONRestoreFP2Registers(ScrnInfoPtr pScrn, RADEONSavePtr restore); -extern void RADEONRestoreLVDSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore); -extern void RADEONRestoreRMXRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore); -extern void RADEONSaveDACRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); -extern void RADEONSaveFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); -extern void radeon_save_palette_on_demand(ScrnInfoPtr pScrn, int palID); - -extern void RADEONGetTVDacAdjInfo(ScrnInfoPtr pScrn, radeon_tvdac_ptr tvdac); -extern void RADEONGetTMDSInfoFromTable(ScrnInfoPtr pScrn, radeon_tmds_ptr tmds); -extern void RADEONGetTMDSInfo(ScrnInfoPtr pScrn, radeon_tmds_ptr tmds); -extern void RADEONGetExtTMDSInfo(ScrnInfoPtr pScrn, radeon_dvo_ptr dvo); -extern void RADEONGetLVDSInfo(ScrnInfoPtr pScrn, radeon_lvds_ptr lvds); - /* radeon_accel.c */ extern Bool RADEONAccelInit(ScreenPtr pScreen); -extern void RADEONEngineFlush(ScrnInfoPtr pScrn); extern void RADEONEngineInit(ScrnInfoPtr pScrn); -extern void RADEONEngineReset(ScrnInfoPtr pScrn); -extern void RADEONEngineRestore(ScrnInfoPtr pScrn); -extern uint8_t *RADEONHostDataBlit(ScrnInfoPtr pScrn, unsigned int cpp, - unsigned int w, uint32_t dstPitchOff, - uint32_t *bufPitch, int x, int *y, - unsigned int *h, unsigned int *hpass); -extern void RADEONHostDataBlitCopyPass(ScrnInfoPtr pScrn, - unsigned int bpp, - uint8_t *dst, uint8_t *src, - unsigned int hpass, - unsigned int dstPitch, - unsigned int srcPitch); extern void RADEONCopySwap(uint8_t *dst, uint8_t *src, unsigned int size, int swap); -extern void RADEONHostDataParams(ScrnInfoPtr pScrn, uint8_t *dst, - uint32_t pitch, int cpp, - uint32_t *dstPitchOffset, int *x, int *y); extern void RADEONInit3DEngine(ScrnInfoPtr pScrn); -extern void RADEONWaitForFifoFunction(ScrnInfoPtr pScrn, int entries); -#ifdef XF86DRI -extern drmBufPtr RADEONCPGetBuffer(ScrnInfoPtr pScrn); -extern void RADEONCPFlushIndirect(ScrnInfoPtr pScrn, int discard); -extern void RADEONCPReleaseIndirect(ScrnInfoPtr pScrn); -extern int RADEONCPStop(ScrnInfoPtr pScrn, RADEONInfoPtr info); -# ifdef USE_XAA -extern Bool RADEONSetupMemXAA_DRI(ScreenPtr pScreen); -# endif uint32_t radeonGetPixmapOffset(PixmapPtr pPix); -#endif extern int radeon_cs_space_remaining(ScrnInfoPtr pScrn); -#ifdef USE_XAA -/* radeon_accelfuncs.c */ -extern void RADEONAccelInitMMIO(ScreenPtr pScreen, XAAInfoRecPtr a); -extern Bool RADEONSetupMemXAA(ScreenPtr pScreen); -#endif - -/* radeon_bios.c */ -extern Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10); -extern Bool RADEONGetClockInfoFromBIOS(ScrnInfoPtr pScrn); -extern Bool RADEONGetConnectorInfoFromBIOS(ScrnInfoPtr pScrn); -extern Bool RADEONGetDAC2InfoFromBIOS(ScrnInfoPtr pScrn, radeon_tvdac_ptr tvdac); -extern Bool RADEONGetExtTMDSInfoFromBIOS (ScrnInfoPtr pScrn, radeon_dvo_ptr dvo); -extern xf86MonPtr RADEONGetHardCodedEDIDFromBIOS(xf86OutputPtr output); -extern Bool RADEONGetBIOSInitTableOffsets(ScrnInfoPtr pScrn); -extern Bool RADEONGetLVDSInfoFromBIOS(ScrnInfoPtr pScrn, radeon_lvds_ptr lvds); -extern Bool RADEONGetTMDSInfoFromBIOS(ScrnInfoPtr pScrn, radeon_tmds_ptr tmds); -extern Bool RADEONGetTVInfoFromBIOS(xf86OutputPtr output); -extern Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output); -extern Bool RADEONPostCardFromBIOSTables(ScrnInfoPtr pScrn); -extern Bool radeon_card_posted(ScrnInfoPtr pScrn); - /* radeon_commonfuncs.c */ -#ifdef XF86DRI -extern void RADEONWaitForIdleCP(ScrnInfoPtr pScrn); extern void RADEONWaitForVLineCP(ScrnInfoPtr pScrn, PixmapPtr pPix, xf86CrtcPtr crtc, int start, int stop); -#endif -extern void RADEONWaitForIdleMMIO(ScrnInfoPtr pScrn); -extern void RADEONWaitForVLineMMIO(ScrnInfoPtr pScrn, PixmapPtr pPix, - xf86CrtcPtr crtc, int start, int stop); - -/* radeon_crtc.c */ -extern void radeon_crtc_dpms(xf86CrtcPtr crtc, int mode); -extern void radeon_do_crtc_dpms(xf86CrtcPtr crtc, int mode); -extern void radeon_crtc_load_lut(xf86CrtcPtr crtc); -extern void radeon_crtc_modeset_ioctl(xf86CrtcPtr crtc, Bool post); -extern Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask); -extern void RADEONBlank(ScrnInfoPtr pScrn); -extern void RADEONComputePLL(xf86CrtcPtr crtc, - RADEONPLLPtr pll, unsigned long freq, - uint32_t *chosen_dot_clock_freq, - uint32_t *chosen_feedback_div, - uint32_t *chosen_frac_feedback_div, - uint32_t *chosen_reference_div, - uint32_t *chosen_post_div, int flags); -extern DisplayModePtr RADEONCrtcFindClosestMode(xf86CrtcPtr crtc, - DisplayModePtr pMode); -extern void RADEONUnblank(ScrnInfoPtr pScrn); -extern Bool RADEONSetTiling(ScrnInfoPtr pScrn); -extern void RADEONInitDispBandwidth(ScrnInfoPtr pScrn); - -/* radeon_cursor.c */ -extern Bool RADEONCursorInit(ScreenPtr pScreen); -extern void radeon_crtc_hide_cursor(xf86CrtcPtr crtc); -extern void radeon_crtc_load_cursor_argb(xf86CrtcPtr crtc, CARD32 *image); -extern void radeon_crtc_set_cursor_colors(xf86CrtcPtr crtc, int bg, int fg); -extern void radeon_crtc_set_cursor_position(xf86CrtcPtr crtc, int x, int y); -extern void radeon_crtc_show_cursor(xf86CrtcPtr crtc); - -#ifdef XF86DRI -/* radeon_dri.c */ -extern void RADEONDRIAllocatePCIGARTTable(ScreenPtr pScreen); -extern void RADEONDRICloseScreen(ScreenPtr pScreen); -extern Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen); -extern int RADEONDRIGetPciAperTableSize(ScrnInfoPtr pScrn); -extern Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn); -extern void RADEONDRIResume(ScreenPtr pScreen); -extern Bool RADEONDRIScreenInit(ScreenPtr pScreen); -extern int RADEONDRISetParam(ScrnInfoPtr pScrn, - unsigned int param, int64_t value); -extern Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on); -extern void RADEONDRIStop(ScreenPtr pScreen); -#endif + /* radeon_driver.c */ -extern void RADEONDoAdjustFrame(ScrnInfoPtr pScrn, int x, int y, Bool clone); -extern void RADEONChangeSurfaces(ScrnInfoPtr pScrn); extern RADEONEntPtr RADEONEntPriv(ScrnInfoPtr pScrn); -extern int RADEONMinBits(int val); -extern unsigned RADEONINMC(ScrnInfoPtr pScrn, int addr); -extern unsigned RADEONINPLL(ScrnInfoPtr pScrn, int addr); -extern unsigned RADEONINPCIE(ScrnInfoPtr pScrn, int addr); -extern unsigned R600INPCIE_PORT(ScrnInfoPtr pScrn, int addr); -extern void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, uint32_t data); -extern void RADEONOUTPLL(ScrnInfoPtr pScrn, int addr, uint32_t data); -extern void RADEONOUTPCIE(ScrnInfoPtr pScrn, int addr, uint32_t data); -extern void R600OUTPCIE_PORT(ScrnInfoPtr pScrn, int addr, uint32_t data); -extern void RADEONPllErrataAfterData(RADEONInfoPtr info); -extern void RADEONPllErrataAfterIndex(RADEONInfoPtr info); -extern void RADEONWaitForVerticalSync(ScrnInfoPtr pScrn); -extern void RADEONWaitForVerticalSync2(ScrnInfoPtr pScrn); -extern void RADEONInitMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save, - RADEONInfoPtr info); -extern void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, - RADEONSavePtr restore); extern Bool RADEONZaphodStringMatches(ScrnInfoPtr pScrn, const char *s, char *output_name); @@ -1232,87 +538,27 @@ void RADEONFreeRec(ScrnInfoPtr pScrn); Bool RADEONPreInitVisual(ScrnInfoPtr pScrn); Bool RADEONPreInitWeight(ScrnInfoPtr pScrn); -extern Bool RADEON_DP_I2CInit(ScrnInfoPtr pScrn, I2CBusPtr *bus_ptr, - char *name, xf86OutputPtr output); -extern void RADEON_DP_GetDPCD(xf86OutputPtr output); -extern int RADEON_DP_GetSinkType(xf86OutputPtr output); - -/* radeon_pm.c */ -extern void RADEONPMInit(ScrnInfoPtr pScrn); -extern void RADEONPMBlockHandler(ScrnInfoPtr pScrn); -extern void RADEONPMEnterVT(ScrnInfoPtr pScrn); -extern void RADEONPMLeaveVT(ScrnInfoPtr pScrn); -extern void RADEONPMFini(ScrnInfoPtr pScrn); - -#ifdef USE_EXA /* radeon_exa.c */ extern unsigned eg_tile_split(unsigned tile_split); -extern Bool RADEONSetupMemEXA(ScreenPtr pScreen); extern Bool radeon_transform_is_affine_or_scaled(PictTransformPtr t); /* radeon_exa_funcs.c */ extern void RADEONCopyCP(PixmapPtr pDst, int srcX, int srcY, int dstX, int dstY, int w, int h); -extern void RADEONCopyMMIO(PixmapPtr pDst, int srcX, int srcY, int dstX, - int dstY, int w, int h); extern Bool RADEONDrawInitCP(ScreenPtr pScreen); -extern Bool RADEONDrawInitMMIO(ScreenPtr pScreen); extern void RADEONDoPrepareCopyCP(ScrnInfoPtr pScrn, uint32_t src_pitch_offset, uint32_t dst_pitch_offset, uint32_t datatype, int rop, Pixel planemask); -extern void RADEONDoPrepareCopyMMIO(ScrnInfoPtr pScrn, - uint32_t src_pitch_offset, - uint32_t dst_pitch_offset, - uint32_t datatype, int rop, - Pixel planemask); extern Bool R600DrawInit(ScreenPtr pScreen); extern Bool R600LoadShaders(ScrnInfoPtr pScrn); -#ifdef XF86DRM_MODE extern Bool EVERGREENDrawInit(ScreenPtr pScreen); -#endif -#endif -#if defined(XF86DRI) && defined(USE_EXA) /* radeon_exa.c */ extern Bool RADEONGetDatatypeBpp(int bpp, uint32_t *type); extern Bool RADEONGetPixmapOffsetPitch(PixmapPtr pPix, uint32_t *pitch_offset); -extern unsigned long long RADEONTexOffsetStart(PixmapPtr pPix); -#endif - -/* radeon_modes.c */ -extern void RADEONSetPitch(ScrnInfoPtr pScrn); -extern DisplayModePtr RADEONProbeOutputModes(xf86OutputPtr output); - -/* radeon_output.c */ -extern RADEONI2CBusRec atom_setup_i2c_bus(int ddc_line); -extern RADEONI2CBusRec legacy_setup_i2c_bus(int ddc_line); -extern void RADEONGetPanelInfo(ScrnInfoPtr pScrn); -extern void RADEONInitConnector(xf86OutputPtr output); -extern void RADEONPrintPortMap(ScrnInfoPtr pScrn); -extern void RADEONSetOutputType(ScrnInfoPtr pScrn, - RADEONOutputPrivatePtr radeon_output); -extern Bool RADEONSetupConnectors(ScrnInfoPtr pScrn); -extern Bool RADEONI2CDoLock(xf86OutputPtr output, I2CBusPtr b, Bool lock_state); - -extern Bool radeon_dp_mode_fixup(xf86OutputPtr output, DisplayModePtr mode, DisplayModePtr adjusted_mode); - -/* radeon_tv.c */ -extern void RADEONSaveTVRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); -extern void RADEONAdjustCrtcRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save, - DisplayModePtr mode, xf86OutputPtr output); -extern void RADEONAdjustPLLRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save, - DisplayModePtr mode, xf86OutputPtr output); -extern void RADEONAdjustCrtc2RegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save, - DisplayModePtr mode, xf86OutputPtr output); -extern void RADEONAdjustPLL2RegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save, - DisplayModePtr mode, xf86OutputPtr output); -extern void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save, - DisplayModePtr mode, BOOL IsPrimary); -extern void RADEONRestoreTVRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore); -extern void RADEONUpdateHVPosition(xf86OutputPtr output, DisplayModePtr mode); /* radeon_video.c */ extern void RADEONInitVideo(ScreenPtr pScreen); @@ -1332,85 +578,16 @@ extern void radeon_legacy_free_memory(ScrnInfoPtr pScrn, void *mem_struct); -#ifdef XF86DRM_MODE extern void radeon_cs_flush_indirect(ScrnInfoPtr pScrn); extern void radeon_ddx_cs_start(ScrnInfoPtr pScrn, int num, const char *file, const char *func, int line); void radeon_kms_update_vram_limit(ScrnInfoPtr pScrn, int new_fb_size); struct radeon_surface *radeon_get_pixmap_surface(PixmapPtr pPix); -#endif struct radeon_bo *radeon_get_pixmap_bo(PixmapPtr pPix); void radeon_set_pixmap_bo(PixmapPtr pPix, struct radeon_bo *bo); uint32_t radeon_get_pixmap_tiling(PixmapPtr pPix); -#ifdef XF86DRI -# ifdef USE_XAA -/* radeon_accelfuncs.c */ -extern void RADEONAccelInitCP(ScreenPtr pScreen, XAAInfoRecPtr a); -# endif - -#define RADEONCP_START(pScrn, info) \ -do { \ - int _ret = drmCommandNone(info->dri->drmFD, DRM_RADEON_CP_START); \ - if (_ret) { \ - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ - "%s: CP start %d\n", __FUNCTION__, _ret); \ - } \ - info->cp->CPStarted = TRUE; \ -} while (0) - -#define RADEONCP_RELEASE(pScrn, info) \ -do { \ - if (info->cs) { \ - radeon_cs_flush_indirect(pScrn); \ - } else if (info->cp->CPInUse) { \ - RADEON_PURGE_CACHE(); \ - RADEON_WAIT_UNTIL_IDLE(); \ - RADEONCPReleaseIndirect(pScrn); \ - info->cp->CPInUse = FALSE; \ - } \ -} while (0) - -#define RADEONCP_STOP(pScrn, info) \ -do { \ - int _ret; \ - if (info->cp->CPStarted) { \ - _ret = RADEONCPStop(pScrn, info); \ - if (_ret) { \ - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ - "%s: CP stop %d\n", __FUNCTION__, _ret); \ - } \ - info->cp->CPStarted = FALSE; \ - } \ - if (info->ChipFamily < CHIP_FAMILY_R600) \ - RADEONEngineRestore(pScrn); \ - info->cp->CPRuns = FALSE; \ -} while (0) - -#define RADEONCP_RESET(pScrn, info) \ -do { \ - int _ret = drmCommandNone(info->dri->drmFD, DRM_RADEON_CP_RESET); \ - if (_ret) { \ - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ - "%s: CP reset %d\n", __FUNCTION__, _ret); \ - } \ -} while (0) - -#define RADEONCP_REFRESH(pScrn, info) \ -do { \ - if (!info->cp->CPInUse && !info->cs) { \ - if (info->cp->needCacheFlush) { \ - RADEON_PURGE_CACHE(); \ - RADEON_PURGE_ZCACHE(); \ - info->cp->needCacheFlush = FALSE; \ - } \ - RADEON_WAIT_UNTIL_IDLE(); \ - info->cp->CPInUse = TRUE; \ - } \ -} while (0) - - #define CP_PACKET0(reg, n) \ (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) #define CP_PACKET1(reg0, reg1) \ @@ -1423,58 +600,18 @@ do { \ #define RADEON_VERBOSE 0 -#define RING_LOCALS uint32_t *__head = NULL; int __expected; int __count = 0 +#define RING_LOCALS #define BEGIN_RING(n) do { \ if (RADEON_VERBOSE) { \ xf86DrvMsg(pScrn->scrnIndex, X_INFO, \ "BEGIN_RING(%d) in %s\n", (unsigned int)n, __FUNCTION__);\ } \ - if (info->cs) { radeon_ddx_cs_start(pScrn, n, __FILE__, __func__, __LINE__); } else { \ - if (++info->cp->dma_begin_count != 1) { \ - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ - "BEGIN_RING without end at %s:%d\n", \ - info->cp->dma_debug_func, info->cp->dma_debug_lineno); \ - info->cp->dma_begin_count = 1; \ - } \ - info->cp->dma_debug_func = __FILE__; \ - info->cp->dma_debug_lineno = __LINE__; \ - if (!info->cp->indirectBuffer) { \ - info->cp->indirectBuffer = RADEONCPGetBuffer(pScrn); \ - info->cp->indirectStart = 0; \ - } else if (info->cp->indirectBuffer->used + (n) * (int)sizeof(uint32_t) > \ - info->cp->indirectBuffer->total) { \ - RADEONCPFlushIndirect(pScrn, 1); \ - } \ - __expected = n; \ - __head = (pointer)((char *)info->cp->indirectBuffer->address + \ - info->cp->indirectBuffer->used); \ - __count = 0; \ - } \ + radeon_ddx_cs_start(pScrn, n, __FILE__, __func__, __LINE__); \ } while (0) #define ADVANCE_RING() do { \ - if (info->cs) radeon_cs_end(info->cs, __FILE__, __func__, __LINE__); else { \ - if (info->cp->dma_begin_count-- != 1) { \ - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ - "ADVANCE_RING without begin at %s:%d\n", \ - __FILE__, __LINE__); \ - info->cp->dma_begin_count = 0; \ - } \ - if (__count != __expected) { \ - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ - "ADVANCE_RING count != expected (%d vs %d) at %s:%d\n", \ - __count, __expected, __FILE__, __LINE__); \ - } \ - if (RADEON_VERBOSE) { \ - xf86DrvMsg(pScrn->scrnIndex, X_INFO, \ - "ADVANCE_RING() start: %d used: %d count: %d\n", \ - info->cp->indirectStart, \ - info->cp->indirectBuffer->used, \ - __count * (int)sizeof(uint32_t)); \ - } \ - info->cp->indirectBuffer->used += __count * (int)sizeof(uint32_t); \ - } \ + radeon_cs_end(info->cs, __FILE__, __func__, __LINE__); \ } while (0) #define OUT_RING(x) do { \ @@ -1482,8 +619,7 @@ do { \ xf86DrvMsg(pScrn->scrnIndex, X_INFO, \ " OUT_RING(0x%08x)\n", (unsigned int)(x)); \ } \ - if (info->cs) radeon_cs_write_dword(info->cs, (x)); else \ - __head[__count++] = (x); \ + radeon_cs_write_dword(info->cs, (x)); \ } while (0) #define OUT_RING_REG(reg, val) \ @@ -1505,10 +641,7 @@ do { \ if (RADEON_VERBOSE) \ xf86DrvMsg(pScrn->scrnIndex, X_INFO, \ "FLUSH_RING in %s\n", __FUNCTION__); \ - if (info->cs) \ - radeon_cs_flush_indirect(pScrn); \ - else if (info->cp->indirectBuffer) \ - RADEONCPFlushIndirect(pScrn, 0); \ + radeon_cs_flush_indirect(pScrn); \ } while (0) @@ -1580,15 +713,7 @@ do { \ } \ } while (0) -#endif /* XF86DRI */ - -#if defined(XF86DRI) && defined(USE_EXA) - -#ifdef XF86DRM_MODE #define CS_FULL(cs) ((cs)->cdw > 15 * 1024) -#else -#define CS_FULL(cs) FALSE -#endif #define RADEON_SWITCH_TO_2D() \ do { \ @@ -1598,17 +723,14 @@ do { \ flush = 1; \ break; \ case EXA_ENGINEMODE_3D: \ - flush = !info->cs || CS_FULL(info->cs); \ + flush = CS_FULL(info->cs); \ break; \ case EXA_ENGINEMODE_2D: \ - flush = info->cs && CS_FULL(info->cs); \ + flush = CS_FULL(info->cs); \ break; \ } \ if (flush) { \ - if (info->cs) \ - radeon_cs_flush_indirect(pScrn); \ - else if (info->directRenderingEnabled) \ - RADEONCPFlushIndirect(pScrn, 1); \ + radeon_cs_flush_indirect(pScrn); \ } \ info->accel_state->engineMode = EXA_ENGINEMODE_2D; \ } while (0); @@ -1621,49 +743,24 @@ do { \ flush = 1; \ break; \ case EXA_ENGINEMODE_2D: \ - flush = !info->cs || CS_FULL(info->cs); \ + flush = CS_FULL(info->cs); \ break; \ case EXA_ENGINEMODE_3D: \ - flush = info->cs && CS_FULL(info->cs); \ + flush = CS_FULL(info->cs); \ break; \ } \ if (flush) { \ - if (info->cs) \ - radeon_cs_flush_indirect(pScrn); \ - else if (info->directRenderingEnabled) \ - RADEONCPFlushIndirect(pScrn, 1); \ + radeon_cs_flush_indirect(pScrn); \ } \ if (!info->accel_state->XInited3D) \ RADEONInit3DEngine(pScrn); \ info->accel_state->engineMode = EXA_ENGINEMODE_3D; \ } while (0); -#else -#define RADEON_SWITCH_TO_2D() -#define RADEON_SWITCH_TO_3D() -#endif - -static __inline__ void RADEON_MARK_SYNC(RADEONInfoPtr info, ScrnInfoPtr pScrn) -{ -#ifdef USE_EXA - if (info->useEXA) - exaMarkSync(pScrn->pScreen); -#endif -#ifdef USE_XAA - if (!info->useEXA) - SET_SYNC_FLAG(info->accel_state->accel); -#endif -} static __inline__ void RADEON_SYNC(RADEONInfoPtr info, ScrnInfoPtr pScrn) { -#ifdef USE_EXA - if (info->useEXA && pScrn->pScreen) + if (pScrn->pScreen) exaWaitSync(pScrn->pScreen); -#endif -#ifdef USE_XAA - if (!info->useEXA && info->accel_state->accel) - info->accel_state->accel->Sync(pScrn); -#endif } static __inline__ void radeon_init_timeout(struct timeval *endtime, diff --git a/src/radeon_accel.c b/src/radeon_accel.c index 89673a77..c51b0e5e 100644 --- a/src/radeon_accel.c +++ b/src/radeon_accel.c @@ -83,10 +83,6 @@ #include "radeon_macros.h" #include "radeon_probe.h" #include "radeon_version.h" -#ifdef XF86DRI -#define _XF86DRI_SERVER_ -#include "radeon_drm.h" -#endif #include "ati_pciids_gen.h" @@ -96,354 +92,19 @@ /* X and server generic header files */ #include "xf86.h" -static void R600EngineReset(ScrnInfoPtr pScrn); - -#ifdef USE_XAA -static struct { - int rop; - int pattern; -} RADEON_ROP[] = { - { RADEON_ROP3_ZERO, RADEON_ROP3_ZERO }, /* GXclear */ - { RADEON_ROP3_DSa, RADEON_ROP3_DPa }, /* Gxand */ - { RADEON_ROP3_SDna, RADEON_ROP3_PDna }, /* GXandReverse */ - { RADEON_ROP3_S, RADEON_ROP3_P }, /* GXcopy */ - { RADEON_ROP3_DSna, RADEON_ROP3_DPna }, /* GXandInverted */ - { RADEON_ROP3_D, RADEON_ROP3_D }, /* GXnoop */ - { RADEON_ROP3_DSx, RADEON_ROP3_DPx }, /* GXxor */ - { RADEON_ROP3_DSo, RADEON_ROP3_DPo }, /* GXor */ - { RADEON_ROP3_DSon, RADEON_ROP3_DPon }, /* GXnor */ - { RADEON_ROP3_DSxn, RADEON_ROP3_PDxn }, /* GXequiv */ - { RADEON_ROP3_Dn, RADEON_ROP3_Dn }, /* GXinvert */ - { RADEON_ROP3_SDno, RADEON_ROP3_PDno }, /* GXorReverse */ - { RADEON_ROP3_Sn, RADEON_ROP3_Pn }, /* GXcopyInverted */ - { RADEON_ROP3_DSno, RADEON_ROP3_DPno }, /* GXorInverted */ - { RADEON_ROP3_DSan, RADEON_ROP3_DPan }, /* GXnand */ - { RADEON_ROP3_ONE, RADEON_ROP3_ONE } /* GXset */ -}; -#endif - -/* The FIFO has 64 slots. This routines waits until at least `entries' - * of these slots are empty. - */ -void RADEONWaitForFifoFunction(ScrnInfoPtr pScrn, int entries) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - int i; - - for (;;) { - for (i = 0; i < RADEON_TIMEOUT; i++) { - info->accel_state->fifo_slots = - INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK; - if (info->accel_state->fifo_slots >= entries) return; - } - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "FIFO timed out: %u entries, stat=0x%08x\n", - (unsigned int)INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK, - (unsigned int)INREG(RADEON_RBBM_STATUS)); - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "FIFO timed out, resetting engine...\n"); - RADEONEngineReset(pScrn); - RADEONEngineRestore(pScrn); -#ifdef XF86DRI - if (info->directRenderingEnabled) { - RADEONCP_RESET(pScrn, info); - RADEONCP_START(pScrn, info); - } -#endif - } -} - -void R600WaitForFifoFunction(ScrnInfoPtr pScrn, int entries) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - int i; - - for (;;) { - for (i = 0; i < RADEON_TIMEOUT; i++) { - if (info->ChipFamily >= CHIP_FAMILY_RV770) - info->accel_state->fifo_slots = - INREG(R600_GRBM_STATUS) & R700_CMDFIFO_AVAIL_MASK; - else - info->accel_state->fifo_slots = - INREG(R600_GRBM_STATUS) & R600_CMDFIFO_AVAIL_MASK; - if (info->accel_state->fifo_slots >= entries) return; - } - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "FIFO timed out: stat=0x%08x\n", - (unsigned int)INREG(R600_GRBM_STATUS)); - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "FIFO timed out, resetting engine...\n"); - R600EngineReset(pScrn); -#ifdef XF86DRI - if (info->directRenderingEnabled) { - RADEONCP_RESET(pScrn, info); - RADEONCP_START(pScrn, info); - } -#endif - } -} - -/* Flush all dirty data in the Pixel Cache to memory */ -void RADEONEngineFlush(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - int i; - - if (info->ChipFamily <= CHIP_FAMILY_RV280) { - OUTREGP(RADEON_RB3D_DSTCACHE_CTLSTAT, - RADEON_RB3D_DC_FLUSH_ALL, - ~RADEON_RB3D_DC_FLUSH_ALL); - for (i = 0; i < RADEON_TIMEOUT; i++) { - if (!(INREG(RADEON_RB3D_DSTCACHE_CTLSTAT) & RADEON_RB3D_DC_BUSY)) - break; - } - if (i == RADEON_TIMEOUT) { - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "DC flush timeout: %x\n", - (unsigned int)INREG(RADEON_RB3D_DSTCACHE_CTLSTAT)); - } - } else { - OUTREGP(R300_DSTCACHE_CTLSTAT, - R300_RB2D_DC_FLUSH_ALL, - ~R300_RB2D_DC_FLUSH_ALL); - for (i = 0; i < RADEON_TIMEOUT; i++) { - if (!(INREG(R300_DSTCACHE_CTLSTAT) & R300_RB2D_DC_BUSY)) - break; - } - if (i == RADEON_TIMEOUT) { - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "DC flush timeout: %x\n", - (unsigned int)INREG(R300_DSTCACHE_CTLSTAT)); - } - } -} - -/* Reset graphics card to known state */ -void RADEONEngineReset(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - uint32_t clock_cntl_index; - uint32_t mclk_cntl; - uint32_t rbbm_soft_reset; - uint32_t host_path_cntl; - - /* The following RBBM_SOFT_RESET sequence can help un-wedge - * an R300 after the command processor got stuck. - */ - rbbm_soft_reset = INREG(RADEON_RBBM_SOFT_RESET); - OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset | - RADEON_SOFT_RESET_CP | - RADEON_SOFT_RESET_HI | - RADEON_SOFT_RESET_SE | - RADEON_SOFT_RESET_RE | - RADEON_SOFT_RESET_PP | - RADEON_SOFT_RESET_E2 | - RADEON_SOFT_RESET_RB)); - INREG(RADEON_RBBM_SOFT_RESET); - OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & (uint32_t) - ~(RADEON_SOFT_RESET_CP | - RADEON_SOFT_RESET_HI | - RADEON_SOFT_RESET_SE | - RADEON_SOFT_RESET_RE | - RADEON_SOFT_RESET_PP | - RADEON_SOFT_RESET_E2 | - RADEON_SOFT_RESET_RB))); - INREG(RADEON_RBBM_SOFT_RESET); - OUTREG(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset); - INREG(RADEON_RBBM_SOFT_RESET); - - RADEONEngineFlush(pScrn); - - clock_cntl_index = INREG(RADEON_CLOCK_CNTL_INDEX); - RADEONPllErrataAfterIndex(info); - -#if 0 /* taken care of by new PM code */ - /* Some ASICs have bugs with dynamic-on feature, which are - * ASIC-version dependent, so we force all blocks on for now - */ - if (info->HasCRTC2) { - uint32_t tmp; - - tmp = INPLL(pScrn, RADEON_SCLK_CNTL); - OUTPLL(RADEON_SCLK_CNTL, ((tmp & ~RADEON_DYN_STOP_LAT_MASK) | - RADEON_CP_MAX_DYN_STOP_LAT | - RADEON_SCLK_FORCEON_MASK)); - - if (info->ChipFamily == CHIP_FAMILY_RV200) { - tmp = INPLL(pScrn, RADEON_SCLK_MORE_CNTL); - OUTPLL(RADEON_SCLK_MORE_CNTL, tmp | RADEON_SCLK_MORE_FORCEON); - } - } -#endif /* new PM code */ - - mclk_cntl = INPLL(pScrn, RADEON_MCLK_CNTL); - -#if 0 /* handled by new PM code */ - OUTPLL(RADEON_MCLK_CNTL, (mclk_cntl | - RADEON_FORCEON_MCLKA | - RADEON_FORCEON_MCLKB | - RADEON_FORCEON_YCLKA | - RADEON_FORCEON_YCLKB | - RADEON_FORCEON_MC | - RADEON_FORCEON_AIC)); -#endif /* new PM code */ - - /* Soft resetting HDP thru RBBM_SOFT_RESET register can cause some - * unexpected behaviour on some machines. Here we use - * RADEON_HOST_PATH_CNTL to reset it. - */ - host_path_cntl = INREG(RADEON_HOST_PATH_CNTL); - rbbm_soft_reset = INREG(RADEON_RBBM_SOFT_RESET); - - if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { - uint32_t tmp; - - OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset | - RADEON_SOFT_RESET_CP | - RADEON_SOFT_RESET_HI | - RADEON_SOFT_RESET_E2)); - INREG(RADEON_RBBM_SOFT_RESET); - OUTREG(RADEON_RBBM_SOFT_RESET, 0); - tmp = INREG(RADEON_RB3D_DSTCACHE_MODE); - OUTREG(RADEON_RB3D_DSTCACHE_MODE, tmp | (1 << 17)); /* FIXME */ - } else { - OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset | - RADEON_SOFT_RESET_CP | - RADEON_SOFT_RESET_SE | - RADEON_SOFT_RESET_RE | - RADEON_SOFT_RESET_PP | - RADEON_SOFT_RESET_E2 | - RADEON_SOFT_RESET_RB)); - INREG(RADEON_RBBM_SOFT_RESET); - OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & (uint32_t) - ~(RADEON_SOFT_RESET_CP | - RADEON_SOFT_RESET_SE | - RADEON_SOFT_RESET_RE | - RADEON_SOFT_RESET_PP | - RADEON_SOFT_RESET_E2 | - RADEON_SOFT_RESET_RB))); - INREG(RADEON_RBBM_SOFT_RESET); - } - - if (!IS_R300_VARIANT && !IS_AVIVO_VARIANT) - OUTREG(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset); - - OUTREG(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index); - RADEONPllErrataAfterIndex(info); - OUTPLL(pScrn, RADEON_MCLK_CNTL, mclk_cntl); -} - -/* Reset graphics card to known state */ -static void R600EngineReset(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - uint32_t cp_ptr, cp_me_cntl, cp_rb_cntl; - - cp_ptr = INREG(R600_CP_RB_WPTR); - - cp_me_cntl = INREG(R600_CP_ME_CNTL); - OUTREG(R600_CP_ME_CNTL, 0x10000000); - - OUTREG(R600_GRBM_SOFT_RESET, 0x7fff); - INREG(R600_GRBM_SOFT_RESET); - usleep (50); - OUTREG(R600_GRBM_SOFT_RESET, 0); - INREG(R600_GRBM_SOFT_RESET); - - OUTREG(R600_CP_RB_WPTR_DELAY, 0); - cp_rb_cntl = INREG(R600_CP_RB_CNTL); - OUTREG(R600_CP_RB_CNTL, 0x80000000); - - OUTREG(R600_CP_RB_RPTR_WR, cp_ptr); - OUTREG(R600_CP_RB_WPTR, cp_ptr); - OUTREG(R600_CP_RB_CNTL, cp_rb_cntl); - OUTREG(R600_CP_ME_CNTL, cp_me_cntl); - -} - -/* Restore the acceleration hardware to its previous state */ -void RADEONEngineRestore(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - if (info->cs) - return; - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "EngineRestore (%d/%d)\n", - info->CurrentLayout.pixel_code, - info->CurrentLayout.bitsPerPixel); - - /* Setup engine location. This shouldn't be necessary since we - * set them appropriately before any accel ops, but let's avoid - * random bogus DMA in case we inadvertently trigger the engine - * in the wrong place (happened). - */ - RADEONWaitForFifo(pScrn, 2); - OUTREG(RADEON_DST_PITCH_OFFSET, info->accel_state->dst_pitch_offset); - OUTREG(RADEON_SRC_PITCH_OFFSET, info->accel_state->dst_pitch_offset); - - RADEONWaitForFifo(pScrn, 1); -#if X_BYTE_ORDER == X_BIG_ENDIAN - OUTREGP(RADEON_DP_DATATYPE, - RADEON_HOST_BIG_ENDIAN_EN, - ~RADEON_HOST_BIG_ENDIAN_EN); -#else - OUTREGP(RADEON_DP_DATATYPE, 0, ~RADEON_HOST_BIG_ENDIAN_EN); -#endif - - /* Restore SURFACE_CNTL */ - OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl); - - RADEONWaitForFifo(pScrn, 1); - OUTREG(RADEON_DEFAULT_SC_BOTTOM_RIGHT, (RADEON_DEFAULT_SC_RIGHT_MAX - | RADEON_DEFAULT_SC_BOTTOM_MAX)); - RADEONWaitForFifo(pScrn, 1); - OUTREG(RADEON_DP_GUI_MASTER_CNTL, (info->accel_state->dp_gui_master_cntl - | RADEON_GMC_BRUSH_SOLID_COLOR - | RADEON_GMC_SRC_DATATYPE_COLOR)); - - RADEONWaitForFifo(pScrn, 5); - OUTREG(RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); - OUTREG(RADEON_DP_BRUSH_BKGD_CLR, 0x00000000); - OUTREG(RADEON_DP_SRC_FRGD_CLR, 0xffffffff); - OUTREG(RADEON_DP_SRC_BKGD_CLR, 0x00000000); - OUTREG(RADEON_DP_WRITE_MASK, 0xffffffff); - - RADEONWaitForIdleMMIO(pScrn); - - info->accel_state->XInited3D = FALSE; -} - static int RADEONDRMGetNumPipes(ScrnInfoPtr pScrn, int *num_pipes) { RADEONInfoPtr info = RADEONPTR(pScrn); - if (info->dri->pKernelDRMVersion->version_major < 2) { - drm_radeon_getparam_t np; - - memset(&np, 0, sizeof(np)); - np.param = RADEON_PARAM_NUM_GB_PIPES; - np.value = num_pipes; - return drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_GETPARAM, &np, sizeof(np)); - } else { - struct drm_radeon_info np2; - np2.value = (unsigned long)num_pipes; - np2.request = RADEON_INFO_NUM_GB_PIPES; - return drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_INFO, &np2, sizeof(np2)); - } + struct drm_radeon_info np2; + np2.value = (unsigned long)num_pipes; + np2.request = RADEON_INFO_NUM_GB_PIPES; + return drmCommandWriteRead(info->dri2.drm_fd, DRM_RADEON_INFO, &np2, sizeof(np2)); } /* Initialize the acceleration hardware */ void RADEONEngineInit(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; int datatype = 0; info->accel_state->num_gb_pipes = 0; @@ -452,7 +113,6 @@ void RADEONEngineInit(ScrnInfoPtr pScrn) info->CurrentLayout.pixel_code, info->CurrentLayout.bitsPerPixel); -#ifdef XF86DRI if (info->directRenderingEnabled && (IS_R300_3D || IS_R500_3D)) { int num_pipes; @@ -465,71 +125,6 @@ void RADEONEngineInit(ScrnInfoPtr pScrn) info->accel_state->num_gb_pipes = num_pipes; } } -#endif - - if (!info->cs) { - if ((info->ChipFamily == CHIP_FAMILY_RV410) || - (info->ChipFamily == CHIP_FAMILY_R420) || - (info->ChipFamily == CHIP_FAMILY_RS600) || - (info->ChipFamily == CHIP_FAMILY_RS690) || - (info->ChipFamily == CHIP_FAMILY_RS740) || - (info->ChipFamily == CHIP_FAMILY_RS400) || - (info->ChipFamily == CHIP_FAMILY_RS480) || - IS_R500_3D) { - if (info->accel_state->num_gb_pipes == 0) { - uint32_t gb_pipe_sel = INREG(R400_GB_PIPE_SELECT); - - info->accel_state->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1; - if (IS_R500_3D) - OUTPLL(pScrn, R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4)); - } - } else { - if (info->accel_state->num_gb_pipes == 0) { - if ((info->ChipFamily == CHIP_FAMILY_R300) || - (info->ChipFamily == CHIP_FAMILY_R350)) { - /* R3xx chips */ - info->accel_state->num_gb_pipes = 2; - } else { - /* RV3xx chips */ - info->accel_state->num_gb_pipes = 1; - } - } - } - - /* SE cards only have 1 quadpipe */ - if ((info->Chipset == PCI_CHIP_RV410_5E4C) || - (info->Chipset == PCI_CHIP_RV410_5E4F) || - (info->Chipset == PCI_CHIP_R300_AD) || - (info->Chipset == PCI_CHIP_R350_AH)) - info->accel_state->num_gb_pipes = 1; - - if (IS_R300_3D || IS_R500_3D) - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "num quad-pipes is %d\n", info->accel_state->num_gb_pipes); - - if (IS_R300_3D || IS_R500_3D) { - uint32_t gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); - - switch(info->accel_state->num_gb_pipes) { - case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break; - case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break; - case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break; - default: - case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break; - } - - OUTREG(R300_GB_TILE_CONFIG, gb_tile_config); - OUTREG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); - if (info->ChipFamily >= CHIP_FAMILY_R420) - OUTREG(R300_DST_PIPE_CONFIG, INREG(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG); - OUTREG(R300_RB2D_DSTCACHE_MODE, (INREG(R300_RB2D_DSTCACHE_MODE) | - R300_DC_AUTOFLUSH_ENABLE | - R300_DC_DC_DISABLE_IGNORE_PE)); - } else - OUTREG(RADEON_RB3D_CNTL, 0); - - RADEONEngineReset(pScrn); - } switch (info->CurrentLayout.pixel_code) { case 8: datatype = 2; break; @@ -550,402 +145,36 @@ void RADEONEngineInit(ScrnInfoPtr pScrn) | RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_DST_PITCH_OFFSET_CNTL); - RADEONEngineRestore(pScrn); } uint32_t radeonGetPixmapOffset(PixmapPtr pPix) { - ScrnInfoPtr pScrn = xf86ScreenToScrn(pPix->drawable.pScreen); - RADEONInfoPtr info = RADEONPTR(pScrn); - uint32_t offset = 0; - if (info->cs) - return 0; -#ifdef USE_EXA - if (info->useEXA) { - offset = exaGetPixmapOffset(pPix); - } else -#endif - { - offset = pPix->devPrivate.ptr - info->FB; - } - offset += info->fbLocation + pScrn->fbOffset; - return offset; + return 0; } int radeon_cs_space_remaining(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); -#ifdef XF86DRM_MODE - if (info->cs) - return (info->cs->ndw - info->cs->cdw); - else -#endif - return (info->cp->indirectBuffer->total - info->cp->indirectBuffer->used) / (int)sizeof(uint32_t); + return (info->cs->ndw - info->cs->cdw); } -#define ACCEL_MMIO -#define ACCEL_PREAMBLE() unsigned char *RADEONMMIO = info->MMIO -#define BEGIN_ACCEL(n) RADEONWaitForFifo(pScrn, (n)) -#define OUT_ACCEL_REG(reg, val) OUTREG(reg, val) -#define FINISH_ACCEL() - -#include "radeon_commonfuncs.c" -#if defined(RENDER) && defined(USE_XAA) -#include "radeon_render.c" -#endif -#include "radeon_accelfuncs.c" - -#undef ACCEL_MMIO -#undef ACCEL_PREAMBLE -#undef BEGIN_ACCEL -#undef OUT_ACCEL_REG -#undef FINISH_ACCEL - -#ifdef XF86DRI - -#define ACCEL_CP #define ACCEL_PREAMBLE() \ - RING_LOCALS; \ - RADEONCP_REFRESH(pScrn, info) + RING_LOCALS; #define BEGIN_ACCEL(n) BEGIN_RING(2*(n)) #define OUT_ACCEL_REG(reg, val) OUT_RING_REG(reg, val) #define FINISH_ACCEL() ADVANCE_RING() #include "radeon_commonfuncs.c" -#if defined(RENDER) && defined(USE_XAA) -#include "radeon_render.c" -#endif -#include "radeon_accelfuncs.c" -#undef ACCEL_CP #undef ACCEL_PREAMBLE #undef BEGIN_ACCEL #undef OUT_ACCEL_REG #undef FINISH_ACCEL -/* Stop the CP */ -int RADEONCPStop(ScrnInfoPtr pScrn, RADEONInfoPtr info) -{ - drm_radeon_cp_stop_t stop; - int ret, i; - - stop.flush = 1; - stop.idle = 1; - - ret = drmCommandWrite(info->dri->drmFD, DRM_RADEON_CP_STOP, &stop, - sizeof(drm_radeon_cp_stop_t)); - - if (ret == 0) { - return 0; - } else if (errno != EBUSY) { - return -errno; - } - - stop.flush = 0; - - i = 0; - do { - ret = drmCommandWrite(info->dri->drmFD, DRM_RADEON_CP_STOP, &stop, - sizeof(drm_radeon_cp_stop_t)); - } while (ret && errno == EBUSY && i++ < RADEON_IDLE_RETRY); - - if (ret == 0) { - return 0; - } else if (errno != EBUSY) { - return -errno; - } - - stop.idle = 0; - - if (drmCommandWrite(info->dri->drmFD, DRM_RADEON_CP_STOP, - &stop, sizeof(drm_radeon_cp_stop_t))) { - return -errno; - } else { - return 0; - } -} - #define RADEON_IB_RESERVE (16 * sizeof(uint32_t)) -/* Get an indirect buffer for the CP 2D acceleration commands */ -drmBufPtr RADEONCPGetBuffer(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - drmDMAReq dma; - drmBufPtr buf = NULL; - int indx = 0; - int size = 0; - int i = 0; - int ret; - -#if 0 - /* FIXME: pScrn->pScreen has not been initialized when this is first - * called from RADEONSelectBuffer via RADEONDRICPInit. We could use - * the screen index from pScrn, which is initialized, and then get - * the screen from screenInfo.screens[index], but that is a hack. - */ - dma.context = DRIGetContext(pScrn->pScreen); -#else - /* This is the X server's context */ - dma.context = 0x00000001; -#endif - - dma.send_count = 0; - dma.send_list = NULL; - dma.send_sizes = NULL; - dma.flags = 0; - dma.request_count = 1; - dma.request_size = RADEON_BUFFER_SIZE; - dma.request_list = &indx; - dma.request_sizes = &size; - dma.granted_count = 0; - - while (1) { - do { - ret = drmDMA(info->dri->drmFD, &dma); - if (ret && ret != -EBUSY) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "%s: CP GetBuffer %d\n", __FUNCTION__, ret); - } - } while ((ret == -EBUSY) && (i++ < RADEON_TIMEOUT)); - - if (ret == 0) { - buf = &info->dri->buffers->list[indx]; - buf->used = 0; - if (RADEON_VERBOSE) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - " GetBuffer returning %d %p\n", - buf->idx, buf->address); - } - return buf; - } - - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "GetBuffer timed out, resetting engine...\n"); - - if (info->ChipFamily < CHIP_FAMILY_R600) { - RADEONEngineReset(pScrn); - RADEONEngineRestore(pScrn); - } else - R600EngineReset(pScrn); - - /* Always restart the engine when doing CP 2D acceleration */ - RADEONCP_RESET(pScrn, info); - RADEONCP_START(pScrn, info); - } -} - -/* Flush the indirect buffer to the kernel for submission to the card */ -void RADEONCPFlushIndirect(ScrnInfoPtr pScrn, int discard) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - drmBufPtr buffer = info->cp->indirectBuffer; - int start = info->cp->indirectStart; - drm_radeon_indirect_t indirect; - - assert(!info->cs); - if (!buffer) return; - if (start == buffer->used && !discard) return; - - if (RADEON_VERBOSE) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Flushing buffer %d\n", - buffer->idx); - } - - if (info->ChipFamily >= CHIP_FAMILY_R600) { - if (buffer->used & 0x3c) { - RING_LOCALS; - - while (buffer->used & 0x3c) { - BEGIN_RING(1); - OUT_RING(CP_PACKET2()); /* fill up to multiple of 16 dwords */ - ADVANCE_RING(); - } - } - } - - indirect.idx = buffer->idx; - indirect.start = start; - indirect.end = buffer->used; - indirect.discard = discard; - - drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_INDIRECT, - &indirect, sizeof(drm_radeon_indirect_t)); - - if (discard) { - info->cp->indirectBuffer = RADEONCPGetBuffer(pScrn); - info->cp->indirectStart = 0; - } else { - /* Start on a double word boundary */ - info->cp->indirectStart = buffer->used = RADEON_ALIGN(buffer->used, 8); - if (RADEON_VERBOSE) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, " Starting at %d\n", - info->cp->indirectStart); - } - } -} - -/* Flush and release the indirect buffer */ -void RADEONCPReleaseIndirect(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - drmBufPtr buffer = info->cp->indirectBuffer; - int start = info->cp->indirectStart; - drm_radeon_indirect_t indirect; - - assert(!info->cs); - if (info->ChipFamily >= CHIP_FAMILY_R600) { - if (buffer && (buffer->used & 0x3c)) { - RING_LOCALS; - - while (buffer->used & 0x3c) { - BEGIN_RING(1); - OUT_RING(CP_PACKET2()); /* fill up to multiple of 16 dwords */ - ADVANCE_RING(); - } - } - } - - info->cp->indirectBuffer = NULL; - info->cp->indirectStart = 0; - - if (!buffer) return; - - if (RADEON_VERBOSE) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Releasing buffer %d\n", - buffer->idx); - } - - indirect.idx = buffer->idx; - indirect.start = start; - indirect.end = buffer->used; - indirect.discard = 1; - - drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_INDIRECT, - &indirect, sizeof(drm_radeon_indirect_t)); -} - -/** \brief Calculate HostDataBlit parameters from pointer and pitch - * - * This is a helper for the trivial HostDataBlit users that don't need to worry - * about tiling etc. - */ -void -RADEONHostDataParams(ScrnInfoPtr pScrn, uint8_t *dst, uint32_t pitch, int cpp, - uint32_t *dstPitchOff, int *x, int *y) -{ - RADEONInfoPtr info = RADEONPTR( pScrn ); - uint32_t dstOffs = dst - (uint8_t*)info->FB + info->fbLocation; - - *dstPitchOff = pitch << 16 | (dstOffs & ~RADEON_BUFFER_ALIGN) >> 10; - *y = ( dstOffs & RADEON_BUFFER_ALIGN ) / pitch; - *x = ( ( dstOffs & RADEON_BUFFER_ALIGN ) - ( *y * pitch ) ) / cpp; -} - -/* Set up a hostdata blit to transfer data from system memory to the - * framebuffer. Returns the address where the data can be written to and sets - * the dstPitch and hpass variables as required. - */ -uint8_t* -RADEONHostDataBlit( - ScrnInfoPtr pScrn, - unsigned int cpp, - unsigned int w, - uint32_t dstPitchOff, - uint32_t *bufPitch, - int x, - int *y, - unsigned int *h, - unsigned int *hpass -){ - RADEONInfoPtr info = RADEONPTR( pScrn ); - uint32_t format, dwords; - uint8_t *ret; - RING_LOCALS; - - if ( *h == 0 ) - { - return NULL; - } - - switch ( cpp ) - { - case 4: - format = RADEON_GMC_DST_32BPP; - *bufPitch = 4 * w; - break; - case 2: - format = RADEON_GMC_DST_16BPP; - *bufPitch = 2 * RADEON_ALIGN(w, 2); - break; - case 1: - format = RADEON_GMC_DST_8BPP_CI; - *bufPitch = RADEON_ALIGN(w, 4); - break; - default: - xf86DrvMsg( pScrn->scrnIndex, X_ERROR, - "%s: Unsupported cpp %d!\n", __func__, cpp ); - return NULL; - } - -#if X_BYTE_ORDER == X_BIG_ENDIAN - /* Swap doesn't work on R300 and later, it's handled during the - * copy to ind. buffer pass - */ - if (info->ChipFamily < CHIP_FAMILY_R300) { - BEGIN_RING(2); - if (cpp == 2) - OUT_RING_REG(RADEON_RBBM_GUICNTL, - RADEON_HOST_DATA_SWAP_HDW); - else if (cpp == 1) - OUT_RING_REG(RADEON_RBBM_GUICNTL, - RADEON_HOST_DATA_SWAP_32BIT); - else - OUT_RING_REG(RADEON_RBBM_GUICNTL, - RADEON_HOST_DATA_SWAP_NONE); - ADVANCE_RING(); - } -#endif - - /*RADEON_PURGE_CACHE(); - RADEON_WAIT_UNTIL_IDLE();*/ - - *hpass = min( *h, ( ( RADEON_BUFFER_SIZE - 10 * 4 ) / *bufPitch ) ); - dwords = *hpass * *bufPitch / 4; - - BEGIN_RING( dwords + 10 ); - OUT_RING( CP_PACKET3( RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT, dwords + 10 - 2 ) ); - OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL - | RADEON_GMC_DST_CLIPPING - | RADEON_GMC_BRUSH_NONE - | format - | RADEON_GMC_SRC_DATATYPE_COLOR - | RADEON_ROP3_S - | RADEON_DP_SRC_SOURCE_HOST_DATA - | RADEON_GMC_CLR_CMP_CNTL_DIS - | RADEON_GMC_WR_MSK_DIS ); - OUT_RING( dstPitchOff ); - OUT_RING( (*y << 16) | x ); - OUT_RING( ((*y + *hpass) << 16) | (x + w) ); - OUT_RING( 0xffffffff ); - OUT_RING( 0xffffffff ); - OUT_RING( *y << 16 | x ); - OUT_RING( *hpass << 16 | (*bufPitch / cpp) ); - OUT_RING( dwords ); - - ret = ( uint8_t* )&__head[__count]; - - __count += dwords; - ADVANCE_RING(); - - *y += *hpass; - *h -= *hpass; - - return ret; -} - void RADEONCopySwap(uint8_t *dst, uint8_t *src, unsigned int size, int swap) { switch(swap) { @@ -993,137 +222,26 @@ void RADEONCopySwap(uint8_t *dst, uint8_t *src, unsigned int size, int swap) memcpy(dst, src, size); } -/* Copies a single pass worth of data for a hostdata blit set up by - * RADEONHostDataBlit(). - */ -void -RADEONHostDataBlitCopyPass( - ScrnInfoPtr pScrn, - unsigned int cpp, - uint8_t *dst, - uint8_t *src, - unsigned int hpass, - unsigned int dstPitch, - unsigned int srcPitch -){ - -#if X_BYTE_ORDER == X_BIG_ENDIAN - RADEONInfoPtr info = RADEONPTR( pScrn ); -#endif - - /* RADEONHostDataBlitCopy can return NULL ! */ - if( (dst==NULL) || (src==NULL)) return; - - if ( dstPitch == srcPitch ) - { -#if X_BYTE_ORDER == X_BIG_ENDIAN - if (info->ChipFamily >= CHIP_FAMILY_R300) { - switch(cpp) { - case 1: - RADEONCopySwap(dst, src, hpass * dstPitch, - RADEON_HOST_DATA_SWAP_32BIT); - return; - case 2: - RADEONCopySwap(dst, src, hpass * dstPitch, - RADEON_HOST_DATA_SWAP_HDW); - return; - } - } -#endif - memcpy( dst, src, hpass * dstPitch ); - } - else - { - unsigned int minPitch = min( dstPitch, srcPitch ); - while ( hpass-- ) - { -#if X_BYTE_ORDER == X_BIG_ENDIAN - if (info->ChipFamily >= CHIP_FAMILY_R300) { - switch(cpp) { - case 1: - RADEONCopySwap(dst, src, minPitch, - RADEON_HOST_DATA_SWAP_32BIT); - goto next; - case 2: - RADEONCopySwap(dst, src, minPitch, - RADEON_HOST_DATA_SWAP_HDW); - goto next; - } - } -#endif - memcpy( dst, src, minPitch ); -#if X_BYTE_ORDER == X_BIG_ENDIAN - next: -#endif - src += srcPitch; - dst += dstPitch; - } - } -} -#endif Bool RADEONAccelInit(ScreenPtr pScreen) { ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); RADEONInfoPtr info = RADEONPTR(pScrn); -#ifdef USE_EXA - if (info->useEXA) { -# ifdef XF86DRI - if (info->directRenderingEnabled) { -#ifdef XF86DRM_MODE - if (info->ChipFamily >= CHIP_FAMILY_CEDAR) { - if (!EVERGREENDrawInit(pScreen)) - return FALSE; - } else -#endif - if (info->ChipFamily >= CHIP_FAMILY_R600) { + if (info->directRenderingEnabled) { + if (info->ChipFamily >= CHIP_FAMILY_CEDAR) { + if (!EVERGREENDrawInit(pScreen)) + return FALSE; + } else + if (info->ChipFamily >= CHIP_FAMILY_R600) { if (!R600DrawInit(pScreen)) return FALSE; } else { if (!RADEONDrawInitCP(pScreen)) return FALSE; } - } else -# endif /* XF86DRI */ - { - if (info->ChipFamily >= CHIP_FAMILY_R600) - return FALSE; - else { - if (!RADEONDrawInitMMIO(pScreen)) - return FALSE; - } - } } -#endif /* USE_EXA */ -#ifdef USE_XAA - if (!info->useEXA) { - XAAInfoRecPtr a; - - if (info->ChipFamily >= CHIP_FAMILY_R600) - return FALSE; - - if (!(a = info->accel_state->accel = XAACreateInfoRec())) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "XAACreateInfoRec Error\n"); - return FALSE; - } - -#ifdef XF86DRI - if (info->directRenderingEnabled) - RADEONAccelInitCP(pScreen, a); - else -#endif /* XF86DRI */ - RADEONAccelInitMMIO(pScreen, a); - - RADEONEngineInit(pScrn); - - if (!XAAInit(pScreen, a)) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "XAAInit Error\n"); - return FALSE; - } - } -#endif /* USE_XAA */ return TRUE; } @@ -1131,341 +249,9 @@ void RADEONInit3DEngine(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR (pScrn); -#ifdef XF86DRI if (info->directRenderingEnabled) { - drm_radeon_sarea_t *pSAREAPriv; - - if (!info->kms_enabled) { - pSAREAPriv = DRIGetSAREAPrivate(pScrn->pScreen); - pSAREAPriv->ctx_owner = DRIGetContext(pScrn->pScreen); - } RADEONInit3DEngineCP(pScrn); - } else -#endif - RADEONInit3DEngineMMIO(pScrn); - - info->accel_state->XInited3D = TRUE; -} - -#ifdef USE_XAA -#ifdef XF86DRI -Bool -RADEONSetupMemXAA_DRI(ScreenPtr pScreen) -{ - ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); - RADEONInfoPtr info = RADEONPTR(pScrn); - int cpp = info->CurrentLayout.pixel_bytes; - int depthCpp = (info->dri->depthBits - 8) / 4; - int width_bytes = pScrn->displayWidth * cpp; - int bufferSize; - int depthSize; - int l; - int scanlines; - int texsizerequest; - BoxRec MemBox; - FBAreaPtr fbarea; - - info->dri->frontOffset = 0; - info->dri->frontPitch = pScrn->displayWidth; - info->dri->backPitch = pScrn->displayWidth; - - /* make sure we use 16 line alignment for tiling (8 might be enough). - * Might need that for non-XF86DRI too? - */ - if (info->allowColorTiling) { - bufferSize = RADEON_ALIGN((RADEON_ALIGN(pScrn->virtualY, 16)) * width_bytes, - RADEON_GPU_PAGE_SIZE); - } else { - bufferSize = RADEON_ALIGN(pScrn->virtualY * width_bytes, - RADEON_GPU_PAGE_SIZE); - } - - /* Due to tiling, the Z buffer pitch must be a multiple of 32 pixels, - * which is always the case if color tiling is used due to color pitch - * but not necessarily otherwise, and its height a multiple of 16 lines. - */ - info->dri->depthPitch = RADEON_ALIGN(pScrn->displayWidth, 32); - depthSize = RADEON_ALIGN((RADEON_ALIGN(pScrn->virtualY, 16)) * info->dri->depthPitch - * depthCpp, RADEON_GPU_PAGE_SIZE); - - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Using %d MB GART aperture\n", info->dri->gartSize); - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Using %d MB for the ring buffer\n", info->dri->ringSize); - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Using %d MB for vertex/indirect buffers\n", info->dri->bufSize); - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Using %d MB for GART textures\n", info->dri->gartTexSize); - - /* Try for front, back, depth, and three framebuffers worth of - * pixmap cache. Should be enough for a fullscreen background - * image plus some leftovers. - * If the FBTexPercent option was used, try to achieve that percentage instead, - * but still have at least one pixmap buffer (get problems with xvideo/render - * otherwise probably), and never reserve more than 3 offscreen buffers as it's - * probably useless for XAA. - */ - if (info->dri->textureSize >= 0) { - texsizerequest = ((int)info->FbMapSize - 2 * bufferSize - depthSize - - 2 * width_bytes - 16384 - info->FbSecureSize) - /* first divide, then multiply or we'll get an overflow (been there...) */ - / 100 * info->dri->textureSize; - } - else { - texsizerequest = (int)info->FbMapSize / 2; - } - info->dri->textureSize = info->FbMapSize - info->FbSecureSize - 5 * bufferSize - depthSize; - - /* If that gives us less than the requested memory, let's - * be greedy and grab some more. Sorry, I care more about 3D - * performance than playing nicely, and you'll get around a full - * framebuffer's worth of pixmap cache anyway. - */ - if (info->dri->textureSize < texsizerequest) { - info->dri->textureSize = info->FbMapSize - 4 * bufferSize - depthSize; - } - if (info->dri->textureSize < texsizerequest) { - info->dri->textureSize = info->FbMapSize - 3 * bufferSize - depthSize; - } - - /* If there's still no space for textures, try without pixmap cache, but - * never use the reserved space, the space hw cursor and PCIGART table might - * use. - */ - if (info->dri->textureSize < 0) { - info->dri->textureSize = info->FbMapSize - 2 * bufferSize - depthSize - - 2 * width_bytes - 16384 - info->FbSecureSize; - } - - /* Check to see if there is more room available after the 8192nd - * scanline for textures - */ - /* FIXME: what's this good for? condition is pretty much impossible to meet */ - if ((int)info->FbMapSize - 8192*width_bytes - bufferSize - depthSize - > info->dri->textureSize) { - info->dri->textureSize = - info->FbMapSize - 8192*width_bytes - bufferSize - depthSize; - } - - /* If backbuffer is disabled, don't allocate memory for it */ - if (info->dri->noBackBuffer) { - info->dri->textureSize += bufferSize; - } - - /* RADEON_BUFFER_ALIGN is not sufficient for backbuffer! - At least for pageflip + color tiling, need to make sure it's 16 scanlines aligned, - otherwise the copy-from-front-to-back will fail (width_bytes * 16 will also guarantee - it's still 4kb aligned for tiled case). Need to round up offset (might get into cursor - area otherwise). - This might cause some space at the end of the video memory to be unused, since it - can't be used (?) due to that log_tex_granularity thing??? - Could use different copyscreentoscreen function for the pageflip copies - (which would use different src and dst offsets) to avoid this. */ - if (info->allowColorTiling && !info->dri->noBackBuffer) { - info->dri->textureSize = info->FbMapSize - ((info->FbMapSize - info->dri->textureSize + - width_bytes * 16 - 1) / (width_bytes * 16)) * (width_bytes * 16); - } - if (info->dri->textureSize > 0) { - l = RADEONMinBits((info->dri->textureSize-1) / RADEON_NR_TEX_REGIONS); - if (l < RADEON_LOG_TEX_GRANULARITY) - l = RADEON_LOG_TEX_GRANULARITY; - /* Round the texture size up to the nearest whole number of - * texture regions. Again, be greedy about this, don't - * round down. - */ - info->dri->log2TexGran = l; - info->dri->textureSize = (info->dri->textureSize >> l) << l; - } else { - info->dri->textureSize = 0; - } - - /* Set a minimum usable local texture heap size. This will fit - * two 256x256x32bpp textures. - */ - if (info->dri->textureSize < 512 * 1024) { - info->dri->textureOffset = 0; - info->dri->textureSize = 0; } - - if (info->allowColorTiling && !info->dri->noBackBuffer) { - info->dri->textureOffset = ((info->FbMapSize - info->dri->textureSize) / - (width_bytes * 16)) * (width_bytes * 16); - } - else { - /* Reserve space for textures */ - info->dri->textureOffset = RADEON_ALIGN(info->FbMapSize - info->dri->textureSize, - RADEON_GPU_PAGE_SIZE); - } - - /* Reserve space for the shared depth - * buffer. - */ - info->dri->depthOffset = RADEON_ALIGN(info->dri->textureOffset - depthSize, - RADEON_GPU_PAGE_SIZE); - - /* Reserve space for the shared back buffer */ - if (info->dri->noBackBuffer) { - info->dri->backOffset = info->dri->depthOffset; - } else { - info->dri->backOffset = RADEON_ALIGN(info->dri->depthOffset - bufferSize, - RADEON_GPU_PAGE_SIZE); - } - - info->dri->backY = info->dri->backOffset / width_bytes; - info->dri->backX = (info->dri->backOffset - (info->dri->backY * width_bytes)) / cpp; - - scanlines = (info->FbMapSize-info->FbSecureSize) / width_bytes; - if (scanlines > 8191) - scanlines = 8191; - - MemBox.x1 = 0; - MemBox.y1 = 0; - MemBox.x2 = pScrn->displayWidth; - MemBox.y2 = scanlines; - - if (!xf86InitFBManager(pScreen, &MemBox)) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Memory manager initialization to " - "(%d,%d) (%d,%d) failed\n", - MemBox.x1, MemBox.y1, MemBox.x2, MemBox.y2); - return FALSE; - } else { - int width, height; - - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Memory manager initialized to (%d,%d) (%d,%d)\n", - MemBox.x1, MemBox.y1, MemBox.x2, MemBox.y2); - /* why oh why can't we just request modes which are guaranteed to be 16 lines - aligned... sigh */ - if ((fbarea = xf86AllocateOffscreenArea(pScreen, - pScrn->displayWidth, - info->allowColorTiling ? - (RADEON_ALIGN(pScrn->virtualY, 16)) - - pScrn->virtualY + 2 : 2, - 0, NULL, NULL, - NULL))) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Reserved area from (%d,%d) to (%d,%d)\n", - fbarea->box.x1, fbarea->box.y1, - fbarea->box.x2, fbarea->box.y2); - } else { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unable to reserve area\n"); - } - - RADEONDRIAllocatePCIGARTTable(pScreen); - - if (xf86QueryLargestOffscreenArea(pScreen, &width, - &height, 0, 0, 0)) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Largest offscreen area available: %d x %d\n", - width, height); - - /* Lines in offscreen area needed for depth buffer and - * textures - */ - info->dri->depthTexLines = (scanlines - - info->dri->depthOffset / width_bytes); - info->dri->backLines = (scanlines - - info->dri->backOffset / width_bytes - - info->dri->depthTexLines); - info->dri->backArea = NULL; - } else { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Unable to determine largest offscreen area " - "available\n"); - return FALSE; - } - } - - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Will use front buffer at offset 0x%x\n", - info->dri->frontOffset); - - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Will use back buffer at offset 0x%x\n", - info->dri->backOffset); - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Will use depth buffer at offset 0x%x\n", - info->dri->depthOffset); - if (info->cardType==CARD_PCIE) - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Will use %d kb for PCI GART table at offset 0x%x\n", - info->dri->pciGartSize/1024, (unsigned)info->dri->pciGartOffset); - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Will use %d kb for textures at offset 0x%x\n", - info->dri->textureSize/1024, info->dri->textureOffset); - - info->dri->frontPitchOffset = (((info->dri->frontPitch * cpp / 64) << 22) | - ((info->dri->frontOffset + info->fbLocation) >> 10)); - - info->dri->backPitchOffset = (((info->dri->backPitch * cpp / 64) << 22) | - ((info->dri->backOffset + info->fbLocation) >> 10)); - - info->dri->depthPitchOffset = (((info->dri->depthPitch * depthCpp / 64) << 22) | - ((info->dri->depthOffset + info->fbLocation) >> 10)); - return TRUE; + info->accel_state->XInited3D = TRUE; } -#endif /* XF86DRI */ - -Bool -RADEONSetupMemXAA(ScreenPtr pScreen) -{ - ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); - RADEONInfoPtr info = RADEONPTR(pScrn); - BoxRec MemBox; - int y2; - - int width_bytes = pScrn->displayWidth * info->CurrentLayout.pixel_bytes; - - MemBox.x1 = 0; - MemBox.y1 = 0; - MemBox.x2 = pScrn->displayWidth; - y2 = info->FbMapSize / width_bytes; - if (y2 >= 32768) - y2 = 32767; /* because MemBox.y2 is signed short */ - MemBox.y2 = y2; - - /* The acceleration engine uses 14 bit - * signed coordinates, so we can't have any - * drawable caches beyond this region. - */ - if (MemBox.y2 > 8191) - MemBox.y2 = 8191; - - if (!xf86InitFBManager(pScreen, &MemBox)) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Memory manager initialization to " - "(%d,%d) (%d,%d) failed\n", - MemBox.x1, MemBox.y1, MemBox.x2, MemBox.y2); - return FALSE; - } else { - int width, height; - FBAreaPtr fbarea; - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Memory manager initialized to (%d,%d) (%d,%d)\n", - MemBox.x1, MemBox.y1, MemBox.x2, MemBox.y2); - if ((fbarea = xf86AllocateOffscreenArea(pScreen, - pScrn->displayWidth, - info->allowColorTiling ? - (RADEON_ALIGN(pScrn->virtualY, 16)) - - pScrn->virtualY + 2 : 2, - 0, NULL, NULL, - NULL))) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Reserved area from (%d,%d) to (%d,%d)\n", - fbarea->box.x1, fbarea->box.y1, - fbarea->box.x2, fbarea->box.y2); - } else { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unable to reserve area\n"); - } - if (xf86QueryLargestOffscreenArea(pScreen, &width, &height, - 0, 0, 0)) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Largest offscreen area available: %d x %d\n", - width, height); - } - return TRUE; - } -} -#endif /* USE_XAA */ diff --git a/src/radeon_accelfuncs.c b/src/radeon_accelfuncs.c deleted file mode 100644 index fe892add..00000000 --- a/src/radeon_accelfuncs.c +++ /dev/null @@ -1,1385 +0,0 @@ -/* - * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and - * VA Linux Systems Inc., Fremont, California. - * - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation on the rights to use, copy, modify, merge, - * publish, distribute, sublicense, and/or sell copies of the Software, - * and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR - * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -/* - * Authors: - * Kevin E. Martin <martin@xfree86.org> - * Rickard E. Faith <faith@valinux.com> - * Alan Hourihane <alanh@fairlite.demon.co.uk> - * Michel Dänzer <michel@daenzer.net> - * - * Credits: - * - * Thanks to Ani Joshi <ajoshi@shell.unixbox.com> for providing source - * code to his Radeon driver. Portions of this file are based on the - * initialization code for that driver. - * - * References: - * - * !!!! FIXME !!!! - * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical - * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April - * 1999. - * - * RAGE 128 Software Development Manual (Technical Reference Manual P/N - * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999. - * - * Notes on unimplemented XAA optimizations: - * - * SetClipping: This has been removed as XAA expects 16bit registers - * for full clipping. - * TwoPointLine: The Radeon supports this. Not Bresenham. - * DashedLine with non-power-of-two pattern length: Apparently, there is - * no way to set the length of the pattern -- it is always - * assumed to be 8 or 32 (or 1024?). - * ScreenToScreenColorExpandFill: See p. 4-17 of the Technical Reference - * Manual where it states that monochrome expansion of frame - * buffer data is not supported. - * CPUToScreenColorExpandFill, direct: The implementation here uses a hybrid - * direct/indirect method. If we had more data registers, - * then we could do better. If XAA supported a trigger write - * address, the code would be simpler. - * Color8x8PatternFill: Apparently, an 8x8 color brush cannot take an 8x8 - * pattern from frame buffer memory. - * ImageWrites: Same as CPUToScreenColorExpandFill - * - */ - -#if defined(ACCEL_MMIO) && defined(ACCEL_CP) -#error Cannot define both MMIO and CP acceleration! -#endif - -#if !defined(UNIXCPP) || defined(ANSICPP) -#define FUNC_NAME_CAT(prefix,suffix) prefix##suffix -#else -#define FUNC_NAME_CAT(prefix,suffix) prefix/**/suffix -#endif - -#ifdef ACCEL_MMIO -#define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,MMIO) -#else -#ifdef ACCEL_CP -#define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,CP) -#else -#error No accel type defined! -#endif -#endif - -#ifdef USE_XAA - -/* This callback is required for multiheader cards using XAA */ -static void -FUNC_NAME(RADEONRestoreAccelState)(ScrnInfoPtr pScrn) -{ - /*RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO;*/ - -#ifdef ACCEL_MMIO - -/* OUTREG(RADEON_DEFAULT_OFFSET, info->dst_pitch_offset);*/ - /* FIXME: May need to restore other things, like BKGD_CLK FG_CLK... */ - - RADEONWaitForIdleMMIO(pScrn); - -#else /* ACCEL_CP */ - -/* RADEONWaitForFifo(pScrn, 1); - OUTREG(RADEON_DEFAULT_OFFSET, info->frontPitchOffset);*/ - - RADEONWaitForIdleMMIO(pScrn); - -#if 0 - /* Not working yet */ - RADEONMMIO_TO_CP(pScrn, info); -#endif - - /* FIXME: May need to restore other things, like BKGD_CLK FG_CLK... */ -#endif -} - -/* Setup for XAA SolidFill */ -static void -FUNC_NAME(RADEONSetupForSolidFill)(ScrnInfoPtr pScrn, - int color, - int rop, - unsigned int planemask) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - ACCEL_PREAMBLE(); - - /* Save for later clipping */ - info->accel_state->dp_gui_master_cntl_clip = (info->accel_state->dp_gui_master_cntl - | RADEON_GMC_BRUSH_SOLID_COLOR - | RADEON_GMC_SRC_DATATYPE_COLOR - | RADEON_ROP[rop].pattern); - - BEGIN_ACCEL(4); - - OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, info->accel_state->dp_gui_master_cntl_clip); - OUT_ACCEL_REG(RADEON_DP_BRUSH_FRGD_CLR, color); - OUT_ACCEL_REG(RADEON_DP_WRITE_MASK, planemask); - OUT_ACCEL_REG(RADEON_DP_CNTL, (RADEON_DST_X_LEFT_TO_RIGHT - | RADEON_DST_Y_TOP_TO_BOTTOM)); - - FINISH_ACCEL(); - BEGIN_ACCEL(2); - OUT_ACCEL_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); - OUT_ACCEL_REG(RADEON_WAIT_UNTIL, - RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); - FINISH_ACCEL(); -} - -/* Subsequent XAA SolidFillRect - * - * Tests: xtest CH06/fllrctngl, xterm - */ -static void -FUNC_NAME(RADEONSubsequentSolidFillRect)(ScrnInfoPtr pScrn, - int x, int y, - int w, int h) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - ACCEL_PREAMBLE(); - - BEGIN_ACCEL(3); - - OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->accel_state->dst_pitch_offset | - ((info->tilingEnabled && (y <= pScrn->virtualY)) ? RADEON_DST_TILE_MACRO : 0)); - OUT_ACCEL_REG(RADEON_DST_Y_X, (y << 16) | x); - OUT_ACCEL_REG(RADEON_DST_WIDTH_HEIGHT, (w << 16) | h); - - FINISH_ACCEL(); -} - -/* Setup for XAA solid lines */ -static void -FUNC_NAME(RADEONSetupForSolidLine)(ScrnInfoPtr pScrn, - int color, - int rop, - unsigned int planemask) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - ACCEL_PREAMBLE(); - - /* Save for later clipping */ - info->accel_state->dp_gui_master_cntl_clip = (info->accel_state->dp_gui_master_cntl - | RADEON_GMC_BRUSH_SOLID_COLOR - | RADEON_GMC_SRC_DATATYPE_COLOR - | RADEON_ROP[rop].pattern); - - if (info->ChipFamily >= CHIP_FAMILY_RV200) { - BEGIN_ACCEL(1); - OUT_ACCEL_REG(RADEON_DST_LINE_PATCOUNT, - 0x55 << RADEON_BRES_CNTL_SHIFT); - FINISH_ACCEL(); - } - - BEGIN_ACCEL(3); - - OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, info->accel_state->dp_gui_master_cntl_clip); - OUT_ACCEL_REG(RADEON_DP_BRUSH_FRGD_CLR, color); - OUT_ACCEL_REG(RADEON_DP_WRITE_MASK, planemask); - - FINISH_ACCEL(); - BEGIN_ACCEL(2); - OUT_ACCEL_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); - OUT_ACCEL_REG(RADEON_WAIT_UNTIL, - RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); - FINISH_ACCEL(); -} - -/* Subsequent XAA solid horizontal and vertical lines */ -static void -FUNC_NAME(RADEONSubsequentSolidHorVertLine)(ScrnInfoPtr pScrn, - int x, int y, - int len, - int dir) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - int w = 1; - int h = 1; - ACCEL_PREAMBLE(); - - if (dir == DEGREES_0) w = len; - else h = len; - - BEGIN_ACCEL(4); - - OUT_ACCEL_REG(RADEON_DP_CNTL, (RADEON_DST_X_LEFT_TO_RIGHT - | RADEON_DST_Y_TOP_TO_BOTTOM)); - OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->accel_state->dst_pitch_offset | - ((info->tilingEnabled && (y <= pScrn->virtualY)) ? RADEON_DST_TILE_MACRO : 0)); - OUT_ACCEL_REG(RADEON_DST_Y_X, (y << 16) | x); - OUT_ACCEL_REG(RADEON_DST_WIDTH_HEIGHT, (w << 16) | h); - - FINISH_ACCEL(); -} - -/* Subsequent XAA solid TwoPointLine line - * - * Tests: xtest CH06/drwln, ico, Mark Vojkovich's linetest program - * - * [See http://www.xfree86.org/devel/archives/devel/1999-Jun/0102.shtml for - * Mark Vojkovich's linetest program, posted 2Jun99 to devel@xfree86.org.] - */ -static void -FUNC_NAME(RADEONSubsequentSolidTwoPointLine)(ScrnInfoPtr pScrn, - int xa, int ya, - int xb, int yb, - int flags) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - ACCEL_PREAMBLE(); - - /* TODO: Check bounds -- RADEON only has 14 bits */ - - if (!(flags & OMIT_LAST)) - FUNC_NAME(RADEONSubsequentSolidHorVertLine)(pScrn, - xb, yb, 1, - DEGREES_0); - - BEGIN_ACCEL(3); - - OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->accel_state->dst_pitch_offset | - ((info->tilingEnabled && (ya <= pScrn->virtualY)) ? RADEON_DST_TILE_MACRO : 0)); - OUT_ACCEL_REG(RADEON_DST_LINE_START, (ya << 16) | xa); - OUT_ACCEL_REG(RADEON_DST_LINE_END, (yb << 16) | xb); - - FINISH_ACCEL(); -} - -/* Setup for XAA dashed lines - * - * Tests: xtest CH05/stdshs, XFree86/drwln - * - * NOTE: Since we can only accelerate lines with power-of-2 patterns of - * length <= 32 - */ -static void -FUNC_NAME(RADEONSetupForDashedLine)(ScrnInfoPtr pScrn, - int fg, - int bg, - int rop, - unsigned int planemask, - int length, - unsigned char *pattern) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - uint32_t pat = *(uint32_t *)(pointer)pattern; - ACCEL_PREAMBLE(); - - /* Save for determining whether or not to draw last pixel */ - info->accel_state->dashLen = length; - info->accel_state->dashPattern = pat; - -#if X_BYTE_ORDER == X_BIG_ENDIAN -# define PAT_SHIFT(pat, shift) (pat >> shift) -#else -# define PAT_SHIFT(pat, shift) (pat << shift) -#endif - - switch (length) { - case 2: pat |= PAT_SHIFT(pat, 2); /* fall through */ - case 4: pat |= PAT_SHIFT(pat, 4); /* fall through */ - case 8: pat |= PAT_SHIFT(pat, 8); /* fall through */ - case 16: pat |= PAT_SHIFT(pat, 16); - } - - /* Save for later clipping */ - info->accel_state->dp_gui_master_cntl_clip = (info->accel_state->dp_gui_master_cntl - | (bg == -1 - ? RADEON_GMC_BRUSH_32x1_MONO_FG_LA - : RADEON_GMC_BRUSH_32x1_MONO_FG_BG) - | RADEON_ROP[rop].pattern - | RADEON_GMC_BYTE_LSB_TO_MSB); - info->accel_state->dash_fg = fg; - info->accel_state->dash_bg = bg; - - BEGIN_ACCEL((bg == -1) ? 4 : 5); - - OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, info->accel_state->dp_gui_master_cntl_clip); - OUT_ACCEL_REG(RADEON_DP_WRITE_MASK, planemask); - OUT_ACCEL_REG(RADEON_DP_BRUSH_FRGD_CLR, fg); - if (bg != -1) - OUT_ACCEL_REG(RADEON_DP_BRUSH_BKGD_CLR, bg); - OUT_ACCEL_REG(RADEON_BRUSH_DATA0, pat); - - FINISH_ACCEL(); - BEGIN_ACCEL(2); - OUT_ACCEL_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); - OUT_ACCEL_REG(RADEON_WAIT_UNTIL, - RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); - FINISH_ACCEL(); -} - -/* Helper function to draw last point for dashed lines */ -static void -FUNC_NAME(RADEONDashedLastPel)(ScrnInfoPtr pScrn, - int x, int y, - int fg) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - uint32_t dp_gui_master_cntl = info->accel_state->dp_gui_master_cntl_clip; - ACCEL_PREAMBLE(); - - dp_gui_master_cntl &= ~RADEON_GMC_BRUSH_DATATYPE_MASK; - dp_gui_master_cntl |= RADEON_GMC_BRUSH_SOLID_COLOR; - - dp_gui_master_cntl &= ~RADEON_GMC_SRC_DATATYPE_MASK; - dp_gui_master_cntl |= RADEON_GMC_SRC_DATATYPE_COLOR; - - BEGIN_ACCEL(8); - - OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, dp_gui_master_cntl); - OUT_ACCEL_REG(RADEON_DP_CNTL, (RADEON_DST_X_LEFT_TO_RIGHT - | RADEON_DST_Y_TOP_TO_BOTTOM)); - OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->accel_state->dst_pitch_offset | - ((info->tilingEnabled && (y <= pScrn->virtualY)) ? RADEON_DST_TILE_MACRO : 0)); - OUT_ACCEL_REG(RADEON_DP_BRUSH_FRGD_CLR, fg); - OUT_ACCEL_REG(RADEON_DST_Y_X, (y << 16) | x); - OUT_ACCEL_REG(RADEON_DST_WIDTH_HEIGHT, (1 << 16) | 1); - - /* Restore old values */ - OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, info->accel_state->dp_gui_master_cntl_clip); - OUT_ACCEL_REG(RADEON_DP_BRUSH_FRGD_CLR, info->accel_state->dash_fg); - - FINISH_ACCEL(); - BEGIN_ACCEL(2); - OUT_ACCEL_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); - OUT_ACCEL_REG(RADEON_WAIT_UNTIL, - RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); - FINISH_ACCEL(); -} - -/* Subsequent XAA dashed line */ -static void -FUNC_NAME(RADEONSubsequentDashedTwoPointLine)(ScrnInfoPtr pScrn, - int xa, int ya, - int xb, int yb, - int flags, - int phase) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - ACCEL_PREAMBLE(); - - /* TODO: Check bounds -- RADEON only has 14 bits */ - - if (!(flags & OMIT_LAST)) { - int deltax = abs(xa - xb); - int deltay = abs(ya - yb); - int shift; - - if (deltax > deltay) shift = deltax; - else shift = deltay; - - shift += phase; - shift %= info->accel_state->dashLen; - - if ((info->accel_state->dashPattern >> shift) & 1) - FUNC_NAME(RADEONDashedLastPel)(pScrn, xb, yb, info->accel_state->dash_fg); - else if (info->accel_state->dash_bg != -1) - FUNC_NAME(RADEONDashedLastPel)(pScrn, xb, yb, info->accel_state->dash_bg); - } - - BEGIN_ACCEL(4); - - OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->accel_state->dst_pitch_offset | - ((info->tilingEnabled && (ya <= pScrn->virtualY)) ? RADEON_DST_TILE_MACRO : 0)); - OUT_ACCEL_REG(RADEON_DST_LINE_START, (ya << 16) | xa); - OUT_ACCEL_REG(RADEON_DST_LINE_PATCOUNT, phase); - OUT_ACCEL_REG(RADEON_DST_LINE_END, (yb << 16) | xb); - - FINISH_ACCEL(); -} - -/* Set up for transparency - * - * Mmmm, Seems as though the transparency compare is opposite to r128. - * It should only draw when source != trans_color, this is the opposite - * of that. - */ -static void -FUNC_NAME(RADEONSetTransparency)(ScrnInfoPtr pScrn, - int trans_color) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - - if ((trans_color != -1) || (info->accel_state->XAAForceTransBlit == TRUE)) { - ACCEL_PREAMBLE(); - - BEGIN_ACCEL(3); - - OUT_ACCEL_REG(RADEON_CLR_CMP_CLR_SRC, trans_color); - OUT_ACCEL_REG(RADEON_CLR_CMP_MASK, RADEON_CLR_CMP_MSK); - OUT_ACCEL_REG(RADEON_CLR_CMP_CNTL, (RADEON_SRC_CMP_EQ_COLOR - | RADEON_CLR_CMP_SRC_SOURCE)); - - FINISH_ACCEL(); - } -} - -/* Setup for XAA screen-to-screen copy - * - * Tests: xtest CH06/fllrctngl (also tests transparency) - */ -static void -FUNC_NAME(RADEONSetupForScreenToScreenCopy)(ScrnInfoPtr pScrn, - int xdir, int ydir, - int rop, - unsigned int planemask, - int trans_color) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - ACCEL_PREAMBLE(); - - info->accel_state->xdir = xdir; - info->accel_state->ydir = ydir; - - /* Save for later clipping */ - info->accel_state->dp_gui_master_cntl_clip = (info->accel_state->dp_gui_master_cntl - | RADEON_GMC_BRUSH_NONE - | RADEON_GMC_SRC_DATATYPE_COLOR - | RADEON_ROP[rop].rop - | RADEON_DP_SRC_SOURCE_MEMORY - | RADEON_GMC_SRC_PITCH_OFFSET_CNTL); - - BEGIN_ACCEL(3); - - OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, info->accel_state->dp_gui_master_cntl_clip); - OUT_ACCEL_REG(RADEON_DP_WRITE_MASK, planemask); - OUT_ACCEL_REG(RADEON_DP_CNTL, - ((xdir >= 0 ? RADEON_DST_X_LEFT_TO_RIGHT : 0) | - (ydir >= 0 ? RADEON_DST_Y_TOP_TO_BOTTOM : 0))); - - FINISH_ACCEL(); - BEGIN_ACCEL(2); - OUT_ACCEL_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); - OUT_ACCEL_REG(RADEON_WAIT_UNTIL, - RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); - FINISH_ACCEL(); - - info->accel_state->trans_color = trans_color; - FUNC_NAME(RADEONSetTransparency)(pScrn, trans_color); -} - -/* Subsequent XAA screen-to-screen copy */ -static void -FUNC_NAME(RADEONSubsequentScreenToScreenCopy)(ScrnInfoPtr pScrn, - int xa, int ya, - int xb, int yb, - int w, int h) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - ACCEL_PREAMBLE(); - - if (info->accel_state->xdir < 0) xa += w - 1, xb += w - 1; - if (info->accel_state->ydir < 0) ya += h - 1, yb += h - 1; - - BEGIN_ACCEL(5); - - OUT_ACCEL_REG(RADEON_SRC_PITCH_OFFSET, info->accel_state->dst_pitch_offset | - ((info->tilingEnabled && (ya <= pScrn->virtualY)) ? RADEON_DST_TILE_MACRO : 0)); - OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->accel_state->dst_pitch_offset | - ((info->tilingEnabled && (yb <= pScrn->virtualY)) ? RADEON_DST_TILE_MACRO : 0)); - OUT_ACCEL_REG(RADEON_SRC_Y_X, (ya << 16) | xa); - OUT_ACCEL_REG(RADEON_DST_Y_X, (yb << 16) | xb); - OUT_ACCEL_REG(RADEON_DST_HEIGHT_WIDTH, (h << 16) | w); - - FINISH_ACCEL(); -} - -/* Setup for XAA mono 8x8 pattern color expansion. Patterns with - * transparency use `bg == -1'. This routine is only used if the XAA - * pixmap cache is turned on. - * - * Tests: xtest XFree86/fllrctngl (no other test will test this routine with - * both transparency and non-transparency) - */ -static void -FUNC_NAME(RADEONSetupForMono8x8PatternFill)(ScrnInfoPtr pScrn, - int patternx, - int patterny, - int fg, - int bg, - int rop, - unsigned int planemask) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); -#if X_BYTE_ORDER == X_BIG_ENDIAN - unsigned char pattern[8]; -#endif - ACCEL_PREAMBLE(); - -#if X_BYTE_ORDER == X_BIG_ENDIAN - /* Take care of endianness */ - pattern[0] = (patternx & 0x000000ff); - pattern[1] = (patternx & 0x0000ff00) >> 8; - pattern[2] = (patternx & 0x00ff0000) >> 16; - pattern[3] = (patternx & 0xff000000) >> 24; - pattern[4] = (patterny & 0x000000ff); - pattern[5] = (patterny & 0x0000ff00) >> 8; - pattern[6] = (patterny & 0x00ff0000) >> 16; - pattern[7] = (patterny & 0xff000000) >> 24; -#endif - - /* Save for later clipping */ - info->accel_state->dp_gui_master_cntl_clip = (info->accel_state->dp_gui_master_cntl - | (bg == -1 - ? RADEON_GMC_BRUSH_8X8_MONO_FG_LA - : RADEON_GMC_BRUSH_8X8_MONO_FG_BG) - | RADEON_ROP[rop].pattern -#if X_BYTE_ORDER == X_LITTLE_ENDIAN - | RADEON_GMC_BYTE_MSB_TO_LSB -#endif - ); - - BEGIN_ACCEL((bg == -1) ? 5 : 6); - - OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, info->accel_state->dp_gui_master_cntl_clip); - OUT_ACCEL_REG(RADEON_DP_WRITE_MASK, planemask); - OUT_ACCEL_REG(RADEON_DP_BRUSH_FRGD_CLR, fg); - if (bg != -1) - OUT_ACCEL_REG(RADEON_DP_BRUSH_BKGD_CLR, bg); -#if X_BYTE_ORDER == X_LITTLE_ENDIAN - OUT_ACCEL_REG(RADEON_BRUSH_DATA0, patternx); - OUT_ACCEL_REG(RADEON_BRUSH_DATA1, patterny); -#else - OUT_ACCEL_REG(RADEON_BRUSH_DATA0, *(uint32_t *)(pointer)&pattern[0]); - OUT_ACCEL_REG(RADEON_BRUSH_DATA1, *(uint32_t *)(pointer)&pattern[4]); -#endif - - FINISH_ACCEL(); - BEGIN_ACCEL(2); - OUT_ACCEL_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); - OUT_ACCEL_REG(RADEON_WAIT_UNTIL, - RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); - FINISH_ACCEL(); -} - -/* Subsequent XAA 8x8 pattern color expansion. Because they are used in - * the setup function, `patternx' and `patterny' are not used here. - */ -static void -FUNC_NAME(RADEONSubsequentMono8x8PatternFillRect)(ScrnInfoPtr pScrn, - int patternx, - int patterny, - int x, int y, - int w, int h) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - ACCEL_PREAMBLE(); - - BEGIN_ACCEL(4); - - OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->accel_state->dst_pitch_offset | - ((info->tilingEnabled && (y <= pScrn->virtualY)) ? RADEON_DST_TILE_MACRO : 0)); - OUT_ACCEL_REG(RADEON_BRUSH_Y_X, (patterny << 8) | patternx); - OUT_ACCEL_REG(RADEON_DST_Y_X, (y << 16) | x); - OUT_ACCEL_REG(RADEON_DST_HEIGHT_WIDTH, (h << 16) | w); - - FINISH_ACCEL(); -} - -#if 0 -/* Setup for XAA color 8x8 pattern fill - * - * Tests: xtest XFree86/fllrctngl (with Mono8x8PatternFill off) - */ -static void -FUNC_NAME(RADEONSetupForColor8x8PatternFill)(ScrnInfoPtr pScrn, - int patx, int paty, - int rop, - unsigned int planemask, - int trans_color) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - ACCEL_PREAMBLE(); - - /* Save for later clipping */ - info->accel_state->dp_gui_master_cntl_clip = (info->accel_state->dp_gui_master_cntl - | RADEON_GMC_BRUSH_8x8_COLOR - | RADEON_GMC_SRC_DATATYPE_COLOR - | RADEON_ROP[rop].pattern - | RADEON_DP_SRC_SOURCE_MEMORY); - - BEGIN_ACCEL(3); - - OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, info->accel_state->dp_gui_master_cntl_clip); - OUT_ACCEL_REG(RADEON_DP_WRITE_MASK, planemask); - OUT_ACCEL_REG(RADEON_SRC_Y_X, (paty << 16) | patx); - - FINISH_ACCEL(); - - info->accel_state->trans_color = trans_color; - FUNC_NAME(RADEONSetTransparency)(pScrn, trans_color); -} - -/* Subsequent XAA 8x8 pattern color expansion */ -static void -FUNC_NAME(RADEONSubsequentColor8x8PatternFillRect)(ScrnInfoPtr pScrn, - int patx, int paty, - int x, int y, - int w, int h) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - ACCEL_PREAMBLE(); - - BEGIN_ACCEL(4); - - OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->accel_state->dst_pitch_offset | - ((info->tilingEnabled && (y <= pScrn->virtualY)) ? RADEON_DST_TILE_MACRO : 0)); - OUT_ACCEL_REG(RADEON_BRUSH_Y_X, (paty << 16) | patx); - OUT_ACCEL_REG(RADEON_DST_Y_X, (y << 16) | x); - OUT_ACCEL_REG(RADEON_DST_HEIGHT_WIDTH, (h << 16) | w); - - FINISH_ACCEL(); -} -#endif - -#ifdef ACCEL_CP -#define CP_BUFSIZE (info->cp->indirectBuffer->total/4-10) - -/* Helper function to write out a HOSTDATA_BLT packet into the indirect - * buffer and set the XAA scratch buffer address appropriately. - */ -static void -RADEONCPScanlinePacket(ScrnInfoPtr pScrn, int bufno) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - int chunk_words = info->accel_state->scanline_hpass * info->accel_state->scanline_words; - ACCEL_PREAMBLE(); - - if (RADEON_VERBOSE) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "CPScanline Packet h=%d hpass=%d chunkwords=%d\n", - info->accel_state->scanline_h, info->accel_state->scanline_hpass, chunk_words); - } - BEGIN_RING(chunk_words+10); - - OUT_RING(CP_PACKET3(RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT,chunk_words+10-2)); - OUT_RING(info->accel_state->dp_gui_master_cntl_clip); - OUT_RING(info->accel_state->dst_pitch_offset | - ((info->tilingEnabled && (info->accel_state->scanline_y <= pScrn->virtualY)) ? RADEON_DST_TILE_MACRO : 0)); - OUT_RING((info->accel_state->scanline_y << 16) | - (info->accel_state->scanline_x1clip & 0xffff)); - OUT_RING(((info->accel_state->scanline_y+info->accel_state->scanline_hpass) << 16) | - (info->accel_state->scanline_x2clip & 0xffff)); - OUT_RING(info->accel_state->scanline_fg); - OUT_RING(info->accel_state->scanline_bg); - OUT_RING((info->accel_state->scanline_y << 16) | - (info->accel_state->scanline_x & 0xffff)); - OUT_RING((info->accel_state->scanline_hpass << 16) | - (info->accel_state->scanline_w & 0xffff)); - OUT_RING(chunk_words); - - info->accel_state->scratch_buffer[bufno] = (unsigned char *)&__head[__count]; - __count += chunk_words; - - /* The ring can only be advanced after the __head and __count have - been adjusted above */ - FINISH_ACCEL(); - - info->accel_state->scanline_y += info->accel_state->scanline_hpass; - info->accel_state->scanline_h -= info->accel_state->scanline_hpass; -} -#endif - -/* Setup for XAA indirect CPU-to-screen color expansion (indirect). - * Because of how the scratch buffer is initialized, this is really a - * mainstore-to-screen color expansion. Transparency is supported when - * `bg == -1'. - */ -static void -FUNC_NAME(RADEONSetupForScanlineCPUToScreenColorExpandFill)(ScrnInfoPtr pScrn, - int fg, - int bg, - int rop, - unsigned int - planemask) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - ACCEL_PREAMBLE(); - - info->accel_state->scanline_bpp = 0; - - /* Save for later clipping */ - info->accel_state->dp_gui_master_cntl_clip = (info->accel_state->dp_gui_master_cntl - | RADEON_GMC_DST_CLIPPING - | RADEON_GMC_BRUSH_NONE - | (bg == -1 - ? RADEON_GMC_SRC_DATATYPE_MONO_FG_LA - : RADEON_GMC_SRC_DATATYPE_MONO_FG_BG) - | RADEON_ROP[rop].rop -#if X_BYTE_ORDER == X_LITTLE_ENDIAN - | RADEON_GMC_BYTE_LSB_TO_MSB -#else - | RADEON_GMC_BYTE_MSB_TO_LSB -#endif - | RADEON_DP_SRC_SOURCE_HOST_DATA); - -#ifdef ACCEL_MMIO - -#if X_BYTE_ORDER == X_LITTLE_ENDIAN - BEGIN_ACCEL(4); -#else - BEGIN_ACCEL(5); - - OUT_ACCEL_REG(RADEON_RBBM_GUICNTL, RADEON_HOST_DATA_SWAP_NONE); -#endif - OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, info->accel_state->dp_gui_master_cntl_clip); - OUT_ACCEL_REG(RADEON_DP_WRITE_MASK, planemask); - OUT_ACCEL_REG(RADEON_DP_SRC_FRGD_CLR, fg); - OUT_ACCEL_REG(RADEON_DP_SRC_BKGD_CLR, bg); - -#else /* ACCEL_CP */ - - info->accel_state->scanline_fg = fg; - info->accel_state->scanline_bg = bg; - -#if X_BYTE_ORDER == X_LITTLE_ENDIAN - BEGIN_ACCEL(1); -#else - if (info->ChipFamily < CHIP_FAMILY_R300) { - BEGIN_ACCEL(2); - - OUT_ACCEL_REG(RADEON_RBBM_GUICNTL, RADEON_HOST_DATA_SWAP_32BIT); - } else - BEGIN_ACCEL(1); -#endif - OUT_ACCEL_REG(RADEON_DP_WRITE_MASK, planemask); - -#endif - - FINISH_ACCEL(); -} - -/* Subsequent XAA indirect CPU-to-screen color expansion. This is only - * called once for each rectangle. - */ -static void -FUNC_NAME(RADEONSubsequentScanlineCPUToScreenColorExpandFill)(ScrnInfoPtr - pScrn, - int x, int y, - int w, int h, - int skipleft) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); -#ifdef ACCEL_MMIO - ACCEL_PREAMBLE(); - - info->accel_state->scanline_h = h; - info->accel_state->scanline_words = (w + 31) >> 5; - -#ifdef __alpha__ - /* Always use indirect for Alpha */ - if (0) -#else - if ((info->accel_state->scanline_words * h) <= 9) -#endif - { - /* Turn on direct for less than 9 dword colour expansion */ - info->accel_state->scratch_buffer[0] = - (unsigned char *)(ADDRREG(RADEON_HOST_DATA_LAST) - - (info->accel_state->scanline_words - 1)); - info->accel_state->scanline_direct = 1; - } else { - /* Use indirect for anything else */ - info->accel_state->scratch_buffer[0] = info->accel_state->scratch_save; - info->accel_state->scanline_direct = 0; - } - - BEGIN_ACCEL(5 + (info->accel_state->scanline_direct ? - (info->accel_state->scanline_words * h) : 0)); - - OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->accel_state->dst_pitch_offset | - ((info->tilingEnabled && (y <= pScrn->virtualY)) ? RADEON_DST_TILE_MACRO : 0)); - OUT_ACCEL_REG(RADEON_SC_TOP_LEFT, (y << 16) | ((x+skipleft) - & 0xffff)); - OUT_ACCEL_REG(RADEON_SC_BOTTOM_RIGHT, ((y+h) << 16) | ((x+w) & 0xffff)); - OUT_ACCEL_REG(RADEON_DST_Y_X, (y << 16) | (x & 0xffff)); - /* Have to pad the width here and use clipping engine */ - OUT_ACCEL_REG(RADEON_DST_HEIGHT_WIDTH, (h << 16) | RADEON_ALIGN(w, 32)); - - FINISH_ACCEL(); - -#else /* ACCEL_CP */ - - info->accel_state->scanline_x = x; - info->accel_state->scanline_y = y; - /* Have to pad the width here and use clipping engine */ - info->accel_state->scanline_w = RADEON_ALIGN(w, 32); - info->accel_state->scanline_h = h; - - info->accel_state->scanline_x1clip = x + skipleft; - info->accel_state->scanline_x2clip = x + w; - - info->accel_state->scanline_words = info->accel_state->scanline_w / 32; - info->accel_state->scanline_hpass = min(h,(CP_BUFSIZE/info->accel_state->scanline_words)); - - RADEONCPScanlinePacket(pScrn, 0); - -#endif -} - -/* Subsequent XAA indirect CPU-to-screen color expansion and indirect - * image write. This is called once for each scanline. - */ -static void -FUNC_NAME(RADEONSubsequentScanline)(ScrnInfoPtr pScrn, - int bufno) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); -#ifdef ACCEL_MMIO - uint32_t *p = (pointer)info->accel_state->scratch_buffer[bufno]; - int i; - int left = info->accel_state->scanline_words; - volatile uint32_t *d; - ACCEL_PREAMBLE(); - - if (info->accel_state->scanline_direct) return; - - --info->accel_state->scanline_h; - - while (left) { - write_mem_barrier(); - if (left <= 8) { - /* Last scanline - finish write to DATA_LAST */ - if (info->accel_state->scanline_h == 0) { - BEGIN_ACCEL(left); - /* Unrolling doesn't improve performance */ - for (d = ADDRREG(RADEON_HOST_DATA_LAST) - (left - 1); left; --left) - *d++ = *p++; - return; - } else { - BEGIN_ACCEL(left); - /* Unrolling doesn't improve performance */ - for (d = ADDRREG(RADEON_HOST_DATA7) - (left - 1); left; --left) - *d++ = *p++; - } - } else { - BEGIN_ACCEL(8); - /* Unrolling doesn't improve performance */ - for (d = ADDRREG(RADEON_HOST_DATA0), i = 0; i < 8; i++) - *d++ = *p++; - left -= 8; - } - } - - FINISH_ACCEL(); - -#else /* ACCEL_CP */ - -#if X_BYTE_ORDER == X_BIG_ENDIAN - if (info->ChipFamily >= CHIP_FAMILY_R300) { - if (info->accel_state->scanline_bpp == 16) { - RADEONCopySwap(info->accel_state->scratch_buffer[bufno], - info->accel_state->scratch_buffer[bufno], - info->accel_state->scanline_words << 2, - RADEON_HOST_DATA_SWAP_HDW); - } else if (info->accel_state->scanline_bpp < 15) { - RADEONCopySwap(info->accel_state->scratch_buffer[bufno], - info->accel_state->scratch_buffer[bufno], - info->accel_state->scanline_words << 2, - RADEON_HOST_DATA_SWAP_32BIT); - } - } -#endif - - if (--info->accel_state->scanline_hpass) { - info->accel_state->scratch_buffer[bufno] += 4 * info->accel_state->scanline_words; - } else if (info->accel_state->scanline_h) { - info->accel_state->scanline_hpass = - min(info->accel_state->scanline_h,(CP_BUFSIZE/info->accel_state->scanline_words)); - RADEONCPScanlinePacket(pScrn, bufno); - } - -#endif -} - -/* Setup for XAA indirect image write */ -static void -FUNC_NAME(RADEONSetupForScanlineImageWrite)(ScrnInfoPtr pScrn, - int rop, - unsigned int planemask, - int trans_color, - int bpp, - int depth) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - ACCEL_PREAMBLE(); - - info->accel_state->scanline_bpp = bpp; - - /* Save for later clipping */ - info->accel_state->dp_gui_master_cntl_clip = (info->accel_state->dp_gui_master_cntl - | RADEON_GMC_DST_CLIPPING - | RADEON_GMC_BRUSH_NONE - | RADEON_GMC_SRC_DATATYPE_COLOR - | RADEON_ROP[rop].rop - | RADEON_GMC_BYTE_MSB_TO_LSB - | RADEON_DP_SRC_SOURCE_HOST_DATA); - -#ifdef ACCEL_MMIO - -#if X_BYTE_ORDER == X_LITTLE_ENDIAN - BEGIN_ACCEL(2); -#else - BEGIN_ACCEL(3); - - if (bpp == 16) - OUT_ACCEL_REG(RADEON_RBBM_GUICNTL, RADEON_HOST_DATA_SWAP_16BIT); - else if (bpp == 32) - OUT_ACCEL_REG(RADEON_RBBM_GUICNTL, RADEON_HOST_DATA_SWAP_32BIT); - else - OUT_ACCEL_REG(RADEON_RBBM_GUICNTL, RADEON_HOST_DATA_SWAP_NONE); -#endif - OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, info->accel_state->dp_gui_master_cntl_clip); - -#else /* ACCEL_CP */ - -#if X_BYTE_ORDER == X_LITTLE_ENDIAN - BEGIN_ACCEL(1); -#else - if (info->ChipFamily < CHIP_FAMILY_R300) { - BEGIN_ACCEL(2); - - if (bpp == 16) - OUT_ACCEL_REG(RADEON_RBBM_GUICNTL, RADEON_HOST_DATA_SWAP_HDW); - else - OUT_ACCEL_REG(RADEON_RBBM_GUICNTL, RADEON_HOST_DATA_SWAP_NONE); - } else - BEGIN_ACCEL(1); -#endif -#endif - OUT_ACCEL_REG(RADEON_DP_WRITE_MASK, planemask); - - FINISH_ACCEL(); - - info->accel_state->trans_color = trans_color; - FUNC_NAME(RADEONSetTransparency)(pScrn, trans_color); -} - -/* Subsequent XAA indirect image write. This is only called once for - * each rectangle. - */ -static void -FUNC_NAME(RADEONSubsequentScanlineImageWriteRect)(ScrnInfoPtr pScrn, - int x, int y, - int w, int h, - int skipleft) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - -#ifdef ACCEL_MMIO - - int shift = 0; /* 32bpp */ - ACCEL_PREAMBLE(); - - if (pScrn->bitsPerPixel == 8) shift = 3; - else if (pScrn->bitsPerPixel == 16) shift = 1; - - info->accel_state->scanline_h = h; - info->accel_state->scanline_words = (w * info->accel_state->scanline_bpp + 31) >> 5; - -#ifdef __alpha__ - /* Always use indirect for Alpha */ - if (0) -#else - if ((info->accel_state->scanline_words * h) <= 9) -#endif - { - /* Turn on direct for less than 9 dword colour expansion */ - info->accel_state->scratch_buffer[0] - = (unsigned char *)(ADDRREG(RADEON_HOST_DATA_LAST) - - (info->accel_state->scanline_words - 1)); - info->accel_state->scanline_direct = 1; - } else { - /* Use indirect for anything else */ - info->accel_state->scratch_buffer[0] = info->accel_state->scratch_save; - info->accel_state->scanline_direct = 0; - } - - BEGIN_ACCEL(5 + (info->accel_state->scanline_direct ? - (info->accel_state->scanline_words * h) : 0)); - - OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->accel_state->dst_pitch_offset | - ((info->tilingEnabled && (y <= pScrn->virtualY)) ? RADEON_DST_TILE_MACRO : 0)); - OUT_ACCEL_REG(RADEON_SC_TOP_LEFT, (y << 16) | ((x+skipleft) - & 0xffff)); - OUT_ACCEL_REG(RADEON_SC_BOTTOM_RIGHT, ((y+h) << 16) | ((x+w) & 0xffff)); - OUT_ACCEL_REG(RADEON_DST_Y_X, (y << 16) | (x & 0xffff)); - /* Have to pad the width here and use clipping engine */ - OUT_ACCEL_REG(RADEON_DST_HEIGHT_WIDTH, (h << 16) | ((w + shift) & - ~shift)); - - FINISH_ACCEL(); - -#else /* ACCEL_CP */ - - int pad = 0; /* 32bpp */ - - if (pScrn->bitsPerPixel == 8) pad = 3; - else if (pScrn->bitsPerPixel == 16) pad = 1; - - info->accel_state->scanline_x = x; - info->accel_state->scanline_y = y; - /* Have to pad the width here and use clipping engine */ - info->accel_state->scanline_w = (w + pad) & ~pad; - info->accel_state->scanline_h = h; - - info->accel_state->scanline_x1clip = x + skipleft; - info->accel_state->scanline_x2clip = x + w; - - info->accel_state->scanline_words = (w * info->accel_state->scanline_bpp + 31) / 32; - info->accel_state->scanline_hpass = min(h,(CP_BUFSIZE/info->accel_state->scanline_words)); - - RADEONCPScanlinePacket(pScrn, 0); - -#endif -} - -/* Set up the clipping rectangle */ -static void -FUNC_NAME(RADEONSetClippingRectangle)(ScrnInfoPtr pScrn, - int xa, int ya, - int xb, int yb) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned long tmp1 = 0; - unsigned long tmp2 = 0; - ACCEL_PREAMBLE(); - - if (xa < 0) { - tmp1 = (-xa) & 0x3fff; - tmp1 |= RADEON_SC_SIGN_MASK_LO; - } else { - tmp1 = xa; - } - - if (ya < 0) { - tmp1 |= (((-ya) & 0x3fff) << 16); - tmp1 |= RADEON_SC_SIGN_MASK_HI; - } else { - tmp1 |= (ya << 16); - } - - xb++; yb++; - - if (xb < 0) { - tmp2 = (-xb) & 0x3fff; - tmp2 |= RADEON_SC_SIGN_MASK_LO; - } else { - tmp2 = xb; - } - - if (yb < 0) { - tmp2 |= (((-yb) & 0x3fff) << 16); - tmp2 |= RADEON_SC_SIGN_MASK_HI; - } else { - tmp2 |= (yb << 16); - } - - BEGIN_ACCEL(3); - - OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, (info->accel_state->dp_gui_master_cntl_clip - | RADEON_GMC_DST_CLIPPING)); - OUT_ACCEL_REG(RADEON_SC_TOP_LEFT, tmp1); - OUT_ACCEL_REG(RADEON_SC_BOTTOM_RIGHT, tmp2); - - FINISH_ACCEL(); - BEGIN_ACCEL(2); - OUT_ACCEL_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); - OUT_ACCEL_REG(RADEON_WAIT_UNTIL, - RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); - FINISH_ACCEL(); - - FUNC_NAME(RADEONSetTransparency)(pScrn, info->accel_state->trans_color); -} - -/* Disable the clipping rectangle */ -static void -FUNC_NAME(RADEONDisableClipping)(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - ACCEL_PREAMBLE(); - - BEGIN_ACCEL(3); - - OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, info->accel_state->dp_gui_master_cntl_clip); - OUT_ACCEL_REG(RADEON_SC_TOP_LEFT, 0); - OUT_ACCEL_REG(RADEON_SC_BOTTOM_RIGHT, (RADEON_DEFAULT_SC_RIGHT_MAX | - RADEON_DEFAULT_SC_BOTTOM_MAX)); - - FINISH_ACCEL(); - BEGIN_ACCEL(2); - OUT_ACCEL_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); - OUT_ACCEL_REG(RADEON_WAIT_UNTIL, - RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); - FINISH_ACCEL(); - - FUNC_NAME(RADEONSetTransparency)(pScrn, info->accel_state->trans_color); -} - -void -FUNC_NAME(RADEONAccelInit)(ScreenPtr pScreen, XAAInfoRecPtr a) -{ - ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); - RADEONInfoPtr info = RADEONPTR(pScrn); - - a->Flags = (PIXMAP_CACHE - | OFFSCREEN_PIXMAPS - | LINEAR_FRAMEBUFFER); - - /* Sync */ - a->Sync = FUNC_NAME(RADEONWaitForIdle); - - /* Solid Filled Rectangle */ - a->PolyFillRectSolidFlags = 0; - a->SetupForSolidFill - = FUNC_NAME(RADEONSetupForSolidFill); - a->SubsequentSolidFillRect - = FUNC_NAME(RADEONSubsequentSolidFillRect); - - /* Screen-to-screen Copy */ - a->ScreenToScreenCopyFlags = 0; - a->SetupForScreenToScreenCopy - = FUNC_NAME(RADEONSetupForScreenToScreenCopy); - a->SubsequentScreenToScreenCopy - = FUNC_NAME(RADEONSubsequentScreenToScreenCopy); - - /* Mono 8x8 Pattern Fill (Color Expand) */ - a->SetupForMono8x8PatternFill - = FUNC_NAME(RADEONSetupForMono8x8PatternFill); - a->SubsequentMono8x8PatternFillRect - = FUNC_NAME(RADEONSubsequentMono8x8PatternFillRect); - a->Mono8x8PatternFillFlags = (HARDWARE_PATTERN_PROGRAMMED_BITS - | HARDWARE_PATTERN_PROGRAMMED_ORIGIN - | HARDWARE_PATTERN_SCREEN_ORIGIN); - -#if X_BYTE_ORDER == X_LITTLE_ENDIAN - if (info->ChipFamily >= CHIP_FAMILY_RV200) - a->Mono8x8PatternFillFlags |= BIT_ORDER_IN_BYTE_MSBFIRST; - else - a->Mono8x8PatternFillFlags |= BIT_ORDER_IN_BYTE_LSBFIRST; -#else - a->Mono8x8PatternFillFlags |= BIT_ORDER_IN_BYTE_LSBFIRST; -#endif - - /* Indirect CPU-To-Screen Color Expand */ - - /* RADEON gets upset, when using HOST provided data without a source - rop. To show run 'xtest's drwarc. */ - a->ScanlineCPUToScreenColorExpandFillFlags - = (LEFT_EDGE_CLIPPING - | ROP_NEEDS_SOURCE - | LEFT_EDGE_CLIPPING_NEGATIVE_X); - a->NumScanlineColorExpandBuffers = 1; - a->ScanlineColorExpandBuffers = info->accel_state->scratch_buffer; - if (!info->accel_state->scratch_save) - info->accel_state->scratch_save - = malloc(((pScrn->virtualX+31)/32*4) - + (pScrn->virtualX * info->CurrentLayout.pixel_bytes)); - info->accel_state->scratch_buffer[0] = info->accel_state->scratch_save; - a->SetupForScanlineCPUToScreenColorExpandFill - = FUNC_NAME(RADEONSetupForScanlineCPUToScreenColorExpandFill); - a->SubsequentScanlineCPUToScreenColorExpandFill - = FUNC_NAME(RADEONSubsequentScanlineCPUToScreenColorExpandFill); - a->SubsequentColorExpandScanline - = FUNC_NAME(RADEONSubsequentScanline); - - /* Solid Lines */ - a->SetupForSolidLine - = FUNC_NAME(RADEONSetupForSolidLine); - a->SubsequentSolidHorVertLine - = FUNC_NAME(RADEONSubsequentSolidHorVertLine); - - if (info->xaaReq.minorversion >= 1) { - - /* RADEON only supports 14 bits for lines and clipping and only - * draws lines that are completely on-screen correctly. This will - * cause display corruption problem in the cases when out-of-range - * commands are issued, like when dimming screen during GNOME logout - * in dual-head setup. Solid and dashed lines are therefore limited - * to the virtual screen. - */ - - a->SolidLineFlags = LINE_LIMIT_COORDS; - a->SolidLineLimits.x1 = 0; - a->SolidLineLimits.y1 = 0; - a->SolidLineLimits.x2 = pScrn->virtualX-1; - a->SolidLineLimits.y2 = pScrn->virtualY-1; - - /* Call miSetZeroLineBias() to have mi/mfb/fb routines match - hardware accel two point lines */ - miSetZeroLineBias(pScreen, (OCTANT5 | OCTANT6 | OCTANT7 | OCTANT8)); - -#ifdef ACCEL_CP - /* RV280s lock up with this using the CP for reasons to be determined. - * See https://bugs.freedesktop.org/show_bug.cgi?id=5986 . - */ - if (info->ChipFamily != CHIP_FAMILY_RV280) -#endif - a->SubsequentSolidTwoPointLine - = FUNC_NAME(RADEONSubsequentSolidTwoPointLine); - - /* Disabled on RV200 and newer because it does not pass XTest */ - if (info->ChipFamily < CHIP_FAMILY_RV200) { - a->SetupForDashedLine - = FUNC_NAME(RADEONSetupForDashedLine); - a->SubsequentDashedTwoPointLine - = FUNC_NAME(RADEONSubsequentDashedTwoPointLine); - a->DashPatternMaxLength = 32; - /* ROP3 doesn't seem to work properly for dashedline with GXinvert */ - a->DashedLineFlags = (LINE_PATTERN_LSBFIRST_LSBJUSTIFIED - | LINE_PATTERN_POWER_OF_2_ONLY - | LINE_LIMIT_COORDS - | ROP_NEEDS_SOURCE); - a->DashedLineLimits.x1 = 0; - a->DashedLineLimits.y1 = 0; - a->DashedLineLimits.x2 = pScrn->virtualX-1; - a->DashedLineLimits.y2 = pScrn->virtualY-1; - } - - } else { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "libxaa too old, can't accelerate TwoPoint lines\n"); - } - - /* Clipping, note that without this, all line accelerations will - * not be called - */ - a->SetClippingRectangle - = FUNC_NAME(RADEONSetClippingRectangle); - a->DisableClipping - = FUNC_NAME(RADEONDisableClipping); - a->ClippingFlags - = (HARDWARE_CLIP_SOLID_LINE - | HARDWARE_CLIP_DASHED_LINE - /* | HARDWARE_CLIP_SOLID_FILL -- seems very slow with this on */ - | HARDWARE_CLIP_MONO_8x8_FILL - | HARDWARE_CLIP_SCREEN_TO_SCREEN_COPY); - - if (xf86IsEntityShared(info->pEnt->index)) { - /* If there are more than one devices sharing this entity, we - * have to assign this call back, otherwise the XAA will be - * disabled - */ - if (xf86GetNumEntityInstances(info->pEnt->index) > 1) - a->RestoreAccelState = FUNC_NAME(RADEONRestoreAccelState); - } - - /* ImageWrite */ - a->NumScanlineImageWriteBuffers = 1; - a->ScanlineImageWriteBuffers = info->accel_state->scratch_buffer; - a->SetupForScanlineImageWrite - = FUNC_NAME(RADEONSetupForScanlineImageWrite); - a->SubsequentScanlineImageWriteRect - = FUNC_NAME(RADEONSubsequentScanlineImageWriteRect); - a->SubsequentImageWriteScanline = FUNC_NAME(RADEONSubsequentScanline); - a->ScanlineImageWriteFlags = (CPU_TRANSFER_PAD_DWORD -#ifdef ACCEL_MMIO - /* Performance tests show that we shouldn't use GXcopy - * for uploads as a memcpy is faster - */ - | NO_GXCOPY -#endif - /* RADEON gets upset, when using HOST provided data - * without a source rop. To show run 'xtest's ptimg - */ - | ROP_NEEDS_SOURCE - | SCANLINE_PAD_DWORD - | LEFT_EDGE_CLIPPING - | LEFT_EDGE_CLIPPING_NEGATIVE_X); - -#if 0 - /* Color 8x8 Pattern Fill */ - a->SetupForColor8x8PatternFill - = FUNC_NAME(RADEONSetupForColor8x8PatternFill); - a->SubsequentColor8x8PatternFillRect - = FUNC_NAME(RADEONSubsequentColor8x8PatternFillRect); - a->Color8x8PatternFillFlags = (HARDWARE_PATTERN_PROGRAMMED_ORIGIN - | HARDWARE_PATTERN_SCREEN_ORIGIN - | BIT_ORDER_IN_BYTE_LSBFIRST); -#endif - -#ifdef RENDER - info->RenderAccel = FALSE; - if (info->RenderAccel && info->xaaReq.minorversion >= 2) { - - a->CPUToScreenAlphaTextureFlags = XAA_RENDER_POWER_OF_2_TILE_ONLY; - a->CPUToScreenAlphaTextureFormats = RADEONTextureFormats; - a->CPUToScreenAlphaTextureDstFormats = RADEONDstFormats; - a->CPUToScreenTextureFlags = XAA_RENDER_POWER_OF_2_TILE_ONLY; - a->CPUToScreenTextureFormats = RADEONTextureFormats; - a->CPUToScreenTextureDstFormats = RADEONDstFormats; - - if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "XAA Render acceleration " - "unsupported on Radeon 9500/9700 and newer. " - "Please use EXA instead.\n"); - } else if (IS_R200_3D) { - a->SetupForCPUToScreenAlphaTexture2 = - FUNC_NAME(R200SetupForCPUToScreenAlphaTexture); - a->SubsequentCPUToScreenAlphaTexture = - FUNC_NAME(R200SubsequentCPUToScreenTexture); - - a->SetupForCPUToScreenTexture2 = - FUNC_NAME(R200SetupForCPUToScreenTexture); - a->SubsequentCPUToScreenTexture = - FUNC_NAME(R200SubsequentCPUToScreenTexture); - } else { - a->SetupForCPUToScreenAlphaTexture2 = - FUNC_NAME(R100SetupForCPUToScreenAlphaTexture); - a->SubsequentCPUToScreenAlphaTexture = - FUNC_NAME(R100SubsequentCPUToScreenTexture); - - a->SetupForCPUToScreenTexture2 = - FUNC_NAME(R100SetupForCPUToScreenTexture); - a->SubsequentCPUToScreenTexture = - FUNC_NAME(R100SubsequentCPUToScreenTexture); - } - } else if (info->RenderAccel) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration currently " - "requires XAA v1.2 or newer.\n"); - } - - if (!a->SetupForCPUToScreenAlphaTexture2 && !a->SetupForCPUToScreenTexture2) - info->RenderAccel = FALSE; - - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration %s\n", - info->RenderAccel ? "enabled" : "disabled"); -#endif /* RENDER */ -} - -#endif /* USE_XAA */ - -#undef FUNC_NAME diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c deleted file mode 100644 index 61ef528a..00000000 --- a/src/radeon_atombios.c +++ /dev/null @@ -1,3022 +0,0 @@ -/* - * Copyright 2007 Egbert Eich <eich@novell.com> - * Copyright 2007 Luc Verhaegen <lverhaegen@novell.com> - * Copyright 2007 Matthias Hopf <mhopf@novell.com> - * Copyright 2007 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifdef HAVE_CONFIG_H -# include "config.h" -#endif -#include "xf86.h" -#include "xf86_OSproc.h" - -#include "radeon.h" -#include "radeon_reg.h" -#include "radeon_atombios.h" -#include "radeon_atomwrapper.h" -#include "radeon_probe.h" -#include "radeon_macros.h" - -#include "ati_pciids_gen.h" - -#include "xorg-server.h" - -/* only for testing now */ -#include "xf86DDC.h" - -typedef AtomBiosResult (*AtomBiosRequestFunc)(atomBiosHandlePtr handle, - AtomBiosRequestID unused, AtomBiosArgPtr data); -typedef struct rhdConnectorInfo *rhdConnectorInfoPtr; - -static AtomBiosResult rhdAtomInit(atomBiosHandlePtr unused1, - AtomBiosRequestID unused2, AtomBiosArgPtr data); -static AtomBiosResult rhdAtomTearDown(atomBiosHandlePtr handle, - AtomBiosRequestID unused1, AtomBiosArgPtr unused2); -static AtomBiosResult rhdAtomVramInfoQuery(atomBiosHandlePtr handle, - AtomBiosRequestID func, AtomBiosArgPtr data); -static AtomBiosResult rhdAtomTmdsInfoQuery(atomBiosHandlePtr handle, - AtomBiosRequestID func, AtomBiosArgPtr data); -static AtomBiosResult rhdAtomAllocateFbScratch(atomBiosHandlePtr handle, - AtomBiosRequestID func, AtomBiosArgPtr data); -static AtomBiosResult rhdAtomLvdsGetTimings(atomBiosHandlePtr handle, - AtomBiosRequestID unused, AtomBiosArgPtr data); -static AtomBiosResult rhdAtomCVGetTimings(atomBiosHandlePtr handle, - AtomBiosRequestID unused, AtomBiosArgPtr data); -static AtomBiosResult rhdAtomLvdsInfoQuery(atomBiosHandlePtr handle, - AtomBiosRequestID func, AtomBiosArgPtr data); -static AtomBiosResult rhdAtomGPIOI2CInfoQuery(atomBiosHandlePtr handle, - AtomBiosRequestID func, AtomBiosArgPtr data); -static AtomBiosResult rhdAtomFirmwareInfoQuery(atomBiosHandlePtr handle, - AtomBiosRequestID func, AtomBiosArgPtr data); -/*static AtomBiosResult rhdAtomConnectorInfo(atomBiosHandlePtr handle, - AtomBiosRequestID unused, AtomBiosArgPtr data);*/ -# ifdef ATOM_BIOS_PARSER -static AtomBiosResult rhdAtomExec(atomBiosHandlePtr handle, - AtomBiosRequestID unused, AtomBiosArgPtr data); -# endif -static AtomBiosResult -rhdAtomCompassionateDataQuery(atomBiosHandlePtr handle, - AtomBiosRequestID func, AtomBiosArgPtr data); - - -static void -RADEONGetATOMLVDSInfo(ScrnInfoPtr pScrn, radeon_lvds_ptr lvds); - - -enum msgDataFormat { - MSG_FORMAT_NONE, - MSG_FORMAT_HEX, - MSG_FORMAT_DEC -}; - -struct atomBIOSRequests { - AtomBiosRequestID id; - AtomBiosRequestFunc request; - char *message; - enum msgDataFormat message_format; -} AtomBiosRequestList [] = { - {ATOMBIOS_INIT, rhdAtomInit, - "AtomBIOS Init", MSG_FORMAT_NONE}, - {ATOMBIOS_TEARDOWN, rhdAtomTearDown, - "AtomBIOS Teardown", MSG_FORMAT_NONE}, -# ifdef ATOM_BIOS_PARSER - {ATOMBIOS_EXEC, rhdAtomExec, - "AtomBIOS Exec", MSG_FORMAT_NONE}, -#endif - {ATOMBIOS_ALLOCATE_FB_SCRATCH, rhdAtomAllocateFbScratch, - "AtomBIOS Set FB Space", MSG_FORMAT_NONE}, - /*{ATOMBIOS_GET_CONNECTORS, rhdAtomConnectorInfo, - "AtomBIOS Get Connectors", MSG_FORMAT_NONE},*/ - {ATOMBIOS_GET_PANEL_MODE, rhdAtomLvdsGetTimings, - "AtomBIOS Get Panel Mode", MSG_FORMAT_NONE}, - {ATOMBIOS_GET_PANEL_EDID, rhdAtomLvdsGetTimings, - "AtomBIOS Get Panel EDID", MSG_FORMAT_NONE}, - {GET_DEFAULT_ENGINE_CLOCK, rhdAtomFirmwareInfoQuery, - "Default Engine Clock", MSG_FORMAT_DEC}, - {GET_DEFAULT_MEMORY_CLOCK, rhdAtomFirmwareInfoQuery, - "Default Memory Clock", MSG_FORMAT_DEC}, - {GET_MAX_PIXEL_CLOCK_PLL_OUTPUT, rhdAtomFirmwareInfoQuery, - "Maximum Pixel ClockPLL Frequency Output", MSG_FORMAT_DEC}, - {GET_MIN_PIXEL_CLOCK_PLL_OUTPUT, rhdAtomFirmwareInfoQuery, - "Minimum Pixel ClockPLL Frequency Output", MSG_FORMAT_DEC}, - {GET_MAX_PIXEL_CLOCK_PLL_INPUT, rhdAtomFirmwareInfoQuery, - "Maximum Pixel ClockPLL Frequency Input", MSG_FORMAT_DEC}, - {GET_MIN_PIXEL_CLOCK_PLL_INPUT, rhdAtomFirmwareInfoQuery, - "Minimum Pixel ClockPLL Frequency Input", MSG_FORMAT_DEC}, - {GET_MAX_PIXEL_CLK, rhdAtomFirmwareInfoQuery, - "Maximum Pixel Clock", MSG_FORMAT_DEC}, - {GET_REF_CLOCK, rhdAtomFirmwareInfoQuery, - "Reference Clock", MSG_FORMAT_DEC}, - {GET_FW_FB_START, rhdAtomVramInfoQuery, - "Start of VRAM area used by Firmware", MSG_FORMAT_HEX}, - {GET_FW_FB_SIZE, rhdAtomVramInfoQuery, - "Framebuffer space used by Firmware (kb)", MSG_FORMAT_DEC}, - {ATOM_TMDS_FREQUENCY, rhdAtomTmdsInfoQuery, - "TMDS Frequency", MSG_FORMAT_DEC}, - {ATOM_TMDS_PLL_CHARGE_PUMP, rhdAtomTmdsInfoQuery, - "TMDS PLL ChargePump", MSG_FORMAT_DEC}, - {ATOM_TMDS_PLL_DUTY_CYCLE, rhdAtomTmdsInfoQuery, - "TMDS PLL DutyCycle", MSG_FORMAT_DEC}, - {ATOM_TMDS_PLL_VCO_GAIN, rhdAtomTmdsInfoQuery, - "TMDS PLL VCO Gain", MSG_FORMAT_DEC}, - {ATOM_TMDS_PLL_VOLTAGE_SWING, rhdAtomTmdsInfoQuery, - "TMDS PLL VoltageSwing", MSG_FORMAT_DEC}, - {ATOM_LVDS_SUPPORTED_REFRESH_RATE, rhdAtomLvdsInfoQuery, - "LVDS Supported Refresh Rate", MSG_FORMAT_DEC}, - {ATOM_LVDS_OFF_DELAY, rhdAtomLvdsInfoQuery, - "LVDS Off Delay", MSG_FORMAT_DEC}, - {ATOM_LVDS_SEQ_DIG_ONTO_DE, rhdAtomLvdsInfoQuery, - "LVDS SEQ Dig onto DE", MSG_FORMAT_DEC}, - {ATOM_LVDS_SEQ_DE_TO_BL, rhdAtomLvdsInfoQuery, - "LVDS SEQ DE to BL", MSG_FORMAT_DEC}, - {ATOM_LVDS_DITHER, rhdAtomLvdsInfoQuery, - "LVDS Ditherc", MSG_FORMAT_HEX}, - {ATOM_LVDS_DUALLINK, rhdAtomLvdsInfoQuery, - "LVDS Duallink", MSG_FORMAT_HEX}, - {ATOM_LVDS_GREYLVL, rhdAtomLvdsInfoQuery, - "LVDS Grey Level", MSG_FORMAT_HEX}, - {ATOM_LVDS_FPDI, rhdAtomLvdsInfoQuery, - "LVDS FPDI", MSG_FORMAT_HEX}, - {ATOM_LVDS_24BIT, rhdAtomLvdsInfoQuery, - "LVDS 24Bit", MSG_FORMAT_HEX}, - {ATOM_GPIO_I2C_CLK_MASK, rhdAtomGPIOI2CInfoQuery, - "GPIO_I2C_Clk_Mask", MSG_FORMAT_HEX}, - {ATOM_DAC1_BG_ADJ, rhdAtomCompassionateDataQuery, - "DAC1 BG Adjustment", MSG_FORMAT_HEX}, - {ATOM_DAC1_DAC_ADJ, rhdAtomCompassionateDataQuery, - "DAC1 DAC Adjustment", MSG_FORMAT_HEX}, - {ATOM_DAC1_FORCE, rhdAtomCompassionateDataQuery, - "DAC1 Force Data", MSG_FORMAT_HEX}, - {ATOM_DAC2_CRTC2_BG_ADJ, rhdAtomCompassionateDataQuery, - "DAC2_CRTC2 BG Adjustment", MSG_FORMAT_HEX}, - {ATOM_DAC2_CRTC2_DAC_ADJ, rhdAtomCompassionateDataQuery, - "DAC2_CRTC2 DAC Adjustment", MSG_FORMAT_HEX}, - {ATOM_DAC2_CRTC2_FORCE, rhdAtomCompassionateDataQuery, - "DAC2_CRTC2 Force", MSG_FORMAT_HEX}, - {ATOM_DAC2_CRTC2_MUX_REG_IND,rhdAtomCompassionateDataQuery, - "DAC2_CRTC2 Mux Register Index", MSG_FORMAT_HEX}, - {ATOM_DAC2_CRTC2_MUX_REG_INFO,rhdAtomCompassionateDataQuery, - "DAC2_CRTC2 Mux Register Info", MSG_FORMAT_HEX}, - {ATOMBIOS_GET_CV_MODES, rhdAtomCVGetTimings, - "AtomBIOS Get CV Mode", MSG_FORMAT_NONE}, - {FUNC_END, NULL, - NULL, MSG_FORMAT_NONE} -}; - -enum { - legacyBIOSLocation = 0xC0000, - legacyBIOSMax = 0x10000 -}; - -#define DEBUGP(x) {x;} -#define LOG_DEBUG 7 - -# ifdef ATOM_BIOS_PARSER - -# define LOG_CAIL LOG_DEBUG + 1 - -#if 0 - -static void -RHDDebug(int scrnIndex, const char *format, ...) -{ - va_list ap; - - va_start(ap, format); - xf86VDrvMsgVerb(scrnIndex, X_INFO, LOG_DEBUG, format, ap); - va_end(ap); -} - -static void -RHDDebugCont(const char *format, ...) -{ - va_list ap; - - va_start(ap, format); - xf86VDrvMsgVerb(-1, X_NONE, LOG_DEBUG, format, ap); - va_end(ap); -} - -#endif - -static void -CailDebug(int scrnIndex, const char *format, ...) -{ - va_list ap; - - va_start(ap, format); - xf86VDrvMsgVerb(scrnIndex, X_INFO, LOG_CAIL, format, ap); - va_end(ap); -} -# define CAILFUNC(ptr) \ - CailDebug(((atomBiosHandlePtr)(ptr))->pScrn->scrnIndex, "CAIL: %s\n", __func__) - -# endif - -static int -rhdAtomAnalyzeCommonHdr(ATOM_COMMON_TABLE_HEADER *hdr) -{ - if (le16_to_cpu(hdr->usStructureSize) == 0xaa55) - return FALSE; - - return TRUE; -} - -static int -rhdAtomAnalyzeRomHdr(unsigned char *rombase, - ATOM_ROM_HEADER *hdr, - unsigned int *data_offset, - unsigned int *command_offset) -{ - if (!rhdAtomAnalyzeCommonHdr(&hdr->sHeader)) { - return FALSE; - } - xf86DrvMsg(-1,X_NONE,"\tSubsystemVendorID: 0x%4.4x SubsystemID: 0x%4.4x\n", - le16_to_cpu(hdr->usSubsystemVendorID),le16_to_cpu(hdr->usSubsystemID)); - xf86DrvMsg(-1,X_NONE,"\tIOBaseAddress: 0x%4.4x\n",le16_to_cpu(hdr->usIoBaseAddress)); - xf86DrvMsgVerb(-1,X_NONE,3,"\tFilename: %s\n",rombase + le16_to_cpu(hdr->usConfigFilenameOffset)); - xf86DrvMsgVerb(-1,X_NONE,3,"\tBIOS Bootup Message: %s\n", - rombase + le16_to_cpu(hdr->usBIOS_BootupMessageOffset)); - - *data_offset = le16_to_cpu(hdr->usMasterDataTableOffset); - *command_offset = le16_to_cpu(hdr->usMasterCommandTableOffset); - - return TRUE; -} - -static int -rhdAtomAnalyzeRomDataTable(unsigned char *base, uint16_t offset, - void *ptr,unsigned short *size) -{ - ATOM_COMMON_TABLE_HEADER *table = (ATOM_COMMON_TABLE_HEADER *) - (base + le16_to_cpu(offset)); - - if (!*size || !rhdAtomAnalyzeCommonHdr(table)) { - if (*size) *size -= 2; - *(void **)ptr = NULL; - return FALSE; - } - *size -= 2; - *(void **)ptr = (void *)(table); - return TRUE; -} - -Bool -rhdAtomGetTableRevisionAndSize(ATOM_COMMON_TABLE_HEADER *hdr, - uint8_t *contentRev, - uint8_t *formatRev, - unsigned short *size) -{ - if (!hdr) - return FALSE; - - if (contentRev) *contentRev = hdr->ucTableContentRevision; - if (formatRev) *formatRev = hdr->ucTableFormatRevision; - if (size) *size = (short)le16_to_cpu(hdr->usStructureSize) - - sizeof(ATOM_COMMON_TABLE_HEADER); - return TRUE; -} - -static Bool -rhdAtomAnalyzeMasterDataTable(unsigned char *base, - ATOM_MASTER_DATA_TABLE *table, - atomDataTablesPtr data) -{ - ATOM_MASTER_LIST_OF_DATA_TABLES *data_table = - &table->ListOfDataTables; - unsigned short size; - - if (!rhdAtomAnalyzeCommonHdr(&table->sHeader)) - return FALSE; - if (!rhdAtomGetTableRevisionAndSize(&table->sHeader,NULL,NULL, - &size)) - return FALSE; -# define SET_DATA_TABLE(x) {\ - rhdAtomAnalyzeRomDataTable(base,data_table->x,(void *)(&(data->x)),&size); \ - } - -# define SET_DATA_TABLE_VERS(x) {\ - rhdAtomAnalyzeRomDataTable(base,data_table->x,&(data->x.base),&size); \ - } - - SET_DATA_TABLE(UtilityPipeLine); - SET_DATA_TABLE(MultimediaCapabilityInfo); - SET_DATA_TABLE(MultimediaConfigInfo); - SET_DATA_TABLE(StandardVESA_Timing); - SET_DATA_TABLE_VERS(FirmwareInfo); - SET_DATA_TABLE(DAC_Info); - SET_DATA_TABLE_VERS(LVDS_Info); - SET_DATA_TABLE(TMDS_Info); - SET_DATA_TABLE_VERS(AnalogTV_Info); - SET_DATA_TABLE_VERS(SupportedDevicesInfo); - SET_DATA_TABLE(GPIO_I2C_Info); - SET_DATA_TABLE(VRAM_UsageByFirmware); - SET_DATA_TABLE(GPIO_Pin_LUT); - SET_DATA_TABLE(VESA_ToInternalModeLUT); - SET_DATA_TABLE_VERS(ComponentVideoInfo); - SET_DATA_TABLE(PowerPlayInfo); - SET_DATA_TABLE(CompassionateData); - SET_DATA_TABLE(SaveRestoreInfo); - SET_DATA_TABLE(PPLL_SS_Info); - SET_DATA_TABLE(OemInfo); - SET_DATA_TABLE(XTMDS_Info); - SET_DATA_TABLE(MclkSS_Info); - SET_DATA_TABLE(Object_Header); - SET_DATA_TABLE(IndirectIOAccess); - SET_DATA_TABLE(MC_InitParameter); - SET_DATA_TABLE(ASIC_VDDC_Info); - SET_DATA_TABLE(ASIC_InternalSS_Info); - SET_DATA_TABLE(TV_VideoMode); - SET_DATA_TABLE_VERS(VRAM_Info); - SET_DATA_TABLE(MemoryTrainingInfo); - SET_DATA_TABLE_VERS(IntegratedSystemInfo); - SET_DATA_TABLE(ASIC_ProfilingInfo); - SET_DATA_TABLE(VoltageObjectInfo); - SET_DATA_TABLE(PowerSourceInfo); -# undef SET_DATA_TABLE - - return TRUE; -} - -static Bool -rhdAtomGetDataTable(int scrnIndex, - unsigned char *base, - atomDataTables *atomDataPtr, - unsigned int *cmd_offset, - unsigned int BIOSImageSize) -{ - unsigned int data_offset; - unsigned int atom_romhdr_off = le16_to_cpu(*(unsigned short*) - (base + OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER)); - ATOM_ROM_HEADER *atom_rom_hdr = - (ATOM_ROM_HEADER *)(base + atom_romhdr_off); - - //RHDFUNCI(scrnIndex); - - if (atom_romhdr_off + sizeof(ATOM_ROM_HEADER) > BIOSImageSize) { - xf86DrvMsg(scrnIndex,X_ERROR, - "%s: AtomROM header extends beyond BIOS image\n",__func__); - return FALSE; - } - - if (memcmp("ATOM",&atom_rom_hdr->uaFirmWareSignature,4)) { - xf86DrvMsg(scrnIndex,X_ERROR,"%s: No AtomBios signature found\n", - __func__); - return FALSE; - } - xf86DrvMsg(scrnIndex, X_INFO, "ATOM BIOS Rom: \n"); - if (!rhdAtomAnalyzeRomHdr(base, atom_rom_hdr, &data_offset, cmd_offset)) { - xf86DrvMsg(scrnIndex, X_ERROR, "RomHeader invalid\n"); - return FALSE; - } - - if (data_offset + sizeof (ATOM_MASTER_DATA_TABLE) > BIOSImageSize) { - xf86DrvMsg(scrnIndex,X_ERROR,"%s: Atom data table outside of BIOS\n", - __func__); - } - - if (*cmd_offset + sizeof (ATOM_MASTER_COMMAND_TABLE) > BIOSImageSize) { - xf86DrvMsg(scrnIndex,X_ERROR,"%s: Atom command table outside of BIOS\n", - __func__); - } - - if (!rhdAtomAnalyzeMasterDataTable(base, (ATOM_MASTER_DATA_TABLE *) - (base + data_offset), - atomDataPtr)) { - xf86DrvMsg(scrnIndex, X_ERROR, "%s: ROM Master Table invalid\n", - __func__); - return FALSE; - } - return TRUE; -} - -static Bool -rhdAtomGetFbBaseAndSize(atomBiosHandlePtr handle, unsigned int *base, - unsigned int *size) -{ - AtomBiosArgRec data; - if (RHDAtomBiosFunc(handle->pScrn, handle, GET_FW_FB_SIZE, &data) - == ATOM_SUCCESS) { - if (data.val == 0) { - xf86DrvMsg(handle->pScrn->scrnIndex, X_WARNING, "%s: AtomBIOS specified VRAM " - "scratch space size invalid\n", __func__); - return FALSE; - } - if (size) - *size = (int)data.val; - } else - return FALSE; - if (RHDAtomBiosFunc(handle->pScrn, handle, GET_FW_FB_START, &data) - == ATOM_SUCCESS) { - if (data.val == 0) - return FALSE; - if (base) - *base = (int)data.val; - } - return TRUE; -} - -/* - * Uses videoRam form ScrnInfoRec. - */ -static AtomBiosResult -rhdAtomAllocateFbScratch(atomBiosHandlePtr handle, - AtomBiosRequestID func, AtomBiosArgPtr data) -{ - unsigned int fb_base = 0; - unsigned int fb_size = 0; - unsigned int start = data->fb.start; - unsigned int size = data->fb.size; - handle->scratchBase = NULL; - handle->fbBase = 0; - - if (rhdAtomGetFbBaseAndSize(handle, &fb_base, &fb_size)) { - xf86DrvMsg(handle->pScrn->scrnIndex, X_INFO, "AtomBIOS requests %ikB" - " of VRAM scratch space\n",fb_size); - fb_size *= 1024; /* convert to bytes */ - xf86DrvMsg(handle->pScrn->scrnIndex, X_INFO, "AtomBIOS VRAM scratch base: 0x%x\n", - fb_base); - } else { - fb_size = 20 * 1024; - xf86DrvMsg(handle->pScrn->scrnIndex, X_INFO, " default to: %i\n",fb_size); - } - if (fb_base && fb_size && size) { - /* 4k align */ - fb_size = (fb_size & ~(uint32_t)0xfff) + ((fb_size & 0xfff) ? 1 : 0); - if ((fb_base + fb_size) > (start + size)) { - xf86DrvMsg(handle->pScrn->scrnIndex, X_WARNING, - "%s: FW FB scratch area %i (size: %i)" - " extends beyond available framebuffer size %i\n", - __func__, fb_base, fb_size, size); - } else if ((fb_base + fb_size) < (start + size)) { - xf86DrvMsg(handle->pScrn->scrnIndex, X_WARNING, - "%s: FW FB scratch area not located " - "at the end of VRAM. Scratch End: " - "0x%x VRAM End: 0x%x\n", __func__, - (unsigned int)(fb_base + fb_size), - size); - } else if (fb_base < start) { - xf86DrvMsg(handle->pScrn->scrnIndex, X_WARNING, - "%s: FW FB scratch area extends below " - "the base of the free VRAM: 0x%x Base: 0x%x\n", - __func__, (unsigned int)(fb_base), start); - } else { - size -= fb_size; - handle->fbBase = fb_base; - return ATOM_SUCCESS; - } - } - - if (!handle->fbBase) { - xf86DrvMsg(handle->pScrn->scrnIndex, X_INFO, - "Cannot get VRAM scratch space. " - "Allocating in main memory instead\n"); - handle->scratchBase = calloc(fb_size,1); - return ATOM_SUCCESS; - } - return ATOM_FAILED; -} - -# ifdef ATOM_BIOS_PARSER -Bool -rhdAtomASICInit(atomBiosHandlePtr handle) -{ - ASIC_INIT_PS_ALLOCATION asicInit; - AtomBiosArgRec data; - - RHDAtomBiosFunc(handle->pScrn, handle, - GET_DEFAULT_ENGINE_CLOCK, - &data); - asicInit.sASICInitClocks.ulDefaultEngineClock = cpu_to_le32(data.val / 10);/*in 10 Khz*/ - RHDAtomBiosFunc(handle->pScrn, handle, - GET_DEFAULT_MEMORY_CLOCK, - &data); - asicInit.sASICInitClocks.ulDefaultMemoryClock = cpu_to_le32(data.val / 10);/*in 10 Khz*/ - data.exec.dataSpace = NULL; - data.exec.index = 0x0; - data.exec.pspace = &asicInit; - xf86DrvMsg(handle->pScrn->scrnIndex, X_INFO, "Calling ASIC Init\n"); - if (RHDAtomBiosFunc(handle->pScrn, handle, - ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { - xf86DrvMsg(handle->pScrn->scrnIndex, X_INFO, "ASIC_INIT Successful\n"); - return TRUE; - } - xf86DrvMsg(handle->pScrn->scrnIndex, X_INFO, "ASIC_INIT Failed\n"); - return FALSE; -} - -int -atombios_clk_gating_setup(ScrnInfoPtr pScrn, Bool enable) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - DYNAMIC_CLOCK_GATING_PS_ALLOCATION dynclk_data; - AtomBiosArgRec data; - unsigned char *space; - - dynclk_data.ucEnable = enable; - - data.exec.index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating); - data.exec.dataSpace = (void *)&space; - data.exec.pspace = &dynclk_data; - - if (RHDAtomBiosFunc(info->atomBIOS->pScrn, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { - ErrorF("Dynamic clock gating %s success\n", enable? "enable" : "disable"); - return ATOM_SUCCESS; - } - - ErrorF("Dynamic clock gating %s failure\n", enable? "enable" : "disable"); - return ATOM_NOT_IMPLEMENTED; - -} - -int -atombios_static_pwrmgt_setup(ScrnInfoPtr pScrn, Bool enable) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION pwrmgt_data; - AtomBiosArgRec data; - unsigned char *space; - - /* disabling static power management causes hangs on some r4xx chips */ - if (((info->ChipFamily == CHIP_FAMILY_R420) || - (info->ChipFamily == CHIP_FAMILY_RV410)) && - !enable) - return ATOM_NOT_IMPLEMENTED; - - pwrmgt_data.ucEnable = enable; - - data.exec.index = GetIndexIntoMasterTable(COMMAND, EnableASIC_StaticPwrMgt); - data.exec.dataSpace = (void *)&space; - data.exec.pspace = &pwrmgt_data; - - if (RHDAtomBiosFunc(info->atomBIOS->pScrn, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { - ErrorF("Static power management %s success\n", enable? "enable" : "disable"); - return ATOM_SUCCESS; - } - - ErrorF("Static power management %s failure\n", enable? "enable" : "disable"); - return ATOM_NOT_IMPLEMENTED; - -} - -int -atombios_set_engine_clock(ScrnInfoPtr pScrn, uint32_t engclock) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - SET_ENGINE_CLOCK_PS_ALLOCATION eng_clock_ps; - AtomBiosArgRec data; - unsigned char *space; - - RADEONWaitForIdleMMIO(pScrn); - - eng_clock_ps.ulTargetEngineClock = engclock; /* 10 khz */ - - /*ErrorF("Attempting to set engine clock to: %d\n", engclock);*/ - data.exec.index = GetIndexIntoMasterTable(COMMAND, SetEngineClock); - data.exec.dataSpace = (void *)&space; - data.exec.pspace = &eng_clock_ps; - - if (RHDAtomBiosFunc(info->atomBIOS->pScrn, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { - /* ErrorF("Set engine clock success\n"); */ - return ATOM_SUCCESS; - } - /* ErrorF("Set engine clock failed\n"); */ - return ATOM_NOT_IMPLEMENTED; -} - -int -atombios_set_memory_clock(ScrnInfoPtr pScrn, uint32_t memclock) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - SET_MEMORY_CLOCK_PS_ALLOCATION mem_clock_ps; - AtomBiosArgRec data; - unsigned char *space; - - if (info->IsIGP) - return ATOM_SUCCESS; - - RADEONWaitForIdleMMIO(pScrn); - - mem_clock_ps.ulTargetMemoryClock = memclock; /* 10 khz */ - - /* ErrorF("Attempting to set mem clock to: %d\n", memclock); */ - data.exec.index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock); - data.exec.dataSpace = (void *)&space; - data.exec.pspace = &mem_clock_ps; - - if (RHDAtomBiosFunc(info->atomBIOS->pScrn, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { - /* ErrorF("Set memory clock success\n"); */ - return ATOM_SUCCESS; - } - /* ErrorF("Set memory clock failed\n"); */ - return ATOM_NOT_IMPLEMENTED; -} - -# endif - -static AtomBiosResult -rhdAtomInit(atomBiosHandlePtr unused1, AtomBiosRequestID unused2, - AtomBiosArgPtr data) -{ - ScrnInfoPtr pScrn = data->pScrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - atomDataTablesPtr atomDataPtr; - unsigned int cmd_offset; - atomBiosHandlePtr handle = NULL; - unsigned int BIOSImageSize = 0; - data->atomhandle = NULL; - -#ifdef XSERVER_LIBPCIACCESS - BIOSImageSize = info->PciInfo->rom_size > RADEON_VBIOS_SIZE ? info->PciInfo->rom_size : RADEON_VBIOS_SIZE; -#else - BIOSImageSize = RADEON_VBIOS_SIZE; -#endif - - if (!(atomDataPtr = calloc(1, sizeof(atomDataTables)))) { - xf86DrvMsg(pScrn->scrnIndex,X_ERROR,"Cannot allocate memory for " - "ATOM BIOS data tabes\n"); - goto error; - } - if (!rhdAtomGetDataTable(pScrn->scrnIndex, info->VBIOS, atomDataPtr, &cmd_offset, BIOSImageSize)) - goto error1; - if (!(handle = calloc(1, sizeof(atomBiosHandleRec)))) { - xf86DrvMsg(pScrn->scrnIndex,X_ERROR,"Cannot allocate memory\n"); - goto error1; - } - handle->BIOSBase = info->VBIOS; - handle->atomDataPtr = atomDataPtr; - handle->cmd_offset = cmd_offset; - handle->pScrn = pScrn; -#if XSERVER_LIBPCIACCESS - handle->device = info->PciInfo; -#else - handle->PciTag = info->PciTag; -#endif - handle->BIOSImageSize = BIOSImageSize; - - data->atomhandle = handle; - return ATOM_SUCCESS; - - error1: - free(atomDataPtr); - error: - return ATOM_FAILED; -} - -static AtomBiosResult -rhdAtomTearDown(atomBiosHandlePtr handle, - AtomBiosRequestID unused1, AtomBiosArgPtr unused2) -{ - //RHDFUNC(handle); - - free(handle->BIOSBase); - free(handle->atomDataPtr); - if (handle->scratchBase) free(handle->scratchBase); - free(handle); - return ATOM_SUCCESS; -} - -static AtomBiosResult -rhdAtomVramInfoQuery(atomBiosHandlePtr handle, AtomBiosRequestID func, - AtomBiosArgPtr data) -{ - atomDataTablesPtr atomDataPtr; - uint32_t *val = &data->val; - //RHDFUNC(handle); - - atomDataPtr = handle->atomDataPtr; - - switch (func) { - case GET_FW_FB_START: - if (atomDataPtr->VRAM_UsageByFirmware) - *val = le32_to_cpu(atomDataPtr->VRAM_UsageByFirmware - ->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware); - else - return ATOM_NOT_IMPLEMENTED; - break; - case GET_FW_FB_SIZE: - if (atomDataPtr->VRAM_UsageByFirmware) - *val = le16_to_cpu(atomDataPtr->VRAM_UsageByFirmware - ->asFirmwareVramReserveInfo[0].usFirmwareUseInKb); - else - return ATOM_NOT_IMPLEMENTED; - break; - default: - return ATOM_NOT_IMPLEMENTED; - } - return ATOM_SUCCESS; -} - -static AtomBiosResult -rhdAtomTmdsInfoQuery(atomBiosHandlePtr handle, - AtomBiosRequestID func, AtomBiosArgPtr data) -{ - atomDataTablesPtr atomDataPtr; - uint32_t *val = &data->val; - int idx = *val; - - atomDataPtr = handle->atomDataPtr; - if (!rhdAtomGetTableRevisionAndSize( - (ATOM_COMMON_TABLE_HEADER *)(atomDataPtr->TMDS_Info), - NULL,NULL,NULL)) { - return ATOM_FAILED; - } - - //RHDFUNC(handle); - - switch (func) { - case ATOM_TMDS_FREQUENCY: - *val = le16_to_cpu(atomDataPtr->TMDS_Info->asMiscInfo[idx].usFrequency); - break; - case ATOM_TMDS_PLL_CHARGE_PUMP: - *val = atomDataPtr->TMDS_Info->asMiscInfo[idx].ucPLL_ChargePump; - break; - case ATOM_TMDS_PLL_DUTY_CYCLE: - *val = atomDataPtr->TMDS_Info->asMiscInfo[idx].ucPLL_DutyCycle; - break; - case ATOM_TMDS_PLL_VCO_GAIN: - *val = atomDataPtr->TMDS_Info->asMiscInfo[idx].ucPLL_VCO_Gain; - break; - case ATOM_TMDS_PLL_VOLTAGE_SWING: - *val = atomDataPtr->TMDS_Info->asMiscInfo[idx].ucPLL_VoltageSwing; - break; - default: - return ATOM_NOT_IMPLEMENTED; - } - return ATOM_SUCCESS; -} - -static DisplayModePtr -rhdAtomDTDTimings(atomBiosHandlePtr handle, ATOM_DTD_FORMAT *dtd) -{ - DisplayModePtr mode; -#define NAME_LEN 16 - char name[NAME_LEN]; - - //RHDFUNC(handle); - - if (!dtd->usHActive || !dtd->usVActive) - return NULL; - - if (!(mode = (DisplayModePtr)calloc(1,sizeof(DisplayModeRec)))) - return NULL; - - mode->CrtcHDisplay = mode->HDisplay = le16_to_cpu(dtd->usHActive); - mode->CrtcVDisplay = mode->VDisplay = le16_to_cpu(dtd->usVActive); - mode->CrtcHBlankStart = le16_to_cpu(dtd->usHActive) + dtd->ucHBorder; - mode->CrtcHBlankEnd = mode->CrtcHBlankStart + le16_to_cpu(dtd->usHBlanking_Time); - mode->CrtcHTotal = mode->HTotal = mode->CrtcHBlankEnd + dtd->ucHBorder; - mode->CrtcVBlankStart = le16_to_cpu(dtd->usVActive) + dtd->ucVBorder; - mode->CrtcVBlankEnd = mode->CrtcVBlankStart + le16_to_cpu(dtd->usVBlanking_Time); - mode->CrtcVTotal = mode->VTotal = mode->CrtcVBlankEnd + dtd->ucVBorder; - mode->CrtcHSyncStart = mode->HSyncStart = le16_to_cpu(dtd->usHActive) + le16_to_cpu(dtd->usHSyncOffset); - mode->CrtcHSyncEnd = mode->HSyncEnd = mode->HSyncStart + le16_to_cpu(dtd->usHSyncWidth); - mode->CrtcVSyncStart = mode->VSyncStart = le16_to_cpu(dtd->usVActive) + le16_to_cpu(dtd->usVSyncOffset); - mode->CrtcVSyncEnd = mode->VSyncEnd = mode->VSyncStart + le16_to_cpu(dtd->usVSyncWidth); - - mode->SynthClock = mode->Clock = le16_to_cpu(dtd->usPixClk) * 10; - - mode->HSync = ((float) mode->Clock) / ((float)mode->HTotal); - mode->VRefresh = (1000.0 * ((float) mode->Clock)) - / ((float)(((float)mode->HTotal) * ((float)mode->VTotal))); - - if (dtd->susModeMiscInfo.sbfAccess.CompositeSync) - mode->Flags |= V_CSYNC; - if (dtd->susModeMiscInfo.sbfAccess.Interlace) - mode->Flags |= V_INTERLACE; - if (dtd->susModeMiscInfo.sbfAccess.DoubleClock) - mode->Flags |= V_DBLSCAN; - if (dtd->susModeMiscInfo.sbfAccess.VSyncPolarity) - mode->Flags |= V_NVSYNC; - if (dtd->susModeMiscInfo.sbfAccess.HSyncPolarity) - mode->Flags |= V_NHSYNC; - - snprintf(name, NAME_LEN, "%dx%d", - mode->HDisplay, mode->VDisplay); - mode->name = xstrdup(name); - - ErrorF("DTD Modeline: %s " - "%2.d %i (%i) %i %i (%i) %i %i (%i) %i %i (%i) %i flags: 0x%x\n", - mode->name, mode->Clock, - mode->HDisplay, mode->CrtcHBlankStart, mode->HSyncStart, mode->CrtcHSyncEnd, - mode->CrtcHBlankEnd, mode->HTotal, - mode->VDisplay, mode->CrtcVBlankStart, mode->VSyncStart, mode->VSyncEnd, - mode->CrtcVBlankEnd, mode->VTotal, mode->Flags); - - return mode; -} - -static unsigned char* -rhdAtomLvdsDDC(atomBiosHandlePtr handle, uint32_t offset, unsigned char *record) -{ - unsigned char *EDIDBlock; - - //RHDFUNC(handle); - - while (*record != ATOM_RECORD_END_TYPE) { - - switch (*record) { - case LCD_MODE_PATCH_RECORD_MODE_TYPE: - offset += sizeof(ATOM_PATCH_RECORD_MODE); - if (offset > handle->BIOSImageSize) break; - record += sizeof(ATOM_PATCH_RECORD_MODE); - break; - - case LCD_RTS_RECORD_TYPE: - offset += sizeof(ATOM_LCD_RTS_RECORD); - if (offset > handle->BIOSImageSize) break; - record += sizeof(ATOM_LCD_RTS_RECORD); - break; - - case LCD_CAP_RECORD_TYPE: - offset += sizeof(ATOM_LCD_MODE_CONTROL_CAP); - if (offset > handle->BIOSImageSize) break; - record += sizeof(ATOM_LCD_MODE_CONTROL_CAP); - break; - - case LCD_FAKE_EDID_PATCH_RECORD_TYPE: - offset += sizeof(ATOM_FAKE_EDID_PATCH_RECORD); - /* check if the structure still fully lives in the BIOS image */ - if (offset > handle->BIOSImageSize) break; - offset += ((ATOM_FAKE_EDID_PATCH_RECORD*)record)->ucFakeEDIDLength - - sizeof(UCHAR); - if (offset > handle->BIOSImageSize) break; - /* dup string as we free it later */ - if (!(EDIDBlock = (unsigned char *)malloc( - ((ATOM_FAKE_EDID_PATCH_RECORD*)record)->ucFakeEDIDLength))) - return NULL; - memcpy(EDIDBlock,&((ATOM_FAKE_EDID_PATCH_RECORD*)record)->ucFakeEDIDString, - ((ATOM_FAKE_EDID_PATCH_RECORD*)record)->ucFakeEDIDLength); - - /* for testing */ - { - xf86MonPtr mon = xf86InterpretEDID(handle->pScrn->scrnIndex,EDIDBlock); - xf86PrintEDID(mon); - free(mon); - } - return EDIDBlock; - - case LCD_PANEL_RESOLUTION_RECORD_TYPE: - offset += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD); - if (offset > handle->BIOSImageSize) break; - record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD); - break; - - default: - xf86DrvMsg(handle->pScrn->scrnIndex, X_ERROR, - "%s: unknown record type: %x\n",__func__,*record); - return NULL; - } - } - - return NULL; -} - -static AtomBiosResult -rhdAtomCVGetTimings(atomBiosHandlePtr handle, AtomBiosRequestID func, - AtomBiosArgPtr data) -{ - atomDataTablesPtr atomDataPtr; - uint8_t crev, frev; - DisplayModePtr last = NULL; - DisplayModePtr new = NULL; - DisplayModePtr first = NULL; - int i; - uint16_t size; - - data->modes = NULL; - - atomDataPtr = handle->atomDataPtr; - - if (!rhdAtomGetTableRevisionAndSize( - (ATOM_COMMON_TABLE_HEADER *)(atomDataPtr->ComponentVideoInfo.base), - &crev,&frev,&size)) { - return ATOM_FAILED; - } - - switch (frev) { - case 1: - switch (func) { - case ATOMBIOS_GET_CV_MODES: - for (i = 0; i < MAX_SUPPORTED_CV_STANDARDS; i++) { - new = rhdAtomDTDTimings(handle, - &atomDataPtr->ComponentVideoInfo - .ComponentVideoInfo->aModeTimings[i]); - - if (!new) - continue; - - new->type |= M_T_DRIVER; - new->next = NULL; - new->prev = last; - - if (last) last->next = new; - last = new; - if (!first) first = new; - } - if (last) { - last->next = NULL; //first; - first->prev = NULL; //last; - data->modes = first; - } - if (data->modes) - return ATOM_SUCCESS; - default: - return ATOM_FAILED; - } - case 2: - switch (func) { - case ATOMBIOS_GET_CV_MODES: - for (i = 0; i < MAX_SUPPORTED_CV_STANDARDS; i++) { - /* my rv730 table has only room for one mode */ - if ((void *)&atomDataPtr->ComponentVideoInfo.ComponentVideoInfo_v21->aModeTimings[i] - - atomDataPtr->ComponentVideoInfo.base > size) - break; - - new = rhdAtomDTDTimings(handle, - &atomDataPtr->ComponentVideoInfo - .ComponentVideoInfo_v21->aModeTimings[i]); - - if (!new) - continue; - - new->type |= M_T_DRIVER; - new->next = NULL; - new->prev = last; - - if (last) last->next = new; - last = new; - if (!first) first = new; - - } - if (last) { - last->next = NULL; //first; - first->prev = NULL; //last; - data->modes = first; - } - if (data->modes) - return ATOM_SUCCESS; - return ATOM_FAILED; - - default: - return ATOM_FAILED; - } - default: - return ATOM_NOT_IMPLEMENTED; - } -/*NOTREACHED*/ -} - -static AtomBiosResult -rhdAtomLvdsGetTimings(atomBiosHandlePtr handle, AtomBiosRequestID func, - AtomBiosArgPtr data) -{ - atomDataTablesPtr atomDataPtr; - uint8_t crev, frev; - unsigned long offset; - - //RHDFUNC(handle); - - atomDataPtr = handle->atomDataPtr; - - if (!rhdAtomGetTableRevisionAndSize( - (ATOM_COMMON_TABLE_HEADER *)(atomDataPtr->LVDS_Info.base), - &frev,&crev,NULL)) { - return ATOM_FAILED; - } - - switch (crev) { - - case 1: - switch (func) { - case ATOMBIOS_GET_PANEL_MODE: - data->modes = rhdAtomDTDTimings(handle, - &atomDataPtr->LVDS_Info - .LVDS_Info->sLCDTiming); - if (data->modes) - return ATOM_SUCCESS; - default: - return ATOM_FAILED; - } - case 2: - switch (func) { - case ATOMBIOS_GET_PANEL_MODE: - data->modes = rhdAtomDTDTimings(handle, - &atomDataPtr->LVDS_Info - .LVDS_Info_v12->sLCDTiming); - if (data->modes) - return ATOM_SUCCESS; - return ATOM_FAILED; - - case ATOMBIOS_GET_PANEL_EDID: - offset = (unsigned long)&atomDataPtr->LVDS_Info.base - - (unsigned long)handle->BIOSBase - + le16_to_cpu(atomDataPtr->LVDS_Info - .LVDS_Info_v12->usExtInfoTableOffset); - - data->EDIDBlock - = rhdAtomLvdsDDC(handle, offset, - (unsigned char *) - &atomDataPtr->LVDS_Info.base - + le16_to_cpu(atomDataPtr->LVDS_Info - .LVDS_Info_v12->usExtInfoTableOffset)); - if (data->EDIDBlock) - return ATOM_SUCCESS; - default: - return ATOM_FAILED; - } - default: - return ATOM_NOT_IMPLEMENTED; - } -/*NOTREACHED*/ -} - -static AtomBiosResult -rhdAtomLvdsInfoQuery(atomBiosHandlePtr handle, - AtomBiosRequestID func, AtomBiosArgPtr data) -{ - atomDataTablesPtr atomDataPtr; - uint8_t crev, frev; - uint32_t *val = &data->val; - - //RHDFUNC(handle); - - atomDataPtr = handle->atomDataPtr; - - if (!rhdAtomGetTableRevisionAndSize( - (ATOM_COMMON_TABLE_HEADER *)(atomDataPtr->LVDS_Info.base), - &frev,&crev,NULL)) { - return ATOM_FAILED; - } - - switch (crev) { - case 1: - switch (func) { - case ATOM_LVDS_SUPPORTED_REFRESH_RATE: - *val = le16_to_cpu(atomDataPtr->LVDS_Info - .LVDS_Info->usSupportedRefreshRate); - break; - case ATOM_LVDS_OFF_DELAY: - *val = le16_to_cpu(atomDataPtr->LVDS_Info - .LVDS_Info->usOffDelayInMs); - break; - case ATOM_LVDS_SEQ_DIG_ONTO_DE: - *val = atomDataPtr->LVDS_Info - .LVDS_Info->ucPowerSequenceDigOntoDEin10Ms * 10; - break; - case ATOM_LVDS_SEQ_DE_TO_BL: - *val = atomDataPtr->LVDS_Info - .LVDS_Info->ucPowerSequenceDEtoBLOnin10Ms * 10; - break; - case ATOM_LVDS_DITHER: - *val = atomDataPtr->LVDS_Info - .LVDS_Info->ucLVDS_Misc & 0x40; - break; - case ATOM_LVDS_DUALLINK: - *val = atomDataPtr->LVDS_Info - .LVDS_Info->ucLVDS_Misc & 0x01; - break; - case ATOM_LVDS_24BIT: - *val = atomDataPtr->LVDS_Info - .LVDS_Info->ucLVDS_Misc & 0x02; - break; - case ATOM_LVDS_GREYLVL: - *val = atomDataPtr->LVDS_Info - .LVDS_Info->ucLVDS_Misc & 0x0C; - break; - case ATOM_LVDS_FPDI: - *val = atomDataPtr->LVDS_Info - .LVDS_Info->ucLVDS_Misc * 0x10; - break; - default: - return ATOM_NOT_IMPLEMENTED; - } - break; - case 2: - switch (func) { - case ATOM_LVDS_SUPPORTED_REFRESH_RATE: - *val = le16_to_cpu(atomDataPtr->LVDS_Info - .LVDS_Info_v12->usSupportedRefreshRate); - break; - case ATOM_LVDS_OFF_DELAY: - *val = le16_to_cpu(atomDataPtr->LVDS_Info - .LVDS_Info_v12->usOffDelayInMs); - break; - case ATOM_LVDS_SEQ_DIG_ONTO_DE: - *val = atomDataPtr->LVDS_Info - .LVDS_Info_v12->ucPowerSequenceDigOntoDEin10Ms * 10; - break; - case ATOM_LVDS_SEQ_DE_TO_BL: - *val = atomDataPtr->LVDS_Info - .LVDS_Info_v12->ucPowerSequenceDEtoBLOnin10Ms * 10; - break; - case ATOM_LVDS_DITHER: - *val = atomDataPtr->LVDS_Info - .LVDS_Info_v12->ucLVDS_Misc & 0x40; - break; - case ATOM_LVDS_DUALLINK: - *val = atomDataPtr->LVDS_Info - .LVDS_Info_v12->ucLVDS_Misc & 0x01; - break; - case ATOM_LVDS_24BIT: - *val = atomDataPtr->LVDS_Info - .LVDS_Info_v12->ucLVDS_Misc & 0x02; - break; - case ATOM_LVDS_GREYLVL: - *val = atomDataPtr->LVDS_Info - .LVDS_Info_v12->ucLVDS_Misc & 0x0C; - break; - case ATOM_LVDS_FPDI: - *val = atomDataPtr->LVDS_Info - .LVDS_Info_v12->ucLVDS_Misc * 0x10; - break; - default: - return ATOM_NOT_IMPLEMENTED; - } - break; - default: - return ATOM_NOT_IMPLEMENTED; - } - - return ATOM_SUCCESS; -} - -static AtomBiosResult -rhdAtomCompassionateDataQuery(atomBiosHandlePtr handle, - AtomBiosRequestID func, AtomBiosArgPtr data) -{ - atomDataTablesPtr atomDataPtr; - uint8_t crev, frev; - uint32_t *val = &data->val; - - //RHDFUNC(handle); - - atomDataPtr = handle->atomDataPtr; - - if (!rhdAtomGetTableRevisionAndSize( - (ATOM_COMMON_TABLE_HEADER *)(atomDataPtr->CompassionateData), - &frev,&crev,NULL)) { - return ATOM_FAILED; - } - - switch (func) { - case ATOM_DAC1_BG_ADJ: - *val = atomDataPtr->CompassionateData-> - ucDAC1_BG_Adjustment; - break; - case ATOM_DAC1_DAC_ADJ: - *val = atomDataPtr->CompassionateData-> - ucDAC1_DAC_Adjustment; - break; - case ATOM_DAC1_FORCE: - *val = atomDataPtr->CompassionateData-> - usDAC1_FORCE_Data; - break; - case ATOM_DAC2_CRTC2_BG_ADJ: - *val = atomDataPtr->CompassionateData-> - ucDAC2_CRT2_BG_Adjustment; - break; - case ATOM_DAC2_CRTC2_DAC_ADJ: - *val = atomDataPtr->CompassionateData-> - ucDAC2_CRT2_DAC_Adjustment; - break; - case ATOM_DAC2_CRTC2_FORCE: - *val = atomDataPtr->CompassionateData-> - usDAC2_CRT2_FORCE_Data; - break; - case ATOM_DAC2_CRTC2_MUX_REG_IND: - *val = atomDataPtr->CompassionateData-> - usDAC2_CRT2_MUX_RegisterIndex; - break; - case ATOM_DAC2_CRTC2_MUX_REG_INFO: - *val = atomDataPtr->CompassionateData-> - ucDAC2_CRT2_MUX_RegisterInfo; - break; - default: - return ATOM_NOT_IMPLEMENTED; - } - return ATOM_SUCCESS; -} - -static AtomBiosResult -rhdAtomGPIOI2CInfoQuery(atomBiosHandlePtr handle, - AtomBiosRequestID func, AtomBiosArgPtr data) -{ - atomDataTablesPtr atomDataPtr; - uint8_t crev, frev; - uint32_t *val = &data->val; - unsigned short size; - - //RHDFUNC(handle); - - atomDataPtr = handle->atomDataPtr; - - if (!rhdAtomGetTableRevisionAndSize( - (ATOM_COMMON_TABLE_HEADER *)(atomDataPtr->GPIO_I2C_Info), - &frev,&crev,&size)) { - return ATOM_FAILED; - } - - switch (func) { - case ATOM_GPIO_I2C_CLK_MASK: - if ((sizeof(ATOM_COMMON_TABLE_HEADER) - + (*val * sizeof(ATOM_GPIO_I2C_ASSIGMENT))) > size) { - xf86DrvMsg(handle->pScrn->scrnIndex, X_ERROR, "%s: GPIO_I2C Device " - "num %lu exeeds table size %u\n",__func__, - (unsigned long)val, - size); - return ATOM_FAILED; - } - - *val = le16_to_cpu(atomDataPtr->GPIO_I2C_Info->asGPIO_Info[*val] - .usClkMaskRegisterIndex); - break; - - default: - return ATOM_NOT_IMPLEMENTED; - } - return ATOM_SUCCESS; -} - -static AtomBiosResult -rhdAtomFirmwareInfoQuery(atomBiosHandlePtr handle, - AtomBiosRequestID func, AtomBiosArgPtr data) -{ - atomDataTablesPtr atomDataPtr; - uint8_t crev, frev; - uint32_t *val = &data->val; - - //RHDFUNC(handle); - - atomDataPtr = handle->atomDataPtr; - - if (!rhdAtomGetTableRevisionAndSize( - (ATOM_COMMON_TABLE_HEADER *)(atomDataPtr->FirmwareInfo.base), - &crev,&frev,NULL)) { - return ATOM_FAILED; - } - - switch (crev) { - case 1: - switch (func) { - case GET_DEFAULT_ENGINE_CLOCK: - *val = le32_to_cpu(atomDataPtr->FirmwareInfo - .FirmwareInfo->ulDefaultEngineClock) * 10; - break; - case GET_DEFAULT_MEMORY_CLOCK: - *val = le32_to_cpu(atomDataPtr->FirmwareInfo - .FirmwareInfo->ulDefaultMemoryClock) * 10; - break; - case GET_MAX_PIXEL_CLOCK_PLL_OUTPUT: - *val = le32_to_cpu(atomDataPtr->FirmwareInfo - .FirmwareInfo->ulMaxPixelClockPLL_Output) * 10; - break; - case GET_MIN_PIXEL_CLOCK_PLL_OUTPUT: - *val = le16_to_cpu(atomDataPtr->FirmwareInfo - .FirmwareInfo->usMinPixelClockPLL_Output) * 10; - case GET_MAX_PIXEL_CLOCK_PLL_INPUT: - *val = le16_to_cpu(atomDataPtr->FirmwareInfo - .FirmwareInfo->usMaxPixelClockPLL_Input) * 10; - break; - case GET_MIN_PIXEL_CLOCK_PLL_INPUT: - *val = le16_to_cpu(atomDataPtr->FirmwareInfo - .FirmwareInfo->usMinPixelClockPLL_Input) * 10; - break; - case GET_MAX_PIXEL_CLK: - *val = le16_to_cpu(atomDataPtr->FirmwareInfo - .FirmwareInfo->usMaxPixelClock) * 10; - break; - case GET_REF_CLOCK: - *val = le16_to_cpu(atomDataPtr->FirmwareInfo - .FirmwareInfo->usReferenceClock) * 10; - break; - default: - return ATOM_NOT_IMPLEMENTED; - } - case 2: - switch (func) { - case GET_DEFAULT_ENGINE_CLOCK: - *val = le32_to_cpu(atomDataPtr->FirmwareInfo - .FirmwareInfo_V_1_2->ulDefaultEngineClock) * 10; - break; - case GET_DEFAULT_MEMORY_CLOCK: - *val = le32_to_cpu(atomDataPtr->FirmwareInfo - .FirmwareInfo_V_1_2->ulDefaultMemoryClock) * 10; - break; - case GET_MAX_PIXEL_CLOCK_PLL_OUTPUT: - *val = le32_to_cpu(atomDataPtr->FirmwareInfo - .FirmwareInfo_V_1_2->ulMaxPixelClockPLL_Output) * 10; - break; - case GET_MIN_PIXEL_CLOCK_PLL_OUTPUT: - *val = le16_to_cpu(atomDataPtr->FirmwareInfo - .FirmwareInfo_V_1_2->usMinPixelClockPLL_Output) * 10; - break; - case GET_MAX_PIXEL_CLOCK_PLL_INPUT: - *val = le16_to_cpu(atomDataPtr->FirmwareInfo - .FirmwareInfo_V_1_2->usMaxPixelClockPLL_Input) * 10; - break; - case GET_MIN_PIXEL_CLOCK_PLL_INPUT: - *val = le16_to_cpu(atomDataPtr->FirmwareInfo - .FirmwareInfo_V_1_2->usMinPixelClockPLL_Input) * 10; - break; - case GET_MAX_PIXEL_CLK: - *val = le16_to_cpu(atomDataPtr->FirmwareInfo - .FirmwareInfo_V_1_2->usMaxPixelClock) * 10; - break; - case GET_REF_CLOCK: - *val = le16_to_cpu(atomDataPtr->FirmwareInfo - .FirmwareInfo_V_1_2->usReferenceClock) * 10; - break; - default: - return ATOM_NOT_IMPLEMENTED; - } - break; - case 3: - switch (func) { - case GET_DEFAULT_ENGINE_CLOCK: - *val = le32_to_cpu(atomDataPtr->FirmwareInfo - .FirmwareInfo_V_1_3->ulDefaultEngineClock) * 10; - break; - case GET_DEFAULT_MEMORY_CLOCK: - *val = le32_to_cpu(atomDataPtr->FirmwareInfo - .FirmwareInfo_V_1_3->ulDefaultMemoryClock) * 10; - break; - case GET_MAX_PIXEL_CLOCK_PLL_OUTPUT: - *val = le32_to_cpu(atomDataPtr->FirmwareInfo - .FirmwareInfo_V_1_3->ulMaxPixelClockPLL_Output) * 10; - break; - case GET_MIN_PIXEL_CLOCK_PLL_OUTPUT: - *val = le16_to_cpu(atomDataPtr->FirmwareInfo - .FirmwareInfo_V_1_3->usMinPixelClockPLL_Output) * 10; - break; - case GET_MAX_PIXEL_CLOCK_PLL_INPUT: - *val = le16_to_cpu(atomDataPtr->FirmwareInfo - .FirmwareInfo_V_1_3->usMaxPixelClockPLL_Input) * 10; - break; - case GET_MIN_PIXEL_CLOCK_PLL_INPUT: - *val = le16_to_cpu(atomDataPtr->FirmwareInfo - .FirmwareInfo_V_1_3->usMinPixelClockPLL_Input) * 10; - break; - case GET_MAX_PIXEL_CLK: - *val = le16_to_cpu(atomDataPtr->FirmwareInfo - .FirmwareInfo_V_1_3->usMaxPixelClock) * 10; - break; - case GET_REF_CLOCK: - *val = le16_to_cpu(atomDataPtr->FirmwareInfo - .FirmwareInfo_V_1_3->usReferenceClock) * 10; - break; - default: - return ATOM_NOT_IMPLEMENTED; - } - break; - case 4: - switch (func) { - case GET_DEFAULT_ENGINE_CLOCK: - *val = le32_to_cpu(atomDataPtr->FirmwareInfo - .FirmwareInfo_V_1_4->ulDefaultEngineClock) * 10; - break; - case GET_DEFAULT_MEMORY_CLOCK: - *val = le32_to_cpu(atomDataPtr->FirmwareInfo - .FirmwareInfo_V_1_4->ulDefaultMemoryClock) * 10; - break; - case GET_MAX_PIXEL_CLOCK_PLL_INPUT: - *val = le16_to_cpu(atomDataPtr->FirmwareInfo - .FirmwareInfo_V_1_4->usMaxPixelClockPLL_Input) * 10; - break; - case GET_MIN_PIXEL_CLOCK_PLL_INPUT: - *val = le16_to_cpu(atomDataPtr->FirmwareInfo - .FirmwareInfo_V_1_4->usMinPixelClockPLL_Input) * 10; - break; - case GET_MAX_PIXEL_CLOCK_PLL_OUTPUT: - *val = le32_to_cpu(atomDataPtr->FirmwareInfo - .FirmwareInfo_V_1_4->ulMaxPixelClockPLL_Output) * 10; - break; - case GET_MIN_PIXEL_CLOCK_PLL_OUTPUT: - *val = le16_to_cpu(atomDataPtr->FirmwareInfo - .FirmwareInfo_V_1_4->usMinPixelClockPLL_Output) * 10; - break; - case GET_MAX_PIXEL_CLK: - *val = le16_to_cpu(atomDataPtr->FirmwareInfo - .FirmwareInfo_V_1_4->usMaxPixelClock) * 10; - break; - case GET_REF_CLOCK: - *val = le16_to_cpu(atomDataPtr->FirmwareInfo - .FirmwareInfo_V_1_4->usReferenceClock) * 10; - break; - default: - return ATOM_NOT_IMPLEMENTED; - } - break; - default: - return ATOM_NOT_IMPLEMENTED; - } - return ATOM_SUCCESS; -} - -const int object_connector_convert[] = - { CONNECTOR_NONE, - CONNECTOR_DVI_I, - CONNECTOR_DVI_I, - CONNECTOR_DVI_D, - CONNECTOR_DVI_D, - CONNECTOR_VGA, - CONNECTOR_CTV, - CONNECTOR_STV, - CONNECTOR_NONE, - CONNECTOR_NONE, - CONNECTOR_DIN, - CONNECTOR_SCART, - CONNECTOR_HDMI_TYPE_A, - CONNECTOR_HDMI_TYPE_B, - CONNECTOR_LVDS, - CONNECTOR_DIN, - CONNECTOR_NONE, - CONNECTOR_NONE, - CONNECTOR_NONE, - CONNECTOR_DISPLAY_PORT, - CONNECTOR_EDP, - CONNECTOR_NONE, - }; - -xf86MonPtr radeon_atom_get_edid(xf86OutputPtr output) -{ - RADEONOutputPrivatePtr radeon_output = output->driver_private; - RADEONInfoPtr info = RADEONPTR(output->scrn); - READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION edid_data; - AtomBiosArgRec data; - unsigned char *space; - int i2c_clock = 50; - int engine_clk = (int)info->sclk * 100; - int prescale; - unsigned char *edid; - xf86MonPtr mon = NULL; - - if (!radeon_output->ddc_i2c.hw_capable) - return mon; - - if (info->atomBIOS->fbBase) - edid = (unsigned char *)info->FB + info->atomBIOS->fbBase; - else if (info->atomBIOS->scratchBase) - edid = (unsigned char *)info->atomBIOS->scratchBase; - else - return mon; - - memset(edid, 0, ATOM_EDID_RAW_DATASIZE); - - if (info->ChipFamily == CHIP_FAMILY_R520) - prescale = (127 << 8) + (engine_clk * 10) / (4 * 127 * i2c_clock); - else if (info->ChipFamily < CHIP_FAMILY_R600) - prescale = (((engine_clk * 10)/(4 * 128 * 100) + 1) << 8) + 128; - else - prescale = (info->pll.reference_freq * 10) / i2c_clock; - - edid_data.usPrescale = prescale; - edid_data.usVRAMAddress = 0; - edid_data.ucSlaveAddr = 0xa0; - edid_data.ucLineNumber = radeon_output->ddc_i2c.hw_line; - - data.exec.index = GetIndexIntoMasterTable(COMMAND, ReadEDIDFromHWAssistedI2C); - data.exec.dataSpace = (void *)&space; - data.exec.pspace = &edid_data; - - if (RHDAtomBiosFunc(info->atomBIOS->pScrn, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) - ErrorF("Atom Get EDID success\n"); - else - ErrorF("Atom Get EDID failed\n"); - - if (edid[1] == 0xff) - mon = xf86InterpretEDID(output->scrn->scrnIndex, edid); - - return mon; - -} - -static RADEONI2CBusRec -RADEONLookupGPIOLineForDDC(ScrnInfoPtr pScrn, uint8_t id) -{ - RADEONInfoPtr info = RADEONPTR (pScrn); - atomDataTablesPtr atomDataPtr; - ATOM_GPIO_I2C_ASSIGMENT *gpio; - RADEONI2CBusRec i2c; - uint8_t crev, frev; - unsigned short size; - int i, num_indices; - - memset(&i2c, 0, sizeof(RADEONI2CBusRec)); - i2c.valid = FALSE; - - atomDataPtr = info->atomBIOS->atomDataPtr; - - if (!rhdAtomGetTableRevisionAndSize( - &(atomDataPtr->GPIO_I2C_Info->sHeader), - &crev,&frev,&size)) { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "No GPIO Info Table found!\n"); - return i2c; - } - - num_indices = size / sizeof(ATOM_GPIO_I2C_ASSIGMENT); - - for (i = 0; i < num_indices; i++) { - gpio = &atomDataPtr->GPIO_I2C_Info->asGPIO_Info[i]; - - if (IS_DCE4_VARIANT) { - if ((i == 7) && - (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) && - (gpio->sucI2cId.ucAccess == 0)) { - gpio->sucI2cId.ucAccess = 0x97; - gpio->ucDataMaskShift = 8; - gpio->ucDataEnShift = 8; - gpio->ucDataY_Shift = 8; - gpio->ucDataA_Shift = 8; - } - } - - if (gpio->sucI2cId.ucAccess == id) { - i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4; - i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4; - i2c.put_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4; - i2c.put_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4; - i2c.get_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4; - i2c.get_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4; - i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4; - i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4; - i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift); - i2c.mask_data_mask = (1 << gpio->ucDataMaskShift); - i2c.put_clk_mask = (1 << gpio->ucClkEnShift); - i2c.put_data_mask = (1 << gpio->ucDataEnShift); - i2c.get_clk_mask = (1 << gpio->ucClkY_Shift); - i2c.get_data_mask = (1 << gpio->ucDataY_Shift); - i2c.a_clk_mask = (1 << gpio->ucClkA_Shift); - i2c.a_data_mask = (1 << gpio->ucDataA_Shift); - i2c.hw_line = gpio->sucI2cId.ucAccess; - i2c.hw_capable = gpio->sucI2cId.sbfAccess.bfHW_Capable; - i2c.valid = TRUE; - break; - } - } - -#if 0 - ErrorF("id: %d\n", id); - ErrorF("hw capable: %d\n", gpio->sucI2cId.sbfAccess.bfHW_Capable); - ErrorF("hw engine id: %d\n", gpio->sucI2cId.sbfAccess.bfHW_EngineID); - ErrorF("line mux %d\n", gpio->sucI2cId.sbfAccess.bfI2C_LineMux); - ErrorF("mask_clk_reg: 0x%x\n", le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4); - ErrorF("mask_data_reg: 0x%x\n", le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4); - ErrorF("put_clk_reg: 0x%x\n", le16_to_cpu(gpio->usClkEnRegisterIndex) * 4); - ErrorF("put_data_reg: 0x%x\n", le16_to_cpu(gpio->usDataEnRegisterIndex) * 4); - ErrorF("get_clk_reg: 0x%x\n", le16_to_cpu(gpio->usClkY_RegisterIndex) * 4); - ErrorF("get_data_reg: 0x%x\n", le16_to_cpu(gpio->usDataY_RegisterIndex) * 4); - ErrorF("a_clk_reg: 0x%x\n", le16_to_cpu(gpio->usClkA_RegisterIndex) * 4); - ErrorF("a_data_reg: 0x%x\n", le16_to_cpu(gpio->usDataA_RegisterIndex) * 4); - ErrorF("mask_clk_mask: %d\n", gpio->ucClkMaskShift); - ErrorF("mask_data_mask: %d\n", gpio->ucDataMaskShift); - ErrorF("put_clk_mask: %d\n", gpio->ucClkEnShift); - ErrorF("put_data_mask: %d\n", gpio->ucDataEnShift); - ErrorF("get_clk_mask: %d\n", gpio->ucClkY_Shift); - ErrorF("get_data_mask: %d\n", gpio->ucDataY_Shift); - ErrorF("a_clk_mask: %d\n", gpio->ucClkA_Shift); - ErrorF("a_data_mask: %d\n", gpio->ucDataA_Shift); -#endif - - return i2c; -} - -static RADEONI2CBusRec -rhdAtomParseI2CRecord(ScrnInfoPtr pScrn, atomBiosHandlePtr handle, - ATOM_I2C_RECORD *Record, int i) -{ - RADEONInfoPtr info = RADEONPTR (pScrn); - uint8_t *temp = &Record->sucI2cId; - - info->BiosConnector[i].i2c_line_mux = *temp; - info->BiosConnector[i].ucI2cId = *temp; - return RADEONLookupGPIOLineForDDC(pScrn, *temp); -} - -static uint8_t -radeon_lookup_hpd_id(ScrnInfoPtr pScrn, ATOM_HPD_INT_RECORD *record) -{ - RADEONInfoPtr info = RADEONPTR (pScrn); - unsigned short size; - uint8_t hpd = 0; - int i, num_indices; - struct _ATOM_GPIO_PIN_LUT *gpio_info; - ATOM_GPIO_PIN_ASSIGNMENT *pin; - atomDataTablesPtr atomDataPtr; - uint8_t crev, frev; - uint32_t reg; - - atomDataPtr = info->atomBIOS->atomDataPtr; - - if (!rhdAtomGetTableRevisionAndSize( - &(atomDataPtr->GPIO_Pin_LUT->sHeader), - &crev,&frev,&size)) { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "No GPIO Pin Table found!\n"); - return hpd; - } - - num_indices = size / sizeof(ATOM_GPIO_PIN_ASSIGNMENT); - - if (IS_DCE4_VARIANT) - reg = EVERGREEN_DC_GPIO_HPD_A; - else - reg = AVIVO_DC_GPIO_HPD_A; - - gpio_info = atomDataPtr->GPIO_Pin_LUT; - for (i = 0; i < num_indices; i++) { - pin = &gpio_info->asGPIO_Pin[i]; - if (record->ucHPDIntGPIOID == pin->ucGPIO_ID) { - if ((le16_to_cpu(pin->usGpioPin_AIndex) * 4) == reg) { - switch (pin->ucGpioPinBitShift) { - case 0: - default: - hpd = 0; - break; - case 8: - hpd = 1; - break; - case 16: - hpd = 2; - break; - case 24: - hpd = 3; - break; - case 26: - hpd = 4; - break; - case 28: - hpd = 5; - break; - } - break; - } - } - } - - return hpd; -} - -static void RADEONApplyATOMQuirks(ScrnInfoPtr pScrn, int index) -{ - RADEONInfoPtr info = RADEONPTR (pScrn); - - /* Asus M2A-VM HDMI board lists the DVI port as HDMI */ - if ((info->Chipset == PCI_CHIP_RS690_791E) && - (PCI_SUB_VENDOR_ID(info->PciInfo) == 0x1043) && - (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x826d)) { - if ((info->BiosConnector[index].ConnectorType == CONNECTOR_HDMI_TYPE_A) && - (info->BiosConnector[index].devices & ATOM_DEVICE_DFP3_SUPPORT)) { - info->BiosConnector[index].ConnectorType = CONNECTOR_DVI_D; - } - } - - /* RS600 board lists the DVI port as HDMI */ - if ((info->Chipset == PCI_CHIP_RS600_7941) && - (PCI_SUB_VENDOR_ID(info->PciInfo) == 0x1849) && - (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x7941)) { - if ((info->BiosConnector[index].ConnectorType == CONNECTOR_HDMI_TYPE_A) && - (info->BiosConnector[index].devices & ATOM_DEVICE_DFP3_SUPPORT)) { - info->BiosConnector[index].ConnectorType = CONNECTOR_DVI_D; - } - } - - /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */ - if ((info->Chipset == PCI_CHIP_RS600_7941) && - (PCI_SUB_VENDOR_ID(info->PciInfo) == 0x147b) && - (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x2412)) { - if (info->BiosConnector[index].ConnectorType == CONNECTOR_DVI_I) - info->BiosConnector[index].valid = FALSE; - } - - /* Falcon NW laptop lists vga ddc line for LVDS */ - if ((info->Chipset == PCI_CHIP_RV410_5653) && - (PCI_SUB_VENDOR_ID(info->PciInfo) == 0x1462) && - (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x0291)) { - if (info->BiosConnector[index].ConnectorType == CONNECTOR_LVDS) { - info->BiosConnector[index].ddc_i2c.valid = FALSE; - } - } - - /* Funky macbooks */ - if ((info->Chipset == PCI_CHIP_RV530_71C5) && - (PCI_SUB_VENDOR_ID(info->PciInfo) == 0x106b) && - (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x0080)) { - if ((index == ATOM_DEVICE_CRT1_INDEX) || - (index == ATOM_DEVICE_CRT2_INDEX) || - (index == ATOM_DEVICE_DFP2_INDEX)) - info->BiosConnector[index].valid = FALSE; - - if (index == ATOM_DEVICE_DFP1_INDEX) { - info->BiosConnector[index].devices |= ATOM_DEVICE_CRT2_SUPPORT; - } - } - - /* ASUS HD 3600 XT board lists the DVI port as HDMI */ - if ((info->Chipset == PCI_CHIP_RV635_9598) && - (PCI_SUB_VENDOR_ID(info->PciInfo) == 0x1043) && - (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x01da)) { - if (info->BiosConnector[index].ConnectorType == CONNECTOR_HDMI_TYPE_A) - info->BiosConnector[index].ConnectorType = CONNECTOR_DVI_I; - } - - /* ASUS HD 3450 board lists the DVI port as HDMI */ - if ((info->Chipset == PCI_CHIP_RV620_95C5) && - (PCI_SUB_VENDOR_ID(info->PciInfo) == 0x1043) && - (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x01e2)) { - if (info->BiosConnector[index].ConnectorType == CONNECTOR_HDMI_TYPE_A) - info->BiosConnector[index].ConnectorType = CONNECTOR_DVI_I; - } - - /* some BIOSes seem to report DAC on HDMI - usually this is a board with - * HDMI + VGA reporting as HDMI - */ - if (info->BiosConnector[index].ConnectorType == CONNECTOR_HDMI_TYPE_A) { - if (info->BiosConnector[index].devices & (ATOM_DEVICE_CRT_SUPPORT)) { - info->BiosConnector[index].devices &= ~(ATOM_DEVICE_DFP_SUPPORT); - info->BiosConnector[index].ConnectorType = CONNECTOR_VGA; - info->BiosConnector[index].connector_object = 0; - } - } - -} - -uint32_t -radeon_get_device_index(uint32_t device_support) -{ - uint32_t device_index = 0; - - if (device_support == 0) - return 0; - - while ((device_support & 1) == 0) { - device_support >>= 1; - device_index++; - } - return device_index; -} - -radeon_encoder_ptr -radeon_get_encoder(xf86OutputPtr output) -{ - RADEONOutputPrivatePtr radeon_output = output->driver_private; - RADEONInfoPtr info = RADEONPTR(output->scrn); - - if (radeon_output->active_device) - return info->encoders[radeon_get_device_index(radeon_output->active_device)]; - else - return NULL; -} - -Bool -radeon_add_encoder(ScrnInfoPtr pScrn, uint32_t encoder_id, uint32_t device_support) -{ - RADEONInfoPtr info = RADEONPTR (pScrn); - uint32_t device_index = radeon_get_device_index(device_support); - int i; - - if (device_support == 0) { - ErrorF("device support == 0\n"); - return FALSE; - } - - if (info->encoders[device_index] != NULL) - return TRUE; - else { - /* look for the encoder */ - for (i = 0; i < RADEON_MAX_BIOS_CONNECTOR; i++) { - if ((info->encoders[i] != NULL) && (info->encoders[i]->encoder_id == encoder_id)) { - info->encoders[device_index] = info->encoders[i]; - switch (encoder_id) { - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: - case ENCODER_OBJECT_ID_INTERNAL_LVTM1: - if (device_support & ATOM_DEVICE_LCD1_SUPPORT) { - if (info->encoders[device_index]->dev_priv == NULL) { - info->encoders[device_index]->dev_priv = - (radeon_lvds_ptr)calloc(1,sizeof(radeon_lvds_rec)); - if (info->encoders[device_index]->dev_priv == NULL) { - ErrorF("calloc failed\n"); - return FALSE; - } else - RADEONGetATOMLVDSInfo(pScrn, (radeon_lvds_ptr)info->encoders[device_index]->dev_priv); - } - } - break; - } - return TRUE; - } - } - - info->encoders[device_index] = (radeon_encoder_ptr)calloc(1,sizeof(radeon_encoder_rec)); - if (info->encoders[device_index] != NULL) { - info->encoders[device_index]->encoder_id = encoder_id; - info->encoders[device_index]->devices = 0; - info->encoders[device_index]->dev_priv = NULL; - // add dev_priv stuff - switch (encoder_id) { - case ENCODER_OBJECT_ID_INTERNAL_LVDS: - info->encoders[device_index]->dev_priv = (radeon_lvds_ptr)calloc(1,sizeof(radeon_lvds_rec)); - if (info->encoders[device_index]->dev_priv == NULL) { - ErrorF("calloc failed\n"); - return FALSE; - } else { - if (info->IsAtomBios) - RADEONGetATOMLVDSInfo(pScrn, (radeon_lvds_ptr)info->encoders[device_index]->dev_priv); - else - RADEONGetLVDSInfo(pScrn, (radeon_lvds_ptr)info->encoders[device_index]->dev_priv); - } - break; - case ENCODER_OBJECT_ID_INTERNAL_DAC2: - if (!IS_AVIVO_VARIANT) { - info->encoders[device_index]->dev_priv = (radeon_tvdac_ptr)calloc(1,sizeof(radeon_tvdac_rec)); - if (info->encoders[device_index]->dev_priv == NULL) { - ErrorF("calloc failed\n"); - return FALSE; - } else - RADEONGetTVDacAdjInfo(pScrn, (radeon_tvdac_ptr)info->encoders[device_index]->dev_priv); - } - break; - case ENCODER_OBJECT_ID_INTERNAL_TMDS1: - if (!IS_AVIVO_VARIANT) { - info->encoders[device_index]->dev_priv = (radeon_tmds_ptr)calloc(1,sizeof(radeon_tmds_rec)); - if (info->encoders[device_index]->dev_priv == NULL) { - ErrorF("calloc failed\n"); - return FALSE; - } else - RADEONGetTMDSInfo(pScrn, (radeon_tmds_ptr)info->encoders[device_index]->dev_priv); - } - break; - case ENCODER_OBJECT_ID_INTERNAL_DVO1: - if (!IS_AVIVO_VARIANT) { - info->encoders[device_index]->dev_priv = (radeon_dvo_ptr)calloc(1,sizeof(radeon_dvo_rec)); - if (info->encoders[device_index]->dev_priv == NULL) { - ErrorF("calloc failed\n"); - return FALSE; - } else - RADEONGetExtTMDSInfo(pScrn, (radeon_dvo_ptr)info->encoders[device_index]->dev_priv); - } - break; - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: - case ENCODER_OBJECT_ID_INTERNAL_LVTM1: - if (device_support & ATOM_DEVICE_LCD1_SUPPORT) { - info->encoders[device_index]->dev_priv = (radeon_lvds_ptr)calloc(1,sizeof(radeon_lvds_rec)); - if (info->encoders[device_index]->dev_priv == NULL) { - ErrorF("calloc failed\n"); - return FALSE; - } else - RADEONGetATOMLVDSInfo(pScrn, (radeon_lvds_ptr)info->encoders[device_index]->dev_priv); - } - break; - } - return TRUE; - } else { - ErrorF("calloc failed\n"); - return FALSE; - } - } - -} - -Bool -RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR (pScrn); - uint8_t crev, frev; - unsigned short size; - atomDataTablesPtr atomDataPtr; - ATOM_CONNECTOR_OBJECT_TABLE *con_obj; - ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj; - ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj = NULL; - int i, j, path_size, device_support; - Bool enable_tv = FALSE; - - if (xf86ReturnOptValBool(info->Options, OPTION_ATOM_TVOUT, FALSE)) - enable_tv = TRUE; - - atomDataPtr = info->atomBIOS->atomDataPtr; - if (!rhdAtomGetTableRevisionAndSize((ATOM_COMMON_TABLE_HEADER *)(atomDataPtr->Object_Header), &crev, &frev, &size)) - return FALSE; - - if (crev < 2) - return FALSE; - - path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *) - ((char *)&atomDataPtr->Object_Header->sHeader + - le16_to_cpu(atomDataPtr->Object_Header->usDisplayPathTableOffset)); - con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *) - ((char *)&atomDataPtr->Object_Header->sHeader + - le16_to_cpu(atomDataPtr->Object_Header->usConnectorObjectTableOffset)); - device_support = le16_to_cpu(atomDataPtr->Object_Header->usDeviceSupport); - - path_size = 0; - for (i = 0; i < path_obj->ucNumOfDispPath; i++) { - uint8_t *addr = (uint8_t *)path_obj->asDispPath; - ATOM_DISPLAY_OBJECT_PATH *path; - addr += path_size; - path = (ATOM_DISPLAY_OBJECT_PATH *)addr; - path_size += le16_to_cpu(path->usSize); - - if (device_support & le16_to_cpu(path->usDeviceTag)) { - uint8_t con_obj_id, con_obj_num, con_obj_type; - - con_obj_id = (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; - con_obj_num = (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK) >> ENUM_ID_SHIFT; - con_obj_type = (le16_to_cpu(path->usConnObjectId) & OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; - - if ((le16_to_cpu(path->usDeviceTag) == ATOM_DEVICE_TV1_SUPPORT) || - (le16_to_cpu(path->usDeviceTag) == ATOM_DEVICE_TV2_SUPPORT)) { - if (!enable_tv) { - info->BiosConnector[i].valid = FALSE; - continue; - } - } - - /* don't support CV yet */ - if (le16_to_cpu(path->usDeviceTag) == ATOM_DEVICE_CV_SUPPORT) { - info->BiosConnector[i].valid = FALSE; - continue; - } - - if (info->IsIGP && - (con_obj_id == CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) { - uint32_t slot_config, ct; - - igp_obj = info->atomBIOS->atomDataPtr->IntegratedSystemInfo.IntegratedSystemInfo_v2; - - if (!igp_obj) - info->BiosConnector[i].ConnectorType = object_connector_convert[con_obj_id]; - else { - if (con_obj_num == 1) - slot_config = igp_obj->ulDDISlot1Config; - else - slot_config = igp_obj->ulDDISlot2Config; - - ct = (slot_config >> 16) & 0xff; - info->BiosConnector[i].ConnectorType = object_connector_convert[ct]; - info->BiosConnector[i].connector_object_id = ct; - info->BiosConnector[i].igp_lane_info = slot_config & 0xffff; - } - } else { - info->BiosConnector[i].ConnectorType = object_connector_convert[con_obj_id]; - info->BiosConnector[i].connector_object_id = con_obj_id; - } - - if (info->BiosConnector[i].ConnectorType == CONNECTOR_NONE) { - info->BiosConnector[i].valid = FALSE; - continue; - } else - info->BiosConnector[i].valid = TRUE; - info->BiosConnector[i].devices = le16_to_cpu(path->usDeviceTag); - info->BiosConnector[i].connector_object = le16_to_cpu(path->usConnObjectId); - - for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) { - uint8_t enc_obj_id, enc_obj_num, enc_obj_type; - - enc_obj_id = (le16_to_cpu(path->usGraphicObjIds[j]) & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; - enc_obj_num = (le16_to_cpu(path->usGraphicObjIds[j]) & ENUM_ID_MASK) >> ENUM_ID_SHIFT; - enc_obj_type = (le16_to_cpu(path->usGraphicObjIds[j]) & OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; - - if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) { - if (enc_obj_num == 2) - info->BiosConnector[i].linkb = TRUE; - else - info->BiosConnector[i].linkb = FALSE; - - if (!radeon_add_encoder(pScrn, enc_obj_id, le16_to_cpu(path->usDeviceTag))) - return FALSE; - } - } - - /* look up gpio for ddc */ - if ((le16_to_cpu(path->usDeviceTag) & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) { - for (j = 0; j < con_obj->ucNumberOfObjects; j++) { - if (le16_to_cpu(path->usConnObjectId) == le16_to_cpu(con_obj->asObjects[j].usObjectID)) { - ATOM_COMMON_RECORD_HEADER *Record = (ATOM_COMMON_RECORD_HEADER *) - ((char *)&atomDataPtr->Object_Header->sHeader - + le16_to_cpu(con_obj->asObjects[j].usRecordOffset)); - - while (Record->ucRecordType > 0 - && Record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER ) { - - /*ErrorF("record type %d\n", Record->ucRecordType);*/ - switch (Record->ucRecordType) { - case ATOM_I2C_RECORD_TYPE: - info->BiosConnector[i].ddc_i2c = - rhdAtomParseI2CRecord(pScrn, info->atomBIOS, - (ATOM_I2C_RECORD *)Record, j); - break; - case ATOM_HPD_INT_RECORD_TYPE: - info->BiosConnector[i].hpd_id = - radeon_lookup_hpd_id(pScrn, - (ATOM_HPD_INT_RECORD *)Record); - break; - case ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE: - break; - } - - Record = (ATOM_COMMON_RECORD_HEADER*) - ((char *)Record + Record->ucRecordSize); - } - break; - } - } - } - } - RADEONApplyATOMQuirks(pScrn, i); - } - - for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) { - if (info->BiosConnector[i].valid) { - /* shared connectors */ - for (j = 0; j < ATOM_MAX_SUPPORTED_DEVICE; j++) { - if (info->BiosConnector[j].valid && (i != j) ) { - if (info->BiosConnector[i].connector_object == info->BiosConnector[j].connector_object) { - info->BiosConnector[i].devices |= info->BiosConnector[j].devices; - info->BiosConnector[j].valid = FALSE; - } - } - } - /* shared ddc */ - for (j = 0; j < ATOM_MAX_SUPPORTED_DEVICE; j++) { - if (info->BiosConnector[j].valid && (i != j) ) { - if (info->BiosConnector[i].i2c_line_mux == info->BiosConnector[j].i2c_line_mux) { - info->BiosConnector[i].shared_ddc = TRUE; - info->BiosConnector[j].shared_ddc = TRUE; - } - } - } - } - } - - return TRUE; -} - -static void -RADEONGetATOMLVDSInfo(ScrnInfoPtr pScrn, radeon_lvds_ptr lvds) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - radeon_native_mode_ptr native_mode = &lvds->native_mode; - atomDataTablesPtr atomDataPtr; - uint8_t crev, frev; - uint16_t misc; - - atomDataPtr = info->atomBIOS->atomDataPtr; - - if (!rhdAtomGetTableRevisionAndSize( - (ATOM_COMMON_TABLE_HEADER *)(atomDataPtr->LVDS_Info.base), - &frev,&crev,NULL)) { - return; - } - - switch (crev) { - case 1: - native_mode->PanelXRes = le16_to_cpu(atomDataPtr->LVDS_Info.LVDS_Info->sLCDTiming.usHActive); - native_mode->PanelYRes = le16_to_cpu(atomDataPtr->LVDS_Info.LVDS_Info->sLCDTiming.usVActive); - native_mode->DotClock = le16_to_cpu(atomDataPtr->LVDS_Info.LVDS_Info->sLCDTiming.usPixClk) * 10; - native_mode->HBlank = le16_to_cpu(atomDataPtr->LVDS_Info.LVDS_Info->sLCDTiming.usHBlanking_Time); - native_mode->HOverPlus = le16_to_cpu(atomDataPtr->LVDS_Info.LVDS_Info->sLCDTiming.usHSyncOffset); - native_mode->HSyncWidth = le16_to_cpu(atomDataPtr->LVDS_Info.LVDS_Info->sLCDTiming.usHSyncWidth); - native_mode->VBlank = le16_to_cpu(atomDataPtr->LVDS_Info.LVDS_Info->sLCDTiming.usVBlanking_Time); - native_mode->VOverPlus = le16_to_cpu(atomDataPtr->LVDS_Info.LVDS_Info->sLCDTiming.usVSyncOffset); - native_mode->VSyncWidth = le16_to_cpu(atomDataPtr->LVDS_Info.LVDS_Info->sLCDTiming.usVSyncWidth); - misc = le16_to_cpu(atomDataPtr->LVDS_Info.LVDS_Info->sLCDTiming.susModeMiscInfo.usAccess); - if (misc & ATOM_VSYNC_POLARITY) - native_mode->Flags |= V_NVSYNC; - if (misc & ATOM_HSYNC_POLARITY) - native_mode->Flags |= V_NHSYNC; - if (misc & ATOM_COMPOSITESYNC) - native_mode->Flags |= V_CSYNC; - if (misc & ATOM_INTERLACE) - native_mode->Flags |= V_INTERLACE; - if (misc & ATOM_DOUBLE_CLOCK_MODE) - native_mode->Flags |= V_DBLSCAN; - lvds->PanelPwrDly = le16_to_cpu(atomDataPtr->LVDS_Info.LVDS_Info->usOffDelayInMs); - lvds->lvds_misc = atomDataPtr->LVDS_Info.LVDS_Info->ucLVDS_Misc; - lvds->lvds_ss_id = atomDataPtr->LVDS_Info.LVDS_Info->ucSS_Id; - break; - case 2: - native_mode->PanelXRes = le16_to_cpu(atomDataPtr->LVDS_Info.LVDS_Info_v12->sLCDTiming.usHActive); - native_mode->PanelYRes = le16_to_cpu(atomDataPtr->LVDS_Info.LVDS_Info_v12->sLCDTiming.usVActive); - native_mode->DotClock = le16_to_cpu(atomDataPtr->LVDS_Info.LVDS_Info_v12->sLCDTiming.usPixClk) * 10; - native_mode->HBlank = le16_to_cpu(atomDataPtr->LVDS_Info.LVDS_Info_v12->sLCDTiming.usHBlanking_Time); - native_mode->HOverPlus = le16_to_cpu(atomDataPtr->LVDS_Info.LVDS_Info_v12->sLCDTiming.usHSyncOffset); - native_mode->HSyncWidth = le16_to_cpu(atomDataPtr->LVDS_Info.LVDS_Info_v12->sLCDTiming.usHSyncWidth); - native_mode->VBlank = le16_to_cpu(atomDataPtr->LVDS_Info.LVDS_Info_v12->sLCDTiming.usVBlanking_Time); - native_mode->VOverPlus = le16_to_cpu(atomDataPtr->LVDS_Info.LVDS_Info_v12->sLCDTiming.usVSyncOffset); - native_mode->VSyncWidth = le16_to_cpu(atomDataPtr->LVDS_Info.LVDS_Info_v12->sLCDTiming.usVSyncWidth); - misc = le16_to_cpu(atomDataPtr->LVDS_Info.LVDS_Info_v12->sLCDTiming.susModeMiscInfo.usAccess); - if (misc & ATOM_VSYNC_POLARITY) - native_mode->Flags |= V_NVSYNC; - if (misc & ATOM_HSYNC_POLARITY) - native_mode->Flags |= V_NHSYNC; - if (misc & ATOM_COMPOSITESYNC) - native_mode->Flags |= V_CSYNC; - if (misc & ATOM_INTERLACE) - native_mode->Flags |= V_INTERLACE; - if (misc & ATOM_DOUBLE_CLOCK_MODE) - native_mode->Flags |= V_DBLSCAN; - lvds->PanelPwrDly = le16_to_cpu(atomDataPtr->LVDS_Info.LVDS_Info_v12->usOffDelayInMs); - lvds->lvds_misc = atomDataPtr->LVDS_Info.LVDS_Info_v12->ucLVDS_Misc; - lvds->lvds_ss_id = atomDataPtr->LVDS_Info.LVDS_Info_v12->ucSS_Id; - break; - } - native_mode->Flags = 0; - - if (lvds->PanelPwrDly > 2000 || lvds->PanelPwrDly < 0) - lvds->PanelPwrDly = 2000; - - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "LVDS Info:\n" - "XRes: %d, YRes: %d, DotClock: %d\n" - "HBlank: %d, HOverPlus: %d, HSyncWidth: %d\n" - "VBlank: %d, VOverPlus: %d, VSyncWidth: %d\n", - native_mode->PanelXRes, native_mode->PanelYRes, native_mode->DotClock, - native_mode->HBlank, native_mode->HOverPlus, native_mode->HSyncWidth, - native_mode->VBlank, native_mode->VOverPlus, native_mode->VSyncWidth); -} - -void -RADEONATOMGetIGPInfo(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - atomDataTablesPtr atomDataPtr; - unsigned short size; - uint8_t crev, frev; - - atomDataPtr = info->atomBIOS->atomDataPtr; - - if (!rhdAtomGetTableRevisionAndSize((ATOM_COMMON_TABLE_HEADER *)(atomDataPtr->IntegratedSystemInfo.base), &frev, &crev, &size)) - return; - - switch (crev) { - case 1: - info->igp_sideport_mclk = atomDataPtr->IntegratedSystemInfo.IntegratedSystemInfo->ulBootUpMemoryClock / 100.0; - info->igp_system_mclk = le16_to_cpu(atomDataPtr->IntegratedSystemInfo.IntegratedSystemInfo->usK8MemoryClock); - info->igp_ht_link_clk = le16_to_cpu(atomDataPtr->IntegratedSystemInfo.IntegratedSystemInfo->usFSBClock); - info->igp_ht_link_width = atomDataPtr->IntegratedSystemInfo.IntegratedSystemInfo->ucHTLinkWidth; - break; - case 2: - info->igp_sideport_mclk = atomDataPtr->IntegratedSystemInfo.IntegratedSystemInfo_v2->ulBootUpSidePortClock / 100.0; - info->igp_system_mclk = atomDataPtr->IntegratedSystemInfo.IntegratedSystemInfo_v2->ulBootUpUMAClock / 100.0; - info->igp_ht_link_clk = atomDataPtr->IntegratedSystemInfo.IntegratedSystemInfo_v2->ulHTLinkFreq / 100.0; - info->igp_ht_link_width = le16_to_cpu(atomDataPtr->IntegratedSystemInfo.IntegratedSystemInfo_v2->usMinHTLinkWidth); - break; - } -} - -Bool -RADEONGetATOMTVInfo(xf86OutputPtr output) -{ - ScrnInfoPtr pScrn = output->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONOutputPrivatePtr radeon_output = output->driver_private; - radeon_tvout_ptr tvout = &radeon_output->tvout; - ATOM_ANALOG_TV_INFO *tv_info; - - tv_info = info->atomBIOS->atomDataPtr->AnalogTV_Info.AnalogTV_Info; - - if (!tv_info) - return FALSE; - - switch(tv_info->ucTV_BootUpDefaultStandard) { - case NTSCJ_SUPPORT: - tvout->default_tvStd = TV_STD_NTSC_J; - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: NTSC-J\n"); - break; - case PAL_SUPPORT: - tvout->default_tvStd = TV_STD_PAL; - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: PAL\n"); - break; - case PALM_SUPPORT: - tvout->default_tvStd = TV_STD_PAL_M; - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: PAL-M\n"); - break; - case PAL60_SUPPORT: - tvout->default_tvStd = TV_STD_PAL_60; - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: PAL-60\n"); - break; - default: - case NTSC_SUPPORT: - tvout->default_tvStd = TV_STD_NTSC; - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: NTSC\n"); - break; - } - - tvout->tvStd = tvout->default_tvStd; - - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "TV standards supported by chip: "); - tvout->SupportedTVStds = tvout->default_tvStd; - if (tv_info->ucTV_SupportedStandard & NTSC_SUPPORT) { - ErrorF("NTSC "); - tvout->SupportedTVStds |= TV_STD_NTSC; - } - if (tv_info->ucTV_SupportedStandard & NTSCJ_SUPPORT) { - ErrorF("NTSC-J "); - tvout->SupportedTVStds |= TV_STD_NTSC_J; - } - if (tv_info->ucTV_SupportedStandard & PAL_SUPPORT) { - ErrorF("PAL "); - tvout->SupportedTVStds |= TV_STD_PAL; - } - if (tv_info->ucTV_SupportedStandard & PALM_SUPPORT) { - ErrorF("PAL-M "); - tvout->SupportedTVStds |= TV_STD_PAL_M; - } - if (tv_info->ucTV_SupportedStandard & PAL60_SUPPORT) { - ErrorF("PAL-60 "); - tvout->SupportedTVStds |= TV_STD_PAL_60; - } - ErrorF("\n"); - - if (tv_info->ucExt_TV_ASIC_ID) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unknown external TV ASIC\n"); - return FALSE; - } - - return TRUE; -} - -Bool -RADEONGetATOMClockInfo(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR (pScrn); - RADEONPLLPtr pll = &info->pll; - atomDataTablesPtr atomDataPtr; - uint8_t crev, frev; - - atomDataPtr = info->atomBIOS->atomDataPtr; - if (!rhdAtomGetTableRevisionAndSize( - (ATOM_COMMON_TABLE_HEADER *)(atomDataPtr->FirmwareInfo.base), - &crev,&frev,NULL)) { - return FALSE; - } - - switch(crev) { - case 1: - info->sclk = le32_to_cpu(atomDataPtr->FirmwareInfo.FirmwareInfo->ulDefaultEngineClock) / 100.0; - info->mclk = le32_to_cpu(atomDataPtr->FirmwareInfo.FirmwareInfo->ulDefaultMemoryClock) / 100.0; - pll->xclk = le16_to_cpu(atomDataPtr->FirmwareInfo.FirmwareInfo->usMaxPixelClock); - pll->pll_in_min = le16_to_cpu(atomDataPtr->FirmwareInfo.FirmwareInfo->usMinPixelClockPLL_Input); - pll->pll_in_max = le16_to_cpu(atomDataPtr->FirmwareInfo.FirmwareInfo->usMaxPixelClockPLL_Input); - pll->pll_out_min = le16_to_cpu(atomDataPtr->FirmwareInfo.FirmwareInfo->usMinPixelClockPLL_Output); - pll->pll_out_max = le32_to_cpu(atomDataPtr->FirmwareInfo.FirmwareInfo->ulMaxPixelClockPLL_Output); - pll->reference_freq = le16_to_cpu(atomDataPtr->FirmwareInfo.FirmwareInfo->usReferenceClock); - break; - case 2: - case 3: - case 4: - default: - info->sclk = le32_to_cpu(atomDataPtr->FirmwareInfo.FirmwareInfo_V_1_2->ulDefaultEngineClock) / 100.0; - info->mclk = le32_to_cpu(atomDataPtr->FirmwareInfo.FirmwareInfo_V_1_2->ulDefaultMemoryClock) / 100.0; - pll->xclk = le16_to_cpu(atomDataPtr->FirmwareInfo.FirmwareInfo_V_1_2->usMaxPixelClock); - pll->pll_in_min = le16_to_cpu(atomDataPtr->FirmwareInfo.FirmwareInfo_V_1_2->usMinPixelClockPLL_Input); - pll->pll_in_max = le16_to_cpu(atomDataPtr->FirmwareInfo.FirmwareInfo_V_1_2->usMaxPixelClockPLL_Input); - pll->pll_out_min = le32_to_cpu(atomDataPtr->FirmwareInfo.FirmwareInfo_V_1_2->ulMinPixelClockPLL_Output); - pll->pll_out_max = le32_to_cpu(atomDataPtr->FirmwareInfo.FirmwareInfo_V_1_2->ulMaxPixelClockPLL_Output); - pll->reference_freq = le16_to_cpu(atomDataPtr->FirmwareInfo.FirmwareInfo_V_1_2->usReferenceClock); - break; - } - pll->reference_div = 0; - if (pll->pll_out_min == 0) { - if (IS_AVIVO_VARIANT) - pll->pll_out_min = 64800; - else - pll->pll_out_min = 20000; - } - - /* limiting the range is a good thing in most cases - * as it limits the number of matching pll combinations, - * however, some duallink DVI monitors seem to prefer combinations that - * would be limited by this. This may need to be revisited - * per chip family. - */ - if (!xf86ReturnOptValBool(info->Options, OPTION_NEW_PLL, TRUE)) { - if (pll->pll_out_min > 64800) - pll->pll_out_min = 64800; - } - - if (IS_DCE4_VARIANT) { - info->default_dispclk = - le32_to_cpu(atomDataPtr->FirmwareInfo.FirmwareInfo_V_2_1->ulDefaultDispEngineClkFreq); - if (info->default_dispclk == 0) - info->default_dispclk = 60000; - info->dp_extclk = le16_to_cpu(atomDataPtr->FirmwareInfo.FirmwareInfo_V_2_1->usUniphyDPModeExtClkFreq); - } - return TRUE; -} - -Bool -RADEONATOMGetTVTimings(ScrnInfoPtr pScrn, int index, DisplayModePtr mode) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - ATOM_ANALOG_TV_INFO *tv_info; - ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2; - ATOM_DTD_FORMAT *dtd_timings; - atomDataTablesPtr atomDataPtr; - uint8_t crev, frev; - uint16_t misc; - - atomDataPtr = info->atomBIOS->atomDataPtr; - if (!rhdAtomGetTableRevisionAndSize( - (ATOM_COMMON_TABLE_HEADER *)(atomDataPtr->AnalogTV_Info.base), - &crev,&frev,NULL)) { - return FALSE; - } - - switch(crev) { - case 1: - tv_info = atomDataPtr->AnalogTV_Info.AnalogTV_Info; - - if (index > MAX_SUPPORTED_TV_TIMING) - return FALSE; - - mode->CrtcHTotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total); - mode->CrtcHDisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp); - mode->CrtcHSyncStart = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart); - mode->CrtcHSyncEnd = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) + - le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth); - - mode->CrtcVTotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total); - mode->CrtcVDisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp); - mode->CrtcVSyncStart = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart); - mode->CrtcVSyncEnd = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) + - le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth); - - mode->Flags = 0; - misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess); - if (misc & ATOM_VSYNC_POLARITY) - mode->Flags |= V_NVSYNC; - if (misc & ATOM_HSYNC_POLARITY) - mode->Flags |= V_NHSYNC; - if (misc & ATOM_COMPOSITESYNC) - mode->Flags |= V_CSYNC; - if (misc & ATOM_INTERLACE) - mode->Flags |= V_INTERLACE; - if (misc & ATOM_DOUBLE_CLOCK_MODE) - mode->Flags |= V_DBLSCAN; - - mode->Clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10; - - if (index == 1) { - /* PAL timings appear to have wrong values for totals */ - mode->CrtcHTotal -= 1; - mode->CrtcVTotal -= 1; - } - break; - case 2: - tv_info_v1_2 = atomDataPtr->AnalogTV_Info.AnalogTV_Info_v1_2; - if (index > MAX_SUPPORTED_TV_TIMING_V1_2) - return FALSE; - - dtd_timings = &tv_info_v1_2->aModeTimings[index]; - mode->CrtcHTotal = le16_to_cpu(dtd_timings->usHActive) + le16_to_cpu(dtd_timings->usHBlanking_Time); - mode->CrtcHDisplay = le16_to_cpu(dtd_timings->usHActive); - mode->CrtcHSyncStart = le16_to_cpu(dtd_timings->usHActive) + le16_to_cpu(dtd_timings->usHSyncOffset); - mode->CrtcHSyncEnd = mode->CrtcHSyncStart + le16_to_cpu(dtd_timings->usHSyncWidth); - - mode->CrtcVTotal = le16_to_cpu(dtd_timings->usVActive) + le16_to_cpu(dtd_timings->usVBlanking_Time); - mode->CrtcVDisplay = le16_to_cpu(dtd_timings->usVActive); - mode->CrtcVSyncStart = le16_to_cpu(dtd_timings->usVActive) + le16_to_cpu(dtd_timings->usVSyncOffset); - mode->CrtcVSyncEnd = mode->CrtcVSyncStart + le16_to_cpu(dtd_timings->usVSyncWidth); - - mode->Flags = 0; - misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess); - if (misc & ATOM_VSYNC_POLARITY) - mode->Flags |= V_NVSYNC; - if (misc & ATOM_HSYNC_POLARITY) - mode->Flags |= V_NHSYNC; - if (misc & ATOM_COMPOSITESYNC) - mode->Flags |= V_CSYNC; - if (misc & ATOM_INTERLACE) - mode->Flags |= V_INTERLACE; - if (misc & ATOM_DOUBLE_CLOCK_MODE) - mode->Flags |= V_DBLSCAN; - - mode->Clock = le16_to_cpu(dtd_timings->usPixClk) * 10; - - break; - } - - return TRUE; -} - -uint32_t -radeon_get_encoder_id_from_supported_device(ScrnInfoPtr pScrn, uint32_t supported_device, int dac) -{ - RADEONInfoPtr info = RADEONPTR (pScrn); - uint32_t ret = 0; - - switch (supported_device) { - case ATOM_DEVICE_CRT1_SUPPORT: - case ATOM_DEVICE_TV1_SUPPORT: - case ATOM_DEVICE_TV2_SUPPORT: - case ATOM_DEVICE_CRT2_SUPPORT: - case ATOM_DEVICE_CV_SUPPORT: - switch (dac) { - // primary dac - case 1: - if ((info->ChipFamily == CHIP_FAMILY_RS300) || - (info->ChipFamily == CHIP_FAMILY_RS400) || - (info->ChipFamily == CHIP_FAMILY_RS480)) - ret = ENCODER_OBJECT_ID_INTERNAL_DAC2; - else if (IS_AVIVO_VARIANT) - ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1; - else - ret = ENCODER_OBJECT_ID_INTERNAL_DAC1; - break; - // secondary dac - case 2: - if (IS_AVIVO_VARIANT) - ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2; - else { - /*if (info->ChipFamily == CHIP_FAMILY_R200) - ret = ENCODER_OBJECT_ID_INTERNAL_DVO1; - else*/ - ret = ENCODER_OBJECT_ID_INTERNAL_DAC2; - } - break; - // external dac - case 3: - if (IS_AVIVO_VARIANT) - ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1; - else - ret = ENCODER_OBJECT_ID_INTERNAL_DVO1; - break; - } - break; - case ATOM_DEVICE_LCD1_SUPPORT: - if (IS_AVIVO_VARIANT) - ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1; - else - ret = ENCODER_OBJECT_ID_INTERNAL_LVDS; - break; - case ATOM_DEVICE_DFP1_SUPPORT: - if ((info->ChipFamily == CHIP_FAMILY_RS300) || - (info->ChipFamily == CHIP_FAMILY_RS400) || - (info->ChipFamily == CHIP_FAMILY_RS480)) - ret = ENCODER_OBJECT_ID_INTERNAL_DVO1; - else if (IS_AVIVO_VARIANT) - ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1; - else - ret = ENCODER_OBJECT_ID_INTERNAL_TMDS1; - break; - case ATOM_DEVICE_LCD2_SUPPORT: - case ATOM_DEVICE_DFP2_SUPPORT: - if ((info->ChipFamily == CHIP_FAMILY_RS600) || - (info->ChipFamily == CHIP_FAMILY_RS690) || - (info->ChipFamily == CHIP_FAMILY_RS740)) - ret = ENCODER_OBJECT_ID_INTERNAL_DDI; - else if (IS_AVIVO_VARIANT) - ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1; - else - ret = ENCODER_OBJECT_ID_INTERNAL_DVO1; - break; - case ATOM_DEVICE_DFP3_SUPPORT: - ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1; - break; - } - - return ret; -} - -Bool -RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR (pScrn); - atomDataTablesPtr atomDataPtr; - uint8_t crev, frev; - int i, j; - Bool enable_tv = FALSE; - - if (xf86ReturnOptValBool(info->Options, OPTION_ATOM_TVOUT, FALSE)) - enable_tv = TRUE; - - atomDataPtr = info->atomBIOS->atomDataPtr; - - if (!rhdAtomGetTableRevisionAndSize( - &(atomDataPtr->SupportedDevicesInfo.SupportedDevicesInfo->sHeader), - &crev,&frev,NULL)) { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "No Device Info Table found!\n"); - return FALSE; - } - - for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) { - ATOM_CONNECTOR_INFO_I2C ci - = atomDataPtr->SupportedDevicesInfo.SupportedDevicesInfo->asConnInfo[i]; - - if (!(le16_to_cpu(atomDataPtr->SupportedDevicesInfo - .SupportedDevicesInfo->usDeviceSupport) & (1 << i))) { - info->BiosConnector[i].valid = FALSE; - continue; - } - - /* don't support CV yet */ - if (i == ATOM_DEVICE_CV_INDEX) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Skipping Component Video\n"); - info->BiosConnector[i].valid = FALSE; - continue; - } - - if (!enable_tv && (i == ATOM_DEVICE_TV1_INDEX)) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Skipping TV-Out\n"); - info->BiosConnector[i].valid = FALSE; - continue; - } - - info->BiosConnector[i].valid = TRUE; - info->BiosConnector[i].load_detection = TRUE; - info->BiosConnector[i].shared_ddc = FALSE; - info->BiosConnector[i].output_id = ci.sucI2cId.ucAccess; - info->BiosConnector[i].devices = (1 << i); - info->BiosConnector[i].ConnectorType = ci.sucConnectorInfo.sbfAccess.bfConnectorType; - - if (info->BiosConnector[i].ConnectorType == CONNECTOR_NONE) { - info->BiosConnector[i].valid = FALSE; - continue; - } - - /* don't assign a gpio for tv */ - if ((i == ATOM_DEVICE_TV1_INDEX) || - (i == ATOM_DEVICE_TV2_INDEX) || - (i == ATOM_DEVICE_CV_INDEX)) - info->BiosConnector[i].ddc_i2c.valid = FALSE; - else - info->BiosConnector[i].ddc_i2c = - RADEONLookupGPIOLineForDDC(pScrn, ci.sucI2cId.ucAccess); - - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, (1 << i), - ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC), - (1 << i))) - return FALSE; - - /* Always set the connector type to VGA for CRT1/CRT2. if they are - * shared with a DVI port, we'll pick up the DVI connector below when we - * merge the outputs - */ - if ((i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX) && - (info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_I || - info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_D || - info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_A)) { - info->BiosConnector[i].ConnectorType = CONNECTOR_VGA; - } - - if (crev > 1) { - ATOM_CONNECTOR_INC_SRC_BITMAP isb - = atomDataPtr->SupportedDevicesInfo - .SupportedDevicesInfo_HD->asIntSrcInfo[i]; - - switch (isb.ucIntSrcBitmap) { - case 0x4: - info->BiosConnector[i].hpd_mask = 0x00000001; - break; - case 0xa: - info->BiosConnector[i].hpd_mask = 0x00000100; - break; - default: - info->BiosConnector[i].hpd_mask = 0; - break; - } - } else - info->BiosConnector[i].hpd_mask = 0; - - RADEONApplyATOMQuirks(pScrn, i); - - } - - /* CRTs/DFPs may share a port */ - for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) { - if (info->BiosConnector[i].valid) { - for (j = 0; j < ATOM_MAX_SUPPORTED_DEVICE; j++) { - if (info->BiosConnector[j].valid && (i != j) ) { - if (info->BiosConnector[i].output_id == info->BiosConnector[j].output_id) { - if (((i == ATOM_DEVICE_DFP1_INDEX) || - (i == ATOM_DEVICE_DFP2_INDEX) || - (i == ATOM_DEVICE_DFP3_INDEX)) && - ((j == ATOM_DEVICE_CRT1_INDEX) || - (j == ATOM_DEVICE_CRT2_INDEX))) { - info->BiosConnector[i].devices |= info->BiosConnector[j].devices; - if (info->BiosConnector[i].ConnectorType == CONNECTOR_DVI_D) - info->BiosConnector[i].ConnectorType = CONNECTOR_DVI_I; - info->BiosConnector[j].valid = FALSE; - } else if (((j == ATOM_DEVICE_DFP1_INDEX) || - (j == ATOM_DEVICE_DFP2_INDEX) || - (j == ATOM_DEVICE_DFP3_INDEX)) && - ((i == ATOM_DEVICE_CRT1_INDEX) || - (i == ATOM_DEVICE_CRT2_INDEX))) { - info->BiosConnector[j].devices |= info->BiosConnector[i].devices; - if (info->BiosConnector[j].ConnectorType == CONNECTOR_DVI_D) - info->BiosConnector[j].ConnectorType = CONNECTOR_DVI_I; - info->BiosConnector[i].valid = FALSE; - } else { - info->BiosConnector[i].shared_ddc = TRUE; - info->BiosConnector[j].shared_ddc = TRUE; - } - /* other possible combos? */ - } - } - } - } - } - - return TRUE; -} - -# ifdef ATOM_BIOS_PARSER -static AtomBiosResult -rhdAtomExec (atomBiosHandlePtr handle, - AtomBiosRequestID unused, AtomBiosArgPtr data) -{ - RADEONInfoPtr info = RADEONPTR (handle->pScrn); - Bool ret = FALSE; - char *msg; - int idx = data->exec.index; - void *pspace = data->exec.pspace; - pointer *dataSpace = data->exec.dataSpace; - - //RHDFUNCI(handle->scrnIndex); - - if (dataSpace) { - if (!handle->fbBase && !handle->scratchBase) - return ATOM_FAILED; - if (handle->fbBase) { - if (!info->FB) { - xf86DrvMsg(handle->pScrn->scrnIndex, X_ERROR, "%s: " - "Cannot exec AtomBIOS: framebuffer not mapped\n", - __func__); - return ATOM_FAILED; - } - *dataSpace = (uint8_t*)info->FB + handle->fbBase; - } else - *dataSpace = (uint8_t*)handle->scratchBase; - } - ret = ParseTableWrapper(pspace, idx, handle, - handle->BIOSBase, - &msg); - if (!ret) - xf86DrvMsg(handle->pScrn->scrnIndex, X_ERROR, "%s\n",msg); - else - xf86DrvMsgVerb(handle->pScrn->scrnIndex, X_INFO, 5, "%s\n",msg); - - return (ret) ? ATOM_SUCCESS : ATOM_FAILED; -} -# endif - -AtomBiosResult -RHDAtomBiosFunc(ScrnInfoPtr pScrn, atomBiosHandlePtr handle, - AtomBiosRequestID id, AtomBiosArgPtr data) -{ - AtomBiosResult ret = ATOM_FAILED; - int i; - char *msg = NULL; - enum msgDataFormat msg_f = MSG_FORMAT_NONE; - AtomBiosRequestFunc req_func = NULL; - - //RHDFUNCI(scrnIndex); - - for (i = 0; AtomBiosRequestList[i].id != FUNC_END; i++) { - if (id == AtomBiosRequestList[i].id) { - req_func = AtomBiosRequestList[i].request; - msg = AtomBiosRequestList[i].message; - msg_f = AtomBiosRequestList[i].message_format; - break; - } - } - - if (req_func == NULL) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unknown AtomBIOS request: %i\n",id); - return ATOM_NOT_IMPLEMENTED; - } - /* Hack for now */ - if (id == ATOMBIOS_INIT) - data->pScrn = pScrn; - - if (id == ATOMBIOS_INIT || handle) - ret = req_func(handle, id, data); - - if (ret == ATOM_SUCCESS) { - - switch (msg_f) { - case MSG_FORMAT_DEC: - xf86DrvMsg(pScrn->scrnIndex,X_INFO,"%s: %li\n", msg, - (unsigned long) data->val); - break; - case MSG_FORMAT_HEX: - xf86DrvMsg(pScrn->scrnIndex,X_INFO,"%s: 0x%lx\n",msg , - (unsigned long) data->val); - break; - case MSG_FORMAT_NONE: - xf86DrvMsgVerb(pScrn->scrnIndex, 7, X_INFO, - "Call to %s succeeded\n", msg); - break; - } - - } else { - - char *result = (ret == ATOM_FAILED) ? "failed" - : "not implemented"; - switch (msg_f) { - case MSG_FORMAT_DEC: - case MSG_FORMAT_HEX: - xf86DrvMsgVerb(pScrn->scrnIndex, 1, X_WARNING, - "Call to %s %s\n", msg, result); - break; - case MSG_FORMAT_NONE: - xf86DrvMsg(pScrn->scrnIndex,X_INFO,"Query for %s: %s\n", msg, result); - break; - } - } - return ret; -} - -# ifdef ATOM_BIOS_PARSER -VOID* -CailAllocateMemory(VOID *CAIL,UINT16 size) -{ - void *ret; - CAILFUNC(CAIL); - - ret = malloc(size); - memset(ret, 0, size); - return ret; -} - -VOID -CailReleaseMemory(VOID *CAIL, VOID *addr) -{ - CAILFUNC(CAIL); - - free(addr); -} - -VOID -CailDelayMicroSeconds(VOID *CAIL, UINT32 delay) -{ - CAILFUNC(CAIL); - - usleep(delay); - - /*DEBUGP(xf86DrvMsg(((atomBiosHandlePtr)CAIL)->scrnIndex,X_INFO,"Delay %i usec\n",delay));*/ -} - -UINT32 -CailReadATIRegister(VOID* CAIL, UINT32 idx) -{ - ScrnInfoPtr pScrn = ((atomBiosHandlePtr)CAIL)->pScrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); - unsigned char *RADEONMMIO = pRADEONEnt->MMIO; - UINT32 ret; - UINT32 mm_reg = idx << 2; - CAILFUNC(CAIL); - - if (mm_reg < info->MMIOSize) - ret = INREG(mm_reg); - else { - OUTREG(RADEON_MM_INDEX, mm_reg); - ret = INREG(RADEON_MM_DATA); - } - - /*DEBUGP(ErrorF("%s(%x) = %x\n",__func__,idx << 2,ret));*/ - return ret; -} - -VOID -CailWriteATIRegister(VOID *CAIL, UINT32 idx, UINT32 data) -{ - ScrnInfoPtr pScrn = ((atomBiosHandlePtr)CAIL)->pScrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); - unsigned char *RADEONMMIO = pRADEONEnt->MMIO; - UINT32 mm_reg = idx << 2; - CAILFUNC(CAIL); - - if (mm_reg < info->MMIOSize) - OUTREG(mm_reg, data); - else { - OUTREG(RADEON_MM_INDEX, mm_reg); - OUTREG(RADEON_MM_DATA, data); - } - - /*DEBUGP(ErrorF("%s(%x,%x)\n",__func__,idx << 2,data));*/ -} - -UINT32 -CailReadFBData(VOID* CAIL, UINT32 idx) -{ - ScrnInfoPtr pScrn = ((atomBiosHandlePtr)CAIL)->pScrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - UINT32 ret; - - CAILFUNC(CAIL); - - if (((atomBiosHandlePtr)CAIL)->fbBase) { - uint8_t *FBBase = (uint8_t*)info->FB; - ret = *((uint32_t*)(FBBase + (((atomBiosHandlePtr)CAIL)->fbBase) + idx)); - /*DEBUGP(ErrorF("%s(%x) = %x\n",__func__,idx,ret));*/ - } else if (((atomBiosHandlePtr)CAIL)->scratchBase) { - ret = *(uint32_t*)((uint8_t*)(((atomBiosHandlePtr)CAIL)->scratchBase) + idx); - /*DEBUGP(ErrorF("%s(%x) = %x\n",__func__,idx,ret));*/ - } else { - xf86DrvMsg(pScrn->scrnIndex,X_ERROR, - "%s: no fbbase set\n",__func__); - return 0; - } - return ret; -} - -VOID -CailWriteFBData(VOID *CAIL, UINT32 idx, UINT32 data) -{ - ScrnInfoPtr pScrn = ((atomBiosHandlePtr)CAIL)->pScrn; - CAILFUNC(CAIL); - - /*DEBUGP(ErrorF("%s(%x,%x)\n",__func__,idx,data));*/ - if (((atomBiosHandlePtr)CAIL)->fbBase) { - uint8_t *FBBase = (uint8_t*) - RADEONPTR(pScrn)->FB; - *((uint32_t*)(FBBase + (((atomBiosHandlePtr)CAIL)->fbBase) + idx)) = data; - } else if (((atomBiosHandlePtr)CAIL)->scratchBase) { - *(uint32_t*)((uint8_t*)(((atomBiosHandlePtr)CAIL)->scratchBase) + idx) = data; - } else - xf86DrvMsg(pScrn->scrnIndex,X_ERROR, - "%s: no fbbase set\n",__func__); -} - -ULONG -CailReadMC(VOID *CAIL, ULONG Address) -{ - ScrnInfoPtr pScrn = ((atomBiosHandlePtr)CAIL)->pScrn; - ULONG ret; - - CAILFUNC(CAIL); - - ret = INMC(pScrn, Address); - /*DEBUGP(ErrorF("%s(%x) = %x\n",__func__,Address,ret));*/ - return ret; -} - -VOID -CailWriteMC(VOID *CAIL, ULONG Address, ULONG data) -{ - ScrnInfoPtr pScrn = ((atomBiosHandlePtr)CAIL)->pScrn; - - CAILFUNC(CAIL); - /*DEBUGP(ErrorF("%s(%x,%x)\n",__func__,Address,data));*/ - OUTMC(pScrn, Address, data); -} - -#ifdef XSERVER_LIBPCIACCESS - -VOID -CailReadPCIConfigData(VOID*CAIL, VOID* ret, UINT32 idx,UINT16 size) -{ - ScrnInfoPtr pScrn = ((atomBiosHandlePtr)CAIL)->pScrn; - pci_device_cfg_read(RADEONPTR(pScrn)->PciInfo, - ret,idx << 2 , size >> 3, NULL); -} - -VOID -CailWritePCIConfigData(VOID*CAIL,VOID*src,UINT32 idx,UINT16 size) -{ - ScrnInfoPtr pScrn = ((atomBiosHandlePtr)CAIL)->pScrn; - pci_device_cfg_write(RADEONPTR(pScrn)->PciInfo, - src, idx << 2, size >> 3, NULL); -} - -#else - -VOID -CailReadPCIConfigData(VOID*CAIL, VOID* ret, UINT32 idx,UINT16 size) -{ - PCITAG tag = ((atomBiosHandlePtr)CAIL)->PciTag; - - CAILFUNC(CAIL); - - switch (size) { - case 8: - *(uint8_t*)ret = pciReadByte(tag,idx << 2); - break; - case 16: - *(uint16_t*)ret = pciReadWord(tag,idx << 2); - break; - case 32: - *(uint32_t*)ret = pciReadLong(tag,idx << 2); - break; - default: - xf86DrvMsg(((atomBiosHandlePtr)CAIL)->scrnIndex, - X_ERROR,"%s: Unsupported size: %i\n", - __func__,(int)size); - return; - break; - } - /*DEBUGP(ErrorF("%s(%x) = %x\n",__func__,idx,*(unsigned int*)ret));*/ - -} - -VOID -CailWritePCIConfigData(VOID*CAIL,VOID*src,UINT32 idx,UINT16 size) -{ - PCITAG tag = ((atomBiosHandlePtr)CAIL)->PciTag; - - CAILFUNC(CAIL); - /*DEBUGP(ErrorF("%s(%x,%x)\n",__func__,idx,(*(unsigned int*)src)));*/ - switch (size) { - case 8: - pciWriteByte(tag,idx << 2,*(uint8_t*)src); - break; - case 16: - pciWriteWord(tag,idx << 2,*(uint16_t*)src); - break; - case 32: - pciWriteLong(tag,idx << 2,*(uint32_t*)src); - break; - default: - xf86DrvMsg(((atomBiosHandlePtr)CAIL)->scrnIndex,X_ERROR, - "%s: Unsupported size: %i\n",__func__,(int)size); - break; - } -} -#endif - -ULONG -CailReadPLL(VOID *CAIL, ULONG Address) -{ - ScrnInfoPtr pScrn = ((atomBiosHandlePtr)CAIL)->pScrn; - ULONG ret; - - CAILFUNC(CAIL); - - ret = RADEONINPLL(pScrn, Address); - /*DEBUGP(ErrorF("%s(%x) = %x\n",__func__,Address,ret));*/ - return ret; -} - -VOID -CailWritePLL(VOID *CAIL, ULONG Address,ULONG Data) -{ - ScrnInfoPtr pScrn = ((atomBiosHandlePtr)CAIL)->pScrn; - CAILFUNC(CAIL); - - /*DEBUGP(ErrorF("%s(%x,%x)\n",__func__,Address,Data));*/ - RADEONOUTPLL(pScrn, Address, Data); -} - -void -atombios_get_command_table_version(atomBiosHandlePtr atomBIOS, int index, int *major, int *minor) -{ - ATOM_MASTER_COMMAND_TABLE *cmd_table = (void *)(atomBIOS->BIOSBase + atomBIOS->cmd_offset); - ATOM_MASTER_LIST_OF_COMMAND_TABLES *table_start; - ATOM_COMMON_ROM_COMMAND_TABLE_HEADER *table_hdr; - - //unsigned short *ptr; - unsigned short offset; - - table_start = &cmd_table->ListOfCommandTables; - - offset = *(((unsigned short *)table_start) + index); - - offset = le16_to_cpu(offset); - table_hdr = (ATOM_COMMON_ROM_COMMAND_TABLE_HEADER *)(atomBIOS->BIOSBase + offset); - - *major = table_hdr->CommonHeader.ucTableFormatRevision; - *minor = table_hdr->CommonHeader.ucTableContentRevision; -} - - -UINT16 ATOM_BSWAP16(UINT16 x) -{ - return bswap_16(x); -} - -UINT32 ATOM_BSWAP32(UINT32 x) -{ - return bswap_32(x); -} - - -#endif /* ATOM_BIOS */ diff --git a/src/radeon_atombios.h b/src/radeon_atombios.h deleted file mode 100644 index 0671b8d0..00000000 --- a/src/radeon_atombios.h +++ /dev/null @@ -1,293 +0,0 @@ -/* - * Copyright 2007 Egbert Eich <eich@novell.com> - * Copyright 2007 Luc Verhaegen <lverhaegen@novell.com> - * Copyright 2007 Matthias Hopf <mhopf@novell.com> - * Copyright 2007 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - - -#ifndef RHD_ATOMBIOS_H_ -# define RHD_ATOMBIOS_H_ - -//#include "radeon.h" - -# ifdef ATOM_BIOS - -typedef enum _AtomBiosRequestID { - ATOMBIOS_INIT, - ATOMBIOS_TEARDOWN, -# ifdef ATOM_BIOS_PARSER - ATOMBIOS_EXEC, -#endif - ATOMBIOS_ALLOCATE_FB_SCRATCH, - ATOMBIOS_GET_CONNECTORS, - ATOMBIOS_GET_PANEL_MODE, - ATOMBIOS_GET_PANEL_EDID, - GET_DEFAULT_ENGINE_CLOCK, - GET_DEFAULT_MEMORY_CLOCK, - GET_MAX_PIXEL_CLOCK_PLL_OUTPUT, - GET_MIN_PIXEL_CLOCK_PLL_OUTPUT, - GET_MAX_PIXEL_CLOCK_PLL_INPUT, - GET_MIN_PIXEL_CLOCK_PLL_INPUT, - GET_MAX_PIXEL_CLK, - GET_REF_CLOCK, - GET_FW_FB_START, - GET_FW_FB_SIZE, - ATOM_TMDS_FREQUENCY, - ATOM_TMDS_PLL_CHARGE_PUMP, - ATOM_TMDS_PLL_DUTY_CYCLE, - ATOM_TMDS_PLL_VCO_GAIN, - ATOM_TMDS_PLL_VOLTAGE_SWING, - ATOM_LVDS_SUPPORTED_REFRESH_RATE, - ATOM_LVDS_OFF_DELAY, - ATOM_LVDS_SEQ_DIG_ONTO_DE, - ATOM_LVDS_SEQ_DE_TO_BL, - ATOM_LVDS_DITHER, - ATOM_LVDS_DUALLINK, - ATOM_LVDS_24BIT, - ATOM_LVDS_GREYLVL, - ATOM_LVDS_FPDI, - ATOM_GPIO_QUERIES, - ATOM_GPIO_I2C_CLK_MASK, - ATOM_DAC1_BG_ADJ, - ATOM_DAC1_DAC_ADJ, - ATOM_DAC1_FORCE, - ATOM_DAC2_CRTC2_BG_ADJ, - ATOM_DAC2_CRTC2_DAC_ADJ, - ATOM_DAC2_CRTC2_FORCE, - ATOM_DAC2_CRTC2_MUX_REG_IND, - ATOM_DAC2_CRTC2_MUX_REG_INFO, - ATOMBIOS_GET_CV_MODES, - FUNC_END -} AtomBiosRequestID; - -typedef enum _AtomBiosResult { - ATOM_SUCCESS, - ATOM_FAILED, - ATOM_NOT_IMPLEMENTED -} AtomBiosResult; - -typedef struct AtomExec { - int index; - pointer pspace; - pointer *dataSpace; -} AtomExecRec, *AtomExecPtr; - -typedef struct AtomFb { - unsigned int start; - unsigned int size; -} AtomFbRec, *AtomFbPtr; - -typedef union AtomBiosArg -{ - uint32_t val; - struct rhdConnectorInfo *connectorInfo; - unsigned char* EDIDBlock; - atomBiosHandlePtr atomhandle; - DisplayModePtr modes; - AtomExecRec exec; - AtomFbRec fb; - ScrnInfoPtr pScrn; -} AtomBiosArgRec, *AtomBiosArgPtr; - -extern AtomBiosResult -RHDAtomBiosFunc(ScrnInfoPtr pScrn, atomBiosHandlePtr handle, - AtomBiosRequestID id, AtomBiosArgPtr data); - -extern Bool -RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn); -extern Bool -RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn); - -extern int -atombios_clk_gating_setup(ScrnInfoPtr pScrn, Bool enable); - -extern int -atombios_static_pwrmgt_setup(ScrnInfoPtr pScrn, Bool enable); - -extern int -atombios_set_engine_clock(ScrnInfoPtr pScrn, uint32_t engclock); - -extern int -atombios_set_memory_clock(ScrnInfoPtr pScrn, uint32_t memclock); - -extern Bool -RADEONGetATOMTVInfo(xf86OutputPtr output); - -extern int -atombios_external_tmds_setup(xf86OutputPtr output, int action); - -extern void -atombios_get_command_table_version(atomBiosHandlePtr atomBIOS, int index, int *major, int *minor); - -extern xf86MonPtr -radeon_atom_get_edid(xf86OutputPtr output); - -Bool -rhdAtomASICInit(atomBiosHandlePtr handle); - -# include "xf86int10.h" -# ifdef ATOM_BIOS_PARSER -# define INT8 INT8 -# define INT16 INT16 -# define INT32 INT32 -# include "CD_Common_Types.h" -# else -# ifndef ULONG -typedef unsigned int ULONG; -# define ULONG ULONG -# endif -# ifndef UCHAR -typedef unsigned char UCHAR; -# define UCHAR UCHAR -# endif -# ifndef USHORT -typedef unsigned short USHORT; -# define USHORT USHORT -# endif -# endif - -# include "atombios.h" -# include "ObjectID.h" - - -/* - * This works around a bug in atombios.h where - * ATOM_MAX_SUPPORTED_DEVICE_INFO is specified incorrectly. - */ - -#define ATOM_MAX_SUPPORTED_DEVICE_INFO_HD (ATOM_DEVICE_RESERVEDF_INDEX+1) -typedef struct _ATOM_SUPPORTED_DEVICES_INFO_HD -{ - ATOM_COMMON_TABLE_HEADER sHeader; - USHORT usDeviceSupport; - ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_HD]; - ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_HD]; -} ATOM_SUPPORTED_DEVICES_INFO_HD; - -typedef struct _atomDataTables -{ - unsigned char *UtilityPipeLine; - ATOM_MULTIMEDIA_CAPABILITY_INFO *MultimediaCapabilityInfo; - ATOM_MULTIMEDIA_CONFIG_INFO *MultimediaConfigInfo; - ATOM_STANDARD_VESA_TIMING *StandardVESA_Timing; - union { - void *base; - ATOM_FIRMWARE_INFO *FirmwareInfo; - ATOM_FIRMWARE_INFO_V1_2 *FirmwareInfo_V_1_2; - ATOM_FIRMWARE_INFO_V1_3 *FirmwareInfo_V_1_3; - ATOM_FIRMWARE_INFO_V1_4 *FirmwareInfo_V_1_4; - ATOM_FIRMWARE_INFO_V2_1 *FirmwareInfo_V_2_1; - } FirmwareInfo; - ATOM_DAC_INFO *DAC_Info; - union { - void *base; - ATOM_LVDS_INFO *LVDS_Info; - ATOM_LVDS_INFO_V12 *LVDS_Info_v12; - } LVDS_Info; - ATOM_TMDS_INFO *TMDS_Info; - union { - void *base; - ATOM_ANALOG_TV_INFO *AnalogTV_Info; - ATOM_ANALOG_TV_INFO_V1_2 *AnalogTV_Info_v1_2; - } AnalogTV_Info; - union { - void *base; - ATOM_SUPPORTED_DEVICES_INFO *SupportedDevicesInfo; - ATOM_SUPPORTED_DEVICES_INFO_2 *SupportedDevicesInfo_2; - ATOM_SUPPORTED_DEVICES_INFO_2d1 *SupportedDevicesInfo_2d1; - ATOM_SUPPORTED_DEVICES_INFO_HD *SupportedDevicesInfo_HD; - } SupportedDevicesInfo; - ATOM_GPIO_I2C_INFO *GPIO_I2C_Info; - ATOM_VRAM_USAGE_BY_FIRMWARE *VRAM_UsageByFirmware; - ATOM_GPIO_PIN_LUT *GPIO_Pin_LUT; - ATOM_VESA_TO_INTENAL_MODE_LUT *VESA_ToInternalModeLUT; - union { - void *base; - ATOM_COMPONENT_VIDEO_INFO *ComponentVideoInfo; - ATOM_COMPONENT_VIDEO_INFO_V21 *ComponentVideoInfo_v21; - } ComponentVideoInfo; -/**/unsigned char *PowerPlayInfo; - COMPASSIONATE_DATA *CompassionateData; - ATOM_DISPLAY_DEVICE_PRIORITY_INFO *SaveRestoreInfo; -/**/unsigned char *PPLL_SS_Info; - ATOM_OEM_INFO *OemInfo; - ATOM_XTMDS_INFO *XTMDS_Info; - ATOM_ASIC_MVDD_INFO *MclkSS_Info; - ATOM_OBJECT_HEADER *Object_Header; - INDIRECT_IO_ACCESS *IndirectIOAccess; - ATOM_MC_INIT_PARAM_TABLE *MC_InitParameter; -/**/unsigned char *ASIC_VDDC_Info; - ATOM_ASIC_INTERNAL_SS_INFO *ASIC_InternalSS_Info; -/**/unsigned char *TV_VideoMode; - union { - void *base; - ATOM_VRAM_INFO_V2 *VRAM_Info_v2; - ATOM_VRAM_INFO_V3 *VRAM_Info_v3; - } VRAM_Info; - ATOM_MEMORY_TRAINING_INFO *MemoryTrainingInfo; - union { - void *base; - ATOM_INTEGRATED_SYSTEM_INFO *IntegratedSystemInfo; - ATOM_INTEGRATED_SYSTEM_INFO_V2 *IntegratedSystemInfo_v2; - } IntegratedSystemInfo; - ATOM_ASIC_PROFILING_INFO *ASIC_ProfilingInfo; - ATOM_VOLTAGE_OBJECT_INFO *VoltageObjectInfo; - ATOM_POWER_SOURCE_INFO *PowerSourceInfo; -} atomDataTables, *atomDataTablesPtr; - -typedef struct _atomBiosHandle { - ScrnInfoPtr pScrn; - unsigned char *BIOSBase; - atomDataTablesPtr atomDataPtr; - unsigned int cmd_offset; - pointer *scratchBase; - uint32_t fbBase; -#if XSERVER_LIBPCIACCESS - struct pci_device *device; -#else - PCITAG PciTag; -#endif - unsigned int BIOSImageSize; -} atomBiosHandleRec; - -# endif - -extern Bool -RADEONATOMGetTVTimings(ScrnInfoPtr pScrn, int index, DisplayModePtr mode); - -extern void -RADEONATOMGetIGPInfo(ScrnInfoPtr pScrn); - -extern Bool -RADEONGetATOMClockInfo(ScrnInfoPtr pScrn); - -extern uint32_t -radeon_get_device_index(uint32_t device_support); -extern radeon_encoder_ptr -radeon_get_encoder(xf86OutputPtr output); -extern Bool -radeon_add_encoder(ScrnInfoPtr pScrn, uint32_t encoder_id, uint32_t device_support); -extern uint32_t -radeon_get_encoder_id_from_supported_device(ScrnInfoPtr pScrn, uint32_t supported_device, int dac); - -void atombios_set_output_crtc_source(xf86OutputPtr output); -#endif /* RHD_ATOMBIOS_H_ */ diff --git a/src/radeon_atomwrapper.c b/src/radeon_atomwrapper.c deleted file mode 100644 index bed1471e..00000000 --- a/src/radeon_atomwrapper.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - * Copyright 2007 Luc Verhaegen <lverhaegen@novell.com> - * Copyright 2007 Matthias Hopf <mhopf@novell.com> - * Copyright 2007 Egbert Eich <eich@novell.com> - * Copyright 2007 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifdef HAVE_CONFIG_H -# include "config.h" -#endif - -#include "radeon_atomwrapper.h" - -#define INT32 INT32 -#include "CD_Common_Types.h" -#include "atombios.h" -#include "CD_Definitions.h" - - -int -ParseTableWrapper(void *pspace, int index, void *handle, void *BIOSBase, - char **msg_return) -{ - DEVICE_DATA deviceData; - int ret = 0; - - /* FILL OUT PARAMETER SPACE */ - deviceData.pParameterSpace = (UINT32*) pspace; - deviceData.CAIL = handle; - deviceData.pBIOS_Image = BIOSBase; - deviceData.format = TABLE_FORMAT_BIOS; - - switch (ParseTable(&deviceData, index)) { /* IndexInMasterTable */ - case CD_SUCCESS: - ret = 1; - *msg_return = "ParseTable said: CD_SUCCESS"; - break; - case CD_CALL_TABLE: - ret = 1; - *msg_return = "ParseTable said: CD_CALL_TABLE"; - break; - case CD_COMPLETED: - ret = 1; - *msg_return = "ParseTable said: CD_COMPLETED"; - break; - case CD_GENERAL_ERROR: - ret = 0; - *msg_return = " ParseTable said: CD_GENERAL_ERROR"; - break; - case CD_INVALID_OPCODE: - ret = 0; - *msg_return = " ParseTable said: CD_INVALID_OPCODE"; - break; - case CD_NOT_IMPLEMENTED: - ret = 0; - *msg_return = " ParseTable said: CD_NOT_IMPLEMENTED"; - break; - case CD_EXEC_TABLE_NOT_FOUND: - ret = 0; - *msg_return = " ParseTable said: CD_EXEC_TABLE_NOT_FOUND"; - break; - case CD_EXEC_PARAMETER_ERROR: - ret = 0; - *msg_return = " ParseTable said: CD_EXEC_PARAMETER_ERROR"; - break; - case CD_EXEC_PARSER_ERROR: - ret = 0; - *msg_return = " ParseTable said: CD_EXEC_PARSER_ERROR"; - break; - case CD_INVALID_DESTINATION_TYPE: - ret = 0; - *msg_return = " ParseTable said: CD_INVALID_DESTINATION_TYPE"; - break; - case CD_UNEXPECTED_BEHAVIOR: - ret = 0; - *msg_return = " ParseTable said: CD_UNEXPECTED_BEHAVIOR"; - break; - case CD_INVALID_SWITCH_OPERAND_SIZE: - ret = 0; - *msg_return = " ParseTable said: CD_INVALID_SWITCH_OPERAND_SIZE\n"; - break; - } - return ret; -} diff --git a/src/radeon_atomwrapper.h b/src/radeon_atomwrapper.h deleted file mode 100644 index 1e7cc773..00000000 --- a/src/radeon_atomwrapper.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright 2007 Luc Verhaegen <lverhaegen@novell.com> - * Copyright 2007 Matthias Hopf <mhopf@novell.com> - * Copyright 2007 Egbert Eich <eich@novell.com> - * Copyright 2007 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef RHD_ATOMWRAPPER_H_ -# define RHD_ATOMWRAPPER_H_ - -extern int ParseTableWrapper(void *pspace, int index, void *CAIL, - void *BIOSBase, char **msg_return); - -#endif /* RHD_ATOMWRAPPER_H_ */ diff --git a/src/radeon_bios.c b/src/radeon_bios.c deleted file mode 100644 index ffa12dfb..00000000 --- a/src/radeon_bios.c +++ /dev/null @@ -1,2052 +0,0 @@ -/* - * Copyright 2004 ATI Technologies Inc., Markham, Ontario - * - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation on the rights to use, copy, modify, merge, - * publish, distribute, sublicense, and/or sell copies of the Software, - * and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR - * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include <string.h> - -#include "xf86.h" -#include "xf86_OSproc.h" - -#include "atipciids.h" -#include "radeon.h" -#include "radeon_reg.h" -#include "radeon_macros.h" -#include "radeon_probe.h" -#include "radeon_atombios.h" - -typedef enum -{ - DDC_NONE_DETECTED, - DDC_MONID, - DDC_DVI, - DDC_VGA, - DDC_CRT2, - DDC_LCD, - DDC_GPIO, -} RADEONLegacyDDCType; - -typedef enum -{ - CONNECTOR_NONE_LEGACY, - CONNECTOR_PROPRIETARY_LEGACY, - CONNECTOR_CRT_LEGACY, - CONNECTOR_DVI_I_LEGACY, - CONNECTOR_DVI_D_LEGACY, - CONNECTOR_CTV_LEGACY, - CONNECTOR_STV_LEGACY, - CONNECTOR_UNSUPPORTED_LEGACY -} RADEONLegacyConnectorType; - -static Bool -radeon_read_bios(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - -#ifdef XSERVER_LIBPCIACCESS - if (pci_device_read_rom(info->PciInfo, info->VBIOS)) { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "Failed to read PCI ROM!\n"); - return FALSE; - } -#else - xf86ReadPciBIOS(0, info->PciTag, 0, info->VBIOS, RADEON_VBIOS_SIZE); - if (info->VBIOS[0] != 0x55 || info->VBIOS[1] != 0xaa) { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "Video BIOS not detected in PCI space!\n"); - if (xf86IsEntityPrimary(info->pEnt->index)) { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "Attempting to read Video BIOS from " - "legacy ISA space!\n"); - info->BIOSAddr = 0x000c0000; - xf86ReadDomainMemory(info->PciTag, info->BIOSAddr, - RADEON_VBIOS_SIZE, info->VBIOS); - } - } -#endif - if (info->VBIOS[0] != 0x55 || info->VBIOS[1] != 0xaa) - return FALSE; - else - return TRUE; -} - -static Bool -radeon_read_disabled_bios(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - Bool ret; - - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Attempting to read un-POSTed bios\n"); - - if (info->ChipFamily >= CHIP_FAMILY_RV770) { - uint32_t viph_control = INREG(RADEON_VIPH_CONTROL); - uint32_t bus_cntl = INREG(RADEON_BUS_CNTL); - uint32_t d1vga_control = INREG(AVIVO_D1VGA_CONTROL); - uint32_t d2vga_control = INREG(AVIVO_D2VGA_CONTROL); - uint32_t vga_render_control = INREG(AVIVO_VGA_RENDER_CONTROL); - uint32_t rom_cntl = INREG(R600_ROM_CNTL); - uint32_t cg_spll_func_cntl = 0; - uint32_t cg_spll_status; - - /* disable VIP */ - OUTREG(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); - - /* enable the rom */ - OUTREG(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); - - /* Disable VGA mode */ - OUTREG(AVIVO_D1VGA_CONTROL, (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | - AVIVO_DVGA_CONTROL_TIMING_SELECT))); - OUTREG(AVIVO_D2VGA_CONTROL, (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | - AVIVO_DVGA_CONTROL_TIMING_SELECT))); - OUTREG(AVIVO_VGA_RENDER_CONTROL, (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); - - if (info->ChipFamily == CHIP_FAMILY_RV730) { - cg_spll_func_cntl = INREG(R600_CG_SPLL_FUNC_CNTL); - - /* enable bypass mode */ - OUTREG(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl | R600_SPLL_BYPASS_EN)); - - /* wait for SPLL_CHG_STATUS to change to 1 */ - cg_spll_status = 0; - while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) - cg_spll_status = INREG(R600_CG_SPLL_STATUS); - - OUTREG(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE)); - } else - OUTREG(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE)); - - ret = radeon_read_bios(pScrn); - - /* restore regs */ - if (info->ChipFamily == CHIP_FAMILY_RV730) { - OUTREG(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl); - - /* wait for SPLL_CHG_STATUS to change to 1 */ - cg_spll_status = 0; - while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) - cg_spll_status = INREG(R600_CG_SPLL_STATUS); - } - OUTREG(RADEON_VIPH_CONTROL, viph_control); - OUTREG(RADEON_BUS_CNTL, bus_cntl); - OUTREG(AVIVO_D1VGA_CONTROL, d1vga_control); - OUTREG(AVIVO_D2VGA_CONTROL, d2vga_control); - OUTREG(AVIVO_VGA_RENDER_CONTROL, vga_render_control); - OUTREG(R600_ROM_CNTL, rom_cntl); - } else if (info->ChipFamily >= CHIP_FAMILY_R600) { - uint32_t viph_control = INREG(RADEON_VIPH_CONTROL); - uint32_t bus_cntl = INREG(RADEON_BUS_CNTL); - uint32_t d1vga_control = INREG(AVIVO_D1VGA_CONTROL); - uint32_t d2vga_control = INREG(AVIVO_D2VGA_CONTROL); - uint32_t vga_render_control = INREG(AVIVO_VGA_RENDER_CONTROL); - uint32_t rom_cntl = INREG(R600_ROM_CNTL); - uint32_t general_pwrmgt = INREG(R600_GENERAL_PWRMGT); - uint32_t low_vid_lower_gpio_cntl = INREG(R600_LOW_VID_LOWER_GPIO_CNTL); - uint32_t medium_vid_lower_gpio_cntl = INREG(R600_MEDIUM_VID_LOWER_GPIO_CNTL); - uint32_t high_vid_lower_gpio_cntl = INREG(R600_HIGH_VID_LOWER_GPIO_CNTL); - uint32_t ctxsw_vid_lower_gpio_cntl = INREG(R600_CTXSW_VID_LOWER_GPIO_CNTL); - uint32_t lower_gpio_enable = INREG(R600_LOWER_GPIO_ENABLE); - - /* disable VIP */ - OUTREG(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); - - /* enable the rom */ - OUTREG(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); - - /* Disable VGA mode */ - OUTREG(AVIVO_D1VGA_CONTROL, (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | - AVIVO_DVGA_CONTROL_TIMING_SELECT))); - OUTREG(AVIVO_D2VGA_CONTROL, (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | - AVIVO_DVGA_CONTROL_TIMING_SELECT))); - OUTREG(AVIVO_VGA_RENDER_CONTROL, (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); - - OUTREG(R600_ROM_CNTL, ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) | - (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) | - R600_SCK_OVERWRITE)); - - OUTREG(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS)); - - OUTREG(R600_LOW_VID_LOWER_GPIO_CNTL, (low_vid_lower_gpio_cntl & ~0x400)); - - OUTREG(R600_MEDIUM_VID_LOWER_GPIO_CNTL, (medium_vid_lower_gpio_cntl & ~0x400)); - - OUTREG(R600_HIGH_VID_LOWER_GPIO_CNTL, (high_vid_lower_gpio_cntl & ~0x400)); - - OUTREG(R600_CTXSW_VID_LOWER_GPIO_CNTL, (ctxsw_vid_lower_gpio_cntl & ~0x400)); - - OUTREG(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400)); - - ret = radeon_read_bios(pScrn); - - /* restore regs */ - OUTREG(RADEON_VIPH_CONTROL, viph_control); - OUTREG(RADEON_BUS_CNTL, bus_cntl); - OUTREG(AVIVO_D1VGA_CONTROL, d1vga_control); - OUTREG(AVIVO_D2VGA_CONTROL, d2vga_control); - OUTREG(AVIVO_VGA_RENDER_CONTROL, vga_render_control); - OUTREG(R600_ROM_CNTL, rom_cntl); - OUTREG(R600_GENERAL_PWRMGT, general_pwrmgt); - OUTREG(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl); - OUTREG(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl); - OUTREG(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl); - OUTREG(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl); - OUTREG(R600_LOWER_GPIO_ENABLE, lower_gpio_enable); - - } else if (info->ChipFamily >= CHIP_FAMILY_RV515) { - uint32_t seprom_cntl1 = INREG(RADEON_SEPROM_CNTL1); - uint32_t viph_control = INREG(RADEON_VIPH_CONTROL); - uint32_t bus_cntl = INREG(RADEON_BUS_CNTL); - uint32_t d1vga_control = INREG(AVIVO_D1VGA_CONTROL); - uint32_t d2vga_control = INREG(AVIVO_D2VGA_CONTROL); - uint32_t vga_render_control = INREG(AVIVO_VGA_RENDER_CONTROL); - uint32_t gpiopad_a = INREG(RADEON_GPIOPAD_A); - uint32_t gpiopad_en = INREG(RADEON_GPIOPAD_EN); - uint32_t gpiopad_mask = INREG(RADEON_GPIOPAD_MASK); - - OUTREG(RADEON_SEPROM_CNTL1, ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | - (0xc << RADEON_SCK_PRESCALE_SHIFT))); - - OUTREG(RADEON_GPIOPAD_A, 0); - OUTREG(RADEON_GPIOPAD_EN, 0); - OUTREG(RADEON_GPIOPAD_MASK, 0); - - /* disable VIP */ - OUTREG(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); - - /* enable the rom */ - OUTREG(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); - - /* Disable VGA mode */ - OUTREG(AVIVO_D1VGA_CONTROL, (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | - AVIVO_DVGA_CONTROL_TIMING_SELECT))); - OUTREG(AVIVO_D2VGA_CONTROL, (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | - AVIVO_DVGA_CONTROL_TIMING_SELECT))); - OUTREG(AVIVO_VGA_RENDER_CONTROL, (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); - - ret = radeon_read_bios(pScrn); - - /* restore regs */ - OUTREG(RADEON_SEPROM_CNTL1, seprom_cntl1); - OUTREG(RADEON_VIPH_CONTROL, viph_control); - OUTREG(RADEON_BUS_CNTL, bus_cntl); - OUTREG(AVIVO_D1VGA_CONTROL, d1vga_control); - OUTREG(AVIVO_D2VGA_CONTROL, d2vga_control); - OUTREG(AVIVO_VGA_RENDER_CONTROL, vga_render_control); - OUTREG(RADEON_GPIOPAD_A, gpiopad_a); - OUTREG(RADEON_GPIOPAD_EN, gpiopad_en); - OUTREG(RADEON_GPIOPAD_MASK, gpiopad_mask); - - } else { - uint32_t seprom_cntl1 = INREG(RADEON_SEPROM_CNTL1); - uint32_t viph_control = INREG(RADEON_VIPH_CONTROL); - uint32_t bus_cntl = INREG(RADEON_BUS_CNTL); - uint32_t crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL); - uint32_t crtc2_gen_cntl = 0; - uint32_t crtc_ext_cntl = INREG(RADEON_CRTC_EXT_CNTL); - uint32_t fp2_gen_cntl = 0; - - if (PCI_DEV_DEVICE_ID(info->PciInfo) == PCI_CHIP_RV100_QY) - fp2_gen_cntl = INREG(RADEON_FP2_GEN_CNTL); - - if (pRADEONEnt->HasCRTC2) - crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL); - - OUTREG(RADEON_SEPROM_CNTL1, ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | - (0xc << RADEON_SCK_PRESCALE_SHIFT))); - - /* disable VIP */ - OUTREG(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); - - /* enable the rom */ - OUTREG(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); - - /* Turn off mem requests and CRTC for both controllers */ - OUTREG(RADEON_CRTC_GEN_CNTL, ((crtc_gen_cntl & ~RADEON_CRTC_EN) | - (RADEON_CRTC_DISP_REQ_EN_B | - RADEON_CRTC_EXT_DISP_EN))); - if (pRADEONEnt->HasCRTC2) - OUTREG(RADEON_CRTC2_GEN_CNTL, ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) | - RADEON_CRTC2_DISP_REQ_EN_B)); - - /* Turn off CRTC */ - OUTREG(RADEON_CRTC_EXT_CNTL, ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) | - (RADEON_CRTC_SYNC_TRISTAT | - RADEON_CRTC_DISPLAY_DIS))); - - if (PCI_DEV_DEVICE_ID(info->PciInfo) == PCI_CHIP_RV100_QY) - OUTREG(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON)); - - ret = radeon_read_bios(pScrn); - - /* restore regs */ - OUTREG(RADEON_SEPROM_CNTL1, seprom_cntl1); - OUTREG(RADEON_VIPH_CONTROL, viph_control); - OUTREG(RADEON_BUS_CNTL, bus_cntl); - OUTREG(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); - if (pRADEONEnt->HasCRTC2) - OUTREG(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); - OUTREG(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); - if (PCI_DEV_DEVICE_ID(info->PciInfo) == PCI_CHIP_RV100_QY) - OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); - } - return ret; -} - -Bool -radeon_card_posted(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - uint32_t reg; - - /* first check CRTCs */ - if (IS_AVIVO_VARIANT) { - reg = INREG(AVIVO_D1CRTC_CONTROL) | INREG(AVIVO_D2CRTC_CONTROL); - if (reg & AVIVO_CRTC_EN) - return TRUE; - } else { - reg = INREG(RADEON_CRTC_GEN_CNTL) | INREG(RADEON_CRTC2_GEN_CNTL); - if (reg & RADEON_CRTC_EN) - return TRUE; - } - - /* then check MEM_SIZE, in case something turned the crtcs off */ - if (info->ChipFamily >= CHIP_FAMILY_R600) - reg = INREG(R600_CONFIG_MEMSIZE); - else - reg = INREG(RADEON_CONFIG_MEMSIZE); - - if (reg) - return TRUE; - - return FALSE; -} - -/* Read the Video BIOS block and the FP registers (if applicable). */ -Bool -RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - int tmp; - unsigned short dptr; - -#ifdef XSERVER_LIBPCIACCESS - int size = info->PciInfo->rom_size > RADEON_VBIOS_SIZE ? info->PciInfo->rom_size : RADEON_VBIOS_SIZE; - info->VBIOS = malloc(size); -#else - info->VBIOS = malloc(RADEON_VBIOS_SIZE); -#endif - if (!info->VBIOS) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Cannot allocate space for hold Video BIOS!\n"); - return FALSE; - } else { - if (pInt10) { - info->BIOSAddr = pInt10->BIOSseg << 4; - (void)memcpy(info->VBIOS, xf86int10Addr(pInt10, info->BIOSAddr), - RADEON_VBIOS_SIZE); - } else if (!radeon_read_bios(pScrn)) - (void)radeon_read_disabled_bios(pScrn); - } - - if (info->VBIOS[0] != 0x55 || info->VBIOS[1] != 0xaa) { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "Unrecognized BIOS signature, BIOS data will not be used\n"); - free (info->VBIOS); - info->VBIOS = NULL; - return FALSE; - } - - /* Verify it's an x86 BIOS not OF firmware, copied from radeonfb */ - dptr = RADEON_BIOS16(0x18); - /* If PCI data signature is wrong assume x86 video BIOS anyway */ - if (RADEON_BIOS32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "ROM PCI data signature incorrect, ignoring\n"); - } - else if (info->VBIOS[dptr + 0x14] != 0x0) { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "Not an x86 BIOS ROM image, BIOS data will not be used\n"); - free (info->VBIOS); - info->VBIOS = NULL; - return FALSE; - } - - if (info->VBIOS) info->ROMHeaderStart = RADEON_BIOS16(0x48); - - if(!info->ROMHeaderStart) { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "Invalid ROM pointer, BIOS data will not be used\n"); - free (info->VBIOS); - info->VBIOS = NULL; - return FALSE; - } - - tmp = info->ROMHeaderStart + 4; - if ((RADEON_BIOS8(tmp) == 'A' && - RADEON_BIOS8(tmp+1) == 'T' && - RADEON_BIOS8(tmp+2) == 'O' && - RADEON_BIOS8(tmp+3) == 'M') || - (RADEON_BIOS8(tmp) == 'M' && - RADEON_BIOS8(tmp+1) == 'O' && - RADEON_BIOS8(tmp+2) == 'T' && - RADEON_BIOS8(tmp+3) == 'A')) - info->IsAtomBios = TRUE; - else - info->IsAtomBios = FALSE; - - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "%s BIOS detected\n", - info->IsAtomBios ? "ATOM":"Legacy"); - - if (info->IsAtomBios) { - AtomBiosArgRec atomBiosArg; - - if (RHDAtomBiosFunc(pScrn, NULL, ATOMBIOS_INIT, &atomBiosArg) - == ATOM_SUCCESS) { - info->atomBIOS = atomBiosArg.atomhandle; - } - - atomBiosArg.fb.start = info->FbFreeStart; - atomBiosArg.fb.size = info->FbFreeSize; - if (RHDAtomBiosFunc(pScrn, info->atomBIOS, ATOMBIOS_ALLOCATE_FB_SCRATCH, - &atomBiosArg) == ATOM_SUCCESS) { - - info->FbFreeStart = atomBiosArg.fb.start; - info->FbFreeSize = atomBiosArg.fb.size; - } - - RHDAtomBiosFunc(pScrn, info->atomBIOS, GET_DEFAULT_ENGINE_CLOCK, - &atomBiosArg); - RHDAtomBiosFunc(pScrn, info->atomBIOS, GET_DEFAULT_MEMORY_CLOCK, - &atomBiosArg); - RHDAtomBiosFunc(pScrn, info->atomBIOS, - GET_MAX_PIXEL_CLOCK_PLL_OUTPUT, &atomBiosArg); - RHDAtomBiosFunc(pScrn, info->atomBIOS, - GET_MIN_PIXEL_CLOCK_PLL_OUTPUT, &atomBiosArg); - RHDAtomBiosFunc(pScrn, info->atomBIOS, - GET_MAX_PIXEL_CLOCK_PLL_INPUT, &atomBiosArg); - RHDAtomBiosFunc(pScrn, info->atomBIOS, - GET_MIN_PIXEL_CLOCK_PLL_INPUT, &atomBiosArg); - RHDAtomBiosFunc(pScrn, info->atomBIOS, - GET_MAX_PIXEL_CLK, &atomBiosArg); - RHDAtomBiosFunc(pScrn, info->atomBIOS, - GET_REF_CLOCK, &atomBiosArg); - - info->MasterDataStart = RADEON_BIOS16 (info->ROMHeaderStart + 32); - } - - /* We are a bit too quick at using this "unposted" to re-post the - * card. This causes some problems with VT switch on some machines, - * so let's work around this for now by only POSTing if none of the - * CRTCs are enabled - */ - if ((!radeon_card_posted(pScrn)) && info->VBIOS) { - if (info->IsAtomBios) { - if (!rhdAtomASICInit(info->atomBIOS)) - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "%s: AsicInit failed.\n",__func__); - } else { -#if 0 - /* FIX ME */ - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Attempting to POST via legacy BIOS tables\n"); - RADEONGetBIOSInitTableOffsets(pScrn); - RADEONPostCardFromBIOSTables(pScrn); -#endif - } - } - - return TRUE; -} - -static Bool RADEONGetATOMConnectorInfoFromBIOS (ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR (pScrn); - - if (!info->VBIOS) return FALSE; - - if (RADEONGetATOMConnectorInfoFromBIOSObject(pScrn)) - return TRUE; - - if (RADEONGetATOMConnectorInfoFromBIOSConnectorTable(pScrn)) - return TRUE; - - return FALSE; -} - -static void RADEONApplyLegacyQuirks(ScrnInfoPtr pScrn, int index) -{ - RADEONInfoPtr info = RADEONPTR (pScrn); - - /* XPRESS DDC quirks */ - if ((info->ChipFamily == CHIP_FAMILY_RS400 || - info->ChipFamily == CHIP_FAMILY_RS480) && - info->BiosConnector[index].ddc_i2c.mask_clk_reg == RADEON_GPIO_CRT2_DDC) { - info->BiosConnector[index].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_MONID); - } else if ((info->ChipFamily == CHIP_FAMILY_RS400 || - info->ChipFamily == CHIP_FAMILY_RS480) && - info->BiosConnector[index].ddc_i2c.mask_clk_reg == RADEON_GPIO_MONID) { - info->BiosConnector[index].ddc_i2c.valid = TRUE; - info->BiosConnector[index].ddc_i2c.mask_clk_mask = (0x20 << 8); - info->BiosConnector[index].ddc_i2c.mask_data_mask = 0x80; - info->BiosConnector[index].ddc_i2c.a_clk_mask = (0x20 << 8); - info->BiosConnector[index].ddc_i2c.a_data_mask = 0x80; - info->BiosConnector[index].ddc_i2c.put_clk_mask = (0x20 << 8); - info->BiosConnector[index].ddc_i2c.put_data_mask = 0x80; - info->BiosConnector[index].ddc_i2c.get_clk_mask = (0x20 << 8); - info->BiosConnector[index].ddc_i2c.get_data_mask = 0x80; - info->BiosConnector[index].ddc_i2c.mask_clk_reg = RADEON_GPIOPAD_MASK; - info->BiosConnector[index].ddc_i2c.mask_data_reg = RADEON_GPIOPAD_MASK; - info->BiosConnector[index].ddc_i2c.a_clk_reg = RADEON_GPIOPAD_A; - info->BiosConnector[index].ddc_i2c.a_data_reg = RADEON_GPIOPAD_A; - info->BiosConnector[index].ddc_i2c.put_clk_reg = RADEON_GPIOPAD_EN; - info->BiosConnector[index].ddc_i2c.put_data_reg = RADEON_GPIOPAD_EN; - info->BiosConnector[index].ddc_i2c.get_clk_reg = RADEON_LCD_GPIO_Y_REG; - info->BiosConnector[index].ddc_i2c.get_data_reg = RADEON_LCD_GPIO_Y_REG; - } - - /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */ - if ((IS_R300_VARIANT) && - info->BiosConnector[index].ddc_i2c.mask_clk_reg == RADEON_GPIO_CRT2_DDC) - info->BiosConnector[index].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC); - - /* Certain IBM chipset RN50s have a BIOS reporting two VGAs, - one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */ - if (info->Chipset == PCI_CHIP_RN50_515E && - PCI_SUB_VENDOR_ID(info->PciInfo) == 0x1014) { - if (info->BiosConnector[index].ConnectorType == CONNECTOR_VGA && - info->BiosConnector[index].ddc_i2c.mask_clk_reg == RADEON_GPIO_CRT2_DDC) { - info->BiosConnector[index].valid = FALSE; - } - } - - /* X300 card with extra non-existent DVI port */ - if (info->Chipset == PCI_CHIP_RV370_5B60 && - PCI_SUB_VENDOR_ID(info->PciInfo) == 0x17af && - PCI_SUB_DEVICE_ID(info->PciInfo) == 0x201e && - index == 2) { - if (info->BiosConnector[index].ConnectorType == CONNECTOR_DVI_I) { - info->BiosConnector[index].valid = FALSE; - } - } - - /* r200 card with primary dac routed to both VGA and DVI - disable load detection - * otherwise you end up detecing load if either port is attached - */ - if (info->Chipset == PCI_CHIP_R200_QL && - PCI_SUB_VENDOR_ID(info->PciInfo) == 0x1569 && - PCI_SUB_DEVICE_ID(info->PciInfo) == 0x514c && - (info->BiosConnector[index].devices & ATOM_DEVICE_CRT1_SUPPORT)) { - info->BiosConnector[index].load_detection = FALSE; - } - -} - -static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR (pScrn); - int offset, i, entry, tmp, tmp0, tmp1; - RADEONLegacyDDCType DDCType; - RADEONLegacyConnectorType ConnectorType; - - if (!info->VBIOS) return FALSE; - - offset = RADEON_BIOS16(info->ROMHeaderStart + 0x50); - if (offset) { - for (i = 0; i < 4; i++) { - entry = offset + 2 + i*2; - - if (!RADEON_BIOS16(entry)) { - break; - } - info->BiosConnector[i].valid = TRUE; - tmp = RADEON_BIOS16(entry); - info->BiosConnector[i].ConnectorType = (tmp >> 12) & 0xf; - ConnectorType = (tmp >> 12) & 0xf; - switch (ConnectorType) { - case CONNECTOR_PROPRIETARY_LEGACY: - info->BiosConnector[i].ConnectorType = CONNECTOR_DVI_D; - if ((tmp >> 4) & 0x1) { - info->BiosConnector[i].devices |= ATOM_DEVICE_DFP2_SUPPORT; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_DFP2_SUPPORT, - 0), - ATOM_DEVICE_DFP2_SUPPORT)) - return FALSE; - } else { - info->BiosConnector[i].devices |= ATOM_DEVICE_DFP1_SUPPORT; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_DFP1_SUPPORT, - 0), - ATOM_DEVICE_DFP1_SUPPORT)) - return FALSE; - } - break; - case CONNECTOR_CRT_LEGACY: - info->BiosConnector[i].ConnectorType = CONNECTOR_VGA; - if (tmp & 0x1) { - info->BiosConnector[i].load_detection = FALSE; - info->BiosConnector[i].devices |= ATOM_DEVICE_CRT2_SUPPORT; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_CRT2_SUPPORT, - 2), - ATOM_DEVICE_CRT2_SUPPORT)) - return FALSE; - } else { - info->BiosConnector[i].load_detection = TRUE; - info->BiosConnector[i].devices |= ATOM_DEVICE_CRT1_SUPPORT; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_CRT1_SUPPORT, - 1), - ATOM_DEVICE_CRT1_SUPPORT)) - return FALSE; - } - break; - case CONNECTOR_DVI_I_LEGACY: - info->BiosConnector[i].ConnectorType = CONNECTOR_DVI_I; - if (tmp & 0x1) { - info->BiosConnector[i].load_detection = FALSE; - info->BiosConnector[i].devices |= ATOM_DEVICE_CRT2_SUPPORT; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_CRT2_SUPPORT, - 2), - ATOM_DEVICE_CRT2_SUPPORT)) - return FALSE; - } else { - info->BiosConnector[i].load_detection = TRUE; - info->BiosConnector[i].devices |= ATOM_DEVICE_CRT1_SUPPORT; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_CRT1_SUPPORT, - 1), - ATOM_DEVICE_CRT1_SUPPORT)) - return FALSE; - } - if ((tmp >> 4) & 0x1) { - info->BiosConnector[i].devices |= ATOM_DEVICE_DFP2_SUPPORT; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_DFP2_SUPPORT, - 0), - ATOM_DEVICE_DFP2_SUPPORT)) - return FALSE; - } else { - info->BiosConnector[i].devices |= ATOM_DEVICE_DFP1_SUPPORT; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_DFP1_SUPPORT, - 0), - ATOM_DEVICE_DFP1_SUPPORT)) - return FALSE; - } - break; - case CONNECTOR_DVI_D_LEGACY: - info->BiosConnector[i].ConnectorType = CONNECTOR_DVI_D; - if ((tmp >> 4) & 0x1) { - info->BiosConnector[i].devices |= ATOM_DEVICE_DFP2_SUPPORT; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_DFP2_SUPPORT, - 0), - ATOM_DEVICE_DFP2_SUPPORT)) - return FALSE; - } else { - info->BiosConnector[i].devices |= ATOM_DEVICE_DFP1_SUPPORT; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_DFP1_SUPPORT, - 0), - ATOM_DEVICE_DFP1_SUPPORT)) - return FALSE; - } - break; - case CONNECTOR_CTV_LEGACY: - info->BiosConnector[i].ConnectorType = CONNECTOR_CTV; - info->BiosConnector[i].load_detection = FALSE; - info->BiosConnector[i].devices = ATOM_DEVICE_TV1_SUPPORT; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_TV1_SUPPORT, - 2), - ATOM_DEVICE_TV1_SUPPORT)) - return FALSE; - break; - case CONNECTOR_STV_LEGACY: - info->BiosConnector[i].ConnectorType = CONNECTOR_STV; - info->BiosConnector[i].load_detection = FALSE; - info->BiosConnector[i].devices = ATOM_DEVICE_TV1_SUPPORT; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_TV1_SUPPORT, - 2), - ATOM_DEVICE_TV1_SUPPORT)) - return FALSE; - break; - default: - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unknown Connector Type: %d\n", ConnectorType); - info->BiosConnector[i].valid = FALSE; - break; - } - - info->BiosConnector[i].ddc_i2c.valid = FALSE; - - DDCType = (tmp >> 8) & 0xf; - switch (DDCType) { - case DDC_MONID: - info->BiosConnector[i].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_MONID); - break; - case DDC_DVI: - info->BiosConnector[i].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC); - break; - case DDC_VGA: - info->BiosConnector[i].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC); - break; - case DDC_CRT2: - info->BiosConnector[i].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_CRT2_DDC); - break; - default: - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unknown DDC Type: %d\n", DDCType); - break; - } - - RADEONApplyLegacyQuirks(pScrn, i); - - } - } else { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "No Connector Info Table found!\n"); - - /* old radeons and r128 didn't use connector tables you just check - * for LVDS, DVI, TV, etc. tables - */ - offset = RADEON_BIOS16(info->ROMHeaderStart + 0x34); - if (offset) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Found DFP table, assuming DVI connector\n"); - info->BiosConnector[0].valid = TRUE; - info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_I; - info->BiosConnector[0].load_detection = TRUE; - info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC); - info->BiosConnector[0].devices = ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_DFP1_SUPPORT; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_DFP1_SUPPORT, - 0), - ATOM_DEVICE_DFP1_SUPPORT)) - return FALSE; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_CRT1_SUPPORT, - 1), - ATOM_DEVICE_CRT1_SUPPORT)) - return FALSE; - } else - return FALSE; - } - - /* check LVDS table */ - /* IGP can be mobile or desktop so check the connectors */ - if (info->IsMobility || info->IsIGP) { - offset = RADEON_BIOS16(info->ROMHeaderStart + 0x40); - if (offset) { - info->BiosConnector[4].valid = TRUE; - info->BiosConnector[4].ConnectorType = CONNECTOR_LVDS; - info->BiosConnector[4].ddc_i2c.valid = FALSE; - - info->BiosConnector[4].devices = ATOM_DEVICE_LCD1_SUPPORT; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_LCD1_SUPPORT, - 0), - ATOM_DEVICE_LCD1_SUPPORT)) - return FALSE; - - tmp = RADEON_BIOS16(info->ROMHeaderStart + 0x42); - if (tmp) { - tmp0 = RADEON_BIOS16(tmp + 0x15); - if (tmp0) { - tmp1 = RADEON_BIOS8(tmp0+2) & 0x07; - if (tmp1) { - DDCType = tmp1; - switch (DDCType) { - case DDC_NONE_DETECTED: - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "No DDC for LCD\n"); - break; - case DDC_MONID: - info->BiosConnector[4].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_MONID); - break; - case DDC_DVI: - info->BiosConnector[4].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC); - break; - case DDC_VGA: - info->BiosConnector[4].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC); - break; - case DDC_CRT2: - info->BiosConnector[4].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_CRT2_DDC); - break; - case DDC_LCD: - info->BiosConnector[4].ddc_i2c = legacy_setup_i2c_bus(RADEON_LCD_GPIO_MASK); - info->BiosConnector[4].ddc_i2c.mask_clk_mask = RADEON_BIOS32(tmp0 + 0x03); - info->BiosConnector[4].ddc_i2c.mask_data_mask = RADEON_BIOS32(tmp0 + 0x07); - info->BiosConnector[4].ddc_i2c.a_clk_mask = RADEON_BIOS32(tmp0 + 0x03); - info->BiosConnector[4].ddc_i2c.a_data_mask = RADEON_BIOS32(tmp0 + 0x07); - info->BiosConnector[4].ddc_i2c.put_clk_mask = RADEON_BIOS32(tmp0 + 0x03); - info->BiosConnector[4].ddc_i2c.put_data_mask = RADEON_BIOS32(tmp0 + 0x07); - info->BiosConnector[4].ddc_i2c.get_clk_mask = RADEON_BIOS32(tmp0 + 0x03); - info->BiosConnector[4].ddc_i2c.get_data_mask = RADEON_BIOS32(tmp0 + 0x07); - break; - case DDC_GPIO: - info->BiosConnector[4].ddc_i2c = legacy_setup_i2c_bus(RADEON_MDGPIO_EN_REG); - info->BiosConnector[4].ddc_i2c.mask_clk_mask = RADEON_BIOS32(tmp0 + 0x03); - info->BiosConnector[4].ddc_i2c.mask_data_mask = RADEON_BIOS32(tmp0 + 0x07); - info->BiosConnector[4].ddc_i2c.a_clk_mask = RADEON_BIOS32(tmp0 + 0x03); - info->BiosConnector[4].ddc_i2c.a_data_mask = RADEON_BIOS32(tmp0 + 0x07); - info->BiosConnector[4].ddc_i2c.put_clk_mask = RADEON_BIOS32(tmp0 + 0x03); - info->BiosConnector[4].ddc_i2c.put_data_mask = RADEON_BIOS32(tmp0 + 0x07); - info->BiosConnector[4].ddc_i2c.get_clk_mask = RADEON_BIOS32(tmp0 + 0x03); - info->BiosConnector[4].ddc_i2c.get_data_mask = RADEON_BIOS32(tmp0 + 0x07); - break; - default: - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unknown DDC Type: %d\n", DDCType); - break; - } - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "LCD DDC Info Table found!\n"); - } - } - } else - info->BiosConnector[4].ddc_i2c.valid = FALSE; - } - } - - /* check TV table */ - if (info->InternalTVOut) { - offset = RADEON_BIOS16(info->ROMHeaderStart + 0x32); - if (offset) { - if (RADEON_BIOS8(offset + 6) == 'T') { - info->BiosConnector[5].valid = TRUE; - /* assume s-video for now */ - info->BiosConnector[5].ConnectorType = CONNECTOR_STV; - info->BiosConnector[5].load_detection = FALSE; - info->BiosConnector[5].ddc_i2c.valid = FALSE; - info->BiosConnector[5].devices = ATOM_DEVICE_TV1_SUPPORT; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_TV1_SUPPORT, - 2), - ATOM_DEVICE_TV1_SUPPORT)) - return FALSE; - } - } - } - - return TRUE; -} - -Bool RADEONGetConnectorInfoFromBIOS (ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR (pScrn); - - if(!info->VBIOS) return FALSE; - - if (info->IsAtomBios) - return RADEONGetATOMConnectorInfoFromBIOS(pScrn); - else - return RADEONGetLegacyConnectorInfoFromBIOS(pScrn); -} - -Bool RADEONGetTVInfoFromBIOS (xf86OutputPtr output) { - ScrnInfoPtr pScrn = output->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONOutputPrivatePtr radeon_output = output->driver_private; - radeon_tvout_ptr tvout = &radeon_output->tvout; - int offset, refclk, stds; - - if (!info->VBIOS) return FALSE; - - if (info->IsAtomBios) - return RADEONGetATOMTVInfo(output); - else { - offset = RADEON_BIOS16(info->ROMHeaderStart + 0x32); - if (offset) { - if (RADEON_BIOS8(offset + 6) == 'T') { - switch (RADEON_BIOS8(offset + 7) & 0xf) { - case 1: - tvout->default_tvStd = TV_STD_NTSC; - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: NTSC\n"); - break; - case 2: - tvout->default_tvStd = TV_STD_PAL; - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: PAL\n"); - break; - case 3: - tvout->default_tvStd = TV_STD_PAL_M; - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: PAL-M\n"); - break; - case 4: - tvout->default_tvStd = TV_STD_PAL_60; - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: PAL-60\n"); - break; - case 5: - tvout->default_tvStd = TV_STD_NTSC_J; - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: NTSC-J\n"); - break; - case 6: - tvout->default_tvStd = TV_STD_SCART_PAL; - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Default TV standard: SCART-PAL\n"); - break; - default: - tvout->default_tvStd = TV_STD_NTSC; - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Unknown TV standard; defaulting to NTSC\n"); - break; - } - tvout->tvStd = tvout->default_tvStd; - - refclk = (RADEON_BIOS8(offset + 9) >> 2) & 0x3; - if (refclk == 0) - tvout->TVRefClk = 29.498928713; /* MHz */ - else if (refclk == 1) - tvout->TVRefClk = 28.636360000; - else if (refclk == 2) - tvout->TVRefClk = 14.318180000; - else if (refclk == 3) - tvout->TVRefClk = 27.000000000; - - tvout->SupportedTVStds = tvout->default_tvStd; - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "TV standards supported by chip: "); - stds = RADEON_BIOS8(offset + 10) & 0x1f; - if (stds & TV_STD_NTSC) { - tvout->SupportedTVStds |= TV_STD_NTSC; - ErrorF("NTSC "); - } - if (stds & TV_STD_PAL) { - tvout->SupportedTVStds |= TV_STD_PAL; - ErrorF("PAL "); - } - if (stds & TV_STD_PAL_M) { - tvout->SupportedTVStds |= TV_STD_PAL_M; - ErrorF("PAL-M "); - } - if (stds & TV_STD_PAL_60) { - tvout->SupportedTVStds |= TV_STD_PAL_60; - ErrorF("PAL-60 "); - } - if (stds & TV_STD_NTSC_J) { - tvout->SupportedTVStds |= TV_STD_NTSC_J; - ErrorF("NTSC-J "); - } - if (stds & TV_STD_SCART_PAL) { - tvout->SupportedTVStds |= TV_STD_SCART_PAL; - ErrorF("SCART-PAL"); - } - ErrorF("\n"); - - return TRUE; - } - } - } - return FALSE; -} - -/* Read PLL parameters from BIOS block. Default to typical values if there - is no BIOS. */ -Bool RADEONGetClockInfoFromBIOS (ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR (pScrn); - RADEONPLLPtr pll = &info->pll; - uint16_t pll_info_block; - - if (!info->VBIOS) { - return FALSE; - } else { - if (info->IsAtomBios) { - return RADEONGetATOMClockInfo(pScrn); - } else { - int rev; - - pll_info_block = RADEON_BIOS16 (info->ROMHeaderStart + 0x30); - - rev = RADEON_BIOS8(pll_info_block); - - pll->reference_freq = RADEON_BIOS16 (pll_info_block + 0x0e); - pll->reference_div = RADEON_BIOS16 (pll_info_block + 0x10); - pll->pll_out_min = RADEON_BIOS32 (pll_info_block + 0x12); - pll->pll_out_max = RADEON_BIOS32 (pll_info_block + 0x16); - - if (rev > 9) { - pll->pll_in_min = RADEON_BIOS32(pll_info_block + 0x36); - pll->pll_in_max = RADEON_BIOS32(pll_info_block + 0x3a); - } else { - pll->pll_in_min = 40; - pll->pll_in_max = 500; - } - - pll->xclk = RADEON_BIOS16(pll_info_block + 0x08); - - info->sclk = RADEON_BIOS16(pll_info_block + 10) / 100.0; - info->mclk = RADEON_BIOS16(pll_info_block + 8) / 100.0; - } - - if (info->sclk == 0) info->sclk = 200; - if (info->mclk == 0) info->mclk = 200; - } - - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "ref_freq: %d, min_out_pll: %u, " - "max_out_pll: %u, min_in_pll: %u, max_in_pll: %u, xclk: %d, " - "sclk: %f, mclk: %f\n", - pll->reference_freq, (unsigned)pll->pll_out_min, - (unsigned)pll->pll_out_max, (unsigned)pll->pll_in_min, - (unsigned)pll->pll_in_max, pll->xclk, info->sclk, info->mclk); - - return TRUE; -} - -Bool RADEONGetDAC2InfoFromBIOS (ScrnInfoPtr pScrn, radeon_tvdac_ptr tvdac) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - int offset, rev, bg, dac; - - if (!info->VBIOS) return FALSE; - - if (xf86ReturnOptValBool(info->Options, OPTION_DEFAULT_TVDAC_ADJ, FALSE)) - return FALSE; - - if (info->IsAtomBios) { - /* not implemented yet */ - return FALSE; - } else { - /* first check TV table */ - offset = RADEON_BIOS16(info->ROMHeaderStart + 0x32); - if (offset) { - rev = RADEON_BIOS8(offset + 0x3); - if (rev > 4) { - bg = RADEON_BIOS8(offset + 0xc) & 0xf; - dac = RADEON_BIOS8(offset + 0xd) & 0xf; - tvdac->ps2_tvdac_adj = (bg << 16) | (dac << 20); - - bg = RADEON_BIOS8(offset + 0xe) & 0xf; - dac = RADEON_BIOS8(offset + 0xf) & 0xf; - tvdac->pal_tvdac_adj = (bg << 16) | (dac << 20); - - bg = RADEON_BIOS8(offset + 0x10) & 0xf; - dac = RADEON_BIOS8(offset + 0x11) & 0xf; - tvdac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); - - return TRUE; - } else if (rev > 1) { - bg = RADEON_BIOS8(offset + 0xc) & 0xf; - dac = (RADEON_BIOS8(offset + 0xc) >> 4) & 0xf; - tvdac->ps2_tvdac_adj = (bg << 16) | (dac << 20); - - bg = RADEON_BIOS8(offset + 0xd) & 0xf; - dac = (RADEON_BIOS8(offset + 0xd) >> 4) & 0xf; - tvdac->pal_tvdac_adj = (bg << 16) | (dac << 20); - - bg = RADEON_BIOS8(offset + 0xe) & 0xf; - dac = (RADEON_BIOS8(offset + 0xe) >> 4) & 0xf; - tvdac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); - - return TRUE; - } - } - /* then check CRT table */ - offset = RADEON_BIOS16(info->ROMHeaderStart + 0x60); - if (offset) { - rev = RADEON_BIOS8(offset) & 0x3; - if (rev < 2) { - bg = RADEON_BIOS8(offset + 0x3) & 0xf; - dac = (RADEON_BIOS8(offset + 0x3) >> 4) & 0xf; - tvdac->ps2_tvdac_adj = (bg << 16) | (dac << 20); - tvdac->pal_tvdac_adj = tvdac->ps2_tvdac_adj; - tvdac->ntsc_tvdac_adj = tvdac->ps2_tvdac_adj; - - return TRUE; - } else { - bg = RADEON_BIOS8(offset + 0x4) & 0xf; - dac = RADEON_BIOS8(offset + 0x5) & 0xf; - tvdac->ps2_tvdac_adj = (bg << 16) | (dac << 20); - tvdac->pal_tvdac_adj = tvdac->ps2_tvdac_adj; - tvdac->ntsc_tvdac_adj = tvdac->ps2_tvdac_adj; - - return TRUE; - } - } - } - - return FALSE; -} - -Bool -RADEONGetLVDSInfoFromBIOS(ScrnInfoPtr pScrn, radeon_lvds_ptr lvds) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - radeon_native_mode_ptr native_mode = &lvds->native_mode; - unsigned long tmp, i; - - if (!info->VBIOS) - return FALSE; - - if (!info->IsAtomBios) { - tmp = RADEON_BIOS16(info->ROMHeaderStart + 0x40); - - if (!tmp) { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "No Panel Info Table found in BIOS!\n"); - return FALSE; - } else { - char stmp[30]; - int tmp0; - - for (i = 0; i < 24; i++) - stmp[i] = RADEON_BIOS8(tmp+i+1); - stmp[24] = 0; - - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Panel ID string: %s\n", stmp); - - native_mode->PanelXRes = RADEON_BIOS16(tmp+25); - native_mode->PanelYRes = RADEON_BIOS16(tmp+27); - xf86DrvMsg(0, X_INFO, "Panel Size from BIOS: %dx%d\n", - native_mode->PanelXRes, native_mode->PanelYRes); - - lvds->PanelPwrDly = RADEON_BIOS16(tmp+44); - if (lvds->PanelPwrDly > 2000 || lvds->PanelPwrDly < 0) - lvds->PanelPwrDly = 2000; - - /* some panels only work well with certain divider combinations. - */ - info->RefDivider = RADEON_BIOS16(tmp+46); - info->PostDivider = RADEON_BIOS8(tmp+48); - info->FeedbackDivider = RADEON_BIOS16(tmp+49); - if ((info->RefDivider != 0) && - (info->FeedbackDivider > 3)) { - info->UseBiosDividers = TRUE; - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "BIOS provided dividers will be used.\n"); - } - - /* We don't use a while loop here just in case we have a corrupted BIOS image. - The max number of table entries is 23 at present, but may grow in future. - To ensure it works with future revisions we loop it to 32. - */ - for (i = 0; i < 32; i++) { - tmp0 = RADEON_BIOS16(tmp+64+i*2); - if (tmp0 == 0) break; - if ((RADEON_BIOS16(tmp0) == native_mode->PanelXRes) && - (RADEON_BIOS16(tmp0+2) == native_mode->PanelYRes)) { - native_mode->HBlank = (RADEON_BIOS16(tmp0+17) - - RADEON_BIOS16(tmp0+19)) * 8; - native_mode->HOverPlus = (RADEON_BIOS16(tmp0+21) - - RADEON_BIOS16(tmp0+19) - 1) * 8; - native_mode->HSyncWidth = RADEON_BIOS8(tmp0+23) * 8; - native_mode->VBlank = (RADEON_BIOS16(tmp0+24) - - RADEON_BIOS16(tmp0+26)); - native_mode->VOverPlus = ((RADEON_BIOS16(tmp0+28) & 0x7ff) - - RADEON_BIOS16(tmp0+26)); - native_mode->VSyncWidth = ((RADEON_BIOS16(tmp0+28) & 0xf800) >> 11); - native_mode->DotClock = RADEON_BIOS16(tmp0+9) * 10; - native_mode->Flags = 0; - } - } - } - - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "LVDS Info:\n" - "XRes: %d, YRes: %d, DotClock: %d\n" - "HBlank: %d, HOverPlus: %d, HSyncWidth: %d\n" - "VBlank: %d, VOverPlus: %d, VSyncWidth: %d\n", - native_mode->PanelXRes, native_mode->PanelYRes, native_mode->DotClock, - native_mode->HBlank, native_mode->HOverPlus, native_mode->HSyncWidth, - native_mode->VBlank, native_mode->VOverPlus, native_mode->VSyncWidth); - - return TRUE; - } - return FALSE; -} - -xf86MonPtr RADEONGetHardCodedEDIDFromBIOS (xf86OutputPtr output) -{ - ScrnInfoPtr pScrn = output->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned long tmp; - unsigned char edid[256]; - xf86MonPtr mon = NULL; - - if (!info->VBIOS) - return mon; - - if (!info->IsAtomBios) { - tmp = RADEON_BIOS16(info->ROMHeaderStart + 0x4c); - if (tmp) { - memcpy(edid, (unsigned char*)(info->VBIOS + tmp), 256); - if (edid[1] == 0xff) - mon = xf86InterpretEDID(output->scrn->scrnIndex, edid); - } - } - - return mon; -} - -Bool RADEONGetTMDSInfoFromBIOS (ScrnInfoPtr pScrn, radeon_tmds_ptr tmds) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - uint32_t tmp, maxfreq; - int i, n; - - if (!info->VBIOS) return FALSE; - - if (info->IsAtomBios) { - if((tmp = RADEON_BIOS16 (info->MasterDataStart + 18))) { - - maxfreq = RADEON_BIOS16(tmp+4); - - for (i=0; i<4; i++) { - tmds->tmds_pll[i].freq = RADEON_BIOS16(tmp+i*6+6); - /* This assumes each field in TMDS_PLL has 6 bit as in R300/R420 */ - tmds->tmds_pll[i].value = ((RADEON_BIOS8(tmp+i*6+8) & 0x3f) | - ((RADEON_BIOS8(tmp+i*6+10) & 0x3f)<<6) | - ((RADEON_BIOS8(tmp+i*6+9) & 0xf)<<12) | - ((RADEON_BIOS8(tmp+i*6+11) & 0xf)<<16)); - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "TMDS PLL from BIOS: %u %x\n", - (unsigned)tmds->tmds_pll[i].freq, - (unsigned)tmds->tmds_pll[i].value); - - if (maxfreq == tmds->tmds_pll[i].freq) { - tmds->tmds_pll[i].freq = 0xffffffff; - break; - } - } - return TRUE; - } - } else { - - tmp = RADEON_BIOS16(info->ROMHeaderStart + 0x34); - if (tmp) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "DFP table revision: %d\n", RADEON_BIOS8(tmp)); - if (RADEON_BIOS8(tmp) == 3) { - n = RADEON_BIOS8(tmp + 5) + 1; - if (n > 4) n = 4; - for (i=0; i<n; i++) { - tmds->tmds_pll[i].value = RADEON_BIOS32(tmp+i*10+0x08); - tmds->tmds_pll[i].freq = RADEON_BIOS16(tmp+i*10+0x10); - } - return TRUE; - } else if (RADEON_BIOS8(tmp) == 4) { - int stride = 0; - n = RADEON_BIOS8(tmp + 5) + 1; - if (n > 4) n = 4; - for (i=0; i<n; i++) { - tmds->tmds_pll[i].value = RADEON_BIOS32(tmp+stride+0x08); - tmds->tmds_pll[i].freq = RADEON_BIOS16(tmp+stride+0x10); - if (i == 0) stride += 10; - else stride += 6; - } - return TRUE; - } - } - } - return FALSE; -} - -static RADEONI2CBusRec -RADEONLookupI2CBlock(ScrnInfoPtr pScrn, int id) -{ - RADEONInfoPtr info = RADEONPTR (pScrn); - int offset, blocks, i; - RADEONI2CBusRec i2c; - - memset(&i2c, 0, sizeof(RADEONI2CBusRec)); - i2c.valid = FALSE; - - offset = RADEON_BIOS16(info->ROMHeaderStart + 0x70); - if (offset) { - blocks = RADEON_BIOS8(offset + 2); - for (i = 0; i < blocks; i++) { - int i2c_id = RADEON_BIOS8(offset + 3 + (i * 5) + 0); - if (id == i2c_id) { - int clock_shift = RADEON_BIOS8(offset + 3 + (i * 5) + 3); - int data_shift = RADEON_BIOS8(offset + 3 + (i * 5) + 4); - - i2c.mask_clk_mask = (1 << clock_shift); - i2c.mask_data_mask = (1 << data_shift); - i2c.a_clk_mask = (1 << clock_shift); - i2c.a_data_mask = (1 << data_shift); - i2c.put_clk_mask = (1 << clock_shift); - i2c.put_data_mask = (1 << data_shift); - i2c.get_clk_mask = (1 << clock_shift); - i2c.get_data_mask = (1 << data_shift); - i2c.mask_clk_reg = RADEON_GPIOPAD_MASK; - i2c.mask_data_reg = RADEON_GPIOPAD_MASK; - i2c.a_clk_reg = RADEON_GPIOPAD_A; - i2c.a_data_reg = RADEON_GPIOPAD_A; - i2c.put_clk_reg = RADEON_GPIOPAD_EN; - i2c.put_data_reg = RADEON_GPIOPAD_EN; - i2c.get_clk_reg = RADEON_LCD_GPIO_Y_REG; - i2c.get_data_reg = RADEON_LCD_GPIO_Y_REG; - i2c.valid = TRUE; - break; - } - } - } - return i2c; -} - -Bool RADEONGetExtTMDSInfoFromBIOS (ScrnInfoPtr pScrn, radeon_dvo_ptr dvo) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - int offset, table_start, max_freq, gpio_reg, flags; - - if (!info->VBIOS) - return FALSE; - - if (info->IsAtomBios) - return FALSE; - else if (info->IsIGP) { - /* RS4xx TMDS stuff is in the mobile table */ - offset = RADEON_BIOS16(info->ROMHeaderStart + 0x42); - if (offset) { - int rev = RADEON_BIOS8(offset); - if (rev >= 6) { - offset = RADEON_BIOS16(offset + 0x17); - if (offset) { - offset = RADEON_BIOS16(offset + 2); - rev = RADEON_BIOS8(offset); - if (offset && (rev > 1)) { - int blocks = RADEON_BIOS8(offset + 3); - int index = offset + 4; - dvo->dvo_i2c.valid = FALSE; - while (blocks > 0) { - int id = RADEON_BIOS16(index); - index += 2; - switch (id >> 13) { - case 0: - index += 6; - break; - case 2: - index += 10; - break; - case 3: - index += 2; - break; - case 4: - index += 2; - break; - case 6: - dvo->dvo_i2c_slave_addr = - RADEON_BIOS16(index) & 0xff; - index += 2; - dvo->dvo_i2c = - RADEONLookupI2CBlock(pScrn, RADEON_BIOS8(index)); - return TRUE; - default: - break; - } - blocks--; - } - } - } - } - } else { - dvo->dvo_i2c_slave_addr = 0x70; - dvo->dvo_i2c = RADEONLookupI2CBlock(pScrn, 136); - info->ext_tmds_chip = RADEON_SIL_164; - } - } else { - offset = RADEON_BIOS16(info->ROMHeaderStart + 0x58); - if (offset) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "External TMDS Table revision: %d\n", - RADEON_BIOS8(offset)); - table_start = offset+4; - max_freq = RADEON_BIOS16(table_start); - dvo->dvo_i2c_slave_addr = RADEON_BIOS8(table_start+2); - dvo->dvo_i2c.valid = FALSE; - gpio_reg = RADEON_BIOS8(table_start+3); - if (gpio_reg == 1) - dvo->dvo_i2c = legacy_setup_i2c_bus(RADEON_GPIO_MONID); - else if (gpio_reg == 2) - dvo->dvo_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC); - else if (gpio_reg == 3) - dvo->dvo_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC); - else if (gpio_reg == 4) { - if (IS_R300_VARIANT) - dvo->dvo_i2c = legacy_setup_i2c_bus(RADEON_GPIO_MONID); - else - dvo->dvo_i2c = legacy_setup_i2c_bus(RADEON_GPIO_CRT2_DDC); - } else if (gpio_reg == 5) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "unsupported MM gpio_reg\n"); - return FALSE; - } else { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Unknown gpio reg: %d\n", gpio_reg); - return FALSE; - } - flags = RADEON_BIOS8(table_start+5); - dvo->dvo_duallink = flags & 0x01; - if (dvo->dvo_duallink) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Duallink TMDS detected\n"); - } - return TRUE; - } - } - - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "No External TMDS Table found\n"); - - return FALSE; -} - -Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output) -{ - ScrnInfoPtr pScrn = output->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - radeon_encoder_ptr radeon_encoder = radeon_get_encoder(output); - radeon_dvo_ptr dvo = NULL; - int offset, index, id; - uint32_t val, reg, and_mask, or_mask; - - if (radeon_encoder == NULL) - return FALSE; - - dvo = (radeon_dvo_ptr)radeon_encoder->dev_priv; - - if (dvo == NULL) - return FALSE; - - if (!info->VBIOS) - return FALSE; - - if (info->IsAtomBios) - return FALSE; - else if (info->IsIGP) { - /* RS4xx TMDS stuff is in the mobile table */ - offset = RADEON_BIOS16(info->ROMHeaderStart + 0x42); - if (offset) { - int rev = RADEON_BIOS8(offset); - if (rev >= 6) { - offset = RADEON_BIOS16(offset + 0x17); - if (offset) { - offset = RADEON_BIOS16(offset + 2); - rev = RADEON_BIOS8(offset); - if (offset && (rev > 1)) { - int blocks = RADEON_BIOS8(offset + 3); - index = offset + 4; - while (blocks > 0) { - id = RADEON_BIOS16(index); - index += 2; - switch (id >> 13) { - case 0: - reg = (id & 0x1fff) * 4; - val = RADEON_BIOS32(index); - index += 4; - ErrorF("MMIO: 0x%x 0x%x\n", - (unsigned)reg, (unsigned)val); - OUTREG(reg, val); - break; - case 2: - reg = (id & 0x1fff) * 4; - and_mask = RADEON_BIOS32(index); - index += 4; - or_mask = RADEON_BIOS32(index); - index += 4; - ErrorF("MMIO mask: 0x%x 0x%x 0x%x\n", - (unsigned)reg, (unsigned)and_mask, (unsigned)or_mask); - val = INREG(reg); - val = (val & and_mask) | or_mask; - OUTREG(reg, val); - break; - case 3: - val = RADEON_BIOS16(index); - index += 2; - ErrorF("delay: %u\n", (unsigned)val); - usleep(val); - break; - case 4: - val = RADEON_BIOS16(index); - index += 2; - ErrorF("delay: %u\n", (unsigned)val * 1000); - usleep(val * 1000); - break; - case 6: - index++; - reg = RADEON_BIOS8(index); - index++; - val = RADEON_BIOS8(index); - index++; - ErrorF("i2c write: 0x%x, 0x%x\n", (unsigned)reg, - (unsigned)val); - RADEONDVOWriteByte(dvo->DVOChip, reg, val); - break; - default: - ErrorF("unknown id %d\n", id>>13); - return FALSE; - } - blocks--; - } - return TRUE; - } - } - } - } - } else { - offset = RADEON_BIOS16(info->ROMHeaderStart + 0x58); - if (offset) { - index = offset+10; - id = RADEON_BIOS16(index); - while (id != 0xffff) { - index += 2; - switch(id >> 13) { - case 0: - reg = (id & 0x1fff) * 4; - val = RADEON_BIOS32(index); - index += 4; - ErrorF("MMIO: 0x%x 0x%x\n", - (unsigned)reg, (unsigned)val); - OUTREG(reg, val); - break; - case 2: - reg = (id & 0x1fff) * 4; - and_mask = RADEON_BIOS32(index); - index += 4; - or_mask = RADEON_BIOS32(index); - index += 4; - val = INREG(reg); - val = (val & and_mask) | or_mask; - ErrorF("MMIO mask: 0x%x 0x%x 0x%x\n", - (unsigned)reg, (unsigned)and_mask, (unsigned)or_mask); - OUTREG(reg, val); - break; - case 4: - val = RADEON_BIOS16(index); - index += 2; - ErrorF("delay: %u\n", (unsigned)val); - usleep(val); - break; - case 5: - reg = id & 0x1fff; - and_mask = RADEON_BIOS32(index); - index += 4; - or_mask = RADEON_BIOS32(index); - index += 4; - ErrorF("PLL mask: 0x%x 0x%x 0x%x\n", - (unsigned)reg, (unsigned)and_mask, (unsigned)or_mask); - val = INPLL(pScrn, reg); - val = (val & and_mask) | or_mask; - OUTPLL(pScrn, reg, val); - break; - case 6: - reg = id & 0x1fff; - val = RADEON_BIOS8(index); - index += 1; - ErrorF("i2c write: 0x%x, 0x%x\n", (unsigned)reg, - (unsigned)val); - RADEONDVOWriteByte(dvo->DVOChip, reg, val); - break; - default: - ErrorF("unknown id %d\n", id>>13); - return FALSE; - }; - id = RADEON_BIOS16(index); - } - return TRUE; - } - } - - return FALSE; -} - -/* support for init from bios tables - * - * Based heavily on the netbsd radeonfb driver - * Written by Garrett D'Amore - * Copyright (c) 2006 Itronix Inc. - * - */ - -/* bios table defines */ - -#define RADEON_TABLE_ENTRY_FLAG_MASK 0xe000 -#define RADEON_TABLE_ENTRY_INDEX_MASK 0x1fff -#define RADEON_TABLE_ENTRY_COMMAND_MASK 0x00ff - -#define RADEON_TABLE_FLAG_WRITE_INDEXED 0x0000 -#define RADEON_TABLE_FLAG_WRITE_DIRECT 0x2000 -#define RADEON_TABLE_FLAG_MASK_INDEXED 0x4000 -#define RADEON_TABLE_FLAG_MASK_DIRECT 0x6000 -#define RADEON_TABLE_FLAG_DELAY 0x8000 -#define RADEON_TABLE_FLAG_SCOMMAND 0xa000 - -#define RADEON_TABLE_SCOMMAND_WAIT_MC_BUSY_MASK 0x03 -#define RADEON_TABLE_SCOMMAND_WAIT_MEM_PWRUP_COMPLETE 0x08 - -#define RADEON_PLL_FLAG_MASK 0xc0 -#define RADEON_PLL_INDEX_MASK 0x3f - -#define RADEON_PLL_FLAG_WRITE 0x00 -#define RADEON_PLL_FLAG_MASK_BYTE 0x40 -#define RADEON_PLL_FLAG_WAIT 0x80 - -#define RADEON_PLL_WAIT_150MKS 1 -#define RADEON_PLL_WAIT_5MS 2 -#define RADEON_PLL_WAIT_MC_BUSY_MASK 3 -#define RADEON_PLL_WAIT_DLL_READY_MASK 4 -#define RADEON_PLL_WAIT_CHK_SET_CLK_PWRMGT_CNTL24 5 - -static uint16_t -RADEONValidateBIOSOffset(ScrnInfoPtr pScrn, uint16_t offset) -{ - RADEONInfoPtr info = RADEONPTR (pScrn); - uint8_t revision = RADEON_BIOS8(offset - 1); - - if (revision > 0x10) { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "Bad revision %d for BIOS table\n", revision); - return 0; - } - - if (offset < 0x60) { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "Bad offset 0x%x for BIOS Table\n", offset); - return 0; - } - - return offset; -} - -Bool -RADEONGetBIOSInitTableOffsets(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR (pScrn); - uint8_t val; - - if (!info->VBIOS) { - return FALSE; - } else { - if (info->IsAtomBios) { - return FALSE; - } else { - info->BiosTable.revision = RADEON_BIOS8(info->ROMHeaderStart + 4); - info->BiosTable.rr1_offset = RADEON_BIOS16(info->ROMHeaderStart + 0x0c); - if (info->BiosTable.rr1_offset) { - info->BiosTable.rr1_offset = - RADEONValidateBIOSOffset(pScrn, info->BiosTable.rr1_offset); - } - if (info->BiosTable.revision > 0x09) - return TRUE; - info->BiosTable.rr2_offset = RADEON_BIOS16(info->ROMHeaderStart + 0x4e); - if (info->BiosTable.rr2_offset) { - info->BiosTable.rr2_offset = - RADEONValidateBIOSOffset(pScrn, info->BiosTable.rr2_offset); - } - info->BiosTable.dyn_clk_offset = RADEON_BIOS16(info->ROMHeaderStart + 0x52); - if (info->BiosTable.dyn_clk_offset) { - info->BiosTable.dyn_clk_offset = - RADEONValidateBIOSOffset(pScrn, info->BiosTable.dyn_clk_offset); - } - info->BiosTable.pll_offset = RADEON_BIOS16(info->ROMHeaderStart + 0x46); - if (info->BiosTable.pll_offset) { - info->BiosTable.pll_offset = - RADEONValidateBIOSOffset(pScrn, info->BiosTable.pll_offset); - } - info->BiosTable.mem_config_offset = RADEON_BIOS16(info->ROMHeaderStart + 0x48); - if (info->BiosTable.mem_config_offset) { - info->BiosTable.mem_config_offset = - RADEONValidateBIOSOffset(pScrn, info->BiosTable.mem_config_offset); - } - if (info->BiosTable.mem_config_offset) { - info->BiosTable.mem_reset_offset = info->BiosTable.mem_config_offset; - if (info->BiosTable.mem_reset_offset) { - while (RADEON_BIOS8(info->BiosTable.mem_reset_offset)) - info->BiosTable.mem_reset_offset++; - info->BiosTable.mem_reset_offset++; - info->BiosTable.mem_reset_offset += 2; - } - } - if (info->BiosTable.mem_config_offset) { - info->BiosTable.short_mem_offset = info->BiosTable.mem_config_offset; - if ((info->BiosTable.short_mem_offset != 0) && - (RADEON_BIOS8(info->BiosTable.short_mem_offset - 2) <= 64)) - info->BiosTable.short_mem_offset += - RADEON_BIOS8(info->BiosTable.short_mem_offset - 3); - } - if (info->BiosTable.rr2_offset) { - info->BiosTable.rr3_offset = info->BiosTable.rr2_offset; - if (info->BiosTable.rr3_offset) { - while ((val = RADEON_BIOS8(info->BiosTable.rr3_offset + 1)) != 0) { - if (val & 0x40) - info->BiosTable.rr3_offset += 10; - else if (val & 0x80) - info->BiosTable.rr3_offset += 4; - else - info->BiosTable.rr3_offset += 6; - } - info->BiosTable.rr3_offset += 2; - } - } - - if (info->BiosTable.rr3_offset) { - info->BiosTable.rr4_offset = info->BiosTable.rr3_offset; - if (info->BiosTable.rr4_offset) { - while ((val = RADEON_BIOS8(info->BiosTable.rr4_offset + 1)) != 0) { - if (val & 0x40) - info->BiosTable.rr4_offset += 10; - else if (val & 0x80) - info->BiosTable.rr4_offset += 4; - else - info->BiosTable.rr4_offset += 6; - } - info->BiosTable.rr4_offset += 2; - } - } - - if (info->BiosTable.rr3_offset + 1 == info->BiosTable.pll_offset) { - info->BiosTable.rr3_offset = 0; - info->BiosTable.rr4_offset = 0; - } - - return TRUE; - - } - } -} - -static void -RADEONRestoreBIOSRegBlock(ScrnInfoPtr pScrn, uint16_t table_offset) -{ - RADEONInfoPtr info = RADEONPTR (pScrn); - unsigned char *RADEONMMIO = info->MMIO; - uint16_t offset = table_offset; - uint16_t value, flag, index, count; - uint32_t andmask, ormask, val, channel_complete_mask; - uint8_t command; - - if (offset == 0) - return; - - while ((value = RADEON_BIOS16(offset)) != 0) { - flag = value & RADEON_TABLE_ENTRY_FLAG_MASK; - index = value & RADEON_TABLE_ENTRY_INDEX_MASK; - command = value & RADEON_TABLE_ENTRY_COMMAND_MASK; - - offset += 2; - - switch (flag) { - case RADEON_TABLE_FLAG_WRITE_INDEXED: - val = RADEON_BIOS32(offset); - ErrorF("WRITE INDEXED: 0x%x 0x%x\n", - index, (unsigned)val); - OUTREG(RADEON_MM_INDEX, index); - OUTREG(RADEON_MM_DATA, val); - offset += 4; - break; - - case RADEON_TABLE_FLAG_WRITE_DIRECT: - val = RADEON_BIOS32(offset); - ErrorF("WRITE DIRECT: 0x%x 0x%x\n", index, (unsigned)val); - OUTREG(index, val); - offset += 4; - break; - - case RADEON_TABLE_FLAG_MASK_INDEXED: - andmask = RADEON_BIOS32(offset); - offset += 4; - ormask = RADEON_BIOS32(offset); - offset += 4; - ErrorF("MASK INDEXED: 0x%x 0x%x 0x%x\n", - index, (unsigned)andmask, (unsigned)ormask); - OUTREG(RADEON_MM_INDEX, index); - val = INREG(RADEON_MM_DATA); - val = (val & andmask) | ormask; - OUTREG(RADEON_MM_DATA, val); - break; - - case RADEON_TABLE_FLAG_MASK_DIRECT: - andmask = RADEON_BIOS32(offset); - offset += 4; - ormask = RADEON_BIOS32(offset); - offset += 4; - ErrorF("MASK DIRECT: 0x%x 0x%x 0x%x\n", - index, (unsigned)andmask, (unsigned)ormask); - val = INREG(index); - val = (val & andmask) | ormask; - OUTREG(index, val); - break; - - case RADEON_TABLE_FLAG_DELAY: - count = RADEON_BIOS16(offset); - ErrorF("delay: %d\n", count); - usleep(count); - offset += 2; - break; - - case RADEON_TABLE_FLAG_SCOMMAND: - ErrorF("SCOMMAND 0x%x\n", command); - switch (command) { - case RADEON_TABLE_SCOMMAND_WAIT_MC_BUSY_MASK: - count = RADEON_BIOS16(offset); - ErrorF("SCOMMAND_WAIT_MC_BUSY_MASK %d\n", count); - while (count--) { - if (!(INPLL(pScrn, RADEON_CLK_PWRMGT_CNTL) & - RADEON_MC_BUSY)) - break; - } - break; - - case RADEON_TABLE_SCOMMAND_WAIT_MEM_PWRUP_COMPLETE: - count = RADEON_BIOS16(offset); - ErrorF("SCOMMAND_WAIT_MEM_PWRUP_COMPLETE %d\n", count); - /* may need to take into account how many memory channels - * each card has - */ - if (IS_R300_VARIANT) - channel_complete_mask = R300_MEM_PWRUP_COMPLETE; - else - channel_complete_mask = RADEON_MEM_PWRUP_COMPLETE; - while (count--) { - /* XXX: may need indexed access */ - if ((INREG(RADEON_MEM_STR_CNTL) & - channel_complete_mask) == - channel_complete_mask) - break; - } - break; - - } - offset += 2; - break; - } - } -} - -static void -RADEONRestoreBIOSMemBlock(ScrnInfoPtr pScrn, uint16_t table_offset) -{ - RADEONInfoPtr info = RADEONPTR (pScrn); - unsigned char *RADEONMMIO = info->MMIO; - uint16_t offset = table_offset; - uint16_t count; - uint32_t ormask, val, channel_complete_mask; - uint8_t index; - - if (offset == 0) - return; - - while ((index = RADEON_BIOS8(offset)) != 0xff) { - offset++; - if (index == 0x0f) { - count = 20000; - ErrorF("MEM_WAIT_MEM_PWRUP_COMPLETE %d\n", count); - /* may need to take into account how many memory channels - * each card has - */ - if (IS_R300_VARIANT) - channel_complete_mask = R300_MEM_PWRUP_COMPLETE; - else - channel_complete_mask = RADEON_MEM_PWRUP_COMPLETE; - while (count--) { - /* XXX: may need indexed access */ - if ((INREG(RADEON_MEM_STR_CNTL) & - channel_complete_mask) == - channel_complete_mask) - break; - } - } else { - ormask = RADEON_BIOS16(offset); - offset += 2; - - ErrorF("INDEX RADEON_MEM_SDRAM_MODE_REG %x %x\n", - RADEON_SDRAM_MODE_MASK, (unsigned)ormask); - - /* can this use direct access? */ - OUTREG(RADEON_MM_INDEX, RADEON_MEM_SDRAM_MODE_REG); - val = INREG(RADEON_MM_DATA); - val = (val & RADEON_SDRAM_MODE_MASK) | ormask; - OUTREG(RADEON_MM_DATA, val); - - ormask = (uint32_t)index << 24; - - ErrorF("INDEX RADEON_MEM_SDRAM_MODE_REG %x %x\n", - RADEON_B3MEM_RESET_MASK, (unsigned)ormask); - - /* can this use direct access? */ - OUTREG(RADEON_MM_INDEX, RADEON_MEM_SDRAM_MODE_REG); - val = INREG(RADEON_MM_DATA); - val = (val & RADEON_B3MEM_RESET_MASK) | ormask; - OUTREG(RADEON_MM_DATA, val); - } - } -} - -static void -RADEONRestoreBIOSPllBlock(ScrnInfoPtr pScrn, uint16_t table_offset) -{ - RADEONInfoPtr info = RADEONPTR (pScrn); - uint16_t offset = table_offset; - uint8_t index, shift; - uint32_t andmask, ormask, val, clk_pwrmgt_cntl; - uint16_t count; - - if (offset == 0) - return; - - while ((index = RADEON_BIOS8(offset)) != 0) { - offset++; - - switch (index & RADEON_PLL_FLAG_MASK) { - case RADEON_PLL_FLAG_WAIT: - switch (index & RADEON_PLL_INDEX_MASK) { - case RADEON_PLL_WAIT_150MKS: - ErrorF("delay: 150 us\n"); - usleep(150); - break; - case RADEON_PLL_WAIT_5MS: - ErrorF("delay: 5 ms\n"); - usleep(5000); - break; - - case RADEON_PLL_WAIT_MC_BUSY_MASK: - count = 1000; - ErrorF("PLL_WAIT_MC_BUSY_MASK %d\n", count); - while (count--) { - if (!(INPLL(pScrn, RADEON_CLK_PWRMGT_CNTL) & - RADEON_MC_BUSY)) - break; - } - break; - - case RADEON_PLL_WAIT_DLL_READY_MASK: - count = 1000; - ErrorF("PLL_WAIT_DLL_READY_MASK %d\n", count); - while (count--) { - if (INPLL(pScrn, RADEON_CLK_PWRMGT_CNTL) & - RADEON_DLL_READY) - break; - } - break; - - case RADEON_PLL_WAIT_CHK_SET_CLK_PWRMGT_CNTL24: - ErrorF("PLL_WAIT_CHK_SET_CLK_PWRMGT_CNTL24\n"); - clk_pwrmgt_cntl = INPLL(pScrn, RADEON_CLK_PWRMGT_CNTL); - if (clk_pwrmgt_cntl & RADEON_CG_NO1_DEBUG_0) { - val = INPLL(pScrn, RADEON_MCLK_CNTL); - /* is this right? */ - val = (val & 0xFFFF0000) | 0x1111; /* seems like we should clear these... */ - OUTPLL(pScrn, RADEON_MCLK_CNTL, val); - usleep(10000); - OUTPLL(pScrn, RADEON_CLK_PWRMGT_CNTL, - clk_pwrmgt_cntl & ~RADEON_CG_NO1_DEBUG_0); - usleep(10000); - } - break; - } - break; - - case RADEON_PLL_FLAG_MASK_BYTE: - shift = RADEON_BIOS8(offset) * 8; - offset++; - - andmask = - (((uint32_t)RADEON_BIOS8(offset)) << shift) | - ~((uint32_t)0xff << shift); - offset++; - - ormask = ((uint32_t)RADEON_BIOS8(offset)) << shift; - offset++; - - ErrorF("PLL_MASK_BYTE 0x%x 0x%x 0x%x 0x%x\n", - index, shift, (unsigned)andmask, (unsigned)ormask); - val = INPLL(pScrn, index); - val = (val & andmask) | ormask; - OUTPLL(pScrn, index, val); - break; - - case RADEON_PLL_FLAG_WRITE: - val = RADEON_BIOS32(offset); - ErrorF("PLL_WRITE 0x%x 0x%x\n", index, (unsigned)val); - OUTPLL(pScrn, index, val); - offset += 4; - break; - } - } -} - -Bool -RADEONPostCardFromBIOSTables(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR (pScrn); - - if (!info->VBIOS) { - return FALSE; - } else { - if (info->IsAtomBios) { - return FALSE; - } else { - if (info->BiosTable.rr1_offset) { - ErrorF("rr1 restore, 0x%x\n", info->BiosTable.rr1_offset); - RADEONRestoreBIOSRegBlock(pScrn, info->BiosTable.rr1_offset); - } - if (info->BiosTable.revision < 0x09) { - if (info->BiosTable.pll_offset) { - ErrorF("pll restore, 0x%x\n", info->BiosTable.pll_offset); - RADEONRestoreBIOSPllBlock(pScrn, info->BiosTable.pll_offset); - } - if (info->BiosTable.rr2_offset) { - ErrorF("rr2 restore, 0x%x\n", info->BiosTable.rr2_offset); - RADEONRestoreBIOSRegBlock(pScrn, info->BiosTable.rr2_offset); - } - if (info->BiosTable.rr4_offset) { - ErrorF("rr4 restore, 0x%x\n", info->BiosTable.rr4_offset); - RADEONRestoreBIOSRegBlock(pScrn, info->BiosTable.rr4_offset); - } - if (info->BiosTable.mem_reset_offset) { - ErrorF("mem reset restore, 0x%x\n", info->BiosTable.mem_reset_offset); - RADEONRestoreBIOSMemBlock(pScrn, info->BiosTable.mem_reset_offset); - } - if (info->BiosTable.rr3_offset) { - ErrorF("rr3 restore, 0x%x\n", info->BiosTable.rr3_offset); - RADEONRestoreBIOSRegBlock(pScrn, info->BiosTable.rr3_offset); - } - if (info->BiosTable.dyn_clk_offset) { - ErrorF("dyn_clk restore, 0x%x\n", info->BiosTable.dyn_clk_offset); - RADEONRestoreBIOSPllBlock(pScrn, info->BiosTable.dyn_clk_offset); - } - } - } - } - return TRUE; -} diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c index e0b026f1..6111af4b 100644 --- a/src/radeon_commonfuncs.c +++ b/src/radeon_commonfuncs.c @@ -32,31 +32,18 @@ #include "ati_pciids_gen.h" -#if defined(ACCEL_MMIO) && defined(ACCEL_CP) -#error Cannot define both MMIO and CP acceleration! -#endif - #if !defined(UNIXCPP) || defined(ANSICPP) #define FUNC_NAME_CAT(prefix,suffix) prefix##suffix #else #define FUNC_NAME_CAT(prefix,suffix) prefix/**/suffix #endif -#ifdef ACCEL_MMIO -#define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,MMIO) -#else -#ifdef ACCEL_CP #define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,CP) -#else -#error No accel type defined! -#endif -#endif static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); - uint32_t gb_tile_config, su_reg_dest, vap_cntl; - int size; + uint32_t gb_tile_config, vap_cntl; ACCEL_PREAMBLE(); info->accel_state->texW[0] = info->accel_state->texH[0] = @@ -64,14 +51,6 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) if (IS_R300_3D || IS_R500_3D) { - if (!info->cs) { - BEGIN_ACCEL(3); - OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); - OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); - OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); - FINISH_ACCEL(); - } - gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); switch(info->accel_state->num_gb_pipes) { @@ -82,28 +61,6 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break; } - if (!info->cs) { - size = (info->ChipFamily >= CHIP_FAMILY_R420) ? 5 : 4; - BEGIN_ACCEL(size); - OUT_ACCEL_REG(R300_GB_TILE_CONFIG, gb_tile_config); - OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); - if (info->ChipFamily >= CHIP_FAMILY_R420) - OUT_ACCEL_REG(R300_DST_PIPE_CONFIG, R300_PIPE_AUTO_CONFIG); - OUT_ACCEL_REG(R300_GB_SELECT, 0); - OUT_ACCEL_REG(R300_GB_ENABLE, 0); - FINISH_ACCEL(); - } - - if (IS_R500_3D) { - if (!info->cs) { - su_reg_dest = ((1 << info->accel_state->num_gb_pipes) - 1); - BEGIN_ACCEL(2); - OUT_ACCEL_REG(R500_SU_REG_DEST, su_reg_dest); - OUT_ACCEL_REG(R500_VAP_INDEX_OFFSET, 0); - FINISH_ACCEL(); - } - } - BEGIN_ACCEL(3); OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); @@ -116,27 +73,6 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); FINISH_ACCEL(); - if (!info->cs) { - BEGIN_ACCEL(3); - OUT_ACCEL_REG(R300_GB_MSPOS0, ((6 << R300_MS_X0_SHIFT) | - (6 << R300_MS_Y0_SHIFT) | - (6 << R300_MS_X1_SHIFT) | - (6 << R300_MS_Y1_SHIFT) | - (6 << R300_MS_X2_SHIFT) | - (6 << R300_MS_Y2_SHIFT) | - (6 << R300_MSBD0_Y_SHIFT) | - (6 << R300_MSBD0_X_SHIFT))); - OUT_ACCEL_REG(R300_GB_MSPOS1, ((6 << R300_MS_X3_SHIFT) | - (6 << R300_MS_Y3_SHIFT) | - (6 << R300_MS_X4_SHIFT) | - (6 << R300_MS_Y4_SHIFT) | - (6 << R300_MS_X5_SHIFT) | - (6 << R300_MS_Y5_SHIFT) | - (6 << R300_MSBD1_SHIFT))); - OUT_ACCEL_REG(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL); - FINISH_ACCEL(); - } - BEGIN_ACCEL(4); OUT_ACCEL_REG(R300_GA_POLY_MODE, R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE); OUT_ACCEL_REG(R300_GA_ROUND_MODE, (R300_GEOMETRY_ROUND_NEAREST | @@ -833,7 +769,7 @@ void FUNC_NAME(RADEONWaitForVLine)(ScrnInfoPtr pScrn, PixmapPtr pPix, xf86CrtcPtr crtc, int start, int stop) { RADEONInfoPtr info = RADEONPTR(pScrn); - uint32_t offset; + drmmode_crtc_private_ptr drmmode_crtc; ACCEL_PREAMBLE(); if (!crtc) @@ -842,21 +778,8 @@ void FUNC_NAME(RADEONWaitForVLine)(ScrnInfoPtr pScrn, PixmapPtr pPix, if (!crtc->enabled) return; - if (info->cs) { - if (pPix != pScrn->pScreen->GetScreenPixmap(pScrn->pScreen)) - return; - } else { -#ifdef USE_EXA - if (info->useEXA) - offset = exaGetPixmapOffset(pPix); - else -#endif - offset = pPix->devPrivate.ptr - info->FB; - - /* if drawing to front buffer */ - if (offset != 0) - return; - } + if (pPix != pScrn->pScreen->GetScreenPixmap(pScrn->pScreen)) + return; start = max(start, crtc->y); stop = min(stop, crtc->y + crtc->mode.VDisplay); @@ -870,168 +793,26 @@ void FUNC_NAME(RADEONWaitForVLine)(ScrnInfoPtr pScrn, PixmapPtr pPix, stop -= crtc->y; } -#if defined(ACCEL_CP) && defined(XF86DRM_MODE) - if (info->cs) { - drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; - - BEGIN_ACCEL(3); - if (IS_AVIVO_VARIANT) { - OUT_ACCEL_REG(AVIVO_D1MODE_VLINE_START_END, /* this is just a marker */ - ((start << AVIVO_D1MODE_VLINE_START_SHIFT) | - (stop << AVIVO_D1MODE_VLINE_END_SHIFT) | - AVIVO_D1MODE_VLINE_INV)); - } else { - OUT_ACCEL_REG(RADEON_CRTC_GUI_TRIG_VLINE, /* another placeholder */ - ((start << RADEON_CRTC_GUI_TRIG_VLINE_START_SHIFT) | - (stop << RADEON_CRTC_GUI_TRIG_VLINE_END_SHIFT) | - RADEON_CRTC_GUI_TRIG_VLINE_INV | - RADEON_CRTC_GUI_TRIG_VLINE_STALL)); - } - OUT_ACCEL_REG(RADEON_WAIT_UNTIL, (RADEON_WAIT_CRTC_VLINE | - RADEON_ENG_DISPLAY_SELECT_CRTC0)); - - OUT_RING(CP_PACKET3(RADEON_CP_PACKET3_NOP, 0)); - OUT_RING(drmmode_crtc->mode_crtc->crtc_id); - FINISH_ACCEL(); - } else -#endif - { - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; + drmmode_crtc = crtc->driver_private; - BEGIN_ACCEL(2); - if (IS_AVIVO_VARIANT) { - OUT_ACCEL_REG(AVIVO_D1MODE_VLINE_START_END + radeon_crtc->crtc_offset, - ((start << AVIVO_D1MODE_VLINE_START_SHIFT) | - (stop << AVIVO_D1MODE_VLINE_END_SHIFT) | - AVIVO_D1MODE_VLINE_INV)); - } else { - if (radeon_crtc->crtc_id == 0) - OUT_ACCEL_REG(RADEON_CRTC_GUI_TRIG_VLINE, - ((start << RADEON_CRTC_GUI_TRIG_VLINE_START_SHIFT) | - (stop << RADEON_CRTC_GUI_TRIG_VLINE_END_SHIFT) | - RADEON_CRTC_GUI_TRIG_VLINE_INV | - RADEON_CRTC_GUI_TRIG_VLINE_STALL)); - else - OUT_ACCEL_REG(RADEON_CRTC2_GUI_TRIG_VLINE, - ((start << RADEON_CRTC_GUI_TRIG_VLINE_START_SHIFT) | - (stop << RADEON_CRTC_GUI_TRIG_VLINE_END_SHIFT) | - RADEON_CRTC_GUI_TRIG_VLINE_INV | - RADEON_CRTC_GUI_TRIG_VLINE_STALL)); - } - - if (radeon_crtc->crtc_id == 0) - OUT_ACCEL_REG(RADEON_WAIT_UNTIL, (RADEON_WAIT_CRTC_VLINE | - RADEON_ENG_DISPLAY_SELECT_CRTC0)); - else - OUT_ACCEL_REG(RADEON_WAIT_UNTIL, (RADEON_WAIT_CRTC_VLINE | - RADEON_ENG_DISPLAY_SELECT_CRTC1)); - FINISH_ACCEL(); - } -} - -/* MMIO: - * - * Wait for the graphics engine to be completely idle: the FIFO has - * drained, the Pixel Cache is flushed, and the engine is idle. This is - * a standard "sync" function that will make the hardware "quiescent". - * - * CP: - * - * Wait until the CP is completely idle: the FIFO has drained and the CP - * is idle. - */ -void FUNC_NAME(RADEONWaitForIdle)(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - int i = 0; - -#ifdef ACCEL_CP - /* Make sure the CP is idle first */ - if (info->cp->CPStarted) { - int ret; - - FLUSH_RING(); - - for (;;) { - do { - ret = drmCommandNone(info->dri->drmFD, DRM_RADEON_CP_IDLE); - if (ret && ret != -EBUSY) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "%s: CP idle %d\n", __FUNCTION__, ret); - } - } while ((ret == -EBUSY) && (i++ < RADEON_TIMEOUT)); - - if (ret == 0) return; - - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Idle timed out, resetting engine...\n"); - if (info->ChipFamily < CHIP_FAMILY_R600) { - RADEONEngineReset(pScrn); - RADEONEngineRestore(pScrn); - } else - R600EngineReset(pScrn); - - /* Always restart the engine when doing CP 2D acceleration */ - RADEONCP_RESET(pScrn, info); - RADEONCP_START(pScrn, info); - } - } -#endif - - if (info->ChipFamily >= CHIP_FAMILY_R600) { - if (!info->accelOn) - return; - - /* Wait for the engine to go idle */ - if (info->ChipFamily >= CHIP_FAMILY_RV770) - R600WaitForFifoFunction(pScrn, 8); - else - R600WaitForFifoFunction(pScrn, 16); - - for (;;) { - for (i = 0; i < RADEON_TIMEOUT; i++) { - if (!(INREG(R600_GRBM_STATUS) & R600_GUI_ACTIVE)) - return; - } - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "Idle timed out: stat=0x%08x\n", - (unsigned int)INREG(R600_GRBM_STATUS)); - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Idle timed out, resetting engine...\n"); - R600EngineReset(pScrn); -#ifdef XF86DRI - if (info->directRenderingEnabled) { - RADEONCP_RESET(pScrn, info); - RADEONCP_START(pScrn, info); - } -#endif - } + BEGIN_ACCEL(3); + if (IS_AVIVO_VARIANT) { + OUT_ACCEL_REG(AVIVO_D1MODE_VLINE_START_END, /* this is just a marker */ + ((start << AVIVO_D1MODE_VLINE_START_SHIFT) | + (stop << AVIVO_D1MODE_VLINE_END_SHIFT) | + AVIVO_D1MODE_VLINE_INV)); } else { - /* Wait for the engine to go idle */ - RADEONWaitForFifoFunction(pScrn, 64); - - for (;;) { - for (i = 0; i < RADEON_TIMEOUT; i++) { - if (!(INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)) { - RADEONEngineFlush(pScrn); - return; - } - } - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "Idle timed out: %u entries, stat=0x%08x\n", - (unsigned int)INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK, - (unsigned int)INREG(RADEON_RBBM_STATUS)); - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Idle timed out, resetting engine...\n"); - RADEONEngineReset(pScrn); - RADEONEngineRestore(pScrn); -#ifdef XF86DRI - if (info->directRenderingEnabled) { - RADEONCP_RESET(pScrn, info); - RADEONCP_START(pScrn, info); - } -#endif - } + OUT_ACCEL_REG(RADEON_CRTC_GUI_TRIG_VLINE, /* another placeholder */ + ((start << RADEON_CRTC_GUI_TRIG_VLINE_START_SHIFT) | + (stop << RADEON_CRTC_GUI_TRIG_VLINE_END_SHIFT) | + RADEON_CRTC_GUI_TRIG_VLINE_INV | + RADEON_CRTC_GUI_TRIG_VLINE_STALL)); } + OUT_ACCEL_REG(RADEON_WAIT_UNTIL, (RADEON_WAIT_CRTC_VLINE | + RADEON_ENG_DISPLAY_SELECT_CRTC0)); + + OUT_RING(CP_PACKET3(RADEON_CP_PACKET3_NOP, 0)); + OUT_RING(drmmode_crtc->mode_crtc->crtc_id); + FINISH_ACCEL(); } + diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c deleted file mode 100644 index 18b01559..00000000 --- a/src/radeon_crtc.c +++ /dev/null @@ -1,1128 +0,0 @@ -/* - * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and - * VA Linux Systems Inc., Fremont, California. - * - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation on the rights to use, copy, modify, merge, - * publish, distribute, sublicense, and/or sell copies of the Software, - * and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR - * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include <string.h> -#include <stdio.h> -#include <assert.h> -#include <math.h> - -/* X and server generic header files */ -#include "xf86.h" -#include "xf86_OSproc.h" -#include "vgaHW.h" -#include "xf86Modes.h" - -/* Driver data structures */ -#include "radeon.h" -#include "radeon_reg.h" -#include "radeon_macros.h" -#include "radeon_probe.h" -#include "radeon_version.h" - -#ifdef XF86DRI -#define _XF86DRI_SERVER_ -#include "radeon_drm.h" -#include "sarea.h" -#endif - -extern void atombios_crtc_mode_set(xf86CrtcPtr crtc, - DisplayModePtr mode, - DisplayModePtr adjusted_mode, - int x, int y); -extern void atombios_crtc_dpms(xf86CrtcPtr crtc, int mode); -extern void -RADEONInitDispBandwidthLegacy(ScrnInfoPtr pScrn, - DisplayModePtr mode1, int pixel_bytes1, - DisplayModePtr mode2, int pixel_bytes2); -extern void -RADEONInitDispBandwidthAVIVO(ScrnInfoPtr pScrn, - DisplayModePtr mode1, int pixel_bytes1, - DisplayModePtr mode2, int pixel_bytes2); - -void -radeon_do_crtc_dpms(xf86CrtcPtr crtc, int mode) -{ - RADEONInfoPtr info = RADEONPTR(crtc->scrn); - RADEONEntPtr pRADEONEnt = RADEONEntPriv(crtc->scrn); - xf86CrtcPtr crtc0 = pRADEONEnt->pCrtc[0]; - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - - if (IS_AVIVO_VARIANT || info->r4xx_atom) { - atombios_crtc_dpms(crtc, mode); - } else { - - /* need to restore crtc1 before crtc0 or we may get a blank screen - * in some cases - */ - if ((radeon_crtc->crtc_id == 1) && (mode == DPMSModeOn)) { - if (crtc0->enabled) - legacy_crtc_dpms(crtc0, DPMSModeOff); - } - - legacy_crtc_dpms(crtc, mode); - - if ((radeon_crtc->crtc_id == 1) && (mode == DPMSModeOn)) { - if (crtc0->enabled) - legacy_crtc_dpms(crtc0, mode); - } - } -} - -void -radeon_crtc_dpms(xf86CrtcPtr crtc, int mode) -{ - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - - if ((mode == DPMSModeOn) && radeon_crtc->enabled) - return; - - if (mode == DPMSModeOff) - radeon_crtc_modeset_ioctl(crtc, FALSE); - - radeon_do_crtc_dpms(crtc, mode); - - if (mode != DPMSModeOff) { - radeon_crtc_modeset_ioctl(crtc, TRUE); - radeon_crtc_load_lut(crtc); - } - - if (mode == DPMSModeOn) - radeon_crtc->enabled = TRUE; - else - radeon_crtc->enabled = FALSE; -} - -static Bool -radeon_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode, - DisplayModePtr adjusted_mode) -{ - return TRUE; -} - -static void -radeon_crtc_mode_prepare(xf86CrtcPtr crtc) -{ - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - - if (radeon_crtc->enabled) - crtc->funcs->hide_cursor(crtc); -} - -static uint32_t RADEONDiv(CARD64 n, uint32_t d) -{ - return (n + (d / 2)) / d; -} - -static void -RADEONComputePLL_old(RADEONPLLPtr pll, - unsigned long freq, - uint32_t *chosen_dot_clock_freq, - uint32_t *chosen_feedback_div, - uint32_t *chosen_frac_feedback_div, - uint32_t *chosen_reference_div, - uint32_t *chosen_post_div, - int flags) -{ - uint32_t min_ref_div = pll->min_ref_div; - uint32_t max_ref_div = pll->max_ref_div; - uint32_t min_post_div = pll->min_post_div; - uint32_t max_post_div = pll->max_post_div; - uint32_t min_fractional_feed_div = 0; - uint32_t max_fractional_feed_div = 0; - uint32_t best_vco = pll->best_vco; - uint32_t best_post_div = 1; - uint32_t best_ref_div = 1; - uint32_t best_feedback_div = 1; - uint32_t best_frac_feedback_div = 0; - uint32_t best_freq = -1; - uint32_t best_error = 0xffffffff; - uint32_t best_vco_diff = 1; - uint32_t post_div; - - freq = freq * 1000; - - ErrorF("freq: %lu\n", freq); - - if (flags & RADEON_PLL_USE_REF_DIV) - min_ref_div = max_ref_div = pll->reference_div; - else { - while (min_ref_div < max_ref_div-1) { - uint32_t mid=(min_ref_div+max_ref_div)/2; - uint32_t pll_in = pll->reference_freq / mid; - if (pll_in < pll->pll_in_min) - max_ref_div = mid; - else if (pll_in > pll->pll_in_max) - min_ref_div = mid; - else break; - } - } - - if (flags & RADEON_PLL_USE_POST_DIV) - min_post_div = max_post_div = pll->post_div; - - if (flags & RADEON_PLL_USE_FRAC_FB_DIV) { - min_fractional_feed_div = pll->min_frac_feedback_div; - max_fractional_feed_div = pll->max_frac_feedback_div; - } - - for (post_div = min_post_div; post_div <= max_post_div; ++post_div) { - uint32_t ref_div; - - if ((flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) - continue; - - /* legacy radeons only have a few post_divs */ - if (flags & RADEON_PLL_LEGACY) { - if ((post_div == 5) || - (post_div == 7) || - (post_div == 9) || - (post_div == 10) || - (post_div == 11)) - continue; - } - - for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { - uint32_t feedback_div, current_freq = 0, error, vco_diff; - uint32_t pll_in = pll->reference_freq / ref_div; - uint32_t min_feed_div = pll->min_feedback_div; - uint32_t max_feed_div = pll->max_feedback_div+1; - - if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) - continue; - - while (min_feed_div < max_feed_div) { - uint32_t vco; - uint32_t min_frac_feed_div = min_fractional_feed_div; - uint32_t max_frac_feed_div = max_fractional_feed_div+1; - uint32_t frac_feedback_div; - CARD64 tmp; - - feedback_div = (min_feed_div+max_feed_div)/2; - - tmp = (CARD64)pll->reference_freq * feedback_div; - vco = RADEONDiv(tmp, ref_div); - - if (vco < pll->pll_out_min) { - min_feed_div = feedback_div+1; - continue; - } else if(vco > pll->pll_out_max) { - max_feed_div = feedback_div; - continue; - } - - while (min_frac_feed_div < max_frac_feed_div) { - frac_feedback_div = (min_frac_feed_div+max_frac_feed_div)/2; - tmp = (CARD64)pll->reference_freq * 10000 * feedback_div; - tmp += (CARD64)pll->reference_freq * 1000 * frac_feedback_div; - current_freq = RADEONDiv(tmp, ref_div * post_div); - - if (flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { - error = freq - current_freq; - error = (int32_t)error < 0 ? 0xffffffff : error; - } else - error = abs(current_freq - freq); - vco_diff = abs(vco - best_vco); - - if ((best_vco == 0 && error < best_error) || - (best_vco != 0 && - (error < best_error - 100 || - (abs(error - best_error) < 100 && vco_diff < best_vco_diff )))) { - best_post_div = post_div; - best_ref_div = ref_div; - best_feedback_div = feedback_div; - best_frac_feedback_div = frac_feedback_div; - best_freq = current_freq; - best_error = error; - best_vco_diff = vco_diff; - } else if (current_freq == freq) { - if (best_freq == -1) { - best_post_div = post_div; - best_ref_div = ref_div; - best_feedback_div = feedback_div; - best_frac_feedback_div = frac_feedback_div; - best_freq = current_freq; - best_error = error; - best_vco_diff = vco_diff; - } else if (((flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || - ((flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || - ((flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || - ((flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || - ((flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || - ((flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { - best_post_div = post_div; - best_ref_div = ref_div; - best_feedback_div = feedback_div; - best_frac_feedback_div = frac_feedback_div; - best_freq = current_freq; - best_error = error; - best_vco_diff = vco_diff; - } - } - if (current_freq < freq) - min_frac_feed_div = frac_feedback_div+1; - else - max_frac_feed_div = frac_feedback_div; - } - if (current_freq < freq) - min_feed_div = feedback_div+1; - else - max_feed_div = feedback_div; - } - } - } - - ErrorF("best_freq: %u\n", (unsigned int)best_freq); - ErrorF("best_feedback_div: %u\n", (unsigned int)best_feedback_div); - ErrorF("best_frac_feedback_div: %u\n", (unsigned int)best_frac_feedback_div); - ErrorF("best_ref_div: %u\n", (unsigned int)best_ref_div); - ErrorF("best_post_div: %u\n", (unsigned int)best_post_div); - - if (best_freq == -1) - FatalError("Couldn't find valid PLL dividers\n"); - *chosen_dot_clock_freq = best_freq / 10000; - *chosen_feedback_div = best_feedback_div; - *chosen_frac_feedback_div = best_frac_feedback_div; - *chosen_reference_div = best_ref_div; - *chosen_post_div = best_post_div; - -} - -static Bool -calc_fb_div(RADEONPLLPtr pll, - unsigned long freq, - int flags, - int post_div, - int ref_div, - int *fb_div, - int *fb_div_frac) -{ - float ffreq = freq / 10; - float vco_freq = ffreq * post_div; - float feedback_divider = vco_freq * ref_div / pll->reference_freq; - - if (flags & RADEON_PLL_USE_FRAC_FB_DIV) { - feedback_divider = floor((feedback_divider * 10.0) + 0.5) * 0.1; - - *fb_div = floor(feedback_divider); - *fb_div_frac = fmod(feedback_divider, 1.0) * 10.0; - - } else { - *fb_div = floor(feedback_divider + 0.5); - *fb_div_frac = 0; - } - if ((*fb_div < pll->min_feedback_div) || (*fb_div > pll->max_feedback_div)) - return FALSE; - else - return TRUE; -} - -static Bool -calc_fb_ref_div(RADEONPLLPtr pll, - unsigned long freq, - int flags, - int post_div, - int *fb_div, - int *fb_div_frac, - int *ref_div) -{ - float ffreq = freq / 10; - float max_error = ffreq * 0.0025; - float vco, error, pll_out; - - for ((*ref_div) = pll->min_ref_div; (*ref_div) < pll->max_ref_div; ++(*ref_div)) { - if (calc_fb_div(pll, freq, flags, post_div, (*ref_div), fb_div, fb_div_frac)) { - vco = pll->reference_freq * ((*fb_div) + ((*fb_div_frac) * 0.1)) / (*ref_div); - - if ((vco < pll->pll_out_min) || (vco > pll->pll_out_max)) - continue; - - pll_out = vco / post_div; - - error = pll_out - ffreq; - if ((fabs(error) <= max_error) && (error >= 0)) - return TRUE; - } - } - return FALSE; -} - -static void -RADEONComputePLL_new(RADEONPLLPtr pll, - unsigned long freq, - uint32_t *chosen_dot_clock_freq, - uint32_t *chosen_feedback_div, - uint32_t *chosen_frac_feedback_div, - uint32_t *chosen_reference_div, - uint32_t *chosen_post_div, - int flags) -{ - float ffreq = freq / 10; - float vco_frequency; - int fb_div = 0, fb_div_frac = 0, post_div = 0, ref_div = 0; - uint32_t best_freq = 0; - - if (flags & RADEON_PLL_USE_POST_DIV) { - post_div = pll->post_div; - if ((post_div < pll->min_post_div) || (post_div > pll->max_post_div)) - goto done; - vco_frequency = ffreq * post_div; - if ((vco_frequency < pll->pll_out_min) || (vco_frequency > pll->pll_out_max)) - goto done; - - if (flags & RADEON_PLL_USE_REF_DIV) { - ref_div = pll->reference_div; - if ((ref_div < pll->min_ref_div) || (ref_div > pll->max_ref_div)) - goto done; - if (!calc_fb_div(pll, freq, flags, post_div, ref_div, &fb_div, &fb_div_frac)) - goto done; - } - } else { - for (post_div = pll->max_post_div; post_div >= pll->min_post_div; --post_div) { - if (flags & RADEON_PLL_LEGACY) { - if ((post_div == 5) || - (post_div == 7) || - (post_div == 9) || - (post_div == 10) || - (post_div == 11)) - continue; - } - if ((flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) - continue; - - vco_frequency = ffreq * post_div; - if ((vco_frequency < pll->pll_out_min) || (vco_frequency > pll->pll_out_max)) - continue; - if (flags & RADEON_PLL_USE_REF_DIV) { - ref_div = pll->reference_div; - if ((ref_div < pll->min_ref_div) || (ref_div > pll->max_ref_div)) - goto done; - if (calc_fb_div(pll, freq, flags, post_div, ref_div, &fb_div, &fb_div_frac)) - break; - } else { - if (calc_fb_ref_div(pll, freq, flags, post_div, &fb_div, &fb_div_frac, &ref_div)) - break; - } - } - } - - best_freq = pll->reference_freq * 10 * fb_div; - best_freq += pll->reference_freq * fb_div_frac; - best_freq = best_freq / (ref_div * post_div); - - ErrorF("best_freq: %u\n", (unsigned int)best_freq); - ErrorF("best_feedback_div: %u\n", (unsigned int)fb_div); - ErrorF("best_frac_feedback_div: %u\n", (unsigned int)fb_div_frac); - ErrorF("best_ref_div: %u\n", (unsigned int)ref_div); - ErrorF("best_post_div: %u\n", (unsigned int)post_div); - -done: - if (best_freq == 0) - FatalError("Couldn't find valid PLL dividers\n"); - - *chosen_dot_clock_freq = best_freq; - *chosen_feedback_div = fb_div; - *chosen_frac_feedback_div = fb_div_frac; - *chosen_reference_div = ref_div; - *chosen_post_div = post_div; - -} - -void -RADEONComputePLL(xf86CrtcPtr crtc, - RADEONPLLPtr pll, - unsigned long freq, - uint32_t *chosen_dot_clock_freq, - uint32_t *chosen_feedback_div, - uint32_t *chosen_frac_feedback_div, - uint32_t *chosen_reference_div, - uint32_t *chosen_post_div, - int flags) -{ - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - - switch (radeon_crtc->pll_algo) { - case RADEON_PLL_OLD: - RADEONComputePLL_old(pll, freq, chosen_dot_clock_freq, - chosen_feedback_div, chosen_frac_feedback_div, - chosen_reference_div, chosen_post_div, flags); - break; - case RADEON_PLL_NEW: - /* disable frac fb dividers */ - flags &= ~RADEON_PLL_USE_FRAC_FB_DIV; - RADEONComputePLL_new(pll, freq, chosen_dot_clock_freq, - chosen_feedback_div, chosen_frac_feedback_div, - chosen_reference_div, chosen_post_div, flags); - break; - } -} - -static void -radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, - DisplayModePtr adjusted_mode, int x, int y) -{ - ScrnInfoPtr pScrn = crtc->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - - if (IS_AVIVO_VARIANT || info->r4xx_atom) { - atombios_crtc_mode_set(crtc, mode, adjusted_mode, x, y); - } else { - legacy_crtc_mode_set(crtc, mode, adjusted_mode, x, y); - } -} - -static void -radeon_crtc_mode_commit(xf86CrtcPtr crtc) -{ - if (crtc->scrn->pScreen != NULL) - xf86_reload_cursors(crtc->scrn->pScreen); -} - -void -radeon_crtc_load_lut(xf86CrtcPtr crtc) -{ - ScrnInfoPtr pScrn = crtc->scrn; - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - int i; - - if (!crtc->enabled) - return; - - radeon_save_palette_on_demand(pScrn, radeon_crtc->crtc_id); - - if (IS_DCE4_VARIANT) { - OUTREG(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); - - OUTREG(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); - OUTREG(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); - OUTREG(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); - - OUTREG(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0x0000ffff); - OUTREG(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0x0000ffff); - OUTREG(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0x0000ffff); - - OUTREG(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); - OUTREG(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); - - for (i = 0; i < 256; i++) { - OUTREG(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, i); - OUTREG(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, - (((radeon_crtc->lut_r[i]) << 20) | - ((radeon_crtc->lut_g[i]) << 10) | - (radeon_crtc->lut_b[i]))); - } - } else { - if (IS_AVIVO_VARIANT) { - OUTREG(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); - - OUTREG(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); - OUTREG(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); - OUTREG(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); - - OUTREG(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0x0000ffff); - OUTREG(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0x0000ffff); - OUTREG(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0x0000ffff); - } - - PAL_SELECT(radeon_crtc->crtc_id); - - if (IS_AVIVO_VARIANT) { - OUTREG(AVIVO_DC_LUT_RW_MODE, 0); - OUTREG(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f); - } - - for (i = 0; i < 256; i++) { - OUTPAL(i, radeon_crtc->lut_r[i], radeon_crtc->lut_g[i], radeon_crtc->lut_b[i]); - } - - if (IS_AVIVO_VARIANT) - OUTREG(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id); - } -} - -static void -radeon_crtc_gamma_set(xf86CrtcPtr crtc, uint16_t *red, uint16_t *green, - uint16_t *blue, int size) -{ - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - int i; - - for (i = 0; i < 256; i++) { - radeon_crtc->lut_r[i] = red[i] >> 6; - radeon_crtc->lut_g[i] = green[i] >> 6; - radeon_crtc->lut_b[i] = blue[i] >> 6; - } - - radeon_crtc_load_lut(crtc); -} - -static Bool -radeon_crtc_lock(xf86CrtcPtr crtc) -{ - ScrnInfoPtr pScrn = crtc->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - -#ifdef XF86DRI - if (info->cp->CPStarted && pScrn->pScreen) { - DRILock(pScrn->pScreen, 0); - if (info->accelOn) - RADEON_SYNC(info, pScrn); - return TRUE; - } -#endif - if (info->accelOn) - RADEON_SYNC(info, pScrn); - - return FALSE; - -} - -static void -radeon_crtc_unlock(xf86CrtcPtr crtc) -{ - ScrnInfoPtr pScrn = crtc->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - -#ifdef XF86DRI - if (info->cp->CPStarted && pScrn->pScreen) DRIUnlock(pScrn->pScreen); -#endif - - if (info->accelOn) - RADEON_SYNC(info, pScrn); -} - -/** - * Allocates memory for a locked-in-framebuffer shadow of the given - * width and height for this CRTC's rotated shadow framebuffer. - */ - -static void * -radeon_crtc_shadow_allocate (xf86CrtcPtr crtc, int width, int height) -{ - ScrnInfoPtr pScrn = crtc->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - unsigned long rotate_pitch; - unsigned long rotate_offset; - int size; - int cpp = pScrn->bitsPerPixel / 8; - - /* No rotation without accel */ - if (((info->ChipFamily >= CHIP_FAMILY_R600) && !info->directRenderingEnabled) || - xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Acceleration required for rotation\n"); - return NULL; - } - - rotate_pitch = pScrn->displayWidth * cpp; - size = rotate_pitch * height; - - /* We could get close to what we want here by just creating a pixmap like - * normal, but we have to lock it down in framebuffer, and there is no - * setter for offscreen area locking in EXA currently. So, we just - * allocate offscreen memory and fake up a pixmap header for it. - */ - rotate_offset = radeon_legacy_allocate_memory(pScrn, &radeon_crtc->crtc_rotate_mem, - size, RADEON_GPU_PAGE_SIZE, RADEON_GEM_DOMAIN_VRAM); - if (rotate_offset == 0) - return NULL; - - return info->FB + rotate_offset; -} - -/** - * Creates a pixmap for this CRTC's rotated shadow framebuffer. - */ -static PixmapPtr -radeon_crtc_shadow_create(xf86CrtcPtr crtc, void *data, int width, int height) -{ - ScrnInfoPtr pScrn = crtc->scrn; - unsigned long rotate_pitch; - PixmapPtr rotate_pixmap; - int cpp = pScrn->bitsPerPixel / 8; - - if (!data) - data = radeon_crtc_shadow_allocate(crtc, width, height); - - rotate_pitch = pScrn->displayWidth * cpp; - - rotate_pixmap = GetScratchPixmapHeader(pScrn->pScreen, - width, height, - pScrn->depth, - pScrn->bitsPerPixel, - rotate_pitch, - data); - - if (rotate_pixmap == NULL) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Couldn't allocate shadow pixmap for rotated CRTC\n"); - } - - return rotate_pixmap; -} - -static void -radeon_crtc_shadow_destroy(xf86CrtcPtr crtc, PixmapPtr rotate_pixmap, void *data) -{ - ScrnInfoPtr pScrn = crtc->scrn; - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - - if (rotate_pixmap) - FreeScratchPixmapHeader(rotate_pixmap); - - if (data) { - radeon_legacy_free_memory(pScrn, radeon_crtc->crtc_rotate_mem); - radeon_crtc->crtc_rotate_mem = NULL; - } - -} - -#if XF86_CRTC_VERSION >= 2 -#include "radeon_atombios.h" - -extern AtomBiosResult -atombios_lock_crtc(atomBiosHandlePtr atomBIOS, int crtc, int lock); -extern void -RADEONInitCrtcBase(xf86CrtcPtr crtc, RADEONSavePtr save, - int x, int y); -extern void -RADEONInitCrtc2Base(xf86CrtcPtr crtc, RADEONSavePtr save, - int x, int y); -extern void -RADEONRestoreCrtcBase(ScrnInfoPtr pScrn, - RADEONSavePtr restore); -extern void -RADEONRestoreCrtc2Base(ScrnInfoPtr pScrn, - RADEONSavePtr restore); - -static void -radeon_crtc_set_origin(xf86CrtcPtr crtc, int x, int y) -{ - ScrnInfoPtr pScrn = crtc->scrn; - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - - if (IS_DCE4_VARIANT) { - x &= ~3; - y &= ~1; - atombios_lock_crtc(info->atomBIOS, radeon_crtc->crtc_id, 1); - OUTREG(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset, (x << 16) | y); - atombios_lock_crtc(info->atomBIOS, radeon_crtc->crtc_id, 0); - } else if (IS_AVIVO_VARIANT) { - x &= ~3; - y &= ~1; - atombios_lock_crtc(info->atomBIOS, radeon_crtc->crtc_id, 1); - OUTREG(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, (x << 16) | y); - atombios_lock_crtc(info->atomBIOS, radeon_crtc->crtc_id, 0); - } else { - switch (radeon_crtc->crtc_id) { - case 0: - RADEONInitCrtcBase(crtc, info->ModeReg, x, y); - RADEONRestoreCrtcBase(pScrn, info->ModeReg); - break; - case 1: - RADEONInitCrtc2Base(crtc, info->ModeReg, x, y); - RADEONRestoreCrtc2Base(pScrn, info->ModeReg); - break; - default: - break; - } - } -} -#endif - - -static xf86CrtcFuncsRec radeon_crtc_funcs = { - .dpms = radeon_crtc_dpms, - .save = NULL, /* XXX */ - .restore = NULL, /* XXX */ - .mode_fixup = radeon_crtc_mode_fixup, - .prepare = radeon_crtc_mode_prepare, - .mode_set = radeon_crtc_mode_set, - .commit = radeon_crtc_mode_commit, - .gamma_set = radeon_crtc_gamma_set, - .lock = radeon_crtc_lock, - .unlock = radeon_crtc_unlock, - .shadow_create = radeon_crtc_shadow_create, - .shadow_allocate = radeon_crtc_shadow_allocate, - .shadow_destroy = radeon_crtc_shadow_destroy, - .set_cursor_colors = radeon_crtc_set_cursor_colors, - .set_cursor_position = radeon_crtc_set_cursor_position, - .show_cursor = radeon_crtc_show_cursor, - .hide_cursor = radeon_crtc_hide_cursor, - .load_cursor_argb = radeon_crtc_load_cursor_argb, - .destroy = NULL, /* XXX */ -#if XF86_CRTC_VERSION >= 2 - .set_origin = radeon_crtc_set_origin, -#endif -}; - -void -RADEONInitDispBandwidth(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); - DisplayModePtr mode1 = NULL, mode2 = NULL; - int pixel_bytes1 = info->CurrentLayout.pixel_bytes; - int pixel_bytes2 = info->CurrentLayout.pixel_bytes; - - /* XXX fix me */ - if (IS_DCE4_VARIANT) - return; - - if (xf86_config->num_crtc == 2) { - if (xf86_config->crtc[1]->enabled && - xf86_config->crtc[0]->enabled) { - mode1 = &xf86_config->crtc[0]->mode; - mode2 = &xf86_config->crtc[1]->mode; - } else if (xf86_config->crtc[0]->enabled) { - mode1 = &xf86_config->crtc[0]->mode; - } else if (xf86_config->crtc[1]->enabled) { - mode2 = &xf86_config->crtc[1]->mode; - } else - return; - } else { - if (info->IsPrimary) - mode1 = &xf86_config->crtc[0]->mode; - else if (info->IsSecondary) - mode2 = &xf86_config->crtc[0]->mode; - else if (xf86_config->crtc[0]->enabled) - mode1 = &xf86_config->crtc[0]->mode; - else - return; - } - - if (IS_AVIVO_VARIANT) - RADEONInitDispBandwidthAVIVO(pScrn, mode1, pixel_bytes1, mode2, pixel_bytes2); - else - RADEONInitDispBandwidthLegacy(pScrn, mode1, pixel_bytes1, mode2, pixel_bytes2); -} - -Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask) -{ - RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); - RADEONInfoPtr info = RADEONPTR(pScrn); - int i; - - if (!xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) { - radeon_crtc_funcs.shadow_create = radeon_crtc_shadow_create; - radeon_crtc_funcs.shadow_allocate = radeon_crtc_shadow_allocate; - radeon_crtc_funcs.shadow_destroy = radeon_crtc_shadow_destroy; - } - - if (mask & 1) { - if (pRADEONEnt->Controller[0]) - return TRUE; - - pRADEONEnt->pCrtc[0] = xf86CrtcCreate(pScrn, &radeon_crtc_funcs); - if (!pRADEONEnt->pCrtc[0]) - return FALSE; - - pRADEONEnt->Controller[0] = xnfcalloc(sizeof(RADEONCrtcPrivateRec), 1); - if (!pRADEONEnt->Controller[0]) - return FALSE; - - pRADEONEnt->pCrtc[0]->driver_private = pRADEONEnt->Controller[0]; - pRADEONEnt->Controller[0]->crtc_id = 0; - pRADEONEnt->Controller[0]->crtc_offset = 0; - pRADEONEnt->Controller[0]->initialized = FALSE; - if (info->allowColorTiling) - pRADEONEnt->Controller[0]->can_tile = 1; - else - pRADEONEnt->Controller[0]->can_tile = 0; - pRADEONEnt->Controller[0]->pll_id = -1; - } - - if (mask & 2) { - if (!pRADEONEnt->HasCRTC2) - return TRUE; - - pRADEONEnt->pCrtc[1] = xf86CrtcCreate(pScrn, &radeon_crtc_funcs); - if (!pRADEONEnt->pCrtc[1]) - return FALSE; - - pRADEONEnt->Controller[1] = xnfcalloc(sizeof(RADEONCrtcPrivateRec), 1); - if (!pRADEONEnt->Controller[1]) - { - free(pRADEONEnt->Controller[0]); - return FALSE; - } - - pRADEONEnt->pCrtc[1]->driver_private = pRADEONEnt->Controller[1]; - pRADEONEnt->Controller[1]->crtc_id = 1; - if (IS_DCE4_VARIANT) - pRADEONEnt->Controller[1]->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET; - else - pRADEONEnt->Controller[1]->crtc_offset = AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; - pRADEONEnt->Controller[1]->initialized = FALSE; - if (info->allowColorTiling) - pRADEONEnt->Controller[1]->can_tile = 1; - else - pRADEONEnt->Controller[1]->can_tile = 0; - pRADEONEnt->Controller[1]->pll_id = -1; - } - - /* 6 crtcs on DCE4 chips */ - if (IS_DCE4_VARIANT && ((mask & 3) == 3) && !IS_DCE41_VARIANT) { - for (i = 2; i < RADEON_MAX_CRTC; i++) { - pRADEONEnt->pCrtc[i] = xf86CrtcCreate(pScrn, &radeon_crtc_funcs); - if (!pRADEONEnt->pCrtc[i]) - return FALSE; - - pRADEONEnt->Controller[i] = xnfcalloc(sizeof(RADEONCrtcPrivateRec), 1); - if (!pRADEONEnt->Controller[i]) - { - free(pRADEONEnt->Controller[i]); - return FALSE; - } - - pRADEONEnt->pCrtc[i]->driver_private = pRADEONEnt->Controller[i]; - pRADEONEnt->Controller[i]->crtc_id = i; - switch (i) { - case 0: - pRADEONEnt->Controller[i]->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET; - break; - case 1: - pRADEONEnt->Controller[i]->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET; - break; - case 2: - pRADEONEnt->Controller[i]->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET; - break; - case 3: - pRADEONEnt->Controller[i]->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET; - break; - case 4: - pRADEONEnt->Controller[i]->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET; - break; - case 5: - pRADEONEnt->Controller[i]->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET; - break; - } - pRADEONEnt->Controller[i]->initialized = FALSE; - if (info->allowColorTiling) - pRADEONEnt->Controller[i]->can_tile = 1; - else - pRADEONEnt->Controller[i]->can_tile = 0; - pRADEONEnt->Controller[i]->pll_id = -1; - } - } - - return TRUE; -} - -/** - * In the current world order, there are lists of modes per output, which may - * or may not include the mode that was asked to be set by XFree86's mode - * selection. Find the closest one, in the following preference order: - * - * - Equality - * - Closer in size to the requested mode, but no larger - * - Closer in refresh rate to the requested mode. - */ -DisplayModePtr -RADEONCrtcFindClosestMode(xf86CrtcPtr crtc, DisplayModePtr pMode) -{ - ScrnInfoPtr pScrn = crtc->scrn; - xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); - DisplayModePtr pBest = NULL, pScan = NULL; - int i; - - /* Assume that there's only one output connected to the given CRTC. */ - for (i = 0; i < xf86_config->num_output; i++) - { - xf86OutputPtr output = xf86_config->output[i]; - if (output->crtc == crtc && output->probed_modes != NULL) - { - pScan = output->probed_modes; - break; - } - } - - /* If the pipe doesn't have any detected modes, just let the system try to - * spam the desired mode in. - */ - if (pScan == NULL) { - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "No crtc mode list for crtc %d," - "continuing with desired mode\n", radeon_crtc->crtc_id); - return pMode; - } - - for (; pScan != NULL; pScan = pScan->next) { - assert(pScan->VRefresh != 0.0); - - /* If there's an exact match, we're done. */ - if (xf86ModesEqual(pScan, pMode)) { - pBest = pMode; - break; - } - - /* Reject if it's larger than the desired mode. */ - if (pScan->HDisplay > pMode->HDisplay || - pScan->VDisplay > pMode->VDisplay) - { - continue; - } - - if (pBest == NULL) { - pBest = pScan; - continue; - } - - /* Find if it's closer to the right size than the current best - * option. - */ - if ((pScan->HDisplay > pBest->HDisplay && - pScan->VDisplay >= pBest->VDisplay) || - (pScan->HDisplay >= pBest->HDisplay && - pScan->VDisplay > pBest->VDisplay)) - { - pBest = pScan; - continue; - } - - /* Find if it's still closer to the right refresh than the current - * best resolution. - */ - if (pScan->HDisplay == pBest->HDisplay && - pScan->VDisplay == pBest->VDisplay && - (fabs(pScan->VRefresh - pMode->VRefresh) < - fabs(pBest->VRefresh - pMode->VRefresh))) { - pBest = pScan; - } - } - - if (pBest == NULL) { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "No suitable mode found to program for the pipe.\n" - " continuing with desired mode %dx%d@%.1f\n", - pMode->HDisplay, pMode->VDisplay, pMode->VRefresh); - } else if (!xf86ModesEqual(pBest, pMode)) { - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - int crtc = radeon_crtc->crtc_id; - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "Choosing pipe %d's mode %dx%d@%.1f instead of xf86 " - "mode %dx%d@%.1f\n", crtc, - pBest->HDisplay, pBest->VDisplay, pBest->VRefresh, - pMode->HDisplay, pMode->VDisplay, pMode->VRefresh); - pMode = pBest; - } - return pMode; -} - -void -RADEONBlank(ScrnInfoPtr pScrn) -{ - xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); - xf86OutputPtr output; - xf86CrtcPtr crtc; - int o, c; - - for (c = 0; c < xf86_config->num_crtc; c++) { - crtc = xf86_config->crtc[c]; - for (o = 0; o < xf86_config->num_output; o++) { - output = xf86_config->output[o]; - if (output->crtc != crtc) - continue; - - output->funcs->dpms(output, DPMSModeOff); - } - crtc->funcs->dpms(crtc, DPMSModeOff); - } -} - -void -RADEONUnblank(ScrnInfoPtr pScrn) -{ - xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); - xf86OutputPtr output; - xf86CrtcPtr crtc; - int o, c; - - for (c = 0; c < xf86_config->num_crtc; c++) { - crtc = xf86_config->crtc[c]; - if(!crtc->enabled) - continue; - crtc->funcs->dpms(crtc, DPMSModeOn); - for (o = 0; o < xf86_config->num_output; o++) { - output = xf86_config->output[o]; - if (output->crtc != crtc) - continue; - - output->funcs->dpms(output, DPMSModeOn); - } - } -} - -Bool -RADEONSetTiling(ScrnInfoPtr pScrn) -{ - xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONCrtcPrivatePtr radeon_crtc; - xf86CrtcPtr crtc; - int c; - int can_tile = 1; - Bool changed = FALSE; - - for (c = 0; c < xf86_config->num_crtc; c++) { - crtc = xf86_config->crtc[c]; - radeon_crtc = crtc->driver_private; - - if (crtc->enabled) { - if (!radeon_crtc->can_tile) - can_tile = 0; - } - } - - if (info->tilingEnabled != can_tile) - changed = TRUE; - -#ifdef XF86DRI - if (info->directRenderingEnabled && (info->tilingEnabled != can_tile)) { - drm_radeon_sarea_t *pSAREAPriv; - if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_SWITCH_TILING, (can_tile ? 1 : 0)) < 0) - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "[drm] failed changing tiling status\n"); - /* if this is called during ScreenInit() we don't have pScrn->pScreen yet */ - pSAREAPriv = DRIGetSAREAPrivate(xf86ScrnToScreen(pScrn)); - info->tilingEnabled = pSAREAPriv->tiling_enabled ? TRUE : FALSE; - } -#endif - - return changed; -} diff --git a/src/radeon_cursor.c b/src/radeon_cursor.c deleted file mode 100644 index faf71aee..00000000 --- a/src/radeon_cursor.c +++ /dev/null @@ -1,449 +0,0 @@ -/* - * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and - * VA Linux Systems Inc., Fremont, California. - * - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation on the rights to use, copy, modify, merge, - * publish, distribute, sublicense, and/or sell copies of the Software, - * and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR - * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#define RADEONCTRACE(x) -/*#define RADEONCTRACE(x) RADEONTRACE(x) */ - -/* - * Authors: - * Kevin E. Martin <martin@xfree86.org> - * Rickard E. Faith <faith@valinux.com> - * - * References: - * - * !!!! FIXME !!!! - * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical - * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April - * 1999. - * - * RAGE 128 Software Development Manual (Technical Reference Manual P/N - * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999. - * - */ - - /* Driver data structures */ -#include "radeon.h" -#include "radeon_version.h" -#include "radeon_reg.h" -#include "radeon_macros.h" - - /* X and server generic header files */ -#include "xf86.h" - -#define CURSOR_WIDTH 64 -#define CURSOR_HEIGHT 64 - -/* - * The cursor bits are always 32bpp. On MSBFirst buses, - * configure byte swapping to swap 32 bit units when writing - * the cursor image. Byte swapping must always be returned - * to its previous value before returning. - */ -#if X_BYTE_ORDER == X_BIG_ENDIAN - -#define CURSOR_SWAPPING_DECL_MMIO unsigned char *RADEONMMIO = info->MMIO; -#define CURSOR_SWAPPING_START() \ - do { \ - if (info->ChipFamily < CHIP_FAMILY_R600) \ - OUTREG(RADEON_SURFACE_CNTL, \ - (info->ModeReg->surface_cntl | \ - RADEON_NONSURF_AP0_SWP_32BPP | RADEON_NONSURF_AP1_SWP_32BPP) & \ - ~(RADEON_NONSURF_AP0_SWP_16BPP | RADEON_NONSURF_AP1_SWP_16BPP)); \ - } while (0) -#define CURSOR_SWAPPING_END() \ - do { \ - if (info->ChipFamily < CHIP_FAMILY_R600) \ - OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl); \ - } while (0) -#else - -#define CURSOR_SWAPPING_DECL_MMIO -#define CURSOR_SWAPPING_START() -#define CURSOR_SWAPPING_END() - -#endif - -static void -avivo_setup_cursor(xf86CrtcPtr crtc, Bool enable) -{ - ScrnInfoPtr pScrn = crtc->scrn; - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - RADEONInfoPtr info = RADEONPTR(crtc->scrn); - unsigned char *RADEONMMIO = info->MMIO; - - /* always use the same cursor mode even if the cursor is disabled, - * otherwise you may end up with cursor curruption bands - */ - OUTREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset, (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT)); - - if (enable) { - uint64_t location = info->fbLocation + radeon_crtc->cursor_offset + pScrn->fbOffset; - if (info->ChipFamily >= CHIP_FAMILY_RV770) { - if (radeon_crtc->crtc_id) - OUTREG(R700_D2CUR_SURFACE_ADDRESS_HIGH, (location >> 32) & 0xf); - else - OUTREG(R700_D1CUR_SURFACE_ADDRESS_HIGH, (location >> 32) & 0xf); - } - OUTREG(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, - info->fbLocation + radeon_crtc->cursor_offset + pScrn->fbOffset); - OUTREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset, - AVIVO_D1CURSOR_EN | (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT)); - } -} - -static void -avivo_lock_cursor(xf86CrtcPtr crtc, Bool lock) -{ - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - RADEONInfoPtr info = RADEONPTR(crtc->scrn); - unsigned char *RADEONMMIO = info->MMIO; - uint32_t tmp; - - tmp = INREG(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset); - - if (lock) - tmp |= AVIVO_D1CURSOR_UPDATE_LOCK; - else - tmp &= ~AVIVO_D1CURSOR_UPDATE_LOCK; - - OUTREG(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, tmp); -} - -static void -evergreen_setup_cursor(xf86CrtcPtr crtc, Bool enable) -{ - ScrnInfoPtr pScrn = crtc->scrn; - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - RADEONInfoPtr info = RADEONPTR(crtc->scrn); - unsigned char *RADEONMMIO = info->MMIO; - - /* always use the same cursor mode even if the cursor is disabled, - * otherwise you may end up with cursor curruption bands - */ - OUTREG(EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset, - EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT)); - - if (enable) { - uint64_t location = info->fbLocation + radeon_crtc->cursor_offset + pScrn->fbOffset; - OUTREG(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, - (location >> 32) & 0xf); - OUTREG(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, - location & EVERGREEN_CUR_SURFACE_ADDRESS_MASK); - OUTREG(EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset, - EVERGREEN_CURSOR_EN | EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT)); - } -} - -static void -evergreen_lock_cursor(xf86CrtcPtr crtc, Bool lock) -{ - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - RADEONInfoPtr info = RADEONPTR(crtc->scrn); - unsigned char *RADEONMMIO = info->MMIO; - uint32_t tmp; - - tmp = INREG(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset); - - if (lock) - tmp |= EVERGREEN_CURSOR_UPDATE_LOCK; - else - tmp &= ~EVERGREEN_CURSOR_UPDATE_LOCK; - - OUTREG(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, tmp); -} - -void -radeon_crtc_show_cursor (xf86CrtcPtr crtc) -{ - ScrnInfoPtr pScrn = crtc->scrn; - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - int crtc_id = radeon_crtc->crtc_id; - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - if (IS_DCE4_VARIANT) { - evergreen_lock_cursor(crtc, TRUE); - evergreen_setup_cursor(crtc, TRUE); - evergreen_lock_cursor(crtc, FALSE); - } else if (IS_AVIVO_VARIANT) { - avivo_lock_cursor(crtc, TRUE); - avivo_setup_cursor(crtc, TRUE); - avivo_lock_cursor(crtc, FALSE); - } else { - switch (crtc_id) { - case 0: - OUTREG(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL); - break; - case 1: - OUTREG(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL); - break; - default: - return; - } - - OUTREGP(RADEON_MM_DATA, RADEON_CRTC_CUR_EN | 2 << 20, - ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK)); - } -} - -void -radeon_crtc_hide_cursor (xf86CrtcPtr crtc) -{ - ScrnInfoPtr pScrn = crtc->scrn; - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - int crtc_id = radeon_crtc->crtc_id; - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - if (IS_DCE4_VARIANT) { - evergreen_lock_cursor(crtc, TRUE); - evergreen_setup_cursor(crtc, FALSE); - evergreen_lock_cursor(crtc, FALSE); - } else if (IS_AVIVO_VARIANT) { - avivo_lock_cursor(crtc, TRUE); - avivo_setup_cursor(crtc, FALSE); - avivo_lock_cursor(crtc, FALSE); - } else { - switch(crtc_id) { - case 0: - OUTREG(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL); - break; - case 1: - OUTREG(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL); - break; - default: - return; - } - - OUTREGP(RADEON_MM_DATA, 0, ~RADEON_CRTC_CUR_EN); - } -} - -void -radeon_crtc_set_cursor_position (xf86CrtcPtr crtc, int x, int y) -{ - ScrnInfoPtr pScrn = crtc->scrn; - RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - int crtc_id = radeon_crtc->crtc_id; - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - int xorigin = 0, yorigin = 0; - int stride = 256; - DisplayModePtr mode = &crtc->mode; - int w = CURSOR_WIDTH; - - if (x < 0) xorigin = -x+1; - if (y < 0) yorigin = -y+1; - if (xorigin >= CURSOR_WIDTH) xorigin = CURSOR_WIDTH - 1; - if (yorigin >= CURSOR_HEIGHT) yorigin = CURSOR_HEIGHT - 1; - - if (IS_AVIVO_VARIANT) { - /* avivo cursor spans the full fb width */ - if (crtc->rotatedData == NULL) { - x += crtc->x; - y += crtc->y; - } - - if (pRADEONEnt->Controller[0]->enabled && - pRADEONEnt->Controller[1]->enabled) { - int cursor_end, frame_end; - - cursor_end = x - xorigin + w; - frame_end = crtc->x + mode->CrtcHDisplay; - - if (cursor_end >= frame_end) { - w = w - (cursor_end - frame_end); - if (!(frame_end & 0x7f)) - w--; - } else { - if (!(cursor_end & 0x7f)) - w--; - } - if (w <= 0) - w = 1; - } - } - - if (IS_DCE4_VARIANT) { - evergreen_lock_cursor(crtc, TRUE); - OUTREG(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, ((xorigin ? 0 : x) << 16) - | (yorigin ? 0 : y)); - OUTREG(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin); - OUTREG(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset, - ((w - 1) << 16) | (CURSOR_HEIGHT - 1)); - evergreen_lock_cursor(crtc, FALSE); - } else if (IS_AVIVO_VARIANT) { - avivo_lock_cursor(crtc, TRUE); - OUTREG(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, ((xorigin ? 0 : x) << 16) - | (yorigin ? 0 : y)); - OUTREG(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin); - OUTREG(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset, ((w - 1) << 16) | (CURSOR_HEIGHT - 1)); - avivo_lock_cursor(crtc, FALSE); - } else { - if (mode->Flags & V_DBLSCAN) - y *= 2; - - if (crtc_id == 0) { - OUTREG(RADEON_CUR_HORZ_VERT_OFF, (RADEON_CUR_LOCK - | (xorigin << 16) - | yorigin)); - OUTREG(RADEON_CUR_HORZ_VERT_POSN, (RADEON_CUR_LOCK - | ((xorigin ? 0 : x) << 16) - | (yorigin ? 0 : y))); - RADEONCTRACE(("cursor_offset: 0x%x, yorigin: %d, stride: %d, temp %08X\n", - radeon_crtc->cursor_offset + pScrn->fbOffset, yorigin, stride, temp)); - OUTREG(RADEON_CUR_OFFSET, - radeon_crtc->cursor_offset + pScrn->fbOffset + yorigin * stride); - } else if (crtc_id == 1) { - OUTREG(RADEON_CUR2_HORZ_VERT_OFF, (RADEON_CUR2_LOCK - | (xorigin << 16) - | yorigin)); - OUTREG(RADEON_CUR2_HORZ_VERT_POSN, (RADEON_CUR2_LOCK - | ((xorigin ? 0 : x) << 16) - | (yorigin ? 0 : y))); - RADEONCTRACE(("cursor_offset2: 0x%x, yorigin: %d, stride: %d, temp %08X\n", - radeon_crtc->cursor_offset + pScrn->fbOffset, yorigin, stride, temp)); - OUTREG(RADEON_CUR2_OFFSET, - radeon_crtc->cursor_offset + pScrn->fbOffset + yorigin * stride); - } - } -} - -void -radeon_crtc_set_cursor_colors (xf86CrtcPtr crtc, int bg, int fg) -{ - ScrnInfoPtr pScrn = crtc->scrn; - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - RADEONInfoPtr info = RADEONPTR(pScrn); - uint32_t *pixels = (uint32_t *)(pointer)(info->FB + pScrn->fbOffset + radeon_crtc->cursor_offset); - int pixel, i; - CURSOR_SWAPPING_DECL_MMIO - - RADEONCTRACE(("RADEONSetCursorColors\n")); - -#ifdef ARGB_CURSOR - /* Don't recolour cursors set with SetCursorARGB. */ - if (info->cursor_argb) - return; -#endif - - fg |= 0xff000000; - bg |= 0xff000000; - - /* Don't recolour the image if we don't have to. */ - if (fg == info->cursor_fg && bg == info->cursor_bg) - return; - - CURSOR_SWAPPING_START(); - - /* Note: We assume that the pixels are either fully opaque or fully - * transparent, so we won't premultiply them, and we can just - * check for non-zero pixel values; those are either fg or bg - */ - for (i = 0; i < CURSOR_WIDTH * CURSOR_HEIGHT; i++, pixels++) - if ((pixel = *pixels)) - *pixels = (pixel == info->cursor_fg) ? fg : bg; - - CURSOR_SWAPPING_END(); - info->cursor_fg = fg; - info->cursor_bg = bg; -} - -#ifdef ARGB_CURSOR - -void -radeon_crtc_load_cursor_argb (xf86CrtcPtr crtc, CARD32 *image) -{ - ScrnInfoPtr pScrn = crtc->scrn; - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - RADEONInfoPtr info = RADEONPTR(pScrn); - CURSOR_SWAPPING_DECL_MMIO - uint32_t *d = (uint32_t *)(pointer)(info->FB + pScrn->fbOffset + radeon_crtc->cursor_offset); - - RADEONCTRACE(("RADEONLoadCursorARGB\n")); - - info->cursor_argb = TRUE; - - CURSOR_SWAPPING_START(); - - memcpy (d, image, CURSOR_HEIGHT * CURSOR_WIDTH * 4); - - CURSOR_SWAPPING_END (); -} - -#endif - - -/* Initialize hardware cursor support. */ -Bool RADEONCursorInit(ScreenPtr pScreen) -{ - ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); - int c; - - for (c = 0; c < xf86_config->num_crtc; c++) { - xf86CrtcPtr crtc = xf86_config->crtc[c]; - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - - if (!info->useEXA) { - int size_bytes = CURSOR_WIDTH * 4 * CURSOR_HEIGHT; - int align = IS_AVIVO_VARIANT ? 4096 : 256; - - radeon_crtc->cursor_offset = - radeon_legacy_allocate_memory(pScrn, &radeon_crtc->cursor_mem, - size_bytes, align, RADEON_GEM_DOMAIN_VRAM); - - if (radeon_crtc->cursor_offset == 0) - return FALSE; - - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Will use %d kb for hardware cursor %d at offset 0x%08x\n", - (size_bytes * xf86_config->num_crtc) / 1024, - c, - (unsigned int)radeon_crtc->cursor_offset); - } - /* set the cursor mode the same on both crtcs to avoid corruption */ - /* XXX check if this is needed on evergreen */ - if (IS_AVIVO_VARIANT) - OUTREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset, - (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT)); - } - - return xf86_cursors_init (pScreen, CURSOR_WIDTH, CURSOR_HEIGHT, - (HARDWARE_CURSOR_TRUECOLOR_AT_8BPP | - HARDWARE_CURSOR_AND_SOURCE_WITH_MASK | - HARDWARE_CURSOR_SOURCE_MASK_INTERLEAVE_1 | - HARDWARE_CURSOR_ARGB)); -} diff --git a/src/radeon_dri.c b/src/radeon_dri.c deleted file mode 100644 index f180f3a2..00000000 --- a/src/radeon_dri.c +++ /dev/null @@ -1,2347 +0,0 @@ -/* - * Copyright 2000 ATI Technologies Inc., Markham, Ontario, - * VA Linux Systems Inc., Fremont, California. - * - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation on the rights to use, copy, modify, merge, - * publish, distribute, sublicense, and/or sell copies of the Software, - * and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR - * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -/* - * Authors: - * Kevin E. Martin <martin@xfree86.org> - * Rickard E. Faith <faith@valinux.com> - * Gareth Hughes <gareth@valinux.com> - * - */ - -#include <string.h> -#include <stdio.h> - - /* Driver data structures */ -#include "radeon.h" -#include "radeon_video.h" -#include "radeon_reg.h" -#include "r600_reg.h" -#include "radeon_macros.h" -#include "radeon_drm.h" -#include "radeon_dri.h" -#include "radeon_version.h" - - - /* X and server generic header files */ -#include "xf86.h" -#include "windowstr.h" - - /* GLX/DRI/DRM definitions */ -#define _XF86DRI_SERVER_ -#include "GL/glxtokens.h" -#include "sarea.h" - -#include "atipciids.h" - -static size_t radeon_drm_page_size; - -#define RADEON_MAX_DRAWABLES 256 - -extern void GlxSetVisualConfigs(int nconfigs, __GLXvisualConfig *configs, - void **configprivs); - -static void RADEONDRITransitionTo2d(ScreenPtr pScreen); -static void RADEONDRITransitionTo3d(ScreenPtr pScreen); -static void RADEONDRITransitionMultiToSingle3d(ScreenPtr pScreen); -static void RADEONDRITransitionSingleToMulti3d(ScreenPtr pScreen); - -#ifdef DAMAGE -static void RADEONDRIRefreshArea(ScrnInfoPtr pScrn, RegionPtr pReg); - -#if (DRIINFO_MAJOR_VERSION > 5 || \ - (DRIINFO_MAJOR_VERSION == 5 && DRIINFO_MINOR_VERSION >= 1)) -static void RADEONDRIClipNotify(ScreenPtr pScreen, WindowPtr *ppWin, int num); -#endif -#endif - -/* Initialize the visual configs that are supported by the hardware. - * These are combined with the visual configs that the indirect - * rendering core supports, and the intersection is exported to the - * client. - */ -static Bool RADEONInitVisualConfigs(ScreenPtr pScreen) -{ - ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); - RADEONInfoPtr info = RADEONPTR(pScrn); - int numConfigs = 0; - __GLXvisualConfig *pConfigs = 0; - RADEONConfigPrivPtr pRADEONConfigs = 0; - RADEONConfigPrivPtr *pRADEONConfigPtrs = 0; - int i, accum, stencil, db, use_db; - - use_db = !info->dri->noBackBuffer ? 1 : 0; - - switch (info->CurrentLayout.pixel_code) { - case 8: /* 8bpp mode is not support */ - case 15: /* FIXME */ - case 24: /* FIXME */ - xf86DrvMsg(pScreen->myNum, X_ERROR, - "[dri] RADEONInitVisualConfigs failed " - "(depth %d not supported). " - "Disabling DRI.\n", info->CurrentLayout.pixel_code); - return FALSE; - -#define RADEON_USE_ACCUM 1 -#define RADEON_USE_STENCIL 1 - - case 16: - numConfigs = 1; - if (RADEON_USE_ACCUM) numConfigs *= 2; - if (RADEON_USE_STENCIL) numConfigs *= 2; - if (use_db) numConfigs *= 2; - - if (!(pConfigs - = (__GLXvisualConfig *)calloc(sizeof(__GLXvisualConfig), - numConfigs))) { - return FALSE; - } - if (!(pRADEONConfigs - = (RADEONConfigPrivPtr)calloc(sizeof(RADEONConfigPrivRec), - numConfigs))) { - free(pConfigs); - return FALSE; - } - if (!(pRADEONConfigPtrs - = (RADEONConfigPrivPtr *)calloc(sizeof(RADEONConfigPrivPtr), - numConfigs))) { - free(pConfigs); - free(pRADEONConfigs); - return FALSE; - } - - i = 0; - for (db = use_db; db >= 0; db--) { - for (accum = 0; accum <= RADEON_USE_ACCUM; accum++) { - for (stencil = 0; stencil <= RADEON_USE_STENCIL; stencil++) { - pRADEONConfigPtrs[i] = &pRADEONConfigs[i]; - - pConfigs[i].vid = (VisualID)(-1); - pConfigs[i].class = -1; - pConfigs[i].rgba = TRUE; - pConfigs[i].redSize = 5; - pConfigs[i].greenSize = 6; - pConfigs[i].blueSize = 5; - pConfigs[i].alphaSize = 0; - pConfigs[i].redMask = 0x0000F800; - pConfigs[i].greenMask = 0x000007E0; - pConfigs[i].blueMask = 0x0000001F; - pConfigs[i].alphaMask = 0x00000000; - if (accum) { /* Simulated in software */ - pConfigs[i].accumRedSize = 16; - pConfigs[i].accumGreenSize = 16; - pConfigs[i].accumBlueSize = 16; - pConfigs[i].accumAlphaSize = 0; - } else { - pConfigs[i].accumRedSize = 0; - pConfigs[i].accumGreenSize = 0; - pConfigs[i].accumBlueSize = 0; - pConfigs[i].accumAlphaSize = 0; - } - if (db) - pConfigs[i].doubleBuffer = TRUE; - else - pConfigs[i].doubleBuffer = FALSE; - pConfigs[i].stereo = FALSE; - pConfigs[i].bufferSize = 16; - pConfigs[i].depthSize = info->dri->depthBits; - if (pConfigs[i].depthSize == 24 ? (RADEON_USE_STENCIL - stencil) - : stencil) { - pConfigs[i].stencilSize = 8; - } else { - pConfigs[i].stencilSize = 0; - } - pConfigs[i].auxBuffers = 0; - pConfigs[i].level = 0; - if (accum || - (pConfigs[i].stencilSize && pConfigs[i].depthSize == 16)) { - pConfigs[i].visualRating = GLX_SLOW_CONFIG; - } else { - pConfigs[i].visualRating = GLX_NONE; - } - pConfigs[i].transparentPixel = GLX_NONE; - pConfigs[i].transparentRed = 0; - pConfigs[i].transparentGreen = 0; - pConfigs[i].transparentBlue = 0; - pConfigs[i].transparentAlpha = 0; - pConfigs[i].transparentIndex = 0; - i++; - } - } - } - break; - - case 32: - numConfigs = 1; - if (RADEON_USE_ACCUM) numConfigs *= 2; - if (RADEON_USE_STENCIL) numConfigs *= 2; - if (use_db) numConfigs *= 2; - - if (!(pConfigs - = (__GLXvisualConfig *)calloc(sizeof(__GLXvisualConfig), - numConfigs))) { - return FALSE; - } - if (!(pRADEONConfigs - = (RADEONConfigPrivPtr)calloc(sizeof(RADEONConfigPrivRec), - numConfigs))) { - free(pConfigs); - return FALSE; - } - if (!(pRADEONConfigPtrs - = (RADEONConfigPrivPtr *)calloc(sizeof(RADEONConfigPrivPtr), - numConfigs))) { - free(pConfigs); - free(pRADEONConfigs); - return FALSE; - } - - i = 0; - for (db = use_db; db >= 0; db--) { - for (accum = 0; accum <= RADEON_USE_ACCUM; accum++) { - for (stencil = 0; stencil <= RADEON_USE_STENCIL; stencil++) { - pRADEONConfigPtrs[i] = &pRADEONConfigs[i]; - - pConfigs[i].vid = (VisualID)(-1); - pConfigs[i].class = -1; - pConfigs[i].rgba = TRUE; - pConfigs[i].redSize = 8; - pConfigs[i].greenSize = 8; - pConfigs[i].blueSize = 8; - pConfigs[i].alphaSize = 8; - pConfigs[i].redMask = 0x00FF0000; - pConfigs[i].greenMask = 0x0000FF00; - pConfigs[i].blueMask = 0x000000FF; - pConfigs[i].alphaMask = 0xFF000000; - if (accum) { /* Simulated in software */ - pConfigs[i].accumRedSize = 16; - pConfigs[i].accumGreenSize = 16; - pConfigs[i].accumBlueSize = 16; - pConfigs[i].accumAlphaSize = 16; - } else { - pConfigs[i].accumRedSize = 0; - pConfigs[i].accumGreenSize = 0; - pConfigs[i].accumBlueSize = 0; - pConfigs[i].accumAlphaSize = 0; - } - if (db) - pConfigs[i].doubleBuffer = TRUE; - else - pConfigs[i].doubleBuffer = FALSE; - pConfigs[i].stereo = FALSE; - pConfigs[i].bufferSize = 32; - pConfigs[i].depthSize = info->dri->depthBits; - if (pConfigs[i].depthSize == 24 ? (RADEON_USE_STENCIL - stencil) - : stencil) { - pConfigs[i].stencilSize = 8; - } else { - pConfigs[i].stencilSize = 0; - } - pConfigs[i].auxBuffers = 0; - pConfigs[i].level = 0; - if (accum || - (pConfigs[i].stencilSize && pConfigs[i].depthSize == 16)) { - pConfigs[i].visualRating = GLX_SLOW_CONFIG; - } else { - pConfigs[i].visualRating = GLX_NONE; - } - pConfigs[i].transparentPixel = GLX_NONE; - pConfigs[i].transparentRed = 0; - pConfigs[i].transparentGreen = 0; - pConfigs[i].transparentBlue = 0; - pConfigs[i].transparentAlpha = 0; - pConfigs[i].transparentIndex = 0; - i++; - } - } - } - break; - } - - info->dri->numVisualConfigs = numConfigs; - info->dri->pVisualConfigs = pConfigs; - info->dri->pVisualConfigsPriv = pRADEONConfigs; - GlxSetVisualConfigs(numConfigs, pConfigs, (void**)pRADEONConfigPtrs); - return TRUE; -} - -/* Create the Radeon-specific context information */ -static Bool RADEONCreateContext(ScreenPtr pScreen, VisualPtr visual, - drm_context_t hwContext, void *pVisualConfigPriv, - DRIContextType contextStore) -{ - return TRUE; -} - -/* Destroy the Radeon-specific context information */ -static void RADEONDestroyContext(ScreenPtr pScreen, drm_context_t hwContext, - DRIContextType contextStore) -{ -} - -/* Called when the X server is woken up to allow the last client's - * context to be saved and the X server's context to be loaded. This is - * not necessary for the Radeon since the client detects when it's - * context is not currently loaded and then load's it itself. Since the - * registers to start and stop the CP are privileged, only the X server - * can start/stop the engine. - */ -static void RADEONEnterServer(ScreenPtr pScreen) -{ - ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); - RADEONInfoPtr info = RADEONPTR(pScrn); - drm_radeon_sarea_t *pSAREAPriv; - - - RADEON_MARK_SYNC(info, pScrn); - - pSAREAPriv = DRIGetSAREAPrivate(pScrn->pScreen); - if (pSAREAPriv->ctx_owner != DRIGetContext(pScrn->pScreen)) { - info->accel_state->XInited3D = FALSE; - info->cp->needCacheFlush = (info->ChipFamily >= CHIP_FAMILY_R300); - } - -#ifdef DAMAGE - if (!info->dri->pDamage && info->dri->allowPageFlip) { - PixmapPtr pPix = pScreen->GetScreenPixmap(pScreen); - info->dri->pDamage = DamageCreate(NULL, NULL, DamageReportNone, TRUE, - pScreen, pPix); - - if (info->dri->pDamage == NULL) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "No screen damage record, page flipping disabled\n"); - info->dri->allowPageFlip = 0; - } else { - DamageRegister(&pPix->drawable, info->dri->pDamage); - - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Damage tracking initialized for page flipping\n"); - } - } -#endif -} - -/* Called when the X server goes to sleep to allow the X server's - * context to be saved and the last client's context to be loaded. This - * is not necessary for the Radeon since the client detects when it's - * context is not currently loaded and then load's it itself. Since the - * registers to start and stop the CP are privileged, only the X server - * can start/stop the engine. - */ -static void RADEONLeaveServer(ScreenPtr pScreen) -{ - ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); - RADEONInfoPtr info = RADEONPTR(pScrn); - RING_LOCALS; - -#ifdef DAMAGE - if (info->dri->pDamage) { - RegionPtr pDamageReg = DamageRegion(info->dri->pDamage); - int nrects = pDamageReg ? REGION_NUM_RECTS(pDamageReg) : 0; - - if (nrects) { - RADEONDRIRefreshArea(pScrn, pDamageReg); - } - } -#endif - - /* The CP is always running, but if we've generated any CP commands - * we must flush them to the kernel module now. - */ - RADEONCP_RELEASE(pScrn, info); - -#ifdef USE_EXA - info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN; -#endif -} - -/* Contexts can be swapped by the X server if necessary. This callback - * is currently only used to perform any functions necessary when - * entering or leaving the X server, and in the future might not be - * necessary. - */ -static void RADEONDRISwapContext(ScreenPtr pScreen, DRISyncType syncType, - DRIContextType oldContextType, - void *oldContext, - DRIContextType newContextType, - void *newContext) -{ - if ((syncType==DRI_3D_SYNC) && (oldContextType==DRI_2D_CONTEXT) && - (newContextType==DRI_2D_CONTEXT)) { /* Entering from Wakeup */ - RADEONEnterServer(pScreen); - } - - if ((syncType==DRI_2D_SYNC) && (oldContextType==DRI_NO_CONTEXT) && - (newContextType==DRI_2D_CONTEXT)) { /* Exiting from Block Handler */ - RADEONLeaveServer(pScreen); - } -} - -#ifdef USE_XAA - -/* The Radeon has depth tiling on all the time. Rely on surface regs to - * translate the addresses (only works if allowColorTiling is true). - */ - -/* 16-bit depth buffer functions */ -#define WRITE_DEPTH16(_x, _y, d) \ - *(uint16_t *)(pointer)(buf + 2*(_x + _y*info->dri->frontPitch)) = (d) - -#define READ_DEPTH16(d, _x, _y) \ - (d) = *(uint16_t *)(pointer)(buf + 2*(_x + _y*info->dri->frontPitch)) - -/* 32-bit depth buffer (stencil and depth simultaneously) functions */ -#define WRITE_DEPTHSTENCIL32(_x, _y, d) \ - *(uint32_t *)(pointer)(buf + 4*(_x + _y*info->dri->frontPitch)) = (d) - -#define READ_DEPTHSTENCIL32(d, _x, _y) \ - (d) = *(uint32_t *)(pointer)(buf + 4*(_x + _y*info->dri->frontPitch)) - -/* Screen to screen copy of data in the depth buffer */ -static void RADEONScreenToScreenCopyDepth(ScrnInfoPtr pScrn, - int xa, int ya, - int xb, int yb, - int w, int h) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *buf = info->FB + info->dri->depthOffset; - int xstart, xend, xdir; - int ystart, yend, ydir; - int x, y, d; - - if (xa < xb) xdir = -1, xstart = w-1, xend = 0; - else xdir = 1, xstart = 0, xend = w-1; - - if (ya < yb) ydir = -1, ystart = h-1, yend = 0; - else ydir = 1, ystart = 0, yend = h-1; - - switch (pScrn->bitsPerPixel) { - case 16: - for (x = xstart; x != xend; x += xdir) { - for (y = ystart; y != yend; y += ydir) { - READ_DEPTH16(d, xa+x, ya+y); - WRITE_DEPTH16(xb+x, yb+y, d); - } - } - break; - - case 32: - for (x = xstart; x != xend; x += xdir) { - for (y = ystart; y != yend; y += ydir) { - READ_DEPTHSTENCIL32(d, xa+x, ya+y); - WRITE_DEPTHSTENCIL32(xb+x, yb+y, d); - } - } - break; - - default: - break; - } -} - -#endif /* USE_XAA */ - -/* Initialize the state of the back and depth buffers */ -static void RADEONDRIInitBuffers(WindowPtr pWin, RegionPtr prgn, CARD32 indx) -{ - /* NOOP. There's no need for the 2d driver to be clearing buffers - * for the 3d client. It knows how to do that on its own. - */ -} - -/* Copy the back and depth buffers when the X server moves a window. - * - * This routine is a modified form of XAADoBitBlt with the calls to - * ScreenToScreenBitBlt built in. My routine has the prgnSrc as source - * instead of destination. My origin is upside down so the ydir cases - * are reversed. - */ -static void RADEONDRIMoveBuffers(WindowPtr pParent, DDXPointRec ptOldOrg, - RegionPtr prgnSrc, CARD32 indx) -{ -#ifdef USE_XAA - ScreenPtr pScreen = pParent->drawable.pScreen; - ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); - RADEONInfoPtr info = RADEONPTR(pScrn); - - BoxPtr pboxTmp, pboxNext, pboxBase; - DDXPointPtr pptTmp; - int xdir, ydir; - - int screenwidth = pScrn->virtualX; - int screenheight = pScrn->virtualY; - - BoxPtr pbox = REGION_RECTS(prgnSrc); - int nbox = REGION_NUM_RECTS(prgnSrc); - - BoxPtr pboxNew1 = NULL; - BoxPtr pboxNew2 = NULL; - DDXPointPtr pptNew1 = NULL; - DDXPointPtr pptNew2 = NULL; - DDXPointPtr pptSrc = &ptOldOrg; - - int dx = pParent->drawable.x - ptOldOrg.x; - int dy = pParent->drawable.y - ptOldOrg.y; - - /* XXX: Fix in EXA case. */ - if (info->useEXA) - return; - - /* If the copy will overlap in Y, reverse the order */ - if (dy > 0) { - ydir = -1; - - if (nbox > 1) { - /* Keep ordering in each band, reverse order of bands */ - pboxNew1 = (BoxPtr)malloc(sizeof(BoxRec)*nbox); - if (!pboxNew1) return; - - pptNew1 = (DDXPointPtr)malloc(sizeof(DDXPointRec)*nbox); - if (!pptNew1) { - free(pboxNew1); - return; - } - - pboxBase = pboxNext = pbox+nbox-1; - - while (pboxBase >= pbox) { - while ((pboxNext >= pbox) && (pboxBase->y1 == pboxNext->y1)) - pboxNext--; - - pboxTmp = pboxNext+1; - pptTmp = pptSrc + (pboxTmp - pbox); - - while (pboxTmp <= pboxBase) { - *pboxNew1++ = *pboxTmp++; - *pptNew1++ = *pptTmp++; - } - - pboxBase = pboxNext; - } - - pboxNew1 -= nbox; - pbox = pboxNew1; - pptNew1 -= nbox; - pptSrc = pptNew1; - } - } else { - /* No changes required */ - ydir = 1; - } - - /* If the regions will overlap in X, reverse the order */ - if (dx > 0) { - xdir = -1; - - if (nbox > 1) { - /* reverse order of rects in each band */ - pboxNew2 = (BoxPtr)malloc(sizeof(BoxRec)*nbox); - pptNew2 = (DDXPointPtr)malloc(sizeof(DDXPointRec)*nbox); - - if (!pboxNew2 || !pptNew2) { - free(pptNew2); - free(pboxNew2); - free(pptNew1); - free(pboxNew1); - return; - } - - pboxBase = pboxNext = pbox; - - while (pboxBase < pbox+nbox) { - while ((pboxNext < pbox+nbox) - && (pboxNext->y1 == pboxBase->y1)) - pboxNext++; - - pboxTmp = pboxNext; - pptTmp = pptSrc + (pboxTmp - pbox); - - while (pboxTmp != pboxBase) { - *pboxNew2++ = *--pboxTmp; - *pptNew2++ = *--pptTmp; - } - - pboxBase = pboxNext; - } - - pboxNew2 -= nbox; - pbox = pboxNew2; - pptNew2 -= nbox; - pptSrc = pptNew2; - } - } else { - /* No changes are needed */ - xdir = 1; - } - - /* pretty much a hack. */ - info->accel_state->dst_pitch_offset = info->dri->backPitchOffset; - if (info->tilingEnabled) - info->accel_state->dst_pitch_offset |= RADEON_DST_TILE_MACRO; - - (*info->accel_state->accel->SetupForScreenToScreenCopy)(pScrn, xdir, ydir, GXcopy, - (uint32_t)(-1), -1); - - for (; nbox-- ; pbox++) { - int xa = pbox->x1; - int ya = pbox->y1; - int destx = xa + dx; - int desty = ya + dy; - int w = pbox->x2 - xa + 1; - int h = pbox->y2 - ya + 1; - - if (destx < 0) xa -= destx, w += destx, destx = 0; - if (desty < 0) ya -= desty, h += desty, desty = 0; - if (destx + w > screenwidth) w = screenwidth - destx; - if (desty + h > screenheight) h = screenheight - desty; - - if (w <= 0) continue; - if (h <= 0) continue; - - (*info->accel_state->accel->SubsequentScreenToScreenCopy)(pScrn, - xa, ya, - destx, desty, - w, h); - - if (info->dri->depthMoves) { - RADEONScreenToScreenCopyDepth(pScrn, - xa, ya, - destx, desty, - w, h); - } - } - - info->accel_state->dst_pitch_offset = info->dri->frontPitchOffset;; - - free(pptNew2); - free(pboxNew2); - free(pptNew1); - free(pboxNew1); - - info->accel_state->accel->NeedToSync = TRUE; -#endif /* USE_XAA */ -} - -static void RADEONDRIInitGARTValues(RADEONInfoPtr info) -{ - int s, l; - - info->dri->gartOffset = 0; - - /* Initialize the CP ring buffer data */ - info->dri->ringStart = info->dri->gartOffset; - info->dri->ringMapSize = info->dri->ringSize*1024*1024 + radeon_drm_page_size; - info->dri->ringSizeLog2QW = RADEONMinBits(info->dri->ringSize*1024*1024/8)-1; - - info->dri->ringReadOffset = info->dri->ringStart + info->dri->ringMapSize; - info->dri->ringReadMapSize = radeon_drm_page_size; - - /* Reserve space for vertex/indirect buffers */ - info->dri->bufStart = info->dri->ringReadOffset + info->dri->ringReadMapSize; - info->dri->bufMapSize = info->dri->bufSize*1024*1024; - - /* Reserve the rest for GART textures */ - info->dri->gartTexStart = info->dri->bufStart + info->dri->bufMapSize; - s = (info->dri->gartSize*1024*1024 - info->dri->gartTexStart); - l = RADEONMinBits((s-1) / RADEON_NR_TEX_REGIONS); - if (l < RADEON_LOG_TEX_GRANULARITY) l = RADEON_LOG_TEX_GRANULARITY; - info->dri->gartTexMapSize = (s >> l) << l; - info->dri->log2GARTTexGran = l; -} - -/* AGP Mode Quirk List - Certain hostbridge/gfx-card combos don't work with - * the standard AGPMode settings, so we detect and handle these - * on a case-by-base basis with quirks. To see if an AGPMode is valid, test - * it by setting Option "AGPMode" "1" (or "2", or "4", or "8"). */ -typedef struct { - unsigned int hostbridgeVendor; - unsigned int hostbridgeDevice; - unsigned int chipVendor; - unsigned int chipDevice; - unsigned int subsysVendor; - unsigned int subsysDevice; - unsigned int defaultMode; -} radeon_agpmode_quirk, *radeon_agpmode_quirk_ptr; - -/* Keep sorted by hostbridge vendor and device */ -static radeon_agpmode_quirk radeon_agpmode_quirk_list[] = { - - /* Intel E7505 Memory Controller Hub / RV350 AR [Radeon 9600XT] Needs AGPMode 4 (deb #515326) */ - { PCI_VENDOR_INTEL,0x2550, PCI_VENDOR_ATI,0x4152, 0x1458,0x4038, 4 }, - /* Intel 82865G/PE/P DRAM Controller/Host-Hub / Mobility 9800 Needs AGPMode 4 (deb #462590) */ - { PCI_VENDOR_INTEL,0x2570, PCI_VENDOR_ATI,0x4a4e, PCI_VENDOR_DELL,0x5106, 4 }, - /* Intel 82865G/PE/P DRAM Controller/Host-Hub / RV280 [Radeon 9200 SE] Needs AGPMode 4 (lp #300304) */ - { PCI_VENDOR_INTEL,0x2570, PCI_VENDOR_ATI,0x5964, 0x148c,0x2073, 4 }, - /* Intel 82855PM host bridge / Mobility M7 LW Needs AGPMode 4 (lp: #353996) */ - { PCI_VENDOR_INTEL,0x3340, PCI_VENDOR_ATI,0x4c57, PCI_VENDOR_IBM,0x0530, 4 }, - /* Intel 82855PM Processor to I/O Controller / Mobility M6 LY Needs AGPMode 1 (deb #467235) */ - { PCI_VENDOR_INTEL,0x3340, PCI_VENDOR_ATI,0x4c59, PCI_VENDOR_IBM,0x052f, 1 }, - /* Intel 82855PM host bridge / Mobility 9600 M10 RV350 Needs AGPMode 1 (lp #195051) */ - { PCI_VENDOR_INTEL,0x3340, PCI_VENDOR_ATI,0x4e50, PCI_VENDOR_IBM,0x0550, 1 }, - /* Intel 82855PM host bridge / FireGL Mobility T2 RV350 Needs AGPMode 2 (fdo #20647) */ - { PCI_VENDOR_INTEL,0x3340, PCI_VENDOR_ATI,0x4e54, PCI_VENDOR_IBM,0x054f, 2 }, - /* Intel 82855PM host bridge / Mobility M9+ / VaioPCG-V505DX Needs AGPMode 2 (fdo #17928) */ - { PCI_VENDOR_INTEL,0x3340, PCI_VENDOR_ATI,0x5c61, PCI_VENDOR_SONY,0x816b, 2 }, - /* Intel 82855PM Processor to I/O Controller / Mobility M9+ Needs AGPMode 8 (phoronix forum) */ - { PCI_VENDOR_INTEL,0x3340, PCI_VENDOR_ATI,0x5c61, PCI_VENDOR_SONY,0x8195, 8 }, - /* Intel 82830 830 Chipset Host Bridge / Mobility M6 LY Needs AGPMode 2 (fdo #17360)*/ - { PCI_VENDOR_INTEL,0x3575, PCI_VENDOR_ATI,0x4c59, PCI_VENDOR_DELL,0x00e3, 2 }, - /* Intel 82852/82855 host bridge / Mobility FireGL 9000 R250 Needs AGPMode 1 (lp #296617) */ - { PCI_VENDOR_INTEL,0x3580, PCI_VENDOR_ATI,0x4c66, PCI_VENDOR_DELL,0x0149, 1 }, - /* Intel 82852/82855 host bridge / Mobility 9600 M10 RV350 Needs AGPMode 1 (deb #467460) */ - { PCI_VENDOR_INTEL,0x3580, PCI_VENDOR_ATI,0x4e50, 0x1025,0x0061, 1 }, - /* Intel 82852/82855 host bridge / Mobility 9600 M10 RV350 Needs AGPMode 1 (lp #203007) */ - { PCI_VENDOR_INTEL,0x3580, PCI_VENDOR_ATI,0x4e50, 0x1025,0x0064, 1 }, - /* Intel 82852/82855 host bridge / Mobility 9600 M10 RV350 Needs AGPMode 1 (lp #141551) */ - { PCI_VENDOR_INTEL,0x3580, PCI_VENDOR_ATI,0x4e50, PCI_VENDOR_ASUS,0x1942, 1 }, - /* Intel 82852/82855 host bridge / Mobility 9600/9700 Needs AGPMode 1 (deb #510208) */ - { PCI_VENDOR_INTEL,0x3580, PCI_VENDOR_ATI,0x4e50, 0x10cf,0x127f, 1 }, - /* Intel 82443BX/ZX/DX Host bridge / RV280 [Radeon 9200] Needs AGPMode 1 (lp #370205) */ - { PCI_VENDOR_INTEL,0x7190, PCI_VENDOR_ATI,0x5961, 0x174b,0x7c13, 1 }, - - /* Ali Corp M1671 Super P4 Northbridge / Mobility M6 LY Needs AGPMode 1 (lp #146303)*/ - { 0x10b9,0x1671, PCI_VENDOR_ATI,0x4c59, 0x103c,0x0027, 1 }, - - /* SiS Host Bridge 655 / R420 [Radeon X800] Needs AGPMode 4 (lp #371296) */ - { 0x1039,0x0655, PCI_VENDOR_ATI,0x4a4b, PCI_VENDOR_ATI,0x4422, 4 }, - /* SiS Host Bridge / RV280 Needs AGPMode 4 */ - { 0x1039,0x0741, PCI_VENDOR_ATI,0x5964, 0x148c,0x2073, 4 }, - - /* ASRock K7VT4A+ AGP 8x / ATI Radeon 9250 AGP Needs AGPMode 4 (lp #133192) */ - { 0x1849,0x3189, PCI_VENDOR_ATI,0x5960, 0x1787,0x5960, 4 }, - - /* VIA K8M800 Host Bridge / RV280 [Radeon 9200 PRO] Needs AGPMode 4 (fdo #12544) */ - { PCI_VENDOR_VIA,0x0204, PCI_VENDOR_ATI,0x5960, 0x17af,0x2020, 4 }, - /* VIA KT880 Host Bridge / RV350 [Radeon 9550] Needs AGPMode 4 (fdo #19981) */ - { PCI_VENDOR_VIA,0x0269, PCI_VENDOR_ATI,0x4153, PCI_VENDOR_ASUS,0x003c, 4 }, - /* VIA VT8363 Host Bridge / R200 QL [Radeon 8500] Needs AGPMode 2 (lp #141551) */ - { PCI_VENDOR_VIA,0x0305, PCI_VENDOR_ATI,0x514c, PCI_VENDOR_ATI,0x013a, 2 }, - /* VIA VT82C693A Host Bridge / RV280 [Radeon 9200 PRO] Needs AGPMode 2 (deb #515512) */ - { PCI_VENDOR_VIA,0x0691, PCI_VENDOR_ATI,0x5960, PCI_VENDOR_ASUS,0x004c, 2 }, - /* VIA VT82C693A Host Bridge / RV280 [Radeon 9200 PRO] Needs AGPMode 2 */ - { PCI_VENDOR_VIA,0x0691, PCI_VENDOR_ATI,0x5960, PCI_VENDOR_ASUS,0x0054, 2 }, - /* VIA VT8377 Host Bridge / R200 QM [Radeon 9100] Needs AGPMode 4 (deb #461144) */ - { PCI_VENDOR_VIA,0x3189, PCI_VENDOR_ATI,0x514d, 0x174b,0x7149, 4 }, - /* VIA VT8377 Host Bridge / RV280 [Radeon 9200 PRO] Needs AGPMode 4 (lp #312693) */ - { PCI_VENDOR_VIA,0x3189, PCI_VENDOR_ATI,0x5960, 0x1462,0x0380, 4 }, - /* VIA VT8377 Host Bridge / RV280 Needs AGPMode 4 (ati ML) */ - { PCI_VENDOR_VIA,0x3189, PCI_VENDOR_ATI,0x5964, 0x148c,0x2073, 4 }, - /* VIA VT8377 Host Bridge / RV280 Needs AGPMode 4 (fdo #12544) */ - { PCI_VENDOR_VIA,0x3189, PCI_VENDOR_ATI,0x5964, PCI_VENDOR_ASUS,0xc008, 4 }, - /* VIA VT8377 Host Bridge / RV280 Needs AGPMode 4 (deb #545040) */ - { PCI_VENDOR_VIA,0x3189, PCI_VENDOR_ATI,0x5960, PCI_VENDOR_ASUS,0x004c, 4 }, - - /* ATI Host Bridge / RV280 [M9+] Needs AGPMode 1 (phoronix forum) */ - { PCI_VENDOR_ATI,0xcbb2, PCI_VENDOR_ATI,0x5c61, PCI_VENDOR_SONY,0x8175, 1 }, - - /* HP Host Bridge / R300 [FireGL X1] Needs AGPMode 2 (fdo #7770) */ - { PCI_VENDOR_HP,0x122e, PCI_VENDOR_ATI,0x4e47, PCI_VENDOR_ATI,0x0152, 2 }, - - /* nVidia Host Bridge / R420 [X800 Pro] Needs AGPMode 4 (fdo #22726) */ - { 0x10de,0x00e1, PCI_VENDOR_ATI,0x4a49, PCI_VENDOR_ATI,0x0002, 4 }, - - { 0, 0, 0, 0, 0, 0, 0 }, -}; - -/* Set AGP transfer mode according to requests and constraints */ -static Bool RADEONSetAgpMode(RADEONInfoPtr info, ScreenPtr pScreen) -{ - unsigned char *RADEONMMIO = info->MMIO; - unsigned long mode = drmAgpGetMode(info->dri->drmFD); /* Default mode */ - unsigned int vendor = drmAgpVendorId(info->dri->drmFD); - unsigned int device = drmAgpDeviceId(info->dri->drmFD); - - if (info->ChipFamily < CHIP_FAMILY_R600) { - /* ignore agp 3.0 mode bit from the chip as it's buggy on some cards with - pcie-agp rialto bridge chip - use the one from bridge which must match */ - uint32_t agp_status = (INREG(RADEON_AGP_STATUS) | RADEON_AGPv3_MODE) & mode; - Bool is_v3 = (agp_status & RADEON_AGPv3_MODE); - unsigned int defaultMode; - MessageType from; - - if (is_v3) { - defaultMode = (agp_status & RADEON_AGPv3_8X_MODE) ? 8 : 4; - } else { - if (agp_status & RADEON_AGP_4X_MODE) defaultMode = 4; - else if (agp_status & RADEON_AGP_2X_MODE) defaultMode = 2; - else defaultMode = 1; - } - - /* Apply AGPMode Quirks */ - radeon_agpmode_quirk_ptr p = radeon_agpmode_quirk_list; - while (p && p->chipDevice != 0) { - if (vendor == p->hostbridgeVendor && - device == p->hostbridgeDevice && - PCI_DEV_VENDOR_ID(info->PciInfo) == p->chipVendor && - PCI_DEV_DEVICE_ID(info->PciInfo) == p->chipDevice && - PCI_SUB_VENDOR_ID(info->PciInfo) == p->subsysVendor && - PCI_SUB_DEVICE_ID(info->PciInfo) == p->subsysDevice) - { - defaultMode = p->defaultMode; - } - ++p; - } - - from = X_DEFAULT; - - if (xf86GetOptValInteger(info->Options, OPTION_AGP_MODE, &info->dri->agpMode)) { - if ((info->dri->agpMode < (is_v3 ? 4 : 1)) || - (info->dri->agpMode > (is_v3 ? 8 : 4)) || - (info->dri->agpMode & (info->dri->agpMode - 1))) { - xf86DrvMsg(pScreen->myNum, X_ERROR, - "Illegal AGP Mode: %d (valid values: %s), leaving at " - "%dx\n", info->dri->agpMode, is_v3 ? "4, 8" : "1, 2, 4", - defaultMode); - info->dri->agpMode = defaultMode; - } else - from = X_CONFIG; - } else - info->dri->agpMode = defaultMode; - - xf86DrvMsg(pScreen->myNum, from, "Using AGP %dx\n", info->dri->agpMode); - - mode &= ~RADEON_AGP_MODE_MASK; - if (is_v3) { - /* only set one mode bit for AGPv3 */ - switch (info->dri->agpMode) { - case 8: mode |= RADEON_AGPv3_8X_MODE; break; - case 4: default: mode |= RADEON_AGPv3_4X_MODE; - } - /*TODO: need to take care of other bits valid for v3 mode - * currently these bits are not used in all tested cards. - */ - } else { - switch (info->dri->agpMode) { - case 4: mode |= RADEON_AGP_4X_MODE; - case 2: mode |= RADEON_AGP_2X_MODE; - case 1: default: mode |= RADEON_AGP_1X_MODE; - } - } - - /* AGP Fast Writes. - * TODO: take into account that certain agp modes don't support fast - * writes at all */ - mode &= ~RADEON_AGP_FW_MODE; /* Disable per default */ - if (xf86ReturnOptValBool(info->Options, OPTION_AGP_FW, FALSE)) { - xf86DrvMsg(pScreen->myNum, X_WARNING, - "WARNING: Using the AGPFastWrite option is not recommended.\n"); - xf86Msg(X_NONE, "\tThis option does not provide much of a noticable speed" - " boost, while it\n\twill probably hard lock your machine." - " All bets are off!\n"); - - /* Black list some host/AGP bridges. */ - if ((vendor == PCI_VENDOR_AMD) && (device == PCI_CHIP_AMD761)) - xf86DrvMsg(pScreen->myNum, X_PROBED, "Ignoring AGPFastWrite option " - "for the AMD 761 northbridge.\n"); - else { - xf86DrvMsg(pScreen->myNum, X_CONFIG, "Enabling AGP Fast Writes.\n"); - mode |= RADEON_AGP_FW_MODE; - } - } /* Don't mention this otherwise, so that people don't get funny ideas */ - } else - info->dri->agpMode = 8; /* doesn't matter at this point */ - - xf86DrvMsg(pScreen->myNum, X_INFO, - "[agp] Mode 0x%08lx [AGP 0x%04x/0x%04x; Card 0x%04x/0x%04x 0x%04x/0x%04x]\n", - mode, vendor, device, - PCI_DEV_VENDOR_ID(info->PciInfo), - PCI_DEV_DEVICE_ID(info->PciInfo), - PCI_SUB_VENDOR_ID(info->PciInfo), - PCI_SUB_DEVICE_ID(info->PciInfo)); - - if (drmAgpEnable(info->dri->drmFD, mode) < 0) { - xf86DrvMsg(pScreen->myNum, X_ERROR, "[agp] AGP not enabled\n"); - drmAgpRelease(info->dri->drmFD); - return FALSE; - } - - /* Workaround for some hardware bugs */ - if (info->ChipFamily < CHIP_FAMILY_R200) - OUTREG(RADEON_AGP_CNTL, INREG(RADEON_AGP_CNTL) | 0x000e0000); - - /* Modify the mode if the default mode - * is not appropriate for this - * particular combination of graphics - * card and AGP chipset. - */ - - return TRUE; -} - -/* Initialize Radeon's AGP registers */ -static void RADEONSetAgpBase(RADEONInfoPtr info, ScreenPtr pScreen) -{ - ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); - unsigned char *RADEONMMIO = info->MMIO; - - if (info->ChipFamily >= CHIP_FAMILY_R600) - return; - - /* drm already does this, so we can probably remove this. - * agp_base_2 ? - */ - if (info->ChipFamily == CHIP_FAMILY_RV515) - OUTMC(pScrn, RV515_MC_AGP_BASE, drmAgpBase(info->dri->drmFD)); - else if ((info->ChipFamily >= CHIP_FAMILY_R520) && - (info->ChipFamily <= CHIP_FAMILY_RV570)) - OUTMC(pScrn, R520_MC_AGP_BASE, drmAgpBase(info->dri->drmFD)); - else if ((info->ChipFamily == CHIP_FAMILY_RS690) || - (info->ChipFamily == CHIP_FAMILY_RS740)) - OUTMC(pScrn, RS690_MC_AGP_BASE, drmAgpBase(info->dri->drmFD)); - else if (info->ChipFamily < CHIP_FAMILY_RV515) - OUTREG(RADEON_AGP_BASE, drmAgpBase(info->dri->drmFD)); -} - -/* Initialize the AGP state. Request memory for use in AGP space, and - * initialize the Radeon registers to point to that memory. - */ -static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen) -{ - int ret; - - if (drmAgpAcquire(info->dri->drmFD) < 0) { - xf86DrvMsg(pScreen->myNum, X_WARNING, "[agp] AGP not available\n"); - return FALSE; - } - - if (!RADEONSetAgpMode(info, pScreen)) - return FALSE; - - RADEONDRIInitGARTValues(info); - - if ((ret = drmAgpAlloc(info->dri->drmFD, info->dri->gartSize*1024*1024, 0, NULL, - &info->dri->agpMemHandle)) < 0) { - xf86DrvMsg(pScreen->myNum, X_ERROR, "[agp] Out of memory (%d)\n", ret); - drmAgpRelease(info->dri->drmFD); - return FALSE; - } - xf86DrvMsg(pScreen->myNum, X_INFO, - "[agp] %d kB allocated with handle 0x%08x\n", - info->dri->gartSize*1024, - (unsigned int)info->dri->agpMemHandle); - - if (drmAgpBind(info->dri->drmFD, - info->dri->agpMemHandle, info->dri->gartOffset) < 0) { - xf86DrvMsg(pScreen->myNum, X_ERROR, "[agp] Could not bind\n"); - drmAgpFree(info->dri->drmFD, info->dri->agpMemHandle); - drmAgpRelease(info->dri->drmFD); - return FALSE; - } - - if (drmAddMap(info->dri->drmFD, info->dri->ringStart, info->dri->ringMapSize, - DRM_AGP, DRM_READ_ONLY, &info->dri->ringHandle) < 0) { - xf86DrvMsg(pScreen->myNum, X_ERROR, - "[agp] Could not add ring mapping\n"); - return FALSE; - } - xf86DrvMsg(pScreen->myNum, X_INFO, - "[agp] ring handle = 0x%08x\n", - (unsigned int)info->dri->ringHandle); - - if (drmMap(info->dri->drmFD, info->dri->ringHandle, info->dri->ringMapSize, - &info->dri->ring) < 0) { - xf86DrvMsg(pScreen->myNum, X_ERROR, "[agp] Could not map ring\n"); - return FALSE; - } - xf86DrvMsg(pScreen->myNum, X_INFO, - "[agp] Ring mapped at 0x%08lx\n", - (unsigned long)info->dri->ring); - - if (drmAddMap(info->dri->drmFD, info->dri->ringReadOffset, info->dri->ringReadMapSize, - DRM_AGP, DRM_READ_ONLY, &info->dri->ringReadPtrHandle) < 0) { - xf86DrvMsg(pScreen->myNum, X_ERROR, - "[agp] Could not add ring read ptr mapping\n"); - return FALSE; - } - xf86DrvMsg(pScreen->myNum, X_INFO, - "[agp] ring read ptr handle = 0x%08x\n", - (unsigned int)info->dri->ringReadPtrHandle); - - if (drmMap(info->dri->drmFD, info->dri->ringReadPtrHandle, info->dri->ringReadMapSize, - &info->dri->ringReadPtr) < 0) { - xf86DrvMsg(pScreen->myNum, X_ERROR, - "[agp] Could not map ring read ptr\n"); - return FALSE; - } - xf86DrvMsg(pScreen->myNum, X_INFO, - "[agp] Ring read ptr mapped at 0x%08lx\n", - (unsigned long)info->dri->ringReadPtr); - - if (drmAddMap(info->dri->drmFD, info->dri->bufStart, info->dri->bufMapSize, - DRM_AGP, 0, &info->dri->bufHandle) < 0) { - xf86DrvMsg(pScreen->myNum, X_ERROR, - "[agp] Could not add vertex/indirect buffers mapping\n"); - return FALSE; - } - xf86DrvMsg(pScreen->myNum, X_INFO, - "[agp] vertex/indirect buffers handle = 0x%08x\n", - (unsigned int)info->dri->bufHandle); - - if (drmMap(info->dri->drmFD, info->dri->bufHandle, info->dri->bufMapSize, - &info->dri->buf) < 0) { - xf86DrvMsg(pScreen->myNum, X_ERROR, - "[agp] Could not map vertex/indirect buffers\n"); - return FALSE; - } - xf86DrvMsg(pScreen->myNum, X_INFO, - "[agp] Vertex/indirect buffers mapped at 0x%08lx\n", - (unsigned long)info->dri->buf); - - if (drmAddMap(info->dri->drmFD, info->dri->gartTexStart, info->dri->gartTexMapSize, - DRM_AGP, 0, &info->dri->gartTexHandle) < 0) { - xf86DrvMsg(pScreen->myNum, X_ERROR, - "[agp] Could not add GART texture map mapping\n"); - return FALSE; - } - xf86DrvMsg(pScreen->myNum, X_INFO, - "[agp] GART texture map handle = 0x%08x\n", - (unsigned int)info->dri->gartTexHandle); - - if (drmMap(info->dri->drmFD, info->dri->gartTexHandle, info->dri->gartTexMapSize, - &info->dri->gartTex) < 0) { - xf86DrvMsg(pScreen->myNum, X_ERROR, - "[agp] Could not map GART texture map\n"); - return FALSE; - } - xf86DrvMsg(pScreen->myNum, X_INFO, - "[agp] GART Texture map mapped at 0x%08lx\n", - (unsigned long)info->dri->gartTex); - - RADEONSetAgpBase(info, pScreen); - - return TRUE; -} - -/* Initialize the PCI GART state. Request memory for use in PCI space, - * and initialize the Radeon registers to point to that memory. - */ -static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen) -{ - int ret; - int flags = DRM_READ_ONLY | DRM_LOCKED | DRM_KERNEL; - - ret = drmScatterGatherAlloc(info->dri->drmFD, info->dri->gartSize*1024*1024, - &info->dri->pciMemHandle); - if (ret < 0) { - xf86DrvMsg(pScreen->myNum, X_ERROR, "[pci] Out of memory (%d)\n", ret); - return FALSE; - } - xf86DrvMsg(pScreen->myNum, X_INFO, - "[pci] %d kB allocated with handle 0x%08x\n", - info->dri->gartSize*1024, - (unsigned int)info->dri->pciMemHandle); - - RADEONDRIInitGARTValues(info); - - if (drmAddMap(info->dri->drmFD, info->dri->ringStart, info->dri->ringMapSize, - DRM_SCATTER_GATHER, flags, &info->dri->ringHandle) < 0) { - xf86DrvMsg(pScreen->myNum, X_ERROR, - "[pci] Could not add ring mapping\n"); - return FALSE; - } - xf86DrvMsg(pScreen->myNum, X_INFO, - "[pci] ring handle = 0x%08x\n", - (unsigned int)info->dri->ringHandle); - - if (drmMap(info->dri->drmFD, info->dri->ringHandle, info->dri->ringMapSize, - &info->dri->ring) < 0) { - xf86DrvMsg(pScreen->myNum, X_ERROR, "[pci] Could not map ring\n"); - return FALSE; - } - xf86DrvMsg(pScreen->myNum, X_INFO, - "[pci] Ring mapped at 0x%08lx\n", - (unsigned long)info->dri->ring); - xf86DrvMsg(pScreen->myNum, X_INFO, - "[pci] Ring contents 0x%08lx\n", - *(unsigned long *)(pointer)info->dri->ring); - - if (drmAddMap(info->dri->drmFD, info->dri->ringReadOffset, info->dri->ringReadMapSize, - DRM_SCATTER_GATHER, flags, &info->dri->ringReadPtrHandle) < 0) { - xf86DrvMsg(pScreen->myNum, X_ERROR, - "[pci] Could not add ring read ptr mapping\n"); - return FALSE; - } - xf86DrvMsg(pScreen->myNum, X_INFO, - "[pci] ring read ptr handle = 0x%08x\n", - (unsigned int)info->dri->ringReadPtrHandle); - - if (drmMap(info->dri->drmFD, info->dri->ringReadPtrHandle, info->dri->ringReadMapSize, - &info->dri->ringReadPtr) < 0) { - xf86DrvMsg(pScreen->myNum, X_ERROR, - "[pci] Could not map ring read ptr\n"); - return FALSE; - } - xf86DrvMsg(pScreen->myNum, X_INFO, - "[pci] Ring read ptr mapped at 0x%08lx\n", - (unsigned long)info->dri->ringReadPtr); - xf86DrvMsg(pScreen->myNum, X_INFO, - "[pci] Ring read ptr contents 0x%08lx\n", - *(unsigned long *)(pointer)info->dri->ringReadPtr); - - if (drmAddMap(info->dri->drmFD, info->dri->bufStart, info->dri->bufMapSize, - DRM_SCATTER_GATHER, 0, &info->dri->bufHandle) < 0) { - xf86DrvMsg(pScreen->myNum, X_ERROR, - "[pci] Could not add vertex/indirect buffers mapping\n"); - return FALSE; - } - xf86DrvMsg(pScreen->myNum, X_INFO, - "[pci] vertex/indirect buffers handle = 0x%08x\n", - (unsigned int)info->dri->bufHandle); - - if (drmMap(info->dri->drmFD, info->dri->bufHandle, info->dri->bufMapSize, - &info->dri->buf) < 0) { - xf86DrvMsg(pScreen->myNum, X_ERROR, - "[pci] Could not map vertex/indirect buffers\n"); - return FALSE; - } - xf86DrvMsg(pScreen->myNum, X_INFO, - "[pci] Vertex/indirect buffers mapped at 0x%08lx\n", - (unsigned long)info->dri->buf); - xf86DrvMsg(pScreen->myNum, X_INFO, - "[pci] Vertex/indirect buffers contents 0x%08lx\n", - *(unsigned long *)(pointer)info->dri->buf); - - if (drmAddMap(info->dri->drmFD, info->dri->gartTexStart, info->dri->gartTexMapSize, - DRM_SCATTER_GATHER, 0, &info->dri->gartTexHandle) < 0) { - xf86DrvMsg(pScreen->myNum, X_ERROR, - "[pci] Could not add GART texture map mapping\n"); - return FALSE; - } - xf86DrvMsg(pScreen->myNum, X_INFO, - "[pci] GART texture map handle = 0x%08x\n", - (unsigned int)info->dri->gartTexHandle); - - if (drmMap(info->dri->drmFD, info->dri->gartTexHandle, info->dri->gartTexMapSize, - &info->dri->gartTex) < 0) { - xf86DrvMsg(pScreen->myNum, X_ERROR, - "[pci] Could not map GART texture map\n"); - return FALSE; - } - xf86DrvMsg(pScreen->myNum, X_INFO, - "[pci] GART Texture map mapped at 0x%08lx\n", - (unsigned long)info->dri->gartTex); - - return TRUE; -} - -/* Add a map for the MMIO registers that will be accessed by any - * DRI-based clients. - */ -static Bool RADEONDRIMapInit(RADEONInfoPtr info, ScreenPtr pScreen) -{ - /* Map registers */ - info->dri->registerSize = info->MMIOSize; - if (drmAddMap(info->dri->drmFD, info->MMIOAddr, info->dri->registerSize, - DRM_REGISTERS, DRM_READ_ONLY, &info->dri->registerHandle) < 0) { - return FALSE; - } - xf86DrvMsg(pScreen->myNum, X_INFO, - "[drm] register handle = 0x%08x\n", - (unsigned int)info->dri->registerHandle); - - return TRUE; -} - -/* Initialize the kernel data structures */ -static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen) -{ - ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); - int cpp = info->CurrentLayout.pixel_bytes; - drm_radeon_init_t drmInfo; - - memset(&drmInfo, 0, sizeof(drm_radeon_init_t)); - if ( info->ChipFamily >= CHIP_FAMILY_R600 ) - drmInfo.func = RADEON_INIT_R600_CP; - else if ( info->ChipFamily >= CHIP_FAMILY_R300 ) - drmInfo.func = RADEON_INIT_R300_CP; - else if ( info->ChipFamily >= CHIP_FAMILY_R200 ) - drmInfo.func = RADEON_INIT_R200_CP; - else - drmInfo.func = RADEON_INIT_CP; - - drmInfo.sarea_priv_offset = sizeof(XF86DRISAREARec); - drmInfo.is_pci = (info->cardType!=CARD_AGP); - drmInfo.cp_mode = RADEON_CSQ_PRIBM_INDBM; - drmInfo.gart_size = info->dri->gartSize*1024*1024; - drmInfo.ring_size = info->dri->ringSize*1024*1024; - drmInfo.usec_timeout = info->cp->CPusecTimeout; - - drmInfo.fb_bpp = info->CurrentLayout.pixel_code; - drmInfo.depth_bpp = (info->dri->depthBits - 8) * 2; - - drmInfo.front_offset = info->dri->frontOffset; - drmInfo.front_pitch = info->dri->frontPitch * cpp; - drmInfo.back_offset = info->dri->backOffset; - drmInfo.back_pitch = info->dri->backPitch * cpp; - drmInfo.depth_offset = info->dri->depthOffset; - drmInfo.depth_pitch = info->dri->depthPitch * drmInfo.depth_bpp / 8; - - drmInfo.fb_offset = info->dri->fbHandle; - drmInfo.mmio_offset = info->dri->registerHandle; - drmInfo.ring_offset = info->dri->ringHandle; - drmInfo.ring_rptr_offset = info->dri->ringReadPtrHandle; - drmInfo.buffers_offset = info->dri->bufHandle; - drmInfo.gart_textures_offset= info->dri->gartTexHandle; - - if (drmCommandWrite(info->dri->drmFD, DRM_RADEON_CP_INIT, - &drmInfo, sizeof(drm_radeon_init_t)) < 0) - return FALSE; - - /* DRM_RADEON_CP_INIT does an engine reset, which resets some engine - * registers back to their default values, so we need to restore - * those engine register here. - */ - if (info->ChipFamily < CHIP_FAMILY_R600) - RADEONEngineRestore(pScrn); - - return TRUE; -} - -static void RADEONDRIGartHeapInit(RADEONInfoPtr info, ScreenPtr pScreen) -{ - drm_radeon_mem_init_heap_t drmHeap; - - /* Start up the simple memory manager for GART space */ - drmHeap.region = RADEON_MEM_REGION_GART; - drmHeap.start = 0; - drmHeap.size = info->dri->gartTexMapSize; - - if (drmCommandWrite(info->dri->drmFD, DRM_RADEON_INIT_HEAP, - &drmHeap, sizeof(drmHeap))) { - xf86DrvMsg(pScreen->myNum, X_ERROR, - "[drm] Failed to initialize GART heap manager\n"); - } else { - xf86DrvMsg(pScreen->myNum, X_INFO, - "[drm] Initialized kernel GART heap manager, %d\n", - info->dri->gartTexMapSize); - } -} - -/* Add a map for the vertex buffers that will be accessed by any - * DRI-based clients. - */ -static Bool RADEONDRIBufInit(RADEONInfoPtr info, ScreenPtr pScreen) -{ - /* Initialize vertex buffers */ - info->dri->bufNumBufs = drmAddBufs(info->dri->drmFD, - info->dri->bufMapSize / RADEON_BUFFER_SIZE, - RADEON_BUFFER_SIZE, - (info->cardType!=CARD_AGP) ? DRM_SG_BUFFER : DRM_AGP_BUFFER, - info->dri->bufStart); - - if (info->dri->bufNumBufs <= 0) { - xf86DrvMsg(pScreen->myNum, X_ERROR, - "[drm] Could not create vertex/indirect buffers list\n"); - return FALSE; - } - xf86DrvMsg(pScreen->myNum, X_INFO, - "[drm] Added %d %d byte vertex/indirect buffers\n", - info->dri->bufNumBufs, RADEON_BUFFER_SIZE); - - if (!(info->dri->buffers = drmMapBufs(info->dri->drmFD))) { - xf86DrvMsg(pScreen->myNum, X_ERROR, - "[drm] Failed to map vertex/indirect buffers list\n"); - return FALSE; - } - xf86DrvMsg(pScreen->myNum, X_INFO, - "[drm] Mapped %d vertex/indirect buffers\n", - info->dri->buffers->count); - - return TRUE; -} - -static void RADEONDRIIrqInit(RADEONInfoPtr info, ScreenPtr pScreen) -{ - ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); - - if (!info->dri->irq) { - info->dri->irq = drmGetInterruptFromBusID( - info->dri->drmFD, - PCI_CFG_BUS(info->PciInfo), - PCI_CFG_DEV(info->PciInfo), - PCI_CFG_FUNC(info->PciInfo)); - - if ((drmCtlInstHandler(info->dri->drmFD, info->dri->irq)) != 0) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "[drm] failure adding irq handler, " - "there is a device already using that irq\n" - "[drm] falling back to irq-free operation\n"); - info->dri->irq = 0; - } else { - if (info->ChipFamily < CHIP_FAMILY_R600) { - unsigned char *RADEONMMIO = info->MMIO; - info->ModeReg->gen_int_cntl = INREG( RADEON_GEN_INT_CNTL ); - - /* Let the DRM know it can safely disable the vblank interrupts */ - radeon_crtc_modeset_ioctl(XF86_CRTC_CONFIG_PTR(pScrn)->crtc[0], - FALSE); - radeon_crtc_modeset_ioctl(XF86_CRTC_CONFIG_PTR(pScrn)->crtc[0], - TRUE); - } - } - } - - if (info->dri->irq) - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "[drm] dma control initialized, using IRQ %d\n", - info->dri->irq); -} - - -/* Initialize the CP state, and start the CP (if used by the X server) */ -static void RADEONDRICPInit(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - - /* Turn on bus mastering */ - info->BusCntl &= ~RADEON_BUS_MASTER_DIS; - - /* Make sure the CP is on for the X server */ - RADEONCP_START(pScrn, info); -#ifdef USE_XAA - if (!info->useEXA) - info->accel_state->dst_pitch_offset = info->dri->frontPitchOffset; -#endif -} - - -/* Get the DRM version and do some basic useability checks of DRI */ -Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - int major, minor, patch, fd; - int req_major, req_minor, req_patch; - char *busId; - - /* Check that the GLX, DRI, and DRM modules have been loaded by testing - * for known symbols in each module. - */ - if (!xf86LoaderCheckSymbol("GlxSetVisualConfigs")) return FALSE; - if (!xf86LoaderCheckSymbol("drmAvailable")) return FALSE; - if (!xf86LoaderCheckSymbol("DRIQueryVersion")) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "[dri] RADEONDRIGetVersion failed (libdri too old)\n" - "[dri] Disabling DRI.\n"); - return FALSE; - } - - /* Check the DRI version */ - DRIQueryVersion(&major, &minor, &patch); - if (major < DRIINFO_MAJOR_VERSION) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "[dri] RADEONDRIGetVersion failed because of a version mismatch.\n" - "[dri] This driver was built with %d.%d.x, which is too new;\n" - "[dri] libdri reports a version of %d.%d.%d." - "[dri] A server upgrade may be needed.\n" - "[dri] Disabling DRI.\n", - DRIINFO_MAJOR_VERSION, 0, - major, minor, patch); - return FALSE; - } else if (major > DRIINFO_MAJOR_VERSION) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "[dri] RADEONDRIGetVersion failed because of a version mismatch.\n" - "[dri] This driver was built with %d.%d.x, which is too old;\n" - "[dri] libdri reports a version of %d.%d.%d." - "[dri] This driver needs to be upgraded/rebuilt.\n" - "[dri] Disabling DRI.\n", - DRIINFO_MAJOR_VERSION, 0, - major, minor, patch); - return FALSE; - } - - /* Check the lib version */ - if (xf86LoaderCheckSymbol("drmGetLibVersion")) - info->dri->pLibDRMVersion = drmGetLibVersion(info->dri->drmFD); - if (info->dri->pLibDRMVersion == NULL) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "[dri] RADEONDRIGetVersion failed because libdrm is really " - "way to old to even get a version number out of it.\n" - "[dri] Disabling DRI.\n"); - return FALSE; - } - if (info->dri->pLibDRMVersion->version_major != 1 || - info->dri->pLibDRMVersion->version_minor < 2) { - /* incompatible drm library version */ - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "[dri] RADEONDRIGetVersion failed because of a " - "version mismatch.\n" - "[dri] libdrm module version is %d.%d.%d but " - "version 1.2.x is needed.\n" - "[dri] Disabling DRI.\n", - info->dri->pLibDRMVersion->version_major, - info->dri->pLibDRMVersion->version_minor, - info->dri->pLibDRMVersion->version_patchlevel); - drmFreeVersion(info->dri->pLibDRMVersion); - info->dri->pLibDRMVersion = NULL; - return FALSE; - } - - /* Create a bus Id */ - if (xf86LoaderCheckSymbol("DRICreatePCIBusID")) { - busId = DRICreatePCIBusID(info->PciInfo); - } else { - busId = malloc(64); - sprintf(busId, - "PCI:%d:%d:%d", - PCI_DEV_BUS(info->PciInfo), - PCI_DEV_DEV(info->PciInfo), - PCI_DEV_FUNC(info->PciInfo)); - } - - /* Low level DRM open */ - fd = drmOpen(RADEON_DRIVER_NAME, busId); - free(busId); - if (fd < 0) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "[dri] RADEONDRIGetVersion failed to open the DRM\n" - "[dri] Disabling DRI.\n"); - return FALSE; - } - - /* Get DRM version & close DRM */ - info->dri->pKernelDRMVersion = drmGetVersion(fd); - drmClose(fd); - if (info->dri->pKernelDRMVersion == NULL) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "[dri] RADEONDRIGetVersion failed to get the DRM version\n" - "[dri] Disabling DRI.\n"); - return FALSE; - } - - /* Now check if we qualify */ - req_major = 1; - if (info->ChipFamily >= CHIP_FAMILY_R300) { - req_minor = 17; - req_patch = 0; - } else if (info->IsIGP) { - req_minor = 10; - req_patch = 0; - } else { /* Many problems have been reported with 1.7 in the 2.4 kernel */ - req_minor = 8; - req_patch = 0; - } - - /* We don't, bummer ! */ - if (info->dri->pKernelDRMVersion->version_major != req_major) { - /* Looks like we're trying to start in UMS mode on a KMS kernel. - * This can happen if the radeon kernel module wasn't loaded before - * X starts. - */ - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "[dri] RADEONDRIGetVersion failed because of a version mismatch.\n" - "[dri] This chipset requires a kernel module version of %d.%d.%d,\n" - "[dri] but the kernel reports a version of %d.%d.%d." - "[dri] Make sure your module is loaded prior to starting X, and\n" - "[dri] that this driver was built with support for KMS.\n" - "[dri] Aborting.\n", - req_major, req_minor, req_patch, - info->dri->pKernelDRMVersion->version_major, - info->dri->pKernelDRMVersion->version_minor, - info->dri->pKernelDRMVersion->version_patchlevel); - drmFreeVersion(info->dri->pKernelDRMVersion); - info->dri->pKernelDRMVersion = NULL; - return -1; - } else if (info->dri->pKernelDRMVersion->version_minor < req_minor || - (info->dri->pKernelDRMVersion->version_minor == req_minor && - info->dri->pKernelDRMVersion->version_patchlevel < req_patch)) { - /* Incompatible drm version */ - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "[dri] RADEONDRIGetVersion failed because of a version mismatch.\n" - "[dri] This chipset requires a kernel module version of %d.%d.%d,\n" - "[dri] but the kernel reports a version of %d.%d.%d." - "[dri] Try upgrading your kernel.\n" - "[dri] Disabling DRI.\n", - req_major, req_minor, req_patch, - info->dri->pKernelDRMVersion->version_major, - info->dri->pKernelDRMVersion->version_minor, - info->dri->pKernelDRMVersion->version_patchlevel); - drmFreeVersion(info->dri->pKernelDRMVersion); - info->dri->pKernelDRMVersion = NULL; - return FALSE; - } - - return TRUE; -} - -Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); - int value = 0; - - if (!info->want_vblank_interrupts) - on = FALSE; - - if (info->directRenderingEnabled && info->dri->pKernelDRMVersion->version_minor >= 28) { - if (on) { - if (xf86_config->num_crtc > 1 && xf86_config->crtc[1]->enabled) - value = DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2; - else - value = DRM_RADEON_VBLANK_CRTC1; - } - - if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_VBLANK_CRTC, value)) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "RADEON Vblank Crtc Setup Failed %d\n", value); - return FALSE; - } - } - return TRUE; -} - - -/* Initialize the screen-specific data structures for the DRI and the - * Radeon. This is the main entry point to the device-specific - * initialization code. It calls device-independent DRI functions to - * create the DRI data structures and initialize the DRI state. - */ -Bool RADEONDRIScreenInit(ScreenPtr pScreen) -{ - ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); - RADEONInfoPtr info = RADEONPTR(pScrn); - DRIInfoPtr pDRIInfo; - RADEONDRIPtr pRADEONDRI; - - info->dri->DRICloseScreen = NULL; - - switch (info->CurrentLayout.pixel_code) { - case 8: - case 15: - case 24: - /* These modes are not supported (yet). */ - xf86DrvMsg(pScreen->myNum, X_ERROR, - "[dri] RADEONInitVisualConfigs failed " - "(depth %d not supported). " - "Disabling DRI.\n", info->CurrentLayout.pixel_code); - return FALSE; - - /* Only 16 and 32 color depths are supports currently. */ - case 16: - case 32: - break; - } - - radeon_drm_page_size = getpagesize(); - - /* Create the DRI data structure, and fill it in before calling the - * DRIScreenInit(). - */ - if (!(pDRIInfo = DRICreateInfoRec())) return FALSE; - - info->dri->pDRIInfo = pDRIInfo; - pDRIInfo->drmDriverName = RADEON_DRIVER_NAME; - - if ( (info->ChipFamily >= CHIP_FAMILY_R600) ) - pDRIInfo->clientDriverName = R600_DRIVER_NAME; - else if ( (info->ChipFamily >= CHIP_FAMILY_R300) ) - pDRIInfo->clientDriverName = R300_DRIVER_NAME; - else if ( info->ChipFamily >= CHIP_FAMILY_R200 ) - pDRIInfo->clientDriverName = R200_DRIVER_NAME; - else - pDRIInfo->clientDriverName = RADEON_DRIVER_NAME; - - if (xf86LoaderCheckSymbol("DRICreatePCIBusID")) { - pDRIInfo->busIdString = DRICreatePCIBusID(info->PciInfo); - } else { - pDRIInfo->busIdString = malloc(64); - sprintf(pDRIInfo->busIdString, - "PCI:%d:%d:%d", - PCI_DEV_BUS(info->PciInfo), - PCI_DEV_DEV(info->PciInfo), - PCI_DEV_FUNC(info->PciInfo)); - } - pDRIInfo->ddxDriverMajorVersion = info->allowColorTiling ? 5 : 4; - pDRIInfo->ddxDriverMinorVersion = 3; - pDRIInfo->ddxDriverPatchVersion = 0; - pDRIInfo->frameBufferPhysicalAddress = (void *)(uintptr_t)info->LinearAddr + info->dri->frontOffset; - pDRIInfo->frameBufferSize = info->FbMapSize - info->FbSecureSize; - pDRIInfo->frameBufferStride = (pScrn->displayWidth * - info->CurrentLayout.pixel_bytes); - pDRIInfo->ddxDrawableTableEntry = RADEON_MAX_DRAWABLES; - pDRIInfo->maxDrawableTableEntry = (SAREA_MAX_DRAWABLES - < RADEON_MAX_DRAWABLES - ? SAREA_MAX_DRAWABLES - : RADEON_MAX_DRAWABLES); - /* kill DRIAdjustFrame. We adjust sarea frame info ourselves to work - correctly with pageflip + mergedfb/color tiling */ - pDRIInfo->wrap.AdjustFrame = NULL; - -#ifdef NOT_DONE - /* FIXME: Need to extend DRI protocol to pass this size back to - * client for SAREA mapping that includes a device private record - */ - pDRIInfo->SAREASize = ((sizeof(XF86DRISAREARec) + 0xfff) - & 0x1000); /* round to page */ - /* + shared memory device private rec */ -#else - /* For now the mapping works by using a fixed size defined - * in the SAREA header - */ - if (sizeof(XF86DRISAREARec)+sizeof(drm_radeon_sarea_t) > SAREA_MAX) { - ErrorF("Data does not fit in SAREA\n"); - return FALSE; - } - pDRIInfo->SAREASize = SAREA_MAX; -#endif - - if (!(pRADEONDRI = (RADEONDRIPtr)calloc(sizeof(RADEONDRIRec),1))) { - DRIDestroyInfoRec(info->dri->pDRIInfo); - info->dri->pDRIInfo = NULL; - return FALSE; - } - pDRIInfo->devPrivate = pRADEONDRI; - pDRIInfo->devPrivateSize = sizeof(RADEONDRIRec); - pDRIInfo->contextSize = sizeof(RADEONDRIContextRec); - - pDRIInfo->CreateContext = RADEONCreateContext; - pDRIInfo->DestroyContext = RADEONDestroyContext; - pDRIInfo->SwapContext = RADEONDRISwapContext; - pDRIInfo->InitBuffers = RADEONDRIInitBuffers; - pDRIInfo->MoveBuffers = RADEONDRIMoveBuffers; - pDRIInfo->bufferRequests = DRI_ALL_WINDOWS; - pDRIInfo->TransitionTo2d = RADEONDRITransitionTo2d; - pDRIInfo->TransitionTo3d = RADEONDRITransitionTo3d; - pDRIInfo->TransitionSingleToMulti3D = RADEONDRITransitionSingleToMulti3d; - pDRIInfo->TransitionMultiToSingle3D = RADEONDRITransitionMultiToSingle3d; -#if defined(DAMAGE) && (DRIINFO_MAJOR_VERSION > 5 || \ - (DRIINFO_MAJOR_VERSION == 5 && \ - DRIINFO_MINOR_VERSION >= 1)) - pDRIInfo->ClipNotify = RADEONDRIClipNotify; -#endif - - pDRIInfo->createDummyCtx = TRUE; - pDRIInfo->createDummyCtxPriv = FALSE; - -#ifdef USE_EXA - if (info->useEXA) { -#if DRIINFO_MAJOR_VERSION == 5 && DRIINFO_MINOR_VERSION >= 3 - int major, minor, patch; - - DRIQueryVersion(&major, &minor, &patch); - - if (minor >= 3) -#endif -#if DRIINFO_MAJOR_VERSION > 5 || \ - (DRIINFO_MAJOR_VERSION == 5 && DRIINFO_MINOR_VERSION >= 3) - pDRIInfo->texOffsetStart = RADEONTexOffsetStart; -#endif - } -#endif - - if (!DRIScreenInit(pScreen, pDRIInfo, &info->dri->drmFD)) { - xf86DrvMsg(pScreen->myNum, X_ERROR, - "[dri] DRIScreenInit failed. Disabling DRI.\n"); - free(pDRIInfo->devPrivate); - pDRIInfo->devPrivate = NULL; - DRIDestroyInfoRec(pDRIInfo); - pDRIInfo = NULL; - return FALSE; - } - /* Initialize AGP */ - if (info->cardType==CARD_AGP && !RADEONDRIAgpInit(info, pScreen)) { - xf86DrvMsg(pScreen->myNum, X_ERROR, - "[agp] AGP failed to initialize. Disabling the DRI.\n" ); - xf86DrvMsg(pScreen->myNum, X_INFO, - "[agp] You may want to make sure the agpgart kernel " - "module\nis loaded before the radeon kernel module.\n"); - RADEONDRICloseScreen(pScreen); - return FALSE; - } - - /* Initialize PCI */ - if ((info->cardType!=CARD_AGP) && !RADEONDRIPciInit(info, pScreen)) { - xf86DrvMsg(pScreen->myNum, X_ERROR, - "[pci] PCI failed to initialize. Disabling the DRI.\n" ); - RADEONDRICloseScreen(pScreen); - return FALSE; - } - - /* DRIScreenInit doesn't add all the - * common mappings. Add additional - * mappings here. - */ - if (!RADEONDRIMapInit(info, pScreen)) { - RADEONDRICloseScreen(pScreen); - return FALSE; - } - - /* DRIScreenInit adds the frame buffer - map, but we need it as well */ - { - void *scratch_ptr; - int scratch_int; - - DRIGetDeviceInfo(pScreen, &info->dri->fbHandle, - &scratch_int, &scratch_int, - &scratch_int, &scratch_int, - &scratch_ptr); - } - - /* FIXME: When are these mappings unmapped? */ - - if (!RADEONInitVisualConfigs(pScreen)) { - RADEONDRICloseScreen(pScreen); - return FALSE; - } - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "[dri] Visual configs initialized\n"); - - return TRUE; -} - -static Bool RADEONDRIDoCloseScreen(CLOSE_SCREEN_ARGS_DECL) -{ - ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); - RADEONInfoPtr info = RADEONPTR(pScrn); - - RADEONDRICloseScreen(pScreen); - - pScreen->CloseScreen = info->dri->DRICloseScreen; - return (*pScreen->CloseScreen)(CLOSE_SCREEN_ARGS); -} - -/* Finish initializing the device-dependent DRI state, and call - * DRIFinishScreenInit() to complete the device-independent DRI - * initialization. - */ -Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen) -{ - ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); - RADEONInfoPtr info = RADEONPTR(pScrn); - drm_radeon_sarea_t *pSAREAPriv; - RADEONDRIPtr pRADEONDRI; - - info->dri->pDRIInfo->driverSwapMethod = DRI_HIDE_X_CONTEXT; - /* info->dri->pDRIInfo->driverSwapMethod = DRI_SERVER_SWAP; */ - - /* NOTE: DRIFinishScreenInit must be called before *DRIKernelInit - * because *DRIKernelInit requires that the hardware lock is held by - * the X server, and the first time the hardware lock is grabbed is - * in DRIFinishScreenInit. - */ - if (!DRIFinishScreenInit(pScreen)) { - RADEONDRICloseScreen(pScreen); - return FALSE; - } - - /* Initialize the kernel data structures */ - if (!RADEONDRIKernelInit(info, pScreen)) { - RADEONDRICloseScreen(pScreen); - return FALSE; - } - - /* Initialize the vertex buffers list */ - if (!RADEONDRIBufInit(info, pScreen)) { - RADEONDRICloseScreen(pScreen); - return FALSE; - } - - /* Initialize IRQ */ - RADEONDRIIrqInit(info, pScreen); - - /* Initialize kernel GART memory manager */ - RADEONDRIGartHeapInit(info, pScreen); - - /* Initialize and start the CP if required */ - RADEONDRICPInit(pScrn); - - /* Initialize the SAREA private data structure */ - pSAREAPriv = (drm_radeon_sarea_t*)DRIGetSAREAPrivate(pScreen); - memset(pSAREAPriv, 0, sizeof(*pSAREAPriv)); - - pRADEONDRI = (RADEONDRIPtr)info->dri->pDRIInfo->devPrivate; - - pRADEONDRI->deviceID = info->Chipset; - pRADEONDRI->width = pScrn->virtualX; - pRADEONDRI->height = pScrn->virtualY; - pRADEONDRI->depth = pScrn->depth; - pRADEONDRI->bpp = pScrn->bitsPerPixel; - - pRADEONDRI->IsPCI = (info->cardType!=CARD_AGP); - pRADEONDRI->AGPMode = info->dri->agpMode; - - pRADEONDRI->frontOffset = info->dri->frontOffset; - pRADEONDRI->frontPitch = info->dri->frontPitch; - pRADEONDRI->backOffset = info->dri->backOffset; - pRADEONDRI->backPitch = info->dri->backPitch; - pRADEONDRI->depthOffset = info->dri->depthOffset; - pRADEONDRI->depthPitch = info->dri->depthPitch; - pRADEONDRI->textureOffset = info->dri->textureOffset; - pRADEONDRI->textureSize = info->dri->textureSize; - pRADEONDRI->log2TexGran = info->dri->log2TexGran; - - pRADEONDRI->registerHandle = info->dri->registerHandle; - pRADEONDRI->registerSize = info->dri->registerSize; - - pRADEONDRI->statusHandle = info->dri->ringReadPtrHandle; - pRADEONDRI->statusSize = info->dri->ringReadMapSize; - - pRADEONDRI->gartTexHandle = info->dri->gartTexHandle; - pRADEONDRI->gartTexMapSize = info->dri->gartTexMapSize; - pRADEONDRI->log2GARTTexGran = info->dri->log2GARTTexGran; - pRADEONDRI->gartTexOffset = info->dri->gartTexStart; - - pRADEONDRI->sarea_priv_offset = sizeof(XF86DRISAREARec); - - info->directRenderingInited = TRUE; - - /* Wrap CloseScreen */ - info->dri->DRICloseScreen = pScreen->CloseScreen; - pScreen->CloseScreen = RADEONDRIDoCloseScreen; - - /* disable vblank at startup */ - RADEONDRISetVBlankInterrupt (pScrn, FALSE); - - return TRUE; -} - -/** - * This function will attempt to get the Radeon hardware back into shape - * after a resume from disc. - * - * Charl P. Botha <http://cpbotha.net> - */ -void RADEONDRIResume(ScreenPtr pScreen) -{ - int _ret; - ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); - RADEONInfoPtr info = RADEONPTR(pScrn); - - if (info->dri->pKernelDRMVersion->version_minor >= 9) { - xf86DrvMsg(pScreen->myNum, X_INFO, - "[RESUME] Attempting to re-init Radeon hardware.\n"); - } else { - xf86DrvMsg(pScreen->myNum, X_WARNING, - "[RESUME] Cannot re-init Radeon hardware, DRM too old\n" - "(need 1.9.0 or newer)\n"); - return; - } - - if (info->cardType==CARD_AGP) { - if (!RADEONSetAgpMode(info, pScreen)) - return; - - RADEONSetAgpBase(info, pScreen); - } - - _ret = drmCommandNone(info->dri->drmFD, DRM_RADEON_CP_RESUME); - if (_ret) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "%s: CP resume %d\n", __FUNCTION__, _ret); - /* FIXME: return? */ - } - - if (info->ChipFamily < CHIP_FAMILY_R600) - RADEONEngineRestore(pScrn); - - RADEONDRICPInit(pScrn); -} - -void RADEONDRIStop(ScreenPtr pScreen) -{ - ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); - RADEONInfoPtr info = RADEONPTR(pScrn); - RING_LOCALS; - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "RADEONDRIStop\n"); - - /* Stop the CP */ - if (info->directRenderingInited) { - /* If we've generated any CP commands, we must flush them to the - * kernel module now. - */ - RADEONCP_RELEASE(pScrn, info); - RADEONCP_STOP(pScrn, info); - } - info->directRenderingInited = FALSE; -} - -/* The screen is being closed, so clean up any state and free any - * resources used by the DRI. - */ -void RADEONDRICloseScreen(ScreenPtr pScreen) -{ - ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); - RADEONInfoPtr info = RADEONPTR(pScrn); - drm_radeon_init_t drmInfo; - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "RADEONDRICloseScreen\n"); - -#ifdef DAMAGE - REGION_UNINIT(pScreen, &info->dri->driRegion); -#endif - - if (info->dri->irq) { - RADEONDRISetVBlankInterrupt (pScrn, FALSE); - drmCtlUninstHandler(info->dri->drmFD); - info->dri->irq = 0; - info->ModeReg->gen_int_cntl = 0; - } - - /* De-allocate vertex buffers */ - if (info->dri->buffers) { - drmUnmapBufs(info->dri->buffers); - info->dri->buffers = NULL; - } - - /* De-allocate all kernel resources */ - memset(&drmInfo, 0, sizeof(drm_radeon_init_t)); - drmInfo.func = RADEON_CLEANUP_CP; - drmCommandWrite(info->dri->drmFD, DRM_RADEON_CP_INIT, - &drmInfo, sizeof(drm_radeon_init_t)); - - /* De-allocate all GART resources */ - if (info->dri->gartTex) { - drmUnmap(info->dri->gartTex, info->dri->gartTexMapSize); - info->dri->gartTex = NULL; - } - if (info->dri->buf) { - drmUnmap(info->dri->buf, info->dri->bufMapSize); - info->dri->buf = NULL; - } - if (info->dri->ringReadPtr) { - drmUnmap(info->dri->ringReadPtr, info->dri->ringReadMapSize); - info->dri->ringReadPtr = NULL; - } - if (info->dri->ring) { - drmUnmap(info->dri->ring, info->dri->ringMapSize); - info->dri->ring = NULL; - } - if (info->dri->agpMemHandle != DRM_AGP_NO_HANDLE) { - drmAgpUnbind(info->dri->drmFD, info->dri->agpMemHandle); - drmAgpFree(info->dri->drmFD, info->dri->agpMemHandle); - info->dri->agpMemHandle = DRM_AGP_NO_HANDLE; - drmAgpRelease(info->dri->drmFD); - } - if (info->dri->pciMemHandle) { - drmScatterGatherFree(info->dri->drmFD, info->dri->pciMemHandle); - info->dri->pciMemHandle = 0; - } - - if (info->dri->pciGartBackup) { - free(info->dri->pciGartBackup); - info->dri->pciGartBackup = NULL; - } - - /* De-allocate all DRI resources */ - DRICloseScreen(pScreen); - - /* De-allocate all DRI data structures */ - if (info->dri->pDRIInfo) { - if (info->dri->pDRIInfo->devPrivate) { - free(info->dri->pDRIInfo->devPrivate); - info->dri->pDRIInfo->devPrivate = NULL; - } - DRIDestroyInfoRec(info->dri->pDRIInfo); - info->dri->pDRIInfo = NULL; - } - if (info->dri->pVisualConfigs) { - free(info->dri->pVisualConfigs); - info->dri->pVisualConfigs = NULL; - } - if (info->dri->pVisualConfigsPriv) { - free(info->dri->pVisualConfigsPriv); - info->dri->pVisualConfigsPriv = NULL; - } -} - -/* Use callbacks from dri.c to support pageflipping mode for a single - * 3d context without need for any specific full-screen extension. - * - * Also use these callbacks to allocate and free 3d-specific memory on - * demand. - */ - - -#ifdef DAMAGE - -/* Use the damage layer to maintain a list of dirty rectangles. - * These are blitted to the back buffer to keep both buffers clean - * during page-flipping when the 3d application isn't fullscreen. - * - * An alternative to this would be to organize for all on-screen drawing - * operations to be duplicated for the two buffers. That might be - * faster, but seems like a lot more work... - */ - - -static void RADEONDRIRefreshArea(ScrnInfoPtr pScrn, RegionPtr pReg) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - int i, num; - ScreenPtr pScreen = pScrn->pScreen; - drm_radeon_sarea_t *pSAREAPriv = DRIGetSAREAPrivate(pScreen); -#ifdef USE_EXA - PixmapPtr pPix = pScreen->GetScreenPixmap(pScreen); -#endif - RegionRec region; - BoxPtr pbox; - - if (!info->directRenderingInited || !info->cp->CPStarted) - return; - - /* Don't want to do this when no 3d is active and pages are - * right-way-round - */ - if (!pSAREAPriv->pfState && pSAREAPriv->pfCurrentPage == 0) - return; - - REGION_NULL(pScreen, ®ion); - REGION_SUBTRACT(pScreen, ®ion, pReg, &info->dri->driRegion); - - num = REGION_NUM_RECTS(®ion); - - if (!num) { - goto out; - } - - pbox = REGION_RECTS(®ion); - - /* pretty much a hack. */ - -#ifdef USE_EXA - if (info->useEXA) { - uint32_t src_pitch_offset, dst_pitch_offset, datatype; - - RADEONGetPixmapOffsetPitch(pPix, &src_pitch_offset); - dst_pitch_offset = src_pitch_offset + (info->dri->backOffset >> 10); - RADEONGetDatatypeBpp(pScrn->bitsPerPixel, &datatype); - info->accel_state->xdir = info->accel_state->ydir = 1; - - RADEONDoPrepareCopyCP(pScrn, src_pitch_offset, dst_pitch_offset, datatype, - GXcopy, ~0); - } -#endif - -#ifdef USE_XAA - if (!info->useEXA) { - /* Make sure accel has been properly inited */ - if (info->accel_state->accel == NULL || - info->accel_state->accel->SetupForScreenToScreenCopy == NULL) - goto out; - if (info->tilingEnabled) - info->accel_state->dst_pitch_offset |= RADEON_DST_TILE_MACRO; - (*info->accel_state->accel->SetupForScreenToScreenCopy)(pScrn, - 1, 1, GXcopy, - (uint32_t)(-1), -1); - } -#endif - - for (i = 0 ; i < num ; i++, pbox++) { - int xa = max(pbox->x1, 0), xb = min(pbox->x2, pScrn->virtualX-1); - int ya = max(pbox->y1, 0), yb = min(pbox->y2, pScrn->virtualY-1); - - if (xa <= xb && ya <= yb) { -#ifdef USE_EXA - if (info->useEXA) { - RADEONCopyCP(pPix, xa, ya, xa, ya, xb - xa + 1, yb - ya + 1); - } -#endif - -#ifdef USE_XAA - if (!info->useEXA) { - (*info->accel_state->accel->SubsequentScreenToScreenCopy)(pScrn, xa, ya, - xa + info->dri->backX, - ya + info->dri->backY, - xb - xa + 1, - yb - ya + 1); - } -#endif - } - } - -#ifdef USE_XAA - info->accel_state->dst_pitch_offset &= ~RADEON_DST_TILE_MACRO; -#endif - -out: - REGION_NULL(pScreen, ®ion); - DamageEmpty(info->dri->pDamage); -} - -#endif /* DAMAGE */ - -static void RADEONEnablePageFlip(ScreenPtr pScreen) -{ -#ifdef DAMAGE - ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); - RADEONInfoPtr info = RADEONPTR(pScrn); - - if (info->dri->allowPageFlip) { - drm_radeon_sarea_t *pSAREAPriv = DRIGetSAREAPrivate(pScreen); - BoxRec box = { .x1 = 0, .y1 = 0, .x2 = pScrn->virtualX - 1, - .y2 = pScrn->virtualY - 1 }; - RegionPtr pReg = REGION_CREATE(pScreen, &box, 1); - - pSAREAPriv->pfState = 1; - RADEONDRIRefreshArea(pScrn, pReg); - REGION_DESTROY(pScreen, pReg); - } -#endif -} - -static void RADEONDisablePageFlip(ScreenPtr pScreen) -{ - /* Tell the clients not to pageflip. How? - * -- Field in sarea, plus bumping the window counters. - * -- DRM needs to cope with Front-to-Back swapbuffers. - */ - drm_radeon_sarea_t *pSAREAPriv = DRIGetSAREAPrivate(pScreen); - - pSAREAPriv->pfState = 0; -} - -static void RADEONDRITransitionSingleToMulti3d(ScreenPtr pScreen) -{ - RADEONDisablePageFlip(pScreen); -} - -static void RADEONDRITransitionMultiToSingle3d(ScreenPtr pScreen) -{ - /* Let the remaining 3d app start page flipping again */ - RADEONEnablePageFlip(pScreen); -} - -static void RADEONDRITransitionTo3d(ScreenPtr pScreen) -{ - ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); - RADEONInfoPtr info = RADEONPTR(pScrn); -#ifdef USE_XAA - FBAreaPtr fbarea; - int width, height; - - /* EXA allocates these areas up front, so it doesn't do the following - * stuff. - */ - if (!info->useEXA) { - /* reserve offscreen area for back and depth buffers and textures */ - - /* If we still have an area for the back buffer reserved, free it - * first so we always start with all free offscreen memory, except - * maybe for Xv - */ - if (info->dri->backArea) { - xf86FreeOffscreenArea(info->dri->backArea); - info->dri->backArea = NULL; - } - - xf86PurgeUnlockedOffscreenAreas(pScreen); - - xf86QueryLargestOffscreenArea(pScreen, &width, &height, 0, 0, 0); - - /* Free Xv linear offscreen memory if necessary - * FIXME: This is hideous. What about telling xv "oh btw you have no memory - * any more?" -- anholt - */ - if (height < (info->dri->depthTexLines + info->dri->backLines)) { - RADEONPortPrivPtr portPriv = info->adaptor->pPortPrivates[0].ptr; - xf86FreeOffscreenLinear((FBLinearPtr)portPriv->video_memory); - portPriv->video_memory = NULL; - xf86QueryLargestOffscreenArea(pScreen, &width, &height, 0, 0, 0); - } - - /* Reserve placeholder area so the other areas will match the - * pre-calculated offsets - * FIXME: We may have other locked allocations and thus this would allocate - * in the wrong place. The XV surface allocations seem likely. -- anholt - */ - fbarea = xf86AllocateOffscreenArea(pScreen, pScrn->displayWidth, - height - - info->dri->depthTexLines - - info->dri->backLines, - pScrn->displayWidth, - NULL, NULL, NULL); - if (!fbarea) - xf86DrvMsg(pScreen->myNum, X_ERROR, "Unable to reserve placeholder " - "offscreen area, you might experience screen corruption\n"); - - info->dri->backArea = xf86AllocateOffscreenArea(pScreen, pScrn->displayWidth, - info->dri->backLines, - pScrn->displayWidth, - NULL, NULL, NULL); - if (!info->dri->backArea) - xf86DrvMsg(pScreen->myNum, X_ERROR, "Unable to reserve offscreen " - "area for back buffer, you might experience screen " - "corruption\n"); - - info->dri->depthTexArea = xf86AllocateOffscreenArea(pScreen, - pScrn->displayWidth, - info->dri->depthTexLines, - pScrn->displayWidth, - NULL, NULL, NULL); - if (!info->dri->depthTexArea) - xf86DrvMsg(pScreen->myNum, X_ERROR, "Unable to reserve offscreen " - "area for depth buffer and textures, you might " - "experience screen corruption\n"); - - xf86FreeOffscreenArea(fbarea); - } -#endif /* USE_XAA */ - - info->dri->have3DWindows = 1; - - RADEONChangeSurfaces(pScrn); - RADEONEnablePageFlip(pScreen); - - info->want_vblank_interrupts = TRUE; - RADEONDRISetVBlankInterrupt(pScrn, TRUE); - - if (info->cursor) - xf86ForceHWCursor (pScreen, TRUE); -} - -static void RADEONDRITransitionTo2d(ScreenPtr pScreen) -{ - ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); - RADEONInfoPtr info = RADEONPTR(pScrn); - drm_radeon_sarea_t *pSAREAPriv = DRIGetSAREAPrivate(pScreen); - - /* Try flipping back to the front page if necessary */ - if (pSAREAPriv->pfCurrentPage == 1) - drmCommandNone(info->dri->drmFD, DRM_RADEON_FLIP); - - /* Shut down shadowing if we've made it back to the front page */ - if (pSAREAPriv->pfCurrentPage == 0) { - RADEONDisablePageFlip(pScreen); -#ifdef USE_XAA - if (!info->useEXA) { - xf86FreeOffscreenArea(info->dri->backArea); - info->dri->backArea = NULL; - } -#endif - } else { - xf86DrvMsg(pScreen->myNum, X_WARNING, - "[dri] RADEONDRITransitionTo2d: " - "kernel failed to unflip buffers.\n"); - } - -#ifdef USE_XAA - if (!info->useEXA) - xf86FreeOffscreenArea(info->dri->depthTexArea); -#endif - - info->dri->have3DWindows = 0; - - RADEONChangeSurfaces(pScrn); - - info->want_vblank_interrupts = FALSE; - RADEONDRISetVBlankInterrupt(pScrn, FALSE); - - if (info->cursor) - xf86ForceHWCursor (pScreen, FALSE); -} - -#if defined(DAMAGE) && (DRIINFO_MAJOR_VERSION > 5 || \ - (DRIINFO_MAJOR_VERSION == 5 && \ - DRIINFO_MINOR_VERSION >= 1)) -static void -RADEONDRIClipNotify(ScreenPtr pScreen, WindowPtr *ppWin, int num) -{ - ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); - RADEONInfoPtr info = RADEONPTR(pScrn); - - REGION_UNINIT(pScreen, &info->dri->driRegion); - REGION_NULL(pScreen, &info->dri->driRegion); - - if (num > 0) { - int i; - - for (i = 0; i < num; i++) { - WindowPtr pWin = ppWin[i]; - - if (pWin) { - REGION_UNION(pScreen, &info->dri->driRegion, &pWin->clipList, - &info->dri->driRegion); - } - } - } -} -#endif - -void RADEONDRIAllocatePCIGARTTable(ScreenPtr pScreen) -{ - ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); - RADEONInfoPtr info = RADEONPTR(pScrn); - - if (info->cardType != CARD_PCIE || - info->dri->pKernelDRMVersion->version_minor < 19) - return; - - if (info->FbSecureSize==0) - return; - - /* set the old default size of pci gart table */ - if (info->dri->pKernelDRMVersion->version_minor < 26) - info->dri->pciGartSize = 32768; - - info->dri->pciGartSize = RADEONDRIGetPciAperTableSize(pScrn); - - /* allocate space to back up PCIEGART table */ - info->dri->pciGartBackup = xnfcalloc(1, info->dri->pciGartSize); - if (info->dri->pciGartBackup == NULL) - return; - - info->dri->pciGartOffset = (info->FbMapSize - info->FbSecureSize); - - -} - -int RADEONDRIGetPciAperTableSize(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - int ret_size; - int num_pages; - - num_pages = (info->dri->pciAperSize * 1024 * 1024) / 4096; - - if ((info->ChipFamily >= CHIP_FAMILY_R600) || - (info->ChipFamily == CHIP_FAMILY_RS600)) - ret_size = num_pages * sizeof(uint64_t); - else - ret_size = num_pages * sizeof(unsigned int); - - return ret_size; -} - -int RADEONDRISetParam(ScrnInfoPtr pScrn, unsigned int param, int64_t value) -{ - drm_radeon_setparam_t radeonsetparam; - RADEONInfoPtr info = RADEONPTR(pScrn); - int ret; - - memset(&radeonsetparam, 0, sizeof(drm_radeon_setparam_t)); - radeonsetparam.param = param; - radeonsetparam.value = value; - ret = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SETPARAM, - &radeonsetparam, sizeof(drm_radeon_setparam_t)); - return ret; -} diff --git a/src/radeon_dri.h b/src/radeon_dri.h deleted file mode 100644 index 15beb522..00000000 --- a/src/radeon_dri.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Copyright 2000 ATI Technologies Inc., Markham, Ontario, - * VA Linux Systems Inc., Fremont, California. - * - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation on the rights to use, copy, modify, merge, - * publish, distribute, sublicense, and/or sell copies of the Software, - * and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR - * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -/* - * Authors: - * Kevin E. Martin <martin@xfree86.org> - * Rickard E. Faith <faith@valinux.com> - * - */ - -#ifndef _RADEON_DRI_ -#define _RADEON_DRI_ - -#include "xf86drm.h" - -/* DRI Driver defaults */ -#define RADEON_DEFAULT_GART_SIZE 8 /* MB (must be 2^n and > 4MB) */ -#define R300_DEFAULT_GART_SIZE 32 /* MB (for R300 and above) */ -#define RADEON_DEFAULT_RING_SIZE 1 /* MB (must be page aligned) */ -#define RADEON_DEFAULT_BUFFER_SIZE 2 /* MB (must be page aligned) */ -#define RADEON_DEFAULT_GART_TEX_SIZE 1 /* MB (must be page aligned) */ - -#define RADEON_DEFAULT_CP_TIMEOUT 100000 /* usecs */ - -#define RADEON_DEFAULT_PCI_APER_SIZE 32 /* in MB */ - -#define RADEON_CARD_TYPE_RADEON 1 - -typedef struct { - /* DRI screen private data */ - int deviceID; /* PCI device ID */ - int width; /* Width in pixels of display */ - int height; /* Height in scanlines of display */ - int depth; /* Depth of display (8, 15, 16, 24) */ - int bpp; /* Bit depth of display (8, 16, 24, 32) */ - - int IsPCI; /* Current card is a PCI card */ - int AGPMode; - - int frontOffset; /* Start of front buffer */ - int frontPitch; - int backOffset; /* Start of shared back buffer */ - int backPitch; - int depthOffset; /* Start of shared depth buffer */ - int depthPitch; - int textureOffset;/* Start of texture data in frame buffer */ - int textureSize; - int log2TexGran; - - /* MMIO register data */ - drm_handle_t registerHandle; - drmSize registerSize; - - /* CP in-memory status information */ - drm_handle_t statusHandle; - drmSize statusSize; - - /* CP GART Texture data */ - drm_handle_t gartTexHandle; - drmSize gartTexMapSize; - int log2GARTTexGran; - int gartTexOffset; - unsigned int sarea_priv_offset; -} RADEONDRIRec, *RADEONDRIPtr; - -#endif diff --git a/src/radeon_dri2.c b/src/radeon_dri2.c index 43514b7b..8c24de90 100644 --- a/src/radeon_dri2.c +++ b/src/radeon_dri2.c @@ -49,7 +49,6 @@ #endif #endif -#ifdef RADEON_DRI2 #include "radeon_bo_gem.h" @@ -1319,11 +1318,6 @@ radeon_dri2_screen_init(ScreenPtr pScreen) Bool scheduling_works = TRUE; #endif - if (!info->useEXA) { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "DRI2 requires EXA\n"); - return FALSE; - } - info->dri2.device_name = drmGetDeviceNameFromFd(info->dri2.drm_fd); if ( (info->ChipFamily >= CHIP_FAMILY_R600) ) { @@ -1349,7 +1343,7 @@ radeon_dri2_screen_init(ScreenPtr pScreen) dri2_info.CopyRegion = radeon_dri2_copy_region; #ifdef USE_DRI2_SCHEDULING - if (info->dri->pKernelDRMVersion->version_minor < 4) { + if (info->dri2.pKernelDRMVersion->version_minor < 4) { xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "You need a newer kernel for " "sync extension\n"); scheduling_works = FALSE; @@ -1426,4 +1420,3 @@ void radeon_dri2_close_screen(ScreenPtr pScreen) drmFree(info->dri2.device_name); } -#endif diff --git a/src/radeon_dri2.h b/src/radeon_dri2.h index 79952862..0dd2a33c 100644 --- a/src/radeon_dri2.h +++ b/src/radeon_dri2.h @@ -28,16 +28,15 @@ #define RADEON_DRI2_H struct radeon_dri2 { + drmVersionPtr pKernelDRMVersion; int drm_fd; Bool enabled; char *device_name; }; -#ifdef RADEON_DRI2 #include "dri2.h" Bool radeon_dri2_screen_init(ScreenPtr pScreen); void radeon_dri2_close_screen(ScreenPtr pScreen); -#endif int drmmode_get_crtc_id(xf86CrtcPtr crtc); xf86CrtcPtr radeon_covering_crtc(ScrnInfoPtr pScrn, BoxPtr box, diff --git a/src/radeon_driver.c b/src/radeon_driver.c index 56354ad5..49865acf 100644 --- a/src/radeon_driver.c +++ b/src/radeon_driver.c @@ -74,14 +74,6 @@ #include "radeon_macros.h" #include "radeon_probe.h" #include "radeon_version.h" -#include "radeon_atombios.h" - -#ifdef XF86DRI -#define _XF86DRI_SERVER_ -#include "radeon_dri.h" -#include "radeon_drm.h" -#include "sarea.h" -#endif #include "fb.h" @@ -115,101 +107,6 @@ #include "atipciids.h" -#include "radeon_chipset_gen.h" - - -#include "radeon_chipinfo_gen.h" - - /* Forward definitions for driver functions */ -static Bool RADEONCloseScreen(CLOSE_SCREEN_ARGS_DECL); -static Bool RADEONSaveScreen(ScreenPtr pScreen, int mode); -static void RADEONSave(ScrnInfoPtr pScrn); - -static void RADEONSaveMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); - -static void -RADEONSaveBIOSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); - -#ifdef XF86DRI -static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); -#endif - -static const OptionInfoRec RADEONOptions[] = { - { OPTION_NOACCEL, "NoAccel", OPTV_BOOLEAN, {0}, FALSE }, - { OPTION_SW_CURSOR, "SWcursor", OPTV_BOOLEAN, {0}, FALSE }, - { OPTION_DAC_6BIT, "Dac6Bit", OPTV_BOOLEAN, {0}, FALSE }, - { OPTION_DAC_8BIT, "Dac8Bit", OPTV_BOOLEAN, {0}, TRUE }, -#ifdef XF86DRI - { OPTION_BUS_TYPE, "BusType", OPTV_ANYSTR, {0}, FALSE }, - { OPTION_CP_PIO, "CPPIOMode", OPTV_BOOLEAN, {0}, FALSE }, - { OPTION_USEC_TIMEOUT, "CPusecTimeout", OPTV_INTEGER, {0}, FALSE }, - { OPTION_AGP_MODE, "AGPMode", OPTV_INTEGER, {0}, FALSE }, - { OPTION_AGP_FW, "AGPFastWrite", OPTV_BOOLEAN, {0}, FALSE }, - { OPTION_GART_SIZE_OLD, "AGPSize", OPTV_INTEGER, {0}, FALSE }, - { OPTION_GART_SIZE, "GARTSize", OPTV_INTEGER, {0}, FALSE }, - { OPTION_RING_SIZE, "RingSize", OPTV_INTEGER, {0}, FALSE }, - { OPTION_BUFFER_SIZE, "BufferSize", OPTV_INTEGER, {0}, FALSE }, - { OPTION_DEPTH_MOVE, "EnableDepthMoves", OPTV_BOOLEAN, {0}, FALSE }, - { OPTION_PAGE_FLIP, "EnablePageFlip", OPTV_BOOLEAN, {0}, FALSE }, - { OPTION_NO_BACKBUFFER, "NoBackBuffer", OPTV_BOOLEAN, {0}, FALSE }, - { OPTION_XV_DMA, "DMAForXv", OPTV_BOOLEAN, {0}, FALSE }, - { OPTION_FBTEX_PERCENT, "FBTexPercent", OPTV_INTEGER, {0}, FALSE }, - { OPTION_DEPTH_BITS, "DepthBits", OPTV_INTEGER, {0}, FALSE }, - { OPTION_PCIAPER_SIZE, "PCIAPERSize", OPTV_INTEGER, {0}, FALSE }, -#ifdef USE_EXA - { OPTION_ACCEL_DFS, "AccelDFS", OPTV_BOOLEAN, {0}, FALSE }, -#endif -#endif - { OPTION_IGNORE_EDID, "IgnoreEDID", OPTV_BOOLEAN, {0}, FALSE }, - { OPTION_CUSTOM_EDID, "CustomEDID", OPTV_ANYSTR, {0}, FALSE }, - { OPTION_DISP_PRIORITY, "DisplayPriority", OPTV_ANYSTR, {0}, FALSE }, - { OPTION_PANEL_SIZE, "PanelSize", OPTV_ANYSTR, {0}, FALSE }, - { OPTION_MIN_DOTCLOCK, "ForceMinDotClock", OPTV_FREQ, {0}, FALSE }, - { OPTION_COLOR_TILING, "ColorTiling", OPTV_BOOLEAN, {0}, FALSE }, -#ifdef XvExtension - { OPTION_VIDEO_KEY, "VideoKey", OPTV_INTEGER, {0}, FALSE }, - { OPTION_RAGE_THEATRE_CRYSTAL, "RageTheatreCrystal", OPTV_INTEGER, {0}, FALSE }, - { OPTION_RAGE_THEATRE_TUNER_PORT, "RageTheatreTunerPort", OPTV_INTEGER, {0}, FALSE }, - { OPTION_RAGE_THEATRE_COMPOSITE_PORT, "RageTheatreCompositePort", OPTV_INTEGER, {0}, FALSE }, - { OPTION_RAGE_THEATRE_SVIDEO_PORT, "RageTheatreSVideoPort", OPTV_INTEGER, {0}, FALSE }, - { OPTION_TUNER_TYPE, "TunerType", OPTV_INTEGER, {0}, FALSE }, - { OPTION_RAGE_THEATRE_MICROC_PATH, "RageTheatreMicrocPath", OPTV_STRING, {0}, FALSE }, - { OPTION_RAGE_THEATRE_MICROC_TYPE, "RageTheatreMicrocType", OPTV_STRING, {0}, FALSE }, - { OPTION_SCALER_WIDTH, "ScalerWidth", OPTV_INTEGER, {0}, FALSE }, -#endif -#ifdef RENDER - { OPTION_RENDER_ACCEL, "RenderAccel", OPTV_BOOLEAN, {0}, FALSE }, - { OPTION_SUBPIXEL_ORDER, "SubPixelOrder", OPTV_ANYSTR, {0}, FALSE }, -#endif - { OPTION_CLOCK_GATING, "ClockGating", OPTV_BOOLEAN, {0}, FALSE }, - { OPTION_VGA_ACCESS, "VGAAccess", OPTV_BOOLEAN, {0}, TRUE }, - { OPTION_REVERSE_DDC, "ReverseDDC", OPTV_BOOLEAN, {0}, FALSE }, - { OPTION_LVDS_PROBE_PLL, "LVDSProbePLL", OPTV_BOOLEAN, {0}, FALSE }, - { OPTION_ACCELMETHOD, "AccelMethod", OPTV_STRING, {0}, FALSE }, - { OPTION_DRI, "DRI", OPTV_BOOLEAN, {0}, FALSE }, - { OPTION_CONNECTORTABLE, "ConnectorTable", OPTV_STRING, {0}, FALSE }, - { OPTION_DEFAULT_CONNECTOR_TABLE, "DefaultConnectorTable", OPTV_BOOLEAN, {0}, FALSE }, - { OPTION_DEFAULT_TMDS_PLL, "DefaultTMDSPLL", OPTV_BOOLEAN, {0}, FALSE }, -#if defined(__powerpc__) - { OPTION_MAC_MODEL, "MacModel", OPTV_STRING, {0}, FALSE }, -#endif - { OPTION_TVDAC_LOAD_DETECT, "TVDACLoadDetect", OPTV_BOOLEAN, {0}, FALSE }, - { OPTION_FORCE_TVOUT, "ForceTVOut", OPTV_BOOLEAN, {0}, FALSE }, - { OPTION_TVSTD, "TVStandard", OPTV_STRING, {0}, FALSE }, - { OPTION_IGNORE_LID_STATUS, "IgnoreLidStatus", OPTV_BOOLEAN, {0}, FALSE }, - { OPTION_DEFAULT_TVDAC_ADJ, "DefaultTVDACAdj", OPTV_BOOLEAN, {0}, FALSE }, - { OPTION_INT10, "Int10", OPTV_BOOLEAN, {0}, FALSE }, - { OPTION_EXA_VSYNC, "EXAVSync", OPTV_BOOLEAN, {0}, FALSE }, - { OPTION_ATOM_TVOUT, "ATOMTVOut", OPTV_BOOLEAN, {0}, FALSE }, - { OPTION_R4XX_ATOM, "R4xxATOM", OPTV_BOOLEAN, {0}, FALSE }, - { OPTION_FORCE_LOW_POWER, "ForceLowPowerMode", OPTV_BOOLEAN, {0}, FALSE }, - { OPTION_DYNAMIC_PM, "DynamicPM", OPTV_BOOLEAN, {0}, FALSE }, - { OPTION_NEW_PLL, "NewPLL", OPTV_BOOLEAN, {0}, FALSE }, - { OPTION_ZAPHOD_HEADS, "ZaphodHeads", OPTV_STRING, {0}, FALSE }, - { -1, NULL, OPTV_NONE, {0}, FALSE } -}; - -const OptionInfoRec *RADEONOptionsWeak(void) { return RADEONOptions; } extern _X_EXPORT int gRADEONEntityIndex; @@ -218,50 +115,6 @@ static int getRADEONEntityIndex(void) return gRADEONEntityIndex; } -struct RADEONInt10Save { - uint32_t MEM_CNTL; - uint32_t MEMSIZE; - uint32_t MPP_TB_CONFIG; -}; - -static Bool RADEONMapMMIO(ScrnInfoPtr pScrn); -static Bool RADEONUnmapMMIO(ScrnInfoPtr pScrn); - -static void * -radeonShadowWindow(ScreenPtr screen, CARD32 row, CARD32 offset, int mode, - CARD32 *size, void *closure) -{ - ScrnInfoPtr pScrn = xf86ScreenToScrn(screen); - RADEONInfoPtr info = RADEONPTR(pScrn); - int stride; - - stride = (pScrn->displayWidth * pScrn->bitsPerPixel) / 8; - *size = stride; - - return ((uint8_t *)info->FB + pScrn->fbOffset + row * stride + offset); -} -static Bool -RADEONCreateScreenResources (ScreenPtr pScreen) -{ - ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); - RADEONInfoPtr info = RADEONPTR(pScrn); - PixmapPtr pixmap; - - pScreen->CreateScreenResources = info->CreateScreenResources; - if (!(*pScreen->CreateScreenResources)(pScreen)) - return FALSE; - pScreen->CreateScreenResources = RADEONCreateScreenResources; - - if (info->r600_shadow_fb) { - pixmap = pScreen->GetScreenPixmap(pScreen); - - if (!shadowAdd(pScreen, pixmap, shadowUpdatePackedWeak(), - radeonShadowWindow, 0, NULL)) - return FALSE; - } - return TRUE; -} - RADEONEntPtr RADEONEntPriv(ScrnInfoPtr pScrn) { DevUnion *pPriv; @@ -271,83 +124,6 @@ RADEONEntPtr RADEONEntPriv(ScrnInfoPtr pScrn) return pPriv->ptr; } -static void -RADEONPreInt10Save(ScrnInfoPtr pScrn, void **pPtr) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - uint32_t CardTmp; - static struct RADEONInt10Save SaveStruct = { 0, 0, 0 }; - - if (!IS_AVIVO_VARIANT) { - /* Save the values and zap MEM_CNTL */ - SaveStruct.MEM_CNTL = INREG(RADEON_MEM_CNTL); - SaveStruct.MEMSIZE = INREG(RADEON_CONFIG_MEMSIZE); - SaveStruct.MPP_TB_CONFIG = INREG(RADEON_MPP_TB_CONFIG); - - /* - * Zap MEM_CNTL and set MPP_TB_CONFIG<31:24> to 4 - */ - OUTREG(RADEON_MEM_CNTL, 0); - CardTmp = SaveStruct.MPP_TB_CONFIG & 0x00ffffffu; - CardTmp |= 0x04 << 24; - OUTREG(RADEON_MPP_TB_CONFIG, CardTmp); - } - - *pPtr = (void *)&SaveStruct; -} - -static void -RADEONPostInt10Check(ScrnInfoPtr pScrn, void *ptr) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - struct RADEONInt10Save *pSave = ptr; - uint32_t CardTmp; - - /* If we don't have a valid (non-zero) saved MEM_CNTL, get out now */ - if (!pSave || !pSave->MEM_CNTL) - return; - - if (IS_AVIVO_VARIANT) - return; - - /* - * If either MEM_CNTL is currently zero or inconistent (configured for - * two channels with the two channels configured differently), restore - * the saved registers. - */ - CardTmp = INREG(RADEON_MEM_CNTL); - if (!CardTmp || - ((CardTmp & 1) && - (((CardTmp >> 8) & 0xff) != ((CardTmp >> 24) & 0xff)))) { - /* Restore the saved registers */ - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "Restoring MEM_CNTL (%08lx), setting to %08lx\n", - (unsigned long)CardTmp, (unsigned long)pSave->MEM_CNTL); - OUTREG(RADEON_MEM_CNTL, pSave->MEM_CNTL); - - CardTmp = INREG(RADEON_CONFIG_MEMSIZE); - if (CardTmp != pSave->MEMSIZE) { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "Restoring CONFIG_MEMSIZE (%08lx), setting to %08lx\n", - (unsigned long)CardTmp, (unsigned long)pSave->MEMSIZE); - OUTREG(RADEON_CONFIG_MEMSIZE, pSave->MEMSIZE); - } - } - - CardTmp = INREG(RADEON_MPP_TB_CONFIG); - if ((CardTmp & 0xff000000u) != (pSave->MPP_TB_CONFIG & 0xff000000u)) { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "Restoring MPP_TB_CONFIG<31:24> (%02lx), setting to %02lx\n", - (unsigned long)CardTmp >> 24, - (unsigned long)pSave->MPP_TB_CONFIG >> 24); - CardTmp &= 0x00ffffffu; - CardTmp |= (pSave->MPP_TB_CONFIG & 0xff000000u); - OUTREG(RADEON_MPP_TB_CONFIG, CardTmp); - } -} - /* Allocate our private RADEONInfoRec */ Bool RADEONGetRec(ScrnInfoPtr pScrn) { @@ -361,953 +137,20 @@ Bool RADEONGetRec(ScrnInfoPtr pScrn) void RADEONFreeRec(ScrnInfoPtr pScrn) { RADEONInfoPtr info; - int i; if (!pScrn || !pScrn->driverPrivate) return; info = RADEONPTR(pScrn); - if (info->cp) { - free(info->cp); - info->cp = NULL; - } - - if (info->dri) { - free(info->dri); - info->dri = NULL; - } - if (info->accel_state) { free(info->accel_state); info->accel_state = NULL; } - for (i = 0; i < RADEON_MAX_BIOS_CONNECTOR; i++) { - if (info->encoders[i]) { - if (info->encoders[i]->dev_priv) { - free(info->encoders[i]->dev_priv); - info->encoders[i]->dev_priv = NULL; - } - free(info->encoders[i]); - info->encoders[i]= NULL; - } - } - free(pScrn->driverPrivate); pScrn->driverPrivate = NULL; } -/* Memory map the MMIO region. Used during pre-init and by RADEONMapMem, - * below - */ -static Bool RADEONMapMMIO(ScrnInfoPtr pScrn) -{ -#ifdef XSERVER_LIBPCIACCESS - int err; -#endif - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); - - if (pRADEONEnt->MMIO) { - pRADEONEnt->MMIO_cnt++; - info->MMIO = pRADEONEnt->MMIO; - return TRUE; - } - -#ifndef XSERVER_LIBPCIACCESS - - info->MMIO = xf86MapPciMem(pScrn->scrnIndex, - VIDMEM_MMIO | VIDMEM_READSIDEEFFECT, - info->PciTag, - info->MMIOAddr, - info->MMIOSize); - - if (!info->MMIO) - return FALSE; -#else - - err = pci_device_map_range(info->PciInfo, - info->MMIOAddr, - info->MMIOSize, - PCI_DEV_MAP_FLAG_WRITABLE, - &info->MMIO); - - if (err) { - xf86DrvMsg (pScrn->scrnIndex, X_ERROR, - "Unable to map MMIO aperture. %s (%d)\n", - strerror (err), err); - return FALSE; - } - -#endif - - pRADEONEnt->MMIO = info->MMIO; - pRADEONEnt->MMIO_cnt = 1; - return TRUE; -} - -/* Unmap the MMIO region. Used during pre-init and by RADEONUnmapMem, - * below - */ -static Bool RADEONUnmapMMIO(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); - - /* refcount for zaphod */ - if (--pRADEONEnt->MMIO_cnt != 0) { - info->MMIO = NULL; - return TRUE; - } - -#ifndef XSERVER_LIBPCIACCESS - xf86UnMapVidMem(pScrn->scrnIndex, info->MMIO, info->MMIOSize); -#else - pci_device_unmap_range(info->PciInfo, info->MMIO, info->MMIOSize); -#endif - - pRADEONEnt->MMIO = NULL; - info->MMIO = NULL; - return TRUE; -} - -/* Memory map the frame buffer. Used by RADEONMapMem, below. */ -static Bool RADEONMapFB(ScrnInfoPtr pScrn) -{ -#ifdef XSERVER_LIBPCIACCESS - int err; -#endif - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); - - if (pRADEONEnt->FB) { - pRADEONEnt->FB_cnt++; - info->FB = pRADEONEnt->FB; - return TRUE; - } - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "Map: 0x%016llx, 0x%08lx\n", info->LinearAddr, info->FbMapSize); - -#ifndef XSERVER_LIBPCIACCESS - - info->FB = xf86MapPciMem(pScrn->scrnIndex, - VIDMEM_FRAMEBUFFER, - info->PciTag, - info->LinearAddr, - info->FbMapSize); - - if (!info->FB) return FALSE; - -#else - - err = pci_device_map_range(info->PciInfo, - info->LinearAddr, - info->FbMapSize, - PCI_DEV_MAP_FLAG_WRITABLE | - PCI_DEV_MAP_FLAG_WRITE_COMBINE, - &info->FB); - - if (err) { - xf86DrvMsg (pScrn->scrnIndex, X_ERROR, - "Unable to map FB aperture. %s (%d)\n", - strerror (err), err); - return FALSE; - } - -#endif - - pRADEONEnt->FB = info->FB; - pRADEONEnt->FB_cnt = 1; - return TRUE; -} - -/* Unmap the frame buffer. Used by RADEONUnmapMem, below. */ -static Bool RADEONUnmapFB(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); - - /* refcount for zaphod */ - if (--pRADEONEnt->FB_cnt != 0) { - info->FB = NULL; - return TRUE; - } - -#ifndef XSERVER_LIBPCIACCESS - xf86UnMapVidMem(pScrn->scrnIndex, info->FB, info->FbMapSize); -#else - pci_device_unmap_range(info->PciInfo, info->FB, info->FbMapSize); -#endif - - pRADEONEnt->FB = NULL; - info->FB = NULL; - return TRUE; -} - -/* Memory map the MMIO region and the frame buffer */ -static Bool RADEONMapMem(ScrnInfoPtr pScrn) -{ - if (!RADEONMapMMIO(pScrn)) return FALSE; - if (!RADEONMapFB(pScrn)) { - RADEONUnmapMMIO(pScrn); - return FALSE; - } - return TRUE; -} - -/* Unmap the MMIO region and the frame buffer */ -static Bool RADEONUnmapMem(ScrnInfoPtr pScrn) -{ - if (!RADEONUnmapMMIO(pScrn) || !RADEONUnmapFB(pScrn)) return FALSE; - return TRUE; -} - -void RADEONPllErrataAfterIndex(RADEONInfoPtr info) -{ - unsigned char *RADEONMMIO = info->MMIO; - - if (!(info->ChipErrata & CHIP_ERRATA_PLL_DUMMYREADS)) - return; - - /* This workaround is necessary on rv200 and RS200 or PLL - * reads may return garbage (among others...) - */ - (void)INREG(RADEON_CLOCK_CNTL_DATA); - (void)INREG(RADEON_CRTC_GEN_CNTL); -} - -void RADEONPllErrataAfterData(RADEONInfoPtr info) -{ - unsigned char *RADEONMMIO = info->MMIO; - - /* This workarounds is necessary on RV100, RS100 and RS200 chips - * or the chip could hang on a subsequent access - */ - if (info->ChipErrata & CHIP_ERRATA_PLL_DELAY) { - /* we can't deal with posted writes here ... */ - usleep(5000); - } - - /* This function is required to workaround a hardware bug in some (all?) - * revisions of the R300. This workaround should be called after every - * CLOCK_CNTL_INDEX register access. If not, register reads afterward - * may not be correct. - */ - if (info->ChipErrata & CHIP_ERRATA_R300_CG) { - uint32_t save, tmp; - - save = INREG(RADEON_CLOCK_CNTL_INDEX); - tmp = save & ~(0x3f | RADEON_PLL_WR_EN); - OUTREG(RADEON_CLOCK_CNTL_INDEX, tmp); - tmp = INREG(RADEON_CLOCK_CNTL_DATA); - OUTREG(RADEON_CLOCK_CNTL_INDEX, save); - } -} - -/* Read PLL register */ -unsigned RADEONINPLL(ScrnInfoPtr pScrn, int addr) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - uint32_t data; - - OUTREG8(RADEON_CLOCK_CNTL_INDEX, addr & 0x3f); - RADEONPllErrataAfterIndex(info); - data = INREG(RADEON_CLOCK_CNTL_DATA); - RADEONPllErrataAfterData(info); - - return data; -} - -/* Write PLL information */ -void RADEONOUTPLL(ScrnInfoPtr pScrn, int addr, uint32_t data) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - OUTREG8(RADEON_CLOCK_CNTL_INDEX, (((addr) & 0x3f) | - RADEON_PLL_WR_EN)); - RADEONPllErrataAfterIndex(info); - OUTREG(RADEON_CLOCK_CNTL_DATA, data); - RADEONPllErrataAfterData(info); -} - -/* Read MC register */ -unsigned RADEONINMC(ScrnInfoPtr pScrn, int addr) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - uint32_t data; - - if ((info->ChipFamily == CHIP_FAMILY_RS690) || - (info->ChipFamily == CHIP_FAMILY_RS740)) { - OUTREG(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK)); - data = INREG(RS690_MC_DATA); - } else if (info->ChipFamily == CHIP_FAMILY_RS600) { - OUTREG(RS600_MC_INDEX, ((addr & RS600_MC_ADDR_MASK) | RS600_MC_IND_CITF_ARB0)); - data = INREG(RS600_MC_DATA); - } else if ((info->ChipFamily == CHIP_FAMILY_RS780) || - (info->ChipFamily == CHIP_FAMILY_RS880)) { - OUTREG(RS780_MC_INDEX, (addr & RS780_MC_INDEX_MASK)); - data = INREG(RS780_MC_DATA); - } else if (info->ChipFamily >= CHIP_FAMILY_R600) { - data = 0; - } else if (IS_AVIVO_VARIANT) { - OUTREG(AVIVO_MC_INDEX, (addr & 0xff) | 0x7f0000); - (void)INREG(AVIVO_MC_INDEX); - data = INREG(AVIVO_MC_DATA); - - OUTREG(AVIVO_MC_INDEX, 0); - (void)INREG(AVIVO_MC_INDEX); - } else { - OUTREG(R300_MC_IND_INDEX, addr & 0x3f); - (void)INREG(R300_MC_IND_INDEX); - data = INREG(R300_MC_IND_DATA); - - OUTREG(R300_MC_IND_INDEX, 0); - (void)INREG(R300_MC_IND_INDEX); - } - - return data; -} - -/* Write MC information */ -void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, uint32_t data) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - if ((info->ChipFamily == CHIP_FAMILY_RS690) || - (info->ChipFamily == CHIP_FAMILY_RS740)) { - OUTREG(RS690_MC_INDEX, ((addr & RS690_MC_INDEX_MASK) | - RS690_MC_INDEX_WR_EN)); - OUTREG(RS690_MC_DATA, data); - OUTREG(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); - } else if (info->ChipFamily == CHIP_FAMILY_RS600) { - OUTREG(RS600_MC_INDEX, ((addr & RS600_MC_ADDR_MASK) | - RS600_MC_IND_CITF_ARB0 | - RS600_MC_IND_WR_EN)); - OUTREG(RS600_MC_DATA, data); - } else if ((info->ChipFamily == CHIP_FAMILY_RS780) || - (info->ChipFamily == CHIP_FAMILY_RS880)) { - OUTREG(RS780_MC_INDEX, ((addr & RS780_MC_INDEX_MASK) | - RS780_MC_INDEX_WR_EN)); - OUTREG(RS780_MC_DATA, data); - } else if (info->ChipFamily >= CHIP_FAMILY_R600) { - // do nothing - } else if (IS_AVIVO_VARIANT) { - OUTREG(AVIVO_MC_INDEX, (addr & 0xff) | 0xff0000); - (void)INREG(AVIVO_MC_INDEX); - OUTREG(AVIVO_MC_DATA, data); - OUTREG(AVIVO_MC_INDEX, 0); - (void)INREG(AVIVO_MC_INDEX); - } else { - OUTREG(R300_MC_IND_INDEX, (((addr) & 0x3f) | - R300_MC_IND_WR_EN)); - (void)INREG(R300_MC_IND_INDEX); - OUTREG(R300_MC_IND_DATA, data); - OUTREG(R300_MC_IND_INDEX, 0); - (void)INREG(R300_MC_IND_INDEX); - } -} - -/* Read PCIE register */ -unsigned RADEONINPCIE(ScrnInfoPtr pScrn, int addr) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - CARD32 data; - - OUTREG(RADEON_PCIE_INDEX, addr & 0xff); - data = INREG(RADEON_PCIE_DATA); - - return data; -} - -/* Write PCIE register */ -void RADEONOUTPCIE(ScrnInfoPtr pScrn, int addr, uint32_t data) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - OUTREG(RADEON_PCIE_INDEX, ((addr) & 0xff)); - OUTREG(RADEON_PCIE_DATA, data); -} - -/* Read PCIE PORT register */ -unsigned R600INPCIE_PORT(ScrnInfoPtr pScrn, int addr) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - CARD32 data; - - OUTREG(R600_PCIE_PORT_INDEX, addr & 0xff); - data = INREG(R600_PCIE_PORT_DATA); - - return data; -} - -/* Write PCIE PORT register */ -void R600OUTPCIE_PORT(ScrnInfoPtr pScrn, int addr, uint32_t data) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - OUTREG(R600_PCIE_PORT_INDEX, ((addr) & 0xff)); - OUTREG(R600_PCIE_PORT_DATA, data); -} - -static Bool radeon_get_mc_idle(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - if (info->ChipFamily >= CHIP_FAMILY_CEDAR) { - if (INREG(R600_SRBM_STATUS) & 0x1f00) - return FALSE; - else - return TRUE; - } else if (info->ChipFamily >= CHIP_FAMILY_R600) { - if (INREG(R600_SRBM_STATUS) & 0x3f00) - return FALSE; - else - return TRUE; - } else if (info->ChipFamily == CHIP_FAMILY_RV515) { - if (INMC(pScrn, RV515_MC_STATUS) & RV515_MC_STATUS_IDLE) - return TRUE; - else - return FALSE; - } else if (info->ChipFamily == CHIP_FAMILY_RS600) { - if (INMC(pScrn, RS600_MC_STATUS) & RS600_MC_IDLE) - return TRUE; - else - return FALSE; - } else if ((info->ChipFamily == CHIP_FAMILY_RS690) || - (info->ChipFamily == CHIP_FAMILY_RS740)) { - if (INMC(pScrn, RS690_MC_STATUS) & RS690_MC_STATUS_IDLE) - return TRUE; - else - return FALSE; - } else if (info->ChipFamily >= CHIP_FAMILY_R520) { - if (INMC(pScrn, R520_MC_STATUS) & R520_MC_STATUS_IDLE) - return TRUE; - else - return FALSE; - } else if ((info->ChipFamily == CHIP_FAMILY_RS400) || - (info->ChipFamily == CHIP_FAMILY_RS480)) { - if (INREG(RADEON_MC_STATUS) & RADEON_MC_IDLE) - return TRUE; - else - return FALSE; - } else if (IS_R300_VARIANT) { - if (INREG(RADEON_MC_STATUS) & R300_MC_IDLE) - return TRUE; - else - return FALSE; - } else { - if (INREG(RADEON_MC_STATUS) & RADEON_MC_IDLE) - return TRUE; - else - return FALSE; - } -} - -#define LOC_FB 0x1 -#define LOC_AGP 0x2 -static void radeon_write_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, uint32_t fb_loc, uint32_t agp_loc, uint32_t agp_loc_hi) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - /* evergreen is same as r7xx */ - if (info->ChipFamily >= CHIP_FAMILY_RV770) { - if (mask & LOC_FB) - OUTREG(R700_MC_VM_FB_LOCATION, fb_loc); - if (mask & LOC_AGP) { - OUTREG(R700_MC_VM_AGP_BOT, agp_loc); - OUTREG(R700_MC_VM_AGP_TOP, agp_loc_hi); - } - } else if (info->ChipFamily >= CHIP_FAMILY_R600) { - if (mask & LOC_FB) - OUTREG(R600_MC_VM_FB_LOCATION, fb_loc); - if (mask & LOC_AGP) { - OUTREG(R600_MC_VM_AGP_BOT, agp_loc); - OUTREG(R600_MC_VM_AGP_TOP, agp_loc_hi); - } - } else if (info->ChipFamily == CHIP_FAMILY_RV515) { - if (mask & LOC_FB) - OUTMC(pScrn, RV515_MC_FB_LOCATION, fb_loc); - if (mask & LOC_AGP) - OUTMC(pScrn, RV515_MC_AGP_LOCATION, agp_loc); - (void)INMC(pScrn, RV515_MC_AGP_LOCATION); - } else if (info->ChipFamily == CHIP_FAMILY_RS600) { - if (mask & LOC_FB) - OUTMC(pScrn, RS600_MC_FB_LOCATION, fb_loc); - if (mask & LOC_AGP) - OUTMC(pScrn, RS600_MC_AGP_LOCATION, agp_loc); - } else if ((info->ChipFamily == CHIP_FAMILY_RS690) || - (info->ChipFamily == CHIP_FAMILY_RS740)) { - if (mask & LOC_FB) - OUTMC(pScrn, RS690_MC_FB_LOCATION, fb_loc); - if (mask & LOC_AGP) - OUTMC(pScrn, RS690_MC_AGP_LOCATION, agp_loc); - } else if (info->ChipFamily >= CHIP_FAMILY_R520) { - if (mask & LOC_FB) - OUTMC(pScrn, R520_MC_FB_LOCATION, fb_loc); - if (mask & LOC_AGP) - OUTMC(pScrn, R520_MC_AGP_LOCATION, agp_loc); - (void)INMC(pScrn, R520_MC_FB_LOCATION); - } else { - if (mask & LOC_FB) - OUTREG(RADEON_MC_FB_LOCATION, fb_loc); - if (mask & LOC_AGP) - OUTREG(RADEON_MC_AGP_LOCATION, agp_loc); - } -} - -static void radeon_read_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, uint32_t *fb_loc, uint32_t *agp_loc, uint32_t *agp_loc_hi) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - /* evergreen is same as r7xx */ - if (info->ChipFamily >= CHIP_FAMILY_RV770) { - if (mask & LOC_FB) - *fb_loc = INREG(R700_MC_VM_FB_LOCATION); - if (mask & LOC_AGP) { - *agp_loc = INREG(R700_MC_VM_AGP_BOT); - *agp_loc_hi = INREG(R700_MC_VM_AGP_TOP); - } - } else if (info->ChipFamily >= CHIP_FAMILY_R600) { - if (mask & LOC_FB) - *fb_loc = INREG(R600_MC_VM_FB_LOCATION); - if (mask & LOC_AGP) { - *agp_loc = INREG(R600_MC_VM_AGP_BOT); - *agp_loc_hi = INREG(R600_MC_VM_AGP_TOP); - } - } else if (info->ChipFamily == CHIP_FAMILY_RV515) { - if (mask & LOC_FB) - *fb_loc = INMC(pScrn, RV515_MC_FB_LOCATION); - if (mask & LOC_AGP) { - *agp_loc = INMC(pScrn, RV515_MC_AGP_LOCATION); - *agp_loc_hi = 0; - } - } else if (info->ChipFamily == CHIP_FAMILY_RS600) { - if (mask & LOC_FB) - *fb_loc = INMC(pScrn, RS600_MC_FB_LOCATION); - if (mask & LOC_AGP) { - *agp_loc = INMC(pScrn, RS600_MC_AGP_LOCATION); - *agp_loc_hi = 0; - } - } else if ((info->ChipFamily == CHIP_FAMILY_RS690) || - (info->ChipFamily == CHIP_FAMILY_RS740)) { - if (mask & LOC_FB) - *fb_loc = INMC(pScrn, RS690_MC_FB_LOCATION); - if (mask & LOC_AGP) { - *agp_loc = INMC(pScrn, RS690_MC_AGP_LOCATION); - *agp_loc_hi = 0; - } - } else if (info->ChipFamily >= CHIP_FAMILY_R520) { - if (mask & LOC_FB) - *fb_loc = INMC(pScrn, R520_MC_FB_LOCATION); - if (mask & LOC_AGP) { - *agp_loc = INMC(pScrn, R520_MC_AGP_LOCATION); - *agp_loc_hi = 0; - } - } else { - if (mask & LOC_FB) - *fb_loc = INREG(RADEON_MC_FB_LOCATION); - if (mask & LOC_AGP) - *agp_loc = INREG(RADEON_MC_AGP_LOCATION); - } -} - -#if 0 -/* Read PAL information (only used for debugging) */ -static int RADEONINPAL(int idx) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - OUTREG(RADEON_PALETTE_INDEX, idx << 16); - return INREG(RADEON_PALETTE_DATA); -} -#endif - -/* Wait for vertical sync on primary CRTC */ -void RADEONWaitForVerticalSync(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - uint32_t crtc_gen_cntl; - struct timeval timeout; - - crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL); - if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) || - !(crtc_gen_cntl & RADEON_CRTC_EN)) - return; - - /* Clear the CRTC_VBLANK_SAVE bit */ - OUTREG(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR); - - /* Wait for it to go back up */ - radeon_init_timeout(&timeout, RADEON_VSYNC_TIMEOUT); - while (!(INREG(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_SAVE) && - !radeon_timedout(&timeout)) - usleep(100); -} - -/* Wait for vertical sync on secondary CRTC */ -void RADEONWaitForVerticalSync2(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - uint32_t crtc2_gen_cntl; - struct timeval timeout; - - crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL); - if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) || - !(crtc2_gen_cntl & RADEON_CRTC2_EN)) - return; - - /* Clear the CRTC2_VBLANK_SAVE bit */ - OUTREG(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR); - - /* Wait for it to go back up */ - radeon_init_timeout(&timeout, RADEON_VSYNC_TIMEOUT); - while (!(INREG(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_SAVE) && - !radeon_timedout(&timeout)) - usleep(100); -} - - -/* Compute log base 2 of val */ -int RADEONMinBits(int val) -{ - int bits; - - if (!val) return 1; - for (bits = 0; val; val >>= 1, ++bits); - return bits; -} - -/* Compute n/d with rounding */ -static int RADEONDiv(int n, int d) -{ - return (n + (d / 2)) / d; -} - -static Bool RADEONProbePLLParameters(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONPLLPtr pll = &info->pll; - unsigned char *RADEONMMIO = info->MMIO; - unsigned char ppll_div_sel; - unsigned mpll_fb_div, spll_fb_div, M; - unsigned xclk, tmp, ref_div; - int hTotal, vTotal, num, denom, m, n; - float hz, prev_xtal, vclk, xtal, mpll, spll; - long total_usecs; - struct timeval start, stop, to1, to2; - unsigned int f1, f2, f3; - int tries = 0; - - prev_xtal = 0; - again: - xtal = 0; - if (++tries > 10) - goto failed; - - gettimeofday(&to1, NULL); - f1 = INREG(RADEON_CRTC_CRNT_FRAME); - for (;;) { - f2 = INREG(RADEON_CRTC_CRNT_FRAME); - if (f1 != f2) - break; - gettimeofday(&to2, NULL); - if ((to2.tv_sec - to1.tv_sec) > 1) { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Clock not counting...\n"); - goto failed; - } - } - gettimeofday(&start, NULL); - for(;;) { - f3 = INREG(RADEON_CRTC_CRNT_FRAME); - if (f3 != f2) - break; - gettimeofday(&to2, NULL); - if ((to2.tv_sec - start.tv_sec) > 1) - goto failed; - } - gettimeofday(&stop, NULL); - - if ((stop.tv_sec - start.tv_sec) != 0) - goto again; - total_usecs = abs(stop.tv_usec - start.tv_usec); - if (total_usecs == 0) - goto again; - hz = 1000000.0/(float)total_usecs; - - hTotal = ((INREG(RADEON_CRTC_H_TOTAL_DISP) & 0x3ff) + 1) * 8; - vTotal = ((INREG(RADEON_CRTC_V_TOTAL_DISP) & 0xfff) + 1); - vclk = (float)(hTotal * (float)(vTotal * hz)); - - switch((INPLL(pScrn, RADEON_PPLL_REF_DIV) & 0x30000) >> 16) { - case 0: - default: - num = 1; - denom = 1; - break; - case 1: - n = ((INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV) >> 16) & 0xff); - m = (INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV) & 0xff); - num = 2*n; - denom = 2*m; - break; - case 2: - n = ((INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV) >> 8) & 0xff); - m = (INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV) & 0xff); - num = 2*n; - denom = 2*m; - break; - } - - ppll_div_sel = INREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3; - RADEONPllErrataAfterIndex(info); - - n = (INPLL(pScrn, RADEON_PPLL_DIV_0 + ppll_div_sel) & 0x7ff); - m = (INPLL(pScrn, RADEON_PPLL_REF_DIV) & 0x3ff); - - num *= n; - denom *= m; - - switch ((INPLL(pScrn, RADEON_PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) { - case 1: - denom *= 2; - break; - case 2: - denom *= 4; - break; - case 3: - denom *= 8; - break; - case 4: - denom *= 3; - break; - case 6: - denom *= 6; - break; - case 7: - denom *= 12; - break; - } - - xtal = (int)(vclk *(float)denom/(float)num); - - if ((xtal > 26900000) && (xtal < 27100000)) - xtal = 2700; - else if ((xtal > 14200000) && (xtal < 14400000)) - xtal = 1432; - else if ((xtal > 29400000) && (xtal < 29600000)) - xtal = 2950; - else - goto again; - failed: - if (xtal == 0) { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Failed to probe xtal value ! " - "Using default 27Mhz\n"); - xtal = 2700; - } else { - if (prev_xtal == 0) { - prev_xtal = xtal; - tries = 0; - goto again; - } else if (prev_xtal != xtal) { - prev_xtal = 0; - goto again; - } - } - - tmp = INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV); - ref_div = INPLL(pScrn, RADEON_PPLL_REF_DIV) & 0x3ff; - - /* Some sanity check based on the BIOS code .... */ - if (ref_div < 2) { - uint32_t tmp; - tmp = INPLL(pScrn, RADEON_PPLL_REF_DIV); - if (IS_R300_VARIANT - || (info->ChipFamily == CHIP_FAMILY_RS300) - || (info->ChipFamily == CHIP_FAMILY_RS400) - || (info->ChipFamily == CHIP_FAMILY_RS480)) - ref_div = (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> - R300_PPLL_REF_DIV_ACC_SHIFT; - else - ref_div = tmp & RADEON_PPLL_REF_DIV_MASK; - if (ref_div < 2) - ref_div = 12; - } - - /* Calculate "base" xclk straight from MPLL, though that isn't - * really useful (hopefully). This isn't called XCLK anymore on - * radeon's... - */ - mpll_fb_div = (tmp & 0xff00) >> 8; - spll_fb_div = (tmp & 0xff0000) >> 16; - M = (tmp & 0xff); - xclk = RADEONDiv((2 * mpll_fb_div * xtal), (M)); - - /* - * Calculate MCLK based on MCLK-A - */ - mpll = (2.0 * (float)mpll_fb_div * (xtal / 100.0)) / (float)M; - spll = (2.0 * (float)spll_fb_div * (xtal / 100.0)) / (float)M; - - tmp = INPLL(pScrn, RADEON_MCLK_CNTL) & 0x7; - switch(tmp) { - case 1: info->mclk = mpll; break; - case 2: info->mclk = mpll / 2.0; break; - case 3: info->mclk = mpll / 4.0; break; - case 4: info->mclk = mpll / 8.0; break; - case 7: info->mclk = spll; break; - default: - info->mclk = 200.00; - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unsupported MCLKA source" - " setting %d, can't probe MCLK value !\n", tmp); - } - - /* - * Calculate SCLK - */ - tmp = INPLL(pScrn, RADEON_SCLK_CNTL) & 0x7; - switch(tmp) { - case 1: info->sclk = spll; break; - case 2: info->sclk = spll / 2.0; break; - case 3: info->sclk = spll / 4.0; break; - case 4: info->sclk = spll / 8.0; break; - case 7: info->sclk = mpll; break; - default: - info->sclk = 200.00; - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unsupported SCLK source" - " setting %d, can't probe SCLK value !\n", tmp); - } - - /* we're done, hopefully these are sane values */ - pll->reference_div = ref_div; - pll->xclk = xclk; - pll->reference_freq = xtal; - - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Probed PLL values: xtal: %f Mhz, " - "sclk: %f Mhz, mclk: %f Mhz\n", xtal/100.0, info->sclk, info->mclk); - - return TRUE; -} - -static void RADEONGetClockInfo(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR (pScrn); - RADEONPLLPtr pll = &info->pll; - double min_dotclock; - - if (RADEONGetClockInfoFromBIOS(pScrn)) { - if (pll->reference_div < 2) { - /* retrive it from register setting for fitting into current PLL algorithm. - We'll probably need a new routine to calculate the best ref_div from BIOS - provided min_input_pll and max_input_pll - */ - if (!IS_AVIVO_VARIANT) { - uint32_t tmp; - tmp = INPLL(pScrn, RADEON_PPLL_REF_DIV); - if (IS_R300_VARIANT || - (info->ChipFamily == CHIP_FAMILY_RS300) || - (info->ChipFamily == CHIP_FAMILY_RS400) || - (info->ChipFamily == CHIP_FAMILY_RS480)) { - pll->reference_div = (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> R300_PPLL_REF_DIV_ACC_SHIFT; - } else { - pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK; - } - } - if (pll->reference_div < 2) pll->reference_div = 12; - } - } else { - xf86DrvMsg (pScrn->scrnIndex, X_WARNING, - "Video BIOS not detected, using default clock settings!\n"); - - /* Default min/max PLL values */ - if (info->ChipFamily == CHIP_FAMILY_R420 || info->ChipFamily == CHIP_FAMILY_RV410) { - pll->pll_in_min = 100; - pll->pll_in_max = 1350; - pll->pll_out_min = 20000; - pll->pll_out_max = 50000; - } else { - pll->pll_in_min = 40; - pll->pll_in_max = 500; - pll->pll_out_min = 12500; - pll->pll_out_max = 35000; - } - - if (!RADEONProbePLLParameters(pScrn)) { - if (info->IsIGP) - pll->reference_freq = 1432; - else - pll->reference_freq = 2700; - - pll->reference_div = 12; - pll->xclk = 10300; - - info->sclk = 200.00; - info->mclk = 200.00; - } - } - - /* card limits for computing PLLs */ - if (IS_AVIVO_VARIANT) { - pll->min_post_div = 2; - pll->max_post_div = 0x7f; - pll->min_frac_feedback_div = 0; - pll->max_frac_feedback_div = 9; - } else { - pll->min_post_div = 1; - pll->max_post_div = 12; //16 on crtc0 - pll->min_frac_feedback_div = 0; - pll->max_frac_feedback_div = 0; - } - pll->min_ref_div = 2; - pll->max_ref_div = 0x3ff; - pll->min_feedback_div = 4; - pll->max_feedback_div = 0x7ff; - pll->best_vco = 0; - - xf86DrvMsg (pScrn->scrnIndex, X_INFO, - "PLL parameters: rf=%u rd=%u min=%u max=%u; xclk=%u\n", - pll->reference_freq, - pll->reference_div, - (unsigned)pll->pll_out_min, (unsigned)pll->pll_out_max, - pll->xclk); - - /* (Some?) Radeon BIOSes seem too lie about their minimum dot - * clocks. Allow users to override the detected minimum dot clock - * value (e.g., and allow it to be suitable for TV sets). - */ - if (xf86GetOptValFreq(info->Options, OPTION_MIN_DOTCLOCK, - OPTUNITS_MHZ, &min_dotclock)) { - if (min_dotclock < 12 || min_dotclock*100 >= pll->pll_out_max) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Illegal minimum dotclock specified %.2f MHz " - "(option ignored)\n", - min_dotclock); - } else { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Forced minimum dotclock to %.2f MHz " - "(instead of detected %.2f MHz)\n", - min_dotclock, ((double)pll->pll_out_min/1000)); - pll->pll_out_min = min_dotclock * 1000; - } - } -} - - - /* This is called by RADEONPreInit to set up the default visual */ Bool RADEONPreInitVisual(ScrnInfoPtr pScrn) { @@ -1383,10 +226,6 @@ Bool RADEONPreInitWeight(ScrnInfoPtr pScrn) if (!xf86SetWeight(pScrn, defaultWeight, defaultWeight)) return FALSE; } else { pScrn->rgbBits = 8; - if (xf86ReturnOptValBool(info->Options, OPTION_DAC_6BIT, FALSE)) { - pScrn->rgbBits = 6; - info->dac6bits = TRUE; - } } xf86DrvMsg(pScrn->scrnIndex, X_INFO, @@ -1396,1437 +235,6 @@ Bool RADEONPreInitWeight(ScrnInfoPtr pScrn) return TRUE; } -void RADEONInitMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save, - RADEONInfoPtr info) -{ - save->mc_fb_location = info->mc_fb_location; - save->mc_agp_location = info->mc_agp_location; - - if (IS_AVIVO_VARIANT) { - save->mc_agp_location_hi = info->mc_agp_location_hi; - } else { - save->display_base_addr = info->fbLocation; - save->display2_base_addr = info->fbLocation; - save->ov0_base_addr = info->fbLocation; - } -} - -static void RADEONInitMemoryMap(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - uint64_t mem_size; - uint64_t aper_size; - - radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &info->mc_fb_location, - &info->mc_agp_location, &info->mc_agp_location_hi); - - /* We shouldn't use info->videoRam here which might have been clipped - * but the real video RAM instead - */ - if (info->ChipFamily >= CHIP_FAMILY_PALM) { - /* size in bytes on fusion */ - mem_size = INREG(R600_CONFIG_MEMSIZE); - /* size in MB on fusion */ - aper_size = INREG(R600_CONFIG_APER_SIZE) * 1024 * 1024; - } else if (info->ChipFamily >= CHIP_FAMILY_CEDAR) { - /* size in MB on evergreen */ - /* XXX watch for overflow!!! */ - mem_size = INREG(R600_CONFIG_MEMSIZE) * 1024 * 1024; - aper_size = INREG(R600_CONFIG_APER_SIZE) * 1024 * 1024; - } else if (info->ChipFamily >= CHIP_FAMILY_R600) { - mem_size = INREG(R600_CONFIG_MEMSIZE); - aper_size = INREG(R600_CONFIG_APER_SIZE); - } else { - mem_size = INREG(RADEON_CONFIG_MEMSIZE); - aper_size = INREG(RADEON_CONFIG_APER_SIZE); - } - - if (mem_size == 0) - mem_size = 0x800000; - - /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - - Novell bug 204882 + along with lots of ubuntu ones */ - if (aper_size > mem_size) - mem_size = aper_size; - - /* don't map the whole FB in the internal address space. - * we don't currently use fb space larger than the aperture - * size and on cards with more than 512 MB of vram, this can overflow - * the internal top of gart calculation on some systems. - * Limit it to cards with more than 512 MB as this causes problems - * on some other cards due to the way the ddx and drm set up the - * internal memory map. - * See fdo bug 24301. - */ - if (mem_size > 0x20000000) - mem_size = aper_size; - -#ifdef XF86DRI - /* Apply memory map limitation if using an old DRI */ - if (info->directRenderingEnabled && !info->dri->newMemoryMap) { - if (aper_size < mem_size) - mem_size = aper_size; - } -#endif - - if ((info->ChipFamily != CHIP_FAMILY_RS600) && - (info->ChipFamily != CHIP_FAMILY_RS690) && - (info->ChipFamily != CHIP_FAMILY_RS740) && - (info->ChipFamily != CHIP_FAMILY_RS780) && - (info->ChipFamily != CHIP_FAMILY_RS880) && - (info->ChipFamily != CHIP_FAMILY_PALM) && - (info->ChipFamily != CHIP_FAMILY_SUMO) && - (info->ChipFamily != CHIP_FAMILY_SUMO2)) { - if (info->IsIGP) - info->mc_fb_location = INREG(RADEON_NB_TOM); - else -#ifdef XF86DRI - /* Old DRI has restrictions on the memory map */ - if ( info->directRenderingEnabled && - info->dri->pKernelDRMVersion->version_minor < 10 ) - info->mc_fb_location = (mem_size - 1) & 0xffff0000U; - else -#endif - { - uint64_t aper0_base; - - if (info->ChipFamily >= CHIP_FAMILY_R600) { - aper0_base = INREG(R600_CONFIG_F0_BASE); - } else { - aper0_base = INREG(RADEON_CONFIG_APER_0_BASE); - } - - /* Recent chips have an "issue" with the memory controller, the - * location must be aligned to the size. We just align it down, - * too bad if we walk over the top of system memory, we don't - * use DMA without a remapped anyway. - * Affected chips are rv280, all r3xx, and all r4xx, but not IGP - */ - if (info->ChipFamily == CHIP_FAMILY_RV280 || - info->ChipFamily == CHIP_FAMILY_R300 || - info->ChipFamily == CHIP_FAMILY_R350 || - info->ChipFamily == CHIP_FAMILY_RV350 || - info->ChipFamily == CHIP_FAMILY_RV380 || - info->ChipFamily == CHIP_FAMILY_R420 || - info->ChipFamily == CHIP_FAMILY_RV410) - aper0_base &= ~(mem_size - 1); - - if (info->ChipFamily >= CHIP_FAMILY_R600) { - uint64_t mc_fb = ((aper0_base >> 24) & 0xffff) | - (((aper0_base + mem_size - 1) >> 8) & 0xffff0000); - info->mc_fb_location = mc_fb & 0xffffffff; - ErrorF("mc fb loc is %08x\n", (unsigned int)info->mc_fb_location); - } else { - uint64_t mc_fb = ((aper0_base >> 16) & 0xffff) | - ((aper0_base + mem_size - 1) & 0xffff0000U); - info->mc_fb_location = mc_fb & 0xffffffff; - } - } - } - if (info->ChipFamily >= CHIP_FAMILY_R600) { - info->fbLocation = ((uint64_t)info->mc_fb_location & 0xffff) << 24; - } else { - info->fbLocation = ((uint64_t)info->mc_fb_location & 0xffff) << 16; - } - /* Just disable the damn AGP apertures for now, it may be - * re-enabled later by the DRM - */ - if (IS_AVIVO_VARIANT) - info->mc_agp_location = 0x003f0000; - else - info->mc_agp_location = 0xffffffc0; - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "RADEONInitMemoryMap() : \n"); - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - " mem_size : 0x%08x\n", (unsigned)mem_size); - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - " MC_FB_LOCATION : 0x%08x\n", (unsigned)info->mc_fb_location); - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - " MC_AGP_LOCATION : 0x%08x\n", - (unsigned)info->mc_agp_location); -} - -static void RADEONGetVRamType(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - uint32_t tmp; - - if (info->IsIGP || (info->ChipFamily >= CHIP_FAMILY_R300)) - info->IsDDR = TRUE; - else if (INREG(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR) - info->IsDDR = TRUE; - else - info->IsDDR = FALSE; - - if ((info->ChipFamily >= CHIP_FAMILY_R600) && - (info->ChipFamily <= CHIP_FAMILY_RV635)) { - int chansize; - /* r6xx */ - tmp = INREG(R600_RAMCFG); - if (tmp & R600_CHANSIZE_OVERRIDE) - chansize = 16; - else if (tmp & R600_CHANSIZE) - chansize = 64; - else - chansize = 32; - if (info->ChipFamily == CHIP_FAMILY_R600) - info->RamWidth = 8 * chansize; - else if (info->ChipFamily == CHIP_FAMILY_RV670) - info->RamWidth = 4 * chansize; - else if ((info->ChipFamily == CHIP_FAMILY_RV610) || - (info->ChipFamily == CHIP_FAMILY_RV620)) - info->RamWidth = chansize; - else if ((info->ChipFamily == CHIP_FAMILY_RV630) || - (info->ChipFamily == CHIP_FAMILY_RV635)) - info->RamWidth = 2 * chansize; - } else if (info->ChipFamily == CHIP_FAMILY_RV515) { - /* rv515/rv550 */ - tmp = INMC(pScrn, RV515_MC_CNTL); - tmp &= RV515_MEM_NUM_CHANNELS_MASK; - switch (tmp) { - case 0: info->RamWidth = 64; break; - case 1: info->RamWidth = 128; break; - default: info->RamWidth = 128; break; - } - } else if ((info->ChipFamily >= CHIP_FAMILY_R520) && - (info->ChipFamily <= CHIP_FAMILY_RV570)){ - /* r520/rv530/rv560/rv570/r580 */ - tmp = INMC(pScrn, R520_MC_CNTL0); - switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) { - case 0: info->RamWidth = 32; break; - case 1: info->RamWidth = 64; break; - case 2: info->RamWidth = 128; break; - case 3: info->RamWidth = 256; break; - default: info->RamWidth = 64; break; - } - if (tmp & R520_MC_CHANNEL_SIZE) { - info->RamWidth *= 2; - } - } else if ((info->ChipFamily >= CHIP_FAMILY_R300) && - (info->ChipFamily <= CHIP_FAMILY_RV410)) { - /* r3xx, r4xx */ - tmp = INREG(RADEON_MEM_CNTL); - tmp &= R300_MEM_NUM_CHANNELS_MASK; - switch (tmp) { - case 0: info->RamWidth = 64; break; - case 1: info->RamWidth = 128; break; - case 2: info->RamWidth = 256; break; - default: info->RamWidth = 128; break; - } - } else if ((info->ChipFamily == CHIP_FAMILY_RV100) || - (info->ChipFamily == CHIP_FAMILY_RS100) || - (info->ChipFamily == CHIP_FAMILY_RS200)){ - tmp = INREG(RADEON_MEM_CNTL); - if (tmp & RV100_HALF_MODE) - info->RamWidth = 32; - else - info->RamWidth = 64; - - if (!pRADEONEnt->HasCRTC2) { - info->RamWidth /= 4; - info->IsDDR = TRUE; - } - } else if (info->ChipFamily <= CHIP_FAMILY_RV280) { - tmp = INREG(RADEON_MEM_CNTL); - if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) - info->RamWidth = 128; - else - info->RamWidth = 64; - } else { - /* newer IGPs */ - info->RamWidth = 128; - } - - /* This may not be correct, as some cards can have half of channel disabled - * ToDo: identify these cases - */ -} - -/* - * Depending on card genertation, chipset bugs, etc... the amount of vram - * accessible to the CPU can vary. This function is our best shot at figuring - * it out. Returns a value in KB. - */ -static uint32_t RADEONGetAccessibleVRAM(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - uint32_t aper_size; - unsigned char byte; - - if (info->ChipFamily >= CHIP_FAMILY_CEDAR) - /* size in MB on evergreen and fusion */ - aper_size = INREG(R600_CONFIG_APER_SIZE) * 1024; - else if (info->ChipFamily >= CHIP_FAMILY_R600) - aper_size = INREG(R600_CONFIG_APER_SIZE) / 1024; - else - aper_size = INREG(RADEON_CONFIG_APER_SIZE) / 1024; - -#ifdef XF86DRI - /* If we use the DRI, we need to check if it's a version that has the - * bug of always cropping MC_FB_LOCATION to one aperture, in which case - * we need to limit the amount of accessible video memory - */ - if (info->directRenderingEnabled && - info->dri->pKernelDRMVersion->version_minor < 23) { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "[dri] limiting video memory to one aperture of %uK\n", - (unsigned)aper_size); - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "[dri] detected radeon kernel module version 1.%d but" - " 1.23 or newer is required for full memory mapping.\n", - info->dri->pKernelDRMVersion->version_minor); - info->dri->newMemoryMap = FALSE; - return aper_size; - } - info->dri->newMemoryMap = TRUE; -#endif /* XF86DRI */ - - if (info->ChipFamily >= CHIP_FAMILY_R600) - return aper_size; - - /* Set HDP_APER_CNTL only on cards that are known not to be broken, - * that is has the 2nd generation multifunction PCI interface - */ - if (info->ChipFamily == CHIP_FAMILY_RV280 || - info->ChipFamily == CHIP_FAMILY_RV350 || - info->ChipFamily == CHIP_FAMILY_RV380 || - info->ChipFamily == CHIP_FAMILY_R420 || - info->ChipFamily == CHIP_FAMILY_RV410 || - IS_AVIVO_VARIANT) { - OUTREGP (RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL, - ~RADEON_HDP_APER_CNTL); - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Generation 2 PCI interface, using max accessible memory\n"); - return aper_size * 2; - } - - /* Older cards have all sorts of funny issues to deal with. First - * check if it's a multifunction card by reading the PCI config - * header type... Limit those to one aperture size - */ - PCI_READ_BYTE(info->PciInfo, &byte, 0xe); - if (byte & 0x80) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Generation 1 PCI interface in multifunction mode" - ", accessible memory limited to one aperture\n"); - return aper_size; - } - - /* Single function older card. We read HDP_APER_CNTL to see how the BIOS - * have set it up. We don't write this as it's broken on some ASICs but - * we expect the BIOS to have done the right thing (might be too optimistic...) - */ - if (INREG(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL) - return aper_size * 2; - - return aper_size; -} - -static Bool RADEONPreInitVRAM(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - EntityInfoPtr pEnt = info->pEnt; - GDevPtr dev = pEnt->device; - unsigned char *RADEONMMIO = info->MMIO; - MessageType from = X_PROBED; - uint32_t accessible, bar_size; - - if ((!IS_AVIVO_VARIANT) && info->IsIGP) { - uint32_t tom = INREG(RADEON_NB_TOM); - - pScrn->videoRam = (((tom >> 16) - - (tom & 0xffff) + 1) << 6); - - OUTREG(RADEON_CONFIG_MEMSIZE, pScrn->videoRam * 1024); - } else { - if (info->ChipFamily >= CHIP_FAMILY_PALM) - /* R600_CONFIG_MEMSIZE is bytes on fusion */ - pScrn->videoRam = INREG(R600_CONFIG_MEMSIZE) / 1024; - else if (info->ChipFamily >= CHIP_FAMILY_CEDAR) - /* R600_CONFIG_MEMSIZE is MB on evergreen */ - /* XXX watch for overflow!!! */ - pScrn->videoRam = INREG(R600_CONFIG_MEMSIZE) * 1024; - else if (info->ChipFamily >= CHIP_FAMILY_R600) - pScrn->videoRam = INREG(R600_CONFIG_MEMSIZE) / 1024; - else { - /* Read VRAM size from card */ - pScrn->videoRam = INREG(RADEON_CONFIG_MEMSIZE) / 1024; - - /* Some production boards of m6 will return 0 if it's 8 MB */ - if (pScrn->videoRam == 0) { - pScrn->videoRam = 8192; - OUTREG(RADEON_CONFIG_MEMSIZE, 0x800000); - } - } - } - - /* Get accessible memory */ - accessible = RADEONGetAccessibleVRAM(pScrn); - - /* Crop it to the size of the PCI BAR */ - bar_size = PCI_REGION_SIZE(info->PciInfo, 0) / 1024; - if (bar_size == 0) - bar_size = 0x20000; - if (accessible > bar_size) - accessible = bar_size; - - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Detected total video RAM=%dK, accessible=%uK (PCI BAR=%uK)\n", - pScrn->videoRam, (unsigned)accessible, (unsigned)bar_size); - if (pScrn->videoRam > accessible) - pScrn->videoRam = accessible; - - if (!IS_AVIVO_VARIANT) { - info->MemCntl = INREG(RADEON_SDRAM_MODE_REG); - info->BusCntl = INREG(RADEON_BUS_CNTL); - } - - RADEONGetVRamType(pScrn); - - if (dev->videoRam) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Video RAM override, using %d kB instead of %d kB\n", - dev->videoRam, - pScrn->videoRam); - from = X_CONFIG; - pScrn->videoRam = dev->videoRam; - } - - xf86DrvMsg(pScrn->scrnIndex, from, - "Mapped VideoRAM: %d kByte (%d bit %s SDRAM)\n", pScrn->videoRam, info->RamWidth, info->IsDDR?"DDR":"SDR"); - - /* Do this before we truncate since we only map fb once */ - info->FbMapSize = (pScrn->videoRam & ~1023) * 1024; - - if (info->IsPrimary) { - pScrn->videoRam /= 2; - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Using %dk of videoram for primary head\n", - pScrn->videoRam); - } else if (info->IsSecondary) { - pScrn->videoRam /= 2; - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Using %dk of videoram for secondary head\n", - pScrn->videoRam); - } - pScrn->videoRam &= ~1023; - - /* if the card is PCI Express reserve the last 32k for the gart table */ -#ifdef XF86DRI - if (info->cardType == CARD_PCIE && info->directRenderingEnabled) - /* work out the size of pcie aperture */ - info->FbSecureSize = RADEONDRIGetPciAperTableSize(pScrn); - else -#endif - info->FbSecureSize = 0; - - return TRUE; -} - - -/* This is called by RADEONPreInit to handle config file overrides for - * things like chipset and memory regions. Also determine memory size - * and type. If memory type ever needs an override, put it in this - * routine. - */ -static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); - EntityInfoPtr pEnt = info->pEnt; - GDevPtr dev = pEnt->device; - unsigned char *RADEONMMIO = info->MMIO; - MessageType from = X_PROBED; - int i; -#ifdef XF86DRI - const char *s; - uint32_t cmd_stat; -#endif - - /* Chipset */ - from = X_PROBED; - if (dev->chipset && *dev->chipset) { - info->Chipset = xf86StringToToken(RADEONChipsets, dev->chipset); - from = X_CONFIG; - } else if (dev->chipID >= 0) { - info->Chipset = dev->chipID; - from = X_CONFIG; - } else { - info->Chipset = PCI_DEV_DEVICE_ID(info->PciInfo); - } - - pScrn->chipset = (char *)xf86TokenToString(RADEONChipsets, info->Chipset); - if (!pScrn->chipset) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "ChipID 0x%04x is not recognized\n", info->Chipset); - return FALSE; - } - if (info->Chipset < 0) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Chipset \"%s\" is not recognized\n", pScrn->chipset); - return FALSE; - } - xf86DrvMsg(pScrn->scrnIndex, from, - "Chipset: \"%s\" (ChipID = 0x%04x)\n", - pScrn->chipset, - info->Chipset); - - pRADEONEnt->HasCRTC2 = TRUE; - info->IsMobility = FALSE; - info->IsIGP = FALSE; - info->IsDellServer = FALSE; - info->HasSingleDAC = FALSE; - info->InternalTVOut = TRUE; - info->get_hardcoded_edid_from_bios = FALSE; - - for (i = 0; i < sizeof(RADEONCards) / sizeof(RADEONCardInfo); i++) { - if (info->Chipset == RADEONCards[i].pci_device_id) { - RADEONCardInfo *card = &RADEONCards[i]; - info->ChipFamily = card->chip_family; - info->IsMobility = card->mobility; - info->IsIGP = card->igp; - pRADEONEnt->HasCRTC2 = !card->nocrtc2; - info->HasSingleDAC = card->singledac; - info->InternalTVOut = !card->nointtvout; - break; - } - } - - if (info->ChipFamily >= CHIP_FAMILY_SUMO) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Chipset: \"%s\" (ChipID = 0x%04x) requires KMS\n", - pScrn->chipset, - info->Chipset); - return FALSE; - } - - switch (info->Chipset) { - case PCI_CHIP_RN50_515E: /* RN50 is based on the RV100 but 3D isn't guaranteed to work. YMMV. */ - case PCI_CHIP_RN50_5969: - /* Some Sun servers have a hardcoded edid so KVMs work properly */ - if ((PCI_SUB_VENDOR_ID(info->PciInfo) == 0x108e) && - (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x4133)) - info->get_hardcoded_edid_from_bios = TRUE; - case PCI_CHIP_RV100_QY: - case PCI_CHIP_RV100_QZ: - /* DELL triple-head configuration. */ - if (((PCI_SUB_VENDOR_ID(info->PciInfo) == PCI_VENDOR_DELL) && - ((PCI_SUB_DEVICE_ID(info->PciInfo) == 0x016c) || - (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x016d) || - (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x016e) || - (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x016f) || - (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x0170) || - (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x017d) || - (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x017e) || - (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x0183) || - (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x018a) || - (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x019a) || - (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x01b1) || - (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x01b2) || - (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x0205))) || - ((PCI_SUB_VENDOR_ID(info->PciInfo) == PCI_VENDOR_HP) && - (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x31fb))) { - info->IsDellServer = TRUE; - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "DELL/HP server detected, force to special setup\n"); - } - break; - case PCI_CHIP_RS482_5974: - /* RH BZ 444586 - non mobility version - * Dell appear to have the Vostro 1100 with a mobility part with the same pci-id */ - if ((PCI_SUB_VENDOR_ID(info->PciInfo) == 0x1462) && - (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x7141)) { - info->IsMobility = FALSE; - } - default: - break; - } - - from = X_PROBED; - info->LinearAddr = PCI_REGION_BASE(info->PciInfo, 0, REGION_MEM) & ~0x1ffffffULL; - pScrn->memPhysBase = info->LinearAddr; - if (dev->MemBase) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Linear address override, using 0x%016lx instead of 0x%016llx\n", - dev->MemBase, - info->LinearAddr); - info->LinearAddr = dev->MemBase; - from = X_CONFIG; - } else if (!info->LinearAddr) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "No valid linear framebuffer address\n"); - return FALSE; - } - xf86DrvMsg(pScrn->scrnIndex, from, - "Linear framebuffer at 0x%016llx\n", info->LinearAddr); - -#ifndef XSERVER_LIBPCIACCESS - /* BIOS */ - from = X_PROBED; - info->BIOSAddr = info->PciInfo->biosBase & 0xfffe0000; - if (info->BIOSAddr) { - xf86DrvMsg(pScrn->scrnIndex, from, - "BIOS at 0x%08lx\n", (unsigned long)info->BIOSAddr); - } -#endif - - /* Read registers used to determine options */ - /* Check chip errata */ - info->ChipErrata = 0; - - if (info->ChipFamily == CHIP_FAMILY_R300 && - (INREG(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) - == RADEON_CFG_ATI_REV_A11) - info->ChipErrata |= CHIP_ERRATA_R300_CG; - - if (info->ChipFamily == CHIP_FAMILY_RV200 || - info->ChipFamily == CHIP_FAMILY_RS200) - info->ChipErrata |= CHIP_ERRATA_PLL_DUMMYREADS; - - if (info->ChipFamily == CHIP_FAMILY_RV100 || - info->ChipFamily == CHIP_FAMILY_RS100 || - info->ChipFamily == CHIP_FAMILY_RS200) - info->ChipErrata |= CHIP_ERRATA_PLL_DELAY; - -#ifdef XF86DRI - /* AGP/PCI */ - /* Proper autodetection of an AGP capable device requires examining - * PCI config registers to determine if the device implements extended - * PCI capabilities, and then walking the capability list as indicated - * in the PCI 2.2 and AGP 2.0 specifications, to determine if AGP - * capability is present. The procedure is outlined as follows: - * - * 1) Test bit 4 (CAP_LIST) of the PCI status register of the device - * to determine wether or not this device implements any extended - * capabilities. If this bit is zero, then the device is a PCI 2.1 - * or earlier device and is not AGP capable, and we can conclude it - * to be a PCI device. - * - * 2) If bit 4 of the status register is set, then the device implements - * extended capabilities. There is an 8 bit wide capabilities pointer - * register located at offset 0x34 in PCI config space which points to - * the first capability in a linked list of extended capabilities that - * this device implements. The lower two bits of this register are - * reserved and MBZ so must be masked out. - * - * 3) The extended capabilities list is formed by one or more extended - * capabilities structures which are aligned on DWORD boundaries. - * The first byte of the structure is the capability ID (CAP_ID) - * indicating what extended capability this structure refers to. The - * second byte of the structure is an offset from the beginning of - * PCI config space pointing to the next capability in the linked - * list (NEXT_PTR) or NULL (0x00) at the end of the list. The lower - * two bits of this pointer are reserved and MBZ. By examining the - * CAP_ID of each capability and walking through the list, we will - * either find the AGP_CAP_ID (0x02) indicating this device is an - * AGP device, or we'll reach the end of the list, indicating it is - * a PCI device. - * - * Mike A. Harris <mharris@redhat.com> - * - * References: - * - PCI Local Bus Specification Revision 2.2, Chapter 6 - * - AGP Interface Specification Revision 2.0, Section 6.1.5 - */ - - info->cardType = CARD_PCI; - - PCI_READ_LONG(info->PciInfo, &cmd_stat, PCI_CMD_STAT_REG); - if (cmd_stat & RADEON_CAP_LIST) { - uint32_t cap_ptr, cap_id; - - PCI_READ_LONG(info->PciInfo, &cap_ptr, RADEON_CAPABILITIES_PTR_PCI_CONFIG); - cap_ptr &= RADEON_CAP_PTR_MASK; - - while(cap_ptr != RADEON_CAP_ID_NULL) { - PCI_READ_LONG(info->PciInfo, &cap_id, cap_ptr); - if ((cap_id & 0xff)== RADEON_CAP_ID_AGP) { - info->cardType = CARD_AGP; - break; - } - if ((cap_id & 0xff)== RADEON_CAP_ID_EXP) { - info->cardType = CARD_PCIE; - break; - } - cap_ptr = (cap_id >> 8) & RADEON_CAP_PTR_MASK; - } - } - - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "%s card detected\n", - (info->cardType==CARD_PCI) ? "PCI" : - (info->cardType==CARD_PCIE) ? "PCIE" : "AGP"); - - /* treat PCIE IGP cards as PCI */ - if (info->cardType == CARD_PCIE && info->IsIGP) - info->cardType = CARD_PCI; - - /* some rs4xx cards report as agp */ - if ((info->ChipFamily == CHIP_FAMILY_RS400) || - (info->ChipFamily == CHIP_FAMILY_RS480)) - info->cardType = CARD_PCI; - - if ((info->ChipFamily >= CHIP_FAMILY_R600) && info->IsIGP) - info->cardType = CARD_PCIE; - - /* not sure about gart table requirements */ - if ((info->ChipFamily == CHIP_FAMILY_RS600) && info->IsIGP) - info->cardType = CARD_PCIE; - - if ((s = xf86GetOptValString(info->Options, OPTION_BUS_TYPE))) { - if (strcmp(s, "AGP") == 0) { - info->cardType = CARD_AGP; - xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Forced into AGP mode\n"); - } else if ((strcmp(s, "PCI") == 0) || - (strcmp(s, "PCIE") == 0)) { - if ((info->ChipFamily == CHIP_FAMILY_RS400) || - (info->ChipFamily == CHIP_FAMILY_RS480) || - (info->ChipFamily == CHIP_FAMILY_RS690) || - (info->ChipFamily == CHIP_FAMILY_RS740)) { - info->cardType = CARD_PCI; - xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Forced into PCI mode\n"); - } else if (info->ChipFamily >= CHIP_FAMILY_RV380) { - info->cardType = CARD_PCIE; - xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Forced into PCI Express mode\n"); - } else { - info->cardType = CARD_PCI; - xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Forced into PCI mode\n"); - } - } else { - xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, - "Invalid BusType option, using detected type\n"); - } - } -#endif -#ifdef RENDER - info->RenderAccel = xf86ReturnOptValBool(info->Options, OPTION_RENDER_ACCEL, - info->Chipset != PCI_CHIP_RN50_515E && - info->Chipset != PCI_CHIP_RN50_5969); -#endif - - info->r4xx_atom = FALSE; - if (((info->ChipFamily == CHIP_FAMILY_R420) || (info->ChipFamily == CHIP_FAMILY_RV410)) && - xf86ReturnOptValBool(info->Options, OPTION_R4XX_ATOM, FALSE)) { - info->r4xx_atom = TRUE; - xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Using ATOMBIOS for R4xx chip\n"); - } - - return TRUE; -} - - -static void RADEONPreInitDDC(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - /* vbeInfoPtr pVbe; */ - - info->ddc1 = FALSE; - info->ddc_bios = FALSE; - if (!xf86LoadSubModule(pScrn, "ddc")) { - info->ddc2 = FALSE; - } else { - info->ddc2 = TRUE; - } - - /* DDC can use I2C bus */ - /* Load I2C if we have the code to use it */ - if (info->ddc2) { - xf86LoadSubModule(pScrn, "i2c"); - } -} - -/* This is called by RADEONPreInit to initialize gamma correction */ -static Bool RADEONPreInitGamma(ScrnInfoPtr pScrn) -{ - Gamma zeros = { 0.0, 0.0, 0.0 }; - - if (!xf86SetGamma(pScrn, zeros)) return FALSE; - return TRUE; -} - -/* This is called by RADEONPreInit to initialize the hardware cursor */ -static Bool RADEONPreInitCursor(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - - if (!xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) { - if (!xf86LoadSubModule(pScrn, "ramdac")) return FALSE; - } - return TRUE; -} - -/* This is called by RADEONPreInit to initialize hardware acceleration */ -static Bool RADEONPreInitAccel(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - MessageType from; -#if defined(USE_EXA) && defined(USE_XAA) - char *optstr; -#endif -#ifdef XF86DRI /* zaphod FbMapSize is wrong, but no dri then */ - int maxy = info->FbMapSize / (pScrn->displayWidth * info->CurrentLayout.pixel_bytes); -#endif - - if (!(info->accel_state = calloc(1, sizeof(struct radeon_accel_state)))) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unable to allocate accel_state rec!\n"); - return FALSE; - } - info->accel_state->fifo_slots = 0; - - if ((info->ChipFamily == CHIP_FAMILY_RS100) || - (info->ChipFamily == CHIP_FAMILY_RS200) || - (info->ChipFamily == CHIP_FAMILY_RS300) || - (info->ChipFamily == CHIP_FAMILY_RS400) || - (info->ChipFamily == CHIP_FAMILY_RS480) || - (info->ChipFamily == CHIP_FAMILY_RS600) || - (info->ChipFamily == CHIP_FAMILY_RS690) || - (info->ChipFamily == CHIP_FAMILY_RS740)) - info->accel_state->has_tcl = FALSE; - else { - info->accel_state->has_tcl = TRUE; - } - - /* if we have shadow fb bail */ - if (info->r600_shadow_fb) { - info->useEXA = FALSE; - return TRUE; - } - -#ifdef XF86DRI - if ((!info->directRenderingEnabled) || - (maxy <= pScrn->virtualY * 3) || - (pScrn->videoRam <= 32768)) - info->useEXA = FALSE; - else - info->useEXA = TRUE; -#else - info->useEXA = FALSE; -#endif - - if (!xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) { - int errmaj = 0, errmin = 0; - - from = X_DEFAULT; -#if defined(USE_EXA) -#if defined(USE_XAA) - optstr = (char *)xf86GetOptValString(info->Options, OPTION_ACCELMETHOD); - if (optstr != NULL) { - if (xf86NameCmp(optstr, "EXA") == 0) { - from = X_CONFIG; - info->useEXA = TRUE; - } else if (xf86NameCmp(optstr, "XAA") == 0) { - from = X_CONFIG; - if (info->ChipFamily < CHIP_FAMILY_R600) - info->useEXA = FALSE; - } - } -#else /* USE_XAA */ - info->useEXA = TRUE; -#endif /* !USE_XAA */ -#else - info->useEXA = FALSE; -#endif /* USE_EXA */ - if (info->ChipFamily < CHIP_FAMILY_R600) - xf86DrvMsg(pScrn->scrnIndex, from, - "Using %s acceleration architecture\n", - info->useEXA ? "EXA" : "XAA"); - else - xf86DrvMsg(pScrn->scrnIndex, X_DEFAULT, - "Will attempt to use R6xx/R7xx EXA support if DRI is enabled.\n"); - -#ifdef USE_EXA - if (info->useEXA) { - info->exaReq.majorversion = EXA_VERSION_MAJOR; - info->exaReq.minorversion = EXA_VERSION_MINOR; - - if (!LoadSubModule(pScrn->module, "exa", NULL, NULL, NULL, - &info->exaReq, &errmaj, &errmin)) { - LoaderErrorMsg(NULL, "exa", errmaj, errmin); - return FALSE; - } - } -#endif /* USE_EXA */ -#ifdef USE_XAA - if (!info->useEXA) { - info->xaaReq.majorversion = 1; - info->xaaReq.minorversion = 2; - - if (!LoadSubModule(pScrn->module, "xaa", NULL, NULL, NULL, - &info->xaaReq, &errmaj, &errmin)) { - info->xaaReq.minorversion = 1; - - if (!LoadSubModule(pScrn->module, "xaa", NULL, NULL, NULL, - &info->xaaReq, &errmaj, &errmin)) { - info->xaaReq.minorversion = 0; - - if (!LoadSubModule(pScrn->module, "xaa", NULL, NULL, NULL, - &info->xaaReq, &errmaj, &errmin)) { - LoaderErrorMsg(NULL, "xaa", errmaj, errmin); - return FALSE; - } - } - } - } -#endif /* USE_XAA */ - } else { - /* NoAccel */ - info->useEXA = FALSE; - } - - return TRUE; -} - -static Bool RADEONPreInitInt10(ScrnInfoPtr pScrn, xf86Int10InfoPtr *ppInt10) -{ -#if (!defined(__powerpc__) && !defined(__sparc__)) || \ - (defined(XSERVER_LIBPCIACCESS) && HAVE_PCI_DEVICE_ENABLE) - RADEONInfoPtr info = RADEONPTR(pScrn); -#endif -#if !defined(__powerpc__) && !defined(__sparc__) - unsigned char *RADEONMMIO = info->MMIO; - uint32_t fp2_gen_ctl_save = 0; -#endif - -#ifdef XSERVER_LIBPCIACCESS -#if HAVE_PCI_DEVICE_ENABLE - pci_device_enable(info->PciInfo); -#endif -#endif - -#if !defined(__powerpc__) && !defined(__sparc__) - /* don't need int10 on atom cards. - * in theory all radeons, but the older stuff - * isn't 100% yet - * secondary atom cards tend to hang when initializing int10, - * however, on some stom cards, you can't read the bios without - * intitializing int10. - */ - if (!xf86ReturnOptValBool(info->Options, OPTION_INT10, TRUE)) - return TRUE; - - if (xf86LoadSubModule(pScrn, "int10")) { - /* The VGA BIOS on the RV100/QY cannot be read when the digital output - * is enabled. Clear and restore FP2_ON around int10 to avoid this. - */ - if (PCI_DEV_DEVICE_ID(info->PciInfo) == PCI_CHIP_RV100_QY) { - fp2_gen_ctl_save = INREG(RADEON_FP2_GEN_CNTL); - if (fp2_gen_ctl_save & RADEON_FP2_ON) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "disabling digital out\n"); - OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_ctl_save & ~RADEON_FP2_ON); - } - } - - xf86DrvMsg(pScrn->scrnIndex,X_INFO,"initializing int10\n"); - *ppInt10 = xf86InitInt10(info->pEnt->index); - - if (PCI_DEV_DEVICE_ID(info->PciInfo) == PCI_CHIP_RV100_QY) { - if (fp2_gen_ctl_save & RADEON_FP2_ON) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "re-enabling digital out\n"); - OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_ctl_save); - } - } - } -#endif - return TRUE; -} - -#ifdef XF86DRI -static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - Bool ret; - MessageType from; - char *reason; - - info->directRenderingEnabled = FALSE; - info->directRenderingInited = FALSE; - - if (!(info->dri = calloc(1, sizeof(struct radeon_dri)))) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Unable to allocate dri rec!\n"); - return FALSE; - } - - if (!(info->cp = calloc(1, sizeof(struct radeon_cp)))) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Unable to allocate cp rec!\n"); - return FALSE; - } - info->cp->CPInUse = FALSE; - info->cp->CPStarted = FALSE; - info->cp->CPusecTimeout = RADEON_DEFAULT_CP_TIMEOUT; - - if (xf86IsEntityShared(info->pEnt->index)) { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "Direct Rendering Disabled -- " - "Zaphod Dual-head configuration is not working with " - "DRI at present.\n" - "Please use the xrandr 1.2 if you " - "want Dual-head with DRI.\n"); - return FALSE; - } - if (info->IsSecondary) - return FALSE; - - if (info->ChipFamily >= CHIP_FAMILY_CEDAR) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "No DRI yet on Evergreen\n"); - return FALSE; - } - - if (info->Chipset == PCI_CHIP_RN50_515E || - info->Chipset == PCI_CHIP_RN50_5969) { - if (xf86ReturnOptValBool(info->Options, OPTION_DRI, FALSE)) { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "Direct rendering for RN50 forced on -- " - "This is NOT officially supported at the hardware level " - "and may cause instability or lockups\n"); - } else { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Direct rendering not officially supported on RN50\n"); - return FALSE; - } - } - - if (!xf86ReturnOptValBool(info->Options, OPTION_DRI, TRUE)) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Direct rendering forced off\n"); - return FALSE; - } - - if (xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "[dri] Acceleration disabled, not initializing the DRI\n"); - return FALSE; - } - - info->dri->pLibDRMVersion = NULL; - info->dri->pKernelDRMVersion = NULL; - - ret = RADEONDRIGetVersion(pScrn); - if (ret <= 0) - return ret; - - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "[dri] Found DRI library version %d.%d.%d and kernel" - " module version %d.%d.%d\n", - info->dri->pLibDRMVersion->version_major, - info->dri->pLibDRMVersion->version_minor, - info->dri->pLibDRMVersion->version_patchlevel, - info->dri->pKernelDRMVersion->version_major, - info->dri->pKernelDRMVersion->version_minor, - info->dri->pKernelDRMVersion->version_patchlevel); - - if (info->Chipset == PCI_CHIP_RS400_5A41 || - info->Chipset == PCI_CHIP_RS400_5A42 || - info->Chipset == PCI_CHIP_RC410_5A61 || - info->Chipset == PCI_CHIP_RC410_5A62 || - info->Chipset == PCI_CHIP_RS480_5954 || - info->Chipset == PCI_CHIP_RS480_5955 || - info->Chipset == PCI_CHIP_RS482_5974 || - info->Chipset == PCI_CHIP_RS485_5975) { - - if (info->dri->pKernelDRMVersion->version_minor < 27) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Direct rendering broken on XPRESS 200 and 200M with DRI less than 1.27\n"); - return FALSE; - } - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Direct rendering experimental on RS400/Xpress 200 enabled\n"); - } - - if (info->ChipFamily >= CHIP_FAMILY_R300) - info->dri->gartSize = R300_DEFAULT_GART_SIZE; - else - info->dri->gartSize = RADEON_DEFAULT_GART_SIZE; - - info->dri->ringSize = RADEON_DEFAULT_RING_SIZE; - info->dri->bufSize = RADEON_DEFAULT_BUFFER_SIZE; - info->dri->gartTexSize = RADEON_DEFAULT_GART_TEX_SIZE; - info->dri->pciAperSize = RADEON_DEFAULT_PCI_APER_SIZE; - info->cp->CPusecTimeout = RADEON_DEFAULT_CP_TIMEOUT; - - if ((xf86GetOptValInteger(info->Options, - OPTION_GART_SIZE, (int *)&(info->dri->gartSize))) || - (xf86GetOptValInteger(info->Options, - OPTION_GART_SIZE_OLD, (int *)&(info->dri->gartSize)))) { - switch (info->dri->gartSize) { - case 4: - case 8: - case 16: - case 32: - case 64: - case 128: - case 256: - break; - - default: - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Illegal GART size: %d MB\n", info->dri->gartSize); - return FALSE; - } - } - - if (xf86GetOptValInteger(info->Options, - OPTION_RING_SIZE, &(info->dri->ringSize))) { - if (info->dri->ringSize < 1 || info->dri->ringSize >= (int)info->dri->gartSize) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Illegal ring buffer size: %d MB\n", - info->dri->ringSize); - return FALSE; - } - } - - if (xf86GetOptValInteger(info->Options, - OPTION_PCIAPER_SIZE, &(info->dri->pciAperSize))) { - switch(info->dri->pciAperSize) { - case 32: - case 64: - case 128: - case 256: - break; - default: - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Illegal pci aper size: %d MB\n", - info->dri->pciAperSize); - return FALSE; - } - } - - - if (xf86GetOptValInteger(info->Options, - OPTION_BUFFER_SIZE, &(info->dri->bufSize))) { - if (info->dri->bufSize < 1 || info->dri->bufSize >= (int)info->dri->gartSize) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Illegal vertex/indirect buffers size: %d MB\n", - info->dri->bufSize); - return FALSE; - } - if (info->dri->bufSize > 2) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Illegal vertex/indirect buffers size: %d MB\n", - info->dri->bufSize); - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Clamping vertex/indirect buffers size to 2 MB\n"); - info->dri->bufSize = 2; - } - } - - if (info->dri->ringSize + info->dri->bufSize + info->dri->gartTexSize > - (int)info->dri->gartSize) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Buffers are too big for requested GART space\n"); - return FALSE; - } - - info->dri->gartTexSize = info->dri->gartSize - (info->dri->ringSize + info->dri->bufSize); - - if (xf86GetOptValInteger(info->Options, OPTION_USEC_TIMEOUT, - &(info->cp->CPusecTimeout))) { - /* This option checked by the RADEON DRM kernel module */ - } - - /* Two options to try and squeeze as much texture memory as possible - * for dedicated 3d rendering boxes - */ - info->dri->noBackBuffer = xf86ReturnOptValBool(info->Options, - OPTION_NO_BACKBUFFER, - FALSE); - - info->dri->allowPageFlip = 0; - -#ifdef DAMAGE - if (info->dri->noBackBuffer) { - from = X_DEFAULT; - reason = " because back buffer disabled"; - } else { - from = xf86GetOptValBool(info->Options, OPTION_PAGE_FLIP, - &info->dri->allowPageFlip) ? X_CONFIG : X_DEFAULT; - - if (IS_AVIVO_VARIANT) { - info->dri->allowPageFlip = 0; - reason = " on r5xx and newer chips.\n"; - } else { - reason = ""; - } - - } -#else - from = X_DEFAULT; - reason = " because Damage layer not available at build time"; -#endif - - xf86DrvMsg(pScrn->scrnIndex, from, "Page Flipping %sabled%s\n", - info->dri->allowPageFlip ? "en" : "dis", reason); - - /* AGP seems to have problems with gart transfers */ - if ((info->ChipFamily >= CHIP_FAMILY_R600) && (info->cardType == CARD_AGP)) - info->DMAForXv = FALSE; - else - info->DMAForXv = TRUE; - from = xf86GetOptValBool(info->Options, OPTION_XV_DMA, &info->DMAForXv) - ? X_CONFIG : X_INFO; - xf86DrvMsg(pScrn->scrnIndex, from, - "Will %stry to use DMA for Xv image transfers\n", - info->DMAForXv ? "" : "not "); - - return TRUE; -} -#endif /* XF86DRI */ - -static void RADEONPreInitColorTiling(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - - info->allowColorTiling = xf86ReturnOptValBool(info->Options, - OPTION_COLOR_TILING, TRUE); - if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { - /* this may be 4096 on r4xx -- need to double check */ - info->MaxSurfaceWidth = 3968; /* one would have thought 4096...*/ - info->MaxLines = 4096; - } else { - info->MaxSurfaceWidth = 2048; - info->MaxLines = 2048; - } - - if (!info->allowColorTiling) - return; - - if (info->ChipFamily >= CHIP_FAMILY_R600) - info->allowColorTiling = FALSE; - - /* for zaphod disable tiling for now */ - if (info->IsPrimary || info->IsSecondary) - info->allowColorTiling = FALSE; - -#ifdef XF86DRI - if (info->directRenderingEnabled && - info->dri->pKernelDRMVersion->version_minor < 14) { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "[dri] color tiling disabled because of version " - "mismatch.\n" - "[dri] radeon.o kernel module version is %d.%d.%d but " - "1.14.0 or later is required for color tiling.\n", - info->dri->pKernelDRMVersion->version_major, - info->dri->pKernelDRMVersion->version_minor, - info->dri->pKernelDRMVersion->version_patchlevel); - info->allowColorTiling = FALSE; - return; - } -#endif /* XF86DRI */ - - if (info->allowColorTiling) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Color tiling enabled by default\n"); - } else { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Color tiling disabled\n"); - } -} - - -static Bool RADEONPreInitXv(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - uint16_t mm_table; - uint16_t bios_header; - uint16_t pll_info_block; -#ifdef XvExtension - char* microc_path = NULL; - char* microc_type = NULL; - MessageType from; - - if (xf86GetOptValInteger(info->Options, OPTION_VIDEO_KEY, - &(info->videoKey))) { - xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "video key set to 0x%x\n", - info->videoKey); - } else { - info->videoKey = 0x1E; - } - - if(xf86GetOptValInteger(info->Options, OPTION_RAGE_THEATRE_CRYSTAL, &(info->RageTheatreCrystal))) { - xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre Crystal frequency was specified as %d.%d Mhz\n", - info->RageTheatreCrystal/100, info->RageTheatreCrystal % 100); - } else { - info->RageTheatreCrystal=-1; - } - - if(xf86GetOptValInteger(info->Options, OPTION_RAGE_THEATRE_TUNER_PORT, &(info->RageTheatreTunerPort))) { - xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre tuner port was specified as %d\n", - info->RageTheatreTunerPort); - } else { - info->RageTheatreTunerPort=-1; - } - - if(info->RageTheatreTunerPort>5){ - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Attempt to assign Rage Theatre tuner port to invalid value. Disabling setting\n"); - info->RageTheatreTunerPort=-1; - } - - if(xf86GetOptValInteger(info->Options, OPTION_RAGE_THEATRE_COMPOSITE_PORT, &(info->RageTheatreCompositePort))) { - xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre composite port was specified as %d\n", - info->RageTheatreCompositePort); - } else { - info->RageTheatreCompositePort=-1; - } - - if(info->RageTheatreCompositePort>6){ - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Attempt to assign Rage Theatre composite port to invalid value. Disabling setting\n"); - info->RageTheatreCompositePort=-1; - } - - if(xf86GetOptValInteger(info->Options, OPTION_RAGE_THEATRE_SVIDEO_PORT, &(info->RageTheatreSVideoPort))) { - xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre SVideo Port was specified as %d\n", - info->RageTheatreSVideoPort); - } else { - info->RageTheatreSVideoPort=-1; - } - - if(info->RageTheatreSVideoPort>6){ - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Attempt to assign Rage Theatre SVideo port to invalid value. Disabling setting\n"); - info->RageTheatreSVideoPort=-1; - } - - if(xf86GetOptValInteger(info->Options, OPTION_TUNER_TYPE, &(info->tunerType))) { - xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Tuner type was specified as %d\n", - info->tunerType); - } else { - info->tunerType=-1; - } - - if(info->tunerType>31){ - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Attempt to set tuner type to invalid value. Disabling setting\n"); - info->tunerType=-1; - } - - if((microc_path = xf86GetOptValString(info->Options, OPTION_RAGE_THEATRE_MICROC_PATH)) != NULL) - { - xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre Microcode path was specified as %s\n", microc_path); - info->RageTheatreMicrocPath = microc_path; - } else { - info->RageTheatreMicrocPath= NULL; - } - - if((microc_type = xf86GetOptValString(info->Options, OPTION_RAGE_THEATRE_MICROC_TYPE)) != NULL) - { - xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre Microcode type was specified as %s\n", microc_type); - info->RageTheatreMicrocType = microc_type; - } else { - info->RageTheatreMicrocType= NULL; - } - - if(xf86GetOptValInteger(info->Options, OPTION_SCALER_WIDTH, &(info->overlay_scaler_buffer_width))) { - if ((info->overlay_scaler_buffer_width < 1024) || - (info->overlay_scaler_buffer_width > 2048) || - ((info->overlay_scaler_buffer_width % 64) != 0)) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Attempt to set illegal scaler width. Using default\n"); - from = X_DEFAULT; - info->overlay_scaler_buffer_width = 0; - } else - from = X_CONFIG; - } else { - from = X_DEFAULT; - info->overlay_scaler_buffer_width = 0; - } - if (!info->overlay_scaler_buffer_width) { - /* overlay scaler line length differs for different revisions - this needs to be maintained by hand */ - switch(info->ChipFamily){ - case CHIP_FAMILY_R200: - case CHIP_FAMILY_R300: - case CHIP_FAMILY_R350: - case CHIP_FAMILY_RV350: - case CHIP_FAMILY_RV380: - case CHIP_FAMILY_R420: - case CHIP_FAMILY_RV410: - info->overlay_scaler_buffer_width = 1920; - break; - default: - info->overlay_scaler_buffer_width = 1536; - } - } - xf86DrvMsg(pScrn->scrnIndex, from, "Assuming overlay scaler buffer width is %d\n", - info->overlay_scaler_buffer_width); -#endif - - /* Rescue MM_TABLE before VBIOS is freed */ - info->MM_TABLE_valid = FALSE; - - if((info->VBIOS==NULL)||(info->VBIOS[0]!=0x55)||(info->VBIOS[1]!=0xaa)){ - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Cannot access BIOS or it is not valid.\n" - "\t\tIf your card is TV-in capable you will need to specify options RageTheatreCrystal, RageTheatreTunerPort, \n" - "\t\tRageTheatreSVideoPort and TunerType in /etc/X11/xorg.conf.\n" - ); - info->MM_TABLE_valid = FALSE; - return TRUE; - } - - bios_header=info->VBIOS[0x48]; - bios_header+=(((int)info->VBIOS[0x49]+0)<<8); - - mm_table=info->VBIOS[bios_header+0x38]; - if(mm_table==0) - { - xf86DrvMsg(pScrn->scrnIndex,X_INFO,"No MM_TABLE found - assuming CARD is not TV-in capable.\n"); - info->MM_TABLE_valid = FALSE; - return TRUE; - } - mm_table+=(((int)info->VBIOS[bios_header+0x39]+0)<<8)-2; - - if(mm_table>0) - { - memcpy(&(info->MM_TABLE), &(info->VBIOS[mm_table]), sizeof(info->MM_TABLE)); - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "MM_TABLE: %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n", - info->MM_TABLE.table_revision, - info->MM_TABLE.table_size, - info->MM_TABLE.tuner_type, - info->MM_TABLE.audio_chip, - info->MM_TABLE.product_id, - info->MM_TABLE.tuner_voltage_teletext_fm, - info->MM_TABLE.i2s_config, - info->MM_TABLE.video_decoder_type, - info->MM_TABLE.video_decoder_host_config, - info->MM_TABLE.input[0], - info->MM_TABLE.input[1], - info->MM_TABLE.input[2], - info->MM_TABLE.input[3], - info->MM_TABLE.input[4]); - - /* Is it an MM_TABLE we know about ? */ - if(info->MM_TABLE.table_size != 0xc){ - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "This card has MM_TABLE we do not recognize.\n" - "\t\tIf your card is TV-in capable you will need to specify options RageTheatreCrystal, RageTheatreTunerPort, \n" - "\t\tRageTheatreSVideoPort and TunerType in /etc/X11/xorg.conf.\n" - ); - info->MM_TABLE_valid = FALSE; - return TRUE; - } - info->MM_TABLE_valid = TRUE; - } else { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "No MM_TABLE found - assuming card is not TV-in capable (mm_table=%d).\n", mm_table); - info->MM_TABLE_valid = FALSE; - } - - pll_info_block=info->VBIOS[bios_header+0x30]; - pll_info_block+=(((int)info->VBIOS[bios_header+0x31]+0)<<8); - - info->video_decoder_type=info->VBIOS[pll_info_block+0x08]; - info->video_decoder_type+=(((int)info->VBIOS[pll_info_block+0x09]+0)<<8); - - return TRUE; -} - -static Bool -RADEONPreInitBIOS(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - - if (!RADEONGetBIOSInfo(pScrn, pInt10)) { - /* Avivo chips require bios for atom */ - if (IS_AVIVO_VARIANT) - return FALSE; - } - return TRUE; -} - Bool RADEONZaphodStringMatches(ScrnInfoPtr pScrn, const char *s, char *output_name) { @@ -2836,7 +244,7 @@ RADEONZaphodStringMatches(ScrnInfoPtr pScrn, const char *s, char *output_name) do { switch(*s) { case ',': - s1[i] = '\0'; + s1[i] = '\0'; i = 0; if (strcmp(s1, output_name) == 0) return TRUE; @@ -2860,3162 +268,6 @@ RADEONZaphodStringMatches(ScrnInfoPtr pScrn, const char *s, char *output_name) return FALSE; } -static void RADEONFixZaphodOutputs(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); - int o; - char *s; - - if ((s = xf86GetOptValString(info->Options, OPTION_ZAPHOD_HEADS))) { - for (o = config->num_output; o > 0; o--) { - if (!RADEONZaphodStringMatches(pScrn, s, config->output[o - 1]->name)) - xf86OutputDestroy(config->output[o - 1]); - } - } else { - if (info->IsPrimary) { - xf86OutputDestroy(config->output[0]); - while (config->num_output > 1) { - xf86OutputDestroy(config->output[1]); - } - } else { - while (config->num_output > 1) { - xf86OutputDestroy(config->output[1]); - } - } - } -} - -static Bool RADEONPreInitControllers(ScrnInfoPtr pScrn) -{ - xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); - RADEONInfoPtr info = RADEONPTR(pScrn); - int i; - int mask; - int found = 0; - - if (info->IsPrimary) - mask = 1; - else if (info->IsSecondary) - mask = 2; - else - mask = 3; - - if (!RADEONAllocateControllers(pScrn, mask)) - return FALSE; - - RADEONGetClockInfo(pScrn); - - if (info->IsAtomBios && info->IsIGP) - RADEONATOMGetIGPInfo(pScrn); - - if (!RADEONSetupConnectors(pScrn)) { - return FALSE; - } - - if (info->IsPrimary || info->IsSecondary) { - /* fixup outputs for zaphod */ - RADEONFixZaphodOutputs(pScrn); - } - - RADEONPrintPortMap(pScrn); - - info->first_load_no_devices = FALSE; - for (i = 0; i < config->num_output; i++) { - xf86OutputPtr output = config->output[i]; - - output->status = (*output->funcs->detect) (output); - ErrorF("finished output detect: %d\n", i); - if (info->IsPrimary || info->IsSecondary) { - if (output->status != XF86OutputStatusConnected) - return FALSE; - } - if (output->status != XF86OutputStatusDisconnected) - found++; - } - - if (!found) { - /* nothing connected, light up some defaults so the server comes up */ - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No connected devices found!\n"); - info->first_load_no_devices = TRUE; - } - - ErrorF("finished all detect\n"); - return TRUE; -} - -static void -RADEONProbeDDC(ScrnInfoPtr pScrn, int indx) -{ - vbeInfoPtr pVbe; - - if (xf86LoadSubModule(pScrn, "vbe")) { - pVbe = VBEInit(NULL,indx); - ConfiguredMonitor = vbeDoEDID(pVbe, NULL); - vbeFree(pVbe); - } -} - -static Bool -RADEONCRTCResize(ScrnInfoPtr scrn, int width, int height) -{ - scrn->virtualX = width; - scrn->virtualY = height; - /* RADEONSetPitch(scrn); */ - return TRUE; -} - -static const xf86CrtcConfigFuncsRec RADEONCRTCResizeFuncs = { - RADEONCRTCResize -}; - -Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) -{ - xf86CrtcConfigPtr xf86_config; - RADEONInfoPtr info; - xf86Int10InfoPtr pInt10 = NULL; - void *int10_save = NULL; - const char *s; - RADEONEntPtr pRADEONEnt; - DevUnion* pPriv; - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "RADEONPreInit\n"); - if (pScrn->numEntities != 1) return FALSE; - - if (!RADEONGetRec(pScrn)) return FALSE; - - info = RADEONPTR(pScrn); - info->MMIO = NULL; - - info->IsSecondary = FALSE; - info->IsPrimary = FALSE; - info->kms_enabled = FALSE; - - info->pEnt = xf86GetEntityInfo(pScrn->entityList[pScrn->numEntities - 1]); - if (info->pEnt->location.type != BUS_PCI) goto fail; - - pPriv = xf86GetEntityPrivate(pScrn->entityList[0], - getRADEONEntityIndex()); - pRADEONEnt = pPriv->ptr; - - if(xf86IsEntityShared(pScrn->entityList[0])) - { - if(xf86IsPrimInitDone(pScrn->entityList[0])) - { - info->IsSecondary = TRUE; - pRADEONEnt->pSecondaryScrn = pScrn; - info->SavedReg = &pRADEONEnt->SavedReg; - info->ModeReg = &pRADEONEnt->ModeReg; - } - else - { - info->IsPrimary = TRUE; - xf86SetPrimInitDone(pScrn->entityList[0]); - pRADEONEnt->pPrimaryScrn = pScrn; - pRADEONEnt->HasSecondary = FALSE; - info->SavedReg = &pRADEONEnt->SavedReg; - info->ModeReg = &pRADEONEnt->ModeReg; - } - } else { - info->SavedReg = &pRADEONEnt->SavedReg; - info->ModeReg = &pRADEONEnt->ModeReg; - } - - info->PciInfo = xf86GetPciInfoForEntity(info->pEnt->index); -#ifndef XSERVER_LIBPCIACCESS - info->PciTag = pciTag(PCI_DEV_BUS(info->PciInfo), - PCI_DEV_DEV(info->PciInfo), - PCI_DEV_FUNC(info->PciInfo)); -#endif - info->MMIOAddr = PCI_REGION_BASE(info->PciInfo, 2, REGION_MEM) & ~0xffULL; - info->MMIOSize = PCI_REGION_SIZE(info->PciInfo, 2); - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "TOTO SAYS %016llx\n", - (unsigned long long)PCI_REGION_BASE(info->PciInfo, - 2, REGION_MEM)); - if (info->pEnt->device->IOBase) { - xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, - "MMIO address override, using 0x%08lx instead of 0x%016llx\n", - info->pEnt->device->IOBase, - info->MMIOAddr); - info->MMIOAddr = info->pEnt->device->IOBase; - } else if (!info->MMIOAddr) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No valid MMIO address\n"); - goto fail1; - } - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "MMIO registers at 0x%016llx: size %ldKB\n", info->MMIOAddr, info->MMIOSize / 1024); - - if(!RADEONMapMMIO(pScrn)) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Memory map the MMIO region failed\n"); - goto fail1; - } - -#if !defined(__alpha__) - if ( -#ifndef XSERVER_LIBPCIACCESS - xf86GetPciDomain(info->PciTag) || -#endif - !xf86IsPrimaryPci(info->PciInfo)) - RADEONPreInt10Save(pScrn, &int10_save); -#else - /* [Alpha] On the primary, the console already ran the BIOS and we're - * going to run it again - so make sure to "fix up" the card - * so that (1) we can read the BIOS ROM and (2) the BIOS will - * get the memory config right. - */ - RADEONPreInt10Save(pScrn, &int10_save); -#endif - - if (flags & PROBE_DETECT) { - RADEONProbeDDC(pScrn, info->pEnt->index); - RADEONPostInt10Check(pScrn, int10_save); - if(info->MMIO) RADEONUnmapMMIO(pScrn); - return TRUE; - } - - - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "PCI bus %d card %d func %d\n", - PCI_DEV_BUS(info->PciInfo), - PCI_DEV_DEV(info->PciInfo), - PCI_DEV_FUNC(info->PciInfo)); - -#ifndef XSERVER_LIBPCIACCESS - if (xf86RegisterResources(info->pEnt->index, 0, ResExclusive)) - goto fail; - - xf86SetOperatingState(resVga, info->pEnt->index, ResUnusedOpr); - - pScrn->racMemFlags = RAC_FB | RAC_COLORMAP | RAC_VIEWPORT | RAC_CURSOR; -#endif - pScrn->monitor = pScrn->confScreen->monitor; - - /* Allocate an xf86CrtcConfig */ - xf86CrtcConfigInit (pScrn, &RADEONCRTCResizeFuncs); - xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); - - - if (!RADEONPreInitVisual(pScrn)) - goto fail; - - /* We can't do this until we have a - pScrn->display. */ - xf86CollectOptions(pScrn, NULL); - if (!(info->Options = malloc(sizeof(RADEONOptions)))) - goto fail; - - memcpy(info->Options, RADEONOptions, sizeof(RADEONOptions)); - xf86ProcessOptions(pScrn->scrnIndex, pScrn->options, info->Options); - - /* By default, don't do VGA IOs on ppc/sparc */ -#if defined(__powerpc__) || defined(__sparc__) || !defined(WITH_VGAHW) - info->VGAAccess = FALSE; -#else - info->VGAAccess = TRUE; -#endif - -#ifdef WITH_VGAHW - xf86GetOptValBool(info->Options, OPTION_VGA_ACCESS, &info->VGAAccess); - if (info->VGAAccess) { - if (!xf86LoadSubModule(pScrn, "vgahw")) - info->VGAAccess = FALSE; - else { - if (!vgaHWGetHWRec(pScrn)) - info->VGAAccess = FALSE; - } - if (!info->VGAAccess) - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Loading VGA module failed," - " trying to run without it\n"); - } else - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "VGAAccess option set to FALSE," - " VGA module load skipped\n"); - if (info->VGAAccess) { - vgaHWSetStdFuncs(VGAHWPTR(pScrn)); - vgaHWGetIOBase(VGAHWPTR(pScrn)); - } -#endif - - - if (!RADEONPreInitWeight(pScrn)) - goto fail; - - info->DispPriority = 1; - if ((s = xf86GetOptValString(info->Options, OPTION_DISP_PRIORITY))) { - if (strcmp(s, "AUTO") == 0) { - info->DispPriority = 1; - } else if (strcmp(s, "BIOS") == 0) { - info->DispPriority = 0; - } else if (strcmp(s, "HIGH") == 0) { - info->DispPriority = 2; - } else - info->DispPriority = 1; - } - - if (!RADEONPreInitChipType(pScrn)) - goto fail; - - if (!RADEONPreInitInt10(pScrn, &pInt10)) - goto fail; - - RADEONPostInt10Check(pScrn, int10_save); - - if (!RADEONPreInitBIOS(pScrn, pInt10)) - goto fail; - - /* Save BIOS scratch registers */ - RADEONSaveBIOSRegisters(pScrn, info->SavedReg); - -#ifdef XF86DRI - /* PreInit DRI first of all since we need that for getting a proper - * memory map - */ - info->directRenderingEnabled = RADEONPreInitDRI(pScrn); - if (info->directRenderingEnabled < 0) - goto fail; -#endif - if (!info->directRenderingEnabled) { - if (info->ChipFamily >= CHIP_FAMILY_R600) { - info->r600_shadow_fb = TRUE; - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "using shadow framebuffer\n"); - if (!xf86LoadSubModule(pScrn, "shadow")) - info->r600_shadow_fb = FALSE; - } - } - - if (!RADEONPreInitVRAM(pScrn)) - goto fail; - - RADEONPreInitColorTiling(pScrn); - - if (IS_AVIVO_VARIANT) - xf86CrtcSetSizeRange (pScrn, 320, 200, 8192, 8192); - else - xf86CrtcSetSizeRange (pScrn, 320, 200, 4096, 4096); - - RADEONPreInitDDC(pScrn); - - if (!RADEONPreInitControllers(pScrn)) - goto fail; - - if (!xf86InitialConfiguration (pScrn, FALSE)) - { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No valid modes.\n"); - goto fail; - } - - /* fix up cloning on rn50 cards - * since they only have one crtc sometimes the xserver doesn't assign - * a crtc to one of the outputs even though both outputs have common modes - * which results in only one monitor being enabled. Assign a crtc here so - * that both outputs light up. - */ - if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2) { - int i; - - for (i = 0; i < xf86_config->num_output; i++) { - xf86OutputPtr output = xf86_config->output[i]; - - /* XXX: double check crtc mode */ - if ((output->probed_modes != NULL) && (output->crtc == NULL)) - output->crtc = xf86_config->crtc[0]; - } - } - - RADEONSetPitch(pScrn); - - /* Set display resolution */ - xf86SetDpi(pScrn, 0, 0); - - /* Get ScreenInit function */ - if (!xf86LoadSubModule(pScrn, "fb")) return FALSE; - - if (!RADEONPreInitGamma(pScrn)) goto fail; - - if (!RADEONPreInitCursor(pScrn)) goto fail; - - if (!RADEONPreInitAccel(pScrn)) goto fail; - - if (!IS_AVIVO_VARIANT) { - if (!RADEONPreInitXv(pScrn)) goto fail; - } - - if (!xf86RandR12PreInit (pScrn)) - { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "RandR initialization failure\n"); - goto fail; - } - - if (pScrn->modes == NULL) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No modes.\n"); - goto fail; - } - - - /* Free int10 info */ - if (pInt10) - xf86FreeInt10(pInt10); - - if(info->MMIO) RADEONUnmapMMIO(pScrn); - info->MMIO = NULL; - - xf86DrvMsg(pScrn->scrnIndex, X_NOTICE, - "MergedFB support has been removed and replaced with" - " xrandr 1.2 support\n"); - - return TRUE; - -fail: - /* Pre-init failed. */ - /* Free the video bios (if applicable) */ - if (info->VBIOS) { - free(info->VBIOS); - info->VBIOS = NULL; - } - - /* Free int10 info */ - if (pInt10) - xf86FreeInt10(pInt10); - -#ifdef WITH_VGAHW - if (info->VGAAccess) - vgaHWFreeHWRec(pScrn); -#endif - - if(info->MMIO) RADEONUnmapMMIO(pScrn); - info->MMIO = NULL; - - fail1: - RADEONFreeRec(pScrn); - - return FALSE; -} - -/* Load a palette */ -static void RADEONLoadPalette(ScrnInfoPtr pScrn, int numColors, - int *indices, LOCO *colors, VisualPtr pVisual) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); - int i; - int index, j; - uint16_t lut_r[256], lut_g[256], lut_b[256]; - int c; - -#ifdef XF86DRI - if (info->cp->CPStarted && pScrn->pScreen) DRILock(pScrn->pScreen, 0); -#endif - - if (info->accelOn && pScrn->pScreen) - RADEON_SYNC(info, pScrn); - - { - - for (c = 0; c < xf86_config->num_crtc; c++) { - xf86CrtcPtr crtc = xf86_config->crtc[c]; - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - - for (i = 0 ; i < 256; i++) { - lut_r[i] = radeon_crtc->lut_r[i] << 6; - lut_g[i] = radeon_crtc->lut_g[i] << 6; - lut_b[i] = radeon_crtc->lut_b[i] << 6; - } - - switch (info->CurrentLayout.depth) { - case 15: - for (i = 0; i < numColors; i++) { - index = indices[i]; - for (j = 0; j < 8; j++) { - lut_r[index * 8 + j] = colors[index].red << 6; - lut_g[index * 8 + j] = colors[index].green << 6; - lut_b[index * 8 + j] = colors[index].blue << 6; - } - } - case 16: - for (i = 0; i < numColors; i++) { - index = indices[i]; - - if (i <= 31) { - for (j = 0; j < 8; j++) { - lut_r[index * 8 + j] = colors[index].red << 6; - lut_b[index * 8 + j] = colors[index].blue << 6; - } - } - - for (j = 0; j < 4; j++) { - lut_g[index * 4 + j] = colors[index].green << 6; - } - } - default: - for (i = 0; i < numColors; i++) { - index = indices[i]; - lut_r[index] = colors[index].red << 6; - lut_g[index] = colors[index].green << 6; - lut_b[index] = colors[index].blue << 6; - } - break; - } - - /* Make the change through RandR */ -#ifdef RANDR_12_INTERFACE - if (crtc->randr_crtc) - RRCrtcGammaSet(crtc->randr_crtc, lut_r, lut_g, lut_b); - else -#endif - crtc->funcs->gamma_set(crtc, lut_r, lut_g, lut_b, 256); - } - } - -#ifdef XF86DRI - if (info->cp->CPStarted && pScrn->pScreen) DRIUnlock(pScrn->pScreen); -#endif -} - -static void RADEONBlockHandler(BLOCKHANDLER_ARGS_DECL) -{ - SCREEN_PTR(arg); - ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); - RADEONInfoPtr info = RADEONPTR(pScrn); - - pScreen->BlockHandler = info->BlockHandler; - (*pScreen->BlockHandler) (BLOCKHANDLER_ARGS); - pScreen->BlockHandler = RADEONBlockHandler; - - if (info->VideoTimerCallback) - (*info->VideoTimerCallback)(pScrn, currentTime.milliseconds); - -#if defined(RENDER) && defined(USE_XAA) - if(info->accel_state->RenderCallback) - (*info->accel_state->RenderCallback)(pScrn); -#endif - -#ifdef USE_EXA - info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN; -#endif - - if (info->pm.dynamic_mode_enabled) - RADEONPMBlockHandler(pScrn); -} - -static void -RADEONInitBIOSRegisters(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - RADEONSavePtr save = info->ModeReg; - - save->bios_0_scratch = info->SavedReg->bios_0_scratch; - save->bios_1_scratch = info->SavedReg->bios_1_scratch; - save->bios_2_scratch = info->SavedReg->bios_2_scratch; - save->bios_3_scratch = info->SavedReg->bios_3_scratch; - save->bios_4_scratch = info->SavedReg->bios_4_scratch; - save->bios_5_scratch = info->SavedReg->bios_5_scratch; - save->bios_6_scratch = info->SavedReg->bios_6_scratch; - save->bios_7_scratch = info->SavedReg->bios_7_scratch; - - if (info->IsAtomBios) { - /* let the bios control the backlight */ - save->bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE; - /* tell the bios not to handle mode switching */ - save->bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | - ATOM_S6_ACC_MODE); - - if (info->ChipFamily >= CHIP_FAMILY_R600) { - OUTREG(R600_BIOS_2_SCRATCH, save->bios_2_scratch); - OUTREG(R600_BIOS_6_SCRATCH, save->bios_6_scratch); - } else { - OUTREG(RADEON_BIOS_2_SCRATCH, save->bios_2_scratch); - OUTREG(RADEON_BIOS_6_SCRATCH, save->bios_6_scratch); - } - } else { - /* let the bios control the backlight */ - save->bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN; - /* tell the bios not to handle mode switching */ - save->bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS | - RADEON_ACC_MODE_CHANGE); - /* tell the bios a driver is loaded */ - save->bios_7_scratch |= RADEON_DRV_LOADED; - - OUTREG(RADEON_BIOS_0_SCRATCH, save->bios_0_scratch); - OUTREG(RADEON_BIOS_6_SCRATCH, save->bios_6_scratch); - //OUTREG(RADEON_BIOS_7_SCRATCH, save->bios_7_scratch); - } - -} - - -/* Called at the start of each server generation. */ -Bool RADEONScreenInit(SCREEN_INIT_ARGS_DECL) -{ - ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); - RADEONInfoPtr info = RADEONPTR(pScrn); - int hasDRI = 0; -#ifdef RENDER - int subPixelOrder = SubPixelUnknown; - char* s; -#endif - - - info->accelOn = FALSE; -#ifdef USE_XAA - info->accel_state->accel = NULL; -#endif -#ifdef XF86DRI - pScrn->fbOffset = info->dri->frontOffset; -#endif - - if (info->IsSecondary) - pScrn->fbOffset = pScrn->videoRam * 1024; -#ifdef XF86DRI - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "RADEONScreenInit %lx %ld %d\n", - pScrn->memPhysBase, pScrn->fbOffset, info->dri->frontOffset); -#else - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "RADEONScreenInit %lx %ld\n", - pScrn->memPhysBase, pScrn->fbOffset); -#endif - if (!RADEONMapMem(pScrn)) return FALSE; - -#ifdef XF86DRI - info->dri->fbX = 0; - info->dri->fbY = 0; -#endif - - info->PaletteSavedOnVT = FALSE; - - info->crtc_on = FALSE; - info->crtc2_on = FALSE; - - /* save the real front buffer size - * it changes with randr, rotation, etc. - */ - info->virtualX = pScrn->virtualX; - info->virtualY = pScrn->virtualY; - - RADEONSave(pScrn); - - /* set initial bios scratch reg state */ - RADEONInitBIOSRegisters(pScrn); - - /* blank the outputs/crtcs */ - RADEONBlank(pScrn); - - RADEONPMInit(pScrn); - - if (info->allowColorTiling && (pScrn->virtualX > info->MaxSurfaceWidth)) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Color tiling not supported with virtual x resolutions larger than %d, disabling\n", - info->MaxSurfaceWidth); - info->allowColorTiling = FALSE; - } - if (info->allowColorTiling) { - info->tilingEnabled = (pScrn->currentMode->Flags & (V_DBLSCAN | V_INTERLACE)) ? FALSE : TRUE; - } - - /* Visual setup */ - miClearVisualTypes(); - if (!miSetVisualTypes(pScrn->depth, - miGetDefaultVisualMask(pScrn->depth), - pScrn->rgbBits, - pScrn->defaultVisual)) return FALSE; - miSetPixmapDepths (); - -#ifdef XF86DRI - if (info->directRenderingEnabled) { - MessageType from; - - info->dri->depthBits = pScrn->depth; - - from = xf86GetOptValInteger(info->Options, OPTION_DEPTH_BITS, - &info->dri->depthBits) - ? X_CONFIG : X_DEFAULT; - - if (info->dri->depthBits != 16 && info->dri->depthBits != 24) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Value for Option \"DepthBits\" must be 16 or 24\n"); - info->dri->depthBits = pScrn->depth; - from = X_DEFAULT; - } - - xf86DrvMsg(pScrn->scrnIndex, from, - "Using %d bit depth buffer\n", info->dri->depthBits); - } - - - hasDRI = info->directRenderingEnabled; -#endif /* XF86DRI */ - - /* Initialize the memory map, this basically calculates the values - * we'll use later on for MC_FB_LOCATION & MC_AGP_LOCATION - */ - RADEONInitMemoryMap(pScrn); - - /* empty the surfaces */ - if (info->ChipFamily < CHIP_FAMILY_R600) { - unsigned char *RADEONMMIO = info->MMIO; - unsigned int j; - for (j = 0; j < 8; j++) { - OUTREG(RADEON_SURFACE0_INFO + 16 * j, 0); - OUTREG(RADEON_SURFACE0_LOWER_BOUND + 16 * j, 0); - OUTREG(RADEON_SURFACE0_UPPER_BOUND + 16 * j, 0); - } - } - -#ifdef XF86DRI - /* Depth moves are disabled by default since they are extremely slow */ - info->dri->depthMoves = xf86ReturnOptValBool(info->Options, - OPTION_DEPTH_MOVE, FALSE); - if (info->dri->depthMoves && info->allowColorTiling) { - xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Enabling depth moves\n"); - } else if (info->dri->depthMoves) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Depth moves don't work without color tiling, disabled\n"); - info->dri->depthMoves = FALSE; - } else { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Depth moves disabled by default\n"); - } -#endif - - /* Initial setup of surfaces */ - if (info->ChipFamily < CHIP_FAMILY_R600) { - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "Setting up initial surfaces\n"); - RADEONChangeSurfaces(pScrn); - } - - /* Memory manager setup */ - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "Setting up accel memmap\n"); - -#ifdef USE_EXA - if (info->useEXA) { -#ifdef XF86DRI - if (hasDRI) { - info->accelDFS = xf86ReturnOptValBool(info->Options, OPTION_ACCEL_DFS, - info->cardType != CARD_AGP); - - /* Reserve approx. half of offscreen memory for local textures by - * default, can be overridden with Option "FBTexPercent". - * Round down to a whole number of texture regions. - */ - info->dri->textureSize = 50; - - if (xf86GetOptValInteger(info->Options, OPTION_FBTEX_PERCENT, - &(info->dri->textureSize))) { - if (info->dri->textureSize < 0 || info->dri->textureSize > 100) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Illegal texture memory percentage: %dx, setting to default 50%%\n", - info->dri->textureSize); - info->dri->textureSize = 50; - } - } - } -#endif /* XF86DRI */ - - if (!RADEONSetupMemEXA(pScreen)) - return FALSE; - } -#endif - -#if defined(XF86DRI) && defined(USE_XAA) - if (!info->useEXA && hasDRI) { - info->dri->textureSize = -1; - if (xf86GetOptValInteger(info->Options, OPTION_FBTEX_PERCENT, - &(info->dri->textureSize))) { - if (info->dri->textureSize < 0 || info->dri->textureSize > 100) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Illegal texture memory percentage: %dx, using default behaviour\n", - info->dri->textureSize); - info->dri->textureSize = -1; - } - } - if (!RADEONSetupMemXAA_DRI(pScreen)) - return FALSE; - pScrn->fbOffset = info->dri->frontOffset; - } -#endif - -#ifdef USE_XAA - if (!info->useEXA && !hasDRI && !RADEONSetupMemXAA(pScreen)) - return FALSE; -#endif - - info->accel_state->dst_pitch_offset = - (((pScrn->displayWidth * info->CurrentLayout.pixel_bytes / 64) - << 22) | ((info->fbLocation + pScrn->fbOffset) >> 10)); - - /* Setup DRI after visuals have been established, but before fbScreenInit is - * called. fbScreenInit will eventually call the driver's InitGLXVisuals - * call back. */ -#ifdef XF86DRI - if (info->directRenderingEnabled) { - /* FIXME: When we move to dynamic allocation of back and depth - * buffers, we will want to revisit the following check for 3 - * times the virtual size of the screen below. - */ - int width_bytes = (pScrn->displayWidth * - info->CurrentLayout.pixel_bytes); - int maxy = info->FbMapSize / width_bytes; - - if (maxy <= pScrn->virtualY * 3) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Static buffer allocation failed. Disabling DRI.\n"); - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "At least %d kB of video memory needed at this " - "resolution and depth.\n", - (pScrn->displayWidth * pScrn->virtualY * - info->CurrentLayout.pixel_bytes * 3 + 1023) / 1024); - info->directRenderingEnabled = FALSE; - } else { - info->directRenderingEnabled = RADEONDRIScreenInit(pScreen); - } - } - - /* Tell DRI about new memory map */ - if (info->directRenderingEnabled && info->dri->newMemoryMap) { - if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_NEW_MEMMAP, 1) < 0) { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "[drm] failed to enable new memory map\n"); - RADEONDRICloseScreen(pScreen); - info->directRenderingEnabled = FALSE; - } - } -#endif - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "Initializing fb layer\n"); - - if (info->r600_shadow_fb) { - info->fb_shadow = calloc(1, - pScrn->displayWidth * pScrn->virtualY * - ((pScrn->bitsPerPixel + 7) >> 3)); - if (info->fb_shadow == NULL) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Failed to allocate shadow framebuffer\n"); - info->r600_shadow_fb = FALSE; - } else { - if (!fbScreenInit(pScreen, info->fb_shadow, - pScrn->virtualX, pScrn->virtualY, - pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth, - pScrn->bitsPerPixel)) - return FALSE; - } - } - - if (info->r600_shadow_fb == FALSE) { - /* Init fb layer */ - if (!fbScreenInit(pScreen, info->FB + pScrn->fbOffset, - pScrn->virtualX, pScrn->virtualY, - pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth, - pScrn->bitsPerPixel)) - return FALSE; - } - - xf86SetBlackWhitePixels(pScreen); - - if (pScrn->bitsPerPixel > 8) { - VisualPtr visual; - - visual = pScreen->visuals + pScreen->numVisuals; - while (--visual >= pScreen->visuals) { - if ((visual->class | DynamicClass) == DirectColor) { - visual->offsetRed = pScrn->offset.red; - visual->offsetGreen = pScrn->offset.green; - visual->offsetBlue = pScrn->offset.blue; - visual->redMask = pScrn->mask.red; - visual->greenMask = pScrn->mask.green; - visual->blueMask = pScrn->mask.blue; - } - } - } - - /* Must be after RGB order fixed */ - fbPictureInit (pScreen, 0, 0); - -#ifdef RENDER - if ((s = xf86GetOptValString(info->Options, OPTION_SUBPIXEL_ORDER))) { - if (strcmp(s, "RGB") == 0) subPixelOrder = SubPixelHorizontalRGB; - else if (strcmp(s, "BGR") == 0) subPixelOrder = SubPixelHorizontalBGR; - else if (strcmp(s, "NONE") == 0) subPixelOrder = SubPixelNone; - PictureSetSubpixelOrder (pScreen, subPixelOrder); - } -#endif - - pScrn->vtSema = TRUE; - - /* restore the memory map here otherwise we may get a hang when - * initializing the drm below - */ - RADEONInitMemMapRegisters(pScrn, info->ModeReg, info); - RADEONRestoreMemMapRegisters(pScrn, info->ModeReg); - - /* Backing store setup */ - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "Initializing backing store\n"); - miInitializeBackingStore(pScreen); - xf86SetBackingStore(pScreen); - - /* DRI finalisation */ -#ifdef XF86DRI - if (info->directRenderingEnabled && info->cardType==CARD_PCIE && - info->dri->pKernelDRMVersion->version_minor >= 19) - { - if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_PCIGART_LOCATION, info->dri->pciGartOffset) < 0) - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "[drm] failed set pci gart location\n"); - - if (info->dri->pKernelDRMVersion->version_minor >= 26) { - if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_PCIGART_TABLE_SIZE, info->dri->pciGartSize) < 0) - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "[drm] failed set pci gart table size\n"); - } - } - if (info->directRenderingEnabled) { - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "DRI Finishing init !\n"); - info->directRenderingEnabled = RADEONDRIFinishScreenInit(pScreen); - } - if (info->directRenderingEnabled) { - /* DRI final init might have changed the memory map, we need to adjust - * our local image to make sure we restore them properly on mode - * changes or VT switches - */ - RADEONAdjustMemMapRegisters(pScrn, info->ModeReg); - - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct rendering enabled\n"); - - /* we might already be in tiled mode, tell drm about it */ - if (info->directRenderingEnabled && info->tilingEnabled) { - if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_SWITCH_TILING, (info->tilingEnabled ? 1 : 0)) < 0) - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "[drm] failed changing tiling status\n"); - } - } else { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "Direct rendering disabled\n"); - } -#endif - - /* Make sure surfaces are allright since DRI setup may have changed them */ - if (info->ChipFamily < CHIP_FAMILY_R600) { - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "Setting up final surfaces\n"); - - RADEONChangeSurfaces(pScrn); - } - - - /* Enable aceleration */ - if (!xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) { - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "Initializing Acceleration\n"); - if (RADEONAccelInit(pScreen)) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Acceleration enabled\n"); - info->accelOn = TRUE; - } else { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Acceleration initialization failed\n"); - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Acceleration disabled\n"); - info->accelOn = FALSE; - } - } else { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Acceleration disabled\n"); - info->accelOn = FALSE; - } - - /* Init DPMS */ - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "Initializing DPMS\n"); - xf86DPMSInit(pScreen, xf86DPMSSet, 0); - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "Initializing Cursor\n"); - - /* Set Silken Mouse */ - xf86SetSilkenMouse(pScreen); - - /* Cursor setup */ - miDCInitialize(pScreen, xf86GetPointerScreenFuncs()); - - /* Hardware cursor setup */ - if (!xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) { - if (RADEONCursorInit(pScreen)) { -#ifdef USE_XAA - if (!info->useEXA) { - int width, height; - - if (xf86QueryLargestOffscreenArea(pScreen, &width, &height, - 0, 0, 0)) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Largest offscreen area available: %d x %d\n", - width, height); - } - } -#endif /* USE_XAA */ - } else { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Hardware cursor initialization failed\n"); - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Using software cursor\n"); - } - } else { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Using software cursor\n"); - } - - /* DGA setup */ -#ifdef XFreeXDGA - xf86DiDGAInit(pScreen, info->LinearAddr + pScrn->fbOffset); -#endif - - /* Init Xv */ - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "Initializing Xv\n"); - RADEONInitVideo(pScreen); - - if (info->r600_shadow_fb == TRUE) { - if (!shadowSetup(pScreen)) { - return FALSE; - } - } - - /* Clear the framebuffer */ - memset(info->FB + pScrn->fbOffset, 0, - pScrn->virtualY * pScrn->displayWidth * info->CurrentLayout.pixel_bytes); - - pScrn->pScreen = pScreen; - - /* set the modes with desired rotation, etc. */ - if (!xf86SetDesiredModes (pScrn)) - return FALSE; - - /* Provide SaveScreen & wrap BlockHandler and CloseScreen */ - /* Wrap CloseScreen */ - info->CloseScreen = pScreen->CloseScreen; - pScreen->CloseScreen = RADEONCloseScreen; - pScreen->SaveScreen = RADEONSaveScreen; - info->BlockHandler = pScreen->BlockHandler; - pScreen->BlockHandler = RADEONBlockHandler; - info->CreateScreenResources = pScreen->CreateScreenResources; - pScreen->CreateScreenResources = RADEONCreateScreenResources; - - if (!xf86CrtcScreenInit (pScreen)) - return FALSE; - - /* Colormap setup */ - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "Initializing color map\n"); - if (!miCreateDefColormap(pScreen)) return FALSE; - /* all radeons support 10 bit CLUTs */ - if (!xf86HandleColormaps(pScreen, 256, 10, - RADEONLoadPalette, NULL, - CMAP_PALETTED_TRUECOLOR -#if 0 /* This option messes up text mode! (eich@suse.de) */ - | CMAP_LOAD_EVEN_IF_OFFSCREEN -#endif - | CMAP_RELOAD_ON_MODE_SWITCH)) return FALSE; - - /* Note unused options */ - if (serverGeneration == 1) - xf86ShowUnusedOptions(pScrn->scrnIndex, pScrn->options); - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "RADEONScreenInit finished\n"); - - return TRUE; -} - -/* Write memory mapping registers */ -void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, - RADEONSavePtr restore) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - int timeout; - uint32_t mc_fb_loc, mc_agp_loc, mc_agp_loc_hi; - - radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &mc_fb_loc, - &mc_agp_loc, &mc_agp_loc_hi); - - if (info->IsSecondary) - return; - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "RADEONRestoreMemMapRegisters() : \n"); - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - " MC_FB_LOCATION : 0x%08x 0x%08x\n", - (unsigned)restore->mc_fb_location, (unsigned int)mc_fb_loc); - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - " MC_AGP_LOCATION : 0x%08x\n", - (unsigned)restore->mc_agp_location); - - if (IS_DCE4_VARIANT) { - if (mc_fb_loc != restore->mc_fb_location || - mc_agp_loc != restore->mc_agp_location) { - uint32_t tmp; - - //XXX - //RADEONWaitForIdleMMIO(pScrn); - - /* disable VGA rendering core */ - OUTREG(AVIVO_VGA_RENDER_CONTROL, INREG(AVIVO_VGA_RENDER_CONTROL) & ~AVIVO_VGA_VSTATUS_CNTL_MASK); - OUTREG(AVIVO_D1VGA_CONTROL, INREG(AVIVO_D1VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); - OUTREG(AVIVO_D2VGA_CONTROL, INREG(AVIVO_D2VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); - OUTREG(EVERGREEN_D3VGA_CONTROL, INREG(EVERGREEN_D3VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); - OUTREG(EVERGREEN_D4VGA_CONTROL, INREG(EVERGREEN_D4VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); - OUTREG(EVERGREEN_D5VGA_CONTROL, INREG(EVERGREEN_D5VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); - OUTREG(EVERGREEN_D6VGA_CONTROL, INREG(EVERGREEN_D6VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); - - /* Stop display & memory access */ - tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET); - OUTREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, tmp & ~EVERGREEN_CRTC_MASTER_EN); - tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET); - - tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); - OUTREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, tmp & ~EVERGREEN_CRTC_MASTER_EN); - tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); - - if (!IS_DCE41_VARIANT) { - tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET); - OUTREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, tmp & ~EVERGREEN_CRTC_MASTER_EN); - tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET); - - tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); - OUTREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, tmp & ~EVERGREEN_CRTC_MASTER_EN); - tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); - - tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET); - OUTREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, tmp & ~EVERGREEN_CRTC_MASTER_EN); - tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET); - - tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); - OUTREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, tmp & ~EVERGREEN_CRTC_MASTER_EN); - tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); - } - - usleep(10000); - timeout = 0; - while (!(radeon_get_mc_idle(pScrn))) { - if (++timeout > 1000000) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Timeout trying to update memory controller settings !\n"); - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "You will probably crash now ... \n"); - /* Nothing we can do except maybe try to kill the server, - * let's wait 2 seconds to leave the above message a chance - * to maybe hit the disk and continue trying to setup despite - * the MC being non-idle - */ - usleep(2000000); - } - usleep(10); - } - - radeon_write_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, - restore->mc_fb_location, - restore->mc_agp_location, - restore->mc_agp_location_hi); - - OUTREG(R600_HDP_NONSURFACE_BASE, (restore->mc_fb_location & 0xffff) << 16); - - } - } else if (IS_AVIVO_VARIANT) { - if (mc_fb_loc != restore->mc_fb_location || - mc_agp_loc != restore->mc_agp_location) { - uint32_t tmp; - - RADEONWaitForIdleMMIO(pScrn); - - /* disable VGA rendering core */ - OUTREG(AVIVO_VGA_RENDER_CONTROL, INREG(AVIVO_VGA_RENDER_CONTROL) &~ AVIVO_VGA_VSTATUS_CNTL_MASK); - - OUTREG(AVIVO_D1VGA_CONTROL, INREG(AVIVO_D1VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); - OUTREG(AVIVO_D2VGA_CONTROL, INREG(AVIVO_D2VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); - - /* Stop display & memory access */ - tmp = INREG(AVIVO_D1CRTC_CONTROL); - OUTREG(AVIVO_D1CRTC_CONTROL, tmp & ~AVIVO_CRTC_EN); - - tmp = INREG(AVIVO_D2CRTC_CONTROL); - OUTREG(AVIVO_D2CRTC_CONTROL, tmp & ~AVIVO_CRTC_EN); - - tmp = INREG(AVIVO_D2CRTC_CONTROL); - - usleep(10000); - timeout = 0; - while (!(radeon_get_mc_idle(pScrn))) { - if (++timeout > 1000000) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Timeout trying to update memory controller settings !\n"); - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "You will probably crash now ... \n"); - /* Nothing we can do except maybe try to kill the server, - * let's wait 2 seconds to leave the above message a chance - * to maybe hit the disk and continue trying to setup despite - * the MC being non-idle - */ - usleep(2000000); - } - usleep(10); - } - - radeon_write_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, - restore->mc_fb_location, - restore->mc_agp_location, - restore->mc_agp_location_hi); - - if (info->ChipFamily < CHIP_FAMILY_R600) { - OUTREG(AVIVO_HDP_FB_LOCATION, restore->mc_fb_location); - } else { - OUTREG(R600_HDP_NONSURFACE_BASE, (restore->mc_fb_location << 16) & 0xff0000); - } - - /* Reset the engine and HDP */ - if (info->ChipFamily < CHIP_FAMILY_R600) - RADEONEngineReset(pScrn); - } - } else { - - /* Write memory mapping registers only if their value change - * since we must ensure no access is done while they are - * reprogrammed - */ - if (mc_fb_loc != restore->mc_fb_location || - mc_agp_loc != restore->mc_agp_location) { - uint32_t crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl=0, ov0_scale_cntl; - uint32_t old_mc_status; - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - " Map Changed ! Applying ...\n"); - - /* Make sure engine is idle. We assume the CCE is stopped - * at this point - */ - RADEONWaitForIdleMMIO(pScrn); - - if (info->IsIGP) - goto igp_no_mcfb; - - /* Capture MC_STATUS in case things go wrong ... */ - old_mc_status = INREG(RADEON_MC_STATUS); - - /* Stop display & memory access */ - ov0_scale_cntl = INREG(RADEON_OV0_SCALE_CNTL); - OUTREG(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl & ~RADEON_SCALER_ENABLE); - crtc_ext_cntl = INREG(RADEON_CRTC_EXT_CNTL); - OUTREG(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl | RADEON_CRTC_DISPLAY_DIS); - crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL); - RADEONWaitForVerticalSync(pScrn); - OUTREG(RADEON_CRTC_GEN_CNTL, - (crtc_gen_cntl - & ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_ICON_EN)) - | RADEON_CRTC_DISP_REQ_EN_B | RADEON_CRTC_EXT_DISP_EN); - - if (pRADEONEnt->HasCRTC2) { - crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL); - RADEONWaitForVerticalSync2(pScrn); - OUTREG(RADEON_CRTC2_GEN_CNTL, - (crtc2_gen_cntl - & ~(RADEON_CRTC2_CUR_EN | RADEON_CRTC2_ICON_EN)) - | RADEON_CRTC2_DISP_REQ_EN_B); - } - - /* Make sure the chip settles down (paranoid !) */ - usleep(100000); - timeout = 0; - while (!(radeon_get_mc_idle(pScrn))) { - if (++timeout > 1000000) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Timeout trying to update memory controller settings !\n"); - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "MC_STATUS = 0x%08x (on entry = 0x%08x)\n", - (unsigned int)INREG(RADEON_MC_STATUS), (unsigned int)old_mc_status); - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "You will probably crash now ... \n"); - /* Nothing we can do except maybe try to kill the server, - * let's wait 2 seconds to leave the above message a chance - * to maybe hit the disk and continue trying to setup despite - * the MC being non-idle - */ - usleep(2000000); - } - usleep(10); - } - - /* Update maps, first clearing out AGP to make sure we don't get - * a temporary overlap - */ - OUTREG(RADEON_MC_AGP_LOCATION, 0xfffffffc); - OUTREG(RADEON_MC_FB_LOCATION, restore->mc_fb_location); - radeon_write_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, restore->mc_fb_location, - 0xfffffffc, 0); - igp_no_mcfb: - radeon_write_mc_fb_agp_location(pScrn, LOC_AGP, 0, - restore->mc_agp_location, 0); - /* Make sure map fully reached the chip */ - (void)INREG(RADEON_MC_FB_LOCATION); - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - " Map applied, resetting engine ...\n"); - - /* Reset the engine and HDP */ - RADEONEngineReset(pScrn); - - /* Make sure we have sane offsets before re-enabling the CRTCs, disable - * stereo, clear offsets, and wait for offsets to catch up with hw - */ - - OUTREG(RADEON_CRTC_OFFSET_CNTL, RADEON_CRTC_OFFSET_FLIP_CNTL); - OUTREG(RADEON_CRTC_OFFSET, 0); - OUTREG(RADEON_CUR_OFFSET, 0); - timeout = 0; - while(INREG(RADEON_CRTC_OFFSET) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) { - if (timeout++ > 1000000) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Timeout waiting for CRTC offset to update !\n"); - break; - } - usleep(1000); - } - if (pRADEONEnt->HasCRTC2) { - OUTREG(RADEON_CRTC2_OFFSET_CNTL, RADEON_CRTC2_OFFSET_FLIP_CNTL); - OUTREG(RADEON_CRTC2_OFFSET, 0); - OUTREG(RADEON_CUR2_OFFSET, 0); - timeout = 0; - while(INREG(RADEON_CRTC2_OFFSET) & RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET) { - if (timeout++ > 1000000) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Timeout waiting for CRTC2 offset to update !\n"); - break; - } - usleep(1000); - } - } - } - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "Updating display base addresses...\n"); - - OUTREG(RADEON_DISPLAY_BASE_ADDR, restore->display_base_addr); - if (pRADEONEnt->HasCRTC2) - OUTREG(RADEON_DISPLAY2_BASE_ADDR, restore->display2_base_addr); - OUTREG(RADEON_OV0_BASE_ADDR, restore->ov0_base_addr); - (void)INREG(RADEON_OV0_BASE_ADDR); - - /* More paranoia delays, wait 100ms */ - usleep(100000); - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "Memory map updated.\n"); - } -} - -#ifdef XF86DRI -static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - uint32_t fb, agp, agp_hi; - int changed = 0; - - if (info->IsSecondary) - return; - - radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &fb, &agp, &agp_hi); - - if (fb != save->mc_fb_location || agp != save->mc_agp_location || - agp_hi != save->mc_agp_location_hi) - changed = 1; - - if (changed) { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "DRI init changed memory map, adjusting ...\n"); - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - " MC_FB_LOCATION was: 0x%08lx is: 0x%08lx\n", - (long unsigned int)info->mc_fb_location, (long unsigned int)fb); - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - " MC_AGP_LOCATION was: 0x%08lx is: 0x%08lx\n", - (long unsigned int)info->mc_agp_location, (long unsigned int)agp); - info->mc_fb_location = fb; - info->mc_agp_location = agp; - if (info->ChipFamily >= CHIP_FAMILY_R600) - info->fbLocation = ((uint64_t)info->mc_fb_location & 0xffff) << 24; - else - info->fbLocation = ((uint64_t)info->mc_fb_location & 0xffff) << 16; - - info->accel_state->dst_pitch_offset = - (((pScrn->displayWidth * info->CurrentLayout.pixel_bytes / 64) - << 22) | ((info->fbLocation + pScrn->fbOffset) >> 10)); - RADEONInitMemMapRegisters(pScrn, save, info); - RADEONRestoreMemMapRegisters(pScrn, save); - } - -#ifdef USE_EXA - if (info->accelDFS || (info->ChipFamily >= CHIP_FAMILY_R600)) - { - drm_radeon_getparam_t gp; - int gart_base; - - memset(&gp, 0, sizeof(gp)); - gp.param = RADEON_PARAM_GART_BASE; - gp.value = &gart_base; - - if (drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_GETPARAM, &gp, - sizeof(gp)) < 0) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Failed to determine GART area MC location, not using " - "accelerated DownloadFromScreen hook!\n"); - info->accelDFS = FALSE; - } else { - info->gartLocation = gart_base; - } - } -#endif /* USE_EXA */ -} -#endif - -/* restore original surface info (for fb console). */ -static void RADEONRestoreSurfaces(ScrnInfoPtr pScrn, RADEONSavePtr restore) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - unsigned int surfnr; - - for ( surfnr = 0; surfnr < 8; surfnr++ ) { - OUTREG(RADEON_SURFACE0_INFO + 16 * surfnr, restore->surfaces[surfnr][0]); - OUTREG(RADEON_SURFACE0_LOWER_BOUND + 16 * surfnr, restore->surfaces[surfnr][1]); - OUTREG(RADEON_SURFACE0_UPPER_BOUND + 16 * surfnr, restore->surfaces[surfnr][2]); - } -} - -/* save original surface info (for fb console). */ -static void RADEONSaveSurfaces(ScrnInfoPtr pScrn, RADEONSavePtr save) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - unsigned int surfnr; - - for ( surfnr = 0; surfnr < 8; surfnr++ ) { - save->surfaces[surfnr][0] = INREG(RADEON_SURFACE0_INFO + 16 * surfnr); - save->surfaces[surfnr][1] = INREG(RADEON_SURFACE0_LOWER_BOUND + 16 * surfnr); - save->surfaces[surfnr][2] = INREG(RADEON_SURFACE0_UPPER_BOUND + 16 * surfnr); - } -} - -void RADEONChangeSurfaces(ScrnInfoPtr pScrn) -{ - /* the idea here is to only set up front buffer as tiled, and back/depth buffer when needed. - Everything else is left as untiled. This means we need to use eplicit src/dst pitch control - when blitting, based on the src/target address, and can no longer use a default offset. - But OTOH we don't need to dynamically change surfaces (for xv for instance), and some - ugly offset / fb reservation (cursor) is gone. And as a bonus, everything actually works... - For simplicity, just always update everything (just let the ioctl fail - could do better). - All surface addresses are relative to RADEON_MC_FB_LOCATION */ - - RADEONInfoPtr info = RADEONPTR(pScrn); - int cpp = info->CurrentLayout.pixel_bytes; - /* depth/front/back pitch must be identical (and the same as displayWidth) */ - int width_bytes = pScrn->displayWidth * cpp; - int bufferSize = RADEON_ALIGN((RADEON_ALIGN(pScrn->virtualY, 16)) * width_bytes, - RADEON_GPU_PAGE_SIZE); - unsigned int color_pattern, swap_pattern; - - if (!info->allowColorTiling) - return; - - swap_pattern = 0; -#if X_BYTE_ORDER == X_BIG_ENDIAN - switch (pScrn->bitsPerPixel) { - case 16: - swap_pattern = RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP; - break; - - case 32: - swap_pattern = RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP; - break; - } -#endif - if (info->ChipFamily < CHIP_FAMILY_R200) { - color_pattern = RADEON_SURF_TILE_COLOR_MACRO; - } else if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { - color_pattern = R300_SURF_TILE_COLOR_MACRO; - } else { - color_pattern = R200_SURF_TILE_COLOR_MACRO; - } -#ifdef XF86DRI - if (info->directRenderingInited) { - drm_radeon_surface_free_t drmsurffree; - drm_radeon_surface_alloc_t drmsurfalloc; - int retvalue; - int depthCpp = (info->dri->depthBits - 8) / 4; - int depth_width_bytes = pScrn->displayWidth * depthCpp; - int depthBufferSize = RADEON_ALIGN((RADEON_ALIGN(pScrn->virtualY, 16)) * depth_width_bytes, - RADEON_GPU_PAGE_SIZE); - unsigned int depth_pattern; - - drmsurffree.address = info->dri->frontOffset; - retvalue = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_FREE, - &drmsurffree, sizeof(drmsurffree)); - - if (!((info->ChipFamily == CHIP_FAMILY_RV100) || - (info->ChipFamily == CHIP_FAMILY_RS100) || - (info->ChipFamily == CHIP_FAMILY_RS200))) { - drmsurffree.address = info->dri->depthOffset; - retvalue = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_FREE, - &drmsurffree, sizeof(drmsurffree)); - } - - if (!info->dri->noBackBuffer) { - drmsurffree.address = info->dri->backOffset; - retvalue = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_FREE, - &drmsurffree, sizeof(drmsurffree)); - } - - drmsurfalloc.size = bufferSize; - drmsurfalloc.address = info->dri->frontOffset; - drmsurfalloc.flags = swap_pattern; - - if (info->tilingEnabled) { - if (IS_R300_VARIANT || IS_AVIVO_VARIANT) - drmsurfalloc.flags |= (width_bytes / 8) | color_pattern; - else - drmsurfalloc.flags |= (width_bytes / 16) | color_pattern; - } - retvalue = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_ALLOC, - &drmsurfalloc, sizeof(drmsurfalloc)); - if (retvalue < 0) - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "drm: could not allocate surface for front buffer!\n"); - - if ((info->dri->have3DWindows) && (!info->dri->noBackBuffer)) { - drmsurfalloc.address = info->dri->backOffset; - retvalue = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_ALLOC, - &drmsurfalloc, sizeof(drmsurfalloc)); - if (retvalue < 0) - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "drm: could not allocate surface for back buffer!\n"); - } - - if (info->ChipFamily < CHIP_FAMILY_R200) { - if (depthCpp == 2) - depth_pattern = RADEON_SURF_TILE_DEPTH_16BPP; - else - depth_pattern = RADEON_SURF_TILE_DEPTH_32BPP; - } else if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { - if (depthCpp == 2) - depth_pattern = R300_SURF_TILE_COLOR_MACRO; - else - depth_pattern = R300_SURF_TILE_COLOR_MACRO | R300_SURF_TILE_DEPTH_32BPP; - } else { - if (depthCpp == 2) - depth_pattern = R200_SURF_TILE_DEPTH_16BPP; - else - depth_pattern = R200_SURF_TILE_DEPTH_32BPP; - } - - /* rv100 and probably the derivative igps don't have depth tiling on all the time? */ - if (info->dri->have3DWindows && - (!((info->ChipFamily == CHIP_FAMILY_RV100) || - (info->ChipFamily == CHIP_FAMILY_RS100) || - (info->ChipFamily == CHIP_FAMILY_RS200)))) { - drm_radeon_surface_alloc_t drmsurfalloc; - drmsurfalloc.size = depthBufferSize; - drmsurfalloc.address = info->dri->depthOffset; - if (IS_R300_VARIANT || IS_AVIVO_VARIANT) - drmsurfalloc.flags = swap_pattern | (depth_width_bytes / 8) | depth_pattern; - else - drmsurfalloc.flags = swap_pattern | (depth_width_bytes / 16) | depth_pattern; - retvalue = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_ALLOC, - &drmsurfalloc, sizeof(drmsurfalloc)); - if (retvalue < 0) - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "drm: could not allocate surface for depth buffer!\n"); - } - } - else -#endif - { - unsigned int surf_info = swap_pattern; - unsigned char *RADEONMMIO = info->MMIO; - /* we don't need anything like WaitForFifo, no? */ - if (info->tilingEnabled) { - if (IS_R300_VARIANT || IS_AVIVO_VARIANT) - surf_info |= (width_bytes / 8) | color_pattern; - else - surf_info |= (width_bytes / 16) | color_pattern; - } - OUTREG(RADEON_SURFACE0_INFO, surf_info); - OUTREG(RADEON_SURFACE0_LOWER_BOUND, 0); - OUTREG(RADEON_SURFACE0_UPPER_BOUND, bufferSize - 1); -/* xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "surface0 set to %x, LB 0x%x UB 0x%x\n", - surf_info, 0, bufferSize - 1024);*/ - } - - /* Update surface images */ - if (info->ChipFamily < CHIP_FAMILY_R600) - RADEONSaveSurfaces(pScrn, info->ModeReg); -} - -/* Read memory map */ -static void RADEONSaveMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &save->mc_fb_location, - &save->mc_agp_location, &save->mc_agp_location_hi); - - if (!IS_AVIVO_VARIANT) { - save->display_base_addr = INREG(RADEON_DISPLAY_BASE_ADDR); - save->display2_base_addr = INREG(RADEON_DISPLAY2_BASE_ADDR); - save->ov0_base_addr = INREG(RADEON_OV0_BASE_ADDR); - } -} - -/* Read palette data */ -static void RADEONSavePalette(ScrnInfoPtr pScrn, int palID, RADEONSavePtr save) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - int i; - - PAL_SELECT(palID); - INPAL_START(0); - - for (i = 0; i < 256; i++) { - save->palette[palID][i] = INREG(RADEON_PALETTE_30_DATA); - } -} - -static void RADEONRestorePalette(ScrnInfoPtr pScrn, RADEONSavePtr restore) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - int i; - - if (restore->palette_saved[1]) { - ErrorF("Restore Palette 2\n"); - PAL_SELECT(1); - OUTPAL_START(0); - for (i = 0; i < 256; i++) { - OUTREG(RADEON_PALETTE_30_DATA, restore->palette[1][i]); - } - } - if (restore->palette_saved[0]) { - ErrorF("Restore Palette 1\n"); - PAL_SELECT(0); - OUTPAL_START(0); - for (i = 0; i < 256; i++) { - OUTREG(RADEON_PALETTE_30_DATA, restore->palette[0][i]); - } - } -} - -static void -dce4_save_grph(ScrnInfoPtr pScrn, struct dce4_main_block_state *state, - uint32_t offset) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - state->grph.enable = INREG(offset + EVERGREEN_GRPH_ENABLE); - state->grph.control = INREG(offset + EVERGREEN_GRPH_CONTROL); - state->grph.swap_control = INREG(offset + EVERGREEN_GRPH_SWAP_CONTROL); - state->grph.prim_surf_addr = INREG(offset + EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS); - state->grph.sec_surf_addr = INREG(offset + EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS); - state->grph.pitch = INREG(offset + EVERGREEN_GRPH_PITCH); - state->grph.prim_surf_addr_hi = INREG(offset + EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH); - state->grph.sec_surf_addr_hi = INREG(offset + EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH); - state->grph.x_offset = INREG(offset + EVERGREEN_GRPH_SURFACE_OFFSET_X); - state->grph.y_offset = INREG(offset + EVERGREEN_GRPH_SURFACE_OFFSET_Y); - state->grph.x_start = INREG(offset + EVERGREEN_GRPH_X_START); - state->grph.y_start = INREG(offset + EVERGREEN_GRPH_Y_START); - state->grph.x_end = INREG(offset + EVERGREEN_GRPH_X_END); - state->grph.y_end = INREG(offset + EVERGREEN_GRPH_Y_END); - - state->grph.desktop_height = INREG(offset + EVERGREEN_DESKTOP_HEIGHT); - state->grph.viewport_start = INREG(offset + EVERGREEN_VIEWPORT_START); - state->grph.viewport_size = INREG(offset + EVERGREEN_VIEWPORT_SIZE); - state->grph.mode_data_format = INREG(offset + EVERGREEN_DATA_FORMAT); -} - -static void -dce4_restore_grph(ScrnInfoPtr pScrn, struct dce4_main_block_state *state, - uint32_t offset) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - OUTREG(offset + EVERGREEN_GRPH_ENABLE, state->grph.enable); - OUTREG(offset + EVERGREEN_GRPH_CONTROL, state->grph.control); - OUTREG(offset + EVERGREEN_GRPH_SWAP_CONTROL, state->grph.swap_control); - OUTREG(offset + EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS, state->grph.prim_surf_addr); - OUTREG(offset + EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS, state->grph.sec_surf_addr); - OUTREG(offset + EVERGREEN_GRPH_PITCH, state->grph.pitch); - OUTREG(offset + EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, state->grph.prim_surf_addr_hi); - OUTREG(offset + EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, state->grph.sec_surf_addr_hi); - OUTREG(offset + EVERGREEN_GRPH_SURFACE_OFFSET_X, state->grph.x_offset); - OUTREG(offset + EVERGREEN_GRPH_SURFACE_OFFSET_Y, state->grph.y_offset); - OUTREG(offset + EVERGREEN_GRPH_X_START, state->grph.x_start); - OUTREG(offset + EVERGREEN_GRPH_Y_START, state->grph.y_start); - OUTREG(offset + EVERGREEN_GRPH_X_END, state->grph.x_end); - OUTREG(offset + EVERGREEN_GRPH_Y_END, state->grph.y_end); - - OUTREG(offset + EVERGREEN_DESKTOP_HEIGHT, state->grph.desktop_height); - OUTREG(offset + EVERGREEN_VIEWPORT_START, state->grph.viewport_start); - OUTREG(offset + EVERGREEN_VIEWPORT_SIZE, state->grph.viewport_size); - OUTREG(offset + EVERGREEN_DATA_FORMAT, state->grph.mode_data_format); -} - -static uint32_t dce4_dac_regs[] = { - 0x6690, 0x6694, 0x66b0, 0x66cc, 0x66d0, 0x66d4, 0x66d8 }; - -static uint32_t dce4_scl_regs[] = { - 0x6d08, 0x6d0c, 0x6d14, 0x6d1c }; - -static uint32_t dce4_dig_regs[] = { - 0x7000, 0x7004, 0x7008, 0x700c, 0x7010, 0x7014, - 0x71f0, 0x71f4, 0x71f8, 0x71fc, 0x7200, 0x7204, - 0x7208, 0x720c, 0x7210, 0x7218, 0x721c, 0x7220, - 0x7230}; - -static uint32_t dce4_crtc_regs[] = { - 0x6e00, 0x6e04, 0x6e08, 0x6e0c, 0x6e1c, 0x6e34, 0x6e38, 0x6e3c, 0x6e70, 0x6e74, 0x6e78}; - - -#define DCE4_REG_SCL_NUM (sizeof(dce4_scl_regs)/sizeof(uint32_t)) -#define DCE4_REG_CRTC_NUM (sizeof(dce4_crtc_regs)/sizeof(uint32_t)) -#define DCE4_REG_DIG_NUM (sizeof(dce4_dig_regs)/sizeof(uint32_t)) -#define DCE4_DAC_NUM (sizeof(dce4_dac_regs)/sizeof(uint32_t)) - - -static void -dce4_save_crtc(ScrnInfoPtr pScrn, struct dce4_main_block_state *state, - uint32_t offset) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - int i; - - for (i = 0; i < DCE4_REG_CRTC_NUM; i++) - state->crtc[i] = INREG(offset + dce4_crtc_regs[i]); -} - -static void -dce4_restore_crtc(ScrnInfoPtr pScrn, struct dce4_main_block_state *state, - uint32_t offset) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - int i; - - for (i = 0; i < DCE4_REG_CRTC_NUM; i++) - OUTREG(offset + dce4_crtc_regs[i], state->crtc[i]); -} - -static void -dce4_save_scl(ScrnInfoPtr pScrn, struct dce4_main_block_state *state, - uint32_t offset) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - int i; - - for (i = 0; i < DCE4_REG_SCL_NUM; i++) - state->scl[i] = INREG(offset + dce4_scl_regs[i]); -} - -static void -dce4_restore_scl(ScrnInfoPtr pScrn, struct dce4_main_block_state *state, - uint32_t offset) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - int i; - - for (i = 0; i < DCE4_REG_SCL_NUM; i++) - OUTREG(offset + dce4_scl_regs[i], state->scl[i]); -} - - -static void -dce4_save_fmt(ScrnInfoPtr pScrn, struct dce4_main_block_state *state, - uint32_t offset) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - int i, index = 0; - - for (i = 0x6fb4; i <= 0x6fd4; i += 4) - state->fmt[index++] = INREG(offset + i); -} - -static void -dce4_restore_fmt(ScrnInfoPtr pScrn, struct dce4_main_block_state *state, - uint32_t offset) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - int i, index = 0; - - for (i = 0x6fb4; i <= 0x6fd4; i += 4) - OUTREG(offset + i, state->fmt[index++]); -} - - -static void -dce4_save_dig(ScrnInfoPtr pScrn, struct dce4_main_block_state *state, - uint32_t offset) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - int i; - - for (i = 0; i < DCE4_REG_DIG_NUM; i++) - state->dig[i] = INREG(offset + dce4_dig_regs[i]); -} - -static void -dce4_restore_dig(ScrnInfoPtr pScrn, struct dce4_main_block_state *state, - uint32_t offset) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - int i; - - for (i = 0; i < DCE4_REG_DIG_NUM; i++) - OUTREG(offset + dce4_dig_regs[i], state->dig[i]); -} - - - -static void dce4_save_block(ScrnInfoPtr pScrn, struct dce4_main_block_state *state, - uint32_t offset) -{ - dce4_save_grph(pScrn, state, offset); - dce4_save_crtc(pScrn, state, offset); - dce4_save_scl(pScrn, state, offset); - dce4_save_dig(pScrn, state, offset); - dce4_save_fmt(pScrn, state, offset); -} - -static void dce4_restore_block(ScrnInfoPtr pScrn, struct dce4_main_block_state *state, - uint32_t offset) -{ - dce4_restore_grph(pScrn, state, offset); - dce4_restore_crtc(pScrn, state, offset); - dce4_restore_scl(pScrn, state, offset); - dce4_restore_dig(pScrn, state, offset); - dce4_restore_fmt(pScrn, state, offset); -} - -static void dce4_save_uniphy(ScrnInfoPtr pScrn, struct dce4_state *state, int index) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - uint32_t uniphy_offset[6] = {0x0, 0x30, 0x60, 0x100, 0x130, 0x160 }; - int i, ri = 0; - for (i = 0; i < 0x18; i+=4) - state->uniphy[index][ri++] = INREG(0x6600 + uniphy_offset[index] + i); -} - -static void dce4_restore_uniphy(ScrnInfoPtr pScrn, struct dce4_state *state, int index) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - uint32_t uniphy_offset[6] = {0x0, 0x30, 0x60, 0x100, 0x130, 0x160 }; - int i, ri = 0; - for (i = 0; i <= 0x18; i+=4) - OUTREG(0x6600 + uniphy_offset[index] + i, state->uniphy[index][ri++]); -} - -static void dce4_save_dig_regs(ScrnInfoPtr pScrn, struct dce4_state *state) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - int i, ri = 0; - - for (i = 0x6578; i <= 0x6598; i += 4) - state->dig[ri++] = INREG(i); - for (i = 0x65ac; i <= 0x65d8; i += 4) - state->dig[ri++] = INREG(i); -} - -static void dce4_restore_dig_regs(ScrnInfoPtr pScrn, struct dce4_state *state) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - int i, ri = 0; - - for (i = 0x6578; i <= 0x6598; i += 4) - OUTREG(i, state->dig[ri++]); - for (i = 0x65ac; i <= 0x65d8; i += 4) - OUTREG(i, state->dig[ri++]); -} - -static void dce4_save_pll_regs(ScrnInfoPtr pScrn, struct dce4_state *state) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - int i, ri = 0; - - for (i = 0x360; i <= 0x368; i += 4) - state->vga_pll[0][ri++] = INREG(i); - - ri = 0; - for (i = 0x370; i <= 0x378; i += 4) - state->vga_pll[1][ri++] = INREG(i); - - ri = 0; - for (i = 0x390; i <= 0x398; i += 4) - state->vga_pll[2][ri++] = INREG(i); - - ri = 0; - for (i = 0x400; i <= 0x408; i += 4) - state->pll[0][ri++] = INREG(i); - for (i = 0x410; i <= 0x43c; i += 4) - state->pll[0][ri++] = INREG(i); - - ri = 0; - for (i = 0x440; i <= 0x448; i += 4) - state->pll[1][ri++] = INREG(i); - for (i = 0x450; i <= 0x47c; i += 4) - state->pll[1][ri++] = INREG(i); - - ri = 0; - for (i = 0x500; i <= 0x550; i += 0x10) - state->pll_route[ri++] = INREG(i); -} - -static void dce4_restore_pll_regs(ScrnInfoPtr pScrn, struct dce4_state *state) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - int i, ri = 0; - - for (i = 0x360; i <= 0x368; i += 4) - OUTREG(i, state->vga_pll[0][ri++]); - - ri = 0; - for (i = 0x370; i <= 0x378; i += 4) - OUTREG(i, state->vga_pll[1][ri++]); - - ri = 0; - for (i = 0x390; i <= 0x398; i += 4) - OUTREG(i, state->vga_pll[2][ri++]); - - ri = 0; - for (i = 0x400; i <= 0x408; i += 4) - OUTREG(i, state->pll[0][ri++]); - for (i = 0x410; i <= 0x43c; i += 4) - OUTREG(i, state->pll[0][ri++]); - - ri = 0; - for (i = 0x440; i <= 0x448; i += 4) - OUTREG(i, state->pll[1][ri++]); - for (i = 0x450; i <= 0x47c; i += 4) - OUTREG(i, state->pll[1][ri++]); - - ri = 0; - for (i = 0x500; i <= 0x550; i += 0x10) - OUTREG(i, state->pll_route[ri++]); -} - -static void -dce4_save(ScrnInfoPtr pScrn, RADEONSavePtr save) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - struct dce4_state *state = &save->dce4; - int i, j; - uint32_t crtc_offset[] = {EVERGREEN_CRTC0_REGISTER_OFFSET, - EVERGREEN_CRTC1_REGISTER_OFFSET, - EVERGREEN_CRTC2_REGISTER_OFFSET, - EVERGREEN_CRTC3_REGISTER_OFFSET, - EVERGREEN_CRTC4_REGISTER_OFFSET, - EVERGREEN_CRTC5_REGISTER_OFFSET}; - - state->vga1_cntl = INREG(AVIVO_D1VGA_CONTROL); - state->vga2_cntl = INREG(AVIVO_D2VGA_CONTROL); - state->vga3_cntl = INREG(EVERGREEN_D3VGA_CONTROL); - state->vga4_cntl = INREG(EVERGREEN_D4VGA_CONTROL); - state->vga5_cntl = INREG(EVERGREEN_D5VGA_CONTROL); - state->vga6_cntl = INREG(EVERGREEN_D6VGA_CONTROL); - state->vga_render_control = INREG(AVIVO_VGA_RENDER_CONTROL); - - dce4_save_pll_regs(pScrn, state); - dce4_save_dig_regs(pScrn, state); - - for (i = 0; i < 6; i++) - dce4_save_block(pScrn, &state->block[i], crtc_offset[i]); - - for (i = 0; i < 6; i++) - dce4_save_uniphy(pScrn, state, i); - - for (i = 0; i < 2; i++) { - for (j = 0; j < DCE4_DAC_NUM; j++) { - uint32_t offset = i ? 0x100 : 0x0; - state->dac[i][j] = INREG(dce4_dac_regs[j] + offset); - } - } -} - -static void -dce4_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - struct dce4_state *state = &restore->dce4; - int i, j; - uint32_t crtc_offset[] = {EVERGREEN_CRTC0_REGISTER_OFFSET, - EVERGREEN_CRTC1_REGISTER_OFFSET, - EVERGREEN_CRTC2_REGISTER_OFFSET, - EVERGREEN_CRTC3_REGISTER_OFFSET, - EVERGREEN_CRTC4_REGISTER_OFFSET, - EVERGREEN_CRTC5_REGISTER_OFFSET}; - - OUTREG(AVIVO_D1VGA_CONTROL, state->vga1_cntl); - OUTREG(AVIVO_D2VGA_CONTROL, state->vga2_cntl);; - OUTREG(EVERGREEN_D3VGA_CONTROL, state->vga3_cntl); - OUTREG(EVERGREEN_D4VGA_CONTROL, state->vga4_cntl); - OUTREG(EVERGREEN_D5VGA_CONTROL, state->vga5_cntl); - OUTREG(EVERGREEN_D6VGA_CONTROL, state->vga6_cntl); - OUTREG(AVIVO_VGA_RENDER_CONTROL, state->vga_render_control); - - dce4_restore_dig_regs(pScrn, state); - dce4_restore_pll_regs(pScrn, state); - for (i = 0; i < 6; i++) - dce4_restore_uniphy(pScrn, state, i); - - for (i = 0; i < 6; i++) - dce4_restore_block(pScrn, &state->block[i], crtc_offset[i]); - - for (i = 0; i < 2; i++) { - for (j = 0; j < DCE4_DAC_NUM; j++) { - uint32_t offset = i ? 0x100 : 0x0; - OUTREG(dce4_dac_regs[j] + offset, state->dac[i][j]); - } - } -} - -static void -avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - struct avivo_state *state = &save->avivo; - int i, j; - - // state->vga_memory_base = INREG(AVIVO_VGA_MEMORY_BASE); - // state->vga_fb_start = INREG(AVIVO_VGA_FB_START); - state->vga1_cntl = INREG(AVIVO_D1VGA_CONTROL); - state->vga2_cntl = INREG(AVIVO_D2VGA_CONTROL); - state->vga_render_control = INREG(AVIVO_VGA_RENDER_CONTROL); - - state->crtc_master_en = INREG(AVIVO_DC_CRTC_MASTER_EN); - state->crtc_tv_control = INREG(AVIVO_DC_CRTC_TV_CONTROL); - state->dc_lb_memory_split = INREG(AVIVO_DC_LB_MEMORY_SPLIT); - - state->pll[0].ref_div_src = INREG(AVIVO_EXT1_PPLL_REF_DIV_SRC); - state->pll[0].ref_div = INREG(AVIVO_EXT1_PPLL_REF_DIV); - state->pll[0].fb_div = INREG(AVIVO_EXT1_PPLL_FB_DIV); - state->pll[0].post_div_src = INREG(AVIVO_EXT1_PPLL_POST_DIV_SRC); - state->pll[0].post_div = INREG(AVIVO_EXT1_PPLL_POST_DIV); - state->pll[0].ext_ppll_cntl = INREG(AVIVO_EXT1_PPLL_CNTL); - state->pll[0].pll_cntl = INREG(AVIVO_P1PLL_CNTL); - state->pll[0].int_ss_cntl = INREG(AVIVO_P1PLL_INT_SS_CNTL); - - state->pll[1].ref_div_src = INREG(AVIVO_EXT1_PPLL_REF_DIV_SRC); - state->pll[1].ref_div = INREG(AVIVO_EXT2_PPLL_REF_DIV); - state->pll[1].fb_div = INREG(AVIVO_EXT2_PPLL_FB_DIV); - state->pll[1].post_div_src = INREG(AVIVO_EXT2_PPLL_POST_DIV_SRC); - state->pll[1].post_div = INREG(AVIVO_EXT2_PPLL_POST_DIV); - state->pll[1].ext_ppll_cntl = INREG(AVIVO_EXT2_PPLL_CNTL); - state->pll[1].pll_cntl = INREG(AVIVO_P2PLL_CNTL); - state->pll[1].int_ss_cntl = INREG(AVIVO_P2PLL_INT_SS_CNTL); - - state->vga25_ppll.ref_div_src = INREG(AVIVO_VGA25_PPLL_REF_DIV_SRC); - state->vga25_ppll.ref_div = INREG(AVIVO_VGA25_PPLL_REF_DIV); - state->vga25_ppll.fb_div = INREG(AVIVO_VGA25_PPLL_FB_DIV); - state->vga25_ppll.post_div_src = INREG(AVIVO_VGA25_PPLL_POST_DIV_SRC); - state->vga25_ppll.post_div = INREG(AVIVO_VGA25_PPLL_POST_DIV); - state->vga25_ppll.pll_cntl = INREG(AVIVO_VGA25_PPLL_CNTL); - - state->vga28_ppll.ref_div_src = INREG(AVIVO_VGA28_PPLL_REF_DIV_SRC); - state->vga28_ppll.ref_div = INREG(AVIVO_VGA28_PPLL_REF_DIV); - state->vga28_ppll.fb_div = INREG(AVIVO_VGA28_PPLL_FB_DIV); - state->vga28_ppll.post_div_src = INREG(AVIVO_VGA28_PPLL_POST_DIV_SRC); - state->vga28_ppll.post_div = INREG(AVIVO_VGA28_PPLL_POST_DIV); - state->vga28_ppll.pll_cntl = INREG(AVIVO_VGA28_PPLL_CNTL); - - state->vga41_ppll.ref_div_src = INREG(AVIVO_VGA41_PPLL_REF_DIV_SRC); - state->vga41_ppll.ref_div = INREG(AVIVO_VGA41_PPLL_REF_DIV); - state->vga41_ppll.fb_div = INREG(AVIVO_VGA41_PPLL_FB_DIV); - state->vga41_ppll.post_div_src = INREG(AVIVO_VGA41_PPLL_POST_DIV_SRC); - state->vga41_ppll.post_div = INREG(AVIVO_VGA41_PPLL_POST_DIV); - state->vga41_ppll.pll_cntl = INREG(AVIVO_VGA41_PPLL_CNTL); - - state->crtc[0].pll_source = INREG(AVIVO_PCLK_CRTC1_CNTL); - - state->crtc[0].h_total = INREG(AVIVO_D1CRTC_H_TOTAL); - state->crtc[0].h_blank_start_end = INREG(AVIVO_D1CRTC_H_BLANK_START_END); - state->crtc[0].h_sync_a = INREG(AVIVO_D1CRTC_H_SYNC_A); - state->crtc[0].h_sync_a_cntl = INREG(AVIVO_D1CRTC_H_SYNC_A_CNTL); - state->crtc[0].h_sync_b = INREG(AVIVO_D1CRTC_H_SYNC_B); - state->crtc[0].h_sync_b_cntl = INREG(AVIVO_D1CRTC_H_SYNC_B_CNTL); - - state->crtc[0].v_total = INREG(AVIVO_D1CRTC_V_TOTAL); - state->crtc[0].v_blank_start_end = INREG(AVIVO_D1CRTC_V_BLANK_START_END); - state->crtc[0].v_sync_a = INREG(AVIVO_D1CRTC_V_SYNC_A); - state->crtc[0].v_sync_a_cntl = INREG(AVIVO_D1CRTC_V_SYNC_A_CNTL); - state->crtc[0].v_sync_b = INREG(AVIVO_D1CRTC_V_SYNC_B); - state->crtc[0].v_sync_b_cntl = INREG(AVIVO_D1CRTC_V_SYNC_B_CNTL); - - state->crtc[0].control = INREG(AVIVO_D1CRTC_CONTROL); - state->crtc[0].blank_control = INREG(AVIVO_D1CRTC_BLANK_CONTROL); - state->crtc[0].interlace_control = INREG(AVIVO_D1CRTC_INTERLACE_CONTROL); - state->crtc[0].stereo_control = INREG(AVIVO_D1CRTC_STEREO_CONTROL); - - state->crtc[0].cursor_control = INREG(AVIVO_D1CUR_CONTROL); - - state->grph[0].enable = INREG(AVIVO_D1GRPH_ENABLE); - state->grph[0].control = INREG(AVIVO_D1GRPH_CONTROL); - state->grph[0].control = INREG(AVIVO_D1GRPH_CONTROL); - state->grph[0].prim_surf_addr = INREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS); - state->grph[0].sec_surf_addr = INREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS); - state->grph[0].pitch = INREG(AVIVO_D1GRPH_PITCH); - state->grph[0].x_offset = INREG(AVIVO_D1GRPH_SURFACE_OFFSET_X); - state->grph[0].y_offset = INREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y); - state->grph[0].x_start = INREG(AVIVO_D1GRPH_X_START); - state->grph[0].y_start = INREG(AVIVO_D1GRPH_Y_START); - state->grph[0].x_end = INREG(AVIVO_D1GRPH_X_END); - state->grph[0].y_end = INREG(AVIVO_D1GRPH_Y_END); - - state->grph[0].desktop_height = INREG(AVIVO_D1MODE_DESKTOP_HEIGHT); - state->grph[0].viewport_start = INREG(AVIVO_D1MODE_VIEWPORT_START); - state->grph[0].viewport_size = INREG(AVIVO_D1MODE_VIEWPORT_SIZE); - state->grph[0].mode_data_format = INREG(AVIVO_D1MODE_DATA_FORMAT); - - state->crtc[1].pll_source = INREG(AVIVO_PCLK_CRTC2_CNTL); - - state->crtc[1].h_total = INREG(AVIVO_D2CRTC_H_TOTAL); - state->crtc[1].h_blank_start_end = INREG(AVIVO_D2CRTC_H_BLANK_START_END); - state->crtc[1].h_sync_a = INREG(AVIVO_D2CRTC_H_SYNC_A); - state->crtc[1].h_sync_a_cntl = INREG(AVIVO_D2CRTC_H_SYNC_A_CNTL); - state->crtc[1].h_sync_b = INREG(AVIVO_D2CRTC_H_SYNC_B); - state->crtc[1].h_sync_b_cntl = INREG(AVIVO_D2CRTC_H_SYNC_B_CNTL); - - state->crtc[1].v_total = INREG(AVIVO_D2CRTC_V_TOTAL); - state->crtc[1].v_blank_start_end = INREG(AVIVO_D2CRTC_V_BLANK_START_END); - state->crtc[1].v_sync_a = INREG(AVIVO_D2CRTC_V_SYNC_A); - state->crtc[1].v_sync_a_cntl = INREG(AVIVO_D2CRTC_V_SYNC_A_CNTL); - state->crtc[1].v_sync_b = INREG(AVIVO_D2CRTC_V_SYNC_B); - state->crtc[1].v_sync_b_cntl = INREG(AVIVO_D2CRTC_V_SYNC_B_CNTL); - - state->crtc[1].control = INREG(AVIVO_D2CRTC_CONTROL); - state->crtc[1].blank_control = INREG(AVIVO_D2CRTC_BLANK_CONTROL); - state->crtc[1].interlace_control = INREG(AVIVO_D2CRTC_INTERLACE_CONTROL); - state->crtc[1].stereo_control = INREG(AVIVO_D2CRTC_STEREO_CONTROL); - - state->crtc[1].cursor_control = INREG(AVIVO_D2CUR_CONTROL); - - state->grph[1].enable = INREG(AVIVO_D2GRPH_ENABLE); - state->grph[1].control = INREG(AVIVO_D2GRPH_CONTROL); - state->grph[1].control = INREG(AVIVO_D2GRPH_CONTROL); - state->grph[1].prim_surf_addr = INREG(AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS); - state->grph[1].sec_surf_addr = INREG(AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS); - state->grph[1].pitch = INREG(AVIVO_D2GRPH_PITCH); - state->grph[1].x_offset = INREG(AVIVO_D2GRPH_SURFACE_OFFSET_X); - state->grph[1].y_offset = INREG(AVIVO_D2GRPH_SURFACE_OFFSET_Y); - state->grph[1].x_start = INREG(AVIVO_D2GRPH_X_START); - state->grph[1].y_start = INREG(AVIVO_D2GRPH_Y_START); - state->grph[1].x_end = INREG(AVIVO_D2GRPH_X_END); - state->grph[1].y_end = INREG(AVIVO_D2GRPH_Y_END); - - state->grph[1].desktop_height = INREG(AVIVO_D2MODE_DESKTOP_HEIGHT); - state->grph[1].viewport_start = INREG(AVIVO_D2MODE_VIEWPORT_START); - state->grph[1].viewport_size = INREG(AVIVO_D2MODE_VIEWPORT_SIZE); - state->grph[1].mode_data_format = INREG(AVIVO_D2MODE_DATA_FORMAT); - - if (IS_DCE3_VARIANT) { - /* save DVOA regs */ - state->dvoa[0] = INREG(0x7080); - state->dvoa[1] = INREG(0x7084); - state->dvoa[2] = INREG(0x708c); - state->dvoa[3] = INREG(0x7090); - state->dvoa[4] = INREG(0x7094); - state->dvoa[5] = INREG(0x70ac); - state->dvoa[6] = INREG(0x70b0); - - j = 0; - /* save DAC regs */ - for (i = 0x7000; i <= 0x7040; i += 4) { - state->daca[j] = INREG(i); - state->dacb[j] = INREG(i + 0x100); - j++; - } - for (i = 0x7058; i <= 0x7060; i += 4) { - state->daca[j] = INREG(i); - state->dacb[j] = INREG(i + 0x100); - j++; - } - for (i = 0x7068; i <= 0x706c; i += 4) { - state->daca[j] = INREG(i); - state->dacb[j] = INREG(i + 0x100); - j++; - } - for (i = 0x7ef0; i <= 0x7ef8; i += 4) { - state->daca[j] = INREG(i); - state->dacb[j] = INREG(i + 0x100); - j++; - } - state->daca[j] = INREG(0x7050); - state->dacb[j] = INREG(0x7050 + 0x100); - - j = 0; - /* save FMT regs */ - for (i = 0x6700; i <= 0x6744; i += 4) { - state->fmt1[j] = INREG(i); - state->fmt2[j] = INREG(i + 0x800); - j++; - } - - j = 0; - /* save DIG regs */ - for (i = 0x75a0; i <= 0x75e0; i += 4) { - state->dig1[j] = INREG(i); - state->dig2[j] = INREG(i + 0x400); - j++; - } - for (i = 0x75e8; i <= 0x75ec; i += 4) { - state->dig1[j] = INREG(i); - state->dig2[j] = INREG(i + 0x400); - j++; - } - - j = 0; - /* save HDMI regs */ - for (i = 0x7400; i <= 0x741c; i += 4) { - state->hdmi1[j] = INREG(i); - state->hdmi2[j] = INREG(i + 0x400); - j++; - } - for (i = 0x7430; i <= 0x74ec; i += 4) { - state->hdmi1[j] = INREG(i); - state->hdmi2[j] = INREG(i + 0x400); - j++; - } - state->hdmi1[j] = INREG(0x7428); - state->hdmi2[j] = INREG(0x7828); - - j = 0; - /* save AUX regs */ - for (i = 0x7780; i <= 0x77b4; i += 4) { - state->aux_cntl1[j] = INREG(i); - state->aux_cntl2[j] = INREG(i + 0x040); - state->aux_cntl3[j] = INREG(i + 0x400); - state->aux_cntl4[j] = INREG(i + 0x440); - if (IS_DCE32_VARIANT) { - state->aux_cntl5[j] = INREG(i + 0x500); - state->aux_cntl6[j] = INREG(i + 0x540); - } - j++; - } - - j = 0; - /* save UNIPHY regs */ - if (IS_DCE32_VARIANT) { - for (i = 0x7680; i <= 0x7690; i += 4) { - state->uniphy1[j] = INREG(i); - state->uniphy2[j] = INREG(i + 0x20); - state->uniphy3[j] = INREG(i + 0x400); - state->uniphy4[j] = INREG(i + 0x420); - state->uniphy5[j] = INREG(i + 0x840); - state->uniphy6[j] = INREG(i + 0x940); - j++; - } - for (i = 0x7698; i <= 0x769c; i += 4) { - state->uniphy1[j] = INREG(i); - state->uniphy2[j] = INREG(i + 0x20); - state->uniphy3[j] = INREG(i + 0x400); - state->uniphy4[j] = INREG(i + 0x420); - state->uniphy5[j] = INREG(i + 0x840); - state->uniphy6[j] = INREG(i + 0x940); - j++; - } - } else { - for (i = 0x7ec0; i <= 0x7edc; i += 4) { - state->uniphy1[j] = INREG(i); - state->uniphy2[j] = INREG(i + 0x100); - j++; - } - } - j = 0; - /* save PHY,LINK regs */ - for (i = 0x7f20; i <= 0x7f34; i += 4) { - state->phy[j] = INREG(i); - j++; - } - for (i = 0x7f9c; i <= 0x7fa4; i += 4) { - state->phy[j] = INREG(i); - j++; - } - state->phy[j] = INREG(0x7f40); - - j = 0; - /* save LVTMA regs */ - for (i = 0x7f00; i <= 0x7f1c; i += 4) { - state->lvtma[j] = INREG(i); - j++; - } - for (i = 0x7f80; i <= 0x7f98; i += 4) { - state->lvtma[j] = INREG(i); - j++; - } - } else { - j = 0; - /* save DVOA regs */ - for (i = 0x7980; i <= 0x79bc; i += 4) { - state->dvoa[j] = INREG(i); - j++; - } - - j = 0; - /* save DAC regs */ - for (i = 0x7800; i <= 0x782c; i += 4) { - state->daca[j] = INREG(i); - state->dacb[j] = INREG(i + 0x200); - j++; - } - for (i = 0x7834; i <= 0x7840; i += 4) { - state->daca[j] = INREG(i); - state->dacb[j] = INREG(i + 0x200); - j++; - } - for (i = 0x7850; i <= 0x7868; i += 4) { - state->daca[j] = INREG(i); - state->dacb[j] = INREG(i + 0x200); - j++; - } - - j = 0; - /* save TMDSA regs */ - for (i = 0x7880; i <= 0x78e0; i += 4) { - state->tmdsa[j] = INREG(i); - j++; - } - for (i = 0x7904; i <= 0x7918; i += 4) { - state->tmdsa[j] = INREG(i); - j++; - } - - j = 0; - /* save LVTMA regs */ - for (i = 0x7a80; i <= 0x7b18; i += 4) { - state->lvtma[j] = INREG(i); - j++; - } - - if ((info->ChipFamily == CHIP_FAMILY_RS600) || - (info->ChipFamily == CHIP_FAMILY_RS690) || - (info->ChipFamily == CHIP_FAMILY_RS740)) { - j = 0; - /* save DDIA regs */ - for (i = 0x7200; i <= 0x7290; i += 4) { - state->ddia[j] = INREG(i); - j++; - } - } - } - - /* scalers */ - j = 0; - for (i = 0x6578; i <= 0x65e4; i += 4) { - state->d1scl[j] = INREG(i); - state->d2scl[j] = INREG(i + 0x800); - j++; - } - for (i = 0x6600; i <= 0x662c; i += 4) { - state->d1scl[j] = INREG(i); - state->d2scl[j] = INREG(i + 0x800); - j++; - } - j = 0; - for (i = 0x66e8; i <= 0x66fc; i += 4) { - state->dxscl[j] = INREG(i); - j++; - } - state->dxscl[6] = INREG(0x6e30); - state->dxscl[7] = INREG(0x6e34); - - if (state->crtc[0].control & AVIVO_CRTC_EN) - info->crtc_on = TRUE; - - if (state->crtc[1].control & AVIVO_CRTC_EN) - info->crtc2_on = TRUE; - -} - -static void -avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - struct avivo_state *state = &restore->avivo; - int i, j; - - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "avivo_restore !\n"); - - /* Disable VGA control for now.. maybe needs to be changed */ - OUTREG(AVIVO_D1VGA_CONTROL, 0); - OUTREG(AVIVO_D2VGA_CONTROL, 0); - - /* Disable CRTCs */ - OUTREG(AVIVO_D1CRTC_CONTROL, - (INREG(AVIVO_D1CRTC_CONTROL) & ~0x300) | 0x01000000); - OUTREG(AVIVO_D2CRTC_CONTROL, - (INREG(AVIVO_D2CRTC_CONTROL) & ~0x300) | 0x01000000); - OUTREG(AVIVO_D1CRTC_CONTROL, - INREG(AVIVO_D1CRTC_CONTROL) & ~0x1); - OUTREG(AVIVO_D2CRTC_CONTROL, - INREG(AVIVO_D2CRTC_CONTROL) & ~0x1); - OUTREG(AVIVO_D1CRTC_CONTROL, - INREG(AVIVO_D1CRTC_CONTROL) | 0x100); - OUTREG(AVIVO_D2CRTC_CONTROL, - INREG(AVIVO_D2CRTC_CONTROL) | 0x100); - - /* Lock graph registers */ - OUTREG(AVIVO_D1GRPH_UPDATE, AVIVO_D1GRPH_UPDATE_LOCK); - OUTREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS, state->grph[0].prim_surf_addr); - OUTREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS, state->grph[0].sec_surf_addr); - OUTREG(AVIVO_D1GRPH_CONTROL, state->grph[0].control); - OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_X, state->grph[0].x_offset); - OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y, state->grph[0].y_offset); - OUTREG(AVIVO_D1GRPH_X_START, state->grph[0].x_start); - OUTREG(AVIVO_D1GRPH_Y_START, state->grph[0].y_start); - OUTREG(AVIVO_D1GRPH_X_END, state->grph[0].x_end); - OUTREG(AVIVO_D1GRPH_Y_END, state->grph[0].y_end); - OUTREG(AVIVO_D1GRPH_PITCH, state->grph[0].pitch); - OUTREG(AVIVO_D1GRPH_ENABLE, state->grph[0].enable); - OUTREG(AVIVO_D1GRPH_UPDATE, 0); - - OUTREG(AVIVO_D2GRPH_UPDATE, AVIVO_D1GRPH_UPDATE_LOCK); - OUTREG(AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS, state->grph[1].prim_surf_addr); - OUTREG(AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS, state->grph[1].sec_surf_addr); - OUTREG(AVIVO_D2GRPH_CONTROL, state->grph[1].control); - OUTREG(AVIVO_D2GRPH_SURFACE_OFFSET_X, state->grph[1].x_offset); - OUTREG(AVIVO_D2GRPH_SURFACE_OFFSET_Y, state->grph[1].y_offset); - OUTREG(AVIVO_D2GRPH_X_START, state->grph[1].x_start); - OUTREG(AVIVO_D2GRPH_Y_START, state->grph[1].y_start); - OUTREG(AVIVO_D2GRPH_X_END, state->grph[1].x_end); - OUTREG(AVIVO_D2GRPH_Y_END, state->grph[1].y_end); - OUTREG(AVIVO_D2GRPH_PITCH, state->grph[1].pitch); - OUTREG(AVIVO_D2GRPH_ENABLE, state->grph[1].enable); - OUTREG(AVIVO_D2GRPH_UPDATE, 0); - - /* Whack some mode regs too */ - OUTREG(AVIVO_D1SCL_UPDATE, AVIVO_D1SCL_UPDATE_LOCK); - OUTREG(AVIVO_D1MODE_DESKTOP_HEIGHT, state->grph[0].desktop_height); - OUTREG(AVIVO_D1MODE_VIEWPORT_START, state->grph[0].viewport_start); - OUTREG(AVIVO_D1MODE_VIEWPORT_SIZE, state->grph[0].viewport_size); - OUTREG(AVIVO_D1MODE_DATA_FORMAT, state->grph[0].mode_data_format); - OUTREG(AVIVO_D1SCL_UPDATE, 0); - - OUTREG(AVIVO_D2SCL_UPDATE, AVIVO_D1SCL_UPDATE_LOCK); - OUTREG(AVIVO_D2MODE_DESKTOP_HEIGHT, state->grph[1].desktop_height); - OUTREG(AVIVO_D2MODE_VIEWPORT_START, state->grph[1].viewport_start); - OUTREG(AVIVO_D2MODE_VIEWPORT_SIZE, state->grph[1].viewport_size); - OUTREG(AVIVO_D2MODE_DATA_FORMAT, state->grph[1].mode_data_format); - OUTREG(AVIVO_D2SCL_UPDATE, 0); - - /* Set the PLL */ - OUTREG(AVIVO_EXT1_PPLL_REF_DIV_SRC, state->pll[0].ref_div_src); - OUTREG(AVIVO_EXT1_PPLL_REF_DIV, state->pll[0].ref_div); - OUTREG(AVIVO_EXT1_PPLL_FB_DIV, state->pll[0].fb_div); - OUTREG(AVIVO_EXT1_PPLL_POST_DIV_SRC, state->pll[0].post_div_src); - OUTREG(AVIVO_EXT1_PPLL_POST_DIV, state->pll[0].post_div); - OUTREG(AVIVO_EXT1_PPLL_CNTL, state->pll[0].ext_ppll_cntl); - OUTREG(AVIVO_P1PLL_CNTL, state->pll[0].pll_cntl); - OUTREG(AVIVO_P1PLL_INT_SS_CNTL, state->pll[0].int_ss_cntl); - - OUTREG(AVIVO_EXT2_PPLL_REF_DIV_SRC, state->pll[1].ref_div_src); - OUTREG(AVIVO_EXT2_PPLL_REF_DIV, state->pll[1].ref_div); - OUTREG(AVIVO_EXT2_PPLL_FB_DIV, state->pll[1].fb_div); - OUTREG(AVIVO_EXT2_PPLL_POST_DIV_SRC, state->pll[1].post_div_src); - OUTREG(AVIVO_EXT2_PPLL_POST_DIV, state->pll[1].post_div); - OUTREG(AVIVO_EXT2_PPLL_CNTL, state->pll[1].ext_ppll_cntl); - OUTREG(AVIVO_P2PLL_CNTL, state->pll[1].pll_cntl); - OUTREG(AVIVO_P2PLL_INT_SS_CNTL, state->pll[1].int_ss_cntl); - - OUTREG(AVIVO_PCLK_CRTC1_CNTL, state->crtc[0].pll_source); - OUTREG(AVIVO_PCLK_CRTC2_CNTL, state->crtc[1].pll_source); - - /* Set the vga PLL */ - OUTREG(AVIVO_VGA25_PPLL_REF_DIV_SRC, state->vga25_ppll.ref_div_src); - OUTREG(AVIVO_VGA25_PPLL_REF_DIV, state->vga25_ppll.ref_div); - OUTREG(AVIVO_VGA25_PPLL_FB_DIV, state->vga25_ppll.fb_div); - OUTREG(AVIVO_VGA25_PPLL_POST_DIV_SRC, state->vga25_ppll.post_div_src); - OUTREG(AVIVO_VGA25_PPLL_POST_DIV, state->vga25_ppll.post_div); - OUTREG(AVIVO_VGA25_PPLL_CNTL, state->vga25_ppll.pll_cntl); - - OUTREG(AVIVO_VGA28_PPLL_REF_DIV_SRC, state->vga28_ppll.ref_div_src); - OUTREG(AVIVO_VGA28_PPLL_REF_DIV, state->vga28_ppll.ref_div); - OUTREG(AVIVO_VGA28_PPLL_FB_DIV, state->vga28_ppll.fb_div); - OUTREG(AVIVO_VGA28_PPLL_POST_DIV_SRC, state->vga28_ppll.post_div_src); - OUTREG(AVIVO_VGA28_PPLL_POST_DIV, state->vga28_ppll.post_div); - OUTREG(AVIVO_VGA28_PPLL_CNTL, state->vga28_ppll.pll_cntl); - - OUTREG(AVIVO_VGA41_PPLL_REF_DIV_SRC, state->vga41_ppll.ref_div_src); - OUTREG(AVIVO_VGA41_PPLL_REF_DIV, state->vga41_ppll.ref_div); - OUTREG(AVIVO_VGA41_PPLL_FB_DIV, state->vga41_ppll.fb_div); - OUTREG(AVIVO_VGA41_PPLL_POST_DIV_SRC, state->vga41_ppll.post_div_src); - OUTREG(AVIVO_VGA41_PPLL_POST_DIV, state->vga41_ppll.post_div); - OUTREG(AVIVO_VGA41_PPLL_CNTL, state->vga41_ppll.pll_cntl); - - /* Set the CRTC */ - OUTREG(AVIVO_D1CRTC_H_TOTAL, state->crtc[0].h_total); - OUTREG(AVIVO_D1CRTC_H_BLANK_START_END, state->crtc[0].h_blank_start_end); - OUTREG(AVIVO_D1CRTC_H_SYNC_A, state->crtc[0].h_sync_a); - OUTREG(AVIVO_D1CRTC_H_SYNC_A_CNTL, state->crtc[0].h_sync_a_cntl); - OUTREG(AVIVO_D1CRTC_H_SYNC_B, state->crtc[0].h_sync_b); - OUTREG(AVIVO_D1CRTC_H_SYNC_B_CNTL, state->crtc[0].h_sync_b_cntl); - - OUTREG(AVIVO_D1CRTC_V_TOTAL, state->crtc[0].v_total); - OUTREG(AVIVO_D1CRTC_V_BLANK_START_END, state->crtc[0].v_blank_start_end); - OUTREG(AVIVO_D1CRTC_V_SYNC_A, state->crtc[0].v_sync_a); - OUTREG(AVIVO_D1CRTC_V_SYNC_A_CNTL, state->crtc[0].v_sync_a_cntl); - OUTREG(AVIVO_D1CRTC_V_SYNC_B, state->crtc[0].v_sync_b); - OUTREG(AVIVO_D1CRTC_V_SYNC_B_CNTL, state->crtc[0].v_sync_b_cntl); - - OUTREG(AVIVO_D1CRTC_INTERLACE_CONTROL, state->crtc[0].interlace_control); - OUTREG(AVIVO_D1CRTC_STEREO_CONTROL, state->crtc[0].stereo_control); - - OUTREG(AVIVO_D1CUR_CONTROL, state->crtc[0].cursor_control); - - /* XXX Fix scaler */ - - OUTREG(AVIVO_D2CRTC_H_TOTAL, state->crtc[1].h_total); - OUTREG(AVIVO_D2CRTC_H_BLANK_START_END, state->crtc[1].h_blank_start_end); - OUTREG(AVIVO_D2CRTC_H_SYNC_A, state->crtc[1].h_sync_a); - OUTREG(AVIVO_D2CRTC_H_SYNC_A_CNTL, state->crtc[1].h_sync_a_cntl); - OUTREG(AVIVO_D2CRTC_H_SYNC_B, state->crtc[1].h_sync_b); - OUTREG(AVIVO_D2CRTC_H_SYNC_B_CNTL, state->crtc[1].h_sync_b_cntl); - - OUTREG(AVIVO_D2CRTC_V_TOTAL, state->crtc[1].v_total); - OUTREG(AVIVO_D2CRTC_V_BLANK_START_END, state->crtc[1].v_blank_start_end); - OUTREG(AVIVO_D2CRTC_V_SYNC_A, state->crtc[1].v_sync_a); - OUTREG(AVIVO_D2CRTC_V_SYNC_A_CNTL, state->crtc[1].v_sync_a_cntl); - OUTREG(AVIVO_D2CRTC_V_SYNC_B, state->crtc[1].v_sync_b); - OUTREG(AVIVO_D2CRTC_V_SYNC_B_CNTL, state->crtc[1].v_sync_b_cntl); - - OUTREG(AVIVO_D2CRTC_INTERLACE_CONTROL, state->crtc[1].interlace_control); - OUTREG(AVIVO_D2CRTC_STEREO_CONTROL, state->crtc[1].stereo_control); - - OUTREG(AVIVO_D2CUR_CONTROL, state->crtc[1].cursor_control); - - if (IS_DCE3_VARIANT) { - /* DVOA regs */ - OUTREG(0x7080, state->dvoa[0]); - OUTREG(0x7084, state->dvoa[1]); - OUTREG(0x708c, state->dvoa[2]); - OUTREG(0x7090, state->dvoa[3]); - OUTREG(0x7094, state->dvoa[4]); - OUTREG(0x70ac, state->dvoa[5]); - OUTREG(0x70b0, state->dvoa[6]); - - j = 0; - /* DAC regs */ - for (i = 0x7000; i <= 0x7040; i += 4) { - OUTREG(i, state->daca[j]); - OUTREG((i + 0x100), state->dacb[j]); - j++; - } - for (i = 0x7058; i <= 0x7060; i += 4) { - OUTREG(i, state->daca[j]); - OUTREG((i + 0x100), state->dacb[j]); - j++; - } - for (i = 0x7068; i <= 0x706c; i += 4) { - OUTREG(i, state->daca[j]); - OUTREG((i + 0x100), state->dacb[j]); - j++; - } - for (i = 0x7ef0; i <= 0x7ef8; i += 4) { - OUTREG(i, state->daca[j]); - OUTREG((i + 0x100), state->dacb[j]); - j++; - } - OUTREG(0x7050, state->daca[j]); - OUTREG((0x7050 + 0x100), state->dacb[j]); - - j = 0; - /* FMT regs */ - for (i = 0x6700; i <= 0x6744; i += 4) { - OUTREG(i, state->fmt1[j]); - OUTREG((i + 0x800), state->fmt2[j]); - j++; - } - - j = 0; - /* DIG regs */ - for (i = 0x75a0; i <= 0x75e0; i += 4) { - OUTREG(i, state->dig1[j]); - OUTREG((i + 0x400), state->dig2[j]); - j++; - } - for (i = 0x75e8; i <= 0x75ec; i += 4) { - OUTREG(i, state->dig1[j]); - OUTREG((i + 0x400), state->dig2[j]); - j++; - } - - j = 0; - /* HDMI regs */ - for (i = 0x7400; i <= 0x741c; i += 4) { - OUTREG(i, state->hdmi1[j]); - OUTREG((i + 0x400), state->hdmi2[j]); - j++; - } - for (i = 0x7430; i <= 0x74ec; i += 4) { - OUTREG(i, state->hdmi1[j]); - OUTREG((i + 0x400), state->hdmi2[j]); - j++; - } - OUTREG(0x7428, state->hdmi1[j]); - OUTREG((0x7428 + 0x400), state->hdmi2[j]); - - j = 0; - /* save AUX regs */ - for (i = 0x7780; i <= 0x77b4; i += 4) { - OUTREG(i, state->aux_cntl1[j]); - OUTREG((i + 0x040), state->aux_cntl2[j]); - OUTREG((i + 0x400), state->aux_cntl3[j]); - OUTREG((i + 0x440), state->aux_cntl4[j]); - if (IS_DCE32_VARIANT) { - OUTREG((i + 0x500), state->aux_cntl5[j]); - OUTREG((i + 0x540), state->aux_cntl6[j]); - } - j++; - } - - j = 0; - /* save UNIPHY regs */ - if (IS_DCE32_VARIANT) { - for (i = 0x7680; i <= 0x7690; i += 4) { - OUTREG(i, state->uniphy1[j]); - OUTREG((i + 0x20), state->uniphy2[j]); - OUTREG((i + 0x400), state->uniphy3[j]); - OUTREG((i + 0x420), state->uniphy4[j]); - OUTREG((i + 0x840), state->uniphy5[j]); - OUTREG((i + 0x940), state->uniphy6[j]); - j++; - } - for (i = 0x7698; i <= 0x769c; i += 4) { - OUTREG(i, state->uniphy1[j]); - OUTREG((i + 0x20), state->uniphy2[j]); - OUTREG((i + 0x400), state->uniphy3[j]); - OUTREG((i + 0x420), state->uniphy4[j]); - OUTREG((i + 0x840), state->uniphy5[j]); - OUTREG((i + 0x940), state->uniphy6[j]); - j++; - } - } else { - for (i = 0x7ec0; i <= 0x7edc; i += 4) { - OUTREG(i, state->uniphy1[j]); - OUTREG((i + 0x100), state->uniphy2[j]); - j++; - } - } - j = 0; - /* save PHY,LINK regs */ - for (i = 0x7f20; i <= 0x7f34; i += 4) { - OUTREG(i, state->phy[j]); - j++; - } - for (i = 0x7f9c; i <= 0x7fa4; i += 4) { - OUTREG(i, state->phy[j]); - j++; - } - state->phy[j] = INREG(0x7f40); - - j = 0; - /* save LVTMA regs */ - for (i = 0x7f00; i <= 0x7f1c; i += 4) { - OUTREG(i, state->lvtma[j]); - j++; - } - for (i = 0x7f80; i <= 0x7f98; i += 4) { - OUTREG(i, state->lvtma[j]); - j++; - } - } else { - j = 0; - /* DVOA regs */ - for (i = 0x7980; i <= 0x79bc; i += 4) { - OUTREG(i, state->dvoa[j]); - j++; - } - - j = 0; - /* DAC regs */ /* -- MIGHT NEED ORDERING FIX & DELAYS -- */ - for (i = 0x7800; i <= 0x782c; i += 4) { - OUTREG(i, state->daca[j]); - OUTREG((i + 0x200), state->dacb[j]); - j++; - } - for (i = 0x7834; i <= 0x7840; i += 4) { - OUTREG(i, state->daca[j]); - OUTREG((i + 0x200), state->dacb[j]); - j++; - } - for (i = 0x7850; i <= 0x7868; i += 4) { - OUTREG(i, state->daca[j]); - OUTREG((i + 0x200), state->dacb[j]); - j++; - } - - j = 0; - /* TMDSA regs */ - for (i = 0x7880; i <= 0x78e0; i += 4) { - OUTREG(i, state->tmdsa[j]); - j++; - } - for (i = 0x7904; i <= 0x7918; i += 4) { - OUTREG(i, state->tmdsa[j]); - j++; - } - - j = 0; - /* LVTMA regs */ - for (i = 0x7a80; i <= 0x7b18; i += 4) { - OUTREG(i, state->lvtma[j]); - j++; - } - - /* DDIA regs */ - if ((info->ChipFamily == CHIP_FAMILY_RS600) || - (info->ChipFamily == CHIP_FAMILY_RS690) || - (info->ChipFamily == CHIP_FAMILY_RS740)) { - j = 0; - for (i = 0x7200; i <= 0x7290; i += 4) { - OUTREG(i, state->ddia[j]); - j++; - } - } - } - - /* scalers */ - j = 0; - for (i = 0x6578; i <= 0x65e4; i += 4) { - OUTREG(i, state->d1scl[j]); - OUTREG((i + 0x800), state->d2scl[j]); - j++; - } - for (i = 0x6600; i <= 0x662c; i += 4) { - OUTREG(i, state->d1scl[j]); - OUTREG((i + 0x800), state->d2scl[j]); - j++; - } - j = 0; - for (i = 0x66e8; i <= 0x66fc; i += 4) { - OUTREG(i, state->dxscl[j]); - j++; - } - OUTREG(0x6e30, state->dxscl[6]); - OUTREG(0x6e34, state->dxscl[7]); - - /* Enable CRTCs */ - if (state->crtc[0].control & 1) { - OUTREG(AVIVO_D1CRTC_CONTROL, 0x01000101); - INREG(AVIVO_D1CRTC_CONTROL); - OUTREG(AVIVO_D1CRTC_CONTROL, 0x00010101); - } - if (state->crtc[1].control & 1) { - OUTREG(AVIVO_D2CRTC_CONTROL, 0x01000101); - INREG(AVIVO_D2CRTC_CONTROL); - OUTREG(AVIVO_D2CRTC_CONTROL, 0x00010101); - } - - /* Where should that go ? */ - OUTREG(AVIVO_DC_CRTC_TV_CONTROL, state->crtc_tv_control); - OUTREG(AVIVO_DC_LB_MEMORY_SPLIT, state->dc_lb_memory_split); - - /* Need fixing too ? */ - OUTREG(AVIVO_D1CRTC_BLANK_CONTROL, state->crtc[0].blank_control); - OUTREG(AVIVO_D2CRTC_BLANK_CONTROL, state->crtc[1].blank_control); - - /* Dbl check */ - OUTREG(AVIVO_VGA_RENDER_CONTROL, state->vga_render_control); - OUTREG(AVIVO_D1VGA_CONTROL, state->vga1_cntl); - OUTREG(AVIVO_D2VGA_CONTROL, state->vga2_cntl); - - /* Should only enable outputs here */ -} - -static void avivo_restore_vga_regs(ScrnInfoPtr pScrn, RADEONSavePtr restore) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - struct avivo_state *state = &restore->avivo; - - OUTREG(AVIVO_VGA_RENDER_CONTROL, state->vga_render_control); - OUTREG(AVIVO_D1VGA_CONTROL, state->vga1_cntl); - OUTREG(AVIVO_D2VGA_CONTROL, state->vga2_cntl); -} - -static void dce4_restore_vga_regs(ScrnInfoPtr pScrn, RADEONSavePtr restore) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - struct dce4_state *state = &restore->dce4; - - OUTREG(AVIVO_VGA_RENDER_CONTROL, state->vga_render_control); - OUTREG(AVIVO_D1VGA_CONTROL, state->vga1_cntl); - OUTREG(AVIVO_D2VGA_CONTROL, state->vga2_cntl); - OUTREG(EVERGREEN_D3VGA_CONTROL, state->vga3_cntl); - OUTREG(EVERGREEN_D4VGA_CONTROL, state->vga4_cntl); - OUTREG(EVERGREEN_D5VGA_CONTROL, state->vga5_cntl); - OUTREG(EVERGREEN_D6VGA_CONTROL, state->vga6_cntl); -} - - -static void -RADEONRestoreBIOSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - if (info->ChipFamily >= CHIP_FAMILY_R600) { - OUTREG(R600_BIOS_0_SCRATCH, restore->bios_0_scratch); - OUTREG(R600_BIOS_1_SCRATCH, restore->bios_1_scratch); - OUTREG(R600_BIOS_2_SCRATCH, restore->bios_2_scratch); - OUTREG(R600_BIOS_3_SCRATCH, restore->bios_3_scratch); - OUTREG(R600_BIOS_4_SCRATCH, restore->bios_4_scratch); - OUTREG(R600_BIOS_5_SCRATCH, restore->bios_5_scratch); - OUTREG(R600_BIOS_6_SCRATCH, restore->bios_6_scratch); - OUTREG(R600_BIOS_7_SCRATCH, restore->bios_7_scratch); - } else { - OUTREG(RADEON_BIOS_0_SCRATCH, restore->bios_0_scratch); - OUTREG(RADEON_BIOS_1_SCRATCH, restore->bios_1_scratch); - OUTREG(RADEON_BIOS_2_SCRATCH, restore->bios_2_scratch); - OUTREG(RADEON_BIOS_3_SCRATCH, restore->bios_3_scratch); - OUTREG(RADEON_BIOS_4_SCRATCH, restore->bios_4_scratch); - OUTREG(RADEON_BIOS_5_SCRATCH, restore->bios_5_scratch); - OUTREG(RADEON_BIOS_6_SCRATCH, restore->bios_6_scratch); - OUTREG(RADEON_BIOS_7_SCRATCH, restore->bios_7_scratch); - } -} - -static void -RADEONSaveBIOSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - if (info->ChipFamily >= CHIP_FAMILY_R600) { - save->bios_0_scratch = INREG(R600_BIOS_0_SCRATCH); - save->bios_1_scratch = INREG(R600_BIOS_1_SCRATCH); - save->bios_2_scratch = INREG(R600_BIOS_2_SCRATCH); - save->bios_3_scratch = INREG(R600_BIOS_3_SCRATCH); - save->bios_4_scratch = INREG(R600_BIOS_4_SCRATCH); - save->bios_5_scratch = INREG(R600_BIOS_5_SCRATCH); - save->bios_6_scratch = INREG(R600_BIOS_6_SCRATCH); - save->bios_7_scratch = INREG(R600_BIOS_7_SCRATCH); - } else { - save->bios_0_scratch = INREG(RADEON_BIOS_0_SCRATCH); - save->bios_1_scratch = INREG(RADEON_BIOS_1_SCRATCH); - save->bios_2_scratch = INREG(RADEON_BIOS_2_SCRATCH); - save->bios_3_scratch = INREG(RADEON_BIOS_3_SCRATCH); - save->bios_4_scratch = INREG(RADEON_BIOS_4_SCRATCH); - save->bios_5_scratch = INREG(RADEON_BIOS_5_SCRATCH); - save->bios_6_scratch = INREG(RADEON_BIOS_6_SCRATCH); - save->bios_7_scratch = INREG(RADEON_BIOS_7_SCRATCH); - } -} - -void radeon_save_palette_on_demand(ScrnInfoPtr pScrn, int palID) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONSavePtr save = info->SavedReg; - - if (save->palette_saved[palID] == TRUE) - return; - - if (!IS_AVIVO_VARIANT) - RADEONSavePalette(pScrn, palID, save); - - save->palette_saved[palID] = TRUE; -} - -/* Save everything needed to restore the original VC state */ -static void RADEONSave(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - RADEONSavePtr save = info->SavedReg; - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "RADEONSave\n"); - -#ifdef WITH_VGAHW - if (info->VGAAccess) { - vgaHWPtr hwp = VGAHWPTR(pScrn); - - vgaHWUnlock(hwp); -# if defined(__powerpc__) - /* temporary hack to prevent crashing on PowerMacs when trying to - * read VGA fonts and colormap, will find a better solution - * in the future. TODO: Check if there's actually some VGA stuff - * setup in the card at all !! - */ - vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_MODE); /* Save mode only */ -# else - /* Save only mode * & fonts */ - vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_MODE | VGA_SR_FONTS ); -# endif - vgaHWLock(hwp); - } -#endif - - if (IS_DCE4_VARIANT) { - RADEONSaveMemMapRegisters(pScrn, save); - dce4_save(pScrn, save); - //XXX - } else if (IS_AVIVO_VARIANT) { - RADEONSaveMemMapRegisters(pScrn, save); - avivo_save(pScrn, save); - } else { - save->dp_datatype = INREG(RADEON_DP_DATATYPE); - save->rbbm_soft_reset = INREG(RADEON_RBBM_SOFT_RESET); - save->clock_cntl_index = INREG(RADEON_CLOCK_CNTL_INDEX); - RADEONPllErrataAfterIndex(info); - - RADEONSaveMemMapRegisters(pScrn, save); - RADEONSaveCommonRegisters(pScrn, save); - RADEONSavePLLRegisters(pScrn, save); - RADEONSaveCrtcRegisters(pScrn, save); - RADEONSaveFPRegisters(pScrn, save); - RADEONSaveDACRegisters(pScrn, save); - /* Palette saving is done on demand now */ - - if (pRADEONEnt->HasCRTC2) { - RADEONSaveCrtc2Registers(pScrn, save); - RADEONSavePLL2Registers(pScrn, save); - } - if (info->InternalTVOut) - RADEONSaveTVRegisters(pScrn, save); - } - - if (info->ChipFamily < CHIP_FAMILY_R600) - RADEONSaveSurfaces(pScrn, save); - -} - -/* Restore the original (text) mode */ -static void RADEONRestore(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - RADEONSavePtr restore = info->SavedReg; - xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); - xf86CrtcPtr crtc; - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "RADEONRestore\n"); - -#if X_BYTE_ORDER == X_BIG_ENDIAN - if (info->ChipFamily < CHIP_FAMILY_R600) { - RADEONWaitForFifo(pScrn, 1); - OUTREG(RADEON_RBBM_GUICNTL, RADEON_HOST_DATA_SWAP_NONE); - } -#endif - - RADEONBlank(pScrn); - - if (IS_DCE4_VARIANT) { - RADEONRestoreMemMapRegisters(pScrn, restore); - dce4_restore(pScrn, restore); - //XXX - } else if (IS_AVIVO_VARIANT) { - RADEONRestoreMemMapRegisters(pScrn, restore); - avivo_restore(pScrn, restore); - } else { - OUTREG(RADEON_RBBM_SOFT_RESET, restore->rbbm_soft_reset); - OUTREG(RADEON_DP_DATATYPE, restore->dp_datatype); - OUTREG(RADEON_GRPH_BUFFER_CNTL, restore->grph_buffer_cntl); - OUTREG(RADEON_GRPH2_BUFFER_CNTL, restore->grph2_buffer_cntl); - - if (!info->IsSecondary) { - RADEONRestoreMemMapRegisters(pScrn, restore); - RADEONRestoreCommonRegisters(pScrn, restore); - - RADEONRestorePalette(pScrn, restore); - if (pRADEONEnt->HasCRTC2) { - RADEONRestoreCrtc2Registers(pScrn, restore); - RADEONRestorePLL2Registers(pScrn, restore); - } - - RADEONRestoreCrtcRegisters(pScrn, restore); - RADEONRestorePLLRegisters(pScrn, restore); - RADEONRestoreRMXRegisters(pScrn, restore); - RADEONRestoreFPRegisters(pScrn, restore); - RADEONRestoreFP2Registers(pScrn, restore); - RADEONRestoreLVDSRegisters(pScrn, restore); - - if (info->InternalTVOut) - RADEONRestoreTVRegisters(pScrn, restore); - } - - OUTREG(RADEON_CLOCK_CNTL_INDEX, restore->clock_cntl_index); - RADEONPllErrataAfterIndex(info); - - RADEONRestoreBIOSRegisters(pScrn, restore); - } - - -#if 1 - /* Temp fix to "solve" VT switch problems. When switching VTs on - * some systems, the console can either hang or the fonts can be - * corrupted. This hack solves the problem 99% of the time. A - * correct fix is being worked on. - */ - usleep(100000); -#endif - - if (info->ChipFamily < CHIP_FAMILY_R600) - RADEONRestoreSurfaces(pScrn, restore); - - /* need to make sure we don't enable a crtc by accident or we may get a hang */ - if (pRADEONEnt->HasCRTC2 && !info->IsSecondary) { - if (info->crtc2_on && xf86_config->num_crtc > 1) { - crtc = xf86_config->crtc[1]; - radeon_do_crtc_dpms(crtc, DPMSModeOn); - } - } - if (info->crtc_on) { - crtc = xf86_config->crtc[0]; - radeon_do_crtc_dpms(crtc, DPMSModeOn); - } - -#ifdef WITH_VGAHW - if (info->VGAAccess) { - vgaHWPtr hwp = VGAHWPTR(pScrn); - vgaHWUnlock(hwp); -# if defined(__powerpc__) - /* Temporary hack to prevent crashing on PowerMacs when trying to - * write VGA fonts, will find a better solution in the future - */ - vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_MODE ); -# else - vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_MODE | VGA_SR_FONTS ); -# endif - vgaHWLock(hwp); - } -#endif - - /* to restore console mode, DAC registers should be set after every other registers are set, - * otherwise,we may get blank screen - */ - if (IS_DCE4_VARIANT) - dce4_restore_vga_regs(pScrn, restore); - else if (IS_AVIVO_VARIANT) - avivo_restore_vga_regs(pScrn, restore); - else { - RADEONRestoreDACRegisters(pScrn, restore); - } -#if 0 - RADEONWaitForVerticalSync(pScrn); -#endif -} - -static Bool RADEONSaveScreen(ScreenPtr pScreen, int mode) -{ - ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); - Bool unblank; - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "RADEONSaveScreen(%d)\n", mode); - - unblank = xf86IsUnblank(mode); - if (unblank) SetTimeSinceLastInputEvent(); - - if ((pScrn != NULL) && pScrn->vtSema) { - if (unblank) - RADEONUnblank(pScrn); - else - RADEONBlank(pScrn); - } - return TRUE; -} - -Bool RADEONSwitchMode(SWITCH_MODE_ARGS_DECL) -{ - SCRN_INFO_PTR(arg); - RADEONInfoPtr info = RADEONPTR(pScrn); - Bool tilingOld = info->tilingEnabled; - Bool ret; -#ifdef XF86DRI - Bool CPStarted = info->cp->CPStarted; - - if (CPStarted) { - DRILock(pScrn->pScreen, 0); - RADEONCP_STOP(pScrn, info); - } -#endif - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "RADEONSwitchMode() !n"); - - if (info->allowColorTiling) { - info->tilingEnabled = (mode->Flags & (V_DBLSCAN | V_INTERLACE)) ? FALSE : TRUE; -#ifdef XF86DRI - if (info->directRenderingEnabled && (info->tilingEnabled != tilingOld)) { - drm_radeon_sarea_t *pSAREAPriv; - if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_SWITCH_TILING, (info->tilingEnabled ? 1 : 0)) < 0) - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "[drm] failed changing tiling status\n"); - pSAREAPriv = DRIGetSAREAPrivate(pScrn->pScreen); - info->tilingEnabled = pSAREAPriv->tiling_enabled ? TRUE : FALSE; - } -#endif - } - - if (info->accelOn) - RADEON_SYNC(info, pScrn); - - ret = xf86SetSingleMode (pScrn, mode, RR_Rotate_0); - - if (info->tilingEnabled != tilingOld) { - /* need to redraw front buffer, I guess this can be considered a hack ? */ - xf86EnableDisableFBAccess(arg, FALSE); - RADEONChangeSurfaces(pScrn); - xf86EnableDisableFBAccess(arg, TRUE); - /* xf86SetRootClip would do, but can't access that here */ - } - - if (info->accelOn) { - RADEON_SYNC(info, pScrn); - if (info->ChipFamily < CHIP_FAMILY_R600) - RADEONEngineRestore(pScrn); - } - -#ifdef XF86DRI - if (CPStarted) { - RADEONCP_START(pScrn, info); - DRIUnlock(pScrn->pScreen); - } -#endif - - /* reset ecp for overlay */ - info->ecp_div = -1; - - return ret; -} - #ifdef X_XF86MiscPassMessage Bool RADEONHandleMessage(int scrnIndex, const char* msgtype, const char* msgval, char** retmsg) @@ -6047,472 +299,3 @@ xf86ModeBandwidth(DisplayModePtr mode, int depth) } #endif -/* Used to disallow modes that are not supported by the hardware */ -ModeStatus RADEONValidMode(SCRN_ARG_TYPE arg, DisplayModePtr mode, - Bool verbose, int flag) -{ - SCRN_INFO_PTR(arg); - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); - - /* - * RN50 has effective maximum mode bandwidth of about 300MiB/s. - * XXX should really do this for all chips by properly computing - * memory bandwidth and an overhead factor. - */ - if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2) { - if (xf86ModeBandwidth(mode, pScrn->bitsPerPixel) > 300) - return MODE_BANDWIDTH; - } - - /* There are problems with double scan mode at high clocks - * They're likely related PLL and display buffer settings. - * Disable these modes for now. - */ - if (mode->Flags & V_DBLSCAN) { - if ((mode->CrtcHDisplay >= 1024) || (mode->CrtcVDisplay >= 768)) - return MODE_CLOCK_RANGE; - } - return MODE_OK; -} - -/* Adjust viewport into virtual desktop such that (0,0) in viewport - * space is (x,y) in virtual space. - */ -void RADEONDoAdjustFrame(ScrnInfoPtr pScrn, int x, int y, Bool crtc2) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - int Base, reg, regcntl, crtcoffsetcntl, xytilereg, crtcxytile = 0; -#ifdef XF86DRI - drm_radeon_sarea_t *pSAREAPriv; - XF86DRISAREAPtr pSAREA; -#endif - -#if 0 /* Verbose */ - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "RADEONDoAdjustFrame(%d,%d,%d)\n", x, y, clone); -#endif - - Base = pScrn->fbOffset; - - /* note we cannot really simply use the info->ModeReg.crtc_offset_cntl value, since the - drm might have set FLIP_CNTL since we wrote that. Unfortunately FLIP_CNTL causes - flickering when scrolling vertically in a virtual screen, possibly because crtc will - pick up the new offset value at the end of each scanline, but the new offset_cntl value - only after a vsync. We'd probably need to wait (in drm) for vsync and only then update - OFFSET and OFFSET_CNTL, if the y coord has changed. Seems hard to fix. */ - if (crtc2) { - reg = RADEON_CRTC2_OFFSET; - regcntl = RADEON_CRTC2_OFFSET_CNTL; - xytilereg = R300_CRTC2_TILE_X0_Y0; - } else { - reg = RADEON_CRTC_OFFSET; - regcntl = RADEON_CRTC_OFFSET_CNTL; - xytilereg = R300_CRTC_TILE_X0_Y0; - } - crtcoffsetcntl = INREG(regcntl) & ~0xf; -#if 0 - /* try to get rid of flickering when scrolling at least for 2d */ -#ifdef XF86DRI - if (!info->dri->have3DWindows) -#endif - crtcoffsetcntl &= ~RADEON_CRTC_OFFSET_FLIP_CNTL; -#endif - if (info->tilingEnabled) { - if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { - /* On r300/r400 when tiling is enabled crtc_offset is set to the address of - * the surface. the x/y offsets are handled by the X_Y tile reg for each crtc - * Makes tiling MUCH easier. - */ - crtcxytile = x | (y << 16); - Base &= ~0x7ff; - } else { - int byteshift = info->CurrentLayout.bitsPerPixel >> 4; - /* crtc uses 256(bytes)x8 "half-tile" start addresses? */ - int tile_addr = (((y >> 3) * info->CurrentLayout.displayWidth + x) >> (8 - byteshift)) << 11; - Base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8); - crtcoffsetcntl = crtcoffsetcntl | (y % 16); - } - } - else { - int offset = y * info->CurrentLayout.displayWidth + x; - switch (info->CurrentLayout.pixel_code) { - case 15: - case 16: offset *= 2; break; - case 24: offset *= 3; break; - case 32: offset *= 4; break; - } - Base += offset; - } - - Base &= ~7; /* 3 lower bits are always 0 */ - -#ifdef XF86DRI - if (info->directRenderingInited) { - /* note cannot use pScrn->pScreen since this is unitialized when called from - RADEONScreenInit, and we need to call from there to get mergedfb + pageflip working */ - /*** NOTE: r3/4xx will need sarea and drm pageflip updates to handle the xytile regs for - *** pageflipping! - ***/ - pSAREAPriv = DRIGetSAREAPrivate(xf86ScrnToScreen(pScrn)); - /* can't get at sarea in a semi-sane way? */ - pSAREA = (void *)((char*)pSAREAPriv - sizeof(XF86DRISAREARec)); - - if (crtc2) { - pSAREAPriv->crtc2_base = Base; - } - else { - pSAREA->frame.x = (Base / info->CurrentLayout.pixel_bytes) - % info->CurrentLayout.displayWidth; - pSAREA->frame.y = (Base / info->CurrentLayout.pixel_bytes) - / info->CurrentLayout.displayWidth; - pSAREA->frame.width = pScrn->frameX1 - x + 1; - pSAREA->frame.height = pScrn->frameY1 - y + 1; - } - - if (pSAREAPriv->pfCurrentPage == 1) { - Base += info->dri->backOffset - info->dri->frontOffset; - } - } -#endif - - if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { - OUTREG(xytilereg, crtcxytile); - } else { - OUTREG(regcntl, crtcoffsetcntl); - } - - OUTREG(reg, Base); -} - -void RADEONAdjustFrame(ADJUST_FRAME_ARGS_DECL) -{ - SCRN_INFO_PTR(arg); - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); - xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); - xf86OutputPtr output = config->output[config->compat_output]; - xf86CrtcPtr crtc = output->crtc; - - /* not handled */ - if (IS_AVIVO_VARIANT) - return; - -#ifdef XF86DRI - if (info->cp->CPStarted && pScrn->pScreen) DRILock(pScrn->pScreen, 0); -#endif - - if (info->accelOn) - RADEON_SYNC(info, pScrn); - - if (crtc && crtc->enabled) { - if (crtc == pRADEONEnt->pCrtc[0]) - RADEONDoAdjustFrame(pScrn, crtc->desiredX + x, crtc->desiredY + y, FALSE); - else - RADEONDoAdjustFrame(pScrn, crtc->desiredX + x, crtc->desiredY + y, TRUE); - crtc->x = output->initial_x + x; - crtc->y = output->initial_y + y; - } - - -#ifdef XF86DRI - if (info->cp->CPStarted && pScrn->pScreen) DRIUnlock(pScrn->pScreen); -#endif -} - -/* Called when VT switching back to the X server. Reinitialize the - * video mode. - */ -Bool RADEONEnterVT(VT_FUNC_ARGS_DECL) -{ - SCRN_INFO_PTR(arg); - RADEONInfoPtr info = RADEONPTR(pScrn); - xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); - int i; - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "RADEONEnterVT\n"); - - if (!radeon_card_posted(pScrn)) { /* Softboot V_BIOS */ - if (info->IsAtomBios) { - rhdAtomASICInit(info->atomBIOS); - } else { - xf86Int10InfoPtr pInt; - - pInt = xf86InitInt10 (info->pEnt->index); - if (pInt) { - pInt->num = 0xe6; - xf86ExecX86int10 (pInt); - xf86FreeInt10 (pInt); - } else { - RADEONGetBIOSInitTableOffsets(pScrn); - RADEONPostCardFromBIOSTables(pScrn); - } - } - } - - /* Makes sure the engine is idle before doing anything */ - RADEONWaitForIdleMMIO(pScrn); - - RADEONPMEnterVT(pScrn); - - for (i = 0; i < config->num_crtc; i++) - radeon_crtc_modeset_ioctl(config->crtc[i], TRUE); - - pScrn->vtSema = TRUE; - - /* Clear the framebuffer */ - memset(info->FB + pScrn->fbOffset, 0, - pScrn->virtualY * pScrn->displayWidth * info->CurrentLayout.pixel_bytes); - - if (!xf86SetDesiredModes(pScrn)) - return FALSE; - - if (info->ChipFamily < CHIP_FAMILY_R600) - RADEONRestoreSurfaces(pScrn, info->ModeReg); -#ifdef XF86DRI - if (info->directRenderingEnabled) { - if (info->cardType == CARD_PCIE && - info->dri->pKernelDRMVersion->version_minor >= 19 && - info->FbSecureSize) { -#if X_BYTE_ORDER == X_BIG_ENDIAN - unsigned char *RADEONMMIO = info->MMIO; - unsigned int sctrl = INREG(RADEON_SURFACE_CNTL); - - /* we need to backup the PCIE GART TABLE from fb memory */ - OUTREG(RADEON_SURFACE_CNTL, 0); -#endif - memcpy(info->FB + info->dri->pciGartOffset, info->dri->pciGartBackup, info->dri->pciGartSize); -#if X_BYTE_ORDER == X_BIG_ENDIAN - OUTREG(RADEON_SURFACE_CNTL, sctrl); -#endif - } - - /* get the DRI back into shape after resume */ - RADEONDRISetVBlankInterrupt (pScrn, TRUE); - RADEONDRIResume(pScrn->pScreen); - RADEONAdjustMemMapRegisters(pScrn, info->ModeReg); - - } -#endif - /* this will get XVideo going again, but only if XVideo was initialised - during server startup (hence the info->adaptor if). */ - if (info->adaptor) - RADEONResetVideo(pScrn); - - if (info->accelOn && (info->ChipFamily < CHIP_FAMILY_R600)) - RADEONEngineRestore(pScrn); - - if (info->accelOn && info->accel_state) - info->accel_state->XInited3D = FALSE; - -#ifdef XF86DRI - if (info->directRenderingEnabled) { - if (info->ChipFamily >= CHIP_FAMILY_R600) - R600LoadShaders(pScrn); - RADEONCP_START(pScrn, info); - DRIUnlock(pScrn->pScreen); - } -#endif - if (IS_R500_3D || IS_R300_3D) - radeon_load_bicubic_texture(pScrn); - - return TRUE; -} - -/* Called when VT switching away from the X server. Restore the - * original text mode. - */ -void RADEONLeaveVT(VT_FUNC_ARGS_DECL) -{ - SCRN_INFO_PTR(arg); - RADEONInfoPtr info = RADEONPTR(pScrn); - xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); - int i; - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "RADEONLeaveVT\n"); -#ifdef XF86DRI - if (RADEONPTR(pScrn)->directRenderingInited) { - - RADEONDRISetVBlankInterrupt (pScrn, FALSE); - DRILock(pScrn->pScreen, 0); - RADEONCP_STOP(pScrn, info); - - if (info->cardType == CARD_PCIE && - info->dri->pKernelDRMVersion->version_minor >= 19 && - info->FbSecureSize) { -#if X_BYTE_ORDER == X_BIG_ENDIAN - unsigned char *RADEONMMIO = info->MMIO; - unsigned int sctrl = INREG(RADEON_SURFACE_CNTL); - - /* we need to backup the PCIE GART TABLE from fb memory */ - OUTREG(RADEON_SURFACE_CNTL, 0); -#endif - memcpy(info->dri->pciGartBackup, (info->FB + info->dri->pciGartOffset), info->dri->pciGartSize); -#if X_BYTE_ORDER == X_BIG_ENDIAN - OUTREG(RADEON_SURFACE_CNTL, sctrl); -#endif - } - - /* Make sure 3D clients will re-upload textures to video RAM */ - if (info->dri->textureSize) { - drm_radeon_sarea_t *pSAREAPriv = - (drm_radeon_sarea_t*)DRIGetSAREAPrivate(pScrn->pScreen); - struct drm_tex_region *list = pSAREAPriv->tex_list[0]; - int age = ++pSAREAPriv->tex_age[0]; - - i = 0; - - do { - list[i].age = age; - i = list[i].next; - } while (i != 0); - } - } -#endif - - - for (i = 0; i < config->num_crtc; i++) { - xf86CrtcPtr crtc = config->crtc[i]; - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - - radeon_crtc->initialized = FALSE; - -#ifndef HAVE_FREE_SHADOW - if (crtc->rotatedPixmap || crtc->rotatedData) { - crtc->funcs->shadow_destroy(crtc, crtc->rotatedPixmap, - crtc->rotatedData); - crtc->rotatedPixmap = NULL; - crtc->rotatedData = NULL; - } -#endif - } - -#ifdef HAVE_FREE_SHADOW - xf86RotateFreeShadow(pScrn); -#endif - - xf86_hide_cursors (pScrn); - - RADEONPMLeaveVT(pScrn); - - RADEONRestore(pScrn); - - for (i = 0; i < config->num_crtc; i++) - radeon_crtc_modeset_ioctl(config->crtc[i], FALSE); - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "Ok, leaving now...\n"); -} - -/* Called at the end of each server generation. Restore the original - * text mode, unmap video memory, and unwrap and call the saved - * CloseScreen function. - */ -static Bool RADEONCloseScreen(CLOSE_SCREEN_ARGS_DECL) -{ - ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); - RADEONInfoPtr info = RADEONPTR(pScrn); - xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); - int i; - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "RADEONCloseScreen\n"); - - RADEONPMFini(pScrn); - - /* Mark acceleration as stopped or we might try to access the engine at - * wrong times, especially if we had DRI, after DRI has been stopped - */ - info->accelOn = FALSE; - - for (i = 0; i < config->num_crtc; i++) { - xf86CrtcPtr crtc = config->crtc[i]; - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - - radeon_crtc->initialized = FALSE; - } - -#ifdef XF86DRI -#ifdef DAMAGE - if (info->dri && info->dri->pDamage) { - PixmapPtr pPix = pScreen->GetScreenPixmap(pScreen); - - DamageUnregister(&pPix->drawable, info->dri->pDamage); - DamageDestroy(info->dri->pDamage); - info->dri->pDamage = NULL; - } -#endif - - RADEONDRIStop(pScreen); -#endif - -#ifdef USE_XAA - if(!info->useEXA && info->accel_state->RenderTex) { - xf86FreeOffscreenLinear(info->accel_state->RenderTex); - info->accel_state->RenderTex = NULL; - } -#endif /* USE_XAA */ - - if (pScrn->vtSema) { - RADEONRestore(pScrn); - } - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "Disposing accel...\n"); -#ifdef USE_EXA - if (info->accel_state->exa) { - exaDriverFini(pScreen); - free(info->accel_state->exa); - info->accel_state->exa = NULL; - } -#endif /* USE_EXA */ -#ifdef USE_XAA - if (!info->useEXA) { - if (info->accel_state->accel) - XAADestroyInfoRec(info->accel_state->accel); - info->accel_state->accel = NULL; - - if (info->accel_state->scratch_save) - free(info->accel_state->scratch_save); - info->accel_state->scratch_save = NULL; - } -#endif /* USE_XAA */ - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "Disposing cursor info\n"); - if (info->cursor) xf86DestroyCursorInfoRec(info->cursor); - info->cursor = NULL; - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "Unmapping memory\n"); - RADEONUnmapMem(pScrn); - - pScrn->vtSema = FALSE; - - xf86ClearPrimInitDone(info->pEnt->index); - - pScreen->BlockHandler = info->BlockHandler; - pScreen->CloseScreen = info->CloseScreen; - return (*pScreen->CloseScreen)(CLOSE_SCREEN_ARGS); -} - -void RADEONFreeScreen(FREE_SCREEN_ARGS_DECL) -{ - SCRN_INFO_PTR(arg); - RADEONInfoPtr info = RADEONPTR(pScrn); - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "RADEONFreeScreen\n"); - - /* when server quits at PreInit, we don't need do this anymore*/ - if (!info) return; - -#ifdef WITH_VGAHW - if (info->VGAAccess && xf86LoaderCheckSymbol("vgaHWFreeHWRec")) - vgaHWFreeHWRec(pScrn); -#endif - RADEONFreeRec(pScrn); -} diff --git a/src/radeon_dummy_bufmgr.h b/src/radeon_dummy_bufmgr.h deleted file mode 100644 index e08e6569..00000000 --- a/src/radeon_dummy_bufmgr.h +++ /dev/null @@ -1,62 +0,0 @@ - -#ifndef RADEON_DUMMY_BUFMGR_H -#define RADEON_DUMMY_BUFMGR_H -/* when we don't have modesetting but we still need these functions */ - -struct radeon_bo { - int dummy; - void *ptr; -}; - -static inline int radeon_cs_begin(Bool dummy, int d2, const char *file, - const char *func, int line) -{ - return 0; -} - -static inline int radeon_cs_end(Bool dummy, const char *file, - const char *func, int line) -{ - return 0; -} - -static inline void radeon_cs_write_dword(Bool cs, uint32_t dword) -{ -} - -static inline int radeon_cs_write_reloc(Bool cs, - struct radeon_bo *bo, - uint32_t read_domain, - uint32_t write_domain, - uint32_t flags) -{ - return 0; -} - -static inline int radeon_bo_map(struct radeon_bo *bo, int write) {return 0;} -static inline void radeon_bo_ref(struct radeon_bo *bo) {return;} -static inline struct radeon_bo *radeon_bo_unref(struct radeon_bo *bo) {return NULL;} -static inline void radeon_bo_unmap(struct radeon_bo *bo) {return;} -static inline int radeon_bo_wait(struct radeon_bo *bo) {return 0;} - -static inline int radeon_cs_space_add_persistent_bo(Bool cs, struct radeon_bo *bo, - uint32_t read_domains, uint32_t write_domain) -{ - return 0; -} - -static inline int radeon_cs_space_check(Bool cs) -{ - return 0; -} - -static inline void radeon_cs_flush_indirect(ScrnInfoPtr pScrn) -{ -} - -static inline void radeon_ddx_cs_start(ScrnInfoPtr pScrn, int n, - const char *file, const char *func, int line) -{ -} - -#endif diff --git a/src/radeon_exa.c b/src/radeon_exa.c index e6d9eafa..e081f3db 100644 --- a/src/radeon_exa.c +++ b/src/radeon_exa.c @@ -36,9 +36,7 @@ #include "radeon.h" #include "radeon_reg.h" #include "r600_reg.h" -#ifdef XF86DRI #include "radeon_drm.h" -#endif #include "radeon_macros.h" #include "radeon_probe.h" #include "radeon_version.h" @@ -128,22 +126,7 @@ Bool RADEONGetDatatypeBpp(int bpp, uint32_t *type) static Bool RADEONPixmapIsColortiled(PixmapPtr pPix) { - RINFO_FROM_SCREEN(pPix->drawable.pScreen); - -#ifdef XF86DRM_MODE - if (info->cs) { - /* Taken care of by the kernel relocation handling */ - return FALSE; - } -#endif - - /* This doesn't account for the back buffer, which we may want to wrap in - * a pixmap at some point for the purposes of DRI buffer moves. - */ - if (info->tilingEnabled && exaGetPixmapOffset(pPix) == 0) - return TRUE; - else - return FALSE; + return FALSE; } static Bool RADEONGetOffsetPitch(PixmapPtr pPix, int bpp, uint32_t *pitch_offset, @@ -194,110 +177,6 @@ Bool radeon_transform_is_affine_or_scaled(PictTransformPtr t) return t->matrix[2][0] == 0 && t->matrix[2][1] == 0 && t->matrix[2][2] == IntToxFixed(1); } -#if X_BYTE_ORDER == X_BIG_ENDIAN - -static unsigned long swapper_surfaces[6]; - -static Bool RADEONPrepareAccess_BE(PixmapPtr pPix, int index) -{ - RINFO_FROM_SCREEN(pPix->drawable.pScreen); - unsigned char *RADEONMMIO = info->MMIO; - uint32_t offset = exaGetPixmapOffset(pPix); - int bpp, soff; - uint32_t size, flags; - - /* Front buffer is always set with proper swappers */ - if (offset == 0) - return TRUE; - - /* If same bpp as front buffer, just do nothing as the main - * swappers will apply - */ - bpp = pPix->drawable.bitsPerPixel; - if (bpp == pScrn->bitsPerPixel) - return TRUE; - - /* We need to setup a separate swapper, let's request a - * surface. We need to align the size first - */ - size = exaGetPixmapSize(pPix); - size = RADEON_ALIGN(size, RADEON_GPU_PAGE_SIZE); - - /* Set surface to tiling disabled with appropriate swapper */ - switch (bpp) { - case 16: - flags = RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP; - break; - case 32: - flags = RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP; - break; - default: - flags = 0; - } -#if defined(XF86DRI) - if (info->directRenderingEnabled && info->allowColorTiling) { - struct drm_radeon_surface_alloc drmsurfalloc; - int rc; - - drmsurfalloc.address = offset; - drmsurfalloc.size = size; - drmsurfalloc.flags = flags | 1; /* bogus pitch to please DRM */ - - rc = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_ALLOC, - &drmsurfalloc, sizeof(drmsurfalloc)); - if (rc < 0) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "drm: could not allocate surface for access" - " swapper, err: %d!\n", rc); - return FALSE; - } - swapper_surfaces[index] = offset; - - return TRUE; - } -#endif - soff = (index + 1) * 0x10; - OUTREG(RADEON_SURFACE0_INFO + soff, flags); - OUTREG(RADEON_SURFACE0_LOWER_BOUND + soff, offset); - OUTREG(RADEON_SURFACE0_UPPER_BOUND + soff, offset + size - 1); - swapper_surfaces[index] = offset; - return TRUE; -} - -static void RADEONFinishAccess_BE(PixmapPtr pPix, int index) -{ - RINFO_FROM_SCREEN(pPix->drawable.pScreen); - unsigned char *RADEONMMIO = info->MMIO; - uint32_t offset = exaGetPixmapOffset(pPix); - int soff; - - /* Front buffer is always set with proper swappers */ - if (offset == 0) - return; - - if (swapper_surfaces[index] == 0) - return; -#if defined(XF86DRI) - if (info->directRenderingEnabled && info->allowColorTiling) { - struct drm_radeon_surface_free drmsurffree; - - drmsurffree.address = offset; - drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_FREE, - &drmsurffree, sizeof(drmsurffree)); - swapper_surfaces[index] = 0; - return; - } -#endif - soff = (index + 1) * 0x10; - OUTREG(RADEON_SURFACE0_INFO + soff, 0); - OUTREG(RADEON_SURFACE0_LOWER_BOUND + soff, 0); - OUTREG(RADEON_SURFACE0_UPPER_BOUND + soff, 0); - swapper_surfaces[index] = 0; -} - -#endif /* X_BYTE_ORDER == X_BIG_ENDIAN */ - -#ifdef XF86DRM_MODE Bool RADEONPrepareAccess_CS(PixmapPtr pPix, int index) { ScreenPtr pScreen = pPix->drawable.pScreen; @@ -457,9 +336,7 @@ void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height, uint32_t size, heighta; uint32_t tiling = 0; int cpp = bitsPerPixel / 8; -#ifdef XF86DRM_MODE struct radeon_surface surface; -#endif #ifdef EXA_MIXED_PIXMAPS if (info->accel_state->exa->flags & EXA_MIXED_PIXMAPS) { @@ -497,7 +374,6 @@ void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height, size = RADEON_ALIGN(heighta * pitch, RADEON_GPU_PAGE_SIZE); memset(&surface, 0, sizeof(struct radeon_surface)); -#ifdef XF86DRM_MODE if (info->ChipFamily >= CHIP_FAMILY_R600 && info->surf_man) { if (width) { surface.npix_x = width; @@ -560,7 +436,6 @@ void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height, } } } -#endif new_priv = calloc(1, sizeof(struct radeon_exa_pixmap_priv)); if (!new_priv) { @@ -607,14 +482,12 @@ struct radeon_bo *radeon_get_pixmap_bo(PixmapPtr pPix) return driver_priv->bo; } -#if defined(XF86DRM_MODE) struct radeon_surface *radeon_get_pixmap_surface(PixmapPtr pPix) { struct radeon_exa_pixmap_priv *driver_priv; driver_priv = exaGetPixmapDriverPrivate(pPix); return &driver_priv->surface; } -#endif uint32_t radeon_get_pixmap_tiling(PixmapPtr pPix) { @@ -653,39 +526,13 @@ Bool RADEONEXAPixmapIsOffscreen(PixmapPtr pPix) return TRUE; return FALSE; } -#endif #define ENTER_DRAW(x) TRACE #define LEAVE_DRAW(x) TRACE /***********************************************************************/ -#define ACCEL_MMIO -#define ACCEL_PREAMBLE() unsigned char *RADEONMMIO = info->MMIO -#define BEGIN_ACCEL(n) RADEONWaitForFifo(pScrn, (n)) -#define OUT_ACCEL_REG(reg, val) OUTREG(reg, val) -#define OUT_ACCEL_REG_F(reg, val) OUTREG(reg, F_TO_DW(val)) -#define OUT_RELOC(x, read, write) do {} while(0) -#define FINISH_ACCEL() - -#ifdef RENDER -#include "radeon_exa_render.c" -#endif -#include "radeon_exa_funcs.c" - -#undef ACCEL_MMIO -#undef ACCEL_PREAMBLE -#undef BEGIN_ACCEL -#undef OUT_ACCEL_REG -#undef OUT_ACCEL_REG_F -#undef FINISH_ACCEL -#undef OUT_RELOC - -#ifdef XF86DRI - -#define ACCEL_CP #define ACCEL_PREAMBLE() \ - RING_LOCALS; \ - RADEONCP_REFRESH(pScrn, info) + RING_LOCALS; #define BEGIN_ACCEL(n) BEGIN_RING(2*(n)) #define OUT_ACCEL_REG(reg, val) OUT_RING_REG(reg, val) #define FINISH_ACCEL() ADVANCE_RING() @@ -698,178 +545,10 @@ Bool RADEONEXAPixmapIsOffscreen(PixmapPtr pPix) #endif #include "radeon_exa_funcs.c" -#undef ACCEL_CP #undef ACCEL_PREAMBLE #undef BEGIN_ACCEL #undef OUT_ACCEL_REG #undef FINISH_ACCEL #undef OUT_RING_F -#endif /* XF86DRI */ - -/* - * Once screen->off_screen_base is set, this function - * allocates the remaining memory appropriately - */ -Bool RADEONSetupMemEXA (ScreenPtr pScreen) -{ - ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); - RADEONInfoPtr info = RADEONPTR(pScrn); - xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); - int cpp = info->CurrentLayout.pixel_bytes; - int screen_size; - int byteStride = pScrn->displayWidth * cpp; - - if (info->accel_state->exa != NULL) { - xf86DrvMsg(pScreen->myNum, X_ERROR, "Memory map already initialized\n"); - return FALSE; - } - info->accel_state->exa = exaDriverAlloc(); - if (info->accel_state->exa == NULL) - return FALSE; - - /* Need to adjust screen size for 16 line tiles, and then make it align to. - * the buffer alignment requirement. - */ - if (info->allowColorTiling) - screen_size = RADEON_ALIGN(pScrn->virtualY, 16) * byteStride; - else - screen_size = pScrn->virtualY * byteStride; - - info->accel_state->exa->memoryBase = info->FB; - info->accel_state->exa->memorySize = info->FbMapSize - info->FbSecureSize; - info->accel_state->exa->offScreenBase = screen_size; - - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Allocating from a screen of %ld kb\n", - info->accel_state->exa->memorySize / 1024); - - /* Reserve static area for hardware cursor */ - if (!xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) { - int cursor_size = 64 * 4 * 64; - int align = IS_AVIVO_VARIANT ? 4096 : 256; - int c; - - for (c = 0; c < xf86_config->num_crtc; c++) { - xf86CrtcPtr crtc = xf86_config->crtc[c]; - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - - radeon_crtc->cursor_offset = - RADEON_ALIGN(info->accel_state->exa->offScreenBase, align); - info->accel_state->exa->offScreenBase = radeon_crtc->cursor_offset + cursor_size; - - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Will use %d kb for hardware cursor %d at offset 0x%08x\n", - (cursor_size * xf86_config->num_crtc) / 1024, - c, - (unsigned int)radeon_crtc->cursor_offset); - } - } - -#if defined(XF86DRI) - if (info->directRenderingEnabled) { - int depthCpp = (info->dri->depthBits - 8) / 4, l, next, depth_size; - - info->dri->frontOffset = 0; - info->dri->frontPitch = pScrn->displayWidth; - - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Will use %d kb for front buffer at offset 0x%08x\n", - screen_size / 1024, info->dri->frontOffset); - RADEONDRIAllocatePCIGARTTable(pScreen); - - if (info->cardType==CARD_PCIE) - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Will use %d kb for PCI GART at offset 0x%08x\n", - info->dri->pciGartSize / 1024, - (int)info->dri->pciGartOffset); - - /* Reserve a static area for the back buffer the same size as the - * visible screen. XXX: This would be better initialized in ati_dri.c - * when GLX is set up, but the offscreen memory manager's allocations - * don't last through VT switches, while the kernel's understanding of - * offscreen locations does. - */ - info->dri->backPitch = pScrn->displayWidth; - next = RADEON_ALIGN(info->accel_state->exa->offScreenBase, RADEON_GPU_PAGE_SIZE); - if (!info->dri->noBackBuffer && - next + screen_size <= info->accel_state->exa->memorySize) - { - info->dri->backOffset = next; - info->accel_state->exa->offScreenBase = next + screen_size; - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Will use %d kb for back buffer at offset 0x%08x\n", - screen_size / 1024, info->dri->backOffset); - } - - /* Reserve the static depth buffer, and adjust pitch and height to - * handle tiling. - */ - info->dri->depthPitch = RADEON_ALIGN(pScrn->displayWidth, 32); - depth_size = RADEON_ALIGN(pScrn->virtualY, 16) * info->dri->depthPitch * depthCpp; - next = RADEON_ALIGN(info->accel_state->exa->offScreenBase, RADEON_GPU_PAGE_SIZE); - if (next + depth_size <= info->accel_state->exa->memorySize) - { - info->dri->depthOffset = next; - info->accel_state->exa->offScreenBase = next + depth_size; - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Will use %d kb for depth buffer at offset 0x%08x\n", - depth_size / 1024, info->dri->depthOffset); - } - - info->dri->textureSize *= (info->accel_state->exa->memorySize - - info->accel_state->exa->offScreenBase) / 100; - - l = RADEONLog2(info->dri->textureSize / RADEON_NR_TEX_REGIONS); - if (l < RADEON_LOG_TEX_GRANULARITY) - l = RADEON_LOG_TEX_GRANULARITY; - info->dri->textureSize = (info->dri->textureSize >> l) << l; - if (info->dri->textureSize >= 512 * 1024) { - info->dri->textureOffset = info->accel_state->exa->offScreenBase; - info->accel_state->exa->offScreenBase += info->dri->textureSize; - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Will use %d kb for textures at offset 0x%08x\n", - info->dri->textureSize / 1024, info->dri->textureOffset); - } else { - /* Minimum texture size is for 2 256x256x32bpp textures */ - info->dri->textureSize = 0; - } - } else -#endif /* XF86DRI */ - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Will use %d kb for front buffer at offset 0x%08x\n", - screen_size / 1024, 0); - - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Will use %ld kb for X Server offscreen at offset 0x%08lx\n", - (info->accel_state->exa->memorySize - info->accel_state->exa->offScreenBase) / - 1024, info->accel_state->exa->offScreenBase); - - return TRUE; -} -#ifdef XF86DRI - -#ifndef ExaOffscreenMarkUsed -extern void ExaOffscreenMarkUsed(PixmapPtr); -#endif - -unsigned long long -RADEONTexOffsetStart(PixmapPtr pPix) -{ - RINFO_FROM_SCREEN(pPix->drawable.pScreen); - unsigned long long offset; - - if (exaGetPixmapDriverPrivate(pPix)) - return -1; - - exaMoveInPixmap(pPix); - ExaOffscreenMarkUsed(pPix); - - offset = exaGetPixmapOffset(pPix); - - if (offset > info->FbMapSize) - return ~0ULL; - else - return info->fbLocation + offset; -} -#endif diff --git a/src/radeon_exa_funcs.c b/src/radeon_exa_funcs.c index 9382e2da..b2f35523 100644 --- a/src/radeon_exa_funcs.c +++ b/src/radeon_exa_funcs.c @@ -31,25 +31,13 @@ * */ -#if defined(ACCEL_MMIO) && defined(ACCEL_CP) -#error Cannot define both MMIO and CP acceleration! -#endif - #if !defined(UNIXCPP) || defined(ANSICPP) #define FUNC_NAME_CAT(prefix,suffix) prefix##suffix #else #define FUNC_NAME_CAT(prefix,suffix) prefix/**/suffix #endif -#ifdef ACCEL_MMIO -#define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,MMIO) -#else -#ifdef ACCEL_CP #define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,CP) -#else -#error No accel type defined! -#endif -#endif #include <errno.h> #include <string.h> @@ -71,20 +59,7 @@ FUNC_NAME(RADEONMarkSync)(ScreenPtr pScreen) static void FUNC_NAME(RADEONSync)(ScreenPtr pScreen, int marker) { - ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); - RADEONInfoPtr info = RADEONPTR(pScrn); - - if (info->cs) - return; - - TRACE; - - if (info->accel_state->exaMarkerSynced != marker) { - FUNC_NAME(RADEONWaitForIdle)(pScrn); - info->accel_state->exaMarkerSynced = marker; - } - RADEONPTR(pScrn)->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN; } static void FUNC_NAME(Emit2DState)(ScrnInfoPtr pScrn, int op) @@ -97,7 +72,7 @@ static void FUNC_NAME(Emit2DState)(ScrnInfoPtr pScrn, int op) if (info->state_2d.op == 0 && op == 0) return; - has_src = info->state_2d.src_pitch_offset || (info->cs && info->state_2d.src_bo); + has_src = info->state_2d.src_pitch_offset || info->state_2d.src_bo; if (has_src) { BEGIN_ACCEL_RELOC(10, 2); @@ -114,21 +89,17 @@ static void FUNC_NAME(Emit2DState)(ScrnInfoPtr pScrn, int op) OUT_ACCEL_REG(RADEON_DP_CNTL, info->state_2d.dp_cntl); OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->state_2d.dst_pitch_offset); - if (info->cs) - OUT_RELOC(info->state_2d.dst_bo, 0, RADEON_GEM_DOMAIN_VRAM); + OUT_RELOC(info->state_2d.dst_bo, 0, RADEON_GEM_DOMAIN_VRAM); if (has_src) { - OUT_ACCEL_REG(RADEON_SRC_PITCH_OFFSET, info->state_2d.src_pitch_offset); - if (info->cs) - OUT_RELOC(info->state_2d.src_bo, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0); - + OUT_ACCEL_REG(RADEON_SRC_PITCH_OFFSET, info->state_2d.src_pitch_offset); + OUT_RELOC(info->state_2d.src_bo, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0); } FINISH_ACCEL(); if (op) info->state_2d.op = op; - if (info->cs) - info->reemit_current2d = FUNC_NAME(Emit2DState); + info->reemit_current2d = FUNC_NAME(Emit2DState); } static void @@ -160,6 +131,8 @@ FUNC_NAME(RADEONPrepareSolid)(PixmapPtr pPix, int alu, Pixel pm, Pixel fg) { RINFO_FROM_SCREEN(pPix->drawable.pScreen); uint32_t datatype, dst_pitch_offset; + struct radeon_exa_pixmap_priv *driver_priv; + int ret; TRACE; @@ -172,25 +145,18 @@ FUNC_NAME(RADEONPrepareSolid)(PixmapPtr pPix, int alu, Pixel pm, Pixel fg) RADEON_SWITCH_TO_2D(); -#ifdef XF86DRM_MODE - if (info->cs) { - struct radeon_exa_pixmap_priv *driver_priv; - int ret; - - radeon_cs_space_reset_bos(info->cs); + radeon_cs_space_reset_bos(info->cs); - driver_priv = exaGetPixmapDriverPrivate(pPix); - radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM); + driver_priv = exaGetPixmapDriverPrivate(pPix); + radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM); - ret = radeon_cs_space_check(info->cs); - if (ret) - RADEON_FALLBACK(("Not enough RAM to hw accel solid operation\n")); + ret = radeon_cs_space_check(info->cs); + if (ret) + RADEON_FALLBACK(("Not enough RAM to hw accel solid operation\n")); - driver_priv = exaGetPixmapDriverPrivate(pPix); - if (driver_priv) - info->state_2d.dst_bo = driver_priv->bo; - } -#endif + driver_priv = exaGetPixmapDriverPrivate(pPix); + if (driver_priv) + info->state_2d.dst_bo = driver_priv->bo; info->state_2d.default_sc_bottom_right = (RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); @@ -226,12 +192,10 @@ FUNC_NAME(RADEONSolid)(PixmapPtr pPix, int x1, int y1, int x2, int y2) TRACE; -#if defined(ACCEL_CP) && defined(XF86DRM_MODE) - if (info->cs && CS_FULL(info->cs)) { + if (CS_FULL(info->cs)) { FUNC_NAME(RADEONFlush2D)(info->accel_state->dst_pix); radeon_cs_flush_indirect(pScrn); } -#endif if (info->accel_state->vsync) FUNC_NAME(RADEONWaitForVLine)(pScrn, pPix, @@ -283,6 +247,8 @@ FUNC_NAME(RADEONPrepareCopy)(PixmapPtr pSrc, PixmapPtr pDst, { RINFO_FROM_SCREEN(pDst->drawable.pScreen); uint32_t datatype, src_pitch_offset, dst_pitch_offset; + struct radeon_exa_pixmap_priv *driver_priv; + int ret; TRACE; if (pDst->drawable.bitsPerPixel == 24) @@ -296,26 +262,19 @@ FUNC_NAME(RADEONPrepareCopy)(PixmapPtr pSrc, PixmapPtr pDst, RADEON_SWITCH_TO_2D(); -#ifdef XF86DRM_MODE - if (info->cs) { - struct radeon_exa_pixmap_priv *driver_priv; - int ret; - - radeon_cs_space_reset_bos(info->cs); + radeon_cs_space_reset_bos(info->cs); - driver_priv = exaGetPixmapDriverPrivate(pSrc); - radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); - info->state_2d.src_bo = driver_priv->bo; + driver_priv = exaGetPixmapDriverPrivate(pSrc); + radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); + info->state_2d.src_bo = driver_priv->bo; - driver_priv = exaGetPixmapDriverPrivate(pDst); - radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM); - info->state_2d.dst_bo = driver_priv->bo; + driver_priv = exaGetPixmapDriverPrivate(pDst); + radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM); + info->state_2d.dst_bo = driver_priv->bo; - ret = radeon_cs_space_check(info->cs); - if (ret) - RADEON_FALLBACK(("Not enough RAM to hw accel copy operation\n")); - } -#endif + ret = radeon_cs_space_check(info->cs); + if (ret) + RADEON_FALLBACK(("Not enough RAM to hw accel copy operation\n")); info->accel_state->xdir = xdir; info->accel_state->ydir = ydir; @@ -338,12 +297,10 @@ FUNC_NAME(RADEONCopy)(PixmapPtr pDst, TRACE; -#if defined(ACCEL_CP) && defined(XF86DRM_MODE) - if (info->cs && CS_FULL(info->cs)) { + if (CS_FULL(info->cs)) { FUNC_NAME(RADEONFlush2D)(info->accel_state->dst_pix); radeon_cs_flush_indirect(pScrn); } -#endif if (info->accel_state->xdir < 0) { srcX += w - 1; @@ -368,50 +325,6 @@ FUNC_NAME(RADEONCopy)(PixmapPtr pDst, FINISH_ACCEL(); } -#ifdef ACCEL_CP - -static Bool -RADEONUploadToScreenCP(PixmapPtr pDst, int x, int y, int w, int h, - char *src, int src_pitch) -{ - RINFO_FROM_SCREEN(pDst->drawable.pScreen); - unsigned int bpp = pDst->drawable.bitsPerPixel; - unsigned int hpass; - uint32_t buf_pitch, dst_pitch_off; - - TRACE; - - if (bpp < 8) - return FALSE; - - if (info->directRenderingEnabled && - RADEONGetPixmapOffsetPitch(pDst, &dst_pitch_off)) { - uint8_t *buf; - int cpp = bpp / 8; - ACCEL_PREAMBLE(); - - RADEON_SWITCH_TO_2D(); - - if (info->accel_state->vsync) - FUNC_NAME(RADEONWaitForVLine)(pScrn, pDst, - radeon_pick_best_crtc(pScrn, x, x + w, y, y + h), - y, y + h); - - while ((buf = RADEONHostDataBlit(pScrn, - cpp, w, dst_pitch_off, &buf_pitch, - x, &y, (unsigned int*)&h, &hpass)) != 0) { - RADEONHostDataBlitCopyPass(pScrn, cpp, buf, (uint8_t *)src, - hpass, buf_pitch, src_pitch); - src += hpass * src_pitch; - } - - exaMarkSync(pDst->drawable.pScreen); - return TRUE; - } - - return FALSE; -} - /* Emit blit with arbitrary source and destination offsets and pitches */ static void RADEONBlitChunk(ScrnInfoPtr pScrn, struct radeon_bo *src_bo, @@ -459,7 +372,6 @@ RADEONBlitChunk(ScrnInfoPtr pScrn, struct radeon_bo *src_bo, FINISH_ACCEL(); } -#if defined(XF86DRM_MODE) static Bool RADEONUploadToScreenCS(PixmapPtr pDst, int x, int y, int w, int h, char *src, int src_pitch) @@ -672,118 +584,6 @@ out: radeon_bo_unref(scratch); return r; } -#endif - -static Bool -RADEONDownloadFromScreenCP(PixmapPtr pSrc, int x, int y, int w, int h, - char *dst, int dst_pitch) -{ - RINFO_FROM_SCREEN(pSrc->drawable.pScreen); - uint8_t *src = info->FB + exaGetPixmapOffset(pSrc); - int bpp = pSrc->drawable.bitsPerPixel; - uint32_t datatype, src_pitch_offset, scratch_pitch = RADEON_ALIGN(w * bpp / 8, 64), scratch_off = 0; - drmBufPtr scratch; - - TRACE; - - /* - * Try to accelerate download. Use an indirect buffer as scratch space, - * blitting the bits to one half while copying them out of the other one and - * then swapping the halves. - */ - if (bpp != 24 && RADEONGetDatatypeBpp(bpp, &datatype) && - RADEONGetPixmapOffsetPitch(pSrc, &src_pitch_offset) && - (scratch = RADEONCPGetBuffer(pScrn))) - { - int swap = RADEON_HOST_DATA_SWAP_NONE, wpass = w * bpp / 8; - int hpass = min(h, scratch->total/2 / scratch_pitch); - uint32_t scratch_pitch_offset = scratch_pitch << 16 - | (info->gartLocation + info->dri->bufStart - + scratch->idx * scratch->total) >> 10; - drm_radeon_indirect_t indirect; - ACCEL_PREAMBLE(); - - RADEON_SWITCH_TO_2D(); - - /* Kick the first blit as early as possible */ - RADEONBlitChunk(pScrn, NULL, NULL, datatype, src_pitch_offset, - scratch_pitch_offset, x, y, 0, 0, w, hpass, 0, 0); - FLUSH_RING(); - -#if X_BYTE_ORDER == X_BIG_ENDIAN - switch (bpp) { - case 16: - swap = RADEON_HOST_DATA_SWAP_16BIT; - break; - case 32: - swap = RADEON_HOST_DATA_SWAP_32BIT; - break; - } -#endif - - while (h) { - int oldhpass = hpass, i = 0; - - src = (uint8_t*)scratch->address + scratch_off; - - y += oldhpass; - h -= oldhpass; - hpass = min(h, scratch->total/2 / scratch_pitch); - - /* Prepare next blit if anything's left */ - if (hpass) { - scratch_off = scratch->total/2 - scratch_off; - RADEONBlitChunk(pScrn, NULL, NULL, datatype, src_pitch_offset, - scratch_pitch_offset + (scratch_off >> 10), - x, y, 0, 0, w, hpass, 0, 0); - } - - /* - * Wait for previous blit to complete. - * - * XXX: Doing here essentially the same things this ioctl does in - * the DRM results in corruption with 'small' transfers, apparently - * because the data doesn't actually land in system RAM before the - * memcpy. I suspect the ioctl helps mostly due to its latency; what - * we'd really need is a way to reliably wait for the host interface - * to be done with pushing the data to the host. - */ - while ((drmCommandNone(info->dri->drmFD, DRM_RADEON_CP_IDLE) == -EBUSY) - && (i++ < RADEON_TIMEOUT)) - ; - - /* Kick next blit */ - if (hpass) - FLUSH_RING(); - - /* Copy out data from previous blit */ - if (wpass == scratch_pitch && wpass == dst_pitch) { - RADEONCopySwap((uint8_t*)dst, src, wpass * oldhpass, swap); - dst += dst_pitch * oldhpass; - } else while (oldhpass--) { - RADEONCopySwap((uint8_t*)dst, src, wpass, swap); - src += scratch_pitch; - dst += dst_pitch; - } - } - - indirect.idx = scratch->idx; - indirect.start = indirect.end = 0; - indirect.discard = 1; - - drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_INDIRECT, - &indirect, sizeof(drm_radeon_indirect_t)); - - info->accel_state->exaMarkerSynced = info->accel_state->exaSyncMarker; - - return TRUE; - } - - return FALSE; -} - -#endif /* def ACCEL_CP */ - Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen) { @@ -807,24 +607,9 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen) info->accel_state->exa->MarkSync = FUNC_NAME(RADEONMarkSync); info->accel_state->exa->WaitMarker = FUNC_NAME(RADEONSync); -#ifdef ACCEL_CP - if (!info->kms_enabled) { - info->accel_state->exa->UploadToScreen = RADEONUploadToScreenCP; - if (info->accelDFS) - info->accel_state->exa->DownloadFromScreen = RADEONDownloadFromScreenCP; - } -# if defined(XF86DRM_MODE) - else { - info->accel_state->exa->UploadToScreen = &RADEONUploadToScreenCS; - info->accel_state->exa->DownloadFromScreen = &RADEONDownloadFromScreenCS; - } -# endif -#endif -#if X_BYTE_ORDER == X_BIG_ENDIAN - info->accel_state->exa->PrepareAccess = RADEONPrepareAccess_BE; - info->accel_state->exa->FinishAccess = RADEONFinishAccess_BE; -#endif + info->accel_state->exa->UploadToScreen = &RADEONUploadToScreenCS; + info->accel_state->exa->DownloadFromScreen = &RADEONDownloadFromScreenCS; info->accel_state->exa->flags = EXA_OFFSCREEN_PIXMAPS; #ifdef EXA_SUPPORTS_PREPARE_AUX @@ -838,21 +623,17 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen) info->accel_state->exa->pixmapPitchAlign = 64; #ifdef EXA_HANDLES_PIXMAPS - if (info->cs) { - info->accel_state->exa->flags |= EXA_HANDLES_PIXMAPS; + info->accel_state->exa->flags |= EXA_HANDLES_PIXMAPS; #ifdef EXA_MIXED_PIXMAPS - info->accel_state->exa->flags |= EXA_MIXED_PIXMAPS; + info->accel_state->exa->flags |= EXA_MIXED_PIXMAPS; #endif - } #endif #ifdef RENDER if (info->RenderAccel) { if (IS_R300_3D || IS_R500_3D) { if ((info->ChipFamily < CHIP_FAMILY_RS400) -#ifdef XF86DRI || (info->directRenderingEnabled) -#endif ) { xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration " "enabled for R300/R400/R500 type cards.\n"); @@ -883,18 +664,14 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen) } #endif -#ifdef XF86DRM_MODE #if (EXA_VERSION_MAJOR == 2 && EXA_VERSION_MINOR >= 4) - if (info->cs) { - info->accel_state->exa->CreatePixmap = RADEONEXACreatePixmap; - info->accel_state->exa->DestroyPixmap = RADEONEXADestroyPixmap; - info->accel_state->exa->PixmapIsOffscreen = RADEONEXAPixmapIsOffscreen; - info->accel_state->exa->PrepareAccess = RADEONPrepareAccess_CS; - info->accel_state->exa->FinishAccess = RADEONFinishAccess_CS; + info->accel_state->exa->CreatePixmap = RADEONEXACreatePixmap; + info->accel_state->exa->DestroyPixmap = RADEONEXADestroyPixmap; + info->accel_state->exa->PixmapIsOffscreen = RADEONEXAPixmapIsOffscreen; + info->accel_state->exa->PrepareAccess = RADEONPrepareAccess_CS; + info->accel_state->exa->FinishAccess = RADEONFinishAccess_CS; #if (EXA_VERSION_MAJOR == 2 && EXA_VERSION_MINOR >= 5) - info->accel_state->exa->CreatePixmap2 = RADEONEXACreatePixmap2; -#endif - } + info->accel_state->exa->CreatePixmap2 = RADEONEXACreatePixmap2; #endif #endif diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c index c42ae287..2866bc8e 100644 --- a/src/radeon_exa_render.c +++ b/src/radeon_exa_render.c @@ -30,29 +30,15 @@ * */ -#if defined(ACCEL_MMIO) && defined(ACCEL_CP) -#error Cannot define both MMIO and CP acceleration! -#endif - #if !defined(UNIXCPP) || defined(ANSICPP) #define FUNC_NAME_CAT(prefix,suffix) prefix##suffix #else #define FUNC_NAME_CAT(prefix,suffix) prefix/**/suffix #endif -#ifdef ACCEL_MMIO -#define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,MMIO) -#else -#ifdef ACCEL_CP #define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,CP) -#else -#error No accel type defined! -#endif -#endif -#ifndef ACCEL_CP #define ONLY_ONCE -#endif /* Only include the following (generic) bits once. */ #ifdef ONLY_ONCE @@ -404,8 +390,6 @@ static Bool FUNC_NAME(R100TextureSetup)(PicturePtr pPict, PixmapPtr pPix, txpitch = exaGetPixmapPitch(pPix); txoffset = 0; - CHECK_OFFSET(pPix, 0x1f, "texture"); - if ((txpitch & 0x1f) != 0) RADEON_FALLBACK(("Bad texture pitch 0x%x\n", (int)txpitch)); @@ -581,6 +565,7 @@ RADEONPrepareCompositeCS(int op, PicturePtr pSrcPicture, PicturePtr pMaskPicture PixmapPtr pDst) { RINFO_FROM_SCREEN(pDst->drawable.pScreen); + int ret; info->accel_state->composite_op = op; info->accel_state->dst_pic = pDstPicture; @@ -590,25 +575,19 @@ RADEONPrepareCompositeCS(int op, PicturePtr pSrcPicture, PicturePtr pMaskPicture info->accel_state->msk_pix = pMask; info->accel_state->src_pix = pSrc; -#ifdef XF86DRM_MODE - if (info->cs) { - int ret; - - radeon_cs_space_reset_bos(info->cs); + radeon_cs_space_reset_bos(info->cs); - radeon_add_pixmap(info->cs, pSrc, - RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); + radeon_add_pixmap(info->cs, pSrc, + RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); - if (pMask) - radeon_add_pixmap(info->cs, pMask, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); + if (pMask) + radeon_add_pixmap(info->cs, pMask, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); - radeon_add_pixmap(info->cs, pDst, 0, RADEON_GEM_DOMAIN_VRAM); + radeon_add_pixmap(info->cs, pDst, 0, RADEON_GEM_DOMAIN_VRAM); - ret = radeon_cs_space_check(info->cs); - if (ret) - RADEON_FALLBACK(("Not enough RAM to hw accel composite operation\n")); - } -#endif + ret = radeon_cs_space_check(info->cs); + if (ret) + RADEON_FALLBACK(("Not enough RAM to hw accel composite operation\n")); return TRUE; } @@ -646,8 +625,6 @@ static Bool FUNC_NAME(R100PrepareComposite)(int op, if (RADEONPixmapIsColortiled(pDst)) colorpitch |= RADEON_COLOR_TILE_ENABLE; - CHECK_OFFSET(pDst, 0x0f, "destination"); - if (!pSrc) { pSrc = RADEONSolidPixmap(pScreen, cpu_to_le32(pSrcPicture->pSourcePict->solidFill.color)); if (!pSrc) @@ -821,7 +798,6 @@ static Bool FUNC_NAME(R200TextureSetup)(PicturePtr pPict, PixmapPtr pPix, txpitch = exaGetPixmapPitch(pPix); txoffset = 0; - CHECK_OFFSET(pPix, 0x1f, "texture"); if ((txpitch & 0x1f) != 0) RADEON_FALLBACK(("Bad texture pitch 0x%x\n", (int)txpitch)); @@ -1019,8 +995,6 @@ static Bool FUNC_NAME(R200PrepareComposite)(int op, PicturePtr pSrcPicture, if (RADEONPixmapIsColortiled(pDst)) colorpitch |= RADEON_COLOR_TILE_ENABLE; - CHECK_OFFSET(pDst, 0xf, "destination"); - if (((dst_pitch >> pixel_shift) & 0x7) != 0) RADEON_FALLBACK(("Bad destination pitch 0x%x\n", (int)dst_pitch)); @@ -1139,9 +1113,6 @@ static Bool R300CheckCompositeTexture(PicturePtr pPict, int unit, Bool is_r500) { - ScreenPtr pScreen = pDstPict->pDrawable->pScreen; - ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); - RADEONInfoPtr info = RADEONPTR(pScrn); unsigned int repeatType = pPict->repeat ? pPict->repeatType : RepeatNone; int i; @@ -1155,14 +1126,14 @@ static Bool R300CheckCompositeTexture(PicturePtr pPict, (int)pPict->format)); if (pPict->pDrawable && !RADEONCheckTexturePOT(pPict, unit == 0)) { - if (info->cs) { - struct radeon_exa_pixmap_priv *driver_priv; +#if 0 + struct radeon_exa_pixmap_priv *driver_priv; PixmapPtr pPix; pPix = RADEONGetDrawablePixmap(pPict->pDrawable); driver_priv = exaGetPixmapDriverPrivate(pPix); //TODOradeon_bufmgr_gem_force_gtt(driver_priv->bo); - } +#endif return FALSE; } @@ -1216,8 +1187,6 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix, txpitch = exaGetPixmapPitch(pPix); txoffset = 0; - CHECK_OFFSET(pPix, 0x1f, "texture"); - if ((txpitch & 0x1f) != 0) RADEON_FALLBACK(("Bad texture pitch 0x%x\n", (int)txpitch)); @@ -1527,8 +1496,6 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, colorpitch |= dst_format; - CHECK_OFFSET(pDst, 0x0f, "destination"); - if (((dst_pitch >> pixel_shift) & 0x7) != 0) RADEON_FALLBACK(("Bad destination pitch 0x%x\n", (int)dst_pitch)); @@ -2233,8 +2200,6 @@ static void FUNC_NAME(RadeonDoneComposite)(PixmapPtr pDst) pScreen->DestroyPixmap(accel_state->msk_pix); } -#ifdef ACCEL_CP - #define VTX_OUT_MASK(_dstX, _dstY, _srcX, _srcY, _maskX, _maskY) \ do { \ OUT_RING_F(_dstX); \ @@ -2253,28 +2218,6 @@ do { \ OUT_RING_F(_srcY); \ } while (0) -#else /* ACCEL_CP */ - -#define VTX_OUT_MASK(_dstX, _dstY, _srcX, _srcY, _maskX, _maskY) \ -do { \ - OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _dstX); \ - OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _dstY); \ - OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _srcX); \ - OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _srcY); \ - OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _maskX); \ - OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _maskY); \ -} while (0) - -#define VTX_OUT(_dstX, _dstY, _srcX, _srcY) \ -do { \ - OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _dstX); \ - OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _dstY); \ - OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _srcX); \ - OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _srcY); \ -} while (0) - -#endif /* !ACCEL_CP */ - #ifdef ONLY_ONCE static inline void transformPoint(PictTransform *transform, xPointFixed *point) { @@ -2306,15 +2249,9 @@ static void FUNC_NAME(RadeonCompositeTile)(ScrnInfoPtr pScrn, /* ErrorF("RadeonComposite (%d,%d) (%d,%d) (%d,%d) (%d,%d)\n", srcX, srcY, maskX, maskY,dstX, dstY, w, h); */ -#if defined(ACCEL_CP) - if ((info->cs && CS_FULL(info->cs)) || - (!info->cs && (info->cp->indirectBuffer->used + 4 * 32) > - info->cp->indirectBuffer->total)) { + if (CS_FULL(info->cs)) { FUNC_NAME(RadeonFinishComposite)(info->accel_state->dst_pix); - if (info->cs) - radeon_cs_flush_indirect(pScrn); - else - RADEONCPFlushIndirect(pScrn, 1); + radeon_cs_flush_indirect(pScrn); info->accel_state->exa->PrepareComposite(info->accel_state->composite_op, info->accel_state->src_pic, info->accel_state->msk_pic, @@ -2323,7 +2260,6 @@ static void FUNC_NAME(RadeonCompositeTile)(ScrnInfoPtr pScrn, info->accel_state->msk_pix, info->accel_state->dst_pix); } -#endif srcTopLeft.x = IntToxFixed(srcX); srcTopLeft.y = IntToxFixed(srcY); @@ -2371,17 +2307,11 @@ static void FUNC_NAME(RadeonCompositeTile)(ScrnInfoPtr pScrn, radeon_pick_best_crtc(pScrn, dstX, dstX + w, dstY, dstY + h), dstY, dstY + h); -#ifdef ACCEL_CP if (info->ChipFamily < CHIP_FAMILY_R200) { if (!info->accel_state->draw_header) { BEGIN_RING(3); -#ifdef XF86DRM_MODE - if (info->cs) - info->accel_state->draw_header = info->cs->packets + info->cs->cdw; - else -#endif - info->accel_state->draw_header = __head; + info->accel_state->draw_header = info->cs->packets + info->cs->cdw; info->accel_state->num_vtx = 0; info->accel_state->vtx_count = vtx_count; @@ -2408,12 +2338,7 @@ static void FUNC_NAME(RadeonCompositeTile)(ScrnInfoPtr pScrn, if (!info->accel_state->draw_header) { BEGIN_RING(2); -#ifdef XF86DRM_MODE - if (info->cs) - info->accel_state->draw_header = info->cs->packets + info->cs->cdw; - else -#endif - info->accel_state->draw_header = __head; + info->accel_state->draw_header = info->cs->packets + info->cs->cdw; info->accel_state->num_vtx = 0; info->accel_state->vtx_count = vtx_count; @@ -2431,12 +2356,7 @@ static void FUNC_NAME(RadeonCompositeTile)(ScrnInfoPtr pScrn, if (!info->accel_state->draw_header) { BEGIN_RING(2); -#ifdef XF86DRM_MODE - if (info->cs) - info->accel_state->draw_header = info->cs->packets + info->cs->cdw; - else -#endif - info->accel_state->draw_header = __head; + info->accel_state->draw_header = info->cs->packets + info->cs->cdw; info->accel_state->num_vtx = 0; info->accel_state->vtx_count = vtx_count; @@ -2452,28 +2372,6 @@ static void FUNC_NAME(RadeonCompositeTile)(ScrnInfoPtr pScrn, BEGIN_RING(3 * vtx_count); } -#else /* ACCEL_CP */ - if (IS_R300_3D || IS_R500_3D) - BEGIN_ACCEL(2 + vtx_count * 4); - else - BEGIN_ACCEL(1 + vtx_count * 3); - - if (info->ChipFamily < CHIP_FAMILY_R200) - OUT_ACCEL_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_RECTANGLE_LIST | - RADEON_VF_PRIM_WALK_DATA | - RADEON_VF_RADEON_MODE | - (3 << RADEON_VF_NUM_VERTICES_SHIFT))); - else if (IS_R300_3D || IS_R500_3D) - OUT_ACCEL_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_QUAD_LIST | - RADEON_VF_PRIM_WALK_DATA | - (4 << RADEON_VF_NUM_VERTICES_SHIFT))); - else - OUT_ACCEL_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_RECTANGLE_LIST | - RADEON_VF_PRIM_WALK_DATA | - (3 << RADEON_VF_NUM_VERTICES_SHIFT))); - -#endif - if (info->accel_state->msk_pic) { if (IS_R300_3D || IS_R500_3D) { VTX_OUT_MASK((float)dstX, (float)dstY, @@ -2502,11 +2400,7 @@ static void FUNC_NAME(RadeonCompositeTile)(ScrnInfoPtr pScrn, xFixedToFloat(srcTopRight.x) / info->accel_state->texW[0], xFixedToFloat(srcTopRight.y) / info->accel_state->texH[0]); } -#ifdef ACCEL_CP ADVANCE_RING(); -#else - FINISH_ACCEL(); -#endif /* !ACCEL_CP */ LEAVE_DRAW(0); } diff --git a/src/radeon_exa_shared.c b/src/radeon_exa_shared.c index b83eb81c..a1a7cf96 100644 --- a/src/radeon_exa_shared.c +++ b/src/radeon_exa_shared.c @@ -35,9 +35,6 @@ #endif #include "radeon.h" -#ifdef XF86DRI -#include "radeon_drm.h" -#endif #include "radeon_macros.h" #include "radeon_probe.h" #include "radeon_version.h" @@ -128,76 +125,32 @@ Bool RADEONCheckBPP(int bpp) PixmapPtr RADEONSolidPixmap(ScreenPtr pScreen, uint32_t solid) { - ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); - RADEONInfoPtr info = RADEONPTR(pScrn); PixmapPtr pPix = pScreen->CreatePixmap(pScreen, 1, 1, 32, 0); - + struct radeon_bo *bo; exaMoveInPixmap(pPix); -#if defined(XF86DRM_MODE) - if (info->cs) { - struct radeon_bo *bo; - - bo = radeon_get_pixmap_bo(pPix); - - if (radeon_bo_map(bo, 1)) { - pScreen->DestroyPixmap(pPix); - return NULL; - } - - memcpy(bo->ptr, &solid, 4); - radeon_bo_unmap(bo); + bo = radeon_get_pixmap_bo(pPix); - return pPix; - } -#endif - - if (!exaDrawableIsOffscreen(&pPix->drawable)) { + if (radeon_bo_map(bo, 1)) { pScreen->DestroyPixmap(pPix); return NULL; } - /* XXX: Big hammer... */ - info->accel_state->exa->WaitMarker(pScreen, info->accel_state->exaSyncMarker); - memcpy(info->FB + exaGetPixmapOffset(pPix), &solid, 4); + memcpy(bo->ptr, &solid, 4); + radeon_bo_unmap(bo); return pPix; } -static Bool radeon_vb_get(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - struct radeon_accel_state *accel_state = info->accel_state; - - accel_state->vbo.vb_mc_addr = info->gartLocation + info->dri->bufStart + - (accel_state->ib->idx*accel_state->ib->total)+ - (accel_state->ib->total / 2); - accel_state->vbo.vb_total = (accel_state->ib->total / 2); - accel_state->vbo.vb_ptr = (pointer)((char*)accel_state->ib->address + - (accel_state->ib->total / 2)); - accel_state->vbo.vb_offset = 0; - return TRUE; -} - int radeon_cp_start(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; -#if defined(XF86DRM_MODE) - if (info->cs) { - if (CS_FULL(info->cs)) { - radeon_cs_flush_indirect(pScrn); - } - accel_state->ib_reset_op = info->cs->cdw; - } else -#endif - { - accel_state->ib = RADEONCPGetBuffer(pScrn); - if (!radeon_vb_get(pScrn)) { - return -1; - } + if (CS_FULL(info->cs)) { + radeon_cs_flush_indirect(pScrn); } + accel_state->ib_reset_op = info->cs->cdw; accel_state->vbo.vb_start_op = accel_state->vbo.vb_offset; accel_state->cbuf.vb_start_op = accel_state->cbuf.vb_offset; return 0; @@ -210,30 +163,20 @@ void radeon_vb_no_space(ScrnInfoPtr pScrn, RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; -#if defined(XF86DRM_MODE) - if (info->cs) { - if (vbo->vb_bo) { - if (vbo->vb_start_op != vbo->vb_offset) { - accel_state->finish_op(pScrn, vert_size); - accel_state->ib_reset_op = info->cs->cdw; - } - - /* release the current VBO */ - radeon_vbo_put(pScrn, vbo); + if (vbo->vb_bo) { + if (vbo->vb_start_op != vbo->vb_offset) { + accel_state->finish_op(pScrn, vert_size); + accel_state->ib_reset_op = info->cs->cdw; } - /* get a new one */ - radeon_vbo_get(pScrn, vbo); - return; - } -#endif - if (vbo->vb_start_op != -1) { - accel_state->finish_op(pScrn, vert_size); - radeon_cp_start(pScrn); + + /* release the current VBO */ + radeon_vbo_put(pScrn, vbo); } + /* get a new one */ + radeon_vbo_get(pScrn, vbo); return; } -#if defined(XF86DRM_MODE) void radeon_ib_discard(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); @@ -277,4 +220,3 @@ void radeon_ib_discard(ScrnInfoPtr pScrn) } } -#endif diff --git a/src/radeon_exa_shared.h b/src/radeon_exa_shared.h index 60a10459..3df7fa20 100644 --- a/src/radeon_exa_shared.h +++ b/src/radeon_exa_shared.h @@ -62,7 +62,6 @@ do { \ #define TRACE #endif -#ifdef XF86DRM_MODE static inline void radeon_add_pixmap(struct radeon_cs *cs, PixmapPtr pPix, int read_domains, int write_domain) { struct radeon_exa_pixmap_priv *driver_priv = exaGetPixmapDriverPrivate(pPix); @@ -71,7 +70,6 @@ static inline void radeon_add_pixmap(struct radeon_cs *cs, PixmapPtr pPix, int r } extern void radeon_ib_discard(ScrnInfoPtr pScrn); -#endif /* XF86DRM_MODE */ extern int radeon_cp_start(ScrnInfoPtr pScrn); extern void radeon_vb_no_space(ScrnInfoPtr pScrn, struct radeon_vbo_object *vbo, int vert_size); diff --git a/src/radeon_kms.c b/src/radeon_kms.c index b6c035d2..f9d4178b 100644 --- a/src/radeon_kms.c +++ b/src/radeon_kms.c @@ -40,8 +40,13 @@ #include "atipciids.h" - -#ifdef XF86DRM_MODE +/* DPMS */ +#ifdef HAVE_XEXTPROTO_71 +#include <X11/extensions/dpmsconst.h> +#else +#define DPMS_SERVER +#include <X11/extensions/dpms.h> +#endif #include "radeon_chipset_gen.h" #include "radeon_chipinfo_gen.h" @@ -76,6 +81,8 @@ const OptionInfoRec RADEONOptions_KMS[] = { { -1, NULL, OPTV_NONE, {0}, FALSE } }; +const OptionInfoRec *RADEONOptionsWeak(void) { return RADEONOptions_KMS; } + void radeon_cs_flush_indirect(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); @@ -202,8 +209,6 @@ static void RADEONBlockHandler_KMS(BLOCKHANDLER_ARGS_DECL) (*pScreen->BlockHandler) (BLOCKHANDLER_ARGS); pScreen->BlockHandler = RADEONBlockHandler_KMS; - if (info->VideoTimerCallback) - (*info->VideoTimerCallback)(pScrn, currentTime.milliseconds); radeon_cs_flush_indirect(pScrn); } @@ -231,7 +236,7 @@ static Bool RADEONIsFusionGARTWorking(ScrnInfoPtr pScrn) memset(&ginfo, 0, sizeof(ginfo)); ginfo.request = RADEON_INFO_FUSION_GART_WORKING; ginfo.value = (uintptr_t)&tmp; - r = drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_INFO, &ginfo, sizeof(ginfo)); + r = drmCommandWriteRead(info->dri2.drm_fd, DRM_RADEON_INFO, &ginfo, sizeof(ginfo)); if (r) { return FALSE; } @@ -255,12 +260,12 @@ static Bool RADEONIsAccelWorking(ScrnInfoPtr pScrn) #endif memset(&ginfo, 0, sizeof(ginfo)); - if (info->dri->pKernelDRMVersion->version_minor >= 5) + if (info->dri2.pKernelDRMVersion->version_minor >= 5) ginfo.request = RADEON_INFO_ACCEL_WORKING2; else ginfo.request = RADEON_INFO_ACCEL_WORKING; ginfo.value = (uintptr_t)&tmp; - r = drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_INFO, &ginfo, sizeof(ginfo)); + r = drmCommandWriteRead(info->dri2.drm_fd, DRM_RADEON_INFO, &ginfo, sizeof(ginfo)); if (r) { /* If kernel is too old before 2.6.32 than assume accel is working */ if (r == -EINVAL) { @@ -312,9 +317,7 @@ static Bool RADEONPreInitAccel_KMS(ScrnInfoPtr pScrn) info->accel_state->has_tcl = TRUE; } - info->useEXA = TRUE; - - if (info->useEXA) { + { int errmaj = 0, errmin = 0; info->exaReq.majorversion = EXA_VERSION_MAJOR; info->exaReq.minorversion = EXA_VERSION_MINOR; @@ -356,7 +359,6 @@ static Bool RADEONPreInitChipType_KMS(ScrnInfoPtr pScrn) if (info->Chipset == RADEONCards[i].pci_device_id) { RADEONCardInfo *card = &RADEONCards[i]; info->ChipFamily = card->chip_family; - info->IsMobility = card->mobility; info->IsIGP = card->igp; break; } @@ -409,21 +411,6 @@ static Bool RADEONPreInitChipType_KMS(ScrnInfoPtr pScrn) return TRUE; } -static Bool radeon_alloc_dri(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - if (!(info->dri = calloc(1, sizeof(struct radeon_dri)))) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Unable to allocate dri rec!\n"); - return FALSE; - } - - if (!(info->cp = calloc(1, sizeof(struct radeon_cp)))) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Unable to allocate cp rec!\n"); - return FALSE; - } - return TRUE; -} - static Bool radeon_open_drm_master(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); @@ -481,7 +468,6 @@ static Bool radeon_open_drm_master(ScrnInfoPtr pScrn) pRADEONEnt->fd = info->dri2.drm_fd; out: info->drmmode.fd = info->dri2.drm_fd; - info->dri->drmFD = info->dri2.drm_fd; return TRUE; } @@ -504,14 +490,14 @@ static Bool r600_get_tile_config(ScrnInfoPtr pScrn) memset(&ginfo, 0, sizeof(ginfo)); ginfo.request = RADEON_INFO_TILING_CONFIG; ginfo.value = (uintptr_t)&tmp; - r = drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_INFO, &ginfo, sizeof(ginfo)); + r = drmCommandWriteRead(info->dri2.drm_fd, DRM_RADEON_INFO, &ginfo, sizeof(ginfo)); if (r) return FALSE; info->tile_config = tmp; info->r7xx_bank_op = 0; if (info->ChipFamily >= CHIP_FAMILY_CEDAR) { - if (info->dri->pKernelDRMVersion->version_minor >= 7) { + if (info->dri2.pKernelDRMVersion->version_minor >= 7) { switch (info->tile_config & 0xf) { case 0: info->num_channels = 1; @@ -615,10 +601,8 @@ Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int flags) if (!RADEONGetRec(pScrn)) return FALSE; info = RADEONPTR(pScrn); - info->MMIO = NULL; info->IsSecondary = FALSE; info->IsPrimary = FALSE; - info->kms_enabled = TRUE; info->pEnt = xf86GetEntityInfo(pScrn->entityList[pScrn->numEntities - 1]); if (info->pEnt->location.type != BUS_PCI) goto fail; @@ -661,17 +645,14 @@ Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int flags) if (!RADEONPreInitChipType_KMS(pScrn)) goto fail; - if (!radeon_alloc_dri(pScrn)) - return FALSE; - if (radeon_open_drm_master(pScrn) == FALSE) { xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Kernel modesetting setup failed\n"); goto fail; } info->dri2.enabled = FALSE; - info->dri->pKernelDRMVersion = drmGetVersion(info->dri->drmFD); - if (info->dri->pKernelDRMVersion == NULL) { + info->dri2.pKernelDRMVersion = drmGetVersion(info->dri2.drm_fd); + if (info->dri2.pKernelDRMVersion == NULL) { xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "RADEONDRIGetVersion failed to get the DRM version\n"); goto fail; @@ -698,7 +679,7 @@ Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int flags) /* set default group bytes, overridden by kernel info below */ info->group_bytes = 256; info->have_tiling_info = FALSE; - if (info->dri->pKernelDRMVersion->version_minor >= 6) { + if (info->dri2.pKernelDRMVersion->version_minor >= 6) { if (r600_get_tile_config(pScrn)) { info->allowColorTiling = xf86ReturnOptValBool(info->Options, OPTION_COLOR_TILING, colorTilingDefault); @@ -724,7 +705,7 @@ Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int flags) xf86DrvMsg(pScrn->scrnIndex, X_INFO, "KMS Color Tiling: %sabled\n", info->allowColorTiling ? "en" : "dis"); - if (info->dri->pKernelDRMVersion->version_minor >= 8) { + if (info->dri2.pKernelDRMVersion->version_minor >= 8) { info->allowPageFlip = xf86ReturnOptValBool(info->Options, OPTION_PAGE_FLIP, TRUE); xf86DrvMsg(pScrn->scrnIndex, X_INFO, @@ -769,7 +750,7 @@ Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int flags) { struct drm_radeon_gem_info mminfo; - if (!drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_GEM_INFO, &mminfo, sizeof(mminfo))) + if (!drmCommandWriteRead(info->dri2.drm_fd, DRM_RADEON_GEM_INFO, &mminfo, sizeof(mminfo))) { info->vram_size = mminfo.vram_visible; info->gart_size = mminfo.gart_size; @@ -838,6 +819,49 @@ static Bool RADEONCursorInit_KMS(ScreenPtr pScreen) HARDWARE_CURSOR_ARGB)); } +void +RADEONBlank(ScrnInfoPtr pScrn) +{ + xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); + xf86OutputPtr output; + xf86CrtcPtr crtc; + int o, c; + + for (c = 0; c < xf86_config->num_crtc; c++) { + crtc = xf86_config->crtc[c]; + for (o = 0; o < xf86_config->num_output; o++) { + output = xf86_config->output[o]; + if (output->crtc != crtc) + continue; + + output->funcs->dpms(output, DPMSModeOff); + } + crtc->funcs->dpms(crtc, DPMSModeOff); + } +} + +void +RADEONUnblank(ScrnInfoPtr pScrn) +{ + xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); + xf86OutputPtr output; + xf86CrtcPtr crtc; + int o, c; + for (c = 0; c < xf86_config->num_crtc; c++) { + crtc = xf86_config->crtc[c]; + if(!crtc->enabled) + continue; + crtc->funcs->dpms(crtc, DPMSModeOn); + for (o = 0; o < xf86_config->num_output; o++) { + output = xf86_config->output[o]; + if (output->crtc != crtc) + continue; + output->funcs->dpms(output, DPMSModeOn); + } + } +} + + static Bool RADEONSaveScreen_KMS(ScreenPtr pScreen, int mode) { ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); @@ -871,8 +895,7 @@ static Bool RADEONCloseScreen_KMS(CLOSE_SCREEN_ARGS_DECL) "RADEONCloseScreen\n"); drmmode_uevent_fini(pScrn, &info->drmmode); - if (info->cs) - radeon_cs_flush_indirect(pScrn); + radeon_cs_flush_indirect(pScrn); DeleteCallback(&FlushCallback, radeon_flush_callback, pScrn); @@ -885,10 +908,7 @@ static Bool RADEONCloseScreen_KMS(CLOSE_SCREEN_ARGS_DECL) if (info->accel_state->use_vbos) radeon_vbo_free_lists(pScrn); - drmDropMaster(info->dri->drmFD); - - if (info->cursor) xf86DestroyCursorInfoRec(info->cursor); - info->cursor = NULL; + drmDropMaster(info->dri2.drm_fd); if (info->dri2.enabled) radeon_dri2_close_screen(pScreen); @@ -933,7 +953,7 @@ Bool RADEONScreenInit_KMS(SCREEN_INIT_ARGS_DECL) pScrn->defaultVisual)) return FALSE; miSetPixmapDepths (); - ret = drmSetMaster(info->dri->drmFD); + ret = drmSetMaster(info->dri2.drm_fd); if (ret) { ErrorF("Unable to retrieve master\n"); return FALSE; @@ -942,11 +962,9 @@ Bool RADEONScreenInit_KMS(SCREEN_INIT_ARGS_DECL) if (info->r600_shadow_fb == FALSE) info->directRenderingEnabled = radeon_dri2_screen_init(pScreen); - front_ptr = info->FB; - - info->surf_man = radeon_surface_manager_new(info->dri->drmFD); + info->surf_man = radeon_surface_manager_new(info->dri2.drm_fd); if (!info->bufmgr) - info->bufmgr = radeon_bo_manager_gem_ctor(info->dri->drmFD); + info->bufmgr = radeon_bo_manager_gem_ctor(info->dri2.drm_fd); if (!info->bufmgr) { xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "failed to initialise GEM buffer manager"); @@ -955,7 +973,7 @@ Bool RADEONScreenInit_KMS(SCREEN_INIT_ARGS_DECL) drmmode_set_bufmgr(pScrn, &info->drmmode, info->bufmgr); if (!info->csm) - info->csm = radeon_cs_manager_gem_ctor(info->dri->drmFD); + info->csm = radeon_cs_manager_gem_ctor(info->dri2.drm_fd); if (!info->csm) { xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "failed to initialise command submission manager"); @@ -1158,7 +1176,7 @@ Bool RADEONEnterVT_KMS(VT_FUNC_ARGS_DECL) "RADEONEnterVT_KMS\n"); - ret = drmSetMaster(info->dri->drmFD); + ret = drmSetMaster(info->dri2.drm_fd); if (ret) ErrorF("Unable to retrieve master\n"); info->accel_state->XInited3D = FALSE; @@ -1169,9 +1187,6 @@ Bool RADEONEnterVT_KMS(VT_FUNC_ARGS_DECL) if (!drmmode_set_desired_modes(pScrn, &info->drmmode)) return FALSE; - if (info->adaptor) - RADEONResetVideo(pScrn); - return TRUE; } @@ -1184,7 +1199,7 @@ void RADEONLeaveVT_KMS(VT_FUNC_ARGS_DECL) xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "RADEONLeaveVT_KMS\n"); - drmDropMaster(info->dri->drmFD); + drmDropMaster(info->dri2.drm_fd); #ifdef HAVE_FREE_SHADOW xf86RotateFreeShadow(pScrn); @@ -1341,8 +1356,6 @@ static Bool radeon_setup_kernel_mem(ScreenPtr pScreen) /* keep area front front buffer - but don't allocate it yet */ total_size_bytes += screen_size; - info->dri->textureSize = 0; - if (info->front_bo == NULL) { info->front_bo = radeon_bo_open(info->bufmgr, 0, screen_size, base_align, RADEON_GEM_DOMAIN_VRAM, 0); @@ -1392,5 +1405,30 @@ void radeon_kms_update_vram_limit(ScrnInfoPtr pScrn, int new_fb_size) xf86DrvMsg(pScrn->scrnIndex, X_INFO, "VRAM usage limit set to %dK\n", remain_size_bytes / 1024); } +/* Used to disallow modes that are not supported by the hardware */ +ModeStatus RADEONValidMode(SCRN_ARG_TYPE arg, DisplayModePtr mode, + Bool verbose, int flag) +{ + SCRN_INFO_PTR(arg); + RADEONInfoPtr info = RADEONPTR(pScrn); + RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); -#endif + /* + * RN50 has effective maximum mode bandwidth of about 300MiB/s. + * XXX should really do this for all chips by properly computing + * memory bandwidth and an overhead factor. + */ + if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2) { + if (xf86ModeBandwidth(mode, pScrn->bitsPerPixel) > 300) + return MODE_BANDWIDTH; + } + /* There are problems with double scan mode at high clocks + * They're likely related PLL and display buffer settings. + * Disable these modes for now. + */ + if (mode->Flags & V_DBLSCAN) { + if ((mode->CrtcHDisplay >= 1024) || (mode->CrtcVDisplay >= 768)) + return MODE_CLOCK_RANGE; + } + return MODE_OK; +} diff --git a/src/radeon_legacy_memory.c b/src/radeon_legacy_memory.c index b01ba8cc..c5ba8e8e 100644 --- a/src/radeon_legacy_memory.c +++ b/src/radeon_legacy_memory.c @@ -18,126 +18,27 @@ radeon_legacy_allocate_memory(ScrnInfoPtr pScrn, int align, int domain) { - ScreenPtr pScreen = xf86ScrnToScreen(pScrn); RADEONInfoPtr info = RADEONPTR(pScrn); - uint32_t offset = 0; + struct radeon_bo *video_bo; -#ifdef XF86DRM_MODE - if (info->cs) { - struct radeon_bo *video_bo; + if (*mem_struct) + radeon_legacy_free_memory(pScrn, *mem_struct); - if (*mem_struct) - radeon_legacy_free_memory(pScrn, *mem_struct); + video_bo = radeon_bo_open(info->bufmgr, 0, size, align, domain, 0); - video_bo = radeon_bo_open(info->bufmgr, 0, size, align, domain, 0); + *mem_struct = video_bo; - *mem_struct = video_bo; + if (!video_bo) + return 0; - if (!video_bo) - return 0; - - return (uint32_t)-1; - } -#endif -#ifdef USE_EXA - if (info->useEXA) { - ExaOffscreenArea *area = *mem_struct; - - if (area != NULL) { - if (area->size >= size) - return area->offset; - - exaOffscreenFree(pScreen, area); - } - - area = exaOffscreenAlloc(pScreen, size, align, TRUE, - NULL, NULL); - - *mem_struct = area; - if (area == NULL) - return 0; - offset = area->offset; - } -#endif /* USE_EXA */ -#ifdef USE_XAA - if (!info->useEXA) { - FBLinearPtr linear = *mem_struct; - int cpp = info->CurrentLayout.bitsPerPixel / 8; - - /* XAA allocates in units of pixels at the screen bpp, so adjust size - * appropriately. - */ - size = (size + cpp - 1) / cpp; - align = (align + cpp - 1) / cpp; - - if (linear) { - if(linear->size >= size) - return linear->offset * cpp; - - if(xf86ResizeOffscreenLinear(linear, size)) - return linear->offset * cpp; - - xf86FreeOffscreenLinear(linear); - } - - linear = xf86AllocateOffscreenLinear(pScreen, size, align, - NULL, NULL, NULL); - *mem_struct = linear; - - if (!linear) { - int max_size; - - xf86QueryLargestOffscreenLinear(pScreen, &max_size, align, - PRIORITY_EXTREME); - - if (max_size < size) - return 0; - - xf86PurgeUnlockedOffscreenAreas(pScreen); - linear = xf86AllocateOffscreenLinear(pScreen, size, align, - NULL, NULL, NULL); - *mem_struct = linear; - if (!linear) - return 0; - } - offset = linear->offset * cpp; - } -#endif /* USE_XAA */ - - return offset; + return (uint32_t)-1; } void radeon_legacy_free_memory(ScrnInfoPtr pScrn, - void *mem_struct) + void *mem_struct) { - RADEONInfoPtr info = RADEONPTR(pScrn); - -#ifdef XF86DRM_MODE - if (info->cs) { - struct radeon_bo *bo = mem_struct; - radeon_bo_unref(bo); - return; - } -#endif -#ifdef USE_EXA - ScreenPtr pScreen = xf86ScrnToScreen(pScrn); - - if (info->useEXA) { - ExaOffscreenArea *area = mem_struct; - - if (area != NULL) - exaOffscreenFree(pScreen, area); - area = NULL; - } -#endif /* USE_EXA */ -#ifdef USE_XAA - if (!info->useEXA) { - FBLinearPtr linear = mem_struct; - - if (linear != NULL) - xf86FreeOffscreenLinear(linear); - linear = NULL; - } -#endif /* USE_XAA */ + struct radeon_bo *bo = mem_struct; + radeon_bo_unref(bo); + return; } diff --git a/src/radeon_macros.h b/src/radeon_macros.h index 26d98250..25a51cef 100644 --- a/src/radeon_macros.h +++ b/src/radeon_macros.h @@ -51,159 +51,31 @@ #include "compiler.h" -#define RADEON_BIOS8(v) (info->VBIOS[v]) -#define RADEON_BIOS16(v) (info->VBIOS[v] | \ - (info->VBIOS[(v) + 1] << 8)) -#define RADEON_BIOS32(v) (info->VBIOS[v] | \ - (info->VBIOS[(v) + 1] << 8) | \ - (info->VBIOS[(v) + 2] << 16) | \ - (info->VBIOS[(v) + 3] << 24)) - /* Memory mapped register access macros */ -#define INREG8(addr) MMIO_IN8(RADEONMMIO, addr) -#define INREG16(addr) MMIO_IN16(RADEONMMIO, addr) -#define INREG(addr) MMIO_IN32(RADEONMMIO, addr) -#define OUTREG8(addr, val) MMIO_OUT8(RADEONMMIO, addr, val) -#define OUTREG16(addr, val) MMIO_OUT16(RADEONMMIO, addr, val) -#define OUTREG(addr, val) MMIO_OUT32(RADEONMMIO, addr, val) - -#define ADDRREG(addr) ((volatile uint32_t *)(pointer)(RADEONMMIO + (addr))) - - -#define OUTREGP(addr, val, mask) \ -do { \ - uint32_t tmp = INREG(addr); \ - tmp &= (mask); \ - tmp |= ((val) & ~(mask)); \ - OUTREG(addr, tmp); \ -} while (0) - -#define INPLL(pScrn, addr) RADEONINPLL(pScrn, addr) - -#define OUTPLL(pScrn, addr, val) RADEONOUTPLL(pScrn, addr, val) - -#define OUTPLLP(pScrn, addr, val, mask) \ -do { \ - uint32_t tmp_ = INPLL(pScrn, addr); \ - tmp_ &= (mask); \ - tmp_ |= ((val) & ~(mask)); \ - OUTPLL(pScrn, addr, tmp_); \ -} while (0) - -#define OUTPAL_START(idx) \ -do { \ - if (IS_AVIVO_VARIANT) { \ - OUTREG8(AVIVO_DC_LUT_RW_INDEX, (idx)); \ - } else { \ - OUTREG8(RADEON_PALETTE_INDEX, (idx)); \ - } \ -} while (0) - -#define OUTPAL_NEXT(r, g, b) \ -do { \ - if (IS_AVIVO_VARIANT) { \ - OUTREG(AVIVO_DC_LUT_30_COLOR, ((r) << 20) | ((g) << 10) | (b)); \ - } else { \ - OUTREG(RADEON_PALETTE_30_DATA, ((r) << 20) | ((g) << 10) | (b)); \ - } \ -} while (0) - -#define OUTPAL(idx, r, g, b) \ -do { \ - OUTPAL_START((idx)); \ - OUTPAL_NEXT((r), (g), (b)); \ -} while (0) - -#define INPAL_START(idx) \ -do { \ - if (IS_AVIVO_VARIANT) { \ - OUTREG8(AVIVO_DC_LUT_RW_INDEX, (idx)); \ - } else { \ - OUTREG(RADEON_PALETTE_INDEX, (idx) << 16); \ - } \ -} while (0) - -#define INPAL_NEXT() \ -do { \ - if (IS_AVIVO_VARIANT) { \ - INREG(AVIVO_DC_LUT_30_COLOR); \ - } else { \ - INREG(RADEON_PALETTE_30_DATA); \ - } \ -} while (0) - -#define PAL_SELECT(idx) \ -do { \ - if (IS_AVIVO_VARIANT) { \ - if (!idx) { \ - OUTREG(AVIVO_DC_LUT_RW_SELECT, 0); \ - } else { \ - OUTREG(AVIVO_DC_LUT_RW_SELECT, 1); \ - } \ - } else { \ - if (!idx) { \ - OUTREG(RADEON_DAC_CNTL2, INREG(RADEON_DAC_CNTL2) & \ - (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL); \ - } else { \ - OUTREG(RADEON_DAC_CNTL2, INREG(RADEON_DAC_CNTL2) | \ - RADEON_DAC2_PALETTE_ACC_CTL); \ - } \ - } \ -} while (0) - -#define INMC(pScrn, addr) RADEONINMC(pScrn, addr) -#define OUTMC(pScrn, addr, val) RADEONOUTMC(pScrn, addr, val) - -#define INPCIE(pScrn, addr) RADEONINPCIE(pScrn, addr) -#define OUTPCIE(pScrn, addr, val) RADEONOUTPCIE(pScrn, addr, val) - -#define INPCIE_P(pScrn, addr) R600INPCIE_PORT(pScrn, addr) -#define OUTPCIE_P(pScrn, addr, val) R600OUTPCIE_PORT(pScrn, addr, val) #define BEGIN_ACCEL_RELOC(n, r) do { \ - int _nqw = (n) + (info->cs ? (r) : 0); \ + int _nqw = (n) + (r); \ BEGIN_ACCEL(_nqw); \ } while (0) -#define CHECK_OFFSET(pPix, mask, type) do { \ - if (!info->cs) { \ - uint32_t _pix_offset = radeonGetPixmapOffset(pPix); \ - if ((_pix_offset & mask) != 0) \ - RADEON_FALLBACK(("Bad %s offset 0x%x\n", type, (int)_pix_offset)); \ - } \ - } while(0) - #define EMIT_OFFSET(reg, value, pPix, rd, wd) do { \ - if (info->cs) { \ - driver_priv = exaGetPixmapDriverPrivate(pPix); \ - OUT_ACCEL_REG((reg), (value)); \ - OUT_RELOC(driver_priv->bo, (rd), (wd)); \ - } else { \ - uint32_t _pix_offset; \ - _pix_offset = radeonGetPixmapOffset(pPix); \ - OUT_ACCEL_REG((reg), _pix_offset | value); \ - } \ + driver_priv = exaGetPixmapDriverPrivate(pPix); \ + OUT_ACCEL_REG((reg), (value)); \ + OUT_RELOC(driver_priv->bo, (rd), (wd)); \ } while(0) #define EMIT_READ_OFFSET(reg, value, pPix) EMIT_OFFSET(reg, value, pPix, (RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT), 0) #define EMIT_WRITE_OFFSET(reg, value, pPix) EMIT_OFFSET(reg, value, pPix, 0, RADEON_GEM_DOMAIN_VRAM) #define OUT_TEXTURE_REG(reg, offset, bo) do { \ - if (info->cs) { \ - OUT_ACCEL_REG((reg), (offset)); \ - OUT_RELOC((bo), RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0); \ - } else { \ - OUT_ACCEL_REG((reg), (offset) + info->fbLocation + pScrn->fbOffset);} \ + OUT_ACCEL_REG((reg), (offset)); \ + OUT_RELOC((bo), RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0); \ } while(0) #define EMIT_COLORPITCH(reg, value, pPix) do { \ - if (info->cs) { \ - driver_priv = exaGetPixmapDriverPrivate(pPix); \ - OUT_ACCEL_REG((reg), value); \ - OUT_RELOC(driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM); \ - } else { \ - OUT_ACCEL_REG((reg), value); \ - } \ + driver_priv = exaGetPixmapDriverPrivate(pPix); \ + OUT_ACCEL_REG((reg), value); \ + OUT_RELOC(driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM); \ }while(0) #endif diff --git a/src/radeon_mm_i2c.c b/src/radeon_mm_i2c.c deleted file mode 100644 index bb454073..00000000 --- a/src/radeon_mm_i2c.c +++ /dev/null @@ -1,642 +0,0 @@ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include <math.h> - -#include "radeon.h" -#include "radeon_reg.h" -#include "radeon_macros.h" -#include "radeon_probe.h" -#include <X11/extensions/Xv.h> -#include "radeon_video.h" -#include "atipciids.h" - -#include "xf86.h" - -/* i2c stuff */ -#include "xf86i2c.h" -#include "fi1236.h" -#include "msp3430.h" -#include "tda9885.h" -#include "uda1380.h" -#include "i2c_def.h" - - -static void RADEON_TDA9885_Init(RADEONPortPrivPtr pPriv); - -/* Wait for 10ms at the most for the I2C_GO register to drop. */ -#define I2C_WAIT_FOR_GO() { \ - int i2ctries = 0; \ - RADEONWaitForIdleMMIO(pScrn); \ - write_mem_barrier(); \ - while (i2ctries < 10) { \ - reg = INREG8(RADEON_I2C_CNTL_0+1); \ - if (!(reg & (RADEON_I2C_GO >> 8))) \ - break; \ - if (reg & (RADEON_I2C_ABORT >> 8)) \ - break; \ - usleep(1000); \ - i2ctries++; \ - } \ -} - -/* Wait, and dump the status in the 'status' register. If we time out or - * receive an abort signal, halt/restart the I2C bus and leave _ABORT in the - * status register. */ -#define I2C_WAIT_WITH_STATUS() { \ - I2C_WAIT_FOR_GO() \ - if (reg & ((RADEON_I2C_ABORT >> 8) | (RADEON_I2C_GO >> 8))) { \ - RADEON_I2C_Halt(pScrn); \ - status = RADEON_I2C_ABORT; \ - } \ - else \ - status = RADEON_I2C_WaitForAck(pScrn, pPriv); \ -} - -/**************************************************************************** - * I2C_WaitForAck (void) * - * * - * Function: polls the I2C status bits, waiting for an acknowledge or * - * an error condition. * - * Inputs: NONE * - * Outputs: I2C_DONE - the I2C transfer was completed * - * I2C_NACK - an NACK was received from the slave * - * I2C_HALT - a timeout condition has occured * - ****************************************************************************/ -static uint8_t RADEON_I2C_WaitForAck (ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) -{ - uint8_t retval = 0; - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - long counter = 0; - - usleep(1000); - while(1) - { - RADEONWaitForIdleMMIO(pScrn); - retval = INREG8(RADEON_I2C_CNTL_0); - if (retval & RADEON_I2C_HALT) - { - return (RADEON_I2C_HALT); - } - if (retval & RADEON_I2C_NACK) - { - return (RADEON_I2C_NACK); - } - if(retval & RADEON_I2C_DONE) - { - return RADEON_I2C_DONE; - } - counter++; - /* 50ms ought to be long enough. */ - if(counter > 50) - { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Timeout condition on Radeon i2c bus\n"); - return RADEON_I2C_HALT; - } - usleep(1000); - } -} - -static void RADEON_I2C_Halt (ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - uint8_t reg; - - /* reset status flags */ - RADEONWaitForIdleMMIO(pScrn); - reg = INREG8 (RADEON_I2C_CNTL_0 + 0) & ~(RADEON_I2C_DONE|RADEON_I2C_NACK|RADEON_I2C_HALT); - OUTREG8 (RADEON_I2C_CNTL_0 + 0, reg); - - /* issue ABORT call */ - RADEONWaitForIdleMMIO(pScrn); - reg = INREG8 (RADEON_I2C_CNTL_0 + 1) & 0xE7; - OUTREG8 (RADEON_I2C_CNTL_0 + 1, (reg |((RADEON_I2C_GO|RADEON_I2C_ABORT) >> 8))); - - /* wait for GO bit to go low */ - I2C_WAIT_FOR_GO(); -} - - -static Bool RADEONI2CWriteRead(I2CDevPtr d, I2CByte *WriteBuffer, int nWrite, - I2CByte *ReadBuffer, int nRead) -{ - int loop, status; - uint32_t i2c_cntl_0, i2c_cntl_1; - uint8_t reg; - RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)(d->pI2CBus->DriverPrivate.ptr); - ScrnInfoPtr pScrn = xf86Screens[d->pI2CBus->scrnIndex]; - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - status=RADEON_I2C_DONE; - - RADEONWaitForIdleMMIO(pScrn); - if(nWrite>0){ -/* RADEONWaitForFifo(pScrn, 4+nWrite); */ - - /* Clear the status bits of the I2C Controller */ - OUTREG(RADEON_I2C_CNTL_0, RADEON_I2C_DONE | RADEON_I2C_NACK | RADEON_I2C_HALT | RADEON_I2C_SOFT_RST); - - /* Write the address into the buffer first */ - OUTREG(RADEON_I2C_DATA, (uint32_t) (d->SlaveAddr) & ~(1)); - - /* Write Value into the buffer */ - for (loop = 0; loop < nWrite; loop++) - { - OUTREG8(RADEON_I2C_DATA, WriteBuffer[loop]); - } - - i2c_cntl_1 = (pPriv->radeon_i2c_timing << 24) | RADEON_I2C_EN | RADEON_I2C_SEL | - nWrite | 0x100; - OUTREG(RADEON_I2C_CNTL_1, i2c_cntl_1); - - i2c_cntl_0 = (pPriv->radeon_N << 24) | (pPriv->radeon_M << 16) | - RADEON_I2C_GO | RADEON_I2C_START | ((nRead >0)?0:RADEON_I2C_STOP) | RADEON_I2C_DRIVE_EN; - OUTREG(RADEON_I2C_CNTL_0, i2c_cntl_0); - - I2C_WAIT_WITH_STATUS(); - - if(status!=RADEON_I2C_DONE){ - RADEON_I2C_Halt(pScrn); - return FALSE; - } - } - - - if(nRead > 0) { - RADEONWaitForFifo(pScrn, 4+nRead); - - OUTREG(RADEON_I2C_CNTL_0, RADEON_I2C_DONE | RADEON_I2C_NACK | RADEON_I2C_HALT | RADEON_I2C_SOFT_RST); - - /* Write the address into the buffer first */ - OUTREG(RADEON_I2C_DATA, (uint32_t) (d->SlaveAddr) | (1)); - - i2c_cntl_1 = (pPriv->radeon_i2c_timing << 24) | RADEON_I2C_EN | RADEON_I2C_SEL | - nRead | 0x100; - OUTREG(RADEON_I2C_CNTL_1, i2c_cntl_1); - - i2c_cntl_0 = (pPriv->radeon_N << 24) | (pPriv->radeon_M << 16) | - RADEON_I2C_GO | RADEON_I2C_START | RADEON_I2C_STOP | RADEON_I2C_DRIVE_EN | RADEON_I2C_RECEIVE; - OUTREG(RADEON_I2C_CNTL_0, i2c_cntl_0); - - I2C_WAIT_WITH_STATUS(); - - /* Write Value into the buffer */ - for (loop = 0; loop < nRead; loop++) - { - RADEONWaitForFifo(pScrn, 1); - if((status == RADEON_I2C_HALT) || (status == RADEON_I2C_NACK)) - { - ReadBuffer[loop]=0xff; - } else { - RADEONWaitForIdleMMIO(pScrn); - ReadBuffer[loop]=INREG8(RADEON_I2C_DATA) & 0xff; - } - } - } - - if(status!=RADEON_I2C_DONE){ - RADEON_I2C_Halt(pScrn); - return FALSE; - } - return TRUE; -} - -static Bool R200_I2CWriteRead(I2CDevPtr d, I2CByte *WriteBuffer, int nWrite, - I2CByte *ReadBuffer, int nRead) -{ - int loop, status; - uint32_t i2c_cntl_0, i2c_cntl_1; - uint8_t reg; - RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)(d->pI2CBus->DriverPrivate.ptr); - ScrnInfoPtr pScrn = xf86Screens[d->pI2CBus->scrnIndex]; - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - status=RADEON_I2C_DONE; - - RADEONWaitForIdleMMIO(pScrn); - if(nWrite>0){ -/* RADEONWaitForFifo(pScrn, 4+nWrite); */ - - /* Clear the status bits of the I2C Controller */ - OUTREG(RADEON_I2C_CNTL_0, RADEON_I2C_DONE | RADEON_I2C_NACK | RADEON_I2C_HALT | RADEON_I2C_SOFT_RST); - - /* Write the address into the buffer first */ - OUTREG(RADEON_I2C_DATA, (uint32_t) (d->SlaveAddr) & ~(1)); - - /* Write Value into the buffer */ - for (loop = 0; loop < nWrite; loop++) - { - OUTREG8(RADEON_I2C_DATA, WriteBuffer[loop]); - } - - i2c_cntl_1 = (pPriv->radeon_i2c_timing << 24) | RADEON_I2C_EN | RADEON_I2C_SEL | - nWrite | 0x010; - OUTREG(RADEON_I2C_CNTL_1, i2c_cntl_1); - - i2c_cntl_0 = (pPriv->radeon_N << 24) | (pPriv->radeon_M << 16) | - RADEON_I2C_GO | RADEON_I2C_START | ((nRead >0)?0:RADEON_I2C_STOP) | RADEON_I2C_DRIVE_EN; - OUTREG(RADEON_I2C_CNTL_0, i2c_cntl_0); - - I2C_WAIT_WITH_STATUS(); - - if(status!=RADEON_I2C_DONE){ - RADEON_I2C_Halt(pScrn); - return FALSE; - } - } - - - if(nRead > 0) { - RADEONWaitForFifo(pScrn, 4+nRead); - - OUTREG(RADEON_I2C_CNTL_0, RADEON_I2C_DONE | RADEON_I2C_NACK | RADEON_I2C_HALT | RADEON_I2C_SOFT_RST); - - /* Write the address into the buffer first */ - OUTREG(RADEON_I2C_DATA, (uint32_t) (d->SlaveAddr) | (1)); - - i2c_cntl_1 = (pPriv->radeon_i2c_timing << 24) | RADEON_I2C_EN | RADEON_I2C_SEL | - nRead | 0x010; - OUTREG(RADEON_I2C_CNTL_1, i2c_cntl_1); - - i2c_cntl_0 = (pPriv->radeon_N << 24) | (pPriv->radeon_M << 16) | - RADEON_I2C_GO | RADEON_I2C_START | RADEON_I2C_STOP | RADEON_I2C_DRIVE_EN | RADEON_I2C_RECEIVE; - OUTREG(RADEON_I2C_CNTL_0, i2c_cntl_0); - - I2C_WAIT_WITH_STATUS(); - - RADEONWaitForIdleMMIO(pScrn); - /* Write Value into the buffer */ - for (loop = 0; loop < nRead; loop++) - { - if((status == RADEON_I2C_HALT) || (status == RADEON_I2C_NACK)) - { - ReadBuffer[loop]=0xff; - } else { - ReadBuffer[loop]=INREG8(RADEON_I2C_DATA) & 0xff; - } - } - } - - if(status!=RADEON_I2C_DONE){ - RADEON_I2C_Halt(pScrn); - return FALSE; - } - return TRUE; -} - -#if 0 -static Bool RADEONProbeAddress(I2CBusPtr b, I2CSlaveAddr addr) -{ - I2CByte a; - I2CDevRec d; - - d.DevName = "Probing"; - d.SlaveAddr = addr; - d.pI2CBus = b; - d.NextDev = NULL; - - return I2C_WriteRead(&d, NULL, 0, &a, 1); -} -#endif - -#define I2C_CLOCK_FREQ (60000.0) - - -const struct -{ - char *name; - int type; -} RADEON_tuners[32] = - { - /* name ,index to tuner_parms table */ - {"NO TUNER" , -1}, - {"Philips FI1236 (or compatible)" , TUNER_TYPE_FI1236}, - {"Philips FI1236 (or compatible)" , TUNER_TYPE_FI1236}, - {"Philips FI1216 (or compatible)" , TUNER_TYPE_FI1216}, - {"Philips FI1246 (or compatible)" , TUNER_TYPE_FI1246}, - {"Philips FI1216MF (or compatible)" , TUNER_TYPE_FI1216}, - {"Philips FI1236 (or compatible)" , TUNER_TYPE_FI1236}, - {"Philips FI1256 (or compatible)" , TUNER_TYPE_FI1256}, - {"Philips FI1236 (or compatible)" , TUNER_TYPE_FI1236}, - {"Philips FI1216 (or compatible)" , TUNER_TYPE_FI1216}, - {"Philips FI1246 (or compatible)" , TUNER_TYPE_FI1246}, - {"Philips FI1216MF (or compatible)" , TUNER_TYPE_FI1216}, - {"Philips FI1236 (or compatible)" , TUNER_TYPE_FI1236}, - {"TEMIC-FN5AL" , TUNER_TYPE_TEMIC_FN5AL}, - {"FQ1216ME/P" , TUNER_TYPE_FI1216}, - {"FI1236W" , TUNER_TYPE_FI1236W}, - {"Philips FI1216ME (or compatible)" , TUNER_TYPE_FM1216ME}, - /*{"Alps TSCxx" , -1},*/ - {"Philips FM1236/F" , TUNER_TYPE_FI1236W}, - {"Philips FI1216ME (or compatible)" , TUNER_TYPE_FM1216ME}, - {"UNKNOWN-19" , -1}, - {"UNKNOWN-20" , -1}, - {"UNKNOWN-21" , -1}, - {"UNKNOWN-22" , -1}, - {"UNKNOWN-23" , -1}, - {"UNKNOWN-24" , -1}, - {"UNKNOWN-25" , -1}, - {"UNKNOWN-26" , -1}, - {"UNKNOWN-27" , -1}, - {"UNKNOWN-28" , -1}, - {"Microtuner MT2032" , TUNER_TYPE_MT2032}, - {"Microtuner MT2032" , TUNER_TYPE_MT2032}, - {"UNKNOWN-31" , -1} - }; - - -void RADEONResetI2C(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - RADEONWaitForFifo(pScrn, 2); - OUTREG8(RADEON_I2C_CNTL_1+2, ((RADEON_I2C_SEL | RADEON_I2C_EN)>>16)); - OUTREG8(RADEON_I2C_CNTL_0+0, (RADEON_I2C_DONE | RADEON_I2C_NACK | RADEON_I2C_HALT | RADEON_I2C_SOFT_RST | RADEON_I2C_DRIVE_EN | RADEON_I2C_DRIVE_SEL)); -} - -void RADEONInitI2C(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) -{ - double nm; - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONPLLPtr pll = &(info->pll); - - pPriv->i2c = NULL; - pPriv->fi1236 = NULL; - pPriv->msp3430 = NULL; - pPriv->tda9885 = NULL; - pPriv->uda1380 = NULL; - #if 0 /* put back on when saa7114 support is present */ - pPriv->saa7114 = NULL; - #endif - - /* Blacklist chipsets that lockup - these are usually older mobility chips */ - - switch(info->Chipset){ - case PCI_CHIP_RADEON_LY: - case PCI_CHIP_RADEON_LZ: - xf86DrvMsg(pScrn->scrnIndex,X_INFO,"Detected Radeon Mobility M6, disabling multimedia i2c\n"); - return; - case PCI_CHIP_RADEON_LW: - xf86DrvMsg(pScrn->scrnIndex,X_INFO,"Detected Radeon Mobility M7, disabling multimedia i2c\n"); - return; - /*case PCI_CHIP_RV250_If: - xf86DrvMsg(pScrn->scrnIndex,X_INFO,"Detected Radeon 9000 - skipping multimedia i2c initialization code.\n"); - return;*/ - case PCI_CHIP_RV370_5460: - xf86DrvMsg(pScrn->scrnIndex,X_INFO,"Detected Radeon Mobility X300, disabling multimedia i2c\n"); - return; - } - - /* no multimedia capabilities detected and no information was provided to substitute for it */ - if(!info->MM_TABLE_valid && - !(info->tunerType>=0)) - { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "No video input capabilities detected and no information is provided - disabling multimedia i2c\n"); - return; - } - - - if(pPriv->i2c!=NULL) return; /* for some reason we are asked to init it again.. Stop ! */ - - if(!xf86LoadSubModule(pScrn,"i2c")) - { - xf86DrvMsg(pScrn->scrnIndex,X_ERROR,"Unable to initialize i2c bus\n"); - pPriv->i2c = NULL; - return; - } - pPriv->i2c=CreateI2CBusRec(); - pPriv->i2c->scrnIndex=pScrn->scrnIndex; - pPriv->i2c->BusName="Radeon multimedia bus"; - pPriv->i2c->DriverPrivate.ptr=(pointer)pPriv; - switch(info->ChipFamily){ - case CHIP_FAMILY_RV350: - case CHIP_FAMILY_R350: - case CHIP_FAMILY_R300: - case CHIP_FAMILY_RV250: - case CHIP_FAMILY_R200: - case CHIP_FAMILY_RV200: - pPriv->i2c->I2CWriteRead=R200_I2CWriteRead; - xf86DrvMsg(pScrn->scrnIndex,X_INFO,"Using R200 i2c bus access method\n"); - break; - default: - pPriv->i2c->I2CWriteRead=RADEONI2CWriteRead; - xf86DrvMsg(pScrn->scrnIndex,X_INFO,"Using Radeon bus access method\n"); - } - if(!I2CBusInit(pPriv->i2c)) - { - xf86DrvMsg(pScrn->scrnIndex,X_ERROR,"Failed to register i2c bus\n"); - } - -#if 1 - switch(info->ChipFamily){ - case CHIP_FAMILY_RV200: - nm=(pll->reference_freq * 40000.0)/(1.0*I2C_CLOCK_FREQ); - break; - case CHIP_FAMILY_R300: - case CHIP_FAMILY_R200: - if(info->MM_TABLE_valid && (RADEON_tuners[info->MM_TABLE.tuner_type & 0x1f].type==TUNER_TYPE_MT2032)){ - nm=(pll->reference_freq * 40000.0)/(4.0*I2C_CLOCK_FREQ); - break; - } - default: - nm=(pll->reference_freq * 10000.0)/(4.0*I2C_CLOCK_FREQ); - } -#else - nm=(pll->xclk * 40000.0)/(1.0*I2C_CLOCK_FREQ); -#endif - for(pPriv->radeon_N=1; pPriv->radeon_N<255; pPriv->radeon_N++) - if((pPriv->radeon_N * (pPriv->radeon_N-1)) > nm)break; - pPriv->radeon_M=pPriv->radeon_N-1; - pPriv->radeon_i2c_timing=2*pPriv->radeon_N; - - -#if 0 - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "ref=%d M=0x%02x N=0x%02x timing=0x%02x\n", pll->reference_freq, pPriv->radeon_M, pPriv->radeon_N, pPriv->radeon_i2c_timing); - pPriv->radeon_M=0x32; - pPriv->radeon_N=0x33; - pPriv->radeon_i2c_timing=2*pPriv->radeon_N; -#endif - RADEONResetI2C(pScrn, pPriv); - -#if 0 /* I don't know whether standalone boards are supported with Radeons */ - /* looks like none of them have AMC connectors anyway */ - if(!info->MM_TABLE_valid)RADEON_read_eeprom(pPriv); -#endif - - if(!xf86LoadSubModule(pScrn,"fi1236")) - { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unable to initialize fi1236 driver\n"); - } - else - { - if(pPriv->fi1236 == NULL) - { - pPriv->fi1236 = xf86_Detect_FI1236(pPriv->i2c, FI1236_ADDR_1); - } - if(pPriv->fi1236 == NULL) - { - pPriv->fi1236 = xf86_Detect_FI1236(pPriv->i2c, FI1236_ADDR_2); - } - } - if(pPriv->fi1236 != NULL) - { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Detected %s device at 0x%02x\n", - RADEON_tuners[info->MM_TABLE.tuner_type & 0x1f].name, - FI1236_ADDR(pPriv->fi1236)); - if(info->MM_TABLE_valid)xf86_FI1236_set_tuner_type(pPriv->fi1236, RADEON_tuners[info->MM_TABLE.tuner_type & 0x1f].type); - else { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "MM_TABLE not found (standalone board ?), forcing tuner type to NTSC\n"); - xf86_FI1236_set_tuner_type(pPriv->fi1236, TUNER_TYPE_FI1236); - } - } - - if(info->MM_TABLE_valid && (RADEON_tuners[info->MM_TABLE.tuner_type & 0x1f].type==TUNER_TYPE_MT2032)){ - if(!xf86LoadSubModule(pScrn,"tda9885")) - { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unable to initialize tda9885 driver\n"); - } - else - { - if(pPriv->tda9885 == NULL) - { - pPriv->tda9885 = xf86_Detect_tda9885(pPriv->i2c, TDA9885_ADDR_1); - } - if(pPriv->tda9885 == NULL) - { - pPriv->tda9885 = xf86_Detect_tda9885(pPriv->i2c, TDA9885_ADDR_2); - } - if(pPriv->tda9885 != NULL) - { - RADEON_TDA9885_Init(pPriv); - } - } - } - - if(info->MM_TABLE_valid && ((RADEON_tuners[info->MM_TABLE.tuner_type & 0x1f].type==TUNER_TYPE_FM1216ME) - || (RADEON_tuners[info->MM_TABLE.tuner_type & 0x1f].type==TUNER_TYPE_FI1236W))) - { - if(!xf86LoadSubModule(pScrn,"tda9885")) - { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unable to initialize tda9885 driver\n"); - } - else - { - if(pPriv->tda9885 == NULL) - { - pPriv->tda9885 = xf86_Detect_tda9885(pPriv->i2c, TDA9885_ADDR_1); - } - if(pPriv->tda9885 == NULL) - { - pPriv->tda9885 = xf86_Detect_tda9885(pPriv->i2c, TDA9885_ADDR_2); - } - if(pPriv->tda9885 != NULL) - { - RADEON_TDA9885_Init(pPriv); - pPriv->fi1236->afc_source = (void*)pPriv->tda9885; - } - } - } - - if(!xf86LoadSubModule(pScrn,"uda1380")) - { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unable to initialize uda1380 driver\n"); - } - else - { - if(pPriv->uda1380 == NULL) - { - pPriv->uda1380 = xf86_Detect_uda1380(pPriv->i2c, UDA1380_ADDR_1); - } - if(pPriv->uda1380 == NULL) - { - pPriv->uda1380 = xf86_Detect_uda1380(pPriv->i2c, UDA1380_ADDR_2); - } - if(pPriv->uda1380 != NULL) - { - xf86_uda1380_init(pPriv->uda1380); - } - } - - - if(!xf86LoadSubModule(pScrn,"msp3430")) - { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unable to initialize msp3430 driver\n"); - } - else - { - if(pPriv->msp3430 == NULL) - { - pPriv->msp3430 = xf86_DetectMSP3430(pPriv->i2c, MSP3430_ADDR_1); - } - if(pPriv->msp3430 == NULL) - { - pPriv->msp3430 = xf86_DetectMSP3430(pPriv->i2c, MSP3430_ADDR_2); - } -#if 0 /* this would confuse bt829 with msp3430 */ - if(pPriv->msp3430 == NULL) - { - pPriv->msp3430 = xf86_DetectMSP3430(pPriv->i2c, MSP3430_ADDR_3); - } -#endif - } - if(pPriv->msp3430 != NULL) - { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Detected MSP3430 at 0x%02x\n", - MSP3430_ADDR(pPriv->msp3430)); - pPriv->msp3430->standard = MSP3430_NTSC; - pPriv->msp3430->connector = MSP3430_CONNECTOR_1; - xf86_ResetMSP3430(pPriv->msp3430); - xf86_InitMSP3430(pPriv->msp3430); - xf86_MSP3430SetVolume(pPriv->msp3430, pPriv->mute ? MSP3430_FAST_MUTE : MSP3430_VOLUME(pPriv->volume)); - } - -#if 0 /* put this back when saa7114 driver is ready */ - if(!xf86LoadSubModule(pScrn,"saa7114")) - { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unable to initialize saa7114 driver\n"); - } - else - { - if(pPriv->saa7114 == NULL) - { - pPriv->saa7114 = xf86_DetectSAA7114(pPriv->i2c, SAA7114_ADDR_1); - } - if(pPriv->saa7114 == NULL) - { - pPriv->saa7114 = xf86_DetectSAA7114(pPriv->i2c, SAA7114_ADDR_2); - } - } - if(pPriv->saa7114 != NULL) - { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Detected SAA7114 at 0x%02x\n", - pPriv->saa7114->d.SlaveAddr); - xf86_InitSAA7114(pPriv->saa7114); - } -#endif - -} - -static void RADEON_TDA9885_Init(RADEONPortPrivPtr pPriv) -{ -TDA9885Ptr t=pPriv->tda9885; -t->sound_trap=0; -t->auto_mute_fm=1; /* ? */ -t->carrier_mode=0; /* ??? */ -t->modulation=2; /* negative FM */ -t->forced_mute_audio=0; -t->port1=1; -t->port2=1; -t->top_adjustment=0x10; -t->deemphasis=1; -t->audio_gain=0; -t->minimum_gain=0; -t->gating=0; -t->vif_agc=1; /* set to 1 ? - depends on design */ -t->gating=0; -} diff --git a/src/radeon_modes.c b/src/radeon_modes.c deleted file mode 100644 index 215cde31..00000000 --- a/src/radeon_modes.c +++ /dev/null @@ -1,542 +0,0 @@ -/* - * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and - * VA Linux Systems Inc., Fremont, California. - * - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation on the rights to use, copy, modify, merge, - * publish, distribute, sublicense, and/or sell copies of the Software, - * and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR - * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -/* - * Authors: - * Kevin E. Martin <martin@xfree86.org> - * Rickard E. Faith <faith@valinux.com> - * Alan Hourihane <alanh@fairlite.demon.co.uk> - */ - -#include <string.h> -#include <stdio.h> - -#include "xf86.h" - /* Driver data structures */ -#include "randrstr.h" -#include "radeon_probe.h" -#include "radeon.h" -#include "radeon_reg.h" -#include "radeon_macros.h" -#include "radeon_version.h" -#include "radeon_atombios.h" - -#include "xf86Modes.h" - /* DDC support */ -#include "xf86DDC.h" -#include <randrstr.h> - -void RADEONSetPitch (ScrnInfoPtr pScrn) -{ - int dummy = pScrn->virtualX; - RADEONInfoPtr info = RADEONPTR(pScrn); - int pitch_mask = 0; - int align_large; - - align_large = info->allowColorTiling || IS_AVIVO_VARIANT; - - /* FIXME: May need to validate line pitch here */ - if (info->ChipFamily < CHIP_FAMILY_R600) { - switch (pScrn->depth / 8) { - case 1: pitch_mask = align_large ? 256 : 128; - break; - case 2: pitch_mask = align_large ? 128 : 32; - break; - case 3: - case 4: pitch_mask = align_large ? 64 : 16; - break; - } - } else - pitch_mask = 256; /* r6xx/r7xx need 256B alignment for accel */ - - dummy = RADEON_ALIGN(pScrn->virtualX, pitch_mask); - pScrn->displayWidth = dummy; - info->CurrentLayout.displayWidth = pScrn->displayWidth; - -} - -static DisplayModePtr -RADEONTVModes(xf86OutputPtr output) -{ - DisplayModePtr new = NULL; - - /* just a place holder */ - new = xf86CVTMode(800, 600, 60.00, FALSE, FALSE); - new->type = M_T_DRIVER | M_T_PREFERRED; - - return new; -} - -static DisplayModePtr -RADEONATOMTVModes(xf86OutputPtr output) -{ - DisplayModePtr last = NULL; - DisplayModePtr new = NULL; - DisplayModePtr first = NULL; - int i; - /* Add some common sizes */ - int widths[5] = {640, 720, 800, 848, 1024}; - int heights[5] = {480, 480, 600, 480, 768}; - - for (i = 0; i < 5; i++) { - new = xf86CVTMode(widths[i], heights[i], 60.0, FALSE, FALSE); - - new->type = M_T_DRIVER; - - new->next = NULL; - new->prev = last; - - if (last) last->next = new; - last = new; - if (!first) first = new; - } - - if (last) { - last->next = NULL; //first; - first->prev = NULL; //last; - } - - return first; -} - -/* This is used only when no mode is specified for FP and no ddc is - * available. We force it to native mode, if possible. - */ -static DisplayModePtr RADEONFPNativeMode(xf86OutputPtr output) -{ - ScrnInfoPtr pScrn = output->scrn; - RADEONOutputPrivatePtr radeon_output = output->driver_private; - radeon_native_mode_ptr native_mode = &radeon_output->native_mode; - DisplayModePtr new = NULL; - char stmp[32]; - - if (native_mode->PanelXRes != 0 && - native_mode->PanelYRes != 0 && - native_mode->DotClock != 0) { - - new = xnfcalloc(1, sizeof (DisplayModeRec)); - sprintf(stmp, "%dx%d", native_mode->PanelXRes, native_mode->PanelYRes); - new->name = xnfalloc(strlen(stmp) + 1); - strcpy(new->name, stmp); - new->HDisplay = native_mode->PanelXRes; - new->VDisplay = native_mode->PanelYRes; - - new->HTotal = new->HDisplay + native_mode->HBlank; - new->HSyncStart = new->HDisplay + native_mode->HOverPlus; - new->HSyncEnd = new->HSyncStart + native_mode->HSyncWidth; - new->VTotal = new->VDisplay + native_mode->VBlank; - new->VSyncStart = new->VDisplay + native_mode->VOverPlus; - new->VSyncEnd = new->VSyncStart + native_mode->VSyncWidth; - - new->Clock = native_mode->DotClock; - new->Flags = native_mode->Flags; - - if (new) { - new->type = M_T_DRIVER | M_T_PREFERRED; - - new->next = NULL; - new->prev = NULL; - } - - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Added native panel mode: %dx%d\n", - native_mode->PanelXRes, native_mode->PanelYRes); - } else if (native_mode->PanelXRes != 0 && - native_mode->PanelYRes != 0) { - - new = xf86CVTMode(native_mode->PanelXRes, native_mode->PanelYRes, 60.0, TRUE, FALSE); - - if (new) { - new->type = M_T_DRIVER | M_T_PREFERRED; - - new->next = NULL; - new->prev = NULL; - } - - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Added native panel mode using CVT: %dx%d\n", - native_mode->PanelXRes, native_mode->PanelYRes); - } - - return new; -} - -#if defined(__powerpc__) -/* Apple eMacs need special modes for the internal CRT, e.g., - * Modeline "640x480" 62.12 640 680 752 864 480 481 484 521 +HSync +Vsync - * Modeline "800x600" 76.84 800 848 936 1072 600 601 604 640 +HSync +Vsync - * Modeline "1024x768" 99.07 1024 1088 1200 1376 768 769 772 809 +HSync +Vsync - * Modeline "1152x864" 112.36 1152 1224 1352 1552 864 865 868 905 +HSync +Vsync - * Modeline "1280x960" 124.54 1280 1368 1504 1728 960 961 964 1001 +HSync +Vsync - */ -static DisplayModePtr RADEONeMacModes(xf86OutputPtr output) -{ - ScrnInfoPtr pScrn = output->scrn; - DisplayModePtr last=NULL, new=NULL, first=NULL; - int i, *modep; - static const char *modenames[5] = { - "640x480", "800x600", "1024x768", "1152x864", "1280x960" - }; - static int modes[9*5] = { - 62120, 640, 680, 752, 864, 480, 481, 484, 521, - 76840, 800, 848, 936, 1072, 600, 601, 604, 640, - 99070, 1024, 1088, 1200, 1376, 768, 769, 772, 809, - 112360, 1152, 1224, 1352, 1552, 864, 865, 868, 905, - 124540, 1280, 1368, 1504, 1728, 960, 961, 964, 1001 - }; - modep = modes; - - for (i=0; i<5; i++) { - new = xnfcalloc(1, sizeof (DisplayModeRec)); - if (new) { - new->name = xnfalloc(strlen(modenames[i]) + 1); - strcpy(new->name, modenames[i]); - new->Clock = *modep++; - - new->HDisplay = *modep++; - new->HSyncStart = *modep++; - new->HSyncEnd = *modep++; - new->HTotal = *modep++; - - new->VDisplay = *modep++; - new->VSyncStart = *modep++; - new->VSyncEnd = *modep++; - new->VTotal = *modep++; - - new->Flags = 0; - new->type = M_T_DRIVER; - if (i==2) - new->type |= M_T_PREFERRED; - new->next = NULL; - new->prev = last; - if (last) last->next = new; - last = new; - if (!first) first = new; - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Added eMac mode %s\n", modenames[i]); - } - } - - return first; -} -#endif - -/* this function is basically a hack to add the screen modes */ -static void RADEONAddScreenModes(xf86OutputPtr output, DisplayModePtr *modeList) -{ - ScrnInfoPtr pScrn = output->scrn; - RADEONOutputPrivatePtr radeon_output = output->driver_private; - radeon_native_mode_ptr native_mode = &radeon_output->native_mode; - DisplayModePtr last = NULL; - DisplayModePtr new = NULL; - DisplayModePtr first = NULL; - int count = 0; - int i, width, height; - char **ppModeName = pScrn->display->modes; - - first = last = *modeList; - - /* We have a flat panel connected to the primary display, and we - * don't have any DDC info. - */ - for (i = 0; ppModeName[i] != NULL; i++) { - - if (sscanf(ppModeName[i], "%dx%d", &width, &height) != 2) continue; - - if (radeon_output->active_device & (ATOM_DEVICE_LCD_SUPPORT)) { - /* already added the native mode */ - if (width == native_mode->PanelXRes && height == native_mode->PanelYRes) - continue; - - /* Note: We allow all non-standard modes as long as they do not - * exceed the native resolution of the panel. Since these modes - * need the internal RMX unit in the video chips (and there is - * only one per card), this will only apply to the primary head. - */ - if (width < 320 || width > native_mode->PanelXRes || - height < 200 || height > native_mode->PanelYRes) { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "Mode %s is out of range.\n", ppModeName[i]); - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "Valid FP modes must be between 320x200-%dx%d\n", - native_mode->PanelXRes, native_mode->PanelYRes); - continue; - } - } - - new = xf86CVTMode(width, height, 60.0, FALSE, FALSE); - - new->type |= M_T_USERDEF; - - new->next = NULL; - new->prev = last; - - if (last) last->next = new; - last = new; - if (!first) first = new; - - count++; - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Adding Screen mode: %s\n", new->name); - } - - - /* Close the doubly-linked mode list, if we found any usable modes */ - if (last) { - last->next = NULL; //first; - first->prev = NULL; //last; - *modeList = first; - } - - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Total number of valid Screen mode(s) added: %d\n", count); - -} - -/* BIOS may not have right panel size, we search through all supported - * DDC modes looking for the maximum panel size. - */ -static void -RADEONUpdatePanelSize(xf86OutputPtr output) -{ - ScrnInfoPtr pScrn = output->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONOutputPrivatePtr radeon_output = output->driver_private; - radeon_native_mode_ptr native_mode = &radeon_output->native_mode; - int j; - xf86MonPtr ddc = output->MonInfo; - DisplayModePtr p; - - // update output's native mode - if (radeon_output->active_device & (ATOM_DEVICE_LCD_SUPPORT)) { - radeon_encoder_ptr radeon_encoder = radeon_get_encoder(output); - if (radeon_encoder) { - radeon_lvds_ptr lvds = (radeon_lvds_ptr)radeon_encoder->dev_priv; - if (lvds) - radeon_output->native_mode = lvds->native_mode; - } - } - - // crtc should handle? - if ((info->UseBiosDividers && native_mode->DotClock != 0) || (ddc == NULL)) - return; - - /* Go thru detailed timing table first */ - for (j = 0; j < 4; j++) { - if (ddc->det_mon[j].type == 0) { - struct detailed_timings *d_timings = - &ddc->det_mon[j].section.d_timings; - int match = 0; - - /* If we didn't get a panel clock or guessed one, try to match the - * mode with the panel size. We do that because we _need_ a panel - * clock, or ValidateFPModes will fail, even when UseBiosDividers - * is set. - */ - if (native_mode->DotClock == 0 && - native_mode->PanelXRes == d_timings->h_active && - native_mode->PanelYRes == d_timings->v_active) - match = 1; - - /* If we don't have a BIOS provided panel data with fixed dividers, - * check for a larger panel size - */ - if (native_mode->PanelXRes < d_timings->h_active && - native_mode->PanelYRes < d_timings->v_active && - !info->UseBiosDividers) - match = 1; - - if (match) { - native_mode->PanelXRes = d_timings->h_active; - native_mode->PanelYRes = d_timings->v_active; - native_mode->DotClock = d_timings->clock / 1000; - native_mode->HOverPlus = d_timings->h_sync_off; - native_mode->HSyncWidth = d_timings->h_sync_width; - native_mode->HBlank = d_timings->h_blanking; - native_mode->VOverPlus = d_timings->v_sync_off; - native_mode->VSyncWidth = d_timings->v_sync_width; - native_mode->VBlank = d_timings->v_blanking; - native_mode->Flags = (d_timings->interlaced ? V_INTERLACE : 0); - switch (d_timings->misc) { - case 0: native_mode->Flags |= V_NHSYNC | V_NVSYNC; break; - case 1: native_mode->Flags |= V_PHSYNC | V_NVSYNC; break; - case 2: native_mode->Flags |= V_NHSYNC | V_PVSYNC; break; - case 3: native_mode->Flags |= V_PHSYNC | V_PVSYNC; break; - } - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Panel infos found from DDC detailed: %dx%d\n", - native_mode->PanelXRes, native_mode->PanelYRes); - } - } - } - - if (info->UseBiosDividers && native_mode->DotClock != 0) - return; - - /* Search thru standard VESA modes from EDID */ - for (j = 0; j < 8; j++) { - if ((native_mode->PanelXRes < ddc->timings2[j].hsize) && - (native_mode->PanelYRes < ddc->timings2[j].vsize)) { - for (p = pScrn->monitor->Modes; p; p = p->next) { - if ((ddc->timings2[j].hsize == p->HDisplay) && - (ddc->timings2[j].vsize == p->VDisplay)) { - float refresh = - (float)p->Clock * 1000.0 / p->HTotal / p->VTotal; - - if (abs((float)ddc->timings2[j].refresh - refresh) < 1.0) { - /* Is this good enough? */ - native_mode->PanelXRes = ddc->timings2[j].hsize; - native_mode->PanelYRes = ddc->timings2[j].vsize; - native_mode->HBlank = p->HTotal - p->HDisplay; - native_mode->HOverPlus = p->HSyncStart - p->HDisplay; - native_mode->HSyncWidth = p->HSyncEnd - p->HSyncStart; - native_mode->VBlank = p->VTotal - p->VDisplay; - native_mode->VOverPlus = p->VSyncStart - p->VDisplay; - native_mode->VSyncWidth = p->VSyncEnd - p->VSyncStart; - native_mode->DotClock = p->Clock; - native_mode->Flags = p->Flags; - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Panel infos found from DDC VESA/EDID: %dx%d\n", - native_mode->PanelXRes, native_mode->PanelYRes); - } - } - } - } - } -} - -static void -radeon_add_common_modes(xf86OutputPtr output, DisplayModePtr modes) -{ - RADEONOutputPrivatePtr radeon_output = output->driver_private; - radeon_native_mode_ptr native_mode = &radeon_output->native_mode; - DisplayModePtr last = NULL; - DisplayModePtr new = NULL; - DisplayModePtr first = NULL; - int i; - /* Add some common sizes */ - int widths[15] = {640, 800, 1024, 1152, 1280, 1280, 1280, 1280, 1280, 1440, 1400, 1680, 1600, 1920, 1920}; - int heights[15] = {480, 600, 768, 768, 720, 800, 854, 960, 1024, 900, 1050, 1050, 1200, 1080, 1200}; - - for (i = 0; i < 15; i++) { - if (radeon_output->active_device & (ATOM_DEVICE_LCD_SUPPORT)) { - /* already added the native mode */ - if (widths[i] == native_mode->PanelXRes && heights[i] == native_mode->PanelYRes) - continue; - - /* Note: We allow all non-standard modes as long as they do not - * exceed the native resolution of the panel. Since these modes - * need the internal RMX unit in the video chips (and there is - * only one per card), this will only apply to the primary head. - */ - if (widths[i] < 320 || widths[i] > native_mode->PanelXRes || - heights[i] < 200 || heights[i] > native_mode->PanelYRes) - continue; - } - - new = xf86CVTMode(widths[i], heights[i], 60.0, FALSE, FALSE); - - new->type = M_T_DRIVER; - - new->next = NULL; - new->prev = last; - - if (last) last->next = new; - last = new; - if (!first) first = new; - } - - if (last) { - last->next = NULL; //first; - first->prev = NULL; //last; - } - - xf86ModesAdd(modes, first); - -} - -DisplayModePtr -RADEONProbeOutputModes(xf86OutputPtr output) -{ - RADEONOutputPrivatePtr radeon_output = output->driver_private; - ScrnInfoPtr pScrn = output->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - DisplayModePtr modes = NULL; - AtomBiosArgRec atomBiosArg; - AtomBiosResult atomBiosResult; - - if (output->status == XF86OutputStatusConnected) { - if (radeon_output->active_device & (ATOM_DEVICE_TV_SUPPORT)) { - if (IS_AVIVO_VARIANT) - modes = RADEONATOMTVModes(output); - else - modes = RADEONTVModes(output); - } else if (radeon_output->active_device & (ATOM_DEVICE_CV_SUPPORT)) { - atomBiosResult = RHDAtomBiosFunc(pScrn, info->atomBIOS, - ATOMBIOS_GET_CV_MODES, &atomBiosArg); - if (atomBiosResult == ATOM_SUCCESS) { - modes = atomBiosArg.modes; - } - } else { - if (radeon_output->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) - RADEONUpdatePanelSize(output); - if (output->MonInfo) - modes = xf86OutputGetEDIDModes (output); -#if defined(__powerpc__) - if ((info->MacModel == RADEON_MAC_EMAC) && - (radeon_output->active_device & ATOM_DEVICE_CRT1_SUPPORT) && - (modes == NULL)) - modes = RADEONeMacModes(output); -#endif - if (modes == NULL) { - if ((radeon_output->active_device & (ATOM_DEVICE_LCD_SUPPORT)) && info->IsAtomBios) { - atomBiosResult = RHDAtomBiosFunc(pScrn, - info->atomBIOS, - ATOMBIOS_GET_PANEL_EDID, &atomBiosArg); - if (atomBiosResult == ATOM_SUCCESS) { - output->MonInfo = xf86InterpretEDID(pScrn->scrnIndex, - atomBiosArg.EDIDBlock); - modes = xf86OutputGetEDIDModes(output); - } - } - if (modes == NULL) { - if (radeon_output->active_device & (ATOM_DEVICE_LCD_SUPPORT)) - modes = RADEONFPNativeMode(output); - /* add the screen modes */ - if (modes == NULL) - RADEONAddScreenModes(output, &modes); - } - } - } - } - - if (radeon_output->active_device & (ATOM_DEVICE_LCD_SUPPORT)) - radeon_add_common_modes(output, modes); - - return modes; -} - diff --git a/src/radeon_output.c b/src/radeon_output.c deleted file mode 100644 index aec7e653..00000000 --- a/src/radeon_output.c +++ /dev/null @@ -1,3193 +0,0 @@ -/* - * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and - * VA Linux Systems Inc., Fremont, California. - * - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation on the rights to use, copy, modify, merge, - * publish, distribute, sublicense, and/or sell copies of the Software, - * and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR - * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include <string.h> -#include <stdio.h> -#include <fcntl.h> - -/* X and server generic header files */ -#include "xf86.h" -#include "xf86_OSproc.h" -#include "vgaHW.h" -#include "xf86Modes.h" - -/* Driver data structures */ -#include "radeon.h" -#include "radeon_reg.h" -#include "radeon_macros.h" -#include "radeon_probe.h" -#include "radeon_version.h" -#include "radeon_tv.h" -#include "radeon_atombios.h" - -const char *encoder_name[34] = { - "NONE", - "INTERNAL_LVDS", - "INTERNAL_TMDS1", - "INTERNAL_TMDS2", - "INTERNAL_DAC1", - "INTERNAL_DAC2", - "INTERNAL_SDVOA", - "INTERNAL_SDVOB", - "SI170B", - "CH7303", - "CH7301", - "INTERNAL_DVO1", - "EXTERNAL_SDVOA", - "EXTERNAL_SDVOB", - "TITFP513", - "INTERNAL_LVTM1", - "VT1623", - "HDMI_SI1930", - "HDMI_INTERNAL", - "INTERNAL_KLDSCP_TMDS1", - "INTERNAL_KLDSCP_DVO1", - "INTERNAL_KLDSCP_DAC1", - "INTERNAL_KLDSCP_DAC2", - "SI178", - "MVPU_FPGA", - "INTERNAL_DDI", - "VT1625", - "HDMI_SI1932", - "DP_AN9801", - "DP_DP501", - "INTERNAL_UNIPHY", - "INTERNAL_KLDSCP_LVTMA", - "INTERNAL_UNIPHY1", - "INTERNAL_UNIPHY2", -}; - -const char *ConnectorTypeName[18] = { - "None", - "VGA", - "DVI-I", - "DVI-D", - "DVI-A", - "S-video", - "Composite", - "LVDS", - "Digital", - "SCART", - "HDMI-A", - "HDMI-B", - "Unsupported", - "Unsupported", - "DIN", - "DisplayPort", - "eDP", - "Unsupported" -}; - -extern void atombios_output_mode_set(xf86OutputPtr output, - DisplayModePtr mode, - DisplayModePtr adjusted_mode); -extern void atombios_output_dpms(xf86OutputPtr output, int mode); -extern RADEONMonitorType atombios_dac_detect(xf86OutputPtr output); -extern AtomBiosResult -atombios_lock_crtc(atomBiosHandlePtr atomBIOS, int crtc, int lock); -static void -radeon_bios_output_dpms(xf86OutputPtr output, int mode); -static void -radeon_bios_output_crtc(xf86OutputPtr output); -static void -radeon_bios_output_lock(xf86OutputPtr output, Bool lock); -extern void -atombios_pick_dig_encoder(xf86OutputPtr output); - -void RADEONPrintPortMap(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); - RADEONOutputPrivatePtr radeon_output; - xf86OutputPtr output; - int o; - - for (o = 0; o < xf86_config->num_output; o++) { - output = xf86_config->output[o]; - radeon_output = output->driver_private; - - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Port%d:\n", o); - ErrorF(" XRANDR name: %s\n", output->name); - ErrorF(" Connector: %s\n", ConnectorTypeName[radeon_output->ConnectorType]); - if (radeon_output->devices & ATOM_DEVICE_CRT1_SUPPORT) - ErrorF(" CRT1: %s\n", encoder_name[info->encoders[ATOM_DEVICE_CRT1_INDEX]->encoder_id]); - if (radeon_output->devices & ATOM_DEVICE_CRT2_SUPPORT) - ErrorF(" CRT2: %s\n", encoder_name[info->encoders[ATOM_DEVICE_CRT2_INDEX]->encoder_id]); - if (radeon_output->devices & ATOM_DEVICE_LCD1_SUPPORT) - ErrorF(" LCD1: %s\n", encoder_name[info->encoders[ATOM_DEVICE_LCD1_INDEX]->encoder_id]); - if (radeon_output->devices & ATOM_DEVICE_DFP1_SUPPORT) - ErrorF(" DFP1: %s\n", encoder_name[info->encoders[ATOM_DEVICE_DFP1_INDEX]->encoder_id]); - if (radeon_output->devices & ATOM_DEVICE_DFP2_SUPPORT) - ErrorF(" DFP2: %s\n", encoder_name[info->encoders[ATOM_DEVICE_DFP2_INDEX]->encoder_id]); - if (radeon_output->devices & ATOM_DEVICE_DFP3_SUPPORT) - ErrorF(" DFP3: %s\n", encoder_name[info->encoders[ATOM_DEVICE_DFP3_INDEX]->encoder_id]); - if (radeon_output->devices & ATOM_DEVICE_DFP4_SUPPORT) - ErrorF(" DFP4: %s\n", encoder_name[info->encoders[ATOM_DEVICE_DFP4_INDEX]->encoder_id]); - if (radeon_output->devices & ATOM_DEVICE_DFP5_SUPPORT) - ErrorF(" DFP5: %s\n", encoder_name[info->encoders[ATOM_DEVICE_DFP5_INDEX]->encoder_id]); - if (radeon_output->devices & ATOM_DEVICE_TV1_SUPPORT) - ErrorF(" TV1: %s\n", encoder_name[info->encoders[ATOM_DEVICE_TV1_INDEX]->encoder_id]); - if (radeon_output->devices & ATOM_DEVICE_CV_SUPPORT) - ErrorF(" CV: %s\n", encoder_name[info->encoders[ATOM_DEVICE_CV_INDEX]->encoder_id]); - ErrorF(" DDC reg: 0x%x\n",(unsigned int)radeon_output->ddc_i2c.mask_clk_reg); - } - -} - -static void -radeon_set_active_device(xf86OutputPtr output) -{ - RADEONOutputPrivatePtr radeon_output = output->driver_private; - - radeon_output->active_device = 0; - - switch (radeon_output->MonType) { - case MT_DP: - case MT_DFP: - if (radeon_output->devices & ATOM_DEVICE_DFP1_SUPPORT) - radeon_output->active_device = ATOM_DEVICE_DFP1_SUPPORT; - else if (radeon_output->devices & ATOM_DEVICE_DFP2_SUPPORT) - radeon_output->active_device = ATOM_DEVICE_DFP2_SUPPORT; - else if (radeon_output->devices & ATOM_DEVICE_DFP3_SUPPORT) - radeon_output->active_device = ATOM_DEVICE_DFP3_SUPPORT; - else if (radeon_output->devices & ATOM_DEVICE_DFP4_SUPPORT) - radeon_output->active_device = ATOM_DEVICE_DFP4_SUPPORT; - else if (radeon_output->devices & ATOM_DEVICE_DFP5_SUPPORT) - radeon_output->active_device = ATOM_DEVICE_DFP5_SUPPORT; - else if (radeon_output->devices & ATOM_DEVICE_LCD1_SUPPORT) - radeon_output->active_device = ATOM_DEVICE_LCD1_SUPPORT; - else if (radeon_output->devices & ATOM_DEVICE_LCD2_SUPPORT) - radeon_output->active_device = ATOM_DEVICE_LCD2_SUPPORT; - break; - case MT_CRT: - if (radeon_output->devices & ATOM_DEVICE_CRT1_SUPPORT) - radeon_output->active_device = ATOM_DEVICE_CRT1_SUPPORT; - else if (radeon_output->devices & ATOM_DEVICE_CRT2_SUPPORT) - radeon_output->active_device = ATOM_DEVICE_CRT2_SUPPORT; - break; - case MT_LCD: - if (radeon_output->devices & ATOM_DEVICE_LCD1_SUPPORT) - radeon_output->active_device = ATOM_DEVICE_LCD1_SUPPORT; - else if (radeon_output->devices & ATOM_DEVICE_LCD2_SUPPORT) - radeon_output->active_device = ATOM_DEVICE_LCD2_SUPPORT; - break; - case MT_STV: - case MT_CTV: - if (radeon_output->devices & ATOM_DEVICE_TV1_SUPPORT) - radeon_output->active_device = ATOM_DEVICE_TV1_SUPPORT; - else if (radeon_output->devices & ATOM_DEVICE_TV2_SUPPORT) - radeon_output->active_device = ATOM_DEVICE_TV2_SUPPORT; - break; - case MT_CV: - if (radeon_output->devices & ATOM_DEVICE_CV_SUPPORT) - radeon_output->active_device = ATOM_DEVICE_CV_SUPPORT; - break; - default: - ErrorF("Unhandled monitor type %d\n", radeon_output->MonType); - radeon_output->active_device = 0; - } -} - -static Bool -monitor_is_digital(xf86MonPtr MonInfo) -{ - return (MonInfo->rawData[0x14] & 0x80) != 0; -} - -static void -RADEONGetHardCodedEDIDFromFile(xf86OutputPtr output) -{ - ScrnInfoPtr pScrn = output->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONOutputPrivatePtr radeon_output = output->driver_private; - char *EDIDlist = (char *)xf86GetOptValString(info->Options, OPTION_CUSTOM_EDID); - - radeon_output->custom_edid = FALSE; - radeon_output->custom_mon = NULL; - - if (EDIDlist != NULL) { - unsigned char* edid = xnfcalloc(128, 1); - char *name = output->name; - char *outputEDID = strstr(EDIDlist, name); - - if (outputEDID != NULL) { - char *end; - char *colon; - char *command = NULL; - int fd; - - outputEDID += strlen(name) + 1; - end = strstr(outputEDID, ";"); - if (end != NULL) - *end = 0; - - colon = strstr(outputEDID, ":"); - if (colon != NULL) { - *colon = 0; - command = colon + 1; - } - - fd = open (outputEDID, O_RDONLY); - if (fd >= 0) { - read(fd, edid, 128); - close(fd); - if (edid[1] == 0xff) { - radeon_output->custom_mon = xf86InterpretEDID(output->scrn->scrnIndex, edid); - radeon_output->custom_edid = TRUE; - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Successfully read Custom EDID data for output %s from %s.\n", - name, outputEDID); - if (command != NULL) { - if (!strcmp(command, "digital")) { - radeon_output->custom_mon->rawData[0x14] |= 0x80; - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Forcing digital output for output %s.\n", name); - } else if (!strcmp(command, "analog")) { - radeon_output->custom_mon->rawData[0x14] &= ~0x80; - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Forcing analog output for output %s.\n", name); - } else { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "Unknown custom EDID command: '%s'.\n", - command); - } - } - } else { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "Custom EDID data for %s read from %s was invalid.\n", - name, outputEDID); - } - } else { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "Could not read custom EDID for output %s from file %s.\n", - name, outputEDID); - } - } else { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "Could not find EDID file name for output %s; using auto detection.\n", - name); - } - } -} - - -static RADEONMonitorType -radeon_ddc_connected(xf86OutputPtr output) -{ - ScrnInfoPtr pScrn = output->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONMonitorType MonType = MT_NONE; - xf86MonPtr MonInfo = NULL; - RADEONOutputPrivatePtr radeon_output = output->driver_private; - int ret; - - if (radeon_output->custom_edid) { - MonInfo = xnfcalloc(sizeof(xf86Monitor), 1); - *MonInfo = *radeon_output->custom_mon; - } else if ((radeon_output->ConnectorType == CONNECTOR_DISPLAY_PORT) || - (radeon_output->ConnectorType == CONNECTOR_EDP)) { - ret = RADEON_DP_GetSinkType(output); - if (ret == CONNECTOR_OBJECT_ID_DISPLAYPORT || - ret == CONNECTOR_OBJECT_ID_eDP) { - MonInfo = xf86OutputGetEDID(output, radeon_output->dp_pI2CBus); - } - if (MonInfo == NULL) { - if (radeon_output->pI2CBus) { - RADEONI2CDoLock(output, radeon_output->pI2CBus, TRUE); - MonInfo = xf86OutputGetEDID(output, radeon_output->pI2CBus); - RADEONI2CDoLock(output, radeon_output->pI2CBus, FALSE); - } - } - } else if (radeon_output->pI2CBus) { - if (info->get_hardcoded_edid_from_bios) - MonInfo = RADEONGetHardCodedEDIDFromBIOS(output); - if (MonInfo == NULL) { - RADEONI2CDoLock(output, radeon_output->pI2CBus, TRUE); - MonInfo = xf86OutputGetEDID(output, radeon_output->pI2CBus); - RADEONI2CDoLock(output, radeon_output->pI2CBus, FALSE); - } - } - if (MonInfo) { - switch (radeon_output->ConnectorType) { - case CONNECTOR_LVDS: - MonType = MT_LCD; - break; - case CONNECTOR_DVI_D: - case CONNECTOR_HDMI_TYPE_A: - if (radeon_output->shared_ddc) { - xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR (output->scrn); - int i; - - if (monitor_is_digital(MonInfo)) - MonType = MT_DFP; - else - MonType = MT_NONE; - - for (i = 0; i < config->num_output; i++) { - if (output != config->output[i]) { - RADEONOutputPrivatePtr other_radeon_output = - config->output[i]->driver_private; - if (radeon_output->devices & other_radeon_output->devices) { -#ifndef EDID_COMPLETE_RAWDATA - if (radeon_output->ConnectorType == CONNECTOR_HDMI_TYPE_A) { - MonType = MT_NONE; - break; - } -#else - if (xf86MonitorIsHDMI(MonInfo)) { - if (radeon_output->ConnectorType == CONNECTOR_DVI_D) { - MonType = MT_NONE; - break; - } - } else { - if (radeon_output->ConnectorType == CONNECTOR_HDMI_TYPE_A) { - MonType = MT_NONE; - break; - } - } -#endif - } - } - } - } else - MonType = MT_DFP; - break; - case CONNECTOR_DISPLAY_PORT: - case CONNECTOR_EDP: - /* - * XXX wrong. need to infer based on whether we got DDC from I2C - * or AUXCH. - */ - ret = RADEON_DP_GetSinkType(output); - - if ((ret == CONNECTOR_OBJECT_ID_DISPLAYPORT) || - (ret == CONNECTOR_OBJECT_ID_eDP)) { - MonType = MT_DP; - RADEON_DP_GetDPCD(output); - } else - MonType = MT_DFP; - break; - case CONNECTOR_HDMI_TYPE_B: - case CONNECTOR_DVI_I: - if (monitor_is_digital(MonInfo)) - MonType = MT_DFP; - else - MonType = MT_CRT; - break; - case CONNECTOR_VGA: - case CONNECTOR_DVI_A: - default: - if (radeon_output->shared_ddc) { - if (monitor_is_digital(MonInfo)) - MonType = MT_NONE; - else - MonType = MT_CRT; - } else - MonType = MT_CRT; - break; - } - - if (MonType != MT_NONE) { - if (!xf86ReturnOptValBool(info->Options, OPTION_IGNORE_EDID, FALSE)) - xf86OutputSetEDID(output, MonInfo); - } else - free(MonInfo); - } else - MonType = MT_NONE; - - return MonType; -} - -#ifndef __powerpc__ - -static RADEONMonitorType -RADEONDetectLidStatus(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONMonitorType MonType = MT_NONE; -#ifdef __linux__ - char lidline[50]; /* 50 should be sufficient for our purposes */ - FILE *f = fopen ("/proc/acpi/button/lid/LID/state", "r"); - - if (f != NULL) { - while (fgets(lidline, sizeof lidline, f)) { - if (!strncmp(lidline, "state:", strlen ("state:"))) { - if (strstr(lidline, "open")) { - fclose(f); - ErrorF("proc lid open\n"); - return MT_LCD; - } - else if (strstr(lidline, "closed")) { - fclose(f); - ErrorF("proc lid closed\n"); - return MT_NONE; - } - } - } - fclose(f); - } -#endif - - if (!info->IsAtomBios) { - unsigned char *RADEONMMIO = info->MMIO; - - /* see if the lid is closed -- only works at boot */ - if (INREG(RADEON_BIOS_6_SCRATCH) & 0x10) - MonType = MT_NONE; - else - MonType = MT_LCD; - } else - MonType = MT_LCD; - - return MonType; -} - -#endif /* __powerpc__ */ - -static void -radeon_dpms(xf86OutputPtr output, int mode) -{ - RADEONInfoPtr info = RADEONPTR(output->scrn); - RADEONOutputPrivatePtr radeon_output = output->driver_private; - - if ((mode == DPMSModeOn) && radeon_output->enabled) - return; - - if ((mode != DPMSModeOn) && radeon_output->shared_ddc) { - xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR (output->scrn); - int i; - - for (i = 0; i < config->num_output; i++) { - if (output != config->output[i]) { - RADEONOutputPrivatePtr other_radeon_output = - config->output[i]->driver_private; - if (radeon_output->devices & other_radeon_output->devices) { - if (output->status == XF86OutputStatusDisconnected) - return; - } - } - } - } - - if (IS_AVIVO_VARIANT || info->r4xx_atom) { - atombios_output_dpms(output, mode); - } else { - legacy_output_dpms(output, mode); - } - radeon_bios_output_dpms(output, mode); - - if (mode == DPMSModeOn) - radeon_output->enabled = TRUE; - else - radeon_output->enabled = FALSE; - -} - -static void -radeon_save(xf86OutputPtr output) -{ - -} - -static void -radeon_restore(xf86OutputPtr restore) -{ - -} - -static int -radeon_mode_valid(xf86OutputPtr output, DisplayModePtr pMode) -{ - RADEONOutputPrivatePtr radeon_output = output->driver_private; - radeon_native_mode_ptr native_mode = &radeon_output->native_mode; - ScrnInfoPtr pScrn = output->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); - - /* - * RN50 has effective maximum mode bandwidth of about 300MiB/s. - * XXX should really do this for all chips by properly computing - * memory bandwidth and an overhead factor. - */ - if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2) { - if (xf86ModeBandwidth(pMode, pScrn->bitsPerPixel) > 300) - return MODE_BANDWIDTH; - } - - if (radeon_output->active_device & (ATOM_DEVICE_TV_SUPPORT)) { - if (IS_AVIVO_VARIANT) - return MODE_OK; - else { - /* FIXME: Update when more modes are added */ - if (pMode->HDisplay == 800 && pMode->VDisplay == 600) - return MODE_OK; - else - return MODE_CLOCK_RANGE; - } - } - - /* clocks over 135 MHz have heat issues with DVI on RV100 */ - if ((radeon_output->MonType == MT_DFP) && - (info->ChipFamily == CHIP_FAMILY_RV100) && - (pMode->Clock > 135000)) - return MODE_CLOCK_HIGH; - - /* single link DVI check */ - if (pMode->Clock > 165000 && radeon_output->MonType == MT_DFP) { - /* DP->DVI converter */ - if (radeon_output->ConnectorType == CONNECTOR_DISPLAY_PORT) - return MODE_CLOCK_HIGH; - - if (radeon_output->ConnectorType == CONNECTOR_EDP) - return MODE_CLOCK_HIGH; - - /* XXX some HDMI can do better than 165MHz on a link */ - if (radeon_output->ConnectorType == CONNECTOR_HDMI_TYPE_A) - return MODE_CLOCK_HIGH; - - /* XXX some R300 and R400 can actually do this */ - if (!IS_AVIVO_VARIANT) - return MODE_CLOCK_HIGH; - - /* XXX and some AVIVO can't */ - } - - if (radeon_output->active_device & (ATOM_DEVICE_LCD_SUPPORT)) { - if (radeon_output->rmx_type == RMX_OFF) { - if (pMode->HDisplay != native_mode->PanelXRes || - pMode->VDisplay != native_mode->PanelYRes) - return MODE_PANEL; - } - if (pMode->HDisplay > native_mode->PanelXRes || - pMode->VDisplay > native_mode->PanelYRes) - return MODE_PANEL; - } - - return MODE_OK; -} - -static Bool -radeon_mode_fixup(xf86OutputPtr output, DisplayModePtr mode, - DisplayModePtr adjusted_mode) -{ - RADEONInfoPtr info = RADEONPTR(output->scrn); - RADEONOutputPrivatePtr radeon_output = output->driver_private; - radeon_native_mode_ptr native_mode = &radeon_output->native_mode; - xf86CrtcPtr crtc = output->crtc; - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - - radeon_output->Flags &= ~RADEON_USE_RMX; - radeon_crtc->scaler_enabled = FALSE; - - /* - * Refresh the Crtc values without INTERLACE_HALVE_V - * Should we use output->scrn->adjustFlags like xf86RandRModeConvert() does? - */ - xf86SetModeCrtc(adjusted_mode, 0); - - /* decide if we are using RMX */ - if ((radeon_output->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) - && radeon_output->rmx_type != RMX_OFF) { - - if (IS_AVIVO_VARIANT || radeon_crtc->crtc_id == 0) { - if (mode->HDisplay < native_mode->PanelXRes || - mode->VDisplay < native_mode->PanelYRes) { - radeon_output->Flags |= RADEON_USE_RMX; - radeon_crtc->scaler_enabled = TRUE; - if (IS_AVIVO_VARIANT) { - radeon_crtc->hsc = (float)mode->HDisplay / (float)native_mode->PanelXRes; - radeon_crtc->vsc = (float)mode->VDisplay / (float)native_mode->PanelYRes; - /* set to the panel's native mode */ - adjusted_mode->HDisplay = native_mode->PanelXRes; - adjusted_mode->VDisplay = native_mode->PanelYRes; - adjusted_mode->HTotal = native_mode->PanelXRes + native_mode->HBlank; - adjusted_mode->HSyncStart = native_mode->PanelXRes + native_mode->HOverPlus; - adjusted_mode->HSyncEnd = adjusted_mode->HSyncStart + native_mode->HSyncWidth; - adjusted_mode->VTotal = native_mode->PanelYRes + native_mode->VBlank; - adjusted_mode->VSyncStart = native_mode->PanelYRes + native_mode->VOverPlus; - adjusted_mode->VSyncEnd = adjusted_mode->VSyncStart + native_mode->VSyncWidth; - /* update crtc values */ - xf86SetModeCrtc(adjusted_mode, INTERLACE_HALVE_V); - /* adjust crtc values */ - adjusted_mode->CrtcHDisplay = native_mode->PanelXRes; - adjusted_mode->CrtcVDisplay = native_mode->PanelYRes; - adjusted_mode->CrtcHTotal = adjusted_mode->CrtcHDisplay + native_mode->HBlank; - adjusted_mode->CrtcHSyncStart = adjusted_mode->CrtcHDisplay + native_mode->HOverPlus; - adjusted_mode->CrtcHSyncEnd = adjusted_mode->CrtcHSyncStart + native_mode->HSyncWidth; - adjusted_mode->CrtcVTotal = adjusted_mode->CrtcVDisplay + native_mode->VBlank; - adjusted_mode->CrtcVSyncStart = adjusted_mode->CrtcVDisplay + native_mode->VOverPlus; - adjusted_mode->CrtcVSyncEnd = adjusted_mode->CrtcVSyncStart + native_mode->VSyncWidth; - } else { - /* set to the panel's native mode */ - adjusted_mode->HTotal = native_mode->PanelXRes + native_mode->HBlank; - adjusted_mode->HSyncStart = native_mode->PanelXRes + native_mode->HOverPlus; - adjusted_mode->HSyncEnd = adjusted_mode->HSyncStart + native_mode->HSyncWidth; - adjusted_mode->VTotal = native_mode->PanelYRes + native_mode->VBlank; - adjusted_mode->VSyncStart = native_mode->PanelYRes + native_mode->VOverPlus; - adjusted_mode->VSyncEnd = adjusted_mode->VSyncStart + native_mode->VSyncWidth; - adjusted_mode->Clock = native_mode->DotClock; - /* update crtc values */ - xf86SetModeCrtc(adjusted_mode, INTERLACE_HALVE_V); - /* adjust crtc values */ - adjusted_mode->CrtcHTotal = adjusted_mode->CrtcHDisplay + native_mode->HBlank; - adjusted_mode->CrtcHSyncStart = adjusted_mode->CrtcHDisplay + native_mode->HOverPlus; - adjusted_mode->CrtcHSyncEnd = adjusted_mode->CrtcHSyncStart + native_mode->HSyncWidth; - adjusted_mode->CrtcVTotal = adjusted_mode->CrtcVDisplay + native_mode->VBlank; - adjusted_mode->CrtcVSyncStart = adjusted_mode->CrtcVDisplay + native_mode->VOverPlus; - adjusted_mode->CrtcVSyncEnd = adjusted_mode->CrtcVSyncStart + native_mode->VSyncWidth; - } - adjusted_mode->Clock = native_mode->DotClock; - adjusted_mode->Flags = native_mode->Flags; - } - } - } - - /* FIXME: vsc/hsc */ - if (radeon_output->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) { - radeon_crtc->scaler_enabled = TRUE; - radeon_crtc->hsc = (float)mode->HDisplay / (float)640; - radeon_crtc->vsc = (float)mode->VDisplay / (float)480; - } - - if (IS_AVIVO_VARIANT) { - /* hw bug */ - if ((mode->Flags & V_INTERLACE) - && (adjusted_mode->CrtcVSyncStart < (adjusted_mode->CrtcVDisplay + 2))) - adjusted_mode->CrtcVSyncStart = adjusted_mode->CrtcVDisplay + 2; - } - - if (IS_AVIVO_VARIANT || info->r4xx_atom) { - if (radeon_output->MonType == MT_STV || radeon_output->MonType == MT_CTV) { - radeon_tvout_ptr tvout = &radeon_output->tvout; - ScrnInfoPtr pScrn = output->scrn; - - if (tvout->tvStd == TV_STD_NTSC || - tvout->tvStd == TV_STD_NTSC_J || - tvout->tvStd == TV_STD_PAL_M) - RADEONATOMGetTVTimings(pScrn, 0, adjusted_mode); - else - RADEONATOMGetTVTimings(pScrn, 1, adjusted_mode); - } - } - - if (((radeon_output->ConnectorType == CONNECTOR_DISPLAY_PORT) || - (radeon_output->ConnectorType == CONNECTOR_EDP)) && - (radeon_output->MonType == MT_DP)) { - radeon_dp_mode_fixup(output, mode, adjusted_mode); - } - return TRUE; -} - -static void -radeon_mode_prepare(xf86OutputPtr output) -{ - RADEONInfoPtr info = RADEONPTR(output->scrn); - xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR (output->scrn); - int o; - - for (o = 0; o < config->num_output; o++) { - xf86OutputPtr loop_output = config->output[o]; - if (loop_output == output) - continue; - else if (loop_output->crtc) { - xf86CrtcPtr other_crtc = loop_output->crtc; - RADEONCrtcPrivatePtr other_radeon_crtc = other_crtc->driver_private; - if (other_crtc->enabled) { - if (other_radeon_crtc->initialized) { - radeon_crtc_dpms(other_crtc, DPMSModeOff); - if (IS_AVIVO_VARIANT || info->r4xx_atom) - atombios_lock_crtc(info->atomBIOS, other_radeon_crtc->crtc_id, 1); - radeon_dpms(loop_output, DPMSModeOff); - } - } - } - } - - radeon_bios_output_lock(output, TRUE); - if (IS_AVIVO_VARIANT) - atombios_pick_dig_encoder(output); - radeon_dpms(output, DPMSModeOff); - radeon_crtc_dpms(output->crtc, DPMSModeOff); - - if (IS_AVIVO_VARIANT || info->r4xx_atom) - atombios_set_output_crtc_source(output); - -} - -static void -radeon_mode_set(xf86OutputPtr output, DisplayModePtr mode, - DisplayModePtr adjusted_mode) -{ - RADEONInfoPtr info = RADEONPTR(output->scrn); - - if (IS_AVIVO_VARIANT || info->r4xx_atom) - atombios_output_mode_set(output, mode, adjusted_mode); - else - legacy_output_mode_set(output, mode, adjusted_mode); - radeon_bios_output_crtc(output); - -} - -static void -radeon_mode_commit(xf86OutputPtr output) -{ - RADEONInfoPtr info = RADEONPTR(output->scrn); - xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR (output->scrn); - int o; - - for (o = 0; o < config->num_output; o++) { - xf86OutputPtr loop_output = config->output[o]; - if (loop_output == output) - continue; - else if (loop_output->crtc) { - xf86CrtcPtr other_crtc = loop_output->crtc; - RADEONCrtcPrivatePtr other_radeon_crtc = other_crtc->driver_private; - if (other_crtc->enabled) { - if (other_radeon_crtc->initialized) { - radeon_crtc_dpms(other_crtc, DPMSModeOn); - if (IS_AVIVO_VARIANT || info->r4xx_atom) - atombios_lock_crtc(info->atomBIOS, other_radeon_crtc->crtc_id, 0); - radeon_dpms(loop_output, DPMSModeOn); - } - } - } - } - - radeon_dpms(output, DPMSModeOn); - radeon_crtc_dpms(output->crtc, DPMSModeOn); - radeon_bios_output_lock(output, FALSE); -} - -static void -radeon_bios_output_lock(xf86OutputPtr output, Bool lock) -{ - ScrnInfoPtr pScrn = output->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - RADEONSavePtr save = info->ModeReg; - - if (info->IsAtomBios) { - if (lock) { - save->bios_6_scratch |= ATOM_S6_CRITICAL_STATE; - } else { - save->bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE; - } - } else { - if (lock) { - save->bios_6_scratch |= RADEON_DRIVER_CRITICAL; - } else { - save->bios_6_scratch &= ~RADEON_DRIVER_CRITICAL; - } - } - if (info->ChipFamily >= CHIP_FAMILY_R600) - OUTREG(R600_BIOS_6_SCRATCH, save->bios_6_scratch); - else - OUTREG(RADEON_BIOS_6_SCRATCH, save->bios_6_scratch); -} - -static void -radeon_bios_output_dpms(xf86OutputPtr output, int mode) -{ - ScrnInfoPtr pScrn = output->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONOutputPrivatePtr radeon_output = output->driver_private; - unsigned char *RADEONMMIO = info->MMIO; - RADEONSavePtr save = info->ModeReg; - - if (info->IsAtomBios) { - if (radeon_output->active_device & ATOM_DEVICE_TV1_SUPPORT) { - if (mode == DPMSModeOn) - save->bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE; - else - save->bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE; - } else if (radeon_output->active_device & ATOM_DEVICE_CV_SUPPORT) { - if (mode == DPMSModeOn) - save->bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE; - else - save->bios_2_scratch |= ATOM_S2_CV_DPMS_STATE; - } else if (radeon_output->active_device & ATOM_DEVICE_CRT1_SUPPORT) { - if (mode == DPMSModeOn) - save->bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE; - else - save->bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE; - } else if (radeon_output->active_device & ATOM_DEVICE_CRT2_SUPPORT) { - if (mode == DPMSModeOn) - save->bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE; - else - save->bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE; - } else if (radeon_output->active_device & ATOM_DEVICE_LCD1_SUPPORT) { - if (mode == DPMSModeOn) - save->bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE; - else - save->bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE; - } else if (radeon_output->active_device & ATOM_DEVICE_DFP1_SUPPORT) { - if (mode == DPMSModeOn) - save->bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE; - else - save->bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE; - } else if (radeon_output->active_device & ATOM_DEVICE_DFP2_SUPPORT) { - if (mode == DPMSModeOn) - save->bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE; - else - save->bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE; - } else if (radeon_output->active_device & ATOM_DEVICE_DFP3_SUPPORT) { - if (mode == DPMSModeOn) - save->bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE; - else - save->bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE; - } else if (radeon_output->active_device & ATOM_DEVICE_DFP4_SUPPORT) { - if (mode == DPMSModeOn) - save->bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE; - else - save->bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE; - } else if (radeon_output->active_device & ATOM_DEVICE_DFP5_SUPPORT) { - if (mode == DPMSModeOn) - save->bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE; - else - save->bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE; - } - if (info->ChipFamily >= CHIP_FAMILY_R600) - OUTREG(R600_BIOS_2_SCRATCH, save->bios_2_scratch); - else - OUTREG(RADEON_BIOS_2_SCRATCH, save->bios_2_scratch); - } else { - if (mode == DPMSModeOn) { - save->bios_6_scratch &= ~(RADEON_DPMS_MASK | RADEON_SCREEN_BLANKING); - save->bios_6_scratch |= RADEON_DPMS_ON; - } else { - save->bios_6_scratch &= ~RADEON_DPMS_MASK; - save->bios_6_scratch |= (RADEON_DPMS_OFF | RADEON_SCREEN_BLANKING); - } - if (radeon_output->active_device & ATOM_DEVICE_TV1_SUPPORT) { - if (mode == DPMSModeOn) - save->bios_6_scratch |= RADEON_TV_DPMS_ON; - else - save->bios_6_scratch &= ~RADEON_TV_DPMS_ON; - } else if (radeon_output->active_device & ATOM_DEVICE_CRT1_SUPPORT) { - if (mode == DPMSModeOn) - save->bios_6_scratch |= RADEON_CRT_DPMS_ON; - else - save->bios_6_scratch &= ~RADEON_CRT_DPMS_ON; - } else if (radeon_output->active_device & ATOM_DEVICE_CRT2_SUPPORT) { - if (mode == DPMSModeOn) - save->bios_6_scratch |= RADEON_CRT_DPMS_ON; - else - save->bios_6_scratch &= ~RADEON_CRT_DPMS_ON; - } else if (radeon_output->active_device & ATOM_DEVICE_LCD1_SUPPORT) { - if (mode == DPMSModeOn) - save->bios_6_scratch |= RADEON_LCD_DPMS_ON; - else - save->bios_6_scratch &= ~RADEON_LCD_DPMS_ON; - } else if (radeon_output->active_device & ATOM_DEVICE_DFP1_SUPPORT) { - if (mode == DPMSModeOn) - save->bios_6_scratch |= RADEON_DFP_DPMS_ON; - else - save->bios_6_scratch &= ~RADEON_DFP_DPMS_ON; - } else if (radeon_output->active_device & ATOM_DEVICE_DFP2_SUPPORT) { - if (mode == DPMSModeOn) - save->bios_6_scratch |= RADEON_DFP_DPMS_ON; - else - save->bios_6_scratch &= ~RADEON_DFP_DPMS_ON; - } - OUTREG(RADEON_BIOS_6_SCRATCH, save->bios_6_scratch); - } -} - -static void -radeon_bios_output_crtc(xf86OutputPtr output) -{ - ScrnInfoPtr pScrn = output->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONOutputPrivatePtr radeon_output = output->driver_private; - unsigned char *RADEONMMIO = info->MMIO; - RADEONSavePtr save = info->ModeReg; - xf86CrtcPtr crtc = output->crtc; - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - - /* no need to update crtc routing scratch regs on DCE4 */ - if (IS_DCE4_VARIANT) - return; - - if (info->IsAtomBios) { - if (radeon_output->active_device & ATOM_DEVICE_TV1_SUPPORT) { - save->bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE; - save->bios_3_scratch |= (radeon_crtc->crtc_id << 18); - } else if (radeon_output->active_device & ATOM_DEVICE_CV_SUPPORT) { - save->bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE; - save->bios_3_scratch |= (radeon_crtc->crtc_id << 24); - } else if (radeon_output->active_device & ATOM_DEVICE_CRT1_SUPPORT) { - save->bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE; - save->bios_3_scratch |= (radeon_crtc->crtc_id << 16); - } else if (radeon_output->active_device & ATOM_DEVICE_CRT2_SUPPORT) { - save->bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE; - save->bios_3_scratch |= (radeon_crtc->crtc_id << 20); - } else if (radeon_output->active_device & ATOM_DEVICE_LCD1_SUPPORT) { - save->bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE; - save->bios_3_scratch |= (radeon_crtc->crtc_id << 17); - } else if (radeon_output->active_device & ATOM_DEVICE_DFP1_SUPPORT) { - save->bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE; - save->bios_3_scratch |= (radeon_crtc->crtc_id << 19); - } else if (radeon_output->active_device & ATOM_DEVICE_DFP2_SUPPORT) { - save->bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE; - save->bios_3_scratch |= (radeon_crtc->crtc_id << 23); - } else if (radeon_output->active_device & ATOM_DEVICE_DFP3_SUPPORT) { - save->bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE; - save->bios_3_scratch |= (radeon_crtc->crtc_id << 25); - } - if (info->ChipFamily >= CHIP_FAMILY_R600) - OUTREG(R600_BIOS_3_SCRATCH, save->bios_3_scratch); - else - OUTREG(RADEON_BIOS_3_SCRATCH, save->bios_3_scratch); - } else { - if (radeon_output->active_device & ATOM_DEVICE_TV1_SUPPORT) { - save->bios_5_scratch &= ~RADEON_TV1_CRTC_MASK; - save->bios_5_scratch |= (radeon_crtc->crtc_id << RADEON_TV1_CRTC_SHIFT); - } else if (radeon_output->active_device & ATOM_DEVICE_CRT1_SUPPORT) { - save->bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK; - save->bios_5_scratch |= (radeon_crtc->crtc_id << RADEON_CRT1_CRTC_SHIFT); - } else if (radeon_output->active_device & ATOM_DEVICE_CRT2_SUPPORT) { - save->bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK; - save->bios_5_scratch |= (radeon_crtc->crtc_id << RADEON_CRT2_CRTC_SHIFT); - } else if (radeon_output->active_device & ATOM_DEVICE_LCD1_SUPPORT) { - save->bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK; - save->bios_5_scratch |= (radeon_crtc->crtc_id << RADEON_LCD1_CRTC_SHIFT); - } else if (radeon_output->active_device & ATOM_DEVICE_DFP1_SUPPORT) { - save->bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK; - save->bios_5_scratch |= (radeon_crtc->crtc_id << RADEON_DFP1_CRTC_SHIFT); - } else if (radeon_output->active_device & ATOM_DEVICE_DFP2_SUPPORT) { - save->bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK; - save->bios_5_scratch |= (radeon_crtc->crtc_id << RADEON_DFP2_CRTC_SHIFT); - } - OUTREG(RADEON_BIOS_5_SCRATCH, save->bios_5_scratch); - } -} - -static void -radeon_bios_output_connected(xf86OutputPtr output, Bool connected) -{ - ScrnInfoPtr pScrn = output->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONOutputPrivatePtr radeon_output = output->driver_private; - unsigned char *RADEONMMIO = info->MMIO; - RADEONSavePtr save = info->ModeReg; - - if (info->IsAtomBios) { - switch (radeon_output->active_device) { - case ATOM_DEVICE_TV1_SUPPORT: - if (connected) - save->bios_3_scratch |= ATOM_S3_TV1_ACTIVE; - else { - save->bios_0_scratch &= ~ATOM_S0_TV1_MASK; - save->bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE; - } - break; - case ATOM_DEVICE_CV_SUPPORT: - if (connected) - save->bios_3_scratch |= ATOM_S3_CV_ACTIVE; - else { - save->bios_0_scratch &= ~ATOM_S0_CV_MASK; - save->bios_3_scratch &= ~ATOM_S3_CV_ACTIVE; - } - break; - case ATOM_DEVICE_LCD1_SUPPORT: - if (connected) { - save->bios_0_scratch |= ATOM_S0_LCD1; - save->bios_3_scratch |= ATOM_S3_LCD1_ACTIVE; - } else { - save->bios_0_scratch &= ~ATOM_S0_LCD1; - save->bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE; - } - break; - case ATOM_DEVICE_CRT1_SUPPORT: - if (connected) { - save->bios_0_scratch |= ATOM_S0_CRT1_COLOR; - save->bios_3_scratch |= ATOM_S3_CRT1_ACTIVE; - } else { - save->bios_0_scratch &= ~ATOM_S0_CRT1_MASK; - save->bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE; - } - break; - case ATOM_DEVICE_CRT2_SUPPORT: - if (connected) { - save->bios_0_scratch |= ATOM_S0_CRT2_COLOR; - save->bios_3_scratch |= ATOM_S3_CRT2_ACTIVE; - } else { - save->bios_0_scratch &= ~ATOM_S0_CRT2_MASK; - save->bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE; - } - break; - case ATOM_DEVICE_DFP1_SUPPORT: - if (connected) { - save->bios_0_scratch |= ATOM_S0_DFP1; - save->bios_3_scratch |= ATOM_S3_DFP1_ACTIVE; - } else { - save->bios_0_scratch &= ~ATOM_S0_DFP1; - save->bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE; - } - break; - case ATOM_DEVICE_DFP2_SUPPORT: - if (connected) { - save->bios_0_scratch |= ATOM_S0_DFP2; - save->bios_3_scratch |= ATOM_S3_DFP2_ACTIVE; - } else { - save->bios_0_scratch &= ~ATOM_S0_DFP2; - save->bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE; - } - break; - case ATOM_DEVICE_DFP3_SUPPORT: - if (connected) { - save->bios_0_scratch |= ATOM_S0_DFP3; - save->bios_3_scratch |= ATOM_S3_DFP3_ACTIVE; - } else { - save->bios_0_scratch &= ~ATOM_S0_DFP3; - save->bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE; - } - break; - case ATOM_DEVICE_DFP4_SUPPORT: - if (connected) { - save->bios_0_scratch |= ATOM_S0_DFP4; - save->bios_3_scratch |= ATOM_S3_DFP4_ACTIVE; - } else { - save->bios_0_scratch &= ~ATOM_S0_DFP4; - save->bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE; - } - break; - case ATOM_DEVICE_DFP5_SUPPORT: - if (connected) { - save->bios_0_scratch |= ATOM_S0_DFP5; - save->bios_3_scratch |= ATOM_S3_DFP5_ACTIVE; - } else { - save->bios_0_scratch &= ~ATOM_S0_DFP5; - save->bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE; - } - break; - } - if (info->ChipFamily >= CHIP_FAMILY_R600) { - OUTREG(R600_BIOS_0_SCRATCH, save->bios_0_scratch); - OUTREG(R600_BIOS_3_SCRATCH, save->bios_3_scratch); - } else { - OUTREG(RADEON_BIOS_0_SCRATCH, save->bios_0_scratch); - OUTREG(RADEON_BIOS_3_SCRATCH, save->bios_3_scratch); - } - } else { - switch (radeon_output->active_device) { - case ATOM_DEVICE_TV1_SUPPORT: - if (connected) { - if (radeon_output->MonType == MT_STV) - save->bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO; - else if (radeon_output->MonType == MT_CTV) - save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; - save->bios_5_scratch |= RADEON_TV1_ON; - } else { - save->bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK; - save->bios_5_scratch &= ~RADEON_TV1_ON; - } - break; - case ATOM_DEVICE_LCD1_SUPPORT: - if (connected) { - save->bios_4_scratch |= RADEON_LCD1_ATTACHED; - save->bios_5_scratch |= RADEON_LCD1_ON; - } else { - save->bios_4_scratch &= ~RADEON_LCD1_ATTACHED; - save->bios_5_scratch &= ~RADEON_LCD1_ON; - } - break; - case ATOM_DEVICE_CRT1_SUPPORT: - if (connected) { - save->bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR; - save->bios_5_scratch |= RADEON_CRT1_ON; - } else { - save->bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK; - save->bios_5_scratch &= ~RADEON_CRT1_ON; - } - break; - case ATOM_DEVICE_CRT2_SUPPORT: - if (connected) { - save->bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR; - save->bios_5_scratch |= RADEON_CRT2_ON; - } else { - save->bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK; - save->bios_5_scratch &= ~RADEON_CRT2_ON; - } - break; - case ATOM_DEVICE_DFP1_SUPPORT: - if (connected) { - save->bios_4_scratch |= RADEON_DFP1_ATTACHED; - save->bios_5_scratch |= RADEON_DFP1_ON; - } else { - save->bios_4_scratch &= ~RADEON_DFP1_ATTACHED; - save->bios_5_scratch &= ~RADEON_DFP1_ON; - } - break; - case ATOM_DEVICE_DFP2_SUPPORT: - if (connected) { - save->bios_4_scratch |= RADEON_DFP2_ATTACHED; - save->bios_5_scratch |= RADEON_DFP2_ON; - } else { - save->bios_4_scratch &= ~RADEON_DFP2_ATTACHED; - save->bios_5_scratch &= ~RADEON_DFP2_ON; - } - break; - } - OUTREG(RADEON_BIOS_4_SCRATCH, save->bios_4_scratch); - OUTREG(RADEON_BIOS_5_SCRATCH, save->bios_5_scratch); - } - -} - -static xf86OutputStatus -radeon_detect(xf86OutputPtr output) -{ - ScrnInfoPtr pScrn = output->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONOutputPrivatePtr radeon_output = output->driver_private; - Bool connected = TRUE; - - radeon_output->MonType = MT_UNKNOWN; - radeon_bios_output_connected(output, FALSE); - radeon_output->MonType = radeon_ddc_connected(output); - if (!radeon_output->MonType) { - if (radeon_output->devices & (ATOM_DEVICE_LCD_SUPPORT)) { - if (xf86ReturnOptValBool(info->Options, OPTION_IGNORE_LID_STATUS, TRUE)) - radeon_output->MonType = MT_LCD; - else -#if defined(__powerpc__) - radeon_output->MonType = MT_LCD; -#else - radeon_output->MonType = RADEONDetectLidStatus(pScrn); -#endif - } else { - if (info->IsAtomBios) - radeon_output->MonType = atombios_dac_detect(output); - else - radeon_output->MonType = legacy_dac_detect(output); - } - } - - // if size is zero panel probably broken or not connected - if (radeon_output->devices & (ATOM_DEVICE_LCD_SUPPORT)) { - radeon_encoder_ptr radeon_encoder = info->encoders[ATOM_DEVICE_LCD1_INDEX]; - if (radeon_encoder) { - radeon_lvds_ptr lvds = (radeon_lvds_ptr)radeon_encoder->dev_priv; - if (lvds) { - if ((lvds->native_mode.PanelXRes == 0) || (lvds->native_mode.PanelYRes == 0)) - radeon_output->MonType = MT_NONE; - } - } - } - - - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Output: %s, Detected Monitor Type: %d\n", output->name, radeon_output->MonType); - if (output->MonInfo) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "EDID data from the display on output: %s ----------------------\n", - output->name); - xf86PrintEDID( output->MonInfo ); - } - - /* nothing connected, light up some defaults so the server comes up */ - if (radeon_output->MonType == MT_NONE && - info->first_load_no_devices) { - if (info->IsMobility) { - if (radeon_output->devices & (ATOM_DEVICE_LCD_SUPPORT)) { - radeon_output->MonType = MT_LCD; - info->first_load_no_devices = FALSE; - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Using LCD default\n"); - } - } else { - if (radeon_output->devices & (ATOM_DEVICE_CRT_SUPPORT)) { - radeon_output->MonType = MT_CRT; - info->first_load_no_devices = FALSE; - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Using CRT default\n"); - } else if (radeon_output->devices & (ATOM_DEVICE_DFP_SUPPORT)) { - radeon_output->MonType = MT_DFP; - info->first_load_no_devices = FALSE; - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Using DFP default\n"); - } - } - } - - radeon_bios_output_connected(output, TRUE); - - /* set montype so users can force outputs on even if detection fails */ - if (radeon_output->MonType == MT_NONE) { - connected = FALSE; - switch (radeon_output->ConnectorType) { - case CONNECTOR_LVDS: - radeon_output->MonType = MT_LCD; - break; - case CONNECTOR_DVI_D: - case CONNECTOR_HDMI_TYPE_A: - case CONNECTOR_HDMI_TYPE_B: - radeon_output->MonType = MT_DFP; - break; - case CONNECTOR_VGA: - case CONNECTOR_DVI_A: - default: - radeon_output->MonType = MT_CRT; - break; - case CONNECTOR_DVI_I: - if (radeon_output->DVIType == DVI_ANALOG) - radeon_output->MonType = MT_CRT; - else if (radeon_output->DVIType == DVI_DIGITAL) - radeon_output->MonType = MT_DFP; - break; - case CONNECTOR_STV: - radeon_output->MonType = MT_STV; - break; - case CONNECTOR_CTV: - radeon_output->MonType = MT_CTV; - break; - case CONNECTOR_DIN: - radeon_output->MonType = MT_CV; - break; - case CONNECTOR_DISPLAY_PORT: - case CONNECTOR_EDP: - radeon_output->MonType = MT_DP; - break; - } - } - - radeon_set_active_device(output); - - if (radeon_output->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) - output->subpixel_order = SubPixelHorizontalRGB; - else - output->subpixel_order = SubPixelNone; - - if (connected) - return XF86OutputStatusConnected; - else - return XF86OutputStatusDisconnected; -} - -static DisplayModePtr -radeon_get_modes(xf86OutputPtr output) -{ - DisplayModePtr modes; - modes = RADEONProbeOutputModes(output); - return modes; -} - -static void -radeon_destroy (xf86OutputPtr output) -{ - if (output->driver_private) - free(output->driver_private); -} - -static void -radeon_set_backlight_level(xf86OutputPtr output, int level) -{ -#if 0 - ScrnInfoPtr pScrn = output->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char * RADEONMMIO = info->MMIO; - uint32_t lvds_gen_cntl; - - lvds_gen_cntl = INREG(RADEON_LVDS_GEN_CNTL); - lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN; - lvds_gen_cntl &= ~RADEON_LVDS_BL_MOD_LEVEL_MASK; - lvds_gen_cntl |= (level << RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & RADEON_LVDS_BL_MOD_LEVEL_MASK; - //usleep (radeon_output->PanelPwrDly * 1000); - OUTREG(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); - lvds_gen_cntl &= ~RADEON_LVDS_BL_MOD_EN; - //usleep (radeon_output->PanelPwrDly * 1000); - OUTREG(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); -#endif -} - -static Atom backlight_atom; -static Atom tmds_pll_atom; -static Atom rmx_atom; -static Atom monitor_type_atom; -static Atom load_detection_atom; -static Atom coherent_mode_atom; -static Atom tv_hsize_atom; -static Atom tv_hpos_atom; -static Atom tv_vpos_atom; -static Atom tv_std_atom; -#define RADEON_MAX_BACKLIGHT_LEVEL 255 - -static void -radeon_create_resources(xf86OutputPtr output) -{ - ScrnInfoPtr pScrn = output->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONOutputPrivatePtr radeon_output = output->driver_private; - INT32 range[2]; - int data, err; - const char *s; - -#if 0 - /* backlight control */ - if (radeon_output->type == OUTPUT_LVDS) { - backlight_atom = MAKE_ATOM("backlight"); - - range[0] = 0; - range[1] = RADEON_MAX_BACKLIGHT_LEVEL; - err = RRConfigureOutputProperty(output->randr_output, backlight_atom, - FALSE, TRUE, FALSE, 2, range); - if (err != 0) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "RRConfigureOutputProperty error, %d\n", err); - } - /* Set the current value of the backlight property */ - //data = (info->SavedReg->lvds_gen_cntl & RADEON_LVDS_BL_MOD_LEVEL_MASK) >> RADEON_LVDS_BL_MOD_LEVEL_SHIFT; - data = RADEON_MAX_BACKLIGHT_LEVEL; - err = RRChangeOutputProperty(output->randr_output, backlight_atom, - XA_INTEGER, 32, PropModeReplace, 1, &data, - FALSE, TRUE); - if (err != 0) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "RRChangeOutputProperty error, %d\n", err); - } - } -#endif - - if (radeon_output->devices & (ATOM_DEVICE_CRT_SUPPORT | ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) { - load_detection_atom = MAKE_ATOM("load_detection"); - - range[0] = 0; /* off */ - range[1] = 1; /* on */ - err = RRConfigureOutputProperty(output->randr_output, load_detection_atom, - FALSE, TRUE, FALSE, 2, range); - if (err != 0) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "RRConfigureOutputProperty error, %d\n", err); - } - - if (radeon_output->load_detection) - data = 1; - else - data = 0; - - err = RRChangeOutputProperty(output->randr_output, load_detection_atom, - XA_INTEGER, 32, PropModeReplace, 1, &data, - FALSE, TRUE); - if (err != 0) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "RRChangeOutputProperty error, %d\n", err); - } - } - - if (IS_AVIVO_VARIANT && (radeon_output->devices & (ATOM_DEVICE_DFP_SUPPORT))) { - coherent_mode_atom = MAKE_ATOM("coherent_mode"); - - range[0] = 0; /* off */ - range[1] = 1; /* on */ - err = RRConfigureOutputProperty(output->randr_output, coherent_mode_atom, - FALSE, TRUE, FALSE, 2, range); - if (err != 0) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "RRConfigureOutputProperty error, %d\n", err); - } - - data = 1; /* coherent mode on by default */ - - err = RRChangeOutputProperty(output->randr_output, coherent_mode_atom, - XA_INTEGER, 32, PropModeReplace, 1, &data, - FALSE, TRUE); - if (err != 0) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "RRChangeOutputProperty error, %d\n", err); - } - } - - if ((!IS_AVIVO_VARIANT) && (radeon_output->devices & (ATOM_DEVICE_DFP1_SUPPORT))) { - tmds_pll_atom = MAKE_ATOM("tmds_pll"); - - err = RRConfigureOutputProperty(output->randr_output, tmds_pll_atom, - FALSE, FALSE, FALSE, 0, NULL); - if (err != 0) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "RRConfigureOutputProperty error, %d\n", err); - } - /* Set the current value of the property */ -#if defined(__powerpc__) - s = "driver"; -#else - s = "bios"; -#endif - if (xf86ReturnOptValBool(info->Options, OPTION_DEFAULT_TMDS_PLL, FALSE)) { - s = "driver"; - } - - err = RRChangeOutputProperty(output->randr_output, tmds_pll_atom, - XA_STRING, 8, PropModeReplace, strlen(s), (pointer)s, - FALSE, FALSE); - if (err != 0) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "RRChangeOutputProperty error, %d\n", err); - } - - } - - /* RMX control - fullscreen, centered, keep ratio, off */ - /* actually more of a crtc property as only crtc1 has rmx */ - if (radeon_output->devices & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) { - rmx_atom = MAKE_ATOM("scaler"); - - err = RRConfigureOutputProperty(output->randr_output, rmx_atom, - FALSE, FALSE, FALSE, 0, NULL); - if (err != 0) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "RRConfigureOutputProperty error, %d\n", err); - } - /* Set the current value of the property */ - switch (radeon_output->rmx_type) { - case RMX_OFF: - default: - s = "off"; - break; - case RMX_FULL: - s = "full"; - break; - case RMX_CENTER: - s = "center"; - break; - case RMX_ASPECT: - s = "aspect"; - break; - } - err = RRChangeOutputProperty(output->randr_output, rmx_atom, - XA_STRING, 8, PropModeReplace, strlen(s), (pointer)s, - FALSE, FALSE); - if (err != 0) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "RRChangeOutputProperty error, %d\n", err); - } - } - - /* force auto/analog/digital for DVI-I ports */ - if ((radeon_output->devices & (ATOM_DEVICE_CRT_SUPPORT)) && - (radeon_output->devices & (ATOM_DEVICE_DFP_SUPPORT))){ - monitor_type_atom = MAKE_ATOM("dvi_monitor_type"); - - err = RRConfigureOutputProperty(output->randr_output, monitor_type_atom, - FALSE, FALSE, FALSE, 0, NULL); - if (err != 0) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "RRConfigureOutputProperty error, %d\n", err); - } - /* Set the current value of the backlight property */ - s = "auto"; - err = RRChangeOutputProperty(output->randr_output, monitor_type_atom, - XA_STRING, 8, PropModeReplace, strlen(s), (pointer)s, - FALSE, FALSE); - if (err != 0) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "RRChangeOutputProperty error, %d\n", err); - } - } - - if (radeon_output->devices & (ATOM_DEVICE_TV_SUPPORT)) { - radeon_tvout_ptr tvout = &radeon_output->tvout; - if (!IS_AVIVO_VARIANT) { - tv_hsize_atom = MAKE_ATOM("tv_horizontal_size"); - - range[0] = -MAX_H_SIZE; - range[1] = MAX_H_SIZE; - err = RRConfigureOutputProperty(output->randr_output, tv_hsize_atom, - FALSE, TRUE, FALSE, 2, range); - if (err != 0) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "RRConfigureOutputProperty error, %d\n", err); - } - data = 0; - err = RRChangeOutputProperty(output->randr_output, tv_hsize_atom, - XA_INTEGER, 32, PropModeReplace, 1, &data, - FALSE, TRUE); - if (err != 0) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "RRChangeOutputProperty error, %d\n", err); - } - - tv_hpos_atom = MAKE_ATOM("tv_horizontal_position"); - - range[0] = -MAX_H_POSITION; - range[1] = MAX_H_POSITION; - err = RRConfigureOutputProperty(output->randr_output, tv_hpos_atom, - FALSE, TRUE, FALSE, 2, range); - if (err != 0) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "RRConfigureOutputProperty error, %d\n", err); - } - data = 0; - err = RRChangeOutputProperty(output->randr_output, tv_hpos_atom, - XA_INTEGER, 32, PropModeReplace, 1, &data, - FALSE, TRUE); - if (err != 0) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "RRChangeOutputProperty error, %d\n", err); - } - - tv_vpos_atom = MAKE_ATOM("tv_vertical_position"); - - range[0] = -MAX_V_POSITION; - range[1] = MAX_V_POSITION; - err = RRConfigureOutputProperty(output->randr_output, tv_vpos_atom, - FALSE, TRUE, FALSE, 2, range); - if (err != 0) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "RRConfigureOutputProperty error, %d\n", err); - } - data = 0; - err = RRChangeOutputProperty(output->randr_output, tv_vpos_atom, - XA_INTEGER, 32, PropModeReplace, 1, &data, - FALSE, TRUE); - if (err != 0) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "RRChangeOutputProperty error, %d\n", err); - } - } - - tv_std_atom = MAKE_ATOM("tv_standard"); - - err = RRConfigureOutputProperty(output->randr_output, tv_std_atom, - FALSE, FALSE, FALSE, 0, NULL); - if (err != 0) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "RRConfigureOutputProperty error, %d\n", err); - } - - /* Set the current value of the property */ - switch (tvout->tvStd) { - case TV_STD_PAL: - s = "pal"; - break; - case TV_STD_PAL_M: - s = "pal-m"; - break; - case TV_STD_PAL_60: - s = "pal-60"; - break; - case TV_STD_NTSC_J: - s = "ntsc-j"; - break; - case TV_STD_SCART_PAL: - s = "scart-pal"; - break; - case TV_STD_NTSC: - default: - s = "ntsc"; - break; - } - - err = RRChangeOutputProperty(output->randr_output, tv_std_atom, - XA_STRING, 8, PropModeReplace, strlen(s), (pointer)s, - FALSE, FALSE); - if (err != 0) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "RRChangeOutputProperty error, %d\n", err); - } - } -} - -static Bool -radeon_set_mode_for_property(xf86OutputPtr output) -{ - ScrnInfoPtr pScrn = output->scrn; - - if (output->crtc) { - xf86CrtcPtr crtc = output->crtc; - - if (crtc->enabled) { -#ifdef RANDR_14_INTERFACE - xf86CrtcSetRec crtc_set_rec; - - crtc_set_rec.flags = (XF86CrtcSetMode | - XF86CrtcSetOutput | - XF86CrtcSetOrigin | - XF86CrtcSetRotation); - crtc_set_rec.mode = &crtc->desiredMode; - crtc_set_rec.rotation = crtc->desiredRotation; - crtc_set_rec.transform = NULL; - crtc_set_rec.x = crtc->desiredX; - crtc_set_rec.y = crtc->desiredY; - if (!xf86CrtcSet(crtc, &crtc_set_rec)) { -#else - if (!xf86CrtcSetMode(crtc, &crtc->desiredMode, crtc->desiredRotation, - crtc->desiredX, crtc->desiredY)) { -#endif - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, - "Failed to set mode after property change!\n"); - return FALSE; - } - } - } - return TRUE; -} - -static Bool -radeon_set_property(xf86OutputPtr output, Atom property, - RRPropertyValuePtr value) -{ - RADEONInfoPtr info = RADEONPTR(output->scrn); - RADEONOutputPrivatePtr radeon_output = output->driver_private; - INT32 val; - - - if (property == backlight_atom) { - if (value->type != XA_INTEGER || - value->format != 32 || - value->size != 1) { - return FALSE; - } - - val = *(INT32 *)value->data; - if (val < 0 || val > RADEON_MAX_BACKLIGHT_LEVEL) - return FALSE; - -#if defined(__powerpc__) - val = RADEON_MAX_BACKLIGHT_LEVEL - val; -#endif - - radeon_set_backlight_level(output, val); - - } else if (property == load_detection_atom) { - if (value->type != XA_INTEGER || - value->format != 32 || - value->size != 1) { - return FALSE; - } - - val = *(INT32 *)value->data; - if (val < 0 || val > 1) - return FALSE; - - radeon_output->load_detection = val; - - } else if (property == coherent_mode_atom) { - Bool coherent_mode = radeon_output->coherent_mode; - - if (value->type != XA_INTEGER || - value->format != 32 || - value->size != 1) { - return FALSE; - } - - val = *(INT32 *)value->data; - if (val < 0 || val > 1) - return FALSE; - - radeon_output->coherent_mode = val; - if (!radeon_set_mode_for_property(output)) { - radeon_output->coherent_mode = coherent_mode; - (void)radeon_set_mode_for_property(output); - return FALSE; - } - - } else if (property == rmx_atom) { - const char *s; - RADEONRMXType rmx = radeon_output->rmx_type; - - if (value->type != XA_STRING || value->format != 8) - return FALSE; - s = (char*)value->data; - if (value->size == strlen("full") && !strncmp("full", s, strlen("full"))) { - radeon_output->rmx_type = RMX_FULL; - } else if (value->size == strlen("center") && !strncmp("center", s, strlen("center"))) { - radeon_output->rmx_type = RMX_CENTER; - } else if (value->size == strlen("aspect") && !strncmp("aspect", s, strlen("aspect"))) { - if (IS_AVIVO_VARIANT) - radeon_output->rmx_type = RMX_ASPECT; - else - return FALSE; - } else if (value->size == strlen("off") && !strncmp("off", s, strlen("off"))) { - radeon_output->rmx_type = RMX_OFF; - } else - return FALSE; - - if (!radeon_set_mode_for_property(output)) { - radeon_output->rmx_type = rmx; - (void)radeon_set_mode_for_property(output); - return FALSE; - } - } else if (property == tmds_pll_atom) { - radeon_tmds_ptr tmds = NULL; - const char *s; - - if (info->encoders[ATOM_DEVICE_DFP1_INDEX] && info->encoders[ATOM_DEVICE_DFP1_INDEX]->dev_priv) - tmds = (radeon_tmds_ptr)info->encoders[ATOM_DEVICE_DFP1_INDEX]->dev_priv; - else - return FALSE; - - if (value->type != XA_STRING || value->format != 8) - return FALSE; - s = (char*)value->data; - if (value->size == strlen("bios") && !strncmp("bios", s, strlen("bios"))) { - if (!RADEONGetTMDSInfoFromBIOS(output->scrn, tmds)) - RADEONGetTMDSInfoFromTable(output->scrn, tmds); - } else if (value->size == strlen("driver") && !strncmp("driver", s, strlen("driver"))) - RADEONGetTMDSInfoFromTable(output->scrn, tmds); - else - return FALSE; - - return radeon_set_mode_for_property(output); - } else if (property == monitor_type_atom) { - const char *s; - if (value->type != XA_STRING || value->format != 8) - return FALSE; - s = (char*)value->data; - if (value->size == strlen("auto") && !strncmp("auto", s, strlen("auto"))) { - radeon_output->DVIType = DVI_AUTO; - return TRUE; - } else if (value->size == strlen("analog") && !strncmp("analog", s, strlen("analog"))) { - radeon_output->DVIType = DVI_ANALOG; - return TRUE; - } else if (value->size == strlen("digital") && !strncmp("digital", s, strlen("digital"))) { - radeon_output->DVIType = DVI_DIGITAL; - return TRUE; - } else - return FALSE; - } else if (property == tv_hsize_atom) { - radeon_tvout_ptr tvout = &radeon_output->tvout; - if (value->type != XA_INTEGER || - value->format != 32 || - value->size != 1) { - return FALSE; - } - - val = *(INT32 *)value->data; - if (val < -MAX_H_SIZE || val > MAX_H_SIZE) - return FALSE; - - tvout->hSize = val; - if (tvout->tv_on && !IS_AVIVO_VARIANT) - RADEONUpdateHVPosition(output, &output->crtc->mode); - - } else if (property == tv_hpos_atom) { - radeon_tvout_ptr tvout = &radeon_output->tvout; - if (value->type != XA_INTEGER || - value->format != 32 || - value->size != 1) { - return FALSE; - } - - val = *(INT32 *)value->data; - if (val < -MAX_H_POSITION || val > MAX_H_POSITION) - return FALSE; - - tvout->hPos = val; - if (tvout->tv_on && !IS_AVIVO_VARIANT) - RADEONUpdateHVPosition(output, &output->crtc->mode); - - } else if (property == tv_vpos_atom) { - radeon_tvout_ptr tvout = &radeon_output->tvout; - if (value->type != XA_INTEGER || - value->format != 32 || - value->size != 1) { - return FALSE; - } - - val = *(INT32 *)value->data; - if (val < -MAX_H_POSITION || val > MAX_H_POSITION) - return FALSE; - - tvout->vPos = val; - if (tvout->tv_on && !IS_AVIVO_VARIANT) - RADEONUpdateHVPosition(output, &output->crtc->mode); - - } else if (property == tv_std_atom) { - const char *s; - radeon_tvout_ptr tvout = &radeon_output->tvout; - TVStd std = tvout->tvStd; - - if (value->type != XA_STRING || value->format != 8) - return FALSE; - s = (char*)value->data; - if (value->size == strlen("ntsc") && !strncmp("ntsc", s, strlen("ntsc"))) { - tvout->tvStd = TV_STD_NTSC; - } else if (value->size == strlen("pal") && !strncmp("pal", s, strlen("pal"))) { - tvout->tvStd = TV_STD_PAL; - } else if (value->size == strlen("pal-m") && !strncmp("pal-m", s, strlen("pal-m"))) { - tvout->tvStd = TV_STD_PAL_M; - } else if (value->size == strlen("pal-60") && !strncmp("pal-60", s, strlen("pal-60"))) { - tvout->tvStd = TV_STD_PAL_60; - } else if (value->size == strlen("ntsc-j") && !strncmp("ntsc-j", s, strlen("ntsc-j"))) { - tvout->tvStd = TV_STD_NTSC_J; - } else if (value->size == strlen("scart-pal") && !strncmp("scart-pal", s, strlen("scart-pal"))) { - tvout->tvStd = TV_STD_SCART_PAL; - } else if (value->size == strlen("pal-cn") && !strncmp("pal-cn", s, strlen("pal-cn"))) { - tvout->tvStd = TV_STD_PAL_CN; - } else if (value->size == strlen("secam") && !strncmp("secam", s, strlen("secam"))) { - tvout->tvStd = TV_STD_SECAM; - } else - return FALSE; - - if (!radeon_set_mode_for_property(output)) { - tvout->tvStd = std; - (void)radeon_set_mode_for_property(output); - return FALSE; - } - } - - return TRUE; -} - -static const xf86OutputFuncsRec radeon_output_funcs = { - .create_resources = radeon_create_resources, - .dpms = radeon_dpms, - .save = radeon_save, - .restore = radeon_restore, - .mode_valid = radeon_mode_valid, - .mode_fixup = radeon_mode_fixup, - .prepare = radeon_mode_prepare, - .mode_set = radeon_mode_set, - .commit = radeon_mode_commit, - .detect = radeon_detect, - .get_modes = radeon_get_modes, - .set_property = radeon_set_property, - .destroy = radeon_destroy -}; - -Bool -RADEONI2CDoLock(xf86OutputPtr output, I2CBusPtr b, int lock_state) -{ - ScrnInfoPtr pScrn = output->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONI2CBusPtr pRADEONI2CBus = b->DriverPrivate.ptr; - unsigned char *RADEONMMIO = info->MMIO; - uint32_t temp; - - if (lock_state) { - /* RV410 appears to have a bug where the hw i2c in reset - * holds the i2c port in a bad state - switch hw i2c away before - * doing DDC - do this for all r200s/r300s for safety sakes */ - if ((info->ChipFamily >= CHIP_FAMILY_R200) && (!IS_AVIVO_VARIANT)) { - if (pRADEONI2CBus->mask_clk_reg == RADEON_GPIO_MONID) - OUTREG(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | - R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1))); - else - OUTREG(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | - R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3))); - } - - /* set the pad in ddc mode */ - if (IS_DCE3_VARIANT && - pRADEONI2CBus->hw_capable) { - temp = INREG(pRADEONI2CBus->mask_clk_reg); - temp &= ~(1 << 16); - OUTREG(pRADEONI2CBus->mask_clk_reg, temp); - } - - temp = INREG(pRADEONI2CBus->a_clk_reg); - temp &= ~(pRADEONI2CBus->a_clk_mask); - OUTREG(pRADEONI2CBus->a_clk_reg, temp); - - temp = INREG(pRADEONI2CBus->a_data_reg); - temp &= ~(pRADEONI2CBus->a_data_mask); - OUTREG(pRADEONI2CBus->a_data_reg, temp); - } - - temp = INREG(pRADEONI2CBus->mask_clk_reg); - if (lock_state) - temp |= (pRADEONI2CBus->mask_clk_mask); - else - temp &= ~(pRADEONI2CBus->mask_clk_mask); - OUTREG(pRADEONI2CBus->mask_clk_reg, temp); - temp = INREG(pRADEONI2CBus->mask_clk_reg); - - temp = INREG(pRADEONI2CBus->mask_data_reg); - if (lock_state) - temp |= (pRADEONI2CBus->mask_data_mask); - else - temp &= ~(pRADEONI2CBus->mask_data_mask); - OUTREG(pRADEONI2CBus->mask_data_reg, temp); - temp = INREG(pRADEONI2CBus->mask_data_reg); - - return TRUE; -} - -static void RADEONI2CGetBits(I2CBusPtr b, int *Clock, int *data) -{ - ScrnInfoPtr pScrn = xf86Screens[b->scrnIndex]; - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned long val; - unsigned char *RADEONMMIO = info->MMIO; - RADEONI2CBusPtr pRADEONI2CBus = b->DriverPrivate.ptr; - - /* Get the result */ - val = INREG(pRADEONI2CBus->get_clk_reg); - *Clock = (val & pRADEONI2CBus->get_clk_mask) != 0; - val = INREG(pRADEONI2CBus->get_data_reg); - *data = (val & pRADEONI2CBus->get_data_mask) != 0; - -} - -static void RADEONI2CPutBits(I2CBusPtr b, int Clock, int data) -{ - ScrnInfoPtr pScrn = xf86Screens[b->scrnIndex]; - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned long val; - unsigned char *RADEONMMIO = info->MMIO; - RADEONI2CBusPtr pRADEONI2CBus = b->DriverPrivate.ptr; - - val = INREG(pRADEONI2CBus->put_clk_reg) & (uint32_t)~(pRADEONI2CBus->put_clk_mask); - val |= (Clock ? 0:pRADEONI2CBus->put_clk_mask); - OUTREG(pRADEONI2CBus->put_clk_reg, val); - /* read back to improve reliability on some cards. */ - val = INREG(pRADEONI2CBus->put_clk_reg); - - val = INREG(pRADEONI2CBus->put_data_reg) & (uint32_t)~(pRADEONI2CBus->put_data_mask); - val |= (data ? 0:pRADEONI2CBus->put_data_mask); - OUTREG(pRADEONI2CBus->put_data_reg, val); - /* read back to improve reliability on some cards. */ - val = INREG(pRADEONI2CBus->put_data_reg); - -} - -Bool -RADEONI2CInit(ScrnInfoPtr pScrn, I2CBusPtr *bus_ptr, char *name, RADEONI2CBusPtr pRADEONI2CBus) -{ - I2CBusPtr pI2CBus; - - pI2CBus = xf86CreateI2CBusRec(); - if (!pI2CBus) return FALSE; - - pI2CBus->BusName = name; - pI2CBus->scrnIndex = pScrn->scrnIndex; - pI2CBus->I2CPutBits = RADEONI2CPutBits; - pI2CBus->I2CGetBits = RADEONI2CGetBits; - pI2CBus->AcknTimeout = 5; - - pI2CBus->DriverPrivate.ptr = (pointer)pRADEONI2CBus; - - if (!xf86I2CBusInit(pI2CBus)) - return FALSE; - - *bus_ptr = pI2CBus; - return TRUE; -} - -RADEONI2CBusRec -legacy_setup_i2c_bus(int ddc_line) -{ - RADEONI2CBusRec i2c; - - i2c.hw_line = 0; - i2c.hw_capable = FALSE; - i2c.mask_clk_mask = RADEON_GPIO_EN_1; - i2c.mask_data_mask = RADEON_GPIO_EN_0; - i2c.a_clk_mask = RADEON_GPIO_A_1; - i2c.a_data_mask = RADEON_GPIO_A_0; - i2c.put_clk_mask = RADEON_GPIO_EN_1; - i2c.put_data_mask = RADEON_GPIO_EN_0; - i2c.get_clk_mask = RADEON_GPIO_Y_1; - i2c.get_data_mask = RADEON_GPIO_Y_0; - if ((ddc_line == RADEON_LCD_GPIO_MASK) || - (ddc_line == RADEON_MDGPIO_EN_REG)) { - i2c.mask_clk_reg = ddc_line; - i2c.mask_data_reg = ddc_line; - i2c.a_clk_reg = ddc_line; - i2c.a_data_reg = ddc_line; - i2c.put_clk_reg = ddc_line; - i2c.put_data_reg = ddc_line; - i2c.get_clk_reg = ddc_line + 4; - i2c.get_data_reg = ddc_line + 4; - } else { - i2c.mask_clk_reg = ddc_line; - i2c.mask_data_reg = ddc_line; - i2c.a_clk_reg = ddc_line; - i2c.a_data_reg = ddc_line; - i2c.put_clk_reg = ddc_line; - i2c.put_data_reg = ddc_line; - i2c.get_clk_reg = ddc_line; - i2c.get_data_reg = ddc_line; - } - - if (ddc_line) - i2c.valid = TRUE; - else - i2c.valid = FALSE; - - return i2c; -} - -RADEONI2CBusRec -atom_setup_i2c_bus(int ddc_line) -{ - RADEONI2CBusRec i2c; - - i2c.hw_line = 0; - i2c.hw_capable = FALSE; - if (ddc_line == AVIVO_GPIO_0) { - i2c.put_clk_mask = (1 << 19); - i2c.put_data_mask = (1 << 18); - i2c.get_clk_mask = (1 << 19); - i2c.get_data_mask = (1 << 18); - i2c.mask_clk_mask = (1 << 19); - i2c.mask_data_mask = (1 << 18); - i2c.a_clk_mask = (1 << 19); - i2c.a_data_mask = (1 << 18); - } else { - i2c.put_clk_mask = (1 << 0); - i2c.put_data_mask = (1 << 8); - i2c.get_clk_mask = (1 << 0); - i2c.get_data_mask = (1 << 8); - i2c.mask_clk_mask = (1 << 0); - i2c.mask_data_mask = (1 << 8); - i2c.a_clk_mask = (1 << 0); - i2c.a_data_mask = (1 << 8); - } - i2c.mask_clk_reg = ddc_line; - i2c.mask_data_reg = ddc_line; - i2c.a_clk_reg = ddc_line + 0x4; - i2c.a_data_reg = ddc_line + 0x4; - i2c.put_clk_reg = ddc_line + 0x8; - i2c.put_data_reg = ddc_line + 0x8; - i2c.get_clk_reg = ddc_line + 0xc; - i2c.get_data_reg = ddc_line + 0xc; - if (ddc_line) - i2c.valid = TRUE; - else - i2c.valid = FALSE; - - return i2c; -} - -static void -RADEONGetTVInfo(xf86OutputPtr output) -{ - ScrnInfoPtr pScrn = output->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONOutputPrivatePtr radeon_output = output->driver_private; - radeon_tvout_ptr tvout = &radeon_output->tvout; - char *optstr; - - tvout->hPos = 0; - tvout->vPos = 0; - tvout->hSize = 0; - tvout->tv_on = FALSE; - - if (!RADEONGetTVInfoFromBIOS(output)) { - /* set some reasonable defaults */ - tvout->default_tvStd = TV_STD_NTSC; - tvout->tvStd = TV_STD_NTSC; - tvout->TVRefClk = 27.000000000; - tvout->SupportedTVStds = TV_STD_NTSC | TV_STD_PAL; - } - - optstr = (char *)xf86GetOptValString(info->Options, OPTION_TVSTD); - if (optstr) { - if (!strncmp("ntsc", optstr, strlen("ntsc"))) - tvout->tvStd = TV_STD_NTSC; - else if (!strncmp("pal", optstr, strlen("pal"))) - tvout->tvStd = TV_STD_PAL; - else if (!strncmp("pal-m", optstr, strlen("pal-m"))) - tvout->tvStd = TV_STD_PAL_M; - else if (!strncmp("pal-60", optstr, strlen("pal-60"))) - tvout->tvStd = TV_STD_PAL_60; - else if (!strncmp("ntsc-j", optstr, strlen("ntsc-j"))) - tvout->tvStd = TV_STD_NTSC_J; - else if (!strncmp("scart-pal", optstr, strlen("scart-pal"))) - tvout->tvStd = TV_STD_SCART_PAL; - else { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Invalid TV Standard: %s\n", optstr); - } - } - -} - -void RADEONInitConnector(xf86OutputPtr output) -{ - ScrnInfoPtr pScrn = output->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONOutputPrivatePtr radeon_output = output->driver_private; - - if (radeon_output->devices & (ATOM_DEVICE_LCD_SUPPORT)) - radeon_output->rmx_type = RMX_FULL; - else - radeon_output->rmx_type = RMX_OFF; - - if (!IS_AVIVO_VARIANT) { - if (radeon_output->devices & (ATOM_DEVICE_CRT2_SUPPORT)) { - if (xf86ReturnOptValBool(info->Options, OPTION_TVDAC_LOAD_DETECT, FALSE)) - radeon_output->load_detection = 1; - } - } - - if (radeon_output->devices & (ATOM_DEVICE_TV_SUPPORT)) - RADEONGetTVInfo(output); - - if (radeon_output->devices & (ATOM_DEVICE_DFP_SUPPORT)) - radeon_output->coherent_mode = TRUE; - - if (radeon_output->ConnectorType == CONNECTOR_DISPLAY_PORT) { - strcpy(radeon_output->dp_bus_name, output->name); - strcat(radeon_output->dp_bus_name, "-DP"); - RADEON_DP_I2CInit(pScrn, &radeon_output->dp_pI2CBus, radeon_output->dp_bus_name, output); - RADEON_DP_GetSinkType(output); - } - - if (radeon_output->ConnectorType == CONNECTOR_EDP) { - strcpy(radeon_output->dp_bus_name, output->name); - strcat(radeon_output->dp_bus_name, "-eDP"); - RADEON_DP_I2CInit(pScrn, &radeon_output->dp_pI2CBus, radeon_output->dp_bus_name, output); - RADEON_DP_GetSinkType(output); - } - - if (radeon_output->ddc_i2c.valid) - RADEONI2CInit(pScrn, &radeon_output->pI2CBus, output->name, &radeon_output->ddc_i2c); - -} - -#if defined(__powerpc__) -static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - - - switch (info->MacModel) { - case RADEON_MAC_IBOOK: - info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC); - info->BiosConnector[0].ConnectorType = CONNECTOR_LVDS; - info->BiosConnector[0].valid = TRUE; - info->BiosConnector[0].devices = ATOM_DEVICE_LCD1_SUPPORT; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_LCD1_SUPPORT, - 0), - ATOM_DEVICE_LCD1_SUPPORT)) - return FALSE; - - info->BiosConnector[1].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC); - info->BiosConnector[1].load_detection = FALSE; - info->BiosConnector[1].ConnectorType = CONNECTOR_VGA; - info->BiosConnector[1].valid = TRUE; - info->BiosConnector[1].devices = ATOM_DEVICE_CRT2_SUPPORT; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_CRT2_SUPPORT, - 2), - ATOM_DEVICE_CRT2_SUPPORT)) - return FALSE; - - info->BiosConnector[2].ConnectorType = CONNECTOR_STV; - info->BiosConnector[2].load_detection = FALSE; - info->BiosConnector[2].ddc_i2c.valid = FALSE; - info->BiosConnector[2].valid = TRUE; - info->BiosConnector[2].devices = ATOM_DEVICE_TV1_SUPPORT; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_TV1_SUPPORT, - 2), - ATOM_DEVICE_TV1_SUPPORT)) - return FALSE; - return TRUE; - case RADEON_MAC_POWERBOOK_EXTERNAL: - info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC); - info->BiosConnector[0].ConnectorType = CONNECTOR_LVDS; - info->BiosConnector[0].valid = TRUE; - info->BiosConnector[0].devices = ATOM_DEVICE_LCD1_SUPPORT; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_LCD1_SUPPORT, - 0), - ATOM_DEVICE_LCD1_SUPPORT)) - return FALSE; - - info->BiosConnector[1].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC); - info->BiosConnector[1].ConnectorType = CONNECTOR_DVI_I; - info->BiosConnector[1].valid = TRUE; - info->BiosConnector[1].devices = ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_CRT1_SUPPORT, - 1), - ATOM_DEVICE_CRT1_SUPPORT)) - return FALSE; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_DFP2_SUPPORT, - 0), - ATOM_DEVICE_DFP2_SUPPORT)) - return FALSE; - - info->BiosConnector[2].ConnectorType = CONNECTOR_STV; - info->BiosConnector[2].load_detection = FALSE; - info->BiosConnector[2].ddc_i2c.valid = FALSE; - info->BiosConnector[2].valid = TRUE; - info->BiosConnector[2].devices = ATOM_DEVICE_TV1_SUPPORT; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_TV1_SUPPORT, - 2), - ATOM_DEVICE_TV1_SUPPORT)) - return FALSE; - return TRUE; - case RADEON_MAC_POWERBOOK_INTERNAL: - info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC); - info->BiosConnector[0].ConnectorType = CONNECTOR_LVDS; - info->BiosConnector[0].valid = TRUE; - info->BiosConnector[0].devices = ATOM_DEVICE_LCD1_SUPPORT; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_LCD1_SUPPORT, - 0), - ATOM_DEVICE_LCD1_SUPPORT)) - return FALSE; - - info->BiosConnector[1].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC); - info->BiosConnector[1].ConnectorType = CONNECTOR_DVI_I; - info->BiosConnector[1].valid = TRUE; - info->BiosConnector[1].devices = ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_DFP1_SUPPORT; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_CRT1_SUPPORT, - 1), - ATOM_DEVICE_CRT1_SUPPORT)) - return FALSE; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_DFP1_SUPPORT, - 0), - ATOM_DEVICE_DFP1_SUPPORT)) - return FALSE; - - info->BiosConnector[2].ConnectorType = CONNECTOR_STV; - info->BiosConnector[2].load_detection = FALSE; - info->BiosConnector[2].ddc_i2c.valid = FALSE; - info->BiosConnector[2].valid = TRUE; - info->BiosConnector[2].devices = ATOM_DEVICE_TV1_SUPPORT; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_TV1_SUPPORT, - 2), - ATOM_DEVICE_TV1_SUPPORT)) - return FALSE; - return TRUE; - case RADEON_MAC_POWERBOOK_VGA: - info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC); - info->BiosConnector[0].ConnectorType = CONNECTOR_LVDS; - info->BiosConnector[0].valid = TRUE; - info->BiosConnector[0].devices = ATOM_DEVICE_LCD1_SUPPORT; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_LCD1_SUPPORT, - 0), - ATOM_DEVICE_LCD1_SUPPORT)) - return FALSE; - - info->BiosConnector[1].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC); - info->BiosConnector[1].ConnectorType = CONNECTOR_VGA; - info->BiosConnector[1].valid = TRUE; - info->BiosConnector[1].devices = ATOM_DEVICE_CRT1_SUPPORT; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_CRT1_SUPPORT, - 1), - ATOM_DEVICE_CRT1_SUPPORT)) - return FALSE; - - info->BiosConnector[2].ConnectorType = CONNECTOR_STV; - info->BiosConnector[2].load_detection = FALSE; - info->BiosConnector[2].ddc_i2c.valid = FALSE; - info->BiosConnector[2].valid = TRUE; - info->BiosConnector[2].devices = ATOM_DEVICE_TV1_SUPPORT; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_TV1_SUPPORT, - 2), - ATOM_DEVICE_TV1_SUPPORT)) - return FALSE; - return TRUE; - case RADEON_MAC_MINI_EXTERNAL: - info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_CRT2_DDC); - info->BiosConnector[0].load_detection = FALSE; - info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_I; - info->BiosConnector[0].valid = TRUE; - info->BiosConnector[0].devices = ATOM_DEVICE_CRT2_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_CRT2_SUPPORT, - 2), - ATOM_DEVICE_CRT2_SUPPORT)) - return FALSE; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_DFP2_SUPPORT, - 0), - ATOM_DEVICE_DFP2_SUPPORT)) - return FALSE; - - info->BiosConnector[1].ConnectorType = CONNECTOR_STV; - info->BiosConnector[1].load_detection = FALSE; - info->BiosConnector[1].ddc_i2c.valid = FALSE; - info->BiosConnector[1].valid = TRUE; - info->BiosConnector[1].devices = ATOM_DEVICE_TV1_SUPPORT; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_TV1_SUPPORT, - 2), - ATOM_DEVICE_TV1_SUPPORT)) - return FALSE; - return TRUE; - case RADEON_MAC_MINI_INTERNAL: - info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_CRT2_DDC); - info->BiosConnector[0].load_detection = FALSE; - info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_I; - info->BiosConnector[0].valid = TRUE; - info->BiosConnector[0].devices = ATOM_DEVICE_CRT2_SUPPORT | ATOM_DEVICE_DFP1_SUPPORT; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_CRT2_SUPPORT, - 2), - ATOM_DEVICE_CRT2_SUPPORT)) - return FALSE; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_DFP1_SUPPORT, - 0), - ATOM_DEVICE_DFP1_SUPPORT)) - return FALSE; - - info->BiosConnector[1].ConnectorType = CONNECTOR_STV; - info->BiosConnector[1].load_detection = FALSE; - info->BiosConnector[1].ddc_i2c.valid = FALSE; - info->BiosConnector[1].valid = TRUE; - info->BiosConnector[1].devices = ATOM_DEVICE_TV1_SUPPORT; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_TV1_SUPPORT, - 2), - ATOM_DEVICE_TV1_SUPPORT)) - return FALSE; - return TRUE; - case RADEON_MAC_IMAC_G5_ISIGHT: - info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_MONID); - info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_D; - info->BiosConnector[0].valid = TRUE; - info->BiosConnector[0].devices = ATOM_DEVICE_DFP1_SUPPORT; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_DFP1_SUPPORT, - 0), - ATOM_DEVICE_DFP1_SUPPORT)) - return FALSE; - - info->BiosConnector[1].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC); - info->BiosConnector[1].load_detection = FALSE; - info->BiosConnector[1].ConnectorType = CONNECTOR_VGA; - info->BiosConnector[1].valid = TRUE; - info->BiosConnector[1].devices = ATOM_DEVICE_CRT2_SUPPORT; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_CRT2_SUPPORT, - 2), - ATOM_DEVICE_CRT2_SUPPORT)) - return FALSE; - - info->BiosConnector[2].ConnectorType = CONNECTOR_STV; - info->BiosConnector[2].load_detection = FALSE; - info->BiosConnector[2].ddc_i2c.valid = FALSE; - info->BiosConnector[2].valid = TRUE; - info->BiosConnector[2].devices = ATOM_DEVICE_TV1_SUPPORT; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_TV1_SUPPORT, - 2), - ATOM_DEVICE_TV1_SUPPORT)) - return FALSE; - return TRUE; - case RADEON_MAC_EMAC: - /* eMac G4 800/1.0 with radeon 7500, no EDID on internal monitor - * later eMac's (G4 1.25/1.42) with radeon 9200 and 9600 may have - * different ddc setups. need to verify - */ - info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC); - info->BiosConnector[0].ConnectorType = CONNECTOR_VGA; - info->BiosConnector[0].valid = TRUE; - info->BiosConnector[0].devices = ATOM_DEVICE_CRT1_SUPPORT; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_CRT1_SUPPORT, - 1), - ATOM_DEVICE_CRT1_SUPPORT)) - return FALSE; - - info->BiosConnector[1].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_CRT2_DDC); - info->BiosConnector[1].load_detection = FALSE; - info->BiosConnector[1].ConnectorType = CONNECTOR_VGA; - info->BiosConnector[1].valid = TRUE; - info->BiosConnector[1].devices = ATOM_DEVICE_CRT2_SUPPORT; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_CRT2_SUPPORT, - 2), - ATOM_DEVICE_CRT2_SUPPORT)) - return FALSE; - - info->BiosConnector[2].ConnectorType = CONNECTOR_STV; - info->BiosConnector[2].load_detection = FALSE; - info->BiosConnector[2].ddc_i2c.valid = FALSE; - info->BiosConnector[2].valid = TRUE; - info->BiosConnector[2].devices = ATOM_DEVICE_TV1_SUPPORT; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_TV1_SUPPORT, - 2), - ATOM_DEVICE_TV1_SUPPORT)) - return FALSE; - return TRUE; - case RADEON_MAC_SAM440EP: - /* LVDS header */ - info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(0); - info->BiosConnector[0].ConnectorType = CONNECTOR_LVDS; - info->BiosConnector[0].valid = TRUE; - info->BiosConnector[0].devices = ATOM_DEVICE_LCD1_SUPPORT; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_LCD1_SUPPORT, - 0), - ATOM_DEVICE_LCD1_SUPPORT)) - return FALSE; - - /* DVI-I port */ - info->BiosConnector[1].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC); - info->BiosConnector[1].ConnectorType = CONNECTOR_DVI_I; - info->BiosConnector[1].valid = TRUE; - info->BiosConnector[1].devices = ATOM_DEVICE_CRT2_SUPPORT | ATOM_DEVICE_DFP1_SUPPORT; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_CRT2_SUPPORT, - 2), - ATOM_DEVICE_CRT2_SUPPORT)) - return FALSE; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_DFP1_SUPPORT, - 0), - ATOM_DEVICE_DFP1_SUPPORT)) - return FALSE; - - /* VGA header */ - info->BiosConnector[2].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC); - info->BiosConnector[2].ConnectorType = CONNECTOR_VGA; - info->BiosConnector[2].valid = TRUE; - info->BiosConnector[2].devices = ATOM_DEVICE_CRT1_SUPPORT; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_CRT1_SUPPORT, - 1), - ATOM_DEVICE_CRT1_SUPPORT)) - return FALSE; - - /* s-video */ - info->BiosConnector[3].ConnectorType = CONNECTOR_STV; - info->BiosConnector[3].load_detection = FALSE; - info->BiosConnector[3].ddc_i2c.valid = FALSE; - info->BiosConnector[3].valid = TRUE; - info->BiosConnector[3].devices = ATOM_DEVICE_TV1_SUPPORT; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_TV1_SUPPORT, - 2), - ATOM_DEVICE_TV1_SUPPORT)) - return FALSE; - return TRUE; - default: - return FALSE; - } - - return FALSE; -} -#endif - -static void RADEONSetupGenericConnectors(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); - - if (IS_AVIVO_VARIANT) - return; - - if (!pRADEONEnt->HasCRTC2) { - info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC); - info->BiosConnector[0].ConnectorType = CONNECTOR_VGA; - info->BiosConnector[0].valid = TRUE; - info->BiosConnector[0].devices = ATOM_DEVICE_CRT1_SUPPORT; - radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_CRT1_SUPPORT, - 1), - ATOM_DEVICE_CRT1_SUPPORT); - return; - } - - if (info->IsMobility) { - /* Below is the most common setting, but may not be true */ - if (info->IsIGP) { - info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_LCD_GPIO_MASK); - info->BiosConnector[0].ConnectorType = CONNECTOR_LVDS; - info->BiosConnector[0].valid = TRUE; - info->BiosConnector[0].devices = ATOM_DEVICE_LCD1_SUPPORT; - radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_LCD1_SUPPORT, - 0), - ATOM_DEVICE_LCD1_SUPPORT); - - /* IGP only has TVDAC */ - if ((info->ChipFamily == CHIP_FAMILY_RS400) || - (info->ChipFamily == CHIP_FAMILY_RS480)) - info->BiosConnector[1].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_CRT2_DDC); - else - info->BiosConnector[1].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC); - info->BiosConnector[1].load_detection = FALSE; - info->BiosConnector[1].ConnectorType = CONNECTOR_VGA; - info->BiosConnector[1].valid = TRUE; - info->BiosConnector[1].devices = ATOM_DEVICE_CRT1_SUPPORT; - radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_CRT1_SUPPORT, - 2), - ATOM_DEVICE_CRT1_SUPPORT); - } else { -#if defined(__powerpc__) - info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC); -#else - info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_LCD_GPIO_MASK); -#endif - info->BiosConnector[0].ConnectorType = CONNECTOR_LVDS; - info->BiosConnector[0].valid = TRUE; - info->BiosConnector[0].devices = ATOM_DEVICE_LCD1_SUPPORT; - radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_LCD1_SUPPORT, - 0), - ATOM_DEVICE_LCD1_SUPPORT); - - info->BiosConnector[1].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC); - info->BiosConnector[1].ConnectorType = CONNECTOR_VGA; - info->BiosConnector[1].valid = TRUE; - info->BiosConnector[1].devices = ATOM_DEVICE_CRT1_SUPPORT; - radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_CRT1_SUPPORT, - 1), - ATOM_DEVICE_CRT1_SUPPORT); - } - } else { - /* Below is the most common setting, but may not be true */ - if (info->IsIGP) { - if ((info->ChipFamily == CHIP_FAMILY_RS400) || - (info->ChipFamily == CHIP_FAMILY_RS480)) - info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_CRT2_DDC); - else - info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC); - info->BiosConnector[0].load_detection = FALSE; - info->BiosConnector[0].ConnectorType = CONNECTOR_VGA; - info->BiosConnector[0].valid = TRUE; - info->BiosConnector[0].devices = ATOM_DEVICE_CRT1_SUPPORT; - radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_CRT1_SUPPORT, - 1), - ATOM_DEVICE_CRT1_SUPPORT); - - /* not sure what a good default DDCType for DVI on - * IGP desktop chips is - */ - info->BiosConnector[1].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_MONID); /* DDC_DVI? */ - info->BiosConnector[1].ConnectorType = CONNECTOR_DVI_D; - info->BiosConnector[1].valid = TRUE; - info->BiosConnector[1].devices = ATOM_DEVICE_DFP1_SUPPORT; - radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_DFP1_SUPPORT, - 0), - ATOM_DEVICE_DFP1_SUPPORT); - } else { - info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC); - info->BiosConnector[0].load_detection = FALSE; - info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_I; - info->BiosConnector[0].valid = TRUE; - info->BiosConnector[0].devices = ATOM_DEVICE_CRT2_SUPPORT | ATOM_DEVICE_DFP1_SUPPORT; - radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_CRT2_SUPPORT, - 2), - ATOM_DEVICE_CRT2_SUPPORT); - radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_DFP1_SUPPORT, - 0), - ATOM_DEVICE_DFP1_SUPPORT); - -#if defined(__powerpc__) - info->BiosConnector[1].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC); - info->BiosConnector[1].ConnectorType = CONNECTOR_DVI_I; - info->BiosConnector[1].valid = TRUE; - info->BiosConnector[1].devices = ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT; - radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_CRT1_SUPPORT, - 1), - ATOM_DEVICE_CRT1_SUPPORT); - radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_DFP2_SUPPORT, - 0), - ATOM_DEVICE_DFP2_SUPPORT); -#else - info->BiosConnector[1].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC); - info->BiosConnector[1].ConnectorType = CONNECTOR_VGA; - info->BiosConnector[1].valid = TRUE; - info->BiosConnector[1].devices = ATOM_DEVICE_CRT1_SUPPORT; - radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_CRT1_SUPPORT, - 1), - ATOM_DEVICE_CRT1_SUPPORT); -#endif - } - } - - if (info->InternalTVOut) { - info->BiosConnector[2].ConnectorType = CONNECTOR_STV; - info->BiosConnector[2].load_detection = FALSE; - info->BiosConnector[2].ddc_i2c.valid = FALSE; - info->BiosConnector[2].valid = TRUE; - info->BiosConnector[2].devices = ATOM_DEVICE_TV1_SUPPORT; - radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_TV1_SUPPORT, - 2), - ATOM_DEVICE_TV1_SUPPORT); - } - - /* Some cards have the DDC lines swapped and we have no way to - * detect it yet (Mac cards) - */ - if (xf86ReturnOptValBool(info->Options, OPTION_REVERSE_DDC, FALSE)) { - info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC); - info->BiosConnector[1].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC); - } -} - -#if defined(__powerpc__) - -#ifdef __OpenBSD__ -#include <sys/param.h> -#include <sys/sysctl.h> -#endif - -/* - * Returns RADEONMacModel or 0 based on lines 'detected as' and 'machine' - * in /proc/cpuinfo (on Linux) */ -static RADEONMacModel RADEONDetectMacModel(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONMacModel ret = 0; -#ifdef __linux__ - char cpuline[50]; /* 50 should be sufficient for our purposes */ - FILE *f = fopen ("/proc/cpuinfo", "r"); - - /* Some macs (minis and powerbooks) use internal tmds, others use external tmds - * and not just for dual-link TMDS, it shows up with single-link as well. - * Unforunately, there doesn't seem to be any good way to figure it out. - */ - - /* - * PowerBook5,[1-5]: external tmds, single-link - * PowerBook5,[789]: external tmds, dual-link - * PowerBook5,6: external tmds, single-link or dual-link - * need to add another option to specify the external tmds chip - * or find out what's used and add it. - */ - - - if (f != NULL) { - while (fgets(cpuline, sizeof cpuline, f)) { - if (!strncmp(cpuline, "machine", strlen ("machine"))) { - if (strstr(cpuline, "PowerBook5,1") || - strstr(cpuline, "PowerBook5,2") || - strstr(cpuline, "PowerBook5,3") || - strstr(cpuline, "PowerBook5,4") || - strstr(cpuline, "PowerBook5,5")) { - ret = RADEON_MAC_POWERBOOK_EXTERNAL; /* single link */ - info->ext_tmds_chip = RADEON_SIL_164; /* works on 5,2 */ - break; - } - - if (strstr(cpuline, "PowerBook5,6")) { - ret = RADEON_MAC_POWERBOOK_EXTERNAL; /* dual or single link */ - break; - } - - if (strstr(cpuline, "PowerBook5,7") || - strstr(cpuline, "PowerBook5,8") || - strstr(cpuline, "PowerBook5,9")) { - ret = RADEON_MAC_POWERBOOK_EXTERNAL; /* dual link */ - info->ext_tmds_chip = RADEON_SIL_1178; /* guess */ - break; - } - - if (strstr(cpuline, "PowerBook3,3")) { - ret = RADEON_MAC_POWERBOOK_VGA; /* vga rather than dvi */ - break; - } - - if (strstr(cpuline, "PowerMac10,1")) { - ret = RADEON_MAC_MINI_INTERNAL; /* internal tmds */ - break; - } - if (strstr(cpuline, "PowerMac10,2")) { - ret = RADEON_MAC_MINI_EXTERNAL; /* external tmds */ - break; - } - } else if (!strncmp(cpuline, "detected as", strlen("detected as"))) { - if (strstr(cpuline, "iBook")) { - ret = RADEON_MAC_IBOOK; - break; - } else if (strstr(cpuline, "PowerBook")) { - ret = RADEON_MAC_POWERBOOK_INTERNAL; /* internal tmds */ - break; - } else if (strstr(cpuline, "iMac G5 (iSight)")) { - ret = RADEON_MAC_IMAC_G5_ISIGHT; - break; - } else if (strstr(cpuline, "eMac")) { - ret = RADEON_MAC_EMAC; - break; - } - - /* No known PowerMac model detected */ - break; - } - } - - fclose (f); - } else - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, - "Cannot detect PowerMac model because /proc/cpuinfo not " - "readable.\n"); - -#endif /* __linux */ - -#ifdef __OpenBSD__ - char model[32]; - int mib[2]; - size_t len; - - mib[0] = CTL_HW; - mib[1] = HW_PRODUCT; - len = sizeof(model); - if (sysctl(mib, 2, model, &len, NULL, 0) >= 0) { - if (strcmp(model, "PowerBook5,1") == 0 || - strcmp(model, "PowerBook5,2") == 0 || - strcmp(model, "PowerBook5,3") == 0 || - strcmp(model, "PowerBook5,4") == 0 || - strcmp(model, "PowerBook5,5") == 0) { - ret = RADEON_MAC_POWERBOOK_EXTERNAL; /* single link */ - info->ext_tmds_chip = RADEON_SIL_164; /* works on 5,2 */ - } - - if (strcmp(model, "PowerBook5,6") == 0) { - ret = RADEON_MAC_POWERBOOK_EXTERNAL; /* dual or single link */ - } - - if (strcmp(model, "PowerBook5,7") || - strcmp(model, "PowerBook5,8") == 0 || - strcmp(model, "PowerBook5,9") == 0) { - ret = RADEON_MAC_POWERBOOK_EXTERNAL; /* dual link */ - info->ext_tmds_chip = RADEON_SIL_1178; /* guess */ - } - - if (strcmp(model, "PowerBook3,3") == 0) { - ret = RADEON_MAC_POWERBOOK_VGA; /* vga rather than dvi */ - } - - if (strcmp(model, "PowerMac10,1") == 0) { - ret = RADEON_MAC_MINI_INTERNAL; /* internal tmds */ - } - - if (strcmp(model, "PowerMac10,2") == 0) { - ret = RADEON_MAC_MINI_EXTERNAL; /* external tmds */ - } - - if (strcmp(model, "PowerBook2,1") == 0 || - strcmp(model, "PowerBook2,2") == 0 || - strcmp(model, "PowerBook4,1") == 0 || - strcmp(model, "PowerBook4,2") == 0 || - strcmp(model, "PowerBook4,3") == 0 || - strcmp(model, "PowerBook6,3") == 0 || - strcmp(model, "PowerBook6,5") == 0 || - strcmp(model, "PowerBook6,7") == 0) { - ret = RADEON_MAC_IBOOK; - } - - if (strcmp(model, "PowerBook1,1") == 0 || - strcmp(model, "PowerBook3,1") == 0 || - strcmp(model, "PowerBook3,2") == 0 || - strcmp(model, "PowerBook3,4") == 0 || - strcmp(model, "PowerBook3,5") == 0) { - ret = RADEON_MAC_POWERBOOK_INTERNAL; - } - - if (strcmp(model, "PowerMac12,1") == 0) { - ret = RADEON_MAC_IMAC_G5_ISIGHT; - } - } -#endif /* __OpenBSD__ */ - - if (ret) { - xf86DrvMsg(pScrn->scrnIndex, X_DEFAULT, "Detected %s.\n", - ret == RADEON_MAC_POWERBOOK_EXTERNAL ? "PowerBook with external DVI" : - ret == RADEON_MAC_POWERBOOK_INTERNAL ? "PowerBook with integrated DVI" : - ret == RADEON_MAC_POWERBOOK_VGA ? "PowerBook with VGA" : - ret == RADEON_MAC_IBOOK ? "iBook" : - ret == RADEON_MAC_MINI_EXTERNAL ? "Mac Mini with external DVI" : - ret == RADEON_MAC_MINI_INTERNAL ? "Mac Mini with integrated DVI" : - "iMac G5 iSight"); - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "If this is not correct, try Option \"MacModel\" and " - "consider reporting to the\n"); - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "xorg-driver-ati@lists.x.org mailing list" -#ifdef __linux__ - " with the contents of /proc/cpuinfo" -#endif - ".\n"); - } - - return ret; -} - -#endif /* __powerpc__ */ - -static int -radeon_output_clones (ScrnInfoPtr pScrn, xf86OutputPtr output) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONOutputPrivatePtr radeon_output = output->driver_private; - xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR (pScrn); - int o; - int index_mask = 0; - - /* no cloning with zaphod */ - if (info->IsPrimary || info->IsSecondary) - return index_mask; - - /* DIG routing gets problematic */ - if (info->ChipFamily >= CHIP_FAMILY_R600) - return index_mask; - - /* LVDS is too wacky */ - if (radeon_output->devices & (ATOM_DEVICE_LCD_SUPPORT)) - return index_mask; - - /* TV requires very specific timing */ - if (radeon_output->devices & (ATOM_DEVICE_TV_SUPPORT)) - return index_mask; - - /* DVO requires 2x ppll clocks depending on the tmds chip */ - if (radeon_output->devices & (ATOM_DEVICE_DFP2_SUPPORT)) - return index_mask; - - for (o = 0; o < config->num_output; o++) { - xf86OutputPtr clone = config->output[o]; - RADEONOutputPrivatePtr radeon_clone = clone->driver_private; - - if (output == clone) /* don't clone yourself */ - continue; - else if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT)) /* LVDS */ - continue; - else if (radeon_clone->devices & (ATOM_DEVICE_TV_SUPPORT)) /* TV */ - continue; - else - index_mask |= (1 << o); - } - - return index_mask; -} - -static xf86OutputPtr -RADEONOutputCreate(ScrnInfoPtr pScrn, const char *name, int i) -{ - char buf[32]; - sprintf(buf, name, i); - return xf86OutputCreate(pScrn, &radeon_output_funcs, buf); -} - -/* - * initialise the static data sos we don't have to re-do at randr change */ -Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) -{ - xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); - RADEONInfoPtr info = RADEONPTR(pScrn); - xf86OutputPtr output; - char *optstr; - int i; - int num_vga = 0; - int num_dvi = 0; - int num_hdmi = 0; - int num_dp = 0; - int num_edp = 0; - - /* We first get the information about all connectors from BIOS. - * This is how the card is phyiscally wired up. - * The information should be correct even on a OEM card. - */ - for (i = 0; i < RADEON_MAX_BIOS_CONNECTOR; i++) { - info->encoders[i] = NULL; - info->BiosConnector[i].valid = FALSE; - info->BiosConnector[i].load_detection = TRUE; - info->BiosConnector[i].shared_ddc = FALSE; - info->BiosConnector[i].ddc_i2c.valid = FALSE; - info->BiosConnector[i].ConnectorType = CONNECTOR_NONE; - info->BiosConnector[i].devices = 0; - } - -#if defined(__powerpc__) - info->MacModel = 0; - optstr = (char *)xf86GetOptValString(info->Options, OPTION_MAC_MODEL); - if (optstr) { - if (!strncmp("ibook", optstr, strlen("ibook"))) - info->MacModel = RADEON_MAC_IBOOK; - else if (!strncmp("powerbook-duallink", optstr, strlen("powerbook-duallink"))) /* alias */ - info->MacModel = RADEON_MAC_POWERBOOK_EXTERNAL; - else if (!strncmp("powerbook-external", optstr, strlen("powerbook-external"))) - info->MacModel = RADEON_MAC_POWERBOOK_EXTERNAL; - else if (!strncmp("powerbook-internal", optstr, strlen("powerbook-internal"))) - info->MacModel = RADEON_MAC_POWERBOOK_INTERNAL; - else if (!strncmp("powerbook-vga", optstr, strlen("powerbook-vga"))) - info->MacModel = RADEON_MAC_POWERBOOK_VGA; - else if (!strncmp("powerbook", optstr, strlen("powerbook"))) /* alias */ - info->MacModel = RADEON_MAC_POWERBOOK_INTERNAL; - else if (!strncmp("mini-internal", optstr, strlen("mini-internal"))) - info->MacModel = RADEON_MAC_MINI_INTERNAL; - else if (!strncmp("mini-external", optstr, strlen("mini-external"))) - info->MacModel = RADEON_MAC_MINI_EXTERNAL; - else if (!strncmp("mini", optstr, strlen("mini"))) /* alias */ - info->MacModel = RADEON_MAC_MINI_EXTERNAL; - else if (!strncmp("imac-g5-isight", optstr, strlen("imac-g5-isight"))) - info->MacModel = RADEON_MAC_IMAC_G5_ISIGHT; - else if (!strncmp("emac", optstr, strlen("emac"))) - info->MacModel = RADEON_MAC_EMAC; - else if (!strncmp("sam440ep", optstr, strlen("sam440ep"))) - info->MacModel = RADEON_MAC_SAM440EP; - else { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Invalid Mac Model: %s\n", optstr); - } - } - - if (!info->MacModel) { - info->MacModel = RADEONDetectMacModel(pScrn); - } - - if (info->MacModel){ - if (!RADEONSetupAppleConnectors(pScrn)) - RADEONSetupGenericConnectors(pScrn); - } else -#endif - if (xf86ReturnOptValBool(info->Options, OPTION_DEFAULT_CONNECTOR_TABLE, FALSE)) { - RADEONSetupGenericConnectors(pScrn); - } else { - if (!RADEONGetConnectorInfoFromBIOS(pScrn)) - RADEONSetupGenericConnectors(pScrn); - } - - /* parse connector table option */ - optstr = (char *)xf86GetOptValString(info->Options, OPTION_CONNECTORTABLE); - - if (optstr) { - unsigned int ddc_line[2]; - int DACType[2], TMDSType[2]; - - for (i = 2; i < RADEON_MAX_BIOS_CONNECTOR; i++) { - info->BiosConnector[i].valid = FALSE; - } - - if (sscanf(optstr, "%u,%u,%u,%u,%u,%u,%u,%u", - &ddc_line[0], - &DACType[0], - &TMDSType[0], - &info->BiosConnector[0].ConnectorType, - &ddc_line[1], - &DACType[1], - &TMDSType[1], - &info->BiosConnector[1].ConnectorType) != 8) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Invalid ConnectorTable option: %s\n", optstr); - return FALSE; - } - - for (i = 0; i < 2; i++) { - info->BiosConnector[i].valid = TRUE; - info->BiosConnector[i].ddc_i2c = legacy_setup_i2c_bus(ddc_line[i]); - switch (DACType[i]) { - case 1: - info->BiosConnector[i].devices |= ATOM_DEVICE_CRT1_SUPPORT; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_CRT1_SUPPORT, - 1), - ATOM_DEVICE_CRT1_SUPPORT)) - return FALSE; - info->BiosConnector[i].load_detection = TRUE; - break; - case 2: - info->BiosConnector[i].devices |= ATOM_DEVICE_CRT2_SUPPORT; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_CRT2_SUPPORT, - 2), - ATOM_DEVICE_CRT2_SUPPORT)) - return FALSE; - info->BiosConnector[i].load_detection = FALSE; - break; - } - switch (TMDSType[i]) { - case 1: - info->BiosConnector[i].devices |= ATOM_DEVICE_DFP1_SUPPORT; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_DFP1_SUPPORT, - 0), - ATOM_DEVICE_DFP1_SUPPORT)) - return FALSE; - break; - case 2: - info->BiosConnector[i].devices |= ATOM_DEVICE_DFP2_SUPPORT; - if (!radeon_add_encoder(pScrn, - radeon_get_encoder_id_from_supported_device(pScrn, - ATOM_DEVICE_DFP2_SUPPORT, - 0), - ATOM_DEVICE_DFP2_SUPPORT)) - return FALSE; - break; - } - } - } - - for (i = 0; i < RADEON_MAX_BIOS_CONNECTOR; i++) { - if (info->BiosConnector[i].valid) { - RADEONConnectorType conntype = info->BiosConnector[i].ConnectorType; - if ((conntype == CONNECTOR_DVI_D) || - (conntype == CONNECTOR_DVI_I) || - (conntype == CONNECTOR_DVI_A) || - (conntype == CONNECTOR_HDMI_TYPE_B)) { - num_dvi++; - } else if (conntype == CONNECTOR_VGA) { - num_vga++; - } else if (conntype == CONNECTOR_HDMI_TYPE_A) { - num_hdmi++; - } else if (conntype == CONNECTOR_DISPLAY_PORT) { - num_dp++; - } else if (conntype == CONNECTOR_EDP) { - num_edp++; - } - } - } - - for (i = 0 ; i < RADEON_MAX_BIOS_CONNECTOR; i++) { - if (info->BiosConnector[i].valid) { - RADEONOutputPrivatePtr radeon_output; - RADEONConnectorType conntype = info->BiosConnector[i].ConnectorType; - - if (conntype == CONNECTOR_NONE) - continue; - - radeon_output = xnfcalloc(sizeof(RADEONOutputPrivateRec), 1); - if (!radeon_output) { - return FALSE; - } - radeon_output->MonType = MT_UNKNOWN; - radeon_output->ConnectorType = conntype; - radeon_output->devices = info->BiosConnector[i].devices; - radeon_output->ddc_i2c = info->BiosConnector[i].ddc_i2c; - radeon_output->igp_lane_info = info->BiosConnector[i].igp_lane_info; - radeon_output->shared_ddc = info->BiosConnector[i].shared_ddc; - radeon_output->load_detection = info->BiosConnector[i].load_detection; - radeon_output->linkb = info->BiosConnector[i].linkb; - radeon_output->dig_encoder = -1; - radeon_output->connector_id = info->BiosConnector[i].connector_object; - radeon_output->connector_object_id = info->BiosConnector[i].connector_object_id; - radeon_output->ucI2cId = info->BiosConnector[i].ucI2cId; - radeon_output->hpd_id = info->BiosConnector[i].hpd_id; - - /* Technically HDMI-B is a glorfied DL DVI so the bios is correct, - * but this can be confusing to users when it comes to output names, - * so call it DVI - */ - if ((conntype == CONNECTOR_DVI_D) || - (conntype == CONNECTOR_DVI_I) || - (conntype == CONNECTOR_DVI_A) || - (conntype == CONNECTOR_HDMI_TYPE_B)) { - output = RADEONOutputCreate(pScrn, "DVI-%d", --num_dvi); - } else if (conntype == CONNECTOR_VGA) { - output = RADEONOutputCreate(pScrn, "VGA-%d", --num_vga); - } else if (conntype == CONNECTOR_HDMI_TYPE_A) { - output = RADEONOutputCreate(pScrn, "HDMI-%d", --num_hdmi); - } else if (conntype == CONNECTOR_DISPLAY_PORT) { - output = RADEONOutputCreate(pScrn, "DisplayPort-%d", --num_dp); - } else if (conntype == CONNECTOR_EDP) { - output = RADEONOutputCreate(pScrn, "eDP-%d", --num_edp); - } else { - output = RADEONOutputCreate(pScrn, - ConnectorTypeName[conntype], 0); - } - - if (!output) { - return FALSE; - } - output->interlaceAllowed = TRUE; - output->doubleScanAllowed = TRUE; - output->driver_private = radeon_output; - if (IS_DCE4_VARIANT) { - output->possible_crtcs = 0x3f; - } else { - output->possible_crtcs = 1; - /* crtc2 can drive LVDS, it just doesn't have RMX */ - if (!(radeon_output->devices & (ATOM_DEVICE_LCD_SUPPORT))) - output->possible_crtcs |= 2; - } - - /* we can clone the DACs, and probably TV-out, - but I'm not sure it's worth the trouble */ - output->possible_clones = 0; - - RADEONInitConnector(output); - } - } - - for (i = 0; i < xf86_config->num_output; i++) { - xf86OutputPtr output = xf86_config->output[i]; - - output->possible_clones = radeon_output_clones(pScrn, output); - RADEONGetHardCodedEDIDFromFile(output); - } - - return TRUE; -} - diff --git a/src/radeon_pm.c b/src/radeon_pm.c deleted file mode 100644 index d5152c80..00000000 --- a/src/radeon_pm.c +++ /dev/null @@ -1,886 +0,0 @@ -/* - * Copyright 2009 Advanced Micro Devices, Inc. - * - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation on the rights to use, copy, modify, merge, - * publish, distribute, sublicense, and/or sell copies of the Software, - * and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR - * AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Author: Alex Deucher <alexander.deucher@amd.com> - * - */ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - - /* Driver data structures */ -#include "radeon.h" -#include "radeon_reg.h" -#include "radeon_macros.h" -#include "radeon_atombios.h" - -#include "ati_pciids_gen.h" - -/* 10 khz */ -static uint32_t calc_eng_mem_clock(ScrnInfoPtr pScrn, - uint32_t req_clock, - int ref_div, - int *fb_div, - int *post_div) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONPLLPtr pll = &info->pll; - - if (req_clock < 15000) { - *post_div = 8; - req_clock *= 8; - } else if (req_clock < 30000) { - *post_div = 4; - req_clock *= 4; - } else if (req_clock < 60000) { - *post_div = 2; - req_clock *= 2; - } else - *post_div = 1; - - req_clock *= ref_div; - req_clock += pll->reference_freq; - req_clock /= (2 * pll->reference_freq); - - *fb_div = req_clock & 0xff; - - req_clock = (req_clock & 0xffff) << 1; - req_clock *= pll->reference_freq; - req_clock /= ref_div; - req_clock /= *post_div; - - return req_clock; - -} - -static void -RADEONSetEngineClock(ScrnInfoPtr pScrn, uint32_t eng_clock) -{ - uint32_t tmp; - int ref_div, fb_div, post_div; - - RADEONWaitForIdleMMIO(pScrn); - - tmp = INPLL(pScrn, RADEON_M_SPLL_REF_FB_DIV); - ref_div = tmp & RADEON_M_SPLL_REF_DIV_MASK; - - eng_clock = calc_eng_mem_clock(pScrn, eng_clock, ref_div, &fb_div, &post_div); - - tmp = INPLL(pScrn, RADEON_CLK_PIN_CNTL); - tmp &= ~RADEON_DONT_USE_XTALIN; - OUTPLL(pScrn, RADEON_CLK_PIN_CNTL, tmp); - - tmp = INPLL(pScrn, RADEON_SCLK_CNTL); - tmp &= ~RADEON_SCLK_SRC_SEL_MASK; - OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); - - usleep(10); - - tmp = INPLL(pScrn, RADEON_SPLL_CNTL); - tmp |= RADEON_SPLL_SLEEP; - OUTPLL(pScrn, RADEON_SPLL_CNTL, tmp); - - usleep(2); - - tmp = INPLL(pScrn, RADEON_SPLL_CNTL); - tmp |= RADEON_SPLL_RESET; - OUTPLL(pScrn, RADEON_SPLL_CNTL, tmp); - - usleep(200); - - tmp = INPLL(pScrn, RADEON_M_SPLL_REF_FB_DIV); - tmp &= ~(RADEON_SPLL_FB_DIV_MASK << RADEON_SPLL_FB_DIV_SHIFT); - tmp |= (fb_div & RADEON_SPLL_FB_DIV_MASK) << RADEON_SPLL_FB_DIV_SHIFT; - OUTPLL(pScrn, RADEON_M_SPLL_REF_FB_DIV, tmp); - - /* XXX: verify on different asics */ - tmp = INPLL(pScrn, RADEON_SPLL_CNTL); - tmp &= ~RADEON_SPLL_PVG_MASK; - if ((eng_clock * post_div) >= 90000) - tmp |= (0x7 << RADEON_SPLL_PVG_SHIFT); - else - tmp |= (0x4 << RADEON_SPLL_PVG_SHIFT); - OUTPLL(pScrn, RADEON_SPLL_CNTL, tmp); - - tmp = INPLL(pScrn, RADEON_SPLL_CNTL); - tmp &= ~RADEON_SPLL_SLEEP; - OUTPLL(pScrn, RADEON_SPLL_CNTL, tmp); - - usleep(2); - - tmp = INPLL(pScrn, RADEON_SPLL_CNTL); - tmp &= ~RADEON_SPLL_RESET; - OUTPLL(pScrn, RADEON_SPLL_CNTL, tmp); - - usleep(200); - - tmp = INPLL(pScrn, RADEON_SCLK_CNTL); - tmp &= ~RADEON_SCLK_SRC_SEL_MASK; - switch (post_div) { - case 1: - default: - tmp |= 1; - break; - case 2: - tmp |= 2; - break; - case 4: - tmp |= 3; - break; - case 8: - tmp |= 4; - break; - } - OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); - - usleep(20); - - tmp = INPLL(pScrn, RADEON_CLK_PIN_CNTL); - tmp |= RADEON_DONT_USE_XTALIN; - OUTPLL(pScrn, RADEON_CLK_PIN_CNTL, tmp); - - usleep(10); - -} - -static void LegacySetClockGating(ScrnInfoPtr pScrn, Bool enable) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - uint32_t tmp; - - if (enable) { - if (!pRADEONEnt->HasCRTC2) { - tmp = INPLL(pScrn, RADEON_SCLK_CNTL); - if ((INREG(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) > - RADEON_CFG_ATI_REV_A13) { - tmp &= ~(RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_RB); - } - tmp &= ~(RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 | - RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_SE | - RADEON_SCLK_FORCE_IDCT | RADEON_SCLK_FORCE_RE | - RADEON_SCLK_FORCE_PB | RADEON_SCLK_FORCE_TAM | - RADEON_SCLK_FORCE_TDM); - OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); - } else if (IS_R300_VARIANT) { - if ((info->ChipFamily == CHIP_FAMILY_RS400) || - (info->ChipFamily == CHIP_FAMILY_RS480)) { - tmp = INPLL(pScrn, RADEON_SCLK_CNTL); - tmp &= ~(RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP | - RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 | - RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 | - R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT | - RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR | - R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX | - R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK | - R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0); - tmp |= RADEON_DYN_STOP_LAT_MASK; - tmp |= RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_VIP; - OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); - - tmp = INPLL(pScrn, RADEON_SCLK_MORE_CNTL); - tmp &= ~RADEON_SCLK_MORE_FORCEON; - tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT; - OUTPLL(pScrn, RADEON_SCLK_MORE_CNTL, tmp); - - tmp = INPLL(pScrn, RADEON_VCLK_ECP_CNTL); - tmp |= (RADEON_PIXCLK_ALWAYS_ONb | - RADEON_PIXCLK_DAC_ALWAYS_ONb); - OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, tmp); - - tmp = INPLL(pScrn, RADEON_PIXCLKS_CNTL); - tmp |= (RADEON_PIX2CLK_ALWAYS_ONb | - RADEON_PIX2CLK_DAC_ALWAYS_ONb | - RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb | - R300_DVOCLK_ALWAYS_ONb | - RADEON_PIXCLK_BLEND_ALWAYS_ONb | - RADEON_PIXCLK_GV_ALWAYS_ONb | - R300_PIXCLK_DVO_ALWAYS_ONb | - RADEON_PIXCLK_LVDS_ALWAYS_ONb | - RADEON_PIXCLK_TMDS_ALWAYS_ONb | - R300_PIXCLK_TRANS_ALWAYS_ONb | - R300_PIXCLK_TVO_ALWAYS_ONb | - R300_P2G2CLK_ALWAYS_ONb | - R300_P2G2CLK_DAC_ALWAYS_ONb); - OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp); - } else if (info->ChipFamily >= CHIP_FAMILY_RV350) { - tmp = INPLL(pScrn, R300_SCLK_CNTL2); - tmp &= ~(R300_SCLK_FORCE_TCL | - R300_SCLK_FORCE_GA | - R300_SCLK_FORCE_CBA); - tmp |= (R300_SCLK_TCL_MAX_DYN_STOP_LAT | - R300_SCLK_GA_MAX_DYN_STOP_LAT | - R300_SCLK_CBA_MAX_DYN_STOP_LAT); - OUTPLL(pScrn, R300_SCLK_CNTL2, tmp); - - tmp = INPLL(pScrn, RADEON_SCLK_CNTL); - tmp &= ~(RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP | - RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 | - RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 | - R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT | - RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR | - R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX | - R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK | - R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0); - tmp |= RADEON_DYN_STOP_LAT_MASK; - OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); - - tmp = INPLL(pScrn, RADEON_SCLK_MORE_CNTL); - tmp &= ~RADEON_SCLK_MORE_FORCEON; - tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT; - OUTPLL(pScrn, RADEON_SCLK_MORE_CNTL, tmp); - - tmp = INPLL(pScrn, RADEON_VCLK_ECP_CNTL); - tmp |= (RADEON_PIXCLK_ALWAYS_ONb | - RADEON_PIXCLK_DAC_ALWAYS_ONb); - OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, tmp); - - tmp = INPLL(pScrn, RADEON_PIXCLKS_CNTL); - tmp |= (RADEON_PIX2CLK_ALWAYS_ONb | - RADEON_PIX2CLK_DAC_ALWAYS_ONb | - RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb | - R300_DVOCLK_ALWAYS_ONb | - RADEON_PIXCLK_BLEND_ALWAYS_ONb | - RADEON_PIXCLK_GV_ALWAYS_ONb | - R300_PIXCLK_DVO_ALWAYS_ONb | - RADEON_PIXCLK_LVDS_ALWAYS_ONb | - RADEON_PIXCLK_TMDS_ALWAYS_ONb | - R300_PIXCLK_TRANS_ALWAYS_ONb | - R300_PIXCLK_TVO_ALWAYS_ONb | - R300_P2G2CLK_ALWAYS_ONb | - R300_P2G2CLK_DAC_ALWAYS_ONb); - OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp); - - tmp = INPLL(pScrn, RADEON_MCLK_MISC); - tmp |= (RADEON_MC_MCLK_DYN_ENABLE | - RADEON_IO_MCLK_DYN_ENABLE); - OUTPLL(pScrn, RADEON_MCLK_MISC, tmp); - - tmp = INPLL(pScrn, RADEON_MCLK_CNTL); - tmp |= (RADEON_FORCEON_MCLKA | - RADEON_FORCEON_MCLKB); - - tmp &= ~(RADEON_FORCEON_YCLKA | - RADEON_FORCEON_YCLKB | - RADEON_FORCEON_MC); - - /* Some releases of vbios have set DISABLE_MC_MCLKA - and DISABLE_MC_MCLKB bits in the vbios table. Setting these - bits will cause H/W hang when reading video memory with dynamic clocking - enabled. */ - if ((tmp & R300_DISABLE_MC_MCLKA) && - (tmp & R300_DISABLE_MC_MCLKB)) { - /* If both bits are set, then check the active channels */ - tmp = INPLL(pScrn, RADEON_MCLK_CNTL); - if (info->RamWidth == 64) { - if (INREG(RADEON_MEM_CNTL) & R300_MEM_USE_CD_CH_ONLY) - tmp &= ~R300_DISABLE_MC_MCLKB; - else - tmp &= ~R300_DISABLE_MC_MCLKA; - } else { - tmp &= ~(R300_DISABLE_MC_MCLKA | - R300_DISABLE_MC_MCLKB); - } - } - - OUTPLL(pScrn, RADEON_MCLK_CNTL, tmp); - } else { - tmp = INPLL(pScrn, RADEON_SCLK_CNTL); - tmp &= ~(R300_SCLK_FORCE_VAP); - tmp |= RADEON_SCLK_FORCE_CP; - OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); - usleep(15000); - - tmp = INPLL(pScrn, R300_SCLK_CNTL2); - tmp &= ~(R300_SCLK_FORCE_TCL | - R300_SCLK_FORCE_GA | - R300_SCLK_FORCE_CBA); - OUTPLL(pScrn, R300_SCLK_CNTL2, tmp); - } - } else { - tmp = INPLL(pScrn, RADEON_CLK_PWRMGT_CNTL); - - tmp &= ~(RADEON_ACTIVE_HILO_LAT_MASK | - RADEON_DISP_DYN_STOP_LAT_MASK | - RADEON_DYN_STOP_MODE_MASK); - - tmp |= (RADEON_ENGIN_DYNCLK_MODE | - (0x01 << RADEON_ACTIVE_HILO_LAT_SHIFT)); - OUTPLL(pScrn, RADEON_CLK_PWRMGT_CNTL, tmp); - usleep(15000); - - tmp = INPLL(pScrn, RADEON_CLK_PIN_CNTL); - tmp |= RADEON_SCLK_DYN_START_CNTL; - OUTPLL(pScrn, RADEON_CLK_PIN_CNTL, tmp); - usleep(15000); - - /* When DRI is enabled, setting DYN_STOP_LAT to zero can cause some R200 - to lockup randomly, leave them as set by BIOS. - */ - tmp = INPLL(pScrn, RADEON_SCLK_CNTL); - /*tmp &= RADEON_SCLK_SRC_SEL_MASK;*/ - tmp &= ~RADEON_SCLK_FORCEON_MASK; - - /*RAGE_6::A11 A12 A12N1 A13, RV250::A11 A12, R300*/ - if (((info->ChipFamily == CHIP_FAMILY_RV250) && - ((INREG(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) < - RADEON_CFG_ATI_REV_A13)) || - ((info->ChipFamily == CHIP_FAMILY_RV100) && - ((INREG(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) <= - RADEON_CFG_ATI_REV_A13))) { - tmp |= RADEON_SCLK_FORCE_CP; - tmp |= RADEON_SCLK_FORCE_VIP; - } - - OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); - - if ((info->ChipFamily == CHIP_FAMILY_RV200) || - (info->ChipFamily == CHIP_FAMILY_RV250) || - (info->ChipFamily == CHIP_FAMILY_RV280)) { - tmp = INPLL(pScrn, RADEON_SCLK_MORE_CNTL); - tmp &= ~RADEON_SCLK_MORE_FORCEON; - - /* RV200::A11 A12 RV250::A11 A12 */ - if (((info->ChipFamily == CHIP_FAMILY_RV200) || - (info->ChipFamily == CHIP_FAMILY_RV250)) && - ((INREG(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) < - RADEON_CFG_ATI_REV_A13)) { - tmp |= RADEON_SCLK_MORE_FORCEON; - } - OUTPLL(pScrn, RADEON_SCLK_MORE_CNTL, tmp); - usleep(15000); - } - - /* RV200::A11 A12, RV250::A11 A12 */ - if (((info->ChipFamily == CHIP_FAMILY_RV200) || - (info->ChipFamily == CHIP_FAMILY_RV250)) && - ((INREG(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) < - RADEON_CFG_ATI_REV_A13)) { - tmp = INPLL(pScrn, RADEON_PLL_PWRMGT_CNTL); - tmp |= RADEON_TCL_BYPASS_DISABLE; - OUTPLL(pScrn, RADEON_PLL_PWRMGT_CNTL, tmp); - } - usleep(15000); - - /*enable dynamic mode for display clocks (PIXCLK and PIX2CLK)*/ - tmp = INPLL(pScrn, RADEON_PIXCLKS_CNTL); - tmp |= (RADEON_PIX2CLK_ALWAYS_ONb | - RADEON_PIX2CLK_DAC_ALWAYS_ONb | - RADEON_PIXCLK_BLEND_ALWAYS_ONb | - RADEON_PIXCLK_GV_ALWAYS_ONb | - RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb | - RADEON_PIXCLK_LVDS_ALWAYS_ONb | - RADEON_PIXCLK_TMDS_ALWAYS_ONb); - - OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp); - usleep(15000); - - tmp = INPLL(pScrn, RADEON_VCLK_ECP_CNTL); - tmp |= (RADEON_PIXCLK_ALWAYS_ONb | - RADEON_PIXCLK_DAC_ALWAYS_ONb); - - OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, tmp); - usleep(15000); - } - } else { - /* Turn everything OFF (ForceON to everything)*/ - if ( !pRADEONEnt->HasCRTC2 ) { - tmp = INPLL(pScrn, RADEON_SCLK_CNTL); - tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_HDP | - RADEON_SCLK_FORCE_DISP1 | RADEON_SCLK_FORCE_TOP | - RADEON_SCLK_FORCE_E2 | RADEON_SCLK_FORCE_SE | - RADEON_SCLK_FORCE_IDCT | RADEON_SCLK_FORCE_VIP | - RADEON_SCLK_FORCE_RE | RADEON_SCLK_FORCE_PB | - RADEON_SCLK_FORCE_TAM | RADEON_SCLK_FORCE_TDM | - RADEON_SCLK_FORCE_RB); - OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); - } else if ((info->ChipFamily == CHIP_FAMILY_RS400) || - (info->ChipFamily == CHIP_FAMILY_RS480)) { - tmp = INPLL(pScrn, RADEON_SCLK_CNTL); - tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP | - RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 | - RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 | - R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT | - RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR | - R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX | - R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK | - R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0); - OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); - - tmp = INPLL(pScrn, RADEON_SCLK_MORE_CNTL); - tmp |= RADEON_SCLK_MORE_FORCEON; - OUTPLL(pScrn, RADEON_SCLK_MORE_CNTL, tmp); - - tmp = INPLL(pScrn, RADEON_VCLK_ECP_CNTL); - tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb | - RADEON_PIXCLK_DAC_ALWAYS_ONb | - R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF); - OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, tmp); - - tmp = INPLL(pScrn, RADEON_PIXCLKS_CNTL); - tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb | - RADEON_PIX2CLK_DAC_ALWAYS_ONb | - RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb | - R300_DVOCLK_ALWAYS_ONb | - RADEON_PIXCLK_BLEND_ALWAYS_ONb | - RADEON_PIXCLK_GV_ALWAYS_ONb | - R300_PIXCLK_DVO_ALWAYS_ONb | - RADEON_PIXCLK_LVDS_ALWAYS_ONb | - RADEON_PIXCLK_TMDS_ALWAYS_ONb | - R300_PIXCLK_TRANS_ALWAYS_ONb | - R300_PIXCLK_TVO_ALWAYS_ONb | - R300_P2G2CLK_ALWAYS_ONb | - R300_P2G2CLK_DAC_ALWAYS_ONb | - R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF); - OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp); - } else if (info->ChipFamily >= CHIP_FAMILY_RV350) { - /* for RV350/M10, no delays are required. */ - tmp = INPLL(pScrn, R300_SCLK_CNTL2); - tmp |= (R300_SCLK_FORCE_TCL | - R300_SCLK_FORCE_GA | - R300_SCLK_FORCE_CBA); - OUTPLL(pScrn, R300_SCLK_CNTL2, tmp); - - tmp = INPLL(pScrn, RADEON_SCLK_CNTL); - tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP | - RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 | - RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 | - R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT | - RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR | - R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX | - R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK | - R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0); - OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); - - tmp = INPLL(pScrn, RADEON_SCLK_MORE_CNTL); - tmp |= RADEON_SCLK_MORE_FORCEON; - OUTPLL(pScrn, RADEON_SCLK_MORE_CNTL, tmp); - - tmp = INPLL(pScrn, RADEON_MCLK_CNTL); - tmp |= (RADEON_FORCEON_MCLKA | - RADEON_FORCEON_MCLKB | - RADEON_FORCEON_YCLKA | - RADEON_FORCEON_YCLKB | - RADEON_FORCEON_MC); - OUTPLL(pScrn, RADEON_MCLK_CNTL, tmp); - - tmp = INPLL(pScrn, RADEON_VCLK_ECP_CNTL); - tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb | - RADEON_PIXCLK_DAC_ALWAYS_ONb | - R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF); - OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, tmp); - - tmp = INPLL(pScrn, RADEON_PIXCLKS_CNTL); - tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb | - RADEON_PIX2CLK_DAC_ALWAYS_ONb | - RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb | - R300_DVOCLK_ALWAYS_ONb | - RADEON_PIXCLK_BLEND_ALWAYS_ONb | - RADEON_PIXCLK_GV_ALWAYS_ONb | - R300_PIXCLK_DVO_ALWAYS_ONb | - RADEON_PIXCLK_LVDS_ALWAYS_ONb | - RADEON_PIXCLK_TMDS_ALWAYS_ONb | - R300_PIXCLK_TRANS_ALWAYS_ONb | - R300_PIXCLK_TVO_ALWAYS_ONb | - R300_P2G2CLK_ALWAYS_ONb | - R300_P2G2CLK_DAC_ALWAYS_ONb | - R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF); - OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp); - } else { - tmp = INPLL(pScrn, RADEON_SCLK_CNTL); - tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_E2); - tmp |= RADEON_SCLK_FORCE_SE; - - if ( !pRADEONEnt->HasCRTC2 ) { - tmp |= ( RADEON_SCLK_FORCE_RB | - RADEON_SCLK_FORCE_TDM | - RADEON_SCLK_FORCE_TAM | - RADEON_SCLK_FORCE_PB | - RADEON_SCLK_FORCE_RE | - RADEON_SCLK_FORCE_VIP | - RADEON_SCLK_FORCE_IDCT | - RADEON_SCLK_FORCE_TOP | - RADEON_SCLK_FORCE_DISP1 | - RADEON_SCLK_FORCE_DISP2 | - RADEON_SCLK_FORCE_HDP ); - } else if ((info->ChipFamily == CHIP_FAMILY_R300) || - (info->ChipFamily == CHIP_FAMILY_R350)) { - tmp |= ( RADEON_SCLK_FORCE_HDP | - RADEON_SCLK_FORCE_DISP1 | - RADEON_SCLK_FORCE_DISP2 | - RADEON_SCLK_FORCE_TOP | - RADEON_SCLK_FORCE_IDCT | - RADEON_SCLK_FORCE_VIP); - } - OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); - - usleep(16000); - - if ((info->ChipFamily == CHIP_FAMILY_R300) || - (info->ChipFamily == CHIP_FAMILY_R350)) { - tmp = INPLL(pScrn, R300_SCLK_CNTL2); - tmp |= ( R300_SCLK_FORCE_TCL | - R300_SCLK_FORCE_GA | - R300_SCLK_FORCE_CBA); - OUTPLL(pScrn, R300_SCLK_CNTL2, tmp); - usleep(16000); - } - - if (info->IsIGP) { - tmp = INPLL(pScrn, RADEON_MCLK_CNTL); - tmp &= ~(RADEON_FORCEON_MCLKA | - RADEON_FORCEON_YCLKA); - OUTPLL(pScrn, RADEON_MCLK_CNTL, tmp); - usleep(16000); - } - - if ((info->ChipFamily == CHIP_FAMILY_RV200) || - (info->ChipFamily == CHIP_FAMILY_RV250) || - (info->ChipFamily == CHIP_FAMILY_RV280)) { - tmp = INPLL(pScrn, RADEON_SCLK_MORE_CNTL); - tmp |= RADEON_SCLK_MORE_FORCEON; - OUTPLL(pScrn, RADEON_SCLK_MORE_CNTL, tmp); - usleep(16000); - } - - tmp = INPLL(pScrn, RADEON_PIXCLKS_CNTL); - tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb | - RADEON_PIX2CLK_DAC_ALWAYS_ONb | - RADEON_PIXCLK_BLEND_ALWAYS_ONb | - RADEON_PIXCLK_GV_ALWAYS_ONb | - RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb | - RADEON_PIXCLK_LVDS_ALWAYS_ONb | - RADEON_PIXCLK_TMDS_ALWAYS_ONb); - - OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp); - usleep(16000); - - tmp = INPLL(pScrn, RADEON_VCLK_ECP_CNTL); - tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb | - RADEON_PIXCLK_DAC_ALWAYS_ONb); - OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, tmp); - } - } -} - -static void RADEONPMQuirks(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - uint32_t tmp; - - RADEONWaitForIdleMMIO(pScrn); - - if (info->ChipFamily < CHIP_FAMILY_RV515) { - tmp = INPLL(pScrn, RADEON_SCLK_CNTL); - if (IS_R300_VARIANT || IS_RV100_VARIANT) - tmp |= RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_VIP; - if ((info->ChipFamily == CHIP_FAMILY_RV250) || (info->ChipFamily == CHIP_FAMILY_RV280)) - tmp |= RADEON_SCLK_FORCE_DISP1 | RADEON_SCLK_FORCE_DISP2; - if ((info->ChipFamily == CHIP_FAMILY_RV350) || (info->ChipFamily == CHIP_FAMILY_RV380)) - tmp |= R300_SCLK_FORCE_VAP; - if (info->ChipFamily == CHIP_FAMILY_R420) - tmp |= R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX; - OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); - } else if (info->ChipFamily < CHIP_FAMILY_R600) { - tmp = INPLL(pScrn, AVIVO_CP_DYN_CNTL); - tmp |= AVIVO_CP_FORCEON; - OUTPLL(pScrn, AVIVO_CP_DYN_CNTL, tmp); - - tmp = INPLL(pScrn, AVIVO_E2_DYN_CNTL); - tmp |= AVIVO_E2_FORCEON; - OUTPLL(pScrn, AVIVO_E2_DYN_CNTL, tmp); - - tmp = INPLL(pScrn, AVIVO_IDCT_DYN_CNTL); - tmp |= AVIVO_IDCT_FORCEON; - OUTPLL(pScrn, AVIVO_IDCT_DYN_CNTL, tmp); - } -} - -static void -RADEONSetPCIELanes(ScrnInfoPtr pScrn, int lanes) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - uint32_t link_width_cntl, mask, target_reg; - - if (info->IsIGP) - return; - - /* don't change lanes on multi-gpu cards for now */ - if ((info->Chipset == PCI_CHIP_RV770_9441) || - (info->Chipset == PCI_CHIP_RV770_9443) || - (info->Chipset == PCI_CHIP_RV770_944B) || - (info->Chipset == PCI_CHIP_RV670_9506) || - (info->Chipset == PCI_CHIP_RV670_9509) || - (info->Chipset == PCI_CHIP_RV670_950F)) - return; - - RADEONWaitForIdleMMIO(pScrn); - - switch (lanes) { - case 0: - mask = RADEON_PCIE_LC_LINK_WIDTH_X0; - break; - case 1: - mask = RADEON_PCIE_LC_LINK_WIDTH_X1; - break; - case 2: - mask = RADEON_PCIE_LC_LINK_WIDTH_X2; - break; - case 4: - mask = RADEON_PCIE_LC_LINK_WIDTH_X4; - break; - case 8: - mask = RADEON_PCIE_LC_LINK_WIDTH_X8; - break; - case 12: - mask = RADEON_PCIE_LC_LINK_WIDTH_X12; - break; - case 16: - default: - mask = RADEON_PCIE_LC_LINK_WIDTH_X16; - break; - } - - if (info->ChipFamily >= CHIP_FAMILY_R600) { - link_width_cntl = INPCIE_P(pScrn, RADEON_PCIE_LC_LINK_WIDTH_CNTL); - - if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) == - (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT)) - return; - - link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK | - RADEON_PCIE_LC_RECONFIG_NOW | - R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE | - R600_PCIE_LC_SHORT_RECONFIG_EN | - R600_PCIE_LC_RENEGOTIATE_EN); - link_width_cntl |= mask; - -#if 0 - /* some northbridges can renegotiate the link rather than requiring - * a complete re-config. - * e.g., AMD 780/790 northbridges (pci ids: 0x5956, 0x5957, 0x5958, etc.) - */ - if (northbridge can renegotiate) - link_width_cntl |= R600_PCIE_LC_RENEGOTIATE_EN; - else -#endif - link_width_cntl |= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE; - - OUTPCIE_P(pScrn, RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); - OUTPCIE_P(pScrn, RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl | RADEON_PCIE_LC_RECONFIG_NOW); - - if (info->ChipFamily >= CHIP_FAMILY_RV770) - target_reg = R700_TARGET_AND_CURRENT_PROFILE_INDEX; - else - target_reg = R600_TARGET_AND_CURRENT_PROFILE_INDEX; - - /* wait for lane set to complete */ - link_width_cntl = INREG(target_reg); - while (link_width_cntl == 0xffffffff) - link_width_cntl = INREG(target_reg); - - } else { - link_width_cntl = INPCIE(pScrn, RADEON_PCIE_LC_LINK_WIDTH_CNTL); - - if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) == - (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT)) - return; - - link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK | - RADEON_PCIE_LC_RECONFIG_NOW | - RADEON_PCIE_LC_RECONFIG_LATER | - RADEON_PCIE_LC_SHORT_RECONFIG_EN); - link_width_cntl |= mask; - OUTPCIE(pScrn, RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); - OUTPCIE(pScrn, RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl | RADEON_PCIE_LC_RECONFIG_NOW); - - /* wait for lane set to complete */ - link_width_cntl = INPCIE(pScrn, RADEON_PCIE_LC_LINK_WIDTH_CNTL); - while (link_width_cntl == 0xffffffff) - link_width_cntl = INPCIE(pScrn, RADEON_PCIE_LC_LINK_WIDTH_CNTL); - - } - -} - -static void -RADEONSetClockGating(ScrnInfoPtr pScrn, Bool enable) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - - RADEONWaitForIdleMMIO(pScrn); - - if (info->ChipFamily >= CHIP_FAMILY_R600) - atombios_static_pwrmgt_setup(pScrn, enable); - else { - if (info->IsAtomBios) { - atombios_static_pwrmgt_setup(pScrn, enable); - atombios_clk_gating_setup(pScrn, enable); - } else if (info->IsMobility) - LegacySetClockGating(pScrn, enable); - } - - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Dynamic Clock Gating %sabled\n", - enable ? "En" : "Dis"); -} - -static void RADEONSetStaticPowerMode(ScrnInfoPtr pScrn, RADEONPMType type) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - int i; - - for (i = 0; i < info->pm.num_modes; i++) { - if (info->pm.mode[i].type == type) - break; - } - - if (i == info->pm.num_modes) - return; - - if (i == info->pm.current_mode) - return; - - RADEONWaitForIdleMMIO(pScrn); - - if (info->IsAtomBios) - atombios_set_engine_clock(pScrn, info->pm.mode[i].sclk); - else - RADEONSetEngineClock(pScrn, info->pm.mode[i].sclk); - - if (info->cardType == CARD_PCIE) - RADEONSetPCIELanes(pScrn, info->pm.mode[i].pcie_lanes); - - info->pm.current_mode = i; - - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Power Mode Switch\n"); -} - - -void RADEONPMInit(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - - if (xf86ReturnOptValBool(info->Options, OPTION_CLOCK_GATING, FALSE)) { - info->pm.clock_gating_enabled = TRUE; - RADEONSetClockGating(pScrn, info->pm.clock_gating_enabled); - } else - info->pm.clock_gating_enabled = FALSE; - - info->pm.mode[0].type = POWER_DEFAULT; - info->pm.mode[0].sclk = (uint32_t)info->sclk * 100; /* 10 khz */ - info->pm.mode[0].mclk = (uint32_t)info->mclk * 100; /* 10 khz */ - info->pm.mode[0].pcie_lanes = 16; /* XXX: read back current lane config */ - info->pm.current_mode = 0; - info->pm.num_modes = 1; - - if (xf86ReturnOptValBool(info->Options, OPTION_DYNAMIC_PM, FALSE)) { - info->pm.dynamic_mode_enabled = TRUE; - info->pm.mode[1].type = POWER_LOW; - info->pm.mode[1].sclk = info->pm.mode[0].sclk / 4; - info->pm.mode[1].mclk = info->pm.mode[0].mclk / 4; - info->pm.mode[1].pcie_lanes = 1; - - info->pm.mode[2].type = POWER_HIGH; - info->pm.mode[2].sclk = info->pm.mode[0].sclk; - info->pm.mode[2].mclk = info->pm.mode[0].mclk; - info->pm.mode[2].pcie_lanes = 16; - - info->pm.num_modes += 2; - - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Dynamic Power Management Enabled\n"); - } else { - info->pm.dynamic_mode_enabled = FALSE; - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Dynamic Power Management Disabled\n"); - } - - if (xf86ReturnOptValBool(info->Options, OPTION_FORCE_LOW_POWER, FALSE)) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Force Low Power Mode Enabled\n"); - info->pm.force_low_power_enabled = TRUE; - if (info->pm.dynamic_mode_enabled) { - info->pm.mode[2].type = POWER_HIGH; - info->pm.mode[2].sclk = info->pm.mode[0].sclk / 2; - info->pm.mode[2].mclk = info->pm.mode[0].mclk / 2; - info->pm.mode[2].pcie_lanes = 4; - } else { - info->pm.mode[1].type = POWER_HIGH; - info->pm.mode[1].sclk = info->pm.mode[0].sclk / 2; - info->pm.mode[1].mclk = info->pm.mode[0].mclk / 2; - info->pm.mode[1].pcie_lanes = 4; - info->pm.num_modes += 1; - } - RADEONSetStaticPowerMode(pScrn, POWER_HIGH); - } else - info->pm.force_low_power_enabled = FALSE; - - RADEONPMQuirks(pScrn); -} - -void RADEONPMEnterVT(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - - if (info->pm.clock_gating_enabled) - RADEONSetClockGating(pScrn, info->pm.clock_gating_enabled); - RADEONPMQuirks(pScrn); - if (info->pm.force_low_power_enabled || info->pm.dynamic_mode_enabled) - RADEONSetStaticPowerMode(pScrn, POWER_HIGH); -} - -void RADEONPMLeaveVT(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - - if (info->pm.clock_gating_enabled) - RADEONSetClockGating(pScrn, FALSE); - if (info->pm.force_low_power_enabled || info->pm.dynamic_mode_enabled) - RADEONSetStaticPowerMode(pScrn, POWER_DEFAULT); -} - -void RADEONPMFini(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - - if (info->pm.clock_gating_enabled) - RADEONSetClockGating(pScrn, FALSE); - if (info->pm.force_low_power_enabled || info->pm.dynamic_mode_enabled) - RADEONSetStaticPowerMode(pScrn, POWER_DEFAULT); -} - -void RADEONPMBlockHandler(ScrnInfoPtr pScrn) -{ - RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); - - if ((!pRADEONEnt->Controller[0]->enabled) && - (!pRADEONEnt->Controller[1]->enabled)) - RADEONSetStaticPowerMode(pScrn, POWER_LOW); - else - RADEONSetStaticPowerMode(pScrn, POWER_HIGH); - -} - diff --git a/src/radeon_probe.c b/src/radeon_probe.c index 26dec285..8044b45a 100644 --- a/src/radeon_probe.c +++ b/src/radeon_probe.c @@ -50,40 +50,15 @@ #include "xf86Resources.h" #endif -#ifdef XF86DRM_MODE #include "xf86drmMode.h" #include "dri.h" -#endif #include "radeon_chipset_gen.h" #include "radeon_pci_chipset_gen.h" -#include "radeon_chipinfo_gen.h" - #ifdef XSERVER_LIBPCIACCESS #include "radeon_pci_device_match_gen.h" - -static Bool radeon_ums_supported(ScrnInfoPtr pScrn, struct pci_device *pci_dev) -{ - unsigned family = 0, i; - - for (i = 0; i < sizeof(RADEONCards) / sizeof(RADEONCardInfo); i++) { - if (pci_dev->device_id == RADEONCards[i].pci_device_id) { - family = RADEONCards[i].chip_family; - break; - } - } - - if (family >= CHIP_FAMILY_SUMO) { - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, 0, - "GPU only supported with KMS, using vesa instead.\n"); - return FALSE; - } - return TRUE; -} -#else -#define radeon_ums_supported(x, y) TRUE #endif #ifndef XSERVER_LIBPCIACCESS @@ -109,7 +84,6 @@ RADEONIdentify(int flags) } -#ifdef XF86DRM_MODE static Bool radeon_kernel_mode_enabled(ScrnInfoPtr pScrn, struct pci_device *pci_dev) { char *busIdString; @@ -134,16 +108,12 @@ static Bool radeon_kernel_mode_enabled(ScrnInfoPtr pScrn, struct pci_device *pci "[KMS] Kernel modesetting enabled.\n"); return TRUE; } -#else -#define radeon_kernel_mode_enabled(x, y) FALSE -#endif static Bool radeon_get_scrninfo(int entity_num, void *pci_dev) { ScrnInfoPtr pScrn = NULL; EntityInfoPtr pEnt; - int kms = 0; pScrn = xf86ConfigPciEntity(pScrn, 0, entity_num, RADEONPciChipsets, NULL, @@ -153,12 +123,8 @@ radeon_get_scrninfo(int entity_num, void *pci_dev) return FALSE; if (pci_dev) { - if (radeon_kernel_mode_enabled(pScrn, pci_dev)) { - kms = 1; - } else { - if (!radeon_ums_supported(pScrn, pci_dev)) { - return FALSE; - } + if (!radeon_kernel_mode_enabled(pScrn, pci_dev)) { + return FALSE; } } @@ -171,28 +137,14 @@ radeon_get_scrninfo(int entity_num, void *pci_dev) pScrn->Probe = RADEONProbe; #endif -#ifdef XF86DRM_MODE - if (kms == 1) { - pScrn->PreInit = RADEONPreInit_KMS; - pScrn->ScreenInit = RADEONScreenInit_KMS; - pScrn->SwitchMode = RADEONSwitchMode_KMS; - pScrn->AdjustFrame = RADEONAdjustFrame_KMS; - pScrn->EnterVT = RADEONEnterVT_KMS; - pScrn->LeaveVT = RADEONLeaveVT_KMS; - pScrn->FreeScreen = RADEONFreeScreen_KMS; - pScrn->ValidMode = RADEONValidMode; - } else -#endif - { - pScrn->PreInit = RADEONPreInit; - pScrn->ScreenInit = RADEONScreenInit; - pScrn->SwitchMode = RADEONSwitchMode; - pScrn->AdjustFrame = RADEONAdjustFrame; - pScrn->EnterVT = RADEONEnterVT; - pScrn->LeaveVT = RADEONLeaveVT; - pScrn->FreeScreen = RADEONFreeScreen; - pScrn->ValidMode = RADEONValidMode; - } + pScrn->PreInit = RADEONPreInit_KMS; + pScrn->ScreenInit = RADEONScreenInit_KMS; + pScrn->SwitchMode = RADEONSwitchMode_KMS; + pScrn->AdjustFrame = RADEONAdjustFrame_KMS; + pScrn->EnterVT = RADEONEnterVT_KMS; + pScrn->LeaveVT = RADEONLeaveVT_KMS; + pScrn->FreeScreen = RADEONFreeScreen_KMS; + pScrn->ValidMode = RADEONValidMode; pEnt = xf86GetEntityInfo(entity_num); diff --git a/src/radeon_probe.h b/src/radeon_probe.h index 337829ff..0af45314 100644 --- a/src/radeon_probe.h +++ b/src/radeon_probe.h @@ -44,18 +44,10 @@ #include "xf86Crtc.h" #include "compat-api.h" -#ifdef USE_EXA #include "exa.h" -#endif -#ifdef USE_XAA -#include "xaa.h" -#endif extern DriverRec RADEON; -#define RADEON_MAX_CRTC 6 -#define RADEON_MAX_BIOS_CONNECTOR 16 - typedef enum { CHIP_FAMILY_UNKNOW, CHIP_FAMILY_LEGACY, @@ -123,634 +115,14 @@ typedef struct { int singledac; } RADEONCardInfo; -typedef enum -{ - MT_UNKNOWN = -1, - MT_NONE = 0, - MT_CRT = 1, - MT_LCD = 2, - MT_DFP = 3, - MT_CTV = 4, - MT_STV = 5, - MT_CV = 6, - MT_HDMI = 7, // this should really just be MT_DFP - MT_DP = 8 -} RADEONMonitorType; - -typedef enum -{ - CONNECTOR_NONE, - CONNECTOR_VGA, - CONNECTOR_DVI_I, - CONNECTOR_DVI_D, - CONNECTOR_DVI_A, - CONNECTOR_STV, - CONNECTOR_CTV, - CONNECTOR_LVDS, - CONNECTOR_DIGITAL, - CONNECTOR_SCART, - CONNECTOR_HDMI_TYPE_A, - CONNECTOR_HDMI_TYPE_B, - CONNECTOR_0XC, - CONNECTOR_0XD, - CONNECTOR_DIN, - CONNECTOR_DISPLAY_PORT, - CONNECTOR_EDP, - CONNECTOR_UNSUPPORTED -} RADEONConnectorType; - -typedef enum -{ - DVI_AUTO, - DVI_DIGITAL, - DVI_ANALOG -} RADEONDviType; - -typedef enum -{ - RMX_OFF, - RMX_FULL, - RMX_CENTER, - RMX_ASPECT -} RADEONRMXType; - -typedef struct { - uint32_t freq; - uint32_t value; -}RADEONTMDSPll; - -/* standards */ -typedef enum -{ - TV_STD_NTSC = 1, - TV_STD_PAL = 2, - TV_STD_PAL_M = 4, - TV_STD_PAL_60 = 8, - TV_STD_NTSC_J = 16, - TV_STD_SCART_PAL = 32, - TV_STD_SECAM = 64, - TV_STD_PAL_CN = 128, -} TVStd; - -typedef struct -{ - Bool valid; - uint32_t mask_clk_reg; - uint32_t mask_data_reg; - uint32_t a_clk_reg; - uint32_t a_data_reg; - uint32_t put_clk_reg; - uint32_t put_data_reg; - uint32_t get_clk_reg; - uint32_t get_data_reg; - uint32_t mask_clk_mask; - uint32_t mask_data_mask; - uint32_t put_clk_mask; - uint32_t put_data_mask; - uint32_t get_clk_mask; - uint32_t get_data_mask; - uint32_t a_clk_mask; - uint32_t a_data_mask; - int hw_line; - Bool hw_capable; -} RADEONI2CBusRec, *RADEONI2CBusPtr; - -enum radeon_pll_algo { - RADEON_PLL_OLD, - RADEON_PLL_NEW -}; - -typedef struct _RADEONCrtcPrivateRec { - void *crtc_rotate_mem; - void *cursor_mem; - int crtc_id; - int binding; - uint32_t cursor_offset; - /* Lookup table values to be set when the CRTC is enabled */ - uint16_t lut_r[256], lut_g[256], lut_b[256]; - - uint32_t crtc_offset; - int can_tile; - Bool enabled; - Bool initialized; - Bool scaler_enabled; - float vsc; - float hsc; - int pll_id; - enum radeon_pll_algo pll_algo; -} RADEONCrtcPrivateRec, *RADEONCrtcPrivatePtr; - -typedef struct _radeon_encoder { - uint16_t encoder_id; - int devices; - void *dev_priv; -} radeon_encoder_rec, *radeon_encoder_ptr; - -typedef struct _radeon_tvout { - /* TV out */ - TVStd default_tvStd; - TVStd tvStd; - int hPos; - int vPos; - int hSize; - float TVRefClk; - int SupportedTVStds; - Bool tv_on; -} radeon_tvout_rec, *radeon_tvout_ptr; - -typedef struct _radeon_native_mode { - /* panel stuff */ - int PanelXRes; - int PanelYRes; - int HOverPlus; - int HSyncWidth; - int HBlank; - int VOverPlus; - int VSyncWidth; - int VBlank; - int Flags; - int DotClock; -} radeon_native_mode_rec, *radeon_native_mode_ptr; - -typedef struct _radeon_tvdac { - // tv dac - uint32_t ps2_tvdac_adj; - uint32_t pal_tvdac_adj; - uint32_t ntsc_tvdac_adj; -} radeon_tvdac_rec, *radeon_tvdac_ptr; - -typedef struct _radeon_tmds { - // tmds - RADEONTMDSPll tmds_pll[4]; -} radeon_tmds_rec, *radeon_tmds_ptr; - -typedef struct _radeon_lvds { - // panel mode - radeon_native_mode_rec native_mode; - // lvds - int PanelPwrDly; - int lvds_misc; - int lvds_ss_id; -} radeon_lvds_rec, *radeon_lvds_ptr; - -typedef struct _radeon_dvo { - /* dvo */ - I2CBusPtr pI2CBus; - I2CDevPtr DVOChip; - RADEONI2CBusRec dvo_i2c; - int dvo_i2c_slave_addr; - Bool dvo_duallink; -} radeon_dvo_rec, *radeon_dvo_ptr; - -typedef struct { - RADEONConnectorType ConnectorType; - Bool valid; - int output_id; - int devices; - int hpd_mask; - RADEONI2CBusRec ddc_i2c; - int igp_lane_info; - Bool shared_ddc; - int i2c_line_mux; - Bool load_detection; - Bool linkb; - uint16_t connector_object; - uint16_t connector_object_id; - uint8_t ucI2cId; - uint8_t hpd_id; -} RADEONBIOSConnector; - -typedef struct _RADEONOutputPrivateRec { - uint16_t connector_id; - uint32_t devices; - uint32_t active_device; - Bool enabled; - - int load_detection; - - // DVI/HDMI - Bool coherent_mode; - Bool linkb; - - RADEONConnectorType ConnectorType; - uint16_t connector_object_id; - RADEONDviType DVIType; - RADEONMonitorType MonType; - - // DDC info - I2CBusPtr pI2CBus; - RADEONI2CBusRec ddc_i2c; - Bool shared_ddc; - - Bool custom_edid; - xf86MonPtr custom_mon; - // router info - // HDP info - - // panel mode - radeon_native_mode_rec native_mode; - - // RMX - RADEONRMXType rmx_type; - int Flags; - - //tvout - move to encoder - radeon_tvout_rec tvout; - - /* dce 3.x dig block */ - int igp_lane_info; - int dig_encoder; - - int pixel_clock; - - /* DP - aux bus*/ - I2CBusPtr dp_pI2CBus; - uint8_t ucI2cId; - char dp_bus_name[20]; - uint32_t dp_i2c_addr; - Bool dp_i2c_running; - /* DP - general config */ - uint8_t dpcd[8]; - int dp_lane_count; - int dp_clock; - uint8_t hpd_id; - int pll_id; -} RADEONOutputPrivateRec, *RADEONOutputPrivatePtr; - -struct avivo_pll_state { - uint32_t ref_div_src; - uint32_t ref_div; - uint32_t fb_div; - uint32_t post_div_src; - uint32_t post_div; - uint32_t ext_ppll_cntl; - uint32_t pll_cntl; - uint32_t int_ss_cntl; -}; - -struct avivo_crtc_state { - uint32_t pll_source; - uint32_t h_total; - uint32_t h_blank_start_end; - uint32_t h_sync_a; - uint32_t h_sync_a_cntl; - uint32_t h_sync_b; - uint32_t h_sync_b_cntl; - uint32_t v_total; - uint32_t v_blank_start_end; - uint32_t v_sync_a; - uint32_t v_sync_a_cntl; - uint32_t v_sync_b; - uint32_t v_sync_b_cntl; - uint32_t control; - uint32_t blank_control; - uint32_t interlace_control; - uint32_t stereo_control; - uint32_t cursor_control; -}; - -struct avivo_grph_state { - uint32_t enable; - uint32_t control; - uint32_t swap_control; - uint32_t prim_surf_addr; - uint32_t sec_surf_addr; - uint32_t pitch; - uint32_t prim_surf_addr_hi; - uint32_t sec_surf_addr_hi; - uint32_t x_offset; - uint32_t y_offset; - uint32_t x_start; - uint32_t y_start; - uint32_t x_end; - uint32_t y_end; - - uint32_t desktop_height; - uint32_t viewport_start; - uint32_t viewport_size; - uint32_t mode_data_format; -}; - -struct dce4_main_block_state { - struct avivo_grph_state grph; - uint32_t scl[6]; - uint32_t crtc[15]; - uint32_t fmt[10]; - uint32_t dig[20]; -}; - -struct dce4_state -{ - - uint32_t vga1_cntl; - uint32_t vga2_cntl; - uint32_t vga3_cntl; - uint32_t vga4_cntl; - uint32_t vga5_cntl; - uint32_t vga6_cntl; - uint32_t vga_render_control; - - struct dce4_main_block_state block[6]; - - uint32_t vga_pll[3][3]; - uint32_t pll[2][15]; - uint32_t pll_route[6]; - - uint32_t dac[2][26]; - uint32_t uniphy[6][10]; - - uint32_t dig[20]; -}; - -struct avivo_state -{ - uint32_t hdp_fb_location; - uint32_t mc_memory_map; - uint32_t vga_memory_base; - uint32_t vga_fb_start; - - uint32_t vga1_cntl; - uint32_t vga2_cntl; - uint32_t vga3_cntl; - uint32_t vga4_cntl; - uint32_t vga5_cntl; - uint32_t vga6_cntl; - uint32_t vga_render_control; - - uint32_t crtc_master_en; - uint32_t crtc_tv_control; - uint32_t dc_lb_memory_split; - - struct avivo_pll_state pll[2]; - - struct avivo_pll_state vga25_ppll; - struct avivo_pll_state vga28_ppll; - struct avivo_pll_state vga41_ppll; - - struct avivo_crtc_state crtc[2]; - - struct avivo_grph_state grph[2]; - - /* DDIA block on RS6xx chips */ - uint32_t ddia[37]; - - /* scalers */ - uint32_t d1scl[40]; - uint32_t d2scl[40]; - uint32_t dxscl[6+2]; - - /* dac regs */ - uint32_t daca[26]; - uint32_t dacb[26]; - - /* tmdsa */ - uint32_t tmdsa[31]; - - /* lvtma */ - uint32_t lvtma[39]; - - /* dvoa */ - uint32_t dvoa[16]; - - /* DCE3+ chips */ - uint32_t fmt1[18]; - uint32_t fmt2[18]; - uint32_t dig1[19]; - uint32_t dig2[19]; - uint32_t hdmi1[57]; - uint32_t hdmi2[57]; - uint32_t aux_cntl1[14]; - uint32_t aux_cntl2[14]; - uint32_t aux_cntl3[14]; - uint32_t aux_cntl4[14]; - uint32_t aux_cntl5[14]; - uint32_t aux_cntl6[14]; - uint32_t phy[10]; - uint32_t uniphy1[8]; - uint32_t uniphy2[8]; - uint32_t uniphy3[8]; - uint32_t uniphy4[8]; - uint32_t uniphy5[8]; - uint32_t uniphy6[8]; - -}; - -/* - * Maximum length of horizontal/vertical code timing tables for state storage - */ -#define MAX_H_CODE_TIMING_LEN 32 -#define MAX_V_CODE_TIMING_LEN 32 - -typedef struct { - struct avivo_state avivo; - struct dce4_state dce4; - - /* Common registers */ - uint32_t ovr_clr; - uint32_t ovr_wid_left_right; - uint32_t ovr_wid_top_bottom; - uint32_t ov0_scale_cntl; - uint32_t mpp_tb_config; - uint32_t mpp_gp_config; - uint32_t subpic_cntl; - uint32_t viph_control; - uint32_t i2c_cntl_1; - uint32_t gen_int_cntl; - uint32_t cap0_trig_cntl; - uint32_t cap1_trig_cntl; - uint32_t bus_cntl; - - uint32_t bios_0_scratch; - uint32_t bios_1_scratch; - uint32_t bios_2_scratch; - uint32_t bios_3_scratch; - uint32_t bios_4_scratch; - uint32_t bios_5_scratch; - uint32_t bios_6_scratch; - uint32_t bios_7_scratch; - - uint32_t surface_cntl; - uint32_t surfaces[8][3]; - uint32_t mc_agp_location; - uint32_t mc_agp_location_hi; - uint32_t mc_fb_location; - uint32_t display_base_addr; - uint32_t display2_base_addr; - uint32_t ov0_base_addr; - - /* Other registers to save for VT switches */ - uint32_t dp_datatype; - uint32_t rbbm_soft_reset; - uint32_t clock_cntl_index; - uint32_t amcgpio_en_reg; - uint32_t amcgpio_mask; - - /* CRTC registers */ - uint32_t crtc_gen_cntl; - uint32_t crtc_ext_cntl; - uint32_t dac_cntl; - uint32_t crtc_h_total_disp; - uint32_t crtc_h_sync_strt_wid; - uint32_t crtc_v_total_disp; - uint32_t crtc_v_sync_strt_wid; - uint32_t crtc_offset; - uint32_t crtc_offset_cntl; - uint32_t crtc_pitch; - uint32_t disp_merge_cntl; - uint32_t grph_buffer_cntl; - uint32_t crtc_more_cntl; - uint32_t crtc_tile_x0_y0; - - /* CRTC2 registers */ - uint32_t crtc2_gen_cntl; - uint32_t dac_macro_cntl; - uint32_t dac2_cntl; - uint32_t disp_output_cntl; - uint32_t disp_tv_out_cntl; - uint32_t disp_hw_debug; - uint32_t disp2_merge_cntl; - uint32_t grph2_buffer_cntl; - uint32_t crtc2_h_total_disp; - uint32_t crtc2_h_sync_strt_wid; - uint32_t crtc2_v_total_disp; - uint32_t crtc2_v_sync_strt_wid; - uint32_t crtc2_offset; - uint32_t crtc2_offset_cntl; - uint32_t crtc2_pitch; - uint32_t crtc2_tile_x0_y0; - - /* Flat panel registers */ - uint32_t fp_crtc_h_total_disp; - uint32_t fp_crtc_v_total_disp; - uint32_t fp_gen_cntl; - uint32_t fp2_gen_cntl; - uint32_t fp_h_sync_strt_wid; - uint32_t fp_h2_sync_strt_wid; - uint32_t fp_horz_stretch; - uint32_t fp_horz_vert_active; - uint32_t fp_panel_cntl; - uint32_t fp_v_sync_strt_wid; - uint32_t fp_v2_sync_strt_wid; - uint32_t fp_vert_stretch; - uint32_t lvds_gen_cntl; - uint32_t lvds_pll_cntl; - uint32_t tmds_pll_cntl; - uint32_t tmds_transmitter_cntl; - - /* Computed values for PLL */ - uint32_t dot_clock_freq; - uint32_t pll_output_freq; - int feedback_div; - int reference_div; - int post_div; - - /* PLL registers */ - unsigned ppll_ref_div; - unsigned ppll_div_3; - uint32_t htotal_cntl; - uint32_t vclk_ecp_cntl; - - /* Computed values for PLL2 */ - uint32_t dot_clock_freq_2; - uint32_t pll_output_freq_2; - int feedback_div_2; - int reference_div_2; - int post_div_2; - - /* PLL2 registers */ - uint32_t p2pll_ref_div; - uint32_t p2pll_div_0; - uint32_t htotal_cntl2; - uint32_t pixclks_cntl; - - /* Pallet */ - Bool palette_valid; - Bool palette_saved[2]; - uint32_t palette[2][256]; - - uint32_t disp2_req_cntl1; - uint32_t disp2_req_cntl2; - uint32_t dmif_mem_cntl1; - uint32_t disp1_req_cntl1; - - uint32_t fp_2nd_gen_cntl; - uint32_t fp2_2_gen_cntl; - uint32_t tmds2_cntl; - uint32_t tmds2_transmitter_cntl; - - - /* TV out registers */ - uint32_t tv_master_cntl; - uint32_t tv_htotal; - uint32_t tv_hsize; - uint32_t tv_hdisp; - uint32_t tv_hstart; - uint32_t tv_vtotal; - uint32_t tv_vdisp; - uint32_t tv_timing_cntl; - uint32_t tv_vscaler_cntl1; - uint32_t tv_vscaler_cntl2; - uint32_t tv_sync_size; - uint32_t tv_vrestart; - uint32_t tv_hrestart; - uint32_t tv_frestart; - uint32_t tv_ftotal; - uint32_t tv_clock_sel_cntl; - uint32_t tv_clkout_cntl; - uint32_t tv_data_delay_a; - uint32_t tv_data_delay_b; - uint32_t tv_dac_cntl; - uint32_t tv_pll_cntl; - uint32_t tv_pll_cntl1; - uint32_t tv_pll_fine_cntl; - uint32_t tv_modulator_cntl1; - uint32_t tv_modulator_cntl2; - uint32_t tv_frame_lock_cntl; - uint32_t tv_pre_dac_mux_cntl; - uint32_t tv_rgb_cntl; - uint32_t tv_y_saw_tooth_cntl; - uint32_t tv_y_rise_cntl; - uint32_t tv_y_fall_cntl; - uint32_t tv_uv_adr; - uint32_t tv_upsamp_and_gain_cntl; - uint32_t tv_gain_limit_settings; - uint32_t tv_linear_gain_settings; - uint32_t tv_crc_cntl; - uint32_t tv_sync_cntl; - uint32_t gpiopad_a; - uint32_t pll_test_cntl; - - uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; - uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; - -} RADEONSaveRec, *RADEONSavePtr; - typedef struct { Bool HasSecondary; Bool HasCRTC2; /* All cards except original Radeon */ - /* - * The next two are used to make sure CRTC2 is restored before CRTC_EXT, - * otherwise it could lead to blank screens. - */ - Bool IsSecondaryRestored; - Bool RestorePrimary; - - Bool ReversedDAC; /* TVDAC used as primary dac */ - Bool ReversedTMDS; /* DDC_DVI is used for external TMDS */ - xf86CrtcPtr pCrtc[RADEON_MAX_CRTC]; - RADEONCrtcPrivatePtr Controller[RADEON_MAX_CRTC]; ScrnInfoPtr pSecondaryScrn; ScrnInfoPtr pPrimaryScrn; - RADEONSaveRec ModeReg; /* Current mode */ - RADEONSaveRec SavedReg; /* Original (text) mode */ - - void *MMIO; /* Map of MMIO region */ - int MMIO_cnt; /* Map of FB region refcount */ - void *FB; /* Map of FB region */ - int FB_cnt; /* Map of FB region refcount */ int fd; /* for sharing across zaphod heads */ unsigned long fd_wakeup_registered; /* server generation for which fd has been registered for wakeup handling */ int dri2_info_cnt; @@ -760,22 +132,13 @@ typedef struct extern PciChipsets RADEONPciChipsets[]; /* radeon_driver.c */ -extern Bool RADEONPreInit(ScrnInfoPtr, int); -extern Bool RADEONScreenInit(SCREEN_INIT_ARGS_DECL); -extern Bool RADEONSwitchMode(SWITCH_MODE_ARGS_DECL); #ifdef X_XF86MiscPassMessage extern Bool RADEONHandleMessage(int, const char*, const char*, char**); #endif -extern void RADEONAdjustFrame(ADJUST_FRAME_ARGS_DECL); -extern Bool RADEONEnterVT(VT_FUNC_ARGS_DECL); -extern void RADEONLeaveVT(VT_FUNC_ARGS_DECL); -extern void RADEONFreeScreen(FREE_SCREEN_ARGS_DECL); -extern ModeStatus RADEONValidMode(SCRN_ARG_TYPE, DisplayModePtr, Bool, int); extern const OptionInfoRec *RADEONOptionsWeak(void); -#ifdef XF86DRM_MODE extern Bool RADEONPreInit_KMS(ScrnInfoPtr, int); extern Bool RADEONScreenInit_KMS(SCREEN_INIT_ARGS_DECL); extern Bool RADEONSwitchMode_KMS(SWITCH_MODE_ARGS_DECL); @@ -783,6 +146,7 @@ extern void RADEONAdjustFrame_KMS(ADJUST_FRAME_ARGS_DECL); extern Bool RADEONEnterVT_KMS(VT_FUNC_ARGS_DECL); extern void RADEONLeaveVT_KMS(VT_FUNC_ARGS_DECL); extern void RADEONFreeScreen_KMS(FREE_SCREEN_ARGS_DECL); -#endif +extern ModeStatus RADEONValidMode(SCRN_ARG_TYPE arg, DisplayModePtr mode, + Bool verbose, int flag); #endif /* _RADEON_PROBE_H_ */ diff --git a/src/radeon_render.c b/src/radeon_render.c deleted file mode 100644 index 3b77345a..00000000 --- a/src/radeon_render.c +++ /dev/null @@ -1,1060 +0,0 @@ -/* - * Copyright 2004 Eric Anholt - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - * - * Authors: - * Eric Anholt <anholt@FreeBSD.org> - * Hui Yu <hyu@ati.com> - * - */ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include <string.h> - -#ifdef USE_XAA - -#include "dixstruct.h" - -#include "xaa.h" -#include "xaalocal.h" - -#ifndef RENDER_GENERIC_HELPER -#define RENDER_GENERIC_HELPER - -struct blendinfo { - Bool dst_alpha; - Bool src_alpha; - uint32_t blend_cntl; -}; - -/* The first part of blend_cntl corresponds to Fa from the render "protocol" - * document, and the second part to Fb. - */ -static const struct blendinfo RadeonBlendOp[] = { - /* Clear */ - {0, 0, RADEON_SRC_BLEND_GL_ZERO | - RADEON_DST_BLEND_GL_ZERO}, - /* Src */ - {0, 0, RADEON_SRC_BLEND_GL_ONE | - RADEON_DST_BLEND_GL_ZERO}, - /* Dst */ - {0, 0, RADEON_SRC_BLEND_GL_ZERO | - RADEON_DST_BLEND_GL_ONE}, - /* Over */ - {0, 1, RADEON_SRC_BLEND_GL_ONE | - RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA}, - /* OverReverse */ - {1, 0, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | - RADEON_DST_BLEND_GL_ONE}, - /* In */ - {1, 0, RADEON_SRC_BLEND_GL_DST_ALPHA | - RADEON_DST_BLEND_GL_ZERO}, - /* InReverse */ - {0, 1, RADEON_SRC_BLEND_GL_ZERO | - RADEON_DST_BLEND_GL_SRC_ALPHA}, - /* Out */ - {1, 0, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | - RADEON_DST_BLEND_GL_ZERO}, - /* OutReverse */ - {0, 1, RADEON_SRC_BLEND_GL_ZERO | - RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA}, - /* Atop */ - {1, 1, RADEON_SRC_BLEND_GL_DST_ALPHA | - RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA}, - /* AtopReverse */ - {1, 1, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | - RADEON_DST_BLEND_GL_SRC_ALPHA}, - /* Xor */ - {1, 1, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | - RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA}, - /* Add */ - {0, 0, RADEON_SRC_BLEND_GL_ONE | - RADEON_DST_BLEND_GL_ONE}, - /* Saturate */ - {1, 1, RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE | - RADEON_DST_BLEND_GL_ONE}, - {0, 0, 0}, - {0, 0, 0}, - /* DisjointClear */ - {0, 0, RADEON_SRC_BLEND_GL_ZERO | - RADEON_DST_BLEND_GL_ZERO}, - /* DisjointSrc */ - {0, 0, RADEON_SRC_BLEND_GL_ONE | - RADEON_DST_BLEND_GL_ZERO}, - /* DisjointDst */ - {0, 0, RADEON_SRC_BLEND_GL_ZERO | - RADEON_DST_BLEND_GL_ONE}, - /* DisjointOver unsupported */ - {0, 0, 0}, - /* DisjointOverReverse */ - {1, 1, RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE | - RADEON_DST_BLEND_GL_ONE}, - /* DisjointIn unsupported */ - {0, 0, 0}, - /* DisjointInReverse unsupported */ - {0, 0, 0}, - /* DisjointOut unsupported */ - {1, 1, RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE | - RADEON_DST_BLEND_GL_ZERO}, - /* DisjointOutReverse unsupported */ - {0, 0, 0}, - /* DisjointAtop unsupported */ - {0, 0, 0}, - /* DisjointAtopReverse unsupported */ - {0, 0, 0}, - /* DisjointXor unsupported */ - {0, 0, 0}, - {0, 0, 0}, - {0, 0, 0}, - {0, 0, 0}, - {0, 0, 0}, - /* ConjointClear */ - {0, 0, RADEON_SRC_BLEND_GL_ZERO | - RADEON_DST_BLEND_GL_ZERO}, - /* ConjointSrc */ - {0, 0, RADEON_SRC_BLEND_GL_ONE | - RADEON_DST_BLEND_GL_ZERO}, - /* ConjointDst */ - {0, 0, RADEON_SRC_BLEND_GL_ZERO | - RADEON_DST_BLEND_GL_ONE}, -}; -#define RadeonOpMax (sizeof(RadeonBlendOp) / sizeof(RadeonBlendOp[0])) - -/* Note on texture formats: - * TXFORMAT_Y8 expands to (Y,Y,Y,1). TXFORMAT_I8 expands to (I,I,I,I) - * The RADEON and R200 TXFORMATS we use are the same on r100/r200. - */ - -static CARD32 RADEONTextureFormats[] = { - PICT_a8r8g8b8, - PICT_a8, - PICT_x8r8g8b8, - PICT_r5g6b5, - PICT_a1r5g5b5, - PICT_x1r5g5b5, - 0 -}; - -static CARD32 RADEONDstFormats[] = { - PICT_a8r8g8b8, - PICT_x8r8g8b8, - PICT_r5g6b5, - PICT_a1r5g5b5, - PICT_x1r5g5b5, - 0 -}; - -static uint32_t -RadeonGetTextureFormat(uint32_t format) -{ - switch (format) { - case PICT_a8r8g8b8: - return RADEON_TXFORMAT_ARGB8888 | RADEON_TXFORMAT_ALPHA_IN_MAP; - case PICT_a8: - return RADEON_TXFORMAT_I8 | RADEON_TXFORMAT_ALPHA_IN_MAP; - case PICT_x8r8g8b8: - return RADEON_TXFORMAT_ARGB8888; - case PICT_r5g6b5: - return RADEON_TXFORMAT_RGB565; - case PICT_a1r5g5b5: - return RADEON_TXFORMAT_ARGB1555 | RADEON_TXFORMAT_ALPHA_IN_MAP; - case PICT_x1r5g5b5: - return RADEON_TXFORMAT_ARGB1555; - default: - return 0; - } -} - -static uint32_t -RadeonGetColorFormat(uint32_t format) -{ - switch (format) { - case PICT_a8r8g8b8: - case PICT_x8r8g8b8: - return RADEON_COLOR_FORMAT_ARGB8888; - case PICT_r5g6b5: - return RADEON_COLOR_FORMAT_RGB565; - case PICT_a1r5g5b5: - case PICT_x1r5g5b5: - return RADEON_COLOR_FORMAT_ARGB1555; - default: - return 0; - } -} - -/* Returns a RADEON_RB3D_BLENDCNTL value, or 0 if the operation is not - * supported - */ -static uint32_t -RadeonGetBlendCntl(uint8_t op, uint32_t dstFormat) -{ - uint32_t blend_cntl; - - if (op >= RadeonOpMax || RadeonBlendOp[op].blend_cntl == 0) - return 0; - - blend_cntl = RadeonBlendOp[op].blend_cntl; - - if (RadeonBlendOp[op].dst_alpha && !PICT_FORMAT_A(dstFormat)) { - uint32_t srcblend = blend_cntl & RADEON_SRC_BLEND_MASK; - - /* If there's no destination alpha channel, we need to wire the blending - * to treat the alpha channel as always 1. - */ - if (srcblend == RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA || - srcblend == RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE) - blend_cntl = (blend_cntl & ~RADEON_SRC_BLEND_MASK) | - RADEON_SRC_BLEND_GL_ZERO; - else if (srcblend == RADEON_SRC_BLEND_GL_DST_ALPHA) - blend_cntl = (blend_cntl & ~RADEON_SRC_BLEND_MASK) | - RADEON_SRC_BLEND_GL_ONE; - } - - return blend_cntl; -} - -static __inline__ uint32_t F_TO_DW(float val) -{ - union { - float f; - uint32_t l; - } tmp; - tmp.f = val; - return tmp.l; -} - -/* Compute log base 2 of val. */ -static __inline__ int -ATILog2(int val) -{ - int bits; -#if (defined __i386__ || defined __x86_64__) && (defined __GNUC__) - __asm volatile("bsrl %1, %0" - : "=r" (bits) - : "c" (val) - ); - return bits; -#else - for (bits = 0; val != 0; val >>= 1, ++bits) - ; - return bits - 1; -#endif -} - -static void -RemoveLinear (FBLinearPtr linear) -{ - RADEONInfoPtr info = (RADEONInfoPtr)(linear->devPrivate.ptr); - - info->accel_state->RenderTex = NULL; -} - -static void -RenderCallback (ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - - if ((currentTime.milliseconds > info->accel_state->RenderTimeout) && - info->accel_state->RenderTex) { - xf86FreeOffscreenLinear(info->accel_state->RenderTex); - info->accel_state->RenderTex = NULL; - } - - if (!info->accel_state->RenderTex) - info->accel_state->RenderCallback = NULL; -} - -static Bool -AllocateLinear ( - ScrnInfoPtr pScrn, - int sizeNeeded -){ - RADEONInfoPtr info = RADEONPTR(pScrn); - int cpp = info->CurrentLayout.bitsPerPixel / 8; - - info->accel_state->RenderTimeout = currentTime.milliseconds + 30000; - info->accel_state->RenderCallback = RenderCallback; - - /* XAA allocates in units of pixels at the screen bpp, so adjust size - * appropriately. - */ - sizeNeeded = (sizeNeeded + cpp - 1) / cpp; - - if (info->accel_state->RenderTex) { - if (info->accel_state->RenderTex->size >= sizeNeeded) - return TRUE; - else { - if (xf86ResizeOffscreenLinear(info->accel_state->RenderTex, sizeNeeded)) - return TRUE; - - xf86FreeOffscreenLinear(info->accel_state->RenderTex); - info->accel_state->RenderTex = NULL; - } - } - - info->accel_state->RenderTex = xf86AllocateOffscreenLinear(pScrn->pScreen, sizeNeeded, 32, - NULL, RemoveLinear, info); - - return (info->accel_state->RenderTex != NULL); -} - -#if X_BYTE_ORDER == X_BIG_ENDIAN -static Bool RADEONSetupRenderByteswap(ScrnInfoPtr pScrn, int tex_bytepp) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - uint32_t swapper = info->ModeReg->surface_cntl; - - swapper &= ~(RADEON_NONSURF_AP0_SWP_16BPP | RADEON_NONSURF_AP1_SWP_16BPP | - RADEON_NONSURF_AP0_SWP_32BPP | RADEON_NONSURF_AP1_SWP_32BPP); - - /* Set up byte swapping for the framebuffer aperture as needed */ - switch (tex_bytepp) { - case 1: - break; - case 2: - swapper |= RADEON_NONSURF_AP0_SWP_16BPP | RADEON_NONSURF_AP1_SWP_16BPP; - break; - case 4: - swapper |= RADEON_NONSURF_AP0_SWP_32BPP | RADEON_NONSURF_AP1_SWP_32BPP; - break; - default: - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "%s: Don't know what to do for " - "tex_bytepp == %d!\n", __func__, tex_bytepp); - return FALSE; - } - OUTREG(RADEON_SURFACE_CNTL, swapper); - return TRUE; -} - -static void RADEONRestoreByteswap(RADEONInfoPtr info) -{ - unsigned char *RADEONMMIO = info->MMIO; - - OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl); -} -#endif /* X_BYTE_ORDER == X_BIG_ENDIAN */ - -#endif /* RENDER_GENERIC_HELPER */ - -#if defined(ACCEL_MMIO) && defined(ACCEL_CP) -#error Cannot define both MMIO and CP acceleration! -#endif - -#if !defined(UNIXCPP) || defined(ANSICPP) -#define FUNC_NAME_CAT(prefix,suffix) prefix##suffix -#else -#define FUNC_NAME_CAT(prefix,suffix) prefix/**/suffix -#endif - -#ifdef ACCEL_MMIO -#define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,MMIO) -#else -#ifdef ACCEL_CP -#define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,CP) -#else -#error No accel type defined! -#endif -#endif - -static Bool FUNC_NAME(R100SetupTexture)( - ScrnInfoPtr pScrn, - uint32_t format, - uint8_t *src, - int src_pitch, - unsigned int width, - unsigned int height, - int flags) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - uint8_t *dst; - uint32_t tex_size = 0, txformat; - int dst_pitch, offset, size, tex_bytepp; -#ifdef ACCEL_CP - uint32_t buf_pitch, dst_pitch_off; - int x, y; - unsigned int hpass; - uint8_t *tmp_dst; -#endif - ACCEL_PREAMBLE(); - - if ((width > 2047) || (height > 2047)) - return FALSE; - - txformat = RadeonGetTextureFormat(format); - tex_bytepp = PICT_FORMAT_BPP(format) >> 3; - - dst_pitch = RADEON_ALIGN(width * tex_bytepp, 64); - size = dst_pitch * height; - - if ((flags & XAA_RENDER_REPEAT) && (height != 1) && - (RADEON_ALIGN(width * tex_bytepp, 32) != dst_pitch)) - return FALSE; - -#ifndef ACCEL_CP - -#if X_BYTE_ORDER == X_BIG_ENDIAN - if (!RADEONSetupRenderByteswap(pScrn, tex_bytepp)) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "%s: RADEONSetupRenderByteswap() " - "failed!\n", __func__); - return FALSE; - } -#endif - -#endif - - if (!AllocateLinear(pScrn, size)) - return FALSE; - - if (flags & XAA_RENDER_REPEAT) { - txformat |= ATILog2(width) << RADEON_TXFORMAT_WIDTH_SHIFT; - txformat |= ATILog2(height) << RADEON_TXFORMAT_HEIGHT_SHIFT; - } else { - tex_size = (height << 16) | width; - txformat |= RADEON_TXFORMAT_NON_POWER2; - } - - offset = info->accel_state->RenderTex->offset * pScrn->bitsPerPixel / 8; - dst = (uint8_t*)(info->FB + offset); - - /* Upload texture to card. */ - -#ifdef ACCEL_CP - - RADEONHostDataParams( pScrn, dst, dst_pitch, tex_bytepp, &dst_pitch_off, &x, &y ); - - while ( height ) - { - tmp_dst = RADEONHostDataBlit( pScrn, tex_bytepp, width, - dst_pitch_off, &buf_pitch, - x, &y, &height, &hpass ); - RADEONHostDataBlitCopyPass( pScrn, tex_bytepp, tmp_dst, src, - hpass, buf_pitch, src_pitch ); - src += hpass * src_pitch; - } - - RADEON_PURGE_CACHE(); - RADEON_WAIT_UNTIL_IDLE(); - -#else - - if (info->accel_state->accel->NeedToSync) - info->accel_state->accel->Sync(pScrn); - - while (height--) { - memcpy(dst, src, width * tex_bytepp); - src += src_pitch; - dst += dst_pitch; - } - -#if X_BYTE_ORDER == X_BIG_ENDIAN - RADEONRestoreByteswap(info); -#endif - -#endif /* ACCEL_CP */ - - BEGIN_ACCEL(5); - OUT_ACCEL_REG(RADEON_PP_TXFORMAT_0, txformat); - OUT_ACCEL_REG(RADEON_PP_TEX_SIZE_0, tex_size); - OUT_ACCEL_REG(RADEON_PP_TEX_PITCH_0, dst_pitch - 32); - OUT_ACCEL_REG(RADEON_PP_TXOFFSET_0, offset + info->fbLocation + - pScrn->fbOffset); - OUT_ACCEL_REG(RADEON_PP_TXFILTER_0, RADEON_MAG_FILTER_LINEAR | - RADEON_MIN_FILTER_LINEAR | - RADEON_CLAMP_S_WRAP | - RADEON_CLAMP_T_WRAP); - FINISH_ACCEL(); - - return TRUE; -} - -static Bool -FUNC_NAME(R100SetupForCPUToScreenAlphaTexture) ( - ScrnInfoPtr pScrn, - int op, - CARD16 red, - CARD16 green, - CARD16 blue, - CARD16 alpha, - CARD32 maskFormat, - CARD32 dstFormat, - CARD8 *alphaPtr, - int alphaPitch, - int width, - int height, - int flags -) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - uint32_t colorformat, srccolor, blend_cntl; - ACCEL_PREAMBLE(); - - blend_cntl = RadeonGetBlendCntl(op, dstFormat); - if (blend_cntl == 0) - return FALSE; - - if (!info->accel_state->XInited3D) - RADEONInit3DEngine(pScrn); - - if (!FUNC_NAME(R100SetupTexture)(pScrn, maskFormat, alphaPtr, alphaPitch, - width, height, flags)) - return FALSE; - - colorformat = RadeonGetColorFormat(dstFormat); - - srccolor = ((alpha & 0xff00) << 16) | ((red & 0xff00) << 8) | (blue >> 8) | - (green & 0xff00); - - BEGIN_ACCEL(7); - OUT_ACCEL_REG(RADEON_RB3D_CNTL, colorformat | RADEON_ALPHA_BLEND_ENABLE); - OUT_ACCEL_REG(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE | - RADEON_TEX_BLEND_0_ENABLE); - OUT_ACCEL_REG(RADEON_PP_TFACTOR_0, srccolor); - OUT_ACCEL_REG(RADEON_PP_TXCBLEND_0, RADEON_COLOR_ARG_A_TFACTOR_COLOR | - RADEON_COLOR_ARG_B_T0_ALPHA); - OUT_ACCEL_REG(RADEON_PP_TXABLEND_0, RADEON_ALPHA_ARG_A_TFACTOR_ALPHA | - RADEON_ALPHA_ARG_B_T0_ALPHA); - OUT_ACCEL_REG(RADEON_SE_VTX_FMT, RADEON_SE_VTX_FMT_XY | - RADEON_SE_VTX_FMT_ST0); - OUT_ACCEL_REG(RADEON_RB3D_BLENDCNTL, blend_cntl); - FINISH_ACCEL(); - - return TRUE; -} - - -static Bool -FUNC_NAME(R100SetupForCPUToScreenTexture) ( - ScrnInfoPtr pScrn, - int op, - CARD32 srcFormat, - CARD32 dstFormat, - CARD8 *texPtr, - int texPitch, - int width, - int height, - int flags -) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - uint32_t colorformat, blend_cntl; - ACCEL_PREAMBLE(); - - blend_cntl = RadeonGetBlendCntl(op, dstFormat); - if (blend_cntl == 0) - return FALSE; - - if (!info->accel_state->XInited3D) - RADEONInit3DEngine(pScrn); - - if (!FUNC_NAME(R100SetupTexture)(pScrn, srcFormat, texPtr, texPitch, width, - height, flags)) - return FALSE; - - colorformat = RadeonGetColorFormat(dstFormat); - - BEGIN_ACCEL(6); - OUT_ACCEL_REG(RADEON_RB3D_CNTL, colorformat | RADEON_ALPHA_BLEND_ENABLE); - OUT_ACCEL_REG(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE | - RADEON_TEX_BLEND_0_ENABLE); - if (srcFormat != PICT_a8) - OUT_ACCEL_REG(RADEON_PP_TXCBLEND_0, RADEON_COLOR_ARG_C_T0_COLOR); - else - OUT_ACCEL_REG(RADEON_PP_TXCBLEND_0, RADEON_COLOR_ARG_C_ZERO); - OUT_ACCEL_REG(RADEON_PP_TXABLEND_0, RADEON_ALPHA_ARG_C_T0_ALPHA); - OUT_ACCEL_REG(RADEON_SE_VTX_FMT, RADEON_SE_VTX_FMT_XY | - RADEON_SE_VTX_FMT_ST0); - OUT_ACCEL_REG(RADEON_RB3D_BLENDCNTL, blend_cntl); - FINISH_ACCEL(); - - return TRUE; -} - - -static void -FUNC_NAME(R100SubsequentCPUToScreenTexture) ( - ScrnInfoPtr pScrn, - int dstx, - int dsty, - int srcx, - int srcy, - int width, - int height -) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - int byteshift; - uint32_t fboffset; - float l, t, r, b, fl, fr, ft, fb; - - ACCEL_PREAMBLE(); - - /* Note: we can't simply set up the 3D surface at the same location as the - * front buffer, because the 2048x2048 limit on coordinates may be smaller - * than the (MergedFB) screen. - * Can't use arbitrary offsets for color tiling - */ - if (info->tilingEnabled) { - /* can't play tricks with x coordinate, or could we - tiling is disabled anyway in that case */ - fboffset = info->fbLocation + pScrn->fbOffset + - (pScrn->displayWidth * (dsty & ~15) * (pScrn->bitsPerPixel >> 3)); - l = dstx; - t = (dsty % 16); - } - else { - byteshift = (pScrn->bitsPerPixel >> 4); - fboffset = (info->fbLocation + pScrn->fbOffset + - ((pScrn->displayWidth * dsty + dstx) << byteshift)) & ~15; - l = ((dstx << byteshift) % 16) >> byteshift; - t = 0.0; - } - - r = width + l; - b = height + t; - fl = srcx; - fr = srcx + width; - ft = srcy; - fb = srcy + height; - -#ifdef ACCEL_CP - BEGIN_RING(25); - - OUT_ACCEL_REG(RADEON_RB3D_COLORPITCH, pScrn->displayWidth | - ((info->tilingEnabled && (dsty <= pScrn->virtualY)) ? RADEON_COLOR_TILE_ENABLE : 0)); - OUT_ACCEL_REG(RADEON_RB3D_COLOROFFSET, fboffset); - OUT_RING(CP_PACKET3(RADEON_CP_PACKET3_3D_DRAW_IMMD, 17)); - /* RADEON_SE_VTX_FMT */ - OUT_RING(RADEON_CP_VC_FRMT_XY | - RADEON_CP_VC_FRMT_ST0); - /* SE_VF_CNTL */ - OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN | - RADEON_CP_VC_CNTL_PRIM_WALK_RING | - RADEON_CP_VC_CNTL_MAOS_ENABLE | - RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE | - (4 << RADEON_CP_VC_CNTL_NUM_SHIFT)); - - OUT_RING(F_TO_DW(l)); - OUT_RING(F_TO_DW(t)); - OUT_RING(F_TO_DW(fl)); - OUT_RING(F_TO_DW(ft)); - - OUT_RING(F_TO_DW(r)); - OUT_RING(F_TO_DW(t)); - OUT_RING(F_TO_DW(fr)); - OUT_RING(F_TO_DW(ft)); - - OUT_RING(F_TO_DW(r)); - OUT_RING(F_TO_DW(b)); - OUT_RING(F_TO_DW(fr)); - OUT_RING(F_TO_DW(fb)); - - OUT_RING(F_TO_DW(l)); - OUT_RING(F_TO_DW(b)); - OUT_RING(F_TO_DW(fl)); - OUT_RING(F_TO_DW(fb)); - - OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN); - - ADVANCE_RING(); -#else - BEGIN_ACCEL(20); - - OUT_ACCEL_REG(RADEON_RB3D_COLORPITCH, pScrn->displayWidth | - ((info->tilingEnabled && (dsty <= pScrn->virtualY)) ? RADEON_COLOR_TILE_ENABLE : 0)); - OUT_ACCEL_REG(RADEON_RB3D_COLOROFFSET, fboffset); - - OUT_ACCEL_REG(RADEON_SE_VF_CNTL, RADEON_VF_PRIM_TYPE_TRIANGLE_FAN | - RADEON_VF_PRIM_WALK_DATA | - RADEON_VF_RADEON_MODE | - (4 << RADEON_VF_NUM_VERTICES_SHIFT)); - - OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(l)); - OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(t)); - OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(fl)); - OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(ft)); - - OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(r)); - OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(t)); - OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(fr)); - OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(ft)); - - OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(r)); - OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(b)); - OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(fr)); - OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(fb)); - - OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(l)); - OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(b)); - OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(fl)); - OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(fb)); - - OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN); - FINISH_ACCEL(); -#endif - -} - -static Bool FUNC_NAME(R200SetupTexture)( - ScrnInfoPtr pScrn, - uint32_t format, - uint8_t *src, - int src_pitch, - unsigned int width, - unsigned int height, - int flags) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - uint8_t *dst; - uint32_t tex_size = 0, txformat; - int dst_pitch, offset, size, tex_bytepp; -#ifdef ACCEL_CP - uint32_t buf_pitch, dst_pitch_off; - int x, y; - unsigned int hpass; - uint8_t *tmp_dst; -#endif - ACCEL_PREAMBLE(); - - if ((width > 2048) || (height > 2048)) - return FALSE; - - txformat = RadeonGetTextureFormat(format); - tex_bytepp = PICT_FORMAT_BPP(format) >> 3; - - dst_pitch = RADEON_ALIGN(width * tex_bytepp, 64); - size = dst_pitch * height; - - if ((flags & XAA_RENDER_REPEAT) && (height != 1) && - (RADEON_ALIGN(width * tex_bytepp, 32) != dst_pitch)) - return FALSE; - -#ifndef ACCEL_CP - -#if X_BYTE_ORDER == X_BIG_ENDIAN - if (!RADEONSetupRenderByteswap(pScrn, tex_bytepp)) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "%s: RADEONSetupRenderByteswap() " - "failed!\n", __func__); - return FALSE; - } -#endif - -#endif - - if (!AllocateLinear(pScrn, size)) - return FALSE; - - if (flags & XAA_RENDER_REPEAT) { - txformat |= ATILog2(width) << R200_TXFORMAT_WIDTH_SHIFT; - txformat |= ATILog2(height) << R200_TXFORMAT_HEIGHT_SHIFT; - } else { - tex_size = ((height - 1) << 16) | (width - 1); - txformat |= RADEON_TXFORMAT_NON_POWER2; - } - - info->accel_state->texW[0] = width; - info->accel_state->texH[0] = height; - - offset = info->accel_state->RenderTex->offset * pScrn->bitsPerPixel / 8; - dst = (uint8_t*)(info->FB + offset); - - /* Upload texture to card. */ - -#ifdef ACCEL_CP - - RADEONHostDataParams( pScrn, dst, dst_pitch, tex_bytepp, &dst_pitch_off, &x, &y ); - - while ( height ) - { - tmp_dst = RADEONHostDataBlit( pScrn, tex_bytepp, width, - dst_pitch_off, &buf_pitch, - x, &y, &height, &hpass ); - RADEONHostDataBlitCopyPass( pScrn, tex_bytepp, tmp_dst, src, - hpass, buf_pitch, src_pitch ); - src += hpass * src_pitch; - } - - RADEON_PURGE_CACHE(); - RADEON_WAIT_UNTIL_IDLE(); - -#else - - if (info->accel_state->accel->NeedToSync) - info->accel_state->accel->Sync(pScrn); - - while (height--) { - memcpy(dst, src, width * tex_bytepp); - src += src_pitch; - dst += dst_pitch; - } - -#if X_BYTE_ORDER == X_BIG_ENDIAN - RADEONRestoreByteswap(info); -#endif - -#endif /* ACCEL_CP */ - - BEGIN_ACCEL(6); - OUT_ACCEL_REG(R200_PP_TXFORMAT_0, txformat); - OUT_ACCEL_REG(R200_PP_TXFORMAT_X_0, 0); - OUT_ACCEL_REG(R200_PP_TXSIZE_0, tex_size); - OUT_ACCEL_REG(R200_PP_TXPITCH_0, dst_pitch - 32); - OUT_ACCEL_REG(R200_PP_TXOFFSET_0, offset + info->fbLocation + - pScrn->fbOffset); - OUT_ACCEL_REG(R200_PP_TXFILTER_0, R200_MAG_FILTER_NEAREST | - R200_MIN_FILTER_NEAREST | - R200_CLAMP_S_WRAP | - R200_CLAMP_T_WRAP); - FINISH_ACCEL(); - - return TRUE; -} - -static Bool -FUNC_NAME(R200SetupForCPUToScreenAlphaTexture) ( - ScrnInfoPtr pScrn, - int op, - CARD16 red, - CARD16 green, - CARD16 blue, - CARD16 alpha, - CARD32 maskFormat, - CARD32 dstFormat, - CARD8 *alphaPtr, - int alphaPitch, - int width, - int height, - int flags -) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - uint32_t colorformat, srccolor, blend_cntl; - ACCEL_PREAMBLE(); - - blend_cntl = RadeonGetBlendCntl(op, dstFormat); - if (blend_cntl == 0) - return FALSE; - - if (!info->accel_state->XInited3D) - RADEONInit3DEngine(pScrn); - - if (!FUNC_NAME(R200SetupTexture)(pScrn, maskFormat, alphaPtr, alphaPitch, - width, height, flags)) - return FALSE; - - colorformat = RadeonGetColorFormat(dstFormat); - - srccolor = ((alpha & 0xff00) << 16) | ((red & 0xff00) << 8) | (blue >> 8) | - (green & 0xff00); - - BEGIN_ACCEL(10); - OUT_ACCEL_REG(RADEON_RB3D_CNTL, colorformat | RADEON_ALPHA_BLEND_ENABLE); - OUT_ACCEL_REG(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE | - RADEON_TEX_BLEND_0_ENABLE); - OUT_ACCEL_REG(R200_PP_TFACTOR_0, srccolor); - OUT_ACCEL_REG(R200_PP_TXCBLEND_0, R200_TXC_ARG_A_TFACTOR_COLOR | - R200_TXC_ARG_B_R0_ALPHA); - OUT_ACCEL_REG(R200_PP_TXCBLEND2_0, R200_TXC_OUTPUT_REG_R0); - OUT_ACCEL_REG(R200_PP_TXABLEND_0, R200_TXA_ARG_A_TFACTOR_ALPHA | - R200_TXA_ARG_B_R0_ALPHA); - OUT_ACCEL_REG(R200_PP_TXABLEND2_0, R200_TXA_OUTPUT_REG_R0); - OUT_ACCEL_REG(R200_SE_VTX_FMT_0, 0); - OUT_ACCEL_REG(R200_SE_VTX_FMT_1, (2 << R200_VTX_TEX0_COMP_CNT_SHIFT)); - OUT_ACCEL_REG(RADEON_RB3D_BLENDCNTL, blend_cntl); - FINISH_ACCEL(); - - return TRUE; -} - -static Bool -FUNC_NAME(R200SetupForCPUToScreenTexture) ( - ScrnInfoPtr pScrn, - int op, - CARD32 srcFormat, - CARD32 dstFormat, - CARD8 *texPtr, - int texPitch, - int width, - int height, - int flags -) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - uint32_t colorformat, blend_cntl; - ACCEL_PREAMBLE(); - - blend_cntl = RadeonGetBlendCntl(op, dstFormat); - if (blend_cntl == 0) - return FALSE; - - if (!info->accel_state->XInited3D) - RADEONInit3DEngine(pScrn); - - if (!FUNC_NAME(R200SetupTexture)(pScrn, srcFormat, texPtr, texPitch, width, - height, flags)) - return FALSE; - - colorformat = RadeonGetColorFormat(dstFormat); - - BEGIN_ACCEL(9); - OUT_ACCEL_REG(RADEON_RB3D_CNTL, colorformat | RADEON_ALPHA_BLEND_ENABLE); - OUT_ACCEL_REG(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE | - RADEON_TEX_BLEND_0_ENABLE); - if (srcFormat != PICT_a8) - OUT_ACCEL_REG(R200_PP_TXCBLEND_0, R200_TXC_ARG_C_R0_COLOR); - else - OUT_ACCEL_REG(R200_PP_TXCBLEND_0, R200_TXC_ARG_C_ZERO); - OUT_ACCEL_REG(R200_PP_TXCBLEND2_0, R200_TXC_OUTPUT_REG_R0); - OUT_ACCEL_REG(R200_PP_TXABLEND_0, R200_TXA_ARG_C_R0_ALPHA); - OUT_ACCEL_REG(R200_PP_TXABLEND2_0, R200_TXA_OUTPUT_REG_R0); - OUT_ACCEL_REG(R200_SE_VTX_FMT_0, 0); - OUT_ACCEL_REG(R200_SE_VTX_FMT_1, (2 << R200_VTX_TEX0_COMP_CNT_SHIFT)); - OUT_ACCEL_REG(RADEON_RB3D_BLENDCNTL, blend_cntl); - FINISH_ACCEL(); - - return TRUE; -} - -static void -FUNC_NAME(R200SubsequentCPUToScreenTexture) ( - ScrnInfoPtr pScrn, - int dstx, - int dsty, - int srcx, - int srcy, - int width, - int height -) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - int byteshift; - uint32_t fboffset; - float l, t, r, b, fl, fr, ft, fb; - ACCEL_PREAMBLE(); - - /* Note: we can't simply set up the 3D surface at the same location as the - * front buffer, because the 2048x2048 limit on coordinates may be smaller - * than the (MergedFB) screen. - * Can't use arbitrary offsets for color tiling - */ - if (info->tilingEnabled) { - /* can't play tricks with x coordinate, or could we - tiling is disabled anyway in that case */ - fboffset = info->fbLocation + pScrn->fbOffset + - (pScrn->displayWidth * (dsty & ~15) * (pScrn->bitsPerPixel >> 3)); - l = dstx; - t = (dsty % 16); - } - else { - byteshift = (pScrn->bitsPerPixel >> 4); - fboffset = (info->fbLocation + pScrn->fbOffset + - ((pScrn->displayWidth * dsty + dstx) << byteshift)) & ~15; - l = ((dstx << byteshift) % 16) >> byteshift; - t = 0.0; - } - - r = width + l; - b = height + t; - fl = (float)srcx / info->accel_state->texW[0]; - fr = (float)(srcx + width) / info->accel_state->texW[0]; - ft = (float)srcy / info->accel_state->texH[0]; - fb = (float)(srcy + height) / info->accel_state->texH[0]; - -#ifdef ACCEL_CP - BEGIN_RING(24); - - OUT_ACCEL_REG(RADEON_RB3D_COLORPITCH, pScrn->displayWidth | - ((info->tilingEnabled && (dsty <= pScrn->virtualY)) ? RADEON_COLOR_TILE_ENABLE : 0)); - OUT_ACCEL_REG(RADEON_RB3D_COLOROFFSET, fboffset); - - OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2, 16)); - /* RADEON_SE_VF_CNTL */ - OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN | - RADEON_CP_VC_CNTL_PRIM_WALK_RING | - (4 << RADEON_CP_VC_CNTL_NUM_SHIFT)); - - OUT_RING(F_TO_DW(l)); - OUT_RING(F_TO_DW(t)); - OUT_RING(F_TO_DW(fl)); - OUT_RING(F_TO_DW(ft)); - - OUT_RING(F_TO_DW(r)); - OUT_RING(F_TO_DW(t)); - OUT_RING(F_TO_DW(fr)); - OUT_RING(F_TO_DW(ft)); - - OUT_RING(F_TO_DW(r)); - OUT_RING(F_TO_DW(b)); - OUT_RING(F_TO_DW(fr)); - OUT_RING(F_TO_DW(fb)); - - OUT_RING(F_TO_DW(l)); - OUT_RING(F_TO_DW(b)); - OUT_RING(F_TO_DW(fl)); - OUT_RING(F_TO_DW(fb)); - - OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN); - - ADVANCE_RING(); -#else - BEGIN_ACCEL(20); - - /* Note: we can't simply setup 3D surface at the same location as the front buffer, - some apps may draw offscreen pictures out of the limitation of radeon 3D surface. - */ - OUT_ACCEL_REG(RADEON_RB3D_COLORPITCH, pScrn->displayWidth | - ((info->tilingEnabled && (dsty <= pScrn->virtualY)) ? RADEON_COLOR_TILE_ENABLE : 0)); - OUT_ACCEL_REG(RADEON_RB3D_COLOROFFSET, fboffset); - - OUT_ACCEL_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_QUAD_LIST | - RADEON_VF_PRIM_WALK_DATA | - 4 << RADEON_VF_NUM_VERTICES_SHIFT)); - - OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(l)); - OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(t)); - OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(fl)); - OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(ft)); - - OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(r)); - OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(t)); - OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(fr)); - OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(ft)); - - OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(r)); - OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(b)); - OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(fr)); - OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(fb)); - - OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(l)); - OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(b)); - OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(fl)); - OUT_ACCEL_REG(RADEON_SE_PORT_DATA0, F_TO_DW(fb)); - - OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN); - - FINISH_ACCEL(); -#endif -} - -#undef FUNC_NAME -#endif /* USE_XAA */ diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c index 48564f82..d98b68db 100644 --- a/src/radeon_textured_video.c +++ b/src/radeon_textured_video.c @@ -46,16 +46,9 @@ extern void R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv); -#ifdef XF86DRM_MODE extern void EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv); -#endif -extern Bool -R600CopyToVRAM(ScrnInfoPtr pScrn, - char *src, int src_pitch, - uint32_t dst_pitch, uint32_t dst_mc_addr, uint32_t dst_width, uint32_t dst_height, int bpp, - int x, int y, int w, int h); #define IMAGE_MAX_WIDTH 2048 #define IMAGE_MAX_HEIGHT 2048 @@ -72,22 +65,7 @@ R600CopyToVRAM(ScrnInfoPtr pScrn, static Bool RADEONTilingEnabled(ScrnInfoPtr pScrn, PixmapPtr pPix) { - RADEONInfoPtr info = RADEONPTR(pScrn); - -#ifdef USE_EXA - if (info->useEXA) { - if (info->tilingEnabled && exaGetPixmapOffset(pPix) == 0) - return TRUE; - else - return FALSE; - } else -#endif - { - if (info->tilingEnabled && ((pPix->devPrivate.ptr - info->FB) == 0)) - return TRUE; - else - return FALSE; - } + return FALSE; } static __inline__ uint32_t F_TO_DW(float val) @@ -144,30 +122,9 @@ static REF_TRANSFORM trans[2] = {1.1643, 0.0, 1.7927, -0.2132, -0.5329, 2.1124, 0.0} /* BT.709 */ }; -#define ACCEL_MMIO -#define ACCEL_PREAMBLE() unsigned char *RADEONMMIO = info->MMIO -#define BEGIN_ACCEL(n) RADEONWaitForFifo(pScrn, (n)) -#define OUT_ACCEL_REG(reg, val) OUTREG(reg, val) -#define OUT_ACCEL_REG_F(reg, val) OUTREG(reg, F_TO_DW(val)) -#define OUT_RELOC(x, read, write) do {} while(0) -#define FINISH_ACCEL() - -#include "radeon_textured_videofuncs.c" - -#undef ACCEL_MMIO -#undef ACCEL_PREAMBLE -#undef BEGIN_ACCEL -#undef OUT_ACCEL_REG -#undef OUT_ACCEL_REG_F -#undef OUT_RELOC -#undef FINISH_ACCEL - -#ifdef XF86DRI -#define ACCEL_CP #define ACCEL_PREAMBLE() \ - RING_LOCALS; \ - RADEONCP_REFRESH(pScrn, info) + RING_LOCALS; #define BEGIN_ACCEL(n) BEGIN_RING(2*(n)) #define OUT_ACCEL_REG(reg, val) OUT_RING_REG(reg, val) #define OUT_ACCEL_REG_F(reg, val) OUT_ACCEL_REG(reg, F_TO_DW(val)) @@ -177,7 +134,6 @@ static REF_TRANSFORM trans[2] = #include "radeon_textured_videofuncs.c" -#undef ACCEL_CP #undef ACCEL_PREAMBLE #undef BEGIN_ACCEL #undef OUT_ACCEL_REG @@ -185,8 +141,6 @@ static REF_TRANSFORM trans[2] = #undef FINISH_ACCEL #undef OUT_RING_F -#endif /* XF86DRI */ - static void R600CopyData( ScrnInfoPtr pScrn, @@ -198,29 +152,18 @@ R600CopyData( unsigned int w, unsigned int cpp ){ - RADEONInfoPtr info = RADEONPTR( pScrn ); - if (cpp == 2) { w *= 2; cpp = 1; } - if (info->DMAForXv) { - uint32_t dst_mc_addr = dst - (unsigned char *)info->FB + info->fbLocation; - - R600CopyToVRAM(pScrn, - (char *)src, srcPitch, - dstPitch, dst_mc_addr, w, h, cpp * 8, - 0, 0, w, h); - } else { - if (srcPitch == dstPitch) - memcpy(dst, src, srcPitch * h); - else { - while (h--) { - memcpy(dst, src, srcPitch); - src += srcPitch; - dst += dstPitch; - } + if (srcPitch == dstPitch) + memcpy(dst, src, srcPitch * h); + else { + while (h--) { + memcpy(dst, src, srcPitch); + src += srcPitch; + dst += dstPitch; } } } @@ -251,11 +194,10 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, BoxRec dstBox; int dst_width = width, dst_height = height; int aligned_height; -#ifdef XF86DRM_MODE int h_align = drmmode_get_height_align(pScrn, 0); -#else - int h_align = 1; -#endif + struct radeon_bo *src_bo; + int ret; + /* make the compiler happy */ s2offset = s3offset = srcPitch2 = 0; @@ -291,20 +233,10 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, pPriv->bicubic_enabled = FALSE; } -#ifdef XF86DRM_MODE - if (info->cs) { - if (info->ChipFamily >= CHIP_FAMILY_R600) - pPriv->hw_align = drmmode_get_base_align(pScrn, 2, 0); - else - pPriv->hw_align = 64; - } else -#endif - { - if (info->ChipFamily >= CHIP_FAMILY_R600) - pPriv->hw_align = 256; - else - pPriv->hw_align = 64; - } + if (info->ChipFamily >= CHIP_FAMILY_R600) + pPriv->hw_align = drmmode_get_base_align(pScrn, 2, 0); + else + pPriv->hw_align = 64; aligned_height = RADEON_ALIGN(dst_height, h_align); @@ -345,12 +277,10 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, if (pPriv->video_offset == 0) return BadAlloc; - if (info->cs) { - pPriv->src_bo[0] = pPriv->video_memory; - radeon_legacy_allocate_memory(pScrn, (void*)&pPriv->src_bo[1], size, - pPriv->hw_align, - RADEON_GEM_DOMAIN_GTT); - } + pPriv->src_bo[0] = pPriv->video_memory; + radeon_legacy_allocate_memory(pScrn, (void*)&pPriv->src_bo[1], size, + pPriv->hw_align, + RADEON_GEM_DOMAIN_GTT); } /* Bicubic filter loading */ @@ -365,47 +295,26 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, else pPriv->pPixmap = (PixmapPtr)pDraw; -#ifdef USE_EXA - if (info->useEXA) { - /* Force the pixmap into framebuffer so we can draw to it. */ - info->exa_force_create = TRUE; - exaMoveInPixmap(pPriv->pPixmap); - info->exa_force_create = FALSE; - } -#endif - - if (!info->useEXA && - (((char *)pPriv->pPixmap->devPrivate.ptr < (char *)info->FB) || - ((char *)pPriv->pPixmap->devPrivate.ptr >= (char *)info->FB + - info->FbMapSize))) { - /* If the pixmap wasn't in framebuffer, then we have no way in XAA to - * force it there. So, we simply refuse to draw and fail. - */ - return BadAlloc; - } + /* Force the pixmap into framebuffer so we can draw to it. */ + info->exa_force_create = TRUE; + exaMoveInPixmap(pPriv->pPixmap); + info->exa_force_create = FALSE; /* copy data */ top = (y1 >> 16) & ~1; nlines = ((y2 + 0xffff) >> 16) - top; pPriv->src_offset = pPriv->video_offset; - if (info->cs) { - struct radeon_bo *src_bo; - int ret; - - pPriv->currentBuffer ^= 1; + + pPriv->currentBuffer ^= 1; + + src_bo = pPriv->src_bo[pPriv->currentBuffer]; - src_bo = pPriv->src_bo[pPriv->currentBuffer]; - - ret = radeon_bo_map(src_bo, 1); - if (ret) - return BadAlloc; - - pPriv->src_addr = src_bo->ptr; - } else { - pPriv->src_addr = (uint8_t *)(info->FB + pPriv->video_offset); - RADEONWaitForIdleMMIO(pScrn); - } + ret = radeon_bo_map(src_bo, 1); + if (ret) + return BadAlloc; + + pPriv->src_addr = src_bo->ptr; pPriv->src_pitch = dstPitch; pPriv->planeu_offset = dstPitch * aligned_height; @@ -489,18 +398,11 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, pPriv->w = width; pPriv->h = height; -#if defined(XF86DRM_MODE) - if (info->cs) - radeon_bo_unmap(pPriv->src_bo[pPriv->currentBuffer]); -#endif -#ifdef XF86DRI + radeon_bo_unmap(pPriv->src_bo[pPriv->currentBuffer]); if (info->directRenderingEnabled) { -#ifdef XF86DRM_MODE if (IS_EVERGREEN_3D) EVERGREENDisplayTexturedVideo(pScrn, pPriv); - else -#endif - if (IS_R600_3D) + else if (IS_R600_3D) R600DisplayTexturedVideo(pScrn, pPriv); else if (IS_R500_3D) R500DisplayTexturedVideoCP(pScrn, pPriv); @@ -510,17 +412,6 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, R200DisplayTexturedVideoCP(pScrn, pPriv); else RADEONDisplayTexturedVideoCP(pScrn, pPriv); - } else -#endif - { - if (IS_R500_3D) - R500DisplayTexturedVideoMMIO(pScrn, pPriv); - else if (IS_R300_3D) - R300DisplayTexturedVideoMMIO(pScrn, pPriv); - else if (IS_R200_3D) - R200DisplayTexturedVideoMMIO(pScrn, pPriv); - else - RADEONDisplayTexturedVideoMMIO(pScrn, pPriv); } return Success; @@ -765,21 +656,17 @@ Bool radeon_load_bicubic_texture(ScrnInfoPtr pScrn) if (info->bicubic_offset == 0) return FALSE; - if (info->cs) - info->bicubic_bo = info->bicubic_memory; + info->bicubic_bo = info->bicubic_memory; /* Upload bicubic filter tex */ if (info->ChipFamily < CHIP_FAMILY_R600) { uint8_t *bicubic_addr; int ret; - if (info->cs) { - ret = radeon_bo_map(info->bicubic_bo, 1); - if (ret) - return FALSE; + ret = radeon_bo_map(info->bicubic_bo, 1); + if (ret) + return FALSE; - bicubic_addr = info->bicubic_bo->ptr; - } else - bicubic_addr = (uint8_t *)(info->FB + info->bicubic_offset); + bicubic_addr = info->bicubic_bo->ptr; RADEONCopySwap(bicubic_addr, (uint8_t *)bicubic_tex_512, 1024, #if X_BYTE_ORDER == X_BIG_ENDIAN @@ -788,8 +675,7 @@ Bool radeon_load_bicubic_texture(ScrnInfoPtr pScrn) RADEON_HOST_DATA_SWAP_NONE #endif ); - if (info->cs) - radeon_bo_unmap(info->bicubic_bo); + radeon_bo_unmap(info->bicubic_bo); } return TRUE; } @@ -895,9 +781,6 @@ RADEONSetupImageTexturedVideo(ScreenPtr pScreen) RADEONPortPrivPtr pPriv = &pPortPriv[i]; pPriv->textured = TRUE; - pPriv->videoStatus = 0; - pPriv->currentBuffer = 0; - pPriv->doubleBuffer = 0; pPriv->bicubic_state = BICUBIC_OFF; pPriv->vsync = TRUE; pPriv->brightness = 0; diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c index 71195530..061fe961 100644 --- a/src/radeon_textured_videofuncs.c +++ b/src/radeon_textured_videofuncs.c @@ -25,9 +25,6 @@ * */ -#if defined(ACCEL_MMIO) && defined(ACCEL_CP) -#error Cannot define both MMIO and CP acceleration! -#endif #if !defined(UNIXCPP) || defined(ANSICPP) #define FUNC_NAME_CAT(prefix,suffix) prefix##suffix @@ -35,17 +32,7 @@ #define FUNC_NAME_CAT(prefix,suffix) prefix/**/suffix #endif -#ifdef ACCEL_MMIO -#define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,MMIO) -#else -#ifdef ACCEL_CP #define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,CP) -#else -#error No accel type defined! -#endif -#endif - -#ifdef ACCEL_CP #define VTX_OUT_6(_dstX, _dstY, _srcX, _srcY, _maskX, _maskY) \ do { \ @@ -65,27 +52,6 @@ do { \ OUT_RING_F(_srcY); \ } while (0) -#else /* ACCEL_CP */ - -#define VTX_OUT_6(_dstX, _dstY, _srcX, _srcY, _maskX, _maskY) \ -do { \ - OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _dstX); \ - OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _dstY); \ - OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _srcX); \ - OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _srcY); \ - OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _maskX); \ - OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _maskY); \ -} while (0) - -#define VTX_OUT_4(_dstX, _dstY, _srcX, _srcY) \ -do { \ - OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _dstX); \ - OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _dstY); \ - OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _srcX); \ - OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _srcY); \ -} while (0) - -#endif /* !ACCEL_CP */ static Bool FUNC_NAME(RADEONPrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) @@ -100,62 +66,28 @@ FUNC_NAME(RADEONPrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv int pixel_shift; int scissor_w = MIN(pPixmap->drawable.width, 2047); int scissor_h = MIN(pPixmap->drawable.height, 2047); + int ret; ACCEL_PREAMBLE(); -#ifdef XF86DRM_MODE - if (info->cs) { - int ret; + radeon_cs_space_reset_bos(info->cs); + radeon_cs_space_add_persistent_bo(info->cs, src_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); - radeon_cs_space_reset_bos(info->cs); - radeon_cs_space_add_persistent_bo(info->cs, src_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); - - if (pPriv->bicubic_enabled) - radeon_cs_space_add_persistent_bo(info->cs, info->bicubic_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); + if (pPriv->bicubic_enabled) + radeon_cs_space_add_persistent_bo(info->cs, info->bicubic_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); - driver_priv = exaGetPixmapDriverPrivate(pPixmap); - radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM); + driver_priv = exaGetPixmapDriverPrivate(pPixmap); + radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM); - ret = radeon_cs_space_check(info->cs); - if (ret) { - ErrorF("Not enough RAM to hw accel xv operation\n"); - return FALSE; - } + ret = radeon_cs_space_check(info->cs); + if (ret) { + ErrorF("Not enough RAM to hw accel xv operation\n"); + return FALSE; } -#else - (void)src_bo; -#endif pixel_shift = pPixmap->drawable.bitsPerPixel >> 4; - -#ifdef USE_EXA - if (info->useEXA) { - dst_pitch = exaGetPixmapPitch(pPixmap); - } else -#endif - { - dst_pitch = pPixmap->devKind; - } - -#ifdef USE_EXA - if (info->useEXA) { - RADEON_SWITCH_TO_3D(); - } else -#endif - { - BEGIN_ACCEL(2); - OUT_ACCEL_REG(RADEON_RB3D_DSTCACHE_CTLSTAT, RADEON_RB3D_DC_FLUSH); - /* We must wait for 3d to idle, in case source was just written as a dest. */ - OUT_ACCEL_REG(RADEON_WAIT_UNTIL, - RADEON_WAIT_HOST_IDLECLEAN | - RADEON_WAIT_2D_IDLECLEAN | - RADEON_WAIT_3D_IDLECLEAN | - RADEON_WAIT_DMA_GUI_IDLE); - FINISH_ACCEL(); - - if (!info->accel_state->XInited3D) - RADEONInit3DEngine(pScrn); - } + dst_pitch = exaGetPixmapPitch(pPixmap); + RADEON_SWITCH_TO_3D(); /* Same for R100/R200 */ switch (pPixmap->drawable.bitsPerPixel) { @@ -190,7 +122,7 @@ FUNC_NAME(RADEONPrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv if (RADEONTilingEnabled(pScrn, pPixmap)) colorpitch |= RADEON_COLOR_TILE_ENABLE; - txoffset = info->cs ? 0 : pPriv->src_offset; + txoffset = 0; BEGIN_ACCEL_RELOC(4,2); @@ -404,16 +336,12 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv * the single triangle up to 2560/4021 pixels; above that we * render as a quad. */ -#ifdef ACCEL_CP while (nBox) { int draw_size = 3 * pPriv->vtx_count + 5; int loop_boxes; if (draw_size > radeon_cs_space_remaining(pScrn)) { - if (info->cs) - radeon_cs_flush_indirect(pScrn); - else - RADEONCPFlushIndirect(pScrn, 1); + radeon_cs_flush_indirect(pScrn); if (!FUNC_NAME(RADEONPrepareTexturedVideo)(pScrn, pPriv)) return; } @@ -486,63 +414,6 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN); ADVANCE_RING(); } -#else /* ACCEL_CP */ - BEGIN_ACCEL(nBox * pPriv->vtx_count * 3 + 2); - OUT_ACCEL_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_RECTANGLE_LIST | - RADEON_VF_PRIM_WALK_DATA | - RADEON_VF_RADEON_MODE | - ((nBox * 3) << RADEON_VF_NUM_VERTICES_SHIFT))); - while (nBox--) { - float srcX, srcY, srcw, srch; - int dstX, dstY, dstw, dsth; - dstX = pBox->x1 + dstxoff; - dstY = pBox->y1 + dstyoff; - dstw = pBox->x2 - pBox->x1; - dsth = pBox->y2 - pBox->y1; - - srcX = pPriv->src_x; - srcX += ((pBox->x1 - pPriv->drw_x) * - pPriv->src_w) / (float)pPriv->dst_w; - srcY = pPriv->src_y; - srcY += ((pBox->y1 - pPriv->drw_y) * - pPriv->src_h) / (float)pPriv->dst_h; - - srcw = (pPriv->src_w * dstw) / (float)pPriv->dst_w; - srch = (pPriv->src_h * dsth) / (float)pPriv->dst_h; - - - if (pPriv->is_planar) { - /* - * Just render a rect (using three coords). - */ - VTX_OUT_6((float)dstX, (float)(dstY + dsth), - (float)srcX / pPriv->w, (float)(srcY + srch) / pPriv->h, - (float)srcX / pPriv->w, (float)(srcY + srch) / pPriv->h); - VTX_OUT_6((float)(dstX + dstw), (float)(dstY + dsth), - (float)(srcX + srcw) / pPriv->w, (float)(srcY + srch) / pPriv->h, - (float)(srcX + srcw) / pPriv->w, (float)(srcY + srch) / pPriv->h); - VTX_OUT_6((float)(dstX + dstw), (float)dstY, - (float)(srcX + srcw) / pPriv->w, (float)srcY / pPriv->h, - (float)(srcX + srcw) / pPriv->w, (float)srcY / pPriv->h); - } else { - /* - * Just render a rect (using three coords). - */ - VTX_OUT_4((float)dstX, (float)(dstY + dsth), - (float)srcX / pPriv->w, (float)(srcY + srch) / pPriv->h); - VTX_OUT_4((float)(dstX + dstw), (float)(dstY + dsth), - (float)(srcX + srcw) / pPriv->w, (float)(srcY + srch) / pPriv->h); - VTX_OUT_4((float)(dstX + dstw), (float)dstY, - (float)(srcX + srcw) / pPriv->w, (float)srcY / pPriv->h); - } - - pBox++; - } - - OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN); - FINISH_ACCEL(); -#endif /* !ACCEL_CP */ - DamageDamageRegion(pPriv->pDraw, &pPriv->clip); } @@ -569,61 +440,29 @@ FUNC_NAME(R200PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) int ref = pPriv->transform_index; float ucscale = 0.25, vcscale = 0.25; Bool needux8 = FALSE, needvx8 = FALSE; + int ret; ACCEL_PREAMBLE(); -#ifdef XF86DRM_MODE - if (info->cs) { - int ret; - - radeon_cs_space_reset_bos(info->cs); - radeon_cs_space_add_persistent_bo(info->cs, src_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); + radeon_cs_space_reset_bos(info->cs); + radeon_cs_space_add_persistent_bo(info->cs, src_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); - if (pPriv->bicubic_enabled) - radeon_cs_space_add_persistent_bo(info->cs, info->bicubic_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); + if (pPriv->bicubic_enabled) + radeon_cs_space_add_persistent_bo(info->cs, info->bicubic_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); - driver_priv = exaGetPixmapDriverPrivate(pPixmap); - radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM); + driver_priv = exaGetPixmapDriverPrivate(pPixmap); + radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM); - ret = radeon_cs_space_check(info->cs); - if (ret) { - ErrorF("Not enough RAM to hw accel xv operation\n"); - return FALSE; - } + ret = radeon_cs_space_check(info->cs); + if (ret) { + ErrorF("Not enough RAM to hw accel xv operation\n"); + return FALSE; } -#else - (void)src_bo; -#endif pixel_shift = pPixmap->drawable.bitsPerPixel >> 4; -#ifdef USE_EXA - if (info->useEXA) { - dst_pitch = exaGetPixmapPitch(pPixmap); - } else -#endif - { - dst_pitch = pPixmap->devKind; - } + dst_pitch = exaGetPixmapPitch(pPixmap); -#ifdef USE_EXA - if (info->useEXA) { - RADEON_SWITCH_TO_3D(); - } else -#endif - { - BEGIN_ACCEL(2); - OUT_ACCEL_REG(RADEON_RB3D_DSTCACHE_CTLSTAT, RADEON_RB3D_DC_FLUSH); - /* We must wait for 3d to idle, in case source was just written as a dest. */ - OUT_ACCEL_REG(RADEON_WAIT_UNTIL, - RADEON_WAIT_HOST_IDLECLEAN | - RADEON_WAIT_2D_IDLECLEAN | - RADEON_WAIT_3D_IDLECLEAN | - RADEON_WAIT_DMA_GUI_IDLE); - FINISH_ACCEL(); - - if (!info->accel_state->XInited3D) - RADEONInit3DEngine(pScrn); - } + RADEON_SWITCH_TO_3D(); /* Same for R100/R200 */ switch (pPixmap->drawable.bitsPerPixel) { @@ -705,7 +544,7 @@ FUNC_NAME(R200PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) vcscale = 0.125; } - txoffset = info->cs ? 0 : pPriv->src_offset; + txoffset = 0; if (pPriv->is_planar) { /* need 2 texcoord sets (even though they are identical) due @@ -1046,16 +885,12 @@ FUNC_NAME(R200DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) * render as a quad. */ -#ifdef ACCEL_CP while (nBox) { int draw_size = 3 * pPriv->vtx_count + 4; int loop_boxes; if (draw_size > radeon_cs_space_remaining(pScrn)) { - if (info->cs) - radeon_cs_flush_indirect(pScrn); - else - RADEONCPFlushIndirect(pScrn, 1); + radeon_cs_flush_indirect(pScrn); if (!FUNC_NAME(R200PrepareTexturedVideo)(pScrn, pPriv)) return; } @@ -1118,60 +953,6 @@ FUNC_NAME(R200DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN); ADVANCE_RING(); } -#else /* ACCEL_CP */ - BEGIN_ACCEL(nBox * 3 * pPriv->vtx_count + 2); - OUT_ACCEL_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_RECTANGLE_LIST | - RADEON_VF_PRIM_WALK_DATA | - ((nBox * 3) << RADEON_VF_NUM_VERTICES_SHIFT))); - while (nBox--) { - float srcX, srcY, srcw, srch; - int dstX, dstY, dstw, dsth; - dstX = pBox->x1 + dstxoff; - dstY = pBox->y1 + dstyoff; - dstw = pBox->x2 - pBox->x1; - dsth = pBox->y2 - pBox->y1; - - srcX = pPriv->src_x; - srcX += ((pBox->x1 - pPriv->drw_x) * - pPriv->src_w) / (float)pPriv->dst_w; - srcY = pPriv->src_y; - srcY += ((pBox->y1 - pPriv->drw_y) * - pPriv->src_h) / (float)pPriv->dst_h; - - srcw = (pPriv->src_w * dstw) / (float)pPriv->dst_w; - srch = (pPriv->src_h * dsth) / (float)pPriv->dst_h; - - if (pPriv->is_planar) { - /* - * Just render a rect (using three coords). - */ - VTX_OUT_6((float)dstX, (float)(dstY + dsth), - (float)srcX / pPriv->w, (float)(srcY + srch) / pPriv->h, - (float)srcX / pPriv->w, (float)(srcY + srch) / pPriv->h); - VTX_OUT_6((float)(dstX + dstw), (float)(dstY + dsth), - (float)(srcX + srcw) / pPriv->w, (float)(srcY + srch) / pPriv->h, - (float)(srcX + srcw) / pPriv->w, (float)(srcY + srch) / pPriv->h); - VTX_OUT_6((float)(dstX + dstw), (float)dstY, - (float)(srcX + srcw) / pPriv->w, (float)srcY / pPriv->h, - (float)(srcX + srcw) / pPriv->w, (float)srcY / pPriv->h); - } else { - /* - * Just render a rect (using three coords). - */ - VTX_OUT_4((float)dstX, (float)(dstY + dsth), - (float)srcX / pPriv->w, (float)(srcY + srch) / pPriv->h); - VTX_OUT_4((float)(dstX + dstw), (float)(dstY + dsth), - (float)(srcX + srcw) / pPriv->w, (float)(srcY + srch) / pPriv->h); - VTX_OUT_4((float)(dstX + dstw), (float)dstY, - (float)(srcX + srcw) / pPriv->w, (float)srcY / pPriv->h); - } - - pBox++; - } - - OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN); - FINISH_ACCEL(); -#endif /* !ACCEL_CP */ DamageDamageRegion(pPriv->pDraw, &pPriv->clip); } @@ -1188,61 +969,28 @@ FUNC_NAME(R300PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) uint32_t txenable, colorpitch, bicubic_offset; uint32_t output_fmt; int pixel_shift; + int ret; ACCEL_PREAMBLE(); -#ifdef XF86DRM_MODE - if (info->cs) { - int ret; + radeon_cs_space_reset_bos(info->cs); + radeon_cs_space_add_persistent_bo(info->cs, src_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); - radeon_cs_space_reset_bos(info->cs); - radeon_cs_space_add_persistent_bo(info->cs, src_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); - - if (pPriv->bicubic_enabled) - radeon_cs_space_add_persistent_bo(info->cs, info->bicubic_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); + if (pPriv->bicubic_enabled) + radeon_cs_space_add_persistent_bo(info->cs, info->bicubic_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); - driver_priv = exaGetPixmapDriverPrivate(pPixmap); - radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM); + driver_priv = exaGetPixmapDriverPrivate(pPixmap); + radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM); - ret = radeon_cs_space_check(info->cs); - if (ret) { - ErrorF("Not enough RAM to hw accel xv operation\n"); - return FALSE; - } + ret = radeon_cs_space_check(info->cs); + if (ret) { + ErrorF("Not enough RAM to hw accel xv operation\n"); + return FALSE; } -#else - (void)src_bo; -#endif pixel_shift = pPixmap->drawable.bitsPerPixel >> 4; -#ifdef USE_EXA - if (info->useEXA) { - dst_pitch = exaGetPixmapPitch(pPixmap); - } else -#endif - { - dst_pitch = pPixmap->devKind; - } - -#ifdef USE_EXA - if (info->useEXA) { - RADEON_SWITCH_TO_3D(); - } else -#endif - { - BEGIN_ACCEL(2); - OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D); - /* We must wait for 3d to idle, in case source was just written as a dest. */ - OUT_ACCEL_REG(RADEON_WAIT_UNTIL, - RADEON_WAIT_HOST_IDLECLEAN | - RADEON_WAIT_2D_IDLECLEAN | - RADEON_WAIT_3D_IDLECLEAN | - RADEON_WAIT_DMA_GUI_IDLE); - FINISH_ACCEL(); - - if (!info->accel_state->XInited3D) - RADEONInit3DEngine(pScrn); - } + dst_pitch = exaGetPixmapPitch(pPixmap); + RADEON_SWITCH_TO_3D(); if (pPriv->bicubic_enabled) pPriv->vtx_count = 6; @@ -1309,7 +1057,7 @@ FUNC_NAME(R300PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) R300_TX_MIN_FILTER_LINEAR | (0 << R300_TX_ID_SHIFT)); - txoffset = info->cs ? 0 : pPriv->src_offset; + txoffset = 0; BEGIN_ACCEL_RELOC(6, 1); OUT_ACCEL_REG(R300_TX_FILTER0_0, txfilter); @@ -1369,10 +1117,7 @@ FUNC_NAME(R300PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) R300_TX_MAG_FILTER_NEAREST | (1 << R300_TX_ID_SHIFT)); - if (info->cs) - bicubic_offset = 0; - else - bicubic_offset = pPriv->bicubic_src_offset; + bicubic_offset = 0; BEGIN_ACCEL_RELOC(6, 1); OUT_ACCEL_REG(R300_TX_FILTER0_1, txfilter); @@ -2502,18 +2247,13 @@ FUNC_NAME(R300DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) float srcX, srcY, srcw, srch; int dstX, dstY, dstw, dsth; Bool use_quad = FALSE; -#ifdef ACCEL_CP int draw_size = 4 * pPriv->vtx_count + 4 + 2 + 3; if (draw_size > radeon_cs_space_remaining(pScrn)) { - if (info->cs) - radeon_cs_flush_indirect(pScrn); - else - RADEONCPFlushIndirect(pScrn, 1); + radeon_cs_flush_indirect(pScrn); if (!FUNC_NAME(R300PrepareTexturedVideo)(pScrn, pPriv)) return; } -#endif dstX = pBox->x1 + dstxoff; dstY = pBox->y1 + dstyoff; @@ -2548,7 +2288,6 @@ FUNC_NAME(R300DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) ((dstY + dsth + 1440 - 1) << R300_SCISSOR_Y_SHIFT))); FINISH_ACCEL(); -#ifdef ACCEL_CP if (use_quad) { BEGIN_RING(4 * pPriv->vtx_count + 4); OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2, @@ -2564,21 +2303,7 @@ FUNC_NAME(R300DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) RADEON_CP_VC_CNTL_PRIM_WALK_RING | (3 << RADEON_CP_VC_CNTL_NUM_SHIFT)); } -#else /* ACCEL_CP */ - if (use_quad) - BEGIN_ACCEL(2 + pPriv->vtx_count * 4); - else - BEGIN_ACCEL(2 + pPriv->vtx_count * 3); - if (use_quad) - OUT_ACCEL_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_QUAD_LIST | - RADEON_VF_PRIM_WALK_DATA | - (4 << RADEON_VF_NUM_VERTICES_SHIFT))); - else - OUT_ACCEL_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_TRIANGLE_LIST | - RADEON_VF_PRIM_WALK_DATA | - (3 << RADEON_VF_NUM_VERTICES_SHIFT))); -#endif if (pPriv->bicubic_enabled) { /* * This code is only executed on >= R300, so we don't @@ -2642,11 +2367,7 @@ FUNC_NAME(R300DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) /* flushing is pipelined, free/finish is not */ OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D); -#ifdef ACCEL_CP ADVANCE_RING(); -#else - FINISH_ACCEL(); -#endif /* !ACCEL_CP */ pBox++; } @@ -2672,61 +2393,28 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) uint32_t txenable, colorpitch, bicubic_offset; uint32_t output_fmt; int pixel_shift, out_size = 6; + int ret; ACCEL_PREAMBLE(); -#ifdef XF86DRM_MODE - if (info->cs) { - int ret; - - radeon_cs_space_reset_bos(info->cs); - radeon_cs_space_add_persistent_bo(info->cs, src_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); + radeon_cs_space_reset_bos(info->cs); + radeon_cs_space_add_persistent_bo(info->cs, src_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); - if (pPriv->bicubic_enabled) - radeon_cs_space_add_persistent_bo(info->cs, info->bicubic_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); - - driver_priv = exaGetPixmapDriverPrivate(pPixmap); - radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM); - - ret = radeon_cs_space_check(info->cs); - if (ret) { - ErrorF("Not enough RAM to hw accel xv operation\n"); - return FALSE; - } + if (pPriv->bicubic_enabled) + radeon_cs_space_add_persistent_bo(info->cs, info->bicubic_bo, RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); + + driver_priv = exaGetPixmapDriverPrivate(pPixmap); + radeon_cs_space_add_persistent_bo(info->cs, driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM); + + ret = radeon_cs_space_check(info->cs); + if (ret) { + ErrorF("Not enough RAM to hw accel xv operation\n"); + return FALSE; } -#else - (void)src_bo; -#endif pixel_shift = pPixmap->drawable.bitsPerPixel >> 4; -#ifdef USE_EXA - if (info->useEXA) { - dst_pitch = exaGetPixmapPitch(pPixmap); - } else -#endif - { - dst_pitch = pPixmap->devKind; - } - -#ifdef USE_EXA - if (info->useEXA) { - RADEON_SWITCH_TO_3D(); - } else -#endif - { - BEGIN_ACCEL(2); - OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D); - /* We must wait for 3d to idle, in case source was just written as a dest. */ - OUT_ACCEL_REG(RADEON_WAIT_UNTIL, - RADEON_WAIT_HOST_IDLECLEAN | - RADEON_WAIT_2D_IDLECLEAN | - RADEON_WAIT_3D_IDLECLEAN | - RADEON_WAIT_DMA_GUI_IDLE); - FINISH_ACCEL(); - - if (!info->accel_state->XInited3D) - RADEONInit3DEngine(pScrn); - } + dst_pitch = exaGetPixmapPitch(pPixmap); + RADEON_SWITCH_TO_3D(); if (pPriv->bicubic_enabled) pPriv->vtx_count = 6; @@ -2818,7 +2506,7 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) out_size++; } - txoffset = info->cs ? 0 : pPriv->src_offset; + txoffset = 0; BEGIN_ACCEL_RELOC(out_size, 1); OUT_ACCEL_REG(R300_TX_FILTER0_0, txfilter); @@ -2877,10 +2565,7 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) R300_TX_MAG_FILTER_NEAREST | (1 << R300_TX_ID_SHIFT)); - if (info->cs) - bicubic_offset = 0; - else - bicubic_offset = pPriv->bicubic_src_offset; + bicubic_offset = 0; BEGIN_ACCEL_RELOC(6, 1); OUT_ACCEL_REG(R300_TX_FILTER0_1, txfilter); @@ -4132,18 +3817,13 @@ FUNC_NAME(R500DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) while (nBox--) { float srcX, srcY, srcw, srch; int dstX, dstY, dstw, dsth; -#ifdef ACCEL_CP int draw_size = 3 * pPriv->vtx_count + 4 + 2 + 3; if (draw_size > radeon_cs_space_remaining(pScrn)) { - if (info->cs) - radeon_cs_flush_indirect(pScrn); - else - RADEONCPFlushIndirect(pScrn, 1); + radeon_cs_flush_indirect(pScrn); if (!FUNC_NAME(R500PrepareTexturedVideo)(pScrn, pPriv)) return; } -#endif dstX = pBox->x1 + dstxoff; dstY = pBox->y1 + dstyoff; @@ -4167,19 +3847,13 @@ FUNC_NAME(R500DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) ((dstY + dsth - 1) << R300_SCISSOR_Y_SHIFT))); FINISH_ACCEL(); -#ifdef ACCEL_CP BEGIN_RING(3 * pPriv->vtx_count + 4); OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2, 3 * pPriv->vtx_count)); OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST | RADEON_CP_VC_CNTL_PRIM_WALK_RING | (3 << RADEON_CP_VC_CNTL_NUM_SHIFT)); -#else /* ACCEL_CP */ - BEGIN_ACCEL(2 + pPriv->vtx_count * 3); - OUT_ACCEL_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_TRIANGLE_LIST | - RADEON_VF_PRIM_WALK_DATA | - (3 << RADEON_VF_NUM_VERTICES_SHIFT))); -#endif + if (pPriv->bicubic_enabled) { VTX_OUT_6((float)dstX, (float)dstY, (float)srcX / pPriv->w, (float)srcY / pPriv->h, @@ -4210,11 +3884,7 @@ FUNC_NAME(R500DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) /* flushing is pipelined, free/finish is not */ OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D); -#ifdef ACCEL_CP ADVANCE_RING(); -#else - FINISH_ACCEL(); -#endif /* !ACCEL_CP */ pBox++; } diff --git a/src/radeon_tv.c b/src/radeon_tv.c deleted file mode 100644 index 74c82db8..00000000 --- a/src/radeon_tv.c +++ /dev/null @@ -1,1283 +0,0 @@ -/* - * Integrated TV out support based on the GATOS code by - * Federico Ulivi <fulivi@lycos.com> - */ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include <string.h> -#include <stdio.h> - -/* X and server generic header files */ -#include "xf86.h" -#include "xf86_OSproc.h" -#include "vgaHW.h" -#include "xf86Modes.h" - -/* Driver data structures */ -#include "radeon.h" -#include "radeon_reg.h" -#include "radeon_macros.h" -#include "radeon_probe.h" -#include "radeon_version.h" -#include "radeon_tv.h" -#include "radeon_atombios.h" - -/********************************************************************** - * - * ModeConstants - * - * Storage of constants related to a single video mode - * - **********************************************************************/ - -typedef struct -{ - uint16_t horResolution; - uint16_t verResolution; - TVStd standard; - uint16_t horTotal; - uint16_t verTotal; - uint16_t horStart; - uint16_t horSyncStart; - uint16_t verSyncStart; - unsigned defRestart; - uint16_t crtcPLL_N; - uint8_t crtcPLL_M; - uint8_t crtcPLL_postDiv; - unsigned pixToTV; -} TVModeConstants; - -static const uint16_t hor_timing_NTSC[] = -{ - 0x0007, - 0x003f, - 0x0263, - 0x0a24, - 0x2a6b, - 0x0a36, - 0x126d, /* H_TABLE_POS1 */ - 0x1bfe, - 0x1a8f, /* H_TABLE_POS2 */ - 0x1ec7, - 0x3863, - 0x1bfe, - 0x1bfe, - 0x1a2a, - 0x1e95, - 0x0e31, - 0x201b, - 0 -}; - -static const uint16_t vert_timing_NTSC[] = -{ - 0x2001, - 0x200d, - 0x1006, - 0x0c06, - 0x1006, - 0x1818, - 0x21e3, - 0x1006, - 0x0c06, - 0x1006, - 0x1817, - 0x21d4, - 0x0002, - 0 -}; - -static const uint16_t hor_timing_PAL[] = -{ - 0x0007, - 0x0058, - 0x027c, - 0x0a31, - 0x2a77, - 0x0a95, - 0x124f, /* H_TABLE_POS1 */ - 0x1bfe, - 0x1b22, /* H_TABLE_POS2 */ - 0x1ef9, - 0x387c, - 0x1bfe, - 0x1bfe, - 0x1b31, - 0x1eb5, - 0x0e43, - 0x201b, - 0 -}; - -static const uint16_t vert_timing_PAL[] = -{ - 0x2001, - 0x200c, - 0x1005, - 0x0c05, - 0x1005, - 0x1401, - 0x1821, - 0x2240, - 0x1005, - 0x0c05, - 0x1005, - 0x1401, - 0x1822, - 0x2230, - 0x0002, - 0 -}; - -/********************************************************************** - * - * availableModes - * - * Table of all allowed modes for tv output - * - **********************************************************************/ -static const TVModeConstants availableTVModes[] = -{ - { /* NTSC timing for 27 Mhz ref clk */ - 800, /* horResolution */ - 600, /* verResolution */ - TV_STD_NTSC, /* standard */ - 990, /* horTotal */ - 740, /* verTotal */ - 813, /* horStart */ - 824, /* horSyncStart */ - 632, /* verSyncStart */ - 625592, /* defRestart */ - 592, /* crtcPLL_N */ - 91, /* crtcPLL_M */ - 4, /* crtcPLL_postDiv */ - 1022, /* pixToTV */ - }, - { /* PAL timing for 27 Mhz ref clk */ - 800, /* horResolution */ - 600, /* verResolution */ - TV_STD_PAL, /* standard */ - 1144, /* horTotal */ - 706, /* verTotal */ - 812, /* horStart */ - 824, /* horSyncStart */ - 669, /* verSyncStart */ - 696700, /* defRestart */ - 1382, /* crtcPLL_N */ - 231, /* crtcPLL_M */ - 4, /* crtcPLL_postDiv */ - 759, /* pixToTV */ - }, - { /* NTSC timing for 14 Mhz ref clk */ - 800, /* horResolution */ - 600, /* verResolution */ - TV_STD_NTSC, /* standard */ - 1018, /* horTotal */ - 727, /* verTotal */ - 813, /* horStart */ - 840, /* horSyncStart */ - 633, /* verSyncStart */ - 630627, /* defRestart */ - 347, /* crtcPLL_N */ - 14, /* crtcPLL_M */ - 8, /* crtcPLL_postDiv */ - 1022, /* pixToTV */ - }, - { /* PAL timing for 14 Mhz ref clk */ - 800, /* horResolution */ - 600, /* verResolution */ - TV_STD_PAL, /* standard */ - 1131, /* horTotal */ - 742, /* verTotal */ - 813, /* horStart */ - 840, /* horSyncStart */ - 633, /* verSyncStart */ - 708369, /* defRestart */ - 211, /* crtcPLL_N */ - 9, /* crtcPLL_M */ - 8, /* crtcPLL_postDiv */ - 759, /* pixToTV */ - }, -}; - -#define N_AVAILABLE_MODES (sizeof(availableModes) / sizeof(availableModes[ 0 ])) - -static long YCOEF_value[5] = { 2, 2, 0, 4, 0 }; -static long YCOEF_EN_value[5] = { 1, 1, 0, 1, 0 }; -static long SLOPE_value[5] = { 1, 2, 2, 4, 8 }; -static long SLOPE_limit[5] = { 6, 5, 4, 3, 2 }; - - -static void -RADEONWaitPLLLock(ScrnInfoPtr pScrn, unsigned nTests, - unsigned nWaitLoops, unsigned cntThreshold) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - uint32_t savePLLTest; - unsigned i; - unsigned j; - - OUTREG(RADEON_TEST_DEBUG_MUX, (INREG(RADEON_TEST_DEBUG_MUX) & 0xffff60ff) | 0x100); - - savePLLTest = INPLL(pScrn, RADEON_PLL_TEST_CNTL); - - OUTPLL(pScrn, RADEON_PLL_TEST_CNTL, savePLLTest & ~RADEON_PLL_MASK_READ_B); - - /* XXX: these should probably be OUTPLL to avoid various PLL errata */ - - OUTREG8(RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_TEST_CNTL); - - for (i = 0; i < nTests; i++) { - OUTREG8(RADEON_CLOCK_CNTL_DATA + 3, 0); - - for (j = 0; j < nWaitLoops; j++) - if (INREG8(RADEON_CLOCK_CNTL_DATA + 3) >= cntThreshold) - break; - } - - OUTPLL(pScrn, RADEON_PLL_TEST_CNTL, savePLLTest); - - OUTREG(RADEON_TEST_DEBUG_MUX, INREG(RADEON_TEST_DEBUG_MUX) & 0xffffe0ff); -} - -/* Write to TV FIFO RAM */ -static void -RADEONWriteTVFIFO(ScrnInfoPtr pScrn, uint16_t addr, - uint32_t value) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - uint32_t tmp; - int i = 0; - - OUTREG(RADEON_TV_HOST_WRITE_DATA, value); - - OUTREG(RADEON_TV_HOST_RD_WT_CNTL, addr); - OUTREG(RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_HOST_FIFO_WT); - - do { - tmp = INREG(RADEON_TV_HOST_RD_WT_CNTL); - if ((tmp & RADEON_HOST_FIFO_WT_ACK) == 0) - break; - i++; - } - while (i < 10000); - /*while ((tmp & RADEON_HOST_FIFO_WT_ACK) == 0);*/ - - OUTREG(RADEON_TV_HOST_RD_WT_CNTL, 0); -} - -/* Read from TV FIFO RAM */ -static uint32_t -RADEONReadTVFIFO(ScrnInfoPtr pScrn, uint16_t addr) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - uint32_t tmp; - int i = 0; - - OUTREG(RADEON_TV_HOST_RD_WT_CNTL, addr); - OUTREG(RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_HOST_FIFO_RD); - - do { - tmp = INREG(RADEON_TV_HOST_RD_WT_CNTL); - if ((tmp & RADEON_HOST_FIFO_RD_ACK) == 0) - break; - i++; - } - while (i < 10000); - /*while ((tmp & RADEON_HOST_FIFO_RD_ACK) == 0);*/ - - OUTREG(RADEON_TV_HOST_RD_WT_CNTL, 0); - - return INREG(RADEON_TV_HOST_READ_DATA); -} - -/* Get FIFO addresses of horizontal & vertical code timing tables from - * settings of uv_adr register. - */ -static uint16_t -RADEONGetHTimingTablesAddr(uint32_t tv_uv_adr) -{ - uint16_t hTable; - - switch ((tv_uv_adr & RADEON_HCODE_TABLE_SEL_MASK) >> RADEON_HCODE_TABLE_SEL_SHIFT) { - case 0: - hTable = RADEON_TV_MAX_FIFO_ADDR_INTERNAL; - break; - case 1: - hTable = ((tv_uv_adr & RADEON_TABLE1_BOT_ADR_MASK) >> RADEON_TABLE1_BOT_ADR_SHIFT) * 2; - break; - case 2: - hTable = ((tv_uv_adr & RADEON_TABLE3_TOP_ADR_MASK) >> RADEON_TABLE3_TOP_ADR_SHIFT) * 2; - break; - default: - /* Of course, this should never happen */ - hTable = 0; - break; - } - return hTable; -} - -static uint16_t -RADEONGetVTimingTablesAddr(uint32_t tv_uv_adr) -{ - uint16_t vTable; - - switch ((tv_uv_adr & RADEON_VCODE_TABLE_SEL_MASK) >> RADEON_VCODE_TABLE_SEL_SHIFT) { - case 0: - vTable = ((tv_uv_adr & RADEON_MAX_UV_ADR_MASK) >> RADEON_MAX_UV_ADR_SHIFT) * 2 + 1; - break; - case 1: - vTable = ((tv_uv_adr & RADEON_TABLE1_BOT_ADR_MASK) >> RADEON_TABLE1_BOT_ADR_SHIFT) * 2 + 1; - break; - case 2: - vTable = ((tv_uv_adr & RADEON_TABLE3_TOP_ADR_MASK) >> RADEON_TABLE3_TOP_ADR_SHIFT) * 2 + 1; - break; - default: - /* Of course, this should never happen */ - vTable = 0; - break; - } - return vTable; -} - -/* Restore horizontal/vertical timing code tables */ -static void -RADEONRestoreTVTimingTables(ScrnInfoPtr pScrn, RADEONSavePtr restore) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - uint16_t hTable; - uint16_t vTable; - uint32_t tmp; - unsigned i; - - OUTREG(RADEON_TV_UV_ADR, restore->tv_uv_adr); - hTable = RADEONGetHTimingTablesAddr(restore->tv_uv_adr); - vTable = RADEONGetVTimingTablesAddr(restore->tv_uv_adr); - - for (i = 0; i < MAX_H_CODE_TIMING_LEN; i += 2, hTable--) { - tmp = ((uint32_t)restore->h_code_timing[ i ] << 14) | ((uint32_t)restore->h_code_timing[ i + 1 ]); - RADEONWriteTVFIFO(pScrn, hTable, tmp); - if (restore->h_code_timing[ i ] == 0 || restore->h_code_timing[ i + 1 ] == 0) - break; - } - - for (i = 0; i < MAX_V_CODE_TIMING_LEN; i += 2, vTable++) { - tmp = ((uint32_t)restore->v_code_timing[ i + 1 ] << 14) | ((uint32_t)restore->v_code_timing[ i ]); - RADEONWriteTVFIFO(pScrn, vTable, tmp); - if (restore->v_code_timing[ i ] == 0 || restore->v_code_timing[ i + 1 ] == 0) - break; - } -} - -/* restore TV PLLs */ -static void -RADEONRestoreTVPLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore) -{ - - OUTPLLP(pScrn, RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVCLK_SRC_SEL_TVPLL); - OUTPLL(pScrn, RADEON_TV_PLL_CNTL, restore->tv_pll_cntl); - OUTPLLP(pScrn, RADEON_TV_PLL_CNTL1, RADEON_TVPLL_RESET, ~RADEON_TVPLL_RESET); - - RADEONWaitPLLLock(pScrn, 200, 800, 135); - - OUTPLLP(pScrn, RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_RESET); - - RADEONWaitPLLLock(pScrn, 300, 160, 27); - RADEONWaitPLLLock(pScrn, 200, 800, 135); - - OUTPLLP(pScrn, RADEON_TV_PLL_CNTL1, 0, ~0xf); - OUTPLLP(pScrn, RADEON_TV_PLL_CNTL1, RADEON_TVCLK_SRC_SEL_TVPLL, ~RADEON_TVCLK_SRC_SEL_TVPLL); - - OUTPLLP(pScrn, RADEON_TV_PLL_CNTL1, (1 << RADEON_TVPDC_SHIFT), ~RADEON_TVPDC_MASK); - OUTPLLP(pScrn, RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_SLEEP); -} - -/* Restore TV horizontal/vertical settings */ -static void -RADEONRestoreTVHVRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - OUTREG(RADEON_TV_RGB_CNTL, restore->tv_rgb_cntl); - - OUTREG(RADEON_TV_HTOTAL, restore->tv_htotal); - OUTREG(RADEON_TV_HDISP, restore->tv_hdisp); - OUTREG(RADEON_TV_HSTART, restore->tv_hstart); - - OUTREG(RADEON_TV_VTOTAL, restore->tv_vtotal); - OUTREG(RADEON_TV_VDISP, restore->tv_vdisp); - - OUTREG(RADEON_TV_FTOTAL, restore->tv_ftotal); - - OUTREG(RADEON_TV_VSCALER_CNTL1, restore->tv_vscaler_cntl1); - OUTREG(RADEON_TV_VSCALER_CNTL2, restore->tv_vscaler_cntl2); - - OUTREG(RADEON_TV_Y_FALL_CNTL, restore->tv_y_fall_cntl); - OUTREG(RADEON_TV_Y_RISE_CNTL, restore->tv_y_rise_cntl); - OUTREG(RADEON_TV_Y_SAW_TOOTH_CNTL, restore->tv_y_saw_tooth_cntl); -} - -/* restore TV RESTART registers */ -static void -RADEONRestoreTVRestarts(ScrnInfoPtr pScrn, RADEONSavePtr restore) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - OUTREG(RADEON_TV_FRESTART, restore->tv_frestart); - OUTREG(RADEON_TV_HRESTART, restore->tv_hrestart); - OUTREG(RADEON_TV_VRESTART, restore->tv_vrestart); -} - -/* restore tv standard & output muxes */ -static void -RADEONRestoreTVOutputStd(ScrnInfoPtr pScrn, RADEONSavePtr restore) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - OUTREG(RADEON_TV_SYNC_CNTL, restore->tv_sync_cntl); - - OUTREG(RADEON_TV_TIMING_CNTL, restore->tv_timing_cntl); - - OUTREG(RADEON_TV_MODULATOR_CNTL1, restore->tv_modulator_cntl1); - OUTREG(RADEON_TV_MODULATOR_CNTL2, restore->tv_modulator_cntl2); - - OUTREG(RADEON_TV_PRE_DAC_MUX_CNTL, restore->tv_pre_dac_mux_cntl); - - OUTREG(RADEON_TV_CRC_CNTL, restore->tv_crc_cntl); -} - -/* Restore TV out regs */ -void -RADEONRestoreTVRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - ErrorF("Entering Restore TV\n"); - - OUTREG(RADEON_TV_MASTER_CNTL, (restore->tv_master_cntl - | RADEON_TV_ASYNC_RST - | RADEON_CRT_ASYNC_RST - | RADEON_TV_FIFO_ASYNC_RST)); - - /* Temporarily turn the TV DAC off */ - OUTREG(RADEON_TV_DAC_CNTL, ((restore->tv_dac_cntl & ~RADEON_TV_DAC_NBLANK) - | RADEON_TV_DAC_BGSLEEP - | RADEON_TV_DAC_RDACPD - | RADEON_TV_DAC_GDACPD - | RADEON_TV_DAC_BDACPD)); - - ErrorF("Restore TV PLL\n"); - RADEONRestoreTVPLLRegisters(pScrn, restore); - - ErrorF("Restore TVHV\n"); - RADEONRestoreTVHVRegisters(pScrn, restore); - - OUTREG(RADEON_TV_MASTER_CNTL, (restore->tv_master_cntl - | RADEON_TV_ASYNC_RST - | RADEON_CRT_ASYNC_RST)); - - ErrorF("Restore TV Restarts\n"); - RADEONRestoreTVRestarts(pScrn, restore); - - ErrorF("Restore Timing Tables\n"); - RADEONRestoreTVTimingTables(pScrn, restore); - - - OUTREG(RADEON_TV_MASTER_CNTL, (restore->tv_master_cntl - | RADEON_TV_ASYNC_RST)); - - ErrorF("Restore TV standard\n"); - RADEONRestoreTVOutputStd(pScrn, restore); - - OUTREG(RADEON_TV_MASTER_CNTL, restore->tv_master_cntl); - - OUTREG(RADEON_TV_GAIN_LIMIT_SETTINGS, restore->tv_gain_limit_settings); - OUTREG(RADEON_TV_LINEAR_GAIN_SETTINGS, restore->tv_linear_gain_settings); - - OUTREG(RADEON_TV_DAC_CNTL, restore->tv_dac_cntl); - - ErrorF("Leaving Restore TV\n"); -} - -/* Save horizontal/vertical timing code tables */ -static void -RADEONSaveTVTimingTables(ScrnInfoPtr pScrn, RADEONSavePtr save) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - uint16_t hTable; - uint16_t vTable; - uint32_t tmp; - unsigned i; - - save->tv_uv_adr = INREG(RADEON_TV_UV_ADR); - hTable = RADEONGetHTimingTablesAddr(save->tv_uv_adr); - vTable = RADEONGetVTimingTablesAddr(save->tv_uv_adr); - - /* - * Reset FIFO arbiter in order to be able to access FIFO RAM - */ - - OUTREG(RADEON_TV_MASTER_CNTL, (RADEON_TV_ASYNC_RST - | RADEON_CRT_ASYNC_RST - | RADEON_RESTART_PHASE_FIX - | RADEON_CRT_FIFO_CE_EN - | RADEON_TV_FIFO_CE_EN - | RADEON_TV_ON)); - - /*OUTREG(RADEON_TV_MASTER_CNTL, save->tv_master_cntl | RADEON_TV_ON);*/ - - ErrorF("saveTimingTables: reading timing tables\n"); - - for (i = 0; i < MAX_H_CODE_TIMING_LEN; i += 2) { - tmp = RADEONReadTVFIFO(pScrn, hTable--); - save->h_code_timing[ i ] = (uint16_t)((tmp >> 14) & 0x3fff); - save->h_code_timing[ i + 1 ] = (uint16_t)(tmp & 0x3fff); - - if (save->h_code_timing[ i ] == 0 || save->h_code_timing[ i + 1 ] == 0) - break; - } - - for (i = 0; i < MAX_V_CODE_TIMING_LEN; i += 2) { - tmp = RADEONReadTVFIFO(pScrn, vTable++); - save->v_code_timing[ i ] = (uint16_t)(tmp & 0x3fff); - save->v_code_timing[ i + 1 ] = (uint16_t)((tmp >> 14) & 0x3fff); - - if (save->v_code_timing[ i ] == 0 || save->v_code_timing[ i + 1 ] == 0) - break; - } -} - -/* read TV regs */ -void -RADEONSaveTVRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - ErrorF("Entering TV Save\n"); - - save->tv_crc_cntl = INREG(RADEON_TV_CRC_CNTL); - save->tv_frestart = INREG(RADEON_TV_FRESTART); - save->tv_hrestart = INREG(RADEON_TV_HRESTART); - save->tv_vrestart = INREG(RADEON_TV_VRESTART); - save->tv_gain_limit_settings = INREG(RADEON_TV_GAIN_LIMIT_SETTINGS); - save->tv_hdisp = INREG(RADEON_TV_HDISP); - save->tv_hstart = INREG(RADEON_TV_HSTART); - save->tv_htotal = INREG(RADEON_TV_HTOTAL); - save->tv_linear_gain_settings = INREG(RADEON_TV_LINEAR_GAIN_SETTINGS); - save->tv_master_cntl = INREG(RADEON_TV_MASTER_CNTL); - save->tv_rgb_cntl = INREG(RADEON_TV_RGB_CNTL); - save->tv_modulator_cntl1 = INREG(RADEON_TV_MODULATOR_CNTL1); - save->tv_modulator_cntl2 = INREG(RADEON_TV_MODULATOR_CNTL2); - save->tv_pre_dac_mux_cntl = INREG(RADEON_TV_PRE_DAC_MUX_CNTL); - save->tv_sync_cntl = INREG(RADEON_TV_SYNC_CNTL); - save->tv_timing_cntl = INREG(RADEON_TV_TIMING_CNTL); - save->tv_dac_cntl = INREG(RADEON_TV_DAC_CNTL); - save->tv_upsamp_and_gain_cntl = INREG(RADEON_TV_UPSAMP_AND_GAIN_CNTL); - save->tv_vdisp = INREG(RADEON_TV_VDISP); - save->tv_ftotal = INREG(RADEON_TV_FTOTAL); - save->tv_vscaler_cntl1 = INREG(RADEON_TV_VSCALER_CNTL1); - save->tv_vscaler_cntl2 = INREG(RADEON_TV_VSCALER_CNTL2); - save->tv_vtotal = INREG(RADEON_TV_VTOTAL); - save->tv_y_fall_cntl = INREG(RADEON_TV_Y_FALL_CNTL); - save->tv_y_rise_cntl = INREG(RADEON_TV_Y_RISE_CNTL); - save->tv_y_saw_tooth_cntl = INREG(RADEON_TV_Y_SAW_TOOTH_CNTL); - - save->tv_pll_cntl = INPLL(pScrn, RADEON_TV_PLL_CNTL); - save->tv_pll_cntl1 = INPLL(pScrn, RADEON_TV_PLL_CNTL1); - - ErrorF("Save TV timing tables\n"); - - RADEONSaveTVTimingTables(pScrn, save); - - ErrorF("TV Save done\n"); -} - - -/* Compute F,V,H restarts from default restart position and hPos & vPos - * Return TRUE when code timing table was changed - */ -static Bool RADEONInitTVRestarts(xf86OutputPtr output, RADEONSavePtr save, - DisplayModePtr mode) -{ - RADEONOutputPrivatePtr radeon_output = output->driver_private; - radeon_tvout_ptr tvout = &radeon_output->tvout; - RADEONInfoPtr info = RADEONPTR(output->scrn); - RADEONPLLPtr pll = &info->pll; - int restart; - unsigned hTotal; - unsigned vTotal; - unsigned fTotal; - int vOffset; - int hOffset; - uint16_t p1; - uint16_t p2; - Bool hChanged; - uint16_t hInc; - const TVModeConstants *constPtr; - - /* FIXME: need to revisit this when we add more modes */ - if (tvout->tvStd == TV_STD_NTSC || - tvout->tvStd == TV_STD_NTSC_J || - tvout->tvStd == TV_STD_PAL_M) { - if (pll->reference_freq == 2700) - constPtr = &availableTVModes[0]; - else - constPtr = &availableTVModes[2]; - } else { - if (pll->reference_freq == 2700) - constPtr = &availableTVModes[1]; - else - constPtr = &availableTVModes[3]; - } - - hTotal = constPtr->horTotal; - vTotal = constPtr->verTotal; - - if (tvout->tvStd == TV_STD_NTSC || - tvout->tvStd == TV_STD_NTSC_J || - tvout->tvStd == TV_STD_PAL_M || - tvout->tvStd == TV_STD_PAL_60) - fTotal = NTSC_TV_VFTOTAL + 1; - else - fTotal = PAL_TV_VFTOTAL + 1; - - /* Adjust positions 1&2 in hor. code timing table */ - hOffset = tvout->hPos * H_POS_UNIT; - - if (tvout->tvStd == TV_STD_NTSC || - tvout->tvStd == TV_STD_NTSC_J || - tvout->tvStd == TV_STD_PAL_M) { - /* improve image centering */ - hOffset -= 50; - p1 = hor_timing_NTSC[ H_TABLE_POS1 ]; - p2 = hor_timing_NTSC[ H_TABLE_POS2 ]; - } else { - p1 = hor_timing_PAL[ H_TABLE_POS1 ]; - p2 = hor_timing_PAL[ H_TABLE_POS2 ]; - } - - - p1 = (uint16_t)((int)p1 + hOffset); - p2 = (uint16_t)((int)p2 - hOffset); - - hChanged = (p1 != save->h_code_timing[ H_TABLE_POS1 ] || - p2 != save->h_code_timing[ H_TABLE_POS2 ]); - - save->h_code_timing[ H_TABLE_POS1 ] = p1; - save->h_code_timing[ H_TABLE_POS2 ] = p2; - - /* Convert hOffset from n. of TV clock periods to n. of CRTC clock periods (CRTC pixels) */ - hOffset = (hOffset * (int)(constPtr->pixToTV)) / 1000; - - /* Adjust restart */ - restart = constPtr->defRestart; - - /* - * Convert vPos TV lines to n. of CRTC pixels - * Be verrrrry careful when mixing signed & unsigned values in C.. - */ - if (tvout->tvStd == TV_STD_NTSC || - tvout->tvStd == TV_STD_NTSC_J || - tvout->tvStd == TV_STD_PAL_M || - tvout->tvStd == TV_STD_PAL_60) - vOffset = ((int)(vTotal * hTotal) * 2 * tvout->vPos) / (int)(NTSC_TV_LINES_PER_FRAME); - else - vOffset = ((int)(vTotal * hTotal) * 2 * tvout->vPos) / (int)(PAL_TV_LINES_PER_FRAME); - - restart -= vOffset + hOffset; - - ErrorF("computeRestarts: def = %u, h = %d, v = %d, p1=%04x, p2=%04x, restart = %d\n", - constPtr->defRestart , tvout->hPos , tvout->vPos , p1 , p2 , restart); - - save->tv_hrestart = restart % hTotal; - restart /= hTotal; - save->tv_vrestart = restart % vTotal; - restart /= vTotal; - save->tv_frestart = restart % fTotal; - - ErrorF("computeRestarts: F/H/V=%u,%u,%u\n", - (unsigned)save->tv_frestart, (unsigned)save->tv_vrestart, - (unsigned)save->tv_hrestart); - - /* Compute H_INC from hSize */ - if (tvout->tvStd == TV_STD_NTSC || - tvout->tvStd == TV_STD_NTSC_J || - tvout->tvStd == TV_STD_PAL_M) - hInc = (uint16_t)((int)(constPtr->horResolution * 4096 * NTSC_TV_CLOCK_T) / - (tvout->hSize * (int)(NTSC_TV_H_SIZE_UNIT) + (int)(NTSC_TV_ZERO_H_SIZE))); - else - hInc = (uint16_t)((int)(constPtr->horResolution * 4096 * PAL_TV_CLOCK_T) / - (tvout->hSize * (int)(PAL_TV_H_SIZE_UNIT) + (int)(PAL_TV_ZERO_H_SIZE))); - - save->tv_timing_cntl = (save->tv_timing_cntl & ~RADEON_H_INC_MASK) | - ((uint32_t)hInc << RADEON_H_INC_SHIFT); - - ErrorF("computeRestarts: hSize=%d,hInc=%u\n" , tvout->hSize , hInc); - - return hChanged; -} - -/* intit TV-out regs */ -void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save, - DisplayModePtr mode, BOOL IsPrimary) -{ - ScrnInfoPtr pScrn = output->scrn; - RADEONOutputPrivatePtr radeon_output = output->driver_private; - radeon_tvout_ptr tvout = &radeon_output->tvout; - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONPLLPtr pll = &info->pll; - unsigned m, n, p; - unsigned i; - unsigned long vert_space, flicker_removal; - uint32_t tmp; - const TVModeConstants *constPtr; - const uint16_t *hor_timing; - const uint16_t *vert_timing; - radeon_encoder_ptr radeon_encoder = radeon_get_encoder(output); - radeon_tvdac_ptr tvdac = NULL; - - if (radeon_encoder == NULL) - return; - - tvdac = (radeon_tvdac_ptr)radeon_encoder->dev_priv; - - if (tvdac == NULL) - return; - - /* FIXME: need to revisit this when we add more modes */ - if (tvout->tvStd == TV_STD_NTSC || - tvout->tvStd == TV_STD_NTSC_J || - tvout->tvStd == TV_STD_PAL_M) { - if (pll->reference_freq == 2700) - constPtr = &availableTVModes[0]; - else - constPtr = &availableTVModes[2]; - } else { - if (pll->reference_freq == 2700) - constPtr = &availableTVModes[1]; - else - constPtr = &availableTVModes[3]; - } - - save->tv_crc_cntl = 0; - - save->tv_gain_limit_settings = (0x17f << RADEON_UV_GAIN_LIMIT_SHIFT) | - (0x5ff << RADEON_Y_GAIN_LIMIT_SHIFT); - - save->tv_hdisp = constPtr->horResolution - 1; - save->tv_hstart = constPtr->horStart; - save->tv_htotal = constPtr->horTotal - 1; - - save->tv_linear_gain_settings = (0x100 << RADEON_UV_GAIN_SHIFT) | - (0x100 << RADEON_Y_GAIN_SHIFT); - - save->tv_master_cntl = (RADEON_VIN_ASYNC_RST - | RADEON_CRT_FIFO_CE_EN - | RADEON_TV_FIFO_CE_EN - | RADEON_TV_ON); - - if (!IS_R300_VARIANT) - save->tv_master_cntl |= RADEON_TVCLK_ALWAYS_ONb; - - if (tvout->tvStd == TV_STD_NTSC || - tvout->tvStd == TV_STD_NTSC_J) - save->tv_master_cntl |= RADEON_RESTART_PHASE_FIX; - - save->tv_modulator_cntl1 = RADEON_SLEW_RATE_LIMIT - | RADEON_SYNC_TIP_LEVEL - | RADEON_YFLT_EN - | RADEON_UVFLT_EN - | (6 << RADEON_CY_FILT_BLEND_SHIFT); - - if (tvout->tvStd == TV_STD_NTSC || - tvout->tvStd == TV_STD_NTSC_J) { - save->tv_modulator_cntl1 |= (0x46 << RADEON_SET_UP_LEVEL_SHIFT) - | (0x3b << RADEON_BLANK_LEVEL_SHIFT); - save->tv_modulator_cntl2 = (-111 & RADEON_TV_U_BURST_LEVEL_MASK) | - ((0 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT); - } else if (tvout->tvStd == TV_STD_SCART_PAL) { - save->tv_modulator_cntl1 |= RADEON_ALT_PHASE_EN; - save->tv_modulator_cntl2 = (0 & RADEON_TV_U_BURST_LEVEL_MASK) | - ((0 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT); - } else { - save->tv_modulator_cntl1 |= RADEON_ALT_PHASE_EN - | (0x3b << RADEON_SET_UP_LEVEL_SHIFT) - | (0x3b << RADEON_BLANK_LEVEL_SHIFT); - save->tv_modulator_cntl2 = (-78 & RADEON_TV_U_BURST_LEVEL_MASK) | - ((62 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT); - } - - save->pll_test_cntl = 0; - - save->tv_pre_dac_mux_cntl = (RADEON_Y_RED_EN - | RADEON_C_GRN_EN - | RADEON_CMP_BLU_EN - | RADEON_DAC_DITHER_EN); - - save->tv_rgb_cntl = (RADEON_RGB_DITHER_EN - | RADEON_TVOUT_SCALE_EN - | (0x0b << RADEON_UVRAM_READ_MARGIN_SHIFT) - | (0x07 << RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT) - | RADEON_RGB_ATTEN_SEL(0x3) - | RADEON_RGB_ATTEN_VAL(0xc)); - - if (IsPrimary) { - if (radeon_output->Flags & RADEON_USE_RMX) - save->tv_rgb_cntl |= RADEON_RGB_SRC_SEL_RMX; - else - save->tv_rgb_cntl |= RADEON_RGB_SRC_SEL_CRTC1; - } else { - save->tv_rgb_cntl |= RADEON_RGB_SRC_SEL_CRTC2; - } - - save->tv_sync_cntl = RADEON_SYNC_PUB | RADEON_TV_SYNC_IO_DRIVE; - - save->tv_sync_size = constPtr->horResolution + 8; - - if (tvout->tvStd == TV_STD_NTSC || - tvout->tvStd == TV_STD_NTSC_J || - tvout->tvStd == TV_STD_PAL_M || - tvout->tvStd == TV_STD_PAL_60) - vert_space = constPtr->verTotal * 2 * 10000 / NTSC_TV_LINES_PER_FRAME; - else - vert_space = constPtr->verTotal * 2 * 10000 / PAL_TV_LINES_PER_FRAME; - - save->tv_vscaler_cntl1 = RADEON_Y_W_EN; - save->tv_vscaler_cntl1 = - (save->tv_vscaler_cntl1 & 0xe3ff0000) | (vert_space * (1 << FRAC_BITS) / 10000); - - if (pll->reference_freq == 2700) - save->tv_vscaler_cntl1 |= RADEON_RESTART_FIELD; - - if (constPtr->horResolution == 1024) - save->tv_vscaler_cntl1 |= (4 << RADEON_Y_DEL_W_SIG_SHIFT); - else - save->tv_vscaler_cntl1 |= (2 << RADEON_Y_DEL_W_SIG_SHIFT); - - if (tvout->tvStd == TV_STD_NTSC || - tvout->tvStd == TV_STD_NTSC_J || - tvout->tvStd == TV_STD_PAL_M || - tvout->tvStd == TV_STD_PAL_60) - flicker_removal = - (float) constPtr->verTotal * 2.0 / NTSC_TV_LINES_PER_FRAME + 0.5; - else - flicker_removal = - (float) constPtr->verTotal * 2.0 / PAL_TV_LINES_PER_FRAME + 0.5; - - if (flicker_removal < 3) - flicker_removal = 3; - for (i = 0; i < 6; ++i) { - if (flicker_removal == SLOPE_limit[i]) - break; - } - save->tv_y_saw_tooth_cntl = - (vert_space * SLOPE_value[i] * (1 << (FRAC_BITS - 1)) + 5001) / 10000 / 8 - | ((SLOPE_value[i] * (1 << (FRAC_BITS - 1)) / 8) << 16); - save->tv_y_fall_cntl = - (YCOEF_EN_value[i] << 17) | ((YCOEF_value[i] * (1 << 8) / 8) << 24) | - RADEON_Y_FALL_PING_PONG | (272 * SLOPE_value[i] / 8) * (1 << (FRAC_BITS - 1)) / - 1024; - save->tv_y_rise_cntl = - RADEON_Y_RISE_PING_PONG - | (flicker_removal * 1024 - 272) * SLOPE_value[i] / 8 * (1 << (FRAC_BITS - 1)) / 1024; - - save->tv_vscaler_cntl2 = ((save->tv_vscaler_cntl2 & 0x00fffff0) - | (0x10 << 24) - | RADEON_DITHER_MODE - | RADEON_Y_OUTPUT_DITHER_EN - | RADEON_UV_OUTPUT_DITHER_EN - | RADEON_UV_TO_BUF_DITHER_EN); - - tmp = (save->tv_vscaler_cntl1 >> RADEON_UV_INC_SHIFT) & RADEON_UV_INC_MASK; - tmp = ((16384 * 256 * 10) / tmp + 5) / 10; - tmp = (tmp << RADEON_UV_OUTPUT_POST_SCALE_SHIFT) | 0x000b0000; - save->tv_timing_cntl = tmp; - - if (tvout->tvStd == TV_STD_NTSC || - tvout->tvStd == TV_STD_NTSC_J || - tvout->tvStd == TV_STD_PAL_M || - tvout->tvStd == TV_STD_PAL_60) - save->tv_dac_cntl = tvdac->ntsc_tvdac_adj; - else - save->tv_dac_cntl = tvdac->pal_tvdac_adj; - - save->tv_dac_cntl |= (RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD); - - if (tvout->tvStd == TV_STD_NTSC || - tvout->tvStd == TV_STD_NTSC_J) - save->tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC; - else - save->tv_dac_cntl |= RADEON_TV_DAC_STD_PAL; - -#if 0 - /* needs fixes for r4xx */ - save->tv_dac_cntl |= (RADEON_TV_DAC_RDACPD | RADEON_TV_DAC_GDACPD - | RADEON_TV_DAC_BDACPD); - - if (radeon_output->MonType == MT_CTV) { - save->tv_dac_cntl &= ~RADEON_TV_DAC_BDACPD; - } - - if (radeon_output->MonType == MT_STV) { - save->tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD | - RADEON_TV_DAC_GDACPD); - } -#endif - - if (tvout->tvStd == TV_STD_NTSC || - tvout->tvStd == TV_STD_NTSC_J) { - if (pll->reference_freq == 2700) { - m = NTSC_TV_PLL_M_27; - n = NTSC_TV_PLL_N_27; - p = NTSC_TV_PLL_P_27; - } else { - m = NTSC_TV_PLL_M_14; - n = NTSC_TV_PLL_N_14; - p = NTSC_TV_PLL_P_14; - } - } else { - if (pll->reference_freq == 2700) { - m = PAL_TV_PLL_M_27; - n = PAL_TV_PLL_N_27; - p = PAL_TV_PLL_P_27; - } else { - m = PAL_TV_PLL_M_14; - n = PAL_TV_PLL_N_14; - p = PAL_TV_PLL_P_14; - } - } - save->tv_pll_cntl = (m & RADEON_TV_M0LO_MASK) | - (((m >> 8) & RADEON_TV_M0HI_MASK) << RADEON_TV_M0HI_SHIFT) | - ((n & RADEON_TV_N0LO_MASK) << RADEON_TV_N0LO_SHIFT) | - (((n >> 9) & RADEON_TV_N0HI_MASK) << RADEON_TV_N0HI_SHIFT) | - ((p & RADEON_TV_P_MASK) << RADEON_TV_P_SHIFT); - - save->tv_pll_cntl1 = (((4 & RADEON_TVPCP_MASK)<< RADEON_TVPCP_SHIFT) | - ((4 & RADEON_TVPVG_MASK) << RADEON_TVPVG_SHIFT) | - ((1 & RADEON_TVPDC_MASK)<< RADEON_TVPDC_SHIFT) | - RADEON_TVCLK_SRC_SEL_TVPLL | - RADEON_TVPLL_TEST_DIS); - - save->tv_upsamp_and_gain_cntl = RADEON_YUPSAMP_EN | RADEON_UVUPSAMP_EN; - - save->tv_uv_adr = 0xc8; - - save->tv_vdisp = constPtr->verResolution - 1; - - if (tvout->tvStd == TV_STD_NTSC || - tvout->tvStd == TV_STD_NTSC_J || - tvout->tvStd == TV_STD_PAL_M || - tvout->tvStd == TV_STD_PAL_60) - save->tv_ftotal = NTSC_TV_VFTOTAL; - else - save->tv_ftotal = PAL_TV_VFTOTAL; - - save->tv_vtotal = constPtr->verTotal - 1; - - if (tvout->tvStd == TV_STD_NTSC || - tvout->tvStd == TV_STD_NTSC_J || - tvout->tvStd == TV_STD_PAL_M) { - hor_timing = hor_timing_NTSC; - } else { - hor_timing = hor_timing_PAL; - } - - if (tvout->tvStd == TV_STD_NTSC || - tvout->tvStd == TV_STD_NTSC_J || - tvout->tvStd == TV_STD_PAL_M || - tvout->tvStd == TV_STD_PAL_60) { - vert_timing = vert_timing_NTSC; - } else { - vert_timing = vert_timing_PAL; - } - - for (i = 0; i < MAX_H_CODE_TIMING_LEN; i++) { - if ((save->h_code_timing[ i ] = hor_timing[ i ]) == 0) - break; - } - - for (i = 0; i < MAX_V_CODE_TIMING_LEN; i++) { - if ((save->v_code_timing[ i ] = vert_timing[ i ]) == 0) - break; - } - - /* - * This must be called AFTER loading timing tables as they are modified by this function - */ - RADEONInitTVRestarts(output, save, mode); - - save->dac_cntl &= ~RADEON_DAC_TVO_EN; - - if (IS_R300_VARIANT) - save->gpiopad_a = info->SavedReg->gpiopad_a & ~1; - - if (IsPrimary) { - save->disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; - save->disp_output_cntl |= (RADEON_DISP_TVDAC_SOURCE_CRTC - | RADEON_DISP_TV_SOURCE_CRTC); - if (info->ChipFamily >= CHIP_FAMILY_R200) { - save->disp_tv_out_cntl &= ~RADEON_DISP_TV_PATH_SRC_CRTC2; - } else { - save->disp_hw_debug |= RADEON_CRT2_DISP1_SEL; - } - } else { - save->disp_output_cntl &= ~RADEON_DISP_DAC_SOURCE_MASK; - save->disp_output_cntl |= RADEON_DISP_TV_SOURCE_CRTC; - - if (info->ChipFamily >= CHIP_FAMILY_R200) { - save->disp_tv_out_cntl |= RADEON_DISP_TV_PATH_SRC_CRTC2; - } else { - save->disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL; - } - } -} - - -/* Set hw registers for a new h/v position & h size */ -void RADEONUpdateHVPosition(xf86OutputPtr output, DisplayModePtr mode) -{ - ScrnInfoPtr pScrn = output->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - Bool reloadTable; - RADEONSavePtr restore = info->ModeReg; - - reloadTable = RADEONInitTVRestarts(output, restore, mode); - - RADEONRestoreTVRestarts(pScrn, restore); - - OUTREG(RADEON_TV_TIMING_CNTL, restore->tv_timing_cntl); - - if (reloadTable) { - OUTREG(RADEON_TV_MASTER_CNTL, restore->tv_master_cntl - | RADEON_TV_ASYNC_RST - | RADEON_CRT_ASYNC_RST - | RADEON_RESTART_PHASE_FIX); - - RADEONRestoreTVTimingTables(pScrn, restore); - - OUTREG(RADEON_TV_MASTER_CNTL, restore->tv_master_cntl); - } -} - -void RADEONAdjustCrtcRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save, - DisplayModePtr mode, xf86OutputPtr output) -{ - const TVModeConstants *constPtr; - RADEONOutputPrivatePtr radeon_output = output->driver_private; - radeon_tvout_ptr tvout = &radeon_output->tvout; - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONPLLPtr pll = &info->pll; - - /* FIXME: need to revisit this when we add more modes */ - if (tvout->tvStd == TV_STD_NTSC || - tvout->tvStd == TV_STD_NTSC_J || - tvout->tvStd == TV_STD_PAL_M) { - if (pll->reference_freq == 2700) - constPtr = &availableTVModes[0]; - else - constPtr = &availableTVModes[2]; - } else { - if (pll->reference_freq == 2700) - constPtr = &availableTVModes[1]; - else - constPtr = &availableTVModes[3]; - } - - save->crtc_h_total_disp = (((constPtr->horResolution / 8) - 1) << RADEON_CRTC_H_DISP_SHIFT) | - (((constPtr->horTotal / 8) - 1) << RADEON_CRTC_H_TOTAL_SHIFT); - - save->crtc_h_sync_strt_wid = (save->crtc_h_sync_strt_wid - & ~(RADEON_CRTC_H_SYNC_STRT_PIX | RADEON_CRTC_H_SYNC_STRT_CHAR)) | - (((constPtr->horSyncStart / 8) - 1) << RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT) | - (constPtr->horSyncStart & 7); - - save->crtc_v_total_disp = ((constPtr->verResolution - 1) << RADEON_CRTC_V_DISP_SHIFT) | - ((constPtr->verTotal - 1) << RADEON_CRTC_V_TOTAL_SHIFT); - - save->crtc_v_sync_strt_wid = (save->crtc_v_sync_strt_wid & ~RADEON_CRTC_V_SYNC_STRT) | - ((constPtr->verSyncStart - 1) << RADEON_CRTC_V_SYNC_STRT_SHIFT); - -} - -void RADEONAdjustPLLRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save, - DisplayModePtr mode, xf86OutputPtr output) -{ - unsigned postDiv; - const TVModeConstants *constPtr; - RADEONOutputPrivatePtr radeon_output = output->driver_private; - radeon_tvout_ptr tvout = &radeon_output->tvout; - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONPLLPtr pll = &info->pll; - - /* FIXME: need to revisit this when we add more modes */ - if (tvout->tvStd == TV_STD_NTSC || - tvout->tvStd == TV_STD_NTSC_J || - tvout->tvStd == TV_STD_PAL_M) { - if (pll->reference_freq == 2700) - constPtr = &availableTVModes[0]; - else - constPtr = &availableTVModes[2]; - } else { - if (pll->reference_freq == 2700) - constPtr = &availableTVModes[1]; - else - constPtr = &availableTVModes[3]; - } - - save->htotal_cntl = (constPtr->horTotal & 0x7 /*0xf*/) | RADEON_HTOT_CNTL_VGA_EN; - - save->ppll_ref_div = constPtr->crtcPLL_M; - - switch (constPtr->crtcPLL_postDiv) { - case 1: - postDiv = 0; - break; - case 2: - postDiv = 1; - break; - case 3: - postDiv = 4; - break; - case 4: - postDiv = 2; - break; - case 6: - postDiv = 6; - break; - case 8: - postDiv = 3; - break; - case 12: - postDiv = 7; - break; - case 16: - default: - postDiv = 5; - break; - } - - save->ppll_div_3 = (constPtr->crtcPLL_N & 0x7ff) | (postDiv << 16); - - save->pixclks_cntl &= ~(RADEON_PIX2CLK_SRC_SEL_MASK | RADEON_PIXCLK_TV_SRC_SEL); - save->pixclks_cntl |= RADEON_PIX2CLK_SRC_SEL_P2PLLCLK; - -} - -void RADEONAdjustCrtc2RegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save, - DisplayModePtr mode, xf86OutputPtr output) -{ - const TVModeConstants *constPtr; - RADEONOutputPrivatePtr radeon_output = output->driver_private; - radeon_tvout_ptr tvout = &radeon_output->tvout; - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONPLLPtr pll = &info->pll; - - /* FIXME: need to revisit this when we add more modes */ - if (tvout->tvStd == TV_STD_NTSC || - tvout->tvStd == TV_STD_NTSC_J || - tvout->tvStd == TV_STD_PAL_M) { - if (pll->reference_freq == 2700) - constPtr = &availableTVModes[0]; - else - constPtr = &availableTVModes[2]; - } else { - if (pll->reference_freq == 2700) - constPtr = &availableTVModes[1]; - else - constPtr = &availableTVModes[3]; - } - - save->crtc2_h_total_disp = (((constPtr->horResolution / 8) - 1) << RADEON_CRTC_H_DISP_SHIFT) | - (((constPtr->horTotal / 8) - 1) << RADEON_CRTC_H_TOTAL_SHIFT); - - save->crtc2_h_sync_strt_wid = (save->crtc2_h_sync_strt_wid - & ~(RADEON_CRTC_H_SYNC_STRT_PIX | RADEON_CRTC_H_SYNC_STRT_CHAR)) | - (((constPtr->horSyncStart / 8) - 1) << RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT) | - (constPtr->horSyncStart & 7); - - save->crtc2_v_total_disp = ((constPtr->verResolution - 1) << RADEON_CRTC_V_DISP_SHIFT) | - ((constPtr->verTotal - 1) << RADEON_CRTC_V_TOTAL_SHIFT); - - save->crtc2_v_sync_strt_wid = (save->crtc2_v_sync_strt_wid & ~RADEON_CRTC_V_SYNC_STRT) | - ((constPtr->verSyncStart - 1) << RADEON_CRTC_V_SYNC_STRT_SHIFT); - -} - -void RADEONAdjustPLL2RegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save, - DisplayModePtr mode, xf86OutputPtr output) -{ - unsigned postDiv; - const TVModeConstants *constPtr; - RADEONOutputPrivatePtr radeon_output = output->driver_private; - radeon_tvout_ptr tvout = &radeon_output->tvout; - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONPLLPtr pll = &info->pll; - - /* FIXME: need to revisit this when we add more modes */ - if (tvout->tvStd == TV_STD_NTSC || - tvout->tvStd == TV_STD_NTSC_J || - tvout->tvStd == TV_STD_PAL_M) { - if (pll->reference_freq == 2700) - constPtr = &availableTVModes[0]; - else - constPtr = &availableTVModes[2]; - } else { - if (pll->reference_freq == 2700) - constPtr = &availableTVModes[1]; - else - constPtr = &availableTVModes[3]; - } - - save->htotal_cntl2 = (constPtr->horTotal & 0x7); /* 0xf */ - - save->p2pll_ref_div = constPtr->crtcPLL_M; - - switch (constPtr->crtcPLL_postDiv) { - case 1: - postDiv = 0; - break; - case 2: - postDiv = 1; - break; - case 3: - postDiv = 4; - break; - case 4: - postDiv = 2; - break; - case 6: - postDiv = 6; - break; - case 8: - postDiv = 3; - break; - case 12: - postDiv = 7; - break; - case 16: - default: - postDiv = 5; - break; - } - - save->p2pll_div_0 = (constPtr->crtcPLL_N & 0x7ff) | (postDiv << 16); - - save->pixclks_cntl &= ~RADEON_PIX2CLK_SRC_SEL_MASK; - save->pixclks_cntl |= (RADEON_PIX2CLK_SRC_SEL_P2PLLCLK - | RADEON_PIXCLK_TV_SRC_SEL); - -} diff --git a/src/radeon_tv.h b/src/radeon_tv.h deleted file mode 100644 index 719452dd..00000000 --- a/src/radeon_tv.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Integrated TV out support based on the GATOS code by - * Federico Ulivi <fulivi@lycos.com> - */ - - -/* - * Limits of h/v positions (hPos & vPos) - */ -#define MAX_H_POSITION 5 /* Range: [-5..5], negative is on the left, 0 is default, positive is on the right */ -#define MAX_V_POSITION 5 /* Range: [-5..5], negative is up, 0 is default, positive is down */ - -/* - * Unit for hPos (in TV clock periods) - */ -#define H_POS_UNIT 10 - -/* - * Indexes in h. code timing table for horizontal line position adjustment - */ -#define H_TABLE_POS1 6 -#define H_TABLE_POS2 8 - -/* - * Limits of hor. size (hSize) - */ -#define MAX_H_SIZE 5 /* Range: [-5..5], negative is smaller, positive is larger */ - -/* tv standard constants */ -#define NTSC_TV_CLOCK_T 233 -#define NTSC_TV_VFTOTAL 1 -#define NTSC_TV_LINES_PER_FRAME 525 -#define NTSC_TV_ZERO_H_SIZE 479166 -#define NTSC_TV_H_SIZE_UNIT 9478 - -#define PAL_TV_CLOCK_T 188 -#define PAL_TV_VFTOTAL 3 -#define PAL_TV_LINES_PER_FRAME 625 -#define PAL_TV_ZERO_H_SIZE 473200 -#define PAL_TV_H_SIZE_UNIT 9360 - -/* tv pll setting for 27 mhz ref clk */ -#define NTSC_TV_PLL_M_27 22 -#define NTSC_TV_PLL_N_27 175 -#define NTSC_TV_PLL_P_27 5 - -#define PAL_TV_PLL_M_27 113 -#define PAL_TV_PLL_N_27 668 -#define PAL_TV_PLL_P_27 3 - -/* tv pll setting for 14 mhz ref clk */ -#define NTSC_TV_PLL_M_14 33 -#define NTSC_TV_PLL_N_14 693 -#define NTSC_TV_PLL_P_14 7 - -#define PAL_TV_PLL_M_14 19 -#define PAL_TV_PLL_N_14 353 -#define PAL_TV_PLL_P_14 5 - -#define VERT_LEAD_IN_LINES 2 -#define FRAC_BITS 0xe -#define FRAC_MASK 0x3fff diff --git a/src/radeon_vbo.c b/src/radeon_vbo.c index 767bb98a..1924772f 100644 --- a/src/radeon_vbo.c +++ b/src/radeon_vbo.c @@ -37,8 +37,6 @@ /* KMS vertex buffer support - for R600 only but could be used on previous gpus */ -#ifdef XF86DRM_MODE - static struct radeon_bo *radeon_vbo_get_bo(ScrnInfoPtr pScrn); void radeon_vbo_put(ScrnInfoPtr pScrn, struct radeon_vbo_object *vbo) @@ -210,4 +208,3 @@ again_alloc: return bo; } -#endif diff --git a/src/radeon_vbo.h b/src/radeon_vbo.h index 583f2626..312e03b3 100644 --- a/src/radeon_vbo.h +++ b/src/radeon_vbo.h @@ -24,9 +24,6 @@ radeon_vbo_space(ScrnInfoPtr pScrn, struct radeon_vbo_object *vbo, int vert_size) { -#if defined(XF86DRM_MODE) - RADEONInfoPtr info = RADEONPTR(pScrn); -#endif void *vb; /* we've ran out of space in the vertex buffer - need to get a @@ -34,12 +31,7 @@ radeon_vbo_space(ScrnInfoPtr pScrn, radeon_vbo_check(pScrn, vbo, vert_size); vbo->vb_op_vert_size = vert_size; -#if defined(XF86DRM_MODE) - if (info->cs) - vb = (pointer)((char *)vbo->vb_bo->ptr + vbo->vb_offset); - else -#endif - vb = (pointer)((char *)vbo->vb_ptr + vbo->vb_offset); + vb = (pointer)((char *)vbo->vb_bo->ptr + vbo->vb_offset); return vb; } diff --git a/src/radeon_video.c b/src/radeon_video.c index fcca5077..52f78a4b 100644 --- a/src/radeon_video.c +++ b/src/radeon_video.c @@ -30,12 +30,6 @@ #include <X11/extensions/Xv.h> #include "fourcc.h" -#include "theatre_detect.h" -#include "theatre_reg.h" -#include "fi1236.h" -#include "msp3430.h" -#include "tda9885.h" - #define OFF_DELAY 250 /* milliseconds */ #define FREE_DELAY 15000 @@ -43,73 +37,6 @@ #define FREE_TIMER 0x02 #define CLIENT_VIDEO_ON 0x04 -#define TIMER_MASK (OFF_TIMER | FREE_TIMER) - -/* capture config constants */ -#define BUF_TYPE_FIELD 0 -#define BUF_TYPE_ALTERNATING 1 -#define BUF_TYPE_FRAME 2 - - -#define BUF_MODE_SINGLE 0 -#define BUF_MODE_DOUBLE 1 -#define BUF_MODE_TRIPLE 2 -/* CAP0_CONFIG values */ - -#define FORMAT_BROOKTREE 0 -#define FORMAT_CCIR656 1 -#define FORMAT_ZV 2 -#define FORMAT_VIP16 3 -#define FORMAT_TRANSPORT 4 - -#define ENABLE_RADEON_CAPTURE_WEAVE (RADEON_CAP0_CONFIG_CONTINUOS \ - | (BUF_MODE_DOUBLE <<7) \ - | (BUF_TYPE_FRAME << 4) \ - | ( (pPriv->theatre !=NULL)?(FORMAT_CCIR656<<23):(FORMAT_BROOKTREE<<23)) \ - | RADEON_CAP0_CONFIG_HORZ_DECIMATOR \ - | (pPriv->capture_vbi_data ? RADEON_CAP0_CONFIG_VBI_EN : 0) \ - | RADEON_CAP0_CONFIG_VIDEO_IN_VYUY422) - -#define ENABLE_RADEON_CAPTURE_BOB (RADEON_CAP0_CONFIG_CONTINUOS \ - | (BUF_MODE_SINGLE <<7) \ - | (BUF_TYPE_ALTERNATING << 4) \ - | ( (pPriv->theatre !=NULL)?(FORMAT_CCIR656<<23):(FORMAT_BROOKTREE<<23)) \ - | RADEON_CAP0_CONFIG_HORZ_DECIMATOR \ - | (pPriv->capture_vbi_data ? RADEON_CAP0_CONFIG_VBI_EN : 0) \ - | RADEON_CAP0_CONFIG_VIDEO_IN_VYUY422) - - -static void RADEONInitOffscreenImages(ScreenPtr); - -static XF86VideoAdaptorPtr RADEONSetupImageVideo(ScreenPtr); -static int RADEONPutImage(ScrnInfoPtr, short, short, short, short, short, - short, short, short, int, unsigned char*, short, - short, Bool, RegionPtr, pointer, - DrawablePtr); -static void RADEONVideoTimerCallback(ScrnInfoPtr pScrn, Time now); -static int RADEONPutVideo(ScrnInfoPtr pScrn, short src_x, short src_y, short drw_x, short drw_y, - short src_w, short src_h, short drw_w, short drw_h, - RegionPtr clipBoxes, pointer data, DrawablePtr pDraw); - -static void RADEON_board_setmisc(RADEONPortPrivPtr pPriv); -static void RADEON_RT_SetEncoding(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv); -static void RADEON_MSP_SetEncoding(RADEONPortPrivPtr pPriv); -static void RADEON_TDA9885_SetEncoding(RADEONPortPrivPtr pPriv); -static void RADEON_FI1236_SetEncoding(RADEONPortPrivPtr pPriv); - -static Atom xvBrightness, xvColorKey, xvSaturation, xvDoubleBuffer; -static Atom xvRedIntensity, xvGreenIntensity, xvBlueIntensity; -static Atom xvContrast, xvHue, xvColor, xvAutopaintColorkey, xvSetDefaults; -static Atom xvGamma, xvColorspace; -static Atom xvCRTC; -static Atom xvEncoding, xvFrequency, xvVolume, xvMute, - xvDecBrightness, xvDecContrast, xvDecHue, xvDecColor, xvDecSaturation, - xvTunerStatus, xvSAP, xvOverlayDeinterlacingMethod, - xvLocationID, xvDeviceID, xvInstanceID, xvDumpStatus, - xvAdjustment; - -static Atom xvOvAlpha, xvGrAlpha, xvAlphaMode; - #define GET_PORT_PRIVATE(pScrn) \ (RADEONPortPrivPtr)((RADEONPTR(pScrn))->adaptor->pPortPrivates[0].ptr) @@ -146,17 +73,8 @@ radeon_box_area(BoxPtr box) static Bool radeon_crtc_is_enabled(xf86CrtcPtr crtc) { - RADEONCrtcPrivatePtr radeon_crtc; - -#ifdef XF86DRM_MODE - if (RADEONPTR(crtc->scrn)->cs) { - drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; - return drmmode_crtc->dpms_mode == DPMSModeOn; - } -#endif - - radeon_crtc = crtc->driver_private; - return radeon_crtc->enabled; + drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; + return drmmode_crtc->dpms_mode == DPMSModeOn; } xf86CrtcPtr @@ -284,37 +202,13 @@ radeon_crtc_clip_video_helper(ScrnInfoPtr pScrn, } #endif -static Bool -radeon_crtc_clip_video(ScrnInfoPtr pScrn, - xf86CrtcPtr *crtc_ret, - xf86CrtcPtr desired_crtc, - BoxPtr dst, - INT32 *xa, - INT32 *xb, - INT32 *ya, - INT32 *yb, - RegionPtr reg, - INT32 width, - INT32 height) -{ -#ifndef HAVE_XF86CRTCCLIPVIDEOHELPER - return radeon_crtc_clip_video_helper(pScrn, crtc_ret, desired_crtc, - dst, xa, xb, ya, yb, - reg, width, height); -#else - return xf86_crtc_clip_video_helper(pScrn, crtc_ret, desired_crtc, - dst, xa, xb, ya, yb, - reg, width, height); -#endif -} - void RADEONInitVideo(ScreenPtr pScreen) { ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); RADEONInfoPtr info = RADEONPTR(pScrn); RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); XF86VideoAdaptorPtr *adaptors, *newAdaptors = NULL; - XF86VideoAdaptorPtr overlayAdaptor = NULL, texturedAdaptor = NULL; + XF86VideoAdaptorPtr texturedAdaptor = NULL; int num_adaptors; /* no overlay or 3D on RN50 */ @@ -329,20 +223,8 @@ void RADEONInitVideo(ScreenPtr pScreen) memcpy(newAdaptors, adaptors, num_adaptors * sizeof(XF86VideoAdaptorPtr)); adaptors = newAdaptors; - if (!IS_AVIVO_VARIANT && !info->kms_enabled) { - overlayAdaptor = RADEONSetupImageVideo(pScreen); - if (overlayAdaptor != NULL) { - adaptors[num_adaptors++] = overlayAdaptor; - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Set up overlay video\n"); - } else - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Failed to set up overlay video\n"); - RADEONInitOffscreenImages(pScreen); - } - if ((info->ChipFamily < CHIP_FAMILY_RS400) -#ifdef XF86DRI || (info->directRenderingEnabled) -#endif ) { texturedAdaptor = RADEONSetupImageTexturedVideo(pScreen); if (texturedAdaptor != NULL) { @@ -371,115 +253,6 @@ void RADEONInitVideo(ScreenPtr pScreen) } -/* client libraries expect an encoding */ -static XF86VideoEncodingRec DummyEncoding = -{ - 0, - "XV_IMAGE", - 2047, 2047, - {1, 1} -}; - - /* the picture is interlaced - hence the half-heights */ - -static XF86VideoEncodingRec -InputVideoEncodings[] = -{ - { 0, "XV_IMAGE", 2047,2047,{1,1}}, - { 1, "pal-composite", 720, 288, { 1, 50 }}, - { 2, "pal-tuner", 720, 288, { 1, 50 }}, - { 3, "pal-svideo", 720, 288, { 1, 50 }}, - { 4, "ntsc-composite", 640, 240, { 1001, 60000 }}, - { 5, "ntsc-tuner", 640, 240, { 1001, 60000 }}, - { 6, "ntsc-svideo", 640, 240, { 1001, 60000 }}, - { 7, "secam-composite", 720, 288, { 1, 50 }}, - { 8, "secam-tuner", 720, 288, { 1, 50 }}, - { 9, "secam-svideo", 720, 288, { 1, 50 }}, - { 10,"pal_60-composite", 768, 288, { 1, 50 }}, - { 11,"pal_60-tuner", 768, 288, { 1, 50 }}, - { 12,"pal_60-svideo", 768, 288, { 1, 50 }} -}; - - -#define NUM_FORMATS 12 - -static XF86VideoFormatRec Formats[NUM_FORMATS] = -{ - {8, TrueColor}, {8, DirectColor}, {8, PseudoColor}, - {8, GrayScale}, {8, StaticGray}, {8, StaticColor}, - {15, TrueColor}, {16, TrueColor}, {24, TrueColor}, - {15, DirectColor}, {16, DirectColor}, {24, DirectColor} -}; - - -#if 0 -#define NUM_ATTRIBUTES 9+6 - -static XF86AttributeRec Attributes[NUM_ATTRIBUTES] = -{ - {XvSettable , 0, 1, "XV_SET_DEFAULTS"}, - {XvSettable | XvGettable, 0, 1, "XV_AUTOPAINT_COLORKEY"}, - {XvSettable | XvGettable, 0, ~0, "XV_COLORKEY"}, - {XvSettable | XvGettable, 0, 1, "XV_DOUBLE_BUFFER"}, - {XvSettable | XvGettable, -1000, 1000, "XV_BRIGHTNESS"}, - {XvSettable | XvGettable, -1000, 1000, "XV_CONTRAST"}, - {XvSettable | XvGettable, -1000, 1000, "XV_SATURATION"}, - {XvSettable | XvGettable, -1000, 1000, "XV_COLOR"}, - {XvSettable | XvGettable, -1000, 1000, "XV_HUE"}, - {XvSettable | XvGettable, -1000, 1000, "XV_RED_INTENSITY"}, - {XvSettable | XvGettable, -1000, 1000, "XV_GREEN_INTENSITY"}, - {XvSettable | XvGettable, -1000, 1000, "XV_BLUE_INTENSITY"}, - {XvSettable | XvGettable, -1, 1, "XV_CRTC"}, - {XvSettable | XvGettable, 100, 10000, "XV_GAMMA"}, - {XvSettable | XvGettable, 0, 1, "XV_COLORSPACE"}, -}; - -#endif - -#define NUM_ATTRIBUTES 22 -#define NUM_DEC_ATTRIBUTES (NUM_ATTRIBUTES+12) - -static XF86AttributeRec Attributes[NUM_DEC_ATTRIBUTES+1] = -{ - { XvGettable, 0, ~0, "XV_DEVICE_ID"}, - { XvGettable, 0, ~0, "XV_LOCATION_ID"}, - { XvGettable, 0, ~0, "XV_INSTANCE_ID"}, - {XvSettable , 0, 1, "XV_DUMP_STATUS"}, - {XvSettable , 0, 1, "XV_SET_DEFAULTS"}, - {XvSettable | XvGettable, 0, 1, "XV_AUTOPAINT_COLORKEY"}, - {XvSettable | XvGettable, 0, ~0,"XV_COLORKEY"}, - {XvSettable | XvGettable, 0, 1, "XV_DOUBLE_BUFFER"}, - {XvSettable | XvGettable, 0, 255, "XV_OVERLAY_ALPHA"}, - {XvSettable | XvGettable, 0, 255, "XV_GRAPHICS_ALPHA"}, - {XvSettable | XvGettable, 0, 1, "XV_ALPHA_MODE"}, - {XvSettable | XvGettable, -1000, 1000, "XV_BRIGHTNESS"}, - {XvSettable | XvGettable, -1000, 1000, "XV_CONTRAST"}, - {XvSettable | XvGettable, -1000, 1000, "XV_SATURATION"}, - {XvSettable | XvGettable, -1000, 1000, "XV_COLOR"}, - {XvSettable | XvGettable, -1000, 1000, "XV_HUE"}, - {XvSettable | XvGettable, -1000, 1000, "XV_RED_INTENSITY"}, - {XvSettable | XvGettable, -1000, 1000, "XV_GREEN_INTENSITY"}, - {XvSettable | XvGettable, -1000, 1000, "XV_BLUE_INTENSITY"}, - {XvSettable | XvGettable, -1, 1, "XV_CRTC"}, - {XvSettable | XvGettable, 100, 10000, "XV_GAMMA"}, - {XvSettable | XvGettable, 0, 1, "XV_COLORSPACE"}, - - {XvSettable | XvGettable, -1000, 1000, "XV_DEC_BRIGHTNESS"}, - {XvSettable | XvGettable, -1000, 1000, "XV_DEC_CONTRAST"}, - {XvSettable | XvGettable, -1000, 1000, "XV_DEC_SATURATION"}, - {XvSettable | XvGettable, -1000, 1000, "XV_DEC_HUE"}, - {XvSettable | XvGettable, 0, 2, "XV_OVERLAY_DEINTERLACING_METHOD"}, - {XvSettable | XvGettable, 0, 12, "XV_ENCODING"}, - {XvSettable | XvGettable, 0, -1, "XV_FREQ"}, - { XvGettable, -1000, 1000, "XV_TUNER_STATUS"}, - {XvSettable | XvGettable, -1000, 1000, "XV_VOLUME"}, - {XvSettable | XvGettable, 0, 1, "XV_MUTE"}, - {XvSettable | XvGettable, 0, 1, "XV_SAP"}, - {XvSettable | XvGettable, 0, 0x1F, "XV_DEBUG_ADJUSTMENT"}, - { 0, 0, 0, NULL} /* just a place holder so I don't have to be fancy with commas */ -}; - - #define INCLUDE_RGB_FORMATS 1 #if INCLUDE_RGB_FORMATS @@ -563,1149 +336,16 @@ static XF86AttributeRec Attributes[NUM_DEC_ATTRIBUTES+1] = 0, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, \ XvTopToBottom \ } - -static XF86ImageRec Images[NUM_IMAGES] = -{ -#if X_BYTE_ORDER == X_BIG_ENDIAN - XVIMAGE_RGBA32(MSBFirst), - XVIMAGE_RGBT16(MSBFirst), - XVIMAGE_RGB16(MSBFirst), -#else - XVIMAGE_RGBA32(LSBFirst), - XVIMAGE_RGBT16(LSBFirst), - XVIMAGE_RGB16(LSBFirst), -#endif - XVIMAGE_RGB24, - XVIMAGE_YUY2, - XVIMAGE_UYVY, - XVIMAGE_YV12, - XVIMAGE_I420 -}; - -#else - -#define NUM_IMAGES 4 - -static XF86ImageRec Images[NUM_IMAGES] = -{ - XVIMAGE_YUY2, - XVIMAGE_UYVY, - XVIMAGE_YV12, - XVIMAGE_I420 -}; - -#endif - -/* Parameters for ITU-R BT.601 and ITU-R BT.709 colour spaces */ -static REF_TRANSFORM trans[2] = -{ - {1.1678, 0.0, 1.6007, -0.3929, -0.8154, 2.0232, 0.0}, /* BT.601 */ - {1.1678, 0.0, 1.7980, -0.2139, -0.5345, 2.1186, 0.0} /* BT.709 */ -}; - -/* Gamma curve definition for preset gammas */ -typedef struct tagGAMMA_CURVE_R100 -{ - uint32_t GAMMA_0_F_SLOPE; - uint32_t GAMMA_0_F_OFFSET; - uint32_t GAMMA_10_1F_SLOPE; - uint32_t GAMMA_10_1F_OFFSET; - uint32_t GAMMA_20_3F_SLOPE; - uint32_t GAMMA_20_3F_OFFSET; - uint32_t GAMMA_40_7F_SLOPE; - uint32_t GAMMA_40_7F_OFFSET; - uint32_t GAMMA_380_3BF_SLOPE; - uint32_t GAMMA_380_3BF_OFFSET; - uint32_t GAMMA_3C0_3FF_SLOPE; - uint32_t GAMMA_3C0_3FF_OFFSET; - float OvGammaCont; -} GAMMA_CURVE_R100; - -typedef struct tagGAMMA_CURVE_R200 -{ - uint32_t GAMMA_0_F_SLOPE; - uint32_t GAMMA_0_F_OFFSET; - uint32_t GAMMA_10_1F_SLOPE; - uint32_t GAMMA_10_1F_OFFSET; - uint32_t GAMMA_20_3F_SLOPE; - uint32_t GAMMA_20_3F_OFFSET; - uint32_t GAMMA_40_7F_SLOPE; - uint32_t GAMMA_40_7F_OFFSET; - uint32_t GAMMA_80_BF_SLOPE; - uint32_t GAMMA_80_BF_OFFSET; - uint32_t GAMMA_C0_FF_SLOPE; - uint32_t GAMMA_C0_FF_OFFSET; - uint32_t GAMMA_100_13F_SLOPE; - uint32_t GAMMA_100_13F_OFFSET; - uint32_t GAMMA_140_17F_SLOPE; - uint32_t GAMMA_140_17F_OFFSET; - uint32_t GAMMA_180_1BF_SLOPE; - uint32_t GAMMA_180_1BF_OFFSET; - uint32_t GAMMA_1C0_1FF_SLOPE; - uint32_t GAMMA_1C0_1FF_OFFSET; - uint32_t GAMMA_200_23F_SLOPE; - uint32_t GAMMA_200_23F_OFFSET; - uint32_t GAMMA_240_27F_SLOPE; - uint32_t GAMMA_240_27F_OFFSET; - uint32_t GAMMA_280_2BF_SLOPE; - uint32_t GAMMA_280_2BF_OFFSET; - uint32_t GAMMA_2C0_2FF_SLOPE; - uint32_t GAMMA_2C0_2FF_OFFSET; - uint32_t GAMMA_300_33F_SLOPE; - uint32_t GAMMA_300_33F_OFFSET; - uint32_t GAMMA_340_37F_SLOPE; - uint32_t GAMMA_340_37F_OFFSET; - uint32_t GAMMA_380_3BF_SLOPE; - uint32_t GAMMA_380_3BF_OFFSET; - uint32_t GAMMA_3C0_3FF_SLOPE; - uint32_t GAMMA_3C0_3FF_OFFSET; - float OvGammaCont; -} GAMMA_CURVE_R200; - - -/* Preset gammas */ -static GAMMA_CURVE_R100 gamma_curve_r100[8] = -{ - /* Gamma 1.0 */ - {0x100, 0x0, - 0x100, 0x20, - 0x100, 0x40, - 0x100, 0x80, - 0x100, 0x100, - 0x100, 0x100, - 1.0}, - /* Gamma 0.85 */ - {0x75, 0x0, - 0xA2, 0xF, - 0xAC, 0x23, - 0xC6, 0x4E, - 0x129, 0xD6, - 0x12B, 0xD5, - 1.0}, - /* Gamma 1.1 */ - {0x180, 0x0, - 0x13C, 0x30, - 0x13C, 0x57, - 0x123, 0xA5, - 0xEA, 0x116, - 0xEA, 0x116, - 0.9913}, - /* Gamma 1.2 */ - {0x21B, 0x0, - 0x16D, 0x43, - 0x172, 0x71, - 0x13D, 0xCD, - 0xD9, 0x128, - 0xD6, 0x12A, - 0.9827}, - /* Gamma 1.45 */ - {0x404, 0x0, - 0x1B9, 0x81, - 0x1EE, 0xB8, - 0x16A, 0x133, - 0xB7, 0x14B, - 0xB2, 0x14E, - 0.9567}, - /* Gamma 1.7 */ - {0x658, 0x0, - 0x1B5, 0xCB, - 0x25F, 0x102, - 0x181, 0x199, - 0x9C, 0x165, - 0x98, 0x167, - 0.9394}, - /* Gamma 2.2 */ - {0x7FF, 0x0, - 0x625, 0x100, - 0x1E4, 0x1C4, - 0x1BD, 0x23D, - 0x79, 0x187, - 0x76, 0x188, - 0.9135}, - /* Gamma 2.5 */ - {0x7FF, 0x0, - 0x7FF, 0x100, - 0x2AD, 0x200, - 0x1A2, 0x2AB, - 0x6E, 0x194, - 0x67, 0x197, - 0.9135} -}; - -static GAMMA_CURVE_R200 gamma_curve_r200[8] = - { - /* Gamma 1.0 */ - {0x00000100, 0x00000000, - 0x00000100, 0x00000020, - 0x00000100, 0x00000040, - 0x00000100, 0x00000080, - 0x00000100, 0x00000100, - 0x00000100, 0x00000100, - 0x00000100, 0x00000200, - 0x00000100, 0x00000200, - 0x00000100, 0x00000300, - 0x00000100, 0x00000300, - 0x00000100, 0x00000400, - 0x00000100, 0x00000400, - 0x00000100, 0x00000500, - 0x00000100, 0x00000500, - 0x00000100, 0x00000600, - 0x00000100, 0x00000600, - 0x00000100, 0x00000700, - 0x00000100, 0x00000700, - 1.0}, - /* Gamma 0.85 */ - {0x0000001D, 0x00000000, - 0x00000028, 0x0000000F, - 0x00000056, 0x00000023, - 0x000000C5, 0x0000004E, - 0x000000DA, 0x000000B0, - 0x000000E6, 0x000000AA, - 0x000000F1, 0x00000190, - 0x000000F9, 0x0000018C, - 0x00000101, 0x00000286, - 0x00000108, 0x00000282, - 0x0000010D, 0x0000038A, - 0x00000113, 0x00000387, - 0x00000118, 0x0000049A, - 0x0000011C, 0x00000498, - 0x00000120, 0x000005B4, - 0x00000124, 0x000005B2, - 0x00000128, 0x000006D6, - 0x0000012C, 0x000006D5, - 1.0}, - /* Gamma 1.1 */ - {0x00000060, 0x00000000, - 0x0000004F, 0x00000030, - 0x0000009C, 0x00000057, - 0x00000121, 0x000000A5, - 0x00000113, 0x00000136, - 0x0000010B, 0x0000013A, - 0x00000105, 0x00000245, - 0x00000100, 0x00000247, - 0x000000FD, 0x00000348, - 0x000000F9, 0x00000349, - 0x000000F6, 0x00000443, - 0x000000F4, 0x00000444, - 0x000000F2, 0x00000538, - 0x000000F0, 0x00000539, - 0x000000EE, 0x00000629, - 0x000000EC, 0x00000629, - 0x000000EB, 0x00000716, - 0x000000E9, 0x00000717, - 0.9913}, - /* Gamma 1.2 */ - {0x00000087, 0x00000000, - 0x0000005B, 0x00000043, - 0x000000B7, 0x00000071, - 0x0000013D, 0x000000CD, - 0x00000121, 0x0000016B, - 0x00000113, 0x00000172, - 0x00000107, 0x00000286, - 0x000000FF, 0x0000028A, - 0x000000F8, 0x00000389, - 0x000000F2, 0x0000038B, - 0x000000ED, 0x0000047D, - 0x000000E9, 0x00000480, - 0x000000E5, 0x00000568, - 0x000000E1, 0x0000056A, - 0x000000DE, 0x0000064B, - 0x000000DB, 0x0000064D, - 0x000000D9, 0x00000728, - 0x000000D6, 0x00000729, - 0.9827}, - /* Gamma 1.45 */ - {0x00000101, 0x00000000, - 0x0000006E, 0x00000081, - 0x000000F7, 0x000000B8, - 0x0000016E, 0x00000133, - 0x00000139, 0x000001EA, - 0x0000011B, 0x000001F9, - 0x00000105, 0x00000314, - 0x000000F6, 0x0000031C, - 0x000000E9, 0x00000411, - 0x000000DF, 0x00000417, - 0x000000D7, 0x000004F6, - 0x000000CF, 0x000004F9, - 0x000000C9, 0x000005C9, - 0x000000C4, 0x000005CC, - 0x000000BF, 0x0000068F, - 0x000000BA, 0x00000691, - 0x000000B6, 0x0000074B, - 0x000000B2, 0x0000074D, - 0.9567}, - /* Gamma 1.7 */ - {0x00000196, 0x00000000, - 0x0000006D, 0x000000CB, - 0x0000012F, 0x00000102, - 0x00000187, 0x00000199, - 0x00000144, 0x0000025b, - 0x00000118, 0x00000273, - 0x000000FE, 0x0000038B, - 0x000000E9, 0x00000395, - 0x000000DA, 0x0000047E, - 0x000000CE, 0x00000485, - 0x000000C3, 0x00000552, - 0x000000BB, 0x00000556, - 0x000000B3, 0x00000611, - 0x000000AC, 0x00000614, - 0x000000A7, 0x000006C1, - 0x000000A1, 0x000006C3, - 0x0000009D, 0x00000765, - 0x00000098, 0x00000767, - 0.9394}, - /* Gamma 2.2 */ - {0x000001FF, 0x00000000, - 0x0000018A, 0x00000100, - 0x000000F1, 0x000001C5, - 0x000001D6, 0x0000023D, - 0x00000124, 0x00000328, - 0x00000116, 0x0000032F, - 0x000000E2, 0x00000446, - 0x000000D3, 0x0000044D, - 0x000000BC, 0x00000520, - 0x000000B0, 0x00000526, - 0x000000A4, 0x000005D6, - 0x0000009B, 0x000005DB, - 0x00000092, 0x00000676, - 0x0000008B, 0x00000679, - 0x00000085, 0x00000704, - 0x00000080, 0x00000707, - 0x0000007B, 0x00000787, - 0x00000076, 0x00000789, - 0.9135}, - /* Gamma 2.5 */ - {0x000001FF, 0x00000000, - 0x000001FF, 0x00000100, - 0x00000159, 0x000001FF, - 0x000001AC, 0x000002AB, - 0x0000012F, 0x00000381, - 0x00000101, 0x00000399, - 0x000000D9, 0x0000049A, - 0x000000C3, 0x000004A5, - 0x000000AF, 0x00000567, - 0x000000A1, 0x0000056E, - 0x00000095, 0x00000610, - 0x0000008C, 0x00000614, - 0x00000084, 0x000006A0, - 0x0000007D, 0x000006A4, - 0x00000077, 0x00000721, - 0x00000071, 0x00000723, - 0x0000006D, 0x00000795, - 0x00000068, 0x00000797, - 0.9135} -}; - -static void -RADEONSetOverlayGamma(ScrnInfoPtr pScrn, uint32_t gamma) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - /* Set gamma */ - RADEONWaitForIdleMMIO(pScrn); - - if (info->ChipFamily < CHIP_FAMILY_R200) { - uint32_t ov0_scale_cntl = INREG(RADEON_OV0_SCALE_CNTL) & ~RADEON_SCALER_GAMMA_SEL_MASK; - OUTREG(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl | (gamma << 5)); - } - - /* Load gamma curve adjustments */ - if (info->ChipFamily >= CHIP_FAMILY_R200) { - OUTREG(RADEON_OV0_GAMMA_000_00F, - (gamma_curve_r200[gamma].GAMMA_0_F_OFFSET << 0x00000000) | - (gamma_curve_r200[gamma].GAMMA_0_F_SLOPE << 0x00000010)); - OUTREG(RADEON_OV0_GAMMA_010_01F, - (gamma_curve_r200[gamma].GAMMA_10_1F_OFFSET << 0x00000000) | - (gamma_curve_r200[gamma].GAMMA_10_1F_SLOPE << 0x00000010)); - OUTREG(RADEON_OV0_GAMMA_020_03F, - (gamma_curve_r200[gamma].GAMMA_20_3F_OFFSET << 0x00000000) | - (gamma_curve_r200[gamma].GAMMA_20_3F_SLOPE << 0x00000010)); - OUTREG(RADEON_OV0_GAMMA_040_07F, - (gamma_curve_r200[gamma].GAMMA_40_7F_OFFSET << 0x00000000) | - (gamma_curve_r200[gamma].GAMMA_40_7F_SLOPE << 0x00000010)); - OUTREG(RADEON_OV0_GAMMA_080_0BF, - (gamma_curve_r200[gamma].GAMMA_80_BF_OFFSET << 0x00000000) | - (gamma_curve_r200[gamma].GAMMA_80_BF_SLOPE << 0x00000010)); - OUTREG(RADEON_OV0_GAMMA_0C0_0FF, - (gamma_curve_r200[gamma].GAMMA_C0_FF_OFFSET << 0x00000000) | - (gamma_curve_r200[gamma].GAMMA_C0_FF_SLOPE << 0x00000010)); - OUTREG(RADEON_OV0_GAMMA_100_13F, - (gamma_curve_r200[gamma].GAMMA_100_13F_OFFSET << 0x00000000) | - (gamma_curve_r200[gamma].GAMMA_100_13F_SLOPE << 0x00000010)); - OUTREG(RADEON_OV0_GAMMA_140_17F, - (gamma_curve_r200[gamma].GAMMA_140_17F_OFFSET << 0x00000000) | - (gamma_curve_r200[gamma].GAMMA_140_17F_SLOPE << 0x00000010)); - OUTREG(RADEON_OV0_GAMMA_180_1BF, - (gamma_curve_r200[gamma].GAMMA_180_1BF_OFFSET << 0x00000000) | - (gamma_curve_r200[gamma].GAMMA_180_1BF_SLOPE << 0x00000010)); - OUTREG(RADEON_OV0_GAMMA_1C0_1FF, - (gamma_curve_r200[gamma].GAMMA_1C0_1FF_OFFSET << 0x00000000) | - (gamma_curve_r200[gamma].GAMMA_1C0_1FF_SLOPE << 0x00000010)); - OUTREG(RADEON_OV0_GAMMA_200_23F, - (gamma_curve_r200[gamma].GAMMA_200_23F_OFFSET << 0x00000000) | - (gamma_curve_r200[gamma].GAMMA_200_23F_SLOPE << 0x00000010)); - OUTREG(RADEON_OV0_GAMMA_240_27F, - (gamma_curve_r200[gamma].GAMMA_240_27F_OFFSET << 0x00000000) | - (gamma_curve_r200[gamma].GAMMA_240_27F_SLOPE << 0x00000010)); - OUTREG(RADEON_OV0_GAMMA_280_2BF, - (gamma_curve_r200[gamma].GAMMA_280_2BF_OFFSET << 0x00000000) | - (gamma_curve_r200[gamma].GAMMA_280_2BF_SLOPE << 0x00000010)); - OUTREG(RADEON_OV0_GAMMA_2C0_2FF, - (gamma_curve_r200[gamma].GAMMA_2C0_2FF_OFFSET << 0x00000000) | - (gamma_curve_r200[gamma].GAMMA_2C0_2FF_SLOPE << 0x00000010)); - OUTREG(RADEON_OV0_GAMMA_300_33F, - (gamma_curve_r200[gamma].GAMMA_300_33F_OFFSET << 0x00000000) | - (gamma_curve_r200[gamma].GAMMA_300_33F_SLOPE << 0x00000010)); - OUTREG(RADEON_OV0_GAMMA_340_37F, - (gamma_curve_r200[gamma].GAMMA_340_37F_OFFSET << 0x00000000) | - (gamma_curve_r200[gamma].GAMMA_340_37F_SLOPE << 0x00000010)); - OUTREG(RADEON_OV0_GAMMA_380_3BF, - (gamma_curve_r200[gamma].GAMMA_380_3BF_OFFSET << 0x00000000) | - (gamma_curve_r200[gamma].GAMMA_380_3BF_SLOPE << 0x00000010)); - OUTREG(RADEON_OV0_GAMMA_3C0_3FF, - (gamma_curve_r200[gamma].GAMMA_3C0_3FF_OFFSET << 0x00000000) | - (gamma_curve_r200[gamma].GAMMA_3C0_3FF_SLOPE << 0x00000010)); - } else { - OUTREG(RADEON_OV0_GAMMA_000_00F, - (gamma_curve_r100[gamma].GAMMA_0_F_OFFSET << 0x00000000) | - (gamma_curve_r100[gamma].GAMMA_0_F_SLOPE << 0x00000010)); - OUTREG(RADEON_OV0_GAMMA_010_01F, - (gamma_curve_r100[gamma].GAMMA_10_1F_OFFSET << 0x00000000) | - (gamma_curve_r100[gamma].GAMMA_10_1F_SLOPE << 0x00000010)); - OUTREG(RADEON_OV0_GAMMA_020_03F, - (gamma_curve_r100[gamma].GAMMA_20_3F_OFFSET << 0x00000000) | - (gamma_curve_r100[gamma].GAMMA_20_3F_SLOPE << 0x00000010)); - OUTREG(RADEON_OV0_GAMMA_040_07F, - (gamma_curve_r100[gamma].GAMMA_40_7F_OFFSET << 0x00000000) | - (gamma_curve_r100[gamma].GAMMA_40_7F_SLOPE << 0x00000010)); - OUTREG(RADEON_OV0_GAMMA_380_3BF, - (gamma_curve_r100[gamma].GAMMA_380_3BF_OFFSET << 0x00000000) | - (gamma_curve_r100[gamma].GAMMA_380_3BF_SLOPE << 0x00000010)); - OUTREG(RADEON_OV0_GAMMA_3C0_3FF, - (gamma_curve_r100[gamma].GAMMA_3C0_3FF_OFFSET << 0x00000000) | - (gamma_curve_r100[gamma].GAMMA_3C0_3FF_SLOPE << 0x00000010)); - } - -} - -static uint32_t -RADEONTranslateUserGamma(uint32_t user_gamma) -{ - /* translate from user_gamma (gamma x 1000) to radeon gamma table index value */ - if (user_gamma <= 925) /* 0.85 */ - return 1; - else if (user_gamma <= 1050) /* 1.0 */ - return 0; - else if (user_gamma <= 1150) /* 1.1 */ - return 2; - else if (user_gamma <= 1325) /* 1.2 */ - return 3; - else if (user_gamma <= 1575) /* 1.45 */ - return 4; - else if (user_gamma <= 1950) /* 1.7 */ - return 5; - else if (user_gamma <= 2350) /* 2.2 */ - return 6; - else if (user_gamma > 2350) /* 2.5 */ - return 7; - else - return 0; -} - - -/**************************************************************************** - * SetTransform * - * Function: Calculates and sets color space transform from supplied * - * reference transform, gamma, brightness, contrast, hue and * - * saturation. * - * Inputs: bright - brightness * - * cont - contrast * - * sat - saturation * - * hue - hue * - * red_intensity - intensity of red component * - * green_intensity - intensity of green component * - * blue_intensity - intensity of blue component * - * ref - index to the table of refernce transforms * - * user_gamma - gamma value x 1000 (e.g., 1200 = gamma of 1.2) * - * Outputs: NONE * - ****************************************************************************/ - -static void RADEONSetTransform (ScrnInfoPtr pScrn, - float bright, - float cont, - float sat, - float hue, - float red_intensity, - float green_intensity, - float blue_intensity, - uint32_t ref, - uint32_t user_gamma) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - float OvHueSin, OvHueCos; - float CAdjLuma, CAdjOff; - float CAdjRCb, CAdjRCr; - float CAdjGCb, CAdjGCr; - float CAdjBCb, CAdjBCr; - float RedAdj,GreenAdj,BlueAdj; - float OvLuma, OvROff, OvGOff, OvBOff; - float OvRCb, OvRCr; - float OvGCb, OvGCr; - float OvBCb, OvBCr; - float Loff = 64.0; - float Coff = 512.0f; - - uint32_t dwOvLuma, dwOvROff, dwOvGOff, dwOvBOff; - uint32_t dwOvRCb, dwOvRCr; - uint32_t dwOvGCb, dwOvGCr; - uint32_t dwOvBCb, dwOvBCr; - uint32_t gamma = 0; - - if (ref >= 2) - return; - - /* translate from user_gamma (gamma x 1000) to radeon gamma table index value */ - gamma = RADEONTranslateUserGamma(user_gamma); - - if (gamma >= 8) - return; - - OvHueSin = sin(hue); - OvHueCos = cos(hue); - - CAdjLuma = cont * trans[ref].RefLuma; - CAdjOff = cont * trans[ref].RefLuma * bright * 1023.0; - RedAdj = cont * trans[ref].RefLuma * red_intensity * 1023.0; - GreenAdj = cont * trans[ref].RefLuma * green_intensity * 1023.0; - BlueAdj = cont * trans[ref].RefLuma * blue_intensity * 1023.0; - - CAdjRCb = sat * -OvHueSin * trans[ref].RefRCr; - CAdjRCr = sat * OvHueCos * trans[ref].RefRCr; - CAdjGCb = sat * (OvHueCos * trans[ref].RefGCb - OvHueSin * trans[ref].RefGCr); - CAdjGCr = sat * (OvHueSin * trans[ref].RefGCb + OvHueCos * trans[ref].RefGCr); - CAdjBCb = sat * OvHueCos * trans[ref].RefBCb; - CAdjBCr = sat * OvHueSin * trans[ref].RefBCb; - -#if 0 /* default constants */ - CAdjLuma = 1.16455078125; - - CAdjRCb = 0.0; - CAdjRCr = 1.59619140625; - CAdjGCb = -0.39111328125; - CAdjGCr = -0.8125; - CAdjBCb = 2.01708984375; - CAdjBCr = 0; -#endif - - OvLuma = CAdjLuma * gamma_curve_r100[gamma].OvGammaCont; - OvRCb = CAdjRCb * gamma_curve_r100[gamma].OvGammaCont; - OvRCr = CAdjRCr * gamma_curve_r100[gamma].OvGammaCont; - OvGCb = CAdjGCb * gamma_curve_r100[gamma].OvGammaCont; - OvGCr = CAdjGCr * gamma_curve_r100[gamma].OvGammaCont; - OvBCb = CAdjBCb * gamma_curve_r100[gamma].OvGammaCont; - OvBCr = CAdjBCr * gamma_curve_r100[gamma].OvGammaCont; - OvROff = RedAdj + CAdjOff * gamma_curve_r100[gamma].OvGammaCont - - OvLuma * Loff - (OvRCb + OvRCr) * Coff; - OvGOff = GreenAdj + CAdjOff * gamma_curve_r100[gamma].OvGammaCont - - OvLuma * Loff - (OvGCb + OvGCr) * Coff; - OvBOff = BlueAdj + CAdjOff * gamma_curve_r100[gamma].OvGammaCont - - OvLuma * Loff - (OvBCb + OvBCr) * Coff; -#if 0 /* default constants */ - OvROff = -888.5; - OvGOff = 545; - OvBOff = -1104; #endif - OvROff = ClipValue(OvROff, -2048.0, 2047.5); - OvGOff = ClipValue(OvGOff, -2048.0, 2047.5); - OvBOff = ClipValue(OvBOff, -2048.0, 2047.5); - dwOvROff = ((INT32)(OvROff * 2.0)) & 0x1fff; - dwOvGOff = ((INT32)(OvGOff * 2.0)) & 0x1fff; - dwOvBOff = ((INT32)(OvBOff * 2.0)) & 0x1fff; - - if(info->ChipFamily == CHIP_FAMILY_RADEON) - { - dwOvLuma =(((INT32)(OvLuma * 2048.0))&0x7fff)<<17; - dwOvRCb = (((INT32)(OvRCb * 2048.0))&0x7fff)<<1; - dwOvRCr = (((INT32)(OvRCr * 2048.0))&0x7fff)<<17; - dwOvGCb = (((INT32)(OvGCb * 2048.0))&0x7fff)<<1; - dwOvGCr = (((INT32)(OvGCr * 2048.0))&0x7fff)<<17; - dwOvBCb = (((INT32)(OvBCb * 2048.0))&0x7fff)<<1; - dwOvBCr = (((INT32)(OvBCr * 2048.0))&0x7fff)<<17; - } - else - { - dwOvLuma = (((INT32)(OvLuma * 256.0))&0xfff)<<20; - dwOvRCb = (((INT32)(OvRCb * 256.0))&0xfff)<<4; - dwOvRCr = (((INT32)(OvRCr * 256.0))&0xfff)<<20; - dwOvGCb = (((INT32)(OvGCb * 256.0))&0xfff)<<4; - dwOvGCr = (((INT32)(OvGCr * 256.0))&0xfff)<<20; - dwOvBCb = (((INT32)(OvBCb * 256.0))&0xfff)<<4; - dwOvBCr = (((INT32)(OvBCr * 256.0))&0xfff)<<20; - } - - /* set gamma */ - RADEONSetOverlayGamma(pScrn, gamma); - - /* color transforms */ - OUTREG(RADEON_OV0_LIN_TRANS_A, dwOvRCb | dwOvLuma); - OUTREG(RADEON_OV0_LIN_TRANS_B, dwOvROff | dwOvRCr); - OUTREG(RADEON_OV0_LIN_TRANS_C, dwOvGCb | dwOvLuma); - OUTREG(RADEON_OV0_LIN_TRANS_D, dwOvGOff | dwOvGCr); - OUTREG(RADEON_OV0_LIN_TRANS_E, dwOvBCb | dwOvLuma); - OUTREG(RADEON_OV0_LIN_TRANS_F, dwOvBOff | dwOvBCr); -} - -static void RADEONSetOverlayAlpha(ScrnInfoPtr pScrn, int ov_alpha, int gr_alpha, int alpha_mode) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - if (alpha_mode == 0) { /* key mode */ - OUTREG(RADEON_OV0_KEY_CNTL, - RADEON_GRAPHIC_KEY_FN_EQ | /* what does this do? */ - RADEON_VIDEO_KEY_FN_FALSE | /* what does this do? */ - RADEON_CMP_MIX_OR); - /* crtc 1 */ - OUTREG(RADEON_DISP_MERGE_CNTL, - (RADEON_DISP_ALPHA_MODE_KEY & - RADEON_DISP_ALPHA_MODE_MASK) | - ((gr_alpha << 0x00000010) & - RADEON_DISP_GRPH_ALPHA_MASK) | - ((ov_alpha << 0x00000018) & - RADEON_DISP_OV0_ALPHA_MASK)); - /* crtc 2 */ - OUTREG(RADEON_DISP2_MERGE_CNTL, - (RADEON_DISP_ALPHA_MODE_KEY & - RADEON_DISP_ALPHA_MODE_MASK) | - ((gr_alpha << 0x00000010) & - RADEON_DISP_GRPH_ALPHA_MASK) | - ((ov_alpha << 0x00000018) & - RADEON_DISP_OV0_ALPHA_MASK)); - } else { /* global mode */ - OUTREG(RADEON_OV0_KEY_CNTL, - RADEON_GRAPHIC_KEY_FN_FALSE | /* what does this do? */ - RADEON_VIDEO_KEY_FN_FALSE | /* what does this do? */ - RADEON_CMP_MIX_AND); - /* crtc 2 */ - OUTREG(RADEON_DISP2_MERGE_CNTL, - (RADEON_DISP_ALPHA_MODE_GLOBAL & - RADEON_DISP_ALPHA_MODE_MASK) | - ((gr_alpha << 0x00000010) & - RADEON_DISP_GRPH_ALPHA_MASK) | - ((ov_alpha << 0x00000018) & - RADEON_DISP_OV0_ALPHA_MASK)); - /* crtc 1 */ - OUTREG(RADEON_DISP_MERGE_CNTL, - (RADEON_DISP_ALPHA_MODE_GLOBAL & - RADEON_DISP_ALPHA_MODE_MASK) | - ((gr_alpha << 0x00000010) & - RADEON_DISP_GRPH_ALPHA_MASK) | - ((ov_alpha << 0x00000018) & - RADEON_DISP_OV0_ALPHA_MASK)); - } - /* per-pixel mode - RADEON_DISP_ALPHA_MODE_PER_PIXEL */ - /* not yet supported */ -} - -static void RADEONSetColorKey(ScrnInfoPtr pScrn, uint32_t colorKey) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - uint32_t min, max; - uint8_t r, g, b; - - if (info->CurrentLayout.depth > 8) - { - uint32_t rbits, gbits, bbits; - - rbits = (colorKey & pScrn->mask.red) >> pScrn->offset.red; - gbits = (colorKey & pScrn->mask.green) >> pScrn->offset.green; - bbits = (colorKey & pScrn->mask.blue) >> pScrn->offset.blue; - - r = rbits << (8 - pScrn->weight.red); - g = gbits << (8 - pScrn->weight.green); - b = bbits << (8 - pScrn->weight.blue); - } - else - { - uint32_t bits; - - bits = colorKey & ((1 << info->CurrentLayout.depth) - 1); - r = bits; - g = bits; - b = bits; - } - min = (r << 16) | (g << 8) | (b); - max = (0xff << 24) | (r << 16) | (g << 8) | (b); - - RADEONWaitForFifo(pScrn, 2); - OUTREG(RADEON_OV0_GRAPHICS_KEY_CLR_HIGH, max); - OUTREG(RADEON_OV0_GRAPHICS_KEY_CLR_LOW, min); -} - -void -RADEONResetVideo(ScrnInfoPtr pScrn) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - RADEONPortPrivPtr pPriv = info->adaptor->pPortPrivates[0].ptr; - char tmp[200]; - - /* this function is called from ScreenInit. pScreen is used - by XAA internally, but not valid until ScreenInit finishs. - */ - if (info->accelOn && pScrn->pScreen) - RADEON_SYNC(info, pScrn); - - /* this is done here because each time the server is reset these - could change.. Otherwise they remain constant */ - xvInstanceID = MAKE_ATOM("XV_INSTANCE_ID"); - xvDeviceID = MAKE_ATOM("XV_DEVICE_ID"); - xvLocationID = MAKE_ATOM("XV_LOCATION_ID"); - xvDumpStatus = MAKE_ATOM("XV_DUMP_STATUS"); - - xvBrightness = MAKE_ATOM("XV_BRIGHTNESS"); - xvSaturation = MAKE_ATOM("XV_SATURATION"); - xvColor = MAKE_ATOM("XV_COLOR"); - xvContrast = MAKE_ATOM("XV_CONTRAST"); - xvColorKey = MAKE_ATOM("XV_COLORKEY"); - xvDoubleBuffer = MAKE_ATOM("XV_DOUBLE_BUFFER"); - xvHue = MAKE_ATOM("XV_HUE"); - xvRedIntensity = MAKE_ATOM("XV_RED_INTENSITY"); - xvGreenIntensity = MAKE_ATOM("XV_GREEN_INTENSITY"); - xvBlueIntensity = MAKE_ATOM("XV_BLUE_INTENSITY"); - xvGamma = MAKE_ATOM("XV_GAMMA"); - xvColorspace = MAKE_ATOM("XV_COLORSPACE"); - - xvAutopaintColorkey = MAKE_ATOM("XV_AUTOPAINT_COLORKEY"); - xvSetDefaults = MAKE_ATOM("XV_SET_DEFAULTS"); - xvCRTC = MAKE_ATOM("XV_CRTC"); - - xvOvAlpha = MAKE_ATOM("XV_OVERLAY_ALPHA"); - xvGrAlpha = MAKE_ATOM("XV_GRAPHICS_ALPHA"); - xvAlphaMode = MAKE_ATOM("XV_ALPHA_MODE"); - - xvOverlayDeinterlacingMethod = MAKE_ATOM("XV_OVERLAY_DEINTERLACING_METHOD"); - - xvDecBrightness = MAKE_ATOM("XV_DEC_BRIGHTNESS"); - xvDecSaturation = MAKE_ATOM("XV_DEC_SATURATION"); - xvDecColor = MAKE_ATOM("XV_DEC_COLOR"); - xvDecContrast = MAKE_ATOM("XV_DEC_CONTRAST"); - xvDecHue = MAKE_ATOM("XV_DEC_HUE"); - - xvEncoding = MAKE_ATOM("XV_ENCODING"); - xvFrequency = MAKE_ATOM("XV_FREQ"); - xvTunerStatus = MAKE_ATOM("XV_TUNER_STATUS"); - xvVolume = MAKE_ATOM("XV_VOLUME"); - xvMute = MAKE_ATOM("XV_MUTE"); - xvSAP = MAKE_ATOM("XV_SAP"); - - xvAdjustment = MAKE_ATOM("XV_DEBUG_ADJUSTMENT"); - - sprintf(tmp, "RXXX:%d.%d.%d", PCI_DEV_VENDOR_ID(info->PciInfo), - PCI_DEV_DEVICE_ID(info->PciInfo), PCI_DEV_REVISION(info->PciInfo)); - pPriv->device_id = MAKE_ATOM(tmp); - sprintf(tmp, "PCI:%02d:%02d.%d", PCI_DEV_BUS(info->PciInfo), - PCI_DEV_DEV(info->PciInfo), PCI_DEV_FUNC(info->PciInfo)); - pPriv->location_id = MAKE_ATOM(tmp); - sprintf(tmp, "INSTANCE:%d", pScrn->scrnIndex); - pPriv->instance_id = MAKE_ATOM(tmp); - - OUTREG(RADEON_OV0_SCALE_CNTL, RADEON_SCALER_SOFT_RESET); - OUTREG(RADEON_OV0_AUTO_FLIP_CNTL, 0); /* maybe */ - OUTREG(RADEON_OV0_EXCLUSIVE_HORZ, 0); - OUTREG(RADEON_OV0_FILTER_CNTL, RADEON_FILTER_PROGRAMMABLE_COEF); - OUTREG(RADEON_OV0_KEY_CNTL, RADEON_GRAPHIC_KEY_FN_EQ | - RADEON_VIDEO_KEY_FN_FALSE | - RADEON_CMP_MIX_OR); - OUTREG(RADEON_OV0_TEST, 0); - OUTREG(RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); - OUTREG(RADEON_CAP0_TRIG_CNTL, 0); - RADEONSetColorKey(pScrn, pPriv->colorKey); - - if (info->ChipFamily == CHIP_FAMILY_RADEON) { - - OUTREG(RADEON_OV0_LIN_TRANS_A, 0x12a00000); - OUTREG(RADEON_OV0_LIN_TRANS_B, 0x1990190e); - OUTREG(RADEON_OV0_LIN_TRANS_C, 0x12a0f9c0); - OUTREG(RADEON_OV0_LIN_TRANS_D, 0xf3000442); - OUTREG(RADEON_OV0_LIN_TRANS_E, 0x12a02040); - OUTREG(RADEON_OV0_LIN_TRANS_F, 0x175f); - - } else { - - OUTREG(RADEON_OV0_LIN_TRANS_A, 0x12a20000); - OUTREG(RADEON_OV0_LIN_TRANS_B, 0x198a190e); - OUTREG(RADEON_OV0_LIN_TRANS_C, 0x12a2f9da); - OUTREG(RADEON_OV0_LIN_TRANS_D, 0xf2fe0442); - OUTREG(RADEON_OV0_LIN_TRANS_E, 0x12a22046); - OUTREG(RADEON_OV0_LIN_TRANS_F, 0x175f); - } - /* - * Set default Gamma ramp: - * - * Of 18 segments for gamma curve, all segments in R200 (and - * newer) are programmable, while only lower 4 and upper 2 - * segments are programmable in the older Radeons. - */ - - RADEONSetOverlayGamma(pScrn, 0); /* gamma = 1.0 */ - - if(pPriv->VIP!=NULL){ - RADEONVIP_reset(pScrn,pPriv); - } - - if(pPriv->theatre != NULL) { - xf86_InitTheatre(pPriv->theatre); -/* xf86_ResetTheatreRegsForNoTVout(pPriv->theatre); */ - } - - if(pPriv->i2c != NULL){ - RADEONResetI2C(pScrn, pPriv); - } -} - -static void RADEONSetupTheatre(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONPLLPtr pll = &(info->pll); - TheatrePtr t; - - uint8_t a; - int i; - - pPriv->theatre = NULL; - - if(!info->MM_TABLE_valid && - !((info->RageTheatreCrystal>=0) && - (info->RageTheatreTunerPort>=0) && (info->RageTheatreCompositePort>=0) && - (info->RageTheatreSVideoPort>=0))) - { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "no multimedia table present, disabling Rage Theatre.\n"); - return; - } - - /* Go and find Rage Theatre, if it exists */ - - if (info->IsMobility) - xf86DrvMsg(pScrn->scrnIndex,X_INFO,"Detected Radeon Mobility, not scanning for Rage Theatre\n"); - else - pPriv->theatre=xf86_DetectTheatre(pPriv->VIP); - - if(pPriv->theatre==NULL)return; - - /* just a matter of convenience */ - t=pPriv->theatre; - - t->video_decoder_type=info->video_decoder_type; - - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "video decoder type is 0x%04x (BIOS value) versus 0x%04x (current PLL setting)\n", - t->video_decoder_type, pll->xclk); - - if(info->MM_TABLE_valid){ - for(i=0;i<5;i++){ - a=info->MM_TABLE.input[i]; - - switch(a & 0x3){ - case 1: - t->wTunerConnector=i; - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Tuner is on port %d\n",i); - break; - case 2: if(a & 0x4){ - t->wComp0Connector=RT_COMP2; - } else { - t->wComp0Connector=RT_COMP1; - } - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Composite connector is port %u\n", (unsigned)t->wComp0Connector); - break; - case 3: if(a & 0x4){ - t->wSVideo0Connector=RT_YCR_COMP4; - } else { - t->wSVideo0Connector=RT_YCF_COMP4; - } - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "SVideo connector is port %u\n", (unsigned)t->wSVideo0Connector); - break; - default: - break; - } - } - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Rage Theatre: Connectors (detected): tuner=%u, composite=%u, svideo=%u\n", - (unsigned)t->wTunerConnector, (unsigned)t->wComp0Connector, (unsigned)t->wSVideo0Connector); - - } - - if(info->RageTheatreTunerPort>=0)t->wTunerConnector=info->RageTheatreTunerPort; - if(info->RageTheatreCompositePort>=0)t->wComp0Connector=info->RageTheatreCompositePort; - if(info->RageTheatreSVideoPort>=0)t->wSVideo0Connector=info->RageTheatreSVideoPort; - - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "RageTheatre: Connectors (using): tuner=%u, composite=%u, svideo=%u\n", - (unsigned)t->wTunerConnector, (unsigned)t->wComp0Connector, (unsigned)t->wSVideo0Connector); - - switch((info->RageTheatreCrystal>=0)?info->RageTheatreCrystal:pll->reference_freq){ - case 2700: - t->video_decoder_type=RT_FREF_2700; - break; - case 2950: - t->video_decoder_type=RT_FREF_2950; - break; - default: - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Unsupported reference clock frequency, Rage Theatre disabled\n"); - t->theatre_num=-1; - free(pPriv->theatre); - pPriv->theatre = NULL; - return; - } - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "video decoder type used: 0x%04x\n", t->video_decoder_type); -} - -static XF86VideoAdaptorPtr -RADEONAllocAdaptor(ScrnInfoPtr pScrn) -{ - XF86VideoAdaptorPtr adapt; - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONPortPrivPtr pPriv; - uint32_t dot_clock; - int ecp; - - if(!(adapt = xf86XVAllocateVideoAdaptorRec(pScrn))) - return NULL; - - if(!(pPriv = calloc(1, sizeof(RADEONPortPrivRec) + sizeof(DevUnion)))) - { - free(adapt); - return NULL; - } - - adapt->pPortPrivates = (DevUnion*)(&pPriv[1]); - adapt->pPortPrivates[0].ptr = (pointer)pPriv; - - pPriv->colorKey = info->videoKey; - pPriv->doubleBuffer = TRUE; - pPriv->videoStatus = 0; - pPriv->brightness = 0; - pPriv->transform_index = 0; - pPriv->saturation = 0; - pPriv->contrast = 0; - pPriv->red_intensity = 0; - pPriv->green_intensity = 0; - pPriv->blue_intensity = 0; - pPriv->hue = 0; - pPriv->currentBuffer = 0; - pPriv->autopaint_colorkey = TRUE; - pPriv->gamma = 1000; - pPriv->desired_crtc = NULL; - - pPriv->ov_alpha = 255; - pPriv->gr_alpha = 255; - pPriv->alpha_mode = 0; - - /* TV-in stuff */ - pPriv->video_stream_active = FALSE; - pPriv->encoding = 4; - pPriv->frequency = 1000; - pPriv->volume = -1000; - pPriv->mute = TRUE; - pPriv->v = 0; - pPriv->overlay_deinterlacing_method = METHOD_BOB; - pPriv->capture_vbi_data = 0; - pPriv->dec_brightness = 0; - pPriv->dec_saturation = 0; - pPriv->dec_contrast = 0; - pPriv->dec_hue = 0; - - - /* - * Unlike older Mach64 chips, RADEON has only two ECP settings: - * 0 for PIXCLK < 175Mhz, and 1 (divide by 2) - * for higher clocks, sure makes life nicer - */ - dot_clock = info->ModeReg->dot_clock_freq; - - if (dot_clock < 17500) - info->ecp_div = 0; - else - info->ecp_div = 1; - ecp = (INPLL(pScrn, RADEON_VCLK_ECP_CNTL) & 0xfffffCff) | (info->ecp_div << 8); - - if (info->IsIGP) { - /* Force the overlay clock on for integrated chips - */ - ecp |= (1<<18); - } - - OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, ecp); - - - /* Decide on tuner type */ - if((info->tunerType<0) && (info->MM_TABLE_valid)) { - pPriv->tuner_type = info->MM_TABLE.tuner_type; - } else - pPriv->tuner_type = info->tunerType; - - /* Initialize I2C bus */ - RADEONInitI2C(pScrn, pPriv); - if(pPriv->i2c != NULL)RADEON_board_setmisc(pPriv); - - - #if 0 /* this is just here for easy debugging - normally off */ - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Scanning I2C Bus\n"); - for(i=0;i<255;i+=2) - if(RADEONProbeAddress(pPriv->i2c, i)) - xf86DrvMsg(pScrn->scrnIndex, X_INFO, " found device at address 0x%02x\n", i); - #endif - - /* resetting the VIP bus causes problems with some mobility chips. - * we don't support video in on any mobility chips at the moment anyway - */ - /* Initialize VIP bus */ - if (!info->IsMobility) - RADEONVIP_init(pScrn, pPriv); - - info->adaptor = adapt; - info->xv_max_width = 2047; - info->xv_max_height = 2047; - - if(!xf86LoadSubModule(pScrn,"theatre_detect")) - { - xf86DrvMsg(pScrn->scrnIndex,X_ERROR,"Unable to load Rage Theatre detect module\n"); - goto skip_theatre; - } - RADEONSetupTheatre(pScrn, pPriv); - - /* - * Now load the correspondind theatre chip based on what has been detected. - */ - if (pPriv->theatre) - { - xf86DrvMsg(pScrn->scrnIndex,X_INFO,"Going to load the corresponding theatre module\n"); - switch (pPriv->theatre->theatre_id) - { - case RT100_ATI_ID: - { - if(!xf86LoadSubModule(pScrn,"theatre")) - { - xf86DrvMsg(pScrn->scrnIndex,X_ERROR,"Unable to load Rage Theatre module\n"); - free(pPriv->theatre); - goto skip_theatre; - } - break; - } - case RT200_ATI_ID: - { - if(!xf86LoadSubModule(pScrn,"theatre200")) - { - xf86DrvMsg(pScrn->scrnIndex,X_ERROR,"Unable to load Rage Theatre module\n"); - free(pPriv->theatre); - goto skip_theatre; - } - pPriv->theatre->microc_path = info->RageTheatreMicrocPath; - pPriv->theatre->microc_type = info->RageTheatreMicrocType; - break; - } - default: - { - xf86DrvMsg(pScrn->scrnIndex,X_ERROR,"Unknown Theatre chip\n"); - free(pPriv->theatre); - goto skip_theatre; - } - } - } - - if(pPriv->theatre!=NULL) - { - xf86_InitTheatre(pPriv->theatre); - if(pPriv->theatre->mode == MODE_UNINITIALIZED) - { - free(pPriv->theatre); - pPriv->theatre = NULL; - xf86DrvMsg(pScrn->scrnIndex,X_INFO,"Rage Theatre disabled\n"); - /* Here the modules must be unloaded */ - goto skip_theatre; - } - } - - if(pPriv->theatre!=NULL){ - xf86_ResetTheatreRegsForNoTVout(pPriv->theatre); - xf86_RT_SetTint(pPriv->theatre, pPriv->dec_hue); - xf86_RT_SetSaturation(pPriv->theatre, pPriv->dec_saturation); - xf86_RT_SetSharpness(pPriv->theatre, RT_NORM_SHARPNESS); - xf86_RT_SetContrast(pPriv->theatre, pPriv->dec_contrast); - xf86_RT_SetBrightness(pPriv->theatre, pPriv->dec_brightness); - - RADEON_RT_SetEncoding(pScrn, pPriv); - } - -skip_theatre: - - return adapt; -} - -static XF86VideoAdaptorPtr -RADEONSetupImageVideo(ScreenPtr pScreen) -{ - ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); - RADEONPortPrivPtr pPriv; - XF86VideoAdaptorPtr adapt; - - if(!(adapt = RADEONAllocAdaptor(pScrn))) - return NULL; - - adapt->type = XvWindowMask | XvInputMask | XvImageMask; - adapt->flags = VIDEO_OVERLAID_IMAGES /*| VIDEO_CLIP_TO_VIEWPORT*/; - adapt->name = "ATI Radeon Video Overlay"; - adapt->nEncodings = 1; - adapt->pEncodings = &DummyEncoding; - adapt->nFormats = NUM_FORMATS; - adapt->pFormats = Formats; - adapt->nPorts = 1; - adapt->nAttributes = NUM_ATTRIBUTES; - adapt->pAttributes = Attributes; - adapt->nImages = NUM_IMAGES; - adapt->pImages = Images; - adapt->PutVideo = NULL; - adapt->PutStill = NULL; - adapt->GetVideo = NULL; - adapt->GetStill = NULL; - adapt->StopVideo = RADEONStopVideo; - adapt->SetPortAttribute = RADEONSetPortAttribute; - adapt->GetPortAttribute = RADEONGetPortAttribute; - adapt->QueryBestSize = RADEONQueryBestSize; - adapt->PutImage = RADEONPutImage; - adapt->QueryImageAttributes = RADEONQueryImageAttributes; - - pPriv = (RADEONPortPrivPtr)(adapt->pPortPrivates[0].ptr); - REGION_NULL(pScreen, &(pPriv->clip)); - - pPriv->textured = FALSE; - - if(pPriv->theatre != NULL) { - /* video decoder is present, extend capabilities */ - adapt->nEncodings = 13; - adapt->pEncodings = InputVideoEncodings; - adapt->type |= XvVideoMask; - adapt->nAttributes = NUM_DEC_ATTRIBUTES; - adapt->PutVideo = RADEONPutVideo; - } - - RADEONResetVideo(pScrn); - - return adapt; -} - void RADEONFreeVideoMemory(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) { - RADEONInfoPtr info = RADEONPTR(pScrn); - if (pPriv->video_memory != NULL) { radeon_legacy_free_memory(pScrn, pPriv->video_memory); pPriv->video_memory = NULL; - if (info->cs && pPriv->textured) { + if (pPriv->textured) { pPriv->src_bo[0] = NULL; radeon_legacy_free_memory(pScrn, pPriv->src_bo[1]); pPriv->src_bo[1] = NULL; @@ -1716,8 +356,6 @@ RADEONFreeVideoMemory(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) void RADEONStopVideo(ScrnInfoPtr pScrn, pointer data, Bool cleanup) { - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)data; if (pPriv->textured) { @@ -1726,394 +364,6 @@ RADEONStopVideo(ScrnInfoPtr pScrn, pointer data, Bool cleanup) } return; } - - REGION_EMPTY(pScrn->pScreen, &pPriv->clip); - - if(cleanup) { - if(pPriv->videoStatus & CLIENT_VIDEO_ON) { - RADEONWaitForFifo(pScrn, 2); - OUTREG(RADEON_OV0_SCALE_CNTL, 0); - } - if(pPriv->video_stream_active){ - RADEONWaitForFifo(pScrn, 2); - OUTREG(RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); - OUTREG(RADEON_CAP0_TRIG_CNTL, 0); - RADEONResetVideo(pScrn); - pPriv->video_stream_active = FALSE; - if(pPriv->msp3430 != NULL) xf86_MSP3430SetVolume(pPriv->msp3430, MSP3430_FAST_MUTE); - if(pPriv->uda1380 != NULL) xf86_uda1380_mute(pPriv->uda1380, TRUE); - if(pPriv->i2c != NULL) RADEON_board_setmisc(pPriv); - } - RADEONFreeVideoMemory(pScrn, pPriv); - pPriv->videoStatus = 0; - } else { - if(pPriv->videoStatus & CLIENT_VIDEO_ON) { - pPriv->videoStatus |= OFF_TIMER; - pPriv->offTime = currentTime.milliseconds + OFF_DELAY; - } - } -} - -int -RADEONSetPortAttribute(ScrnInfoPtr pScrn, - Atom attribute, - INT32 value, - pointer data) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)data; - Bool setTransform = FALSE; - Bool setAlpha = FALSE; - unsigned char *RADEONMMIO = info->MMIO; - - RADEON_SYNC(info, pScrn); - - if(attribute == xvAutopaintColorkey) - { - pPriv->autopaint_colorkey = ClipValue (value, 0, 1); - } - else if(attribute == xvSetDefaults) - { - pPriv->autopaint_colorkey = TRUE; - pPriv->brightness = 0; - pPriv->saturation = 0; - pPriv->contrast = 0; - pPriv->hue = 0; - pPriv->red_intensity = 0; - pPriv->green_intensity = 0; - pPriv->blue_intensity = 0; - pPriv->gamma = 1000; - pPriv->transform_index = 0; - pPriv->doubleBuffer = FALSE; - pPriv->ov_alpha = 255; - pPriv->gr_alpha = 255; - pPriv->alpha_mode = 0; - - /* It is simpler to call itself */ - RADEONSetPortAttribute(pScrn, xvDecBrightness, 0, data); - RADEONSetPortAttribute(pScrn, xvDecSaturation, 0, data); - RADEONSetPortAttribute(pScrn, xvDecContrast, 0, data); - RADEONSetPortAttribute(pScrn, xvDecHue, 0, data); - - RADEONSetPortAttribute(pScrn, xvVolume, -1000, data); - RADEONSetPortAttribute(pScrn, xvMute, 1, data); - RADEONSetPortAttribute(pScrn, xvSAP, 0, data); - RADEONSetPortAttribute(pScrn, xvDoubleBuffer, 1, data); - - setTransform = TRUE; - setAlpha = TRUE; - } - else if(attribute == xvBrightness) - { - pPriv->brightness = ClipValue (value, -1000, 1000); - setTransform = TRUE; - } - else if((attribute == xvSaturation) || (attribute == xvColor)) - { - pPriv->saturation = ClipValue (value, -1000, 1000); - setTransform = TRUE; - } - else if(attribute == xvContrast) - { - pPriv->contrast = ClipValue (value, -1000, 1000); - setTransform = TRUE; - } - else if(attribute == xvHue) - { - pPriv->hue = ClipValue (value, -1000, 1000); - setTransform = TRUE; - } - else if(attribute == xvRedIntensity) - { - pPriv->red_intensity = ClipValue (value, -1000, 1000); - setTransform = TRUE; - } - else if(attribute == xvGreenIntensity) - { - pPriv->green_intensity = ClipValue (value, -1000, 1000); - setTransform = TRUE; - } - else if(attribute == xvBlueIntensity) - { - pPriv->blue_intensity = ClipValue (value, -1000, 1000); - setTransform = TRUE; - } - else if(attribute == xvGamma) - { - pPriv->gamma = ClipValue (value, 100, 10000); - setTransform = TRUE; - } - else if(attribute == xvColorspace) - { - pPriv->transform_index = ClipValue (value, 0, 1); - setTransform = TRUE; - } - else if(attribute == xvDoubleBuffer) - { - pPriv->doubleBuffer = ClipValue (value, 0, 1); - } - else if(attribute == xvColorKey) - { - pPriv->colorKey = value; - RADEONSetColorKey (pScrn, pPriv->colorKey); - REGION_EMPTY(pScrn->pScreen, &pPriv->clip); - } - else if(attribute == xvCRTC) - { - xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); - if ((value < -1) || (value > xf86_config->num_crtc)) - return BadValue; - if (value < 0) - pPriv->desired_crtc = NULL; - else - pPriv->desired_crtc = xf86_config->crtc[value]; - } - else if(attribute == xvOvAlpha) - { - pPriv->ov_alpha = ClipValue (value, 0, 255); - setAlpha = TRUE; - } - else if(attribute == xvGrAlpha) - { - pPriv->gr_alpha = ClipValue (value, 0, 255); - setAlpha = TRUE; - } - else if(attribute == xvAlphaMode) - { - pPriv->alpha_mode = ClipValue (value, 0, 1); - setAlpha = TRUE; - } - else if(attribute == xvDecBrightness) - { - pPriv->dec_brightness = value; - if(pPriv->theatre!=NULL) xf86_RT_SetBrightness(pPriv->theatre, pPriv->dec_brightness); - } - else if((attribute == xvDecSaturation) || (attribute == xvDecColor)) - { - if(value<-1000)value = -1000; - if(value>1000)value = 1000; - pPriv->dec_saturation = value; - if(pPriv->theatre != NULL)xf86_RT_SetSaturation(pPriv->theatre, value); - } - else if(attribute == xvDecContrast) - { - pPriv->dec_contrast = value; - if(pPriv->theatre != NULL)xf86_RT_SetContrast(pPriv->theatre, value); - } - else if(attribute == xvDecHue) - { - pPriv->dec_hue = value; - if(pPriv->theatre != NULL)xf86_RT_SetTint(pPriv->theatre, value); - } - else if(attribute == xvEncoding) - { - pPriv->encoding = value; - if(pPriv->video_stream_active) - { - if(pPriv->theatre != NULL) RADEON_RT_SetEncoding(pScrn, pPriv); - if(pPriv->msp3430 != NULL) RADEON_MSP_SetEncoding(pPriv); - if(pPriv->tda9885 != NULL) RADEON_TDA9885_SetEncoding(pPriv); - if(pPriv->fi1236 != NULL) RADEON_FI1236_SetEncoding(pPriv); - if(pPriv->i2c != NULL) RADEON_board_setmisc(pPriv); - /* put more here to actually change it */ - } - } - else if(attribute == xvFrequency) - { - pPriv->frequency = value; - /* mute volume if it was not muted before */ - if((pPriv->msp3430!=NULL)&& !pPriv->mute)xf86_MSP3430SetVolume(pPriv->msp3430, MSP3430_FAST_MUTE); - if((pPriv->uda1380!=NULL)&& !pPriv->mute)xf86_uda1380_mute(pPriv->uda1380, TRUE); - if(pPriv->fi1236 != NULL) xf86_TUNER_set_frequency(pPriv->fi1236, value); -/* if(pPriv->theatre != NULL) RADEON_RT_SetEncoding(pScrn, pPriv); */ - if((pPriv->msp3430 != NULL) && (pPriv->msp3430->recheck)) - xf86_InitMSP3430(pPriv->msp3430); - if((pPriv->msp3430 != NULL)&& !pPriv->mute) xf86_MSP3430SetVolume(pPriv->msp3430, MSP3430_VOLUME(pPriv->volume)); - if((pPriv->uda1380 != NULL)&& !pPriv->mute) xf86_uda1380_setvolume(pPriv->uda1380, pPriv->volume); - } - else if(attribute == xvMute) - { - pPriv->mute = value; - if(pPriv->msp3430 != NULL) xf86_MSP3430SetVolume(pPriv->msp3430, pPriv->mute ? MSP3430_FAST_MUTE : MSP3430_VOLUME(pPriv->volume)); - if(pPriv->i2c != NULL) RADEON_board_setmisc(pPriv); - if(pPriv->uda1380 != NULL) xf86_uda1380_mute(pPriv->uda1380, pPriv->mute); - } - else if(attribute == xvSAP) - { - pPriv->sap_channel = value; - if(pPriv->msp3430 != NULL) xf86_MSP3430SetSAP(pPriv->msp3430, pPriv->sap_channel?4:3); - } - else if(attribute == xvVolume) - { - if(value<-1000)value = -1000; - if(value>1000)value = 1000; - pPriv->volume = value; - pPriv->mute = FALSE; - if(pPriv->msp3430 != NULL) xf86_MSP3430SetVolume(pPriv->msp3430, MSP3430_VOLUME(value)); - if(pPriv->i2c != NULL) RADEON_board_setmisc(pPriv); - if(pPriv->uda1380 != NULL) xf86_uda1380_setvolume(pPriv->uda1380, value); - } - else if(attribute == xvOverlayDeinterlacingMethod) - { - if(value<0)value = 0; - if(value>2)value = 2; - pPriv->overlay_deinterlacing_method = value; - switch(pPriv->overlay_deinterlacing_method){ - case METHOD_BOB: - OUTREG(RADEON_OV0_DEINTERLACE_PATTERN, 0xAAAAA); - break; - case METHOD_SINGLE: - OUTREG(RADEON_OV0_DEINTERLACE_PATTERN, 0xEEEEE | (9<<28)); - break; - case METHOD_WEAVE: - OUTREG(RADEON_OV0_DEINTERLACE_PATTERN, 0x0); - break; - default: - OUTREG(RADEON_OV0_DEINTERLACE_PATTERN, 0xAAAAA); - } - } - else if(attribute == xvDumpStatus) - { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Current mode flags 0x%08x: %s%s\n", - pScrn->currentMode->Flags, - pScrn->currentMode->Flags & V_INTERLACE ? " interlaced" : "" , - pScrn->currentMode->Flags & V_DBLSCAN ? " doublescan" : "" - ); - if(pPriv->tda9885 != NULL){ - xf86_tda9885_getstatus(pPriv->tda9885); - xf86_tda9885_dumpstatus(pPriv->tda9885); - } - if(pPriv->fi1236!=NULL){ - xf86_fi1236_dump_status(pPriv->fi1236); - } - } - else if(attribute == xvAdjustment) - { - pPriv->adjustment=value; - xf86DrvMsg(pScrn->scrnIndex,X_ERROR,"Setting pPriv->adjustment to %u\n", - (unsigned)pPriv->adjustment); - if(pPriv->tda9885!=0){ - pPriv->tda9885->top_adjustment=value; - RADEON_TDA9885_SetEncoding(pPriv); - } - } - else - return BadMatch; - - if (setTransform) - { - RADEONSetTransform(pScrn, - RTFBrightness(pPriv->brightness), - RTFContrast(pPriv->contrast), - RTFSaturation(pPriv->saturation), - RTFHue(pPriv->hue), - RTFIntensity(pPriv->red_intensity), - RTFIntensity(pPriv->green_intensity), - RTFIntensity(pPriv->blue_intensity), - pPriv->transform_index, - pPriv->gamma); - } - - if (setAlpha) - { - RADEONSetOverlayAlpha(pScrn, pPriv->ov_alpha, pPriv->gr_alpha, pPriv->alpha_mode); - } - - return Success; -} - -int -RADEONGetPortAttribute(ScrnInfoPtr pScrn, - Atom attribute, - INT32 *value, - pointer data) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)data; - - if (info->accelOn) RADEON_SYNC(info, pScrn); - - if(attribute == xvAutopaintColorkey) - *value = pPriv->autopaint_colorkey; - else if(attribute == xvBrightness) - *value = pPriv->brightness; - else if((attribute == xvSaturation) || (attribute == xvColor)) - *value = pPriv->saturation; - else if(attribute == xvContrast) - *value = pPriv->contrast; - else if(attribute == xvHue) - *value = pPriv->hue; - else if(attribute == xvRedIntensity) - *value = pPriv->red_intensity; - else if(attribute == xvGreenIntensity) - *value = pPriv->green_intensity; - else if(attribute == xvBlueIntensity) - *value = pPriv->blue_intensity; - else if(attribute == xvGamma) - *value = pPriv->gamma; - else if(attribute == xvColorspace) - *value = pPriv->transform_index; - else if(attribute == xvDoubleBuffer) - *value = pPriv->doubleBuffer ? 1 : 0; - else if(attribute == xvColorKey) - *value = pPriv->colorKey; - else if(attribute == xvCRTC) { - int c; - xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); - for (c = 0; c < xf86_config->num_crtc; c++) - if (xf86_config->crtc[c] == pPriv->desired_crtc) - break; - if (c == xf86_config->num_crtc) - c = -1; - *value = c; - } - else if(attribute == xvOvAlpha) - *value = pPriv->ov_alpha; - else if(attribute == xvGrAlpha) - *value = pPriv->gr_alpha; - else if(attribute == xvAlphaMode) - *value = pPriv->alpha_mode; - else if(attribute == xvDecBrightness) - *value = pPriv->dec_brightness; - else if((attribute == xvDecSaturation) || (attribute == xvDecColor)) - *value = pPriv->dec_saturation; - else if(attribute == xvDecContrast) - *value = pPriv->dec_contrast; - else if(attribute == xvDecHue) - *value = pPriv->dec_hue; - else if(attribute == xvEncoding) - *value = pPriv->encoding; - else if(attribute == xvFrequency) - *value = pPriv->frequency; - else - if(attribute == xvTunerStatus) { - if(pPriv->fi1236==NULL){ - *value=TUNER_OFF; - } else - { - *value = xf86_TUNER_get_afc_hint(pPriv->fi1236); - } - } - else if(attribute == xvMute) - *value = pPriv->mute; - else if(attribute == xvSAP) - *value = pPriv->sap_channel; - else if(attribute == xvVolume) - *value = pPriv->volume; - else if(attribute == xvOverlayDeinterlacingMethod) - *value = pPriv->overlay_deinterlacing_method; - else if(attribute == xvDeviceID) - *value = pPriv->device_id; - else if(attribute == xvLocationID) - *value = pPriv->location_id; - else if(attribute == xvInstanceID) - *value = pPriv->instance_id; - else if(attribute == xvAdjustment) - *value = pPriv->adjustment; - else - return BadMatch; - - return Success; } void @@ -2138,89 +388,6 @@ RADEONQueryBestSize( *p_h = drw_h; } -static struct { - double range; - signed char coeff[5][4]; - } TapCoeffs[]= - { - {0.25, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, - {0.26, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, - {0.27, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, - {0.28, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, - {0.29, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, - {0.30, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, - {0.31, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, - {0.32, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, - {0.33, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, - {0.34, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, - {0.35, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, - {0.36, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, - {0.37, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, - {0.38, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, - {0.39, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, - {0.40, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, - {0.41, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, - {0.42, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, - {0.43, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, - {0.44, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, - {0.45, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, - {0.46, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, - {0.47, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, - {0.48, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, - {0.49, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, - {0.50, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, - {0.51, {{ 7, 17, 8, 0}, { 6, 17, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 2, 14, 14, 2}, }}, - {0.52, {{ 7, 17, 8, 0}, { 6, 17, 9, 0}, { 5, 16, 11, 0}, { 3, 15, 13, 1}, { 2, 14, 14, 2}, }}, - {0.53, {{ 7, 17, 8, 0}, { 6, 17, 9, 0}, { 5, 16, 11, 0}, { 3, 15, 13, 1}, { 2, 14, 14, 2}, }}, - {0.54, {{ 7, 17, 8, 0}, { 6, 17, 9, 0}, { 4, 17, 11, 0}, { 3, 15, 13, 1}, { 2, 14, 14, 2}, }}, - {0.55, {{ 7, 18, 7, 0}, { 6, 17, 9, 0}, { 4, 17, 11, 0}, { 3, 15, 13, 1}, { 1, 15, 15, 1}, }}, - {0.56, {{ 7, 18, 7, 0}, { 5, 18, 9, 0}, { 4, 17, 11, 0}, { 2, 17, 13, 0}, { 1, 15, 15, 1}, }}, - {0.57, {{ 7, 18, 7, 0}, { 5, 18, 9, 0}, { 4, 17, 11, 0}, { 2, 17, 13, 0}, { 1, 15, 15, 1}, }}, - {0.58, {{ 7, 18, 7, 0}, { 5, 18, 9, 0}, { 4, 17, 11, 0}, { 2, 17, 13, 0}, { 1, 15, 15, 1}, }}, - {0.59, {{ 7, 18, 7, 0}, { 5, 18, 9, 0}, { 4, 17, 11, 0}, { 2, 17, 13, 0}, { 1, 15, 15, 1}, }}, - {0.60, {{ 7, 18, 8, -1}, { 6, 17, 10, -1}, { 4, 17, 11, 0}, { 2, 17, 13, 0}, { 1, 15, 15, 1}, }}, - {0.61, {{ 7, 18, 8, -1}, { 6, 17, 10, -1}, { 4, 17, 11, 0}, { 2, 17, 13, 0}, { 1, 15, 15, 1}, }}, - {0.62, {{ 7, 18, 8, -1}, { 6, 17, 10, -1}, { 4, 17, 11, 0}, { 2, 17, 13, 0}, { 1, 15, 15, 1}, }}, - {0.63, {{ 7, 18, 8, -1}, { 6, 17, 10, -1}, { 4, 17, 11, 0}, { 2, 17, 13, 0}, { 1, 15, 15, 1}, }}, - {0.64, {{ 7, 18, 8, -1}, { 6, 17, 10, -1}, { 4, 17, 12, -1}, { 2, 17, 13, 0}, { 1, 15, 15, 1}, }}, - {0.65, {{ 7, 18, 8, -1}, { 6, 17, 10, -1}, { 4, 17, 12, -1}, { 2, 17, 13, 0}, { 0, 16, 16, 0}, }}, - {0.66, {{ 7, 18, 8, -1}, { 6, 18, 10, -2}, { 4, 17, 12, -1}, { 2, 17, 13, 0}, { 0, 16, 16, 0}, }}, - {0.67, {{ 7, 20, 7, -2}, { 5, 19, 10, -2}, { 3, 18, 12, -1}, { 2, 17, 13, 0}, { 0, 16, 16, 0}, }}, - {0.68, {{ 7, 20, 7, -2}, { 5, 19, 10, -2}, { 3, 19, 12, -2}, { 1, 18, 14, -1}, { 0, 16, 16, 0}, }}, - {0.69, {{ 7, 20, 7, -2}, { 5, 19, 10, -2}, { 3, 19, 12, -2}, { 1, 18, 14, -1}, { 0, 16, 16, 0}, }}, - {0.70, {{ 7, 20, 7, -2}, { 5, 20, 9, -2}, { 3, 19, 12, -2}, { 1, 18, 14, -1}, { 0, 16, 16, 0}, }}, - {0.71, {{ 7, 20, 7, -2}, { 5, 20, 9, -2}, { 3, 19, 12, -2}, { 1, 18, 14, -1}, { 0, 16, 16, 0}, }}, - {0.72, {{ 7, 20, 7, -2}, { 5, 20, 9, -2}, { 2, 20, 12, -2}, { 0, 19, 15, -2}, {-1, 17, 17, -1}, }}, - {0.73, {{ 7, 20, 7, -2}, { 4, 21, 9, -2}, { 2, 20, 12, -2}, { 0, 19, 15, -2}, {-1, 17, 17, -1}, }}, - {0.74, {{ 6, 22, 6, -2}, { 4, 21, 9, -2}, { 2, 20, 12, -2}, { 0, 19, 15, -2}, {-1, 17, 17, -1}, }}, - {0.75, {{ 6, 22, 6, -2}, { 4, 21, 9, -2}, { 1, 21, 12, -2}, { 0, 19, 15, -2}, {-1, 17, 17, -1}, }}, - {0.76, {{ 6, 22, 6, -2}, { 4, 21, 9, -2}, { 1, 21, 12, -2}, { 0, 19, 15, -2}, {-1, 17, 17, -1}, }}, - {0.77, {{ 6, 22, 6, -2}, { 3, 22, 9, -2}, { 1, 22, 12, -3}, { 0, 19, 15, -2}, {-2, 18, 18, -2}, }}, - {0.78, {{ 6, 21, 6, -1}, { 3, 22, 9, -2}, { 1, 22, 12, -3}, { 0, 19, 15, -2}, {-2, 18, 18, -2}, }}, - {0.79, {{ 5, 23, 5, -1}, { 3, 22, 9, -2}, { 0, 23, 12, -3}, {-1, 21, 15, -3}, {-2, 18, 18, -2}, }}, - {0.80, {{ 5, 23, 5, -1}, { 3, 23, 8, -2}, { 0, 23, 12, -3}, {-1, 21, 15, -3}, {-2, 18, 18, -2}, }}, - {0.81, {{ 5, 23, 5, -1}, { 2, 24, 8, -2}, { 0, 23, 12, -3}, {-1, 21, 15, -3}, {-2, 18, 18, -2}, }}, - {0.82, {{ 5, 23, 5, -1}, { 2, 24, 8, -2}, { 0, 23, 12, -3}, {-1, 21, 15, -3}, {-3, 19, 19, -3}, }}, - {0.83, {{ 5, 23, 5, -1}, { 2, 24, 8, -2}, { 0, 23, 11, -2}, {-2, 22, 15, -3}, {-3, 19, 19, -3}, }}, - {0.84, {{ 4, 25, 4, -1}, { 1, 25, 8, -2}, { 0, 23, 11, -2}, {-2, 22, 15, -3}, {-3, 19, 19, -3}, }}, - {0.85, {{ 4, 25, 4, -1}, { 1, 25, 8, -2}, { 0, 23, 11, -2}, {-2, 22, 15, -3}, {-3, 19, 19, -3}, }}, - {0.86, {{ 4, 24, 4, 0}, { 1, 25, 7, -1}, {-1, 24, 11, -2}, {-2, 22, 15, -3}, {-3, 19, 19, -3}, }}, - {0.87, {{ 4, 24, 4, 0}, { 1, 25, 7, -1}, {-1, 24, 11, -2}, {-2, 22, 15, -3}, {-3, 19, 19, -3}, }}, - {0.88, {{ 3, 26, 3, 0}, { 0, 26, 7, -1}, {-1, 24, 11, -2}, {-3, 23, 15, -3}, {-3, 19, 19, -3}, }}, - {0.89, {{ 3, 26, 3, 0}, { 0, 26, 7, -1}, {-1, 24, 11, -2}, {-3, 23, 15, -3}, {-3, 19, 19, -3}, }}, - {0.90, {{ 3, 26, 3, 0}, { 0, 26, 7, -1}, {-2, 25, 11, -2}, {-3, 23, 15, -3}, {-3, 19, 19, -3}, }}, - {0.91, {{ 3, 26, 3, 0}, { 0, 27, 6, -1}, {-2, 25, 11, -2}, {-3, 23, 15, -3}, {-3, 19, 19, -3}, }}, - {0.92, {{ 2, 28, 2, 0}, { 0, 27, 6, -1}, {-2, 25, 11, -2}, {-3, 23, 15, -3}, {-3, 19, 19, -3}, }}, - {0.93, {{ 2, 28, 2, 0}, { 0, 26, 6, 0}, {-2, 25, 10, -1}, {-3, 23, 15, -3}, {-3, 19, 19, -3}, }}, - {0.94, {{ 2, 28, 2, 0}, { 0, 26, 6, 0}, {-2, 25, 10, -1}, {-3, 23, 15, -3}, {-3, 19, 19, -3}, }}, - {0.95, {{ 1, 30, 1, 0}, {-1, 28, 5, 0}, {-3, 26, 10, -1}, {-3, 23, 14, -2}, {-3, 19, 19, -3}, }}, - {0.96, {{ 1, 30, 1, 0}, {-1, 28, 5, 0}, {-3, 26, 10, -1}, {-3, 23, 14, -2}, {-3, 19, 19, -3}, }}, - {0.97, {{ 1, 30, 1, 0}, {-1, 28, 5, 0}, {-3, 26, 10, -1}, {-3, 23, 14, -2}, {-3, 19, 19, -3}, }}, - {0.98, {{ 1, 30, 1, 0}, {-2, 29, 5, 0}, {-3, 27, 9, -1}, {-3, 23, 14, -2}, {-3, 19, 19, -3}, }}, - {0.99, {{ 0, 32, 0, 0}, {-2, 29, 5, 0}, {-3, 27, 9, -1}, {-4, 24, 14, -2}, {-3, 19, 19, -3}, }}, - {1.00, {{ 0, 32, 0, 0}, {-2, 29, 5, 0}, {-3, 27, 9, -1}, {-4, 24, 14, -2}, {-3, 19, 19, -3}, }} - }; - void RADEONCopyData( ScrnInfoPtr pScrn, @@ -2232,61 +399,23 @@ RADEONCopyData( unsigned int w, unsigned int bpp ){ - RADEONInfoPtr info = RADEONPTR(pScrn); - /* Get the byte-swapping right for big endian systems */ if ( bpp == 2 ) { w *= 2; bpp = 1; } -#ifdef XF86DRI - - if ( info->directRenderingEnabled && info->DMAForXv ) - { - uint8_t *buf; - uint32_t bufPitch, dstPitchOff; - int x, y; - unsigned int hpass; - - RADEONHostDataParams( pScrn, dst, dstPitch, bpp, &dstPitchOff, &x, &y ); - - while ( (buf = RADEONHostDataBlit( pScrn, bpp, w, dstPitchOff, &bufPitch, - x, &y, &h, &hpass )) ) - { - RADEONHostDataBlitCopyPass( pScrn, bpp, buf, src, hpass, bufPitch, - srcPitch ); - src += hpass * srcPitch; - } - - FLUSH_RING(); - - return; - } - else -#endif /* XF86DRI */ { int swap = RADEON_HOST_DATA_SWAP_NONE; #if X_BYTE_ORDER == X_BIG_ENDIAN - if (info->kms_enabled) { - switch(bpp) { - case 2: - swap = RADEON_HOST_DATA_SWAP_16BIT; - break; - case 4: - swap = RADEON_HOST_DATA_SWAP_32BIT; - break; - } - } else { - switch (pScrn->bitsPerPixel) { - case 16: - swap = RADEON_HOST_DATA_SWAP_16BIT; - break; - case 32: - swap = RADEON_HOST_DATA_SWAP_32BIT; - break; - } + switch(bpp) { + case 2: + swap = RADEON_HOST_DATA_SWAP_16BIT; + break; + case 4: + swap = RADEON_HOST_DATA_SWAP_32BIT; + break; } #endif @@ -2304,98 +433,6 @@ RADEONCopyData( } } -static void -RADEONCopyRGB24Data( - ScrnInfoPtr pScrn, - unsigned char *src, - unsigned char *dst, - unsigned int srcPitch, - unsigned int dstPitch, - unsigned int h, - unsigned int w -){ - uint32_t *dptr; - uint8_t *sptr; - int i,j; - RADEONInfoPtr info = RADEONPTR(pScrn); -#ifdef XF86DRI - - if ( info->directRenderingEnabled && info->DMAForXv ) - { - uint32_t bufPitch, dstPitchOff; - int x, y; - unsigned int hpass; - - RADEONHostDataParams( pScrn, dst, dstPitch, 4, &dstPitchOff, &x, &y ); - - while ( (dptr = ( uint32_t* )RADEONHostDataBlit( pScrn, 4, w, dstPitchOff, - &bufPitch, x, &y, &h, - &hpass )) ) - { - for( j = 0; j < hpass; j++ ) - { - sptr = src; - - for ( i = 0 ; i < w; i++, sptr += 3 ) - { - dptr[i] = (sptr[2] << 16) | (sptr[1] << 8) | sptr[0]; - } - - src += srcPitch; - dptr += bufPitch / 4; - } - } - - FLUSH_RING(); - - return; - } - else -#endif /* XF86DRI */ - { -#if X_BYTE_ORDER == X_BIG_ENDIAN - unsigned char *RADEONMMIO = info->MMIO; - - if (!info->kms_enabled) - OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl & - ~(RADEON_NONSURF_AP0_SWP_16BPP | RADEON_NONSURF_AP0_SWP_32BPP)); -#endif - - for (j = 0; j < h; j++) { - dptr = (uint32_t *)(dst + j * dstPitch); - sptr = src + j * srcPitch; - - for (i = 0; i < w; i++, sptr += 3) { - dptr[i] = cpu_to_le32((sptr[2] << 16) | (sptr[1] << 8) | sptr[0]); - } - } - -#if X_BYTE_ORDER == X_BIG_ENDIAN - if (!info->kms_enabled) { - /* restore byte swapping */ - OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl); - } -#endif - } -} - - -#ifdef XF86DRI -static void RADEON_420_422( - unsigned int *d, - unsigned char *s1, - unsigned char *s2, - unsigned char *s3, - unsigned int n -) -{ - while ( n ) { - *(d++) = s1[0] | (s1[1] << 16) | (s3[0] << 8) | (s2[0] << 24); - s1+=2; s2++; s3++; - n--; - } -} -#endif void RADEONCopyMungedData( @@ -2410,739 +447,39 @@ RADEONCopyMungedData( unsigned int h, unsigned int w ){ - RADEONInfoPtr info = RADEONPTR(pScrn); -#ifdef XF86DRI - - if ( info->directRenderingEnabled && info->DMAForXv ) - { - uint8_t *buf; - uint32_t y = 0, bufPitch, dstPitchOff; - int blitX, blitY; - unsigned int hpass; - - /* XXX Fix endian flip on R300 */ - - RADEONHostDataParams( pScrn, dst1, dstPitch, 4, &dstPitchOff, &blitX, &blitY ); - - while ( (buf = RADEONHostDataBlit( pScrn, 4, w/2, dstPitchOff, &bufPitch, - blitX, &blitY, &h, &hpass )) ) - { - while ( hpass-- ) - { - RADEON_420_422( (unsigned int *) buf, src1, src2, src3, - bufPitch / 4 ); - src1 += srcPitch; - if ( y & 1 ) - { - src2 += srcPitch2; - src3 += srcPitch2; - } - buf += bufPitch; - y++; - } - } - - FLUSH_RING(); - } - else -#endif /* XF86DRI */ - { - uint32_t *dst; - uint8_t *s1, *s2, *s3; - int i, j; - -#if X_BYTE_ORDER == X_BIG_ENDIAN - unsigned char *RADEONMMIO = info->MMIO; - - if (!info->kms_enabled) - OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl & - ~(RADEON_NONSURF_AP0_SWP_16BPP | RADEON_NONSURF_AP0_SWP_32BPP)); -#endif - - w /= 2; - - for( j = 0; j < h; j++ ) - { - dst = (pointer)dst1; - s1 = src1; s2 = src2; s3 = src3; - i = w; - while( i > 4 ) - { - dst[0] = cpu_to_le32(s1[0] | (s1[1] << 16) | (s3[0] << 8) | (s2[0] << 24)); - dst[1] = cpu_to_le32(s1[2] | (s1[3] << 16) | (s3[1] << 8) | (s2[1] << 24)); - dst[2] = cpu_to_le32(s1[4] | (s1[5] << 16) | (s3[2] << 8) | (s2[2] << 24)); - dst[3] = cpu_to_le32(s1[6] | (s1[7] << 16) | (s3[3] << 8) | (s2[3] << 24)); - dst += 4; s2 += 4; s3 += 4; s1 += 8; - i -= 4; - } - while( i-- ) - { - dst[0] = cpu_to_le32(s1[0] | (s1[1] << 16) | (s3[0] << 8) | (s2[0] << 24)); - dst++; s2++; s3++; - s1 += 2; - } - - dst1 += dstPitch; - src1 += srcPitch; - if( j & 1 ) - { - src2 += srcPitch2; - src3 += srcPitch2; - } - } -#if X_BYTE_ORDER == X_BIG_ENDIAN - if (!info->kms_enabled) { - /* restore byte swapping */ - OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl); - } -#endif - } -} - -static void -RADEONDisplayVideo( - ScrnInfoPtr pScrn, - xf86CrtcPtr crtc, - RADEONPortPrivPtr pPriv, - int id, - int base_offset, - int offset1, int offset2, - int offset3, int offset4, - int offset5, int offset6, - short width, short height, - int pitch, - int left, int right, int top, - BoxPtr dstBox, - short src_w, short src_h, - short drw_w, short drw_h, - int deinterlacing_method -){ - RADEONInfoPtr info = RADEONPTR(pScrn); - xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - uint32_t v_inc, h_inc, h_inc_uv, step_by_y, step_by_uv, tmp; - double h_inc_d; - int p1_h_accum_init, p23_h_accum_init; - int p1_v_accum_init, p23_v_accum_init; - int p23_blank_lines; - int ecp_div; - int v_inc_shift; - int y_mult; - int x_off; - int y_off; - uint32_t scaler_src; - uint32_t dot_clock; - int is_rgb; - int is_planar; - int i; - uint32_t scale_cntl; - double dsr; - int tap_set; - int predownscale=0; - int src_w_d; - int leftuv = 0; - DisplayModePtr mode; - RADEONOutputPrivatePtr radeon_output; - xf86OutputPtr output; - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - - is_rgb=0; is_planar=0; - switch(id){ - case FOURCC_I420: - case FOURCC_YV12: - is_planar=1; - break; - case FOURCC_RGBA32: - case FOURCC_RGB24: - case FOURCC_RGBT16: - case FOURCC_RGB16: - is_rgb=1; - break; - default: - break; - } - - /* Here we need to find ecp_div again, as the user may have switched resolutions - but only call OUTPLL/INPLL if needed since it may cause a 10ms delay due to - workarounds for chip erratas */ - - /* Figure out which head we are on for dot clock */ - if (radeon_crtc->crtc_id == 1) - dot_clock = info->ModeReg->dot_clock_freq_2; - else - dot_clock = info->ModeReg->dot_clock_freq; - - if (dot_clock < 17500) - ecp_div = 0; - else - ecp_div = 1; - - if (ecp_div != info->ecp_div) { - info->ecp_div = ecp_div; - OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, - (INPLL(pScrn, RADEON_VCLK_ECP_CNTL) & 0xfffffCff) | (ecp_div << 8)); - } - - /* I suspect we may need a usleep after writing to the PLL. if you play a video too soon - after switching crtcs in mergedfb clone mode you get a temporary one pixel line of colorkey - on the right edge video output. - Is this still the case? Might have been chips which need the errata, - there is now plenty of usleep after INPLL/OUTPLL for those...*/ - - v_inc_shift = 20; - y_mult = 1; - - mode = &crtc->mode; - - if (mode->Flags & V_INTERLACE) - v_inc_shift++; - if (mode->Flags & V_DBLSCAN) { - v_inc_shift--; - y_mult = 2; - } - - v_inc = (src_h << v_inc_shift) / drw_h; - - for (i = 0; i < xf86_config->num_output; i++) { - output = xf86_config->output[i]; - if (output->crtc == crtc) { - radeon_output = output->driver_private; - if (radeon_output->Flags & RADEON_USE_RMX) - v_inc = ((src_h * mode->CrtcVDisplay / - radeon_output->native_mode.PanelYRes) << v_inc_shift) / drw_h; - break; - } - } - - h_inc = (1 << (12 + ecp_div)); - - step_by_y = 1; - step_by_uv = step_by_y; - - src_w_d = src_w; -#if 0 - /* XXX this does not appear to work */ - /* if the source width was larger than what would fit in overlay scaler increase step_by values */ - i=src_w; - while(i>info->overlay_scaler_buffer_width){ - step_by_y++; - step_by_uv++; - h_inc >>=1; - i=i/2; - } -#else - /* predownscale instead (yes this hurts quality) - will only work for widths up - to 2 times the overlay_scaler_buffer_width, should be enough */ - if (src_w_d > info->overlay_scaler_buffer_width) { - src_w_d /= 2; /* odd widths? */ - predownscale = 1; - } -#endif - - h_inc_d = src_w_d; - h_inc_d = h_inc_d/drw_w; - /* we could do a tad better - but why - bother when this concerns downscaling and the code is so much more - hairy */ - while(h_inc*h_inc_d >= (2 << 12)) { - if(!is_rgb && (((h_inc+h_inc/2)*h_inc_d)<(2<<12))){ - step_by_uv = step_by_y+1; - break; - } - step_by_y++; - step_by_uv = step_by_y; - h_inc >>= 1; - } - - h_inc_uv = h_inc>>(step_by_uv-step_by_y); - h_inc = h_inc * h_inc_d; - h_inc_uv = h_inc_uv * h_inc_d; - /* info->overlay_scaler_buffer_width is magic number - maximum line length the overlay scaler can fit - in the buffer for 2 tap filtering */ - /* the only place it is documented in is in ATI source code */ - /* we need twice as much space for 4 tap filtering.. */ - /* under special circumstances turn on 4 tap filtering */ - /* disable this code for now as it has a DISASTROUS effect on image quality when upscaling - at least on rv250 (only as long as the drw_w*2 <=... requirement is still met of course) */ -#if 0 - if(!is_rgb && (step_by_y==1) && (step_by_uv==1) && (h_inc < (1<<12)) - && (deinterlacing_method!=METHOD_WEAVE) - && (drw_w*2 <= info->overlay_scaler_buffer_width)){ - step_by_y=0; - step_by_uv=1; - h_inc_uv = h_inc; - } -#endif - - /* Make the overlay base address as close to the buffers as possible to - * prevent the buffer offsets from exceeding the hardware limit of 128 MB. - * The base address must be aligned to a multiple of 4 MB. - */ - base_offset = ((info->fbLocation + base_offset) & (~0 << 22)) - - info->fbLocation; - - offset1 -= base_offset; - offset2 -= base_offset; - offset3 -= base_offset; - offset4 -= base_offset; - offset5 -= base_offset; - offset6 -= base_offset; - - /* keep everything in 16.16 */ - - if (is_planar) { - offset1 += ((left >> 16) & ~15); - offset2 += ((left >> 16) & ~31) >> 1; - offset3 += ((left >> 16) & ~31) >> 1; - offset4 += ((left >> 16) & ~15); - offset5 += ((left >> 16) & ~31) >> 1; - offset6 += ((left >> 16) & ~31) >> 1; - offset2 |= RADEON_VIF_BUF0_PITCH_SEL; - offset3 |= RADEON_VIF_BUF0_PITCH_SEL; - offset5 |= RADEON_VIF_BUF0_PITCH_SEL; - offset6 |= RADEON_VIF_BUF0_PITCH_SEL; - } - else { - /* is this really correct for non-2-byte formats? */ - offset1 += ((left >> 16) & ~7) << 1; - offset2 += ((left >> 16) & ~7) << 1; - offset3 += ((left >> 16) & ~7) << 1; - offset4 += ((left >> 16) & ~7) << 1; - offset5 += ((left >> 16) & ~7) << 1; - offset6 += ((left >> 16) & ~7) << 1; - } - - tmp = (left & 0x0003ffff) + 0x00028000 + (h_inc << 3); - p1_h_accum_init = ((tmp << 4) & 0x000f8000) | - ((tmp << 12) & 0xf0000000); - - tmp = ((left >> 1) & 0x0001ffff) + 0x00028000 + (h_inc_uv << 2); - p23_h_accum_init = ((tmp << 4) & 0x000f8000) | - ((tmp << 12) & 0x70000000); - - tmp = (top & 0x0000ffff) + 0x00018000; - p1_v_accum_init = ((tmp << 4) & 0x03ff8000) | - (((deinterlacing_method!=METHOD_WEAVE)&&!is_rgb)?0x03:0x01); - - if (is_planar) { - p23_v_accum_init = ((tmp << 4) & 0x03ff8000) | - ((deinterlacing_method != METHOD_WEAVE) ? 0x03 : 0x01); - p23_blank_lines = (((src_h >> 1) - 1) << 16); - } - else { - p23_v_accum_init = 0; - p23_blank_lines = 0; - } - - if (is_planar) { - leftuv = ((left >> 16) >> 1) & 15; - left = (left >> 16) & 15; - } - else { - left = (left >> 16) & 7; - if (!is_rgb) - leftuv = left >> 1; - } - - RADEONWaitForFifo(pScrn, 2); - OUTREG(RADEON_OV0_REG_LOAD_CNTL, RADEON_REG_LD_CTL_LOCK); - if (info->accelOn) RADEON_SYNC(info, pScrn); - while(!(INREG(RADEON_OV0_REG_LOAD_CNTL) & RADEON_REG_LD_CTL_LOCK_READBACK)); - - RADEONWaitForFifo(pScrn, 10); - OUTREG(RADEON_OV0_H_INC, h_inc | ((is_rgb? h_inc_uv: (h_inc_uv >> 1)) << 16)); - OUTREG(RADEON_OV0_STEP_BY, step_by_y | (step_by_uv << 8) | - predownscale << 4 | predownscale << 12); - - x_off = 8; - y_off = 0; - - if (IS_R300_VARIANT || - (info->ChipFamily == CHIP_FAMILY_R200)) - x_off = 0; - - /* needed to make the overlay work on crtc1 in leftof and above modes */ - /* XXX: may need to adjust x_off/y_off for dualhead like mergedfb -- need to test */ - /* - if (srel == radeonLeftOf) { - x_off -= mode->CrtcHDisplay; - } - if (srel == radeonAbove) { - y_off -= mode->CrtcVDisplay; - } - */ - - /* Put the hardware overlay on CRTC2: - * - * Since one hardware overlay can not be displayed on two heads - * at the same time, we might need to consider using software - * rendering for the second head. - */ - - if (radeon_crtc->crtc_id == 1) { - x_off = 0; - OUTREG(RADEON_OV1_Y_X_START, ((dstBox->x1 + x_off) | - ((dstBox->y1*y_mult) << 16))); - OUTREG(RADEON_OV1_Y_X_END, ((dstBox->x2 + x_off) | - ((dstBox->y2*y_mult) << 16))); - scaler_src = RADEON_SCALER_CRTC_SEL; - } else { - OUTREG(RADEON_OV0_Y_X_START, ((dstBox->x1 + x_off) | - (((dstBox->y1*y_mult) + y_off) << 16))); - OUTREG(RADEON_OV0_Y_X_END, ((dstBox->x2 + x_off) | - (((dstBox->y2*y_mult) + y_off) << 16))); - scaler_src = 0; - } - - /* program the tap coefficients for better downscaling quality. - Could do slightly better by using hardcoded coefficients for one axis - in case only the other axis is downscaled (see RADEON_OV0_FILTER_CNTL) */ - dsr=(double)(1<<0xC)/h_inc; - if(dsr<0.25)dsr=0.25; - if(dsr>1.0)dsr=1.0; - tap_set=(int)((dsr-0.25)*100); - for(i=0;i<5;i++){ - OUTREG(RADEON_OV0_FOUR_TAP_COEF_0+i*4, (TapCoeffs[tap_set].coeff[i][0] &0xf) | - ((TapCoeffs[tap_set].coeff[i][1] &0x7f)<<8) | - ((TapCoeffs[tap_set].coeff[i][2] &0x7f)<<16) | - ((TapCoeffs[tap_set].coeff[i][3] &0xf)<<24)); - } - - RADEONWaitForFifo(pScrn, 11); - OUTREG(RADEON_OV0_V_INC, v_inc); - OUTREG(RADEON_OV0_P1_BLANK_LINES_AT_TOP, 0x00000fff | ((src_h - 1) << 16)); - OUTREG(RADEON_OV0_P23_BLANK_LINES_AT_TOP, 0x000007ff | p23_blank_lines); - OUTREG(RADEON_OV0_VID_BUF_PITCH0_VALUE, pitch); - OUTREG(RADEON_OV0_VID_BUF_PITCH1_VALUE, is_planar ? pitch >> 1 : pitch); - OUTREG(RADEON_OV0_P1_X_START_END, (src_w + left - 1) | (left << 16)); - if (!is_rgb) - src_w >>= 1; - OUTREG(RADEON_OV0_P2_X_START_END, (src_w + leftuv - 1) | (leftuv << 16)); - OUTREG(RADEON_OV0_P3_X_START_END, (src_w + leftuv - 1) | (leftuv << 16)); - if (info->ModeReg->ov0_base_addr != (info->fbLocation + base_offset)) { - ErrorF("Changing OV0_BASE_ADDR from 0x%08x to 0x%08x\n", - info->ModeReg->ov0_base_addr, (uint32_t)info->fbLocation + base_offset); - info->ModeReg->ov0_base_addr = info->fbLocation + base_offset; - OUTREG(RADEON_OV0_BASE_ADDR, info->ModeReg->ov0_base_addr); - } - OUTREG(RADEON_OV0_VID_BUF0_BASE_ADRS, offset1); - OUTREG(RADEON_OV0_VID_BUF1_BASE_ADRS, offset2); - OUTREG(RADEON_OV0_VID_BUF2_BASE_ADRS, offset3); - - RADEONWaitForFifo(pScrn, 9); - OUTREG(RADEON_OV0_VID_BUF3_BASE_ADRS, offset4); - OUTREG(RADEON_OV0_VID_BUF4_BASE_ADRS, offset5); - OUTREG(RADEON_OV0_VID_BUF5_BASE_ADRS, offset6); - OUTREG(RADEON_OV0_P1_V_ACCUM_INIT, p1_v_accum_init); - OUTREG(RADEON_OV0_P1_H_ACCUM_INIT, p1_h_accum_init); - OUTREG(RADEON_OV0_P23_V_ACCUM_INIT, p23_v_accum_init); - OUTREG(RADEON_OV0_P23_H_ACCUM_INIT, p23_h_accum_init); - - scale_cntl = RADEON_SCALER_ADAPTIVE_DEINT | RADEON_SCALER_DOUBLE_BUFFER - | RADEON_SCALER_ENABLE | RADEON_SCALER_SMART_SWITCH | (0x7f<<16) | scaler_src; - switch(id){ - case FOURCC_UYVY: - scale_cntl |= RADEON_SCALER_SOURCE_YVYU422; - break; - case FOURCC_RGB24: - case FOURCC_RGBA32: - scale_cntl |= RADEON_SCALER_SOURCE_32BPP | RADEON_SCALER_LIN_TRANS_BYPASS; - break; - case FOURCC_RGB16: - scale_cntl |= RADEON_SCALER_SOURCE_16BPP | RADEON_SCALER_LIN_TRANS_BYPASS; - break; - case FOURCC_RGBT16: - scale_cntl |= RADEON_SCALER_SOURCE_15BPP | RADEON_SCALER_LIN_TRANS_BYPASS; - break; - case FOURCC_YV12: - case FOURCC_I420: - scale_cntl |= RADEON_SCALER_SOURCE_YUV12; - break; - case FOURCC_YUY2: - default: - scale_cntl |= RADEON_SCALER_SOURCE_VYUY422 - | ((info->ChipFamily >= CHIP_FAMILY_R200) ? RADEON_SCALER_TEMPORAL_DEINT : 0); - break; - } - - if (info->ChipFamily < CHIP_FAMILY_R200) { - scale_cntl &= ~RADEON_SCALER_GAMMA_SEL_MASK; - scale_cntl |= ((RADEONTranslateUserGamma(pPriv->gamma)) << 5); - } - - OUTREG(RADEON_OV0_SCALE_CNTL, scale_cntl); - OUTREG(RADEON_OV0_REG_LOAD_CNTL, 0); -} - - -static void -RADEONFillKeyHelper(DrawablePtr pDraw, uint32_t colorKey, RegionPtr clipBoxes) -{ -#if HAVE_XV_DRAWABLE_HELPER - xf86XVFillKeyHelperDrawable(pDraw, colorKey, clipBoxes); -#else - xf86XVFillKeyHelper(pDraw->pScreen, colorKey, clipBoxes); -#endif -} - - -static int -RADEONPutImage( - ScrnInfoPtr pScrn, - short src_x, short src_y, - short drw_x, short drw_y, - short src_w, short src_h, - short drw_w, short drw_h, - int id, unsigned char* buf, - short width, short height, - Bool Sync, - RegionPtr clipBoxes, pointer data, - DrawablePtr pDraw -){ - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)data; - INT32 xa, xb, ya, yb; - unsigned char *dst_start; - int new_size, offset, s2offset, s3offset; - int srcPitch, srcPitch2, dstPitch; - int d2line, d3line; - int top, left, npixels, nlines, bpp; - int idconv = id; - BoxRec dstBox; - uint32_t tmp; - xf86CrtcPtr crtc; - - /* - * s2offset, s3offset - byte offsets into U and V plane of the - * source where copying starts. Y plane is - * done by editing "buf". - * - * offset - byte offset to the first line of the destination. - * - * dst_start - byte address to the first displayed pel. - * - */ - - /* make the compiler happy */ - s2offset = s3offset = srcPitch2 = 0; - d2line = d3line = 0; - - if(src_w > (drw_w << 4)) - drw_w = src_w >> 4; - if(src_h > (drw_h << 4)) - drw_h = src_h >> 4; - - /* Clip */ - xa = src_x; - xb = src_x + src_w; - ya = src_y; - yb = src_y + src_h; - - dstBox.x1 = drw_x; - dstBox.x2 = drw_x + drw_w; - dstBox.y1 = drw_y; - dstBox.y2 = drw_y + drw_h; - - if (!radeon_crtc_clip_video(pScrn, &crtc, pPriv->desired_crtc, - &dstBox, &xa, &xb, &ya, &yb, - clipBoxes, width, height)) - return Success; - - if (!crtc) { - if (pPriv->videoStatus & CLIENT_VIDEO_ON) { - unsigned char *RADEONMMIO = info->MMIO; - OUTREG(RADEON_OV0_SCALE_CNTL, 0); - pPriv->videoStatus &= ~CLIENT_VIDEO_ON; - } - return Success; - } - - dstBox.x1 -= crtc->x; - dstBox.x2 -= crtc->x; - dstBox.y1 -= crtc->y; - dstBox.y2 -= crtc->y; - - bpp = pScrn->bitsPerPixel >> 3; - - switch(id) { - case FOURCC_RGB24: - dstPitch = width * 4; - srcPitch = width * 3; - break; - case FOURCC_RGBA32: - dstPitch = width * 4; - srcPitch = width * 4; - break; - case FOURCC_RGB16: - case FOURCC_RGBT16: - dstPitch = width * 2; - srcPitch = RADEON_ALIGN(width * 2, 4); - break; - case FOURCC_YV12: - case FOURCC_I420: - /* it seems rs4xx chips (all of them???) either can't handle planar - yuv at all or would need some unknown different setup. */ - if ((info->ChipFamily != CHIP_FAMILY_RS400) && - (info->ChipFamily != CHIP_FAMILY_RS480)) { - /* need 16bytes alignment for u,v plane, so 2 times that for width - but blitter needs 64bytes alignment. 128byte is a waste but dstpitch - for uv planes needs to be dstpitch yplane >> 1 for now. */ - dstPitch = (RADEON_ALIGN(width, 128)); - srcPitch = RADEON_ALIGN(width, 4); - } - else { - dstPitch = width * 2; - srcPitch = RADEON_ALIGN(width, 4); - idconv = FOURCC_YUY2; + uint32_t *dst; + uint8_t *s1, *s2, *s3; + int i, j; + + w /= 2; + + for( j = 0; j < h; j++ ) { + dst = (pointer)dst1; + s1 = src1; s2 = src2; s3 = src3; + i = w; + while( i > 4 ) { + dst[0] = cpu_to_le32(s1[0] | (s1[1] << 16) | (s3[0] << 8) | (s2[0] << 24)); + dst[1] = cpu_to_le32(s1[2] | (s1[3] << 16) | (s3[1] << 8) | (s2[1] << 24)); + dst[2] = cpu_to_le32(s1[4] | (s1[5] << 16) | (s3[2] << 8) | (s2[2] << 24)); + dst[3] = cpu_to_le32(s1[6] | (s1[7] << 16) | (s3[3] << 8) | (s2[3] << 24)); + dst += 4; s2 += 4; s3 += 4; s1 += 8; + i -= 4; } - break; - case FOURCC_UYVY: - case FOURCC_YUY2: - default: - dstPitch = width * 2; - srcPitch = width * 2; - break; - } - -#ifdef XF86DRI - if (info->directRenderingEnabled && info->DMAForXv) { - /* The upload blit only supports multiples of 64 bytes */ - dstPitch = RADEON_ALIGN(dstPitch, 64); - } else -#endif - /* The overlay only supports multiples of 16 bytes */ - dstPitch = RADEON_ALIGN(dstPitch, 16); - - new_size = dstPitch * height; - if (idconv == FOURCC_YV12 || id == FOURCC_I420) { - new_size += (dstPitch >> 1) * (RADEON_ALIGN(height, 2)); - } - pPriv->video_offset = radeon_legacy_allocate_memory(pScrn, &pPriv->video_memory, - (pPriv->doubleBuffer ? - (new_size * 2) : new_size), 64, - RADEON_GEM_DOMAIN_VRAM); - if (pPriv->video_offset == 0) - return BadAlloc; - - pPriv->currentBuffer ^= 1; - - /* copy data */ - top = ya >> 16; - left = (xa >> 16) & ~1; - npixels = ((xb + 0xffff) >> 16) - left; - - offset = (pPriv->video_offset) + (top * dstPitch); - - if(pPriv->doubleBuffer) { - unsigned char *RADEONMMIO = info->MMIO; - - /* Wait for last flip to take effect */ - while(!(INREG(RADEON_OV0_REG_LOAD_CNTL) & RADEON_REG_LD_CTL_FLIP_READBACK)); - - offset += pPriv->currentBuffer * new_size; - } - - dst_start = info->FB + offset; - - switch(id) { - case FOURCC_YV12: - case FOURCC_I420: - if (id == idconv) { - /* meh. Such a mess just for someone who wants to watch half the video clipped */ - top &= ~1; - /* odd number of pixels? That may not work correctly */ - srcPitch2 = RADEON_ALIGN(width >> 1, 4); - /* odd number of lines? Maybe... */ - s2offset = srcPitch * (RADEON_ALIGN(height, 2)); - s3offset = s2offset + srcPitch2 * ((height + 1) >> 1); - s2offset += (top >> 1) * srcPitch2 + (left >> 1); - s3offset += (top >> 1) * srcPitch2 + (left >> 1); - d2line = (height * dstPitch); - d3line = d2line + ((height + 1) >> 1) * (dstPitch >> 1); - nlines = ((yb + 0xffff) >> 16) - top; - d2line += (top >> 1) * (dstPitch >> 1) - (top * dstPitch); - d3line += (top >> 1) * (dstPitch >> 1) - (top * dstPitch); - if(id == FOURCC_YV12) { - tmp = s2offset; - s2offset = s3offset; - s3offset = tmp; - } - RADEONCopyData(pScrn, buf + (top * srcPitch) + left, dst_start + left, - srcPitch, dstPitch, nlines, npixels, 1); - RADEONCopyData(pScrn, buf + s2offset, dst_start + d2line + (left >> 1), - srcPitch2, dstPitch >> 1, (nlines + 1) >> 1, npixels >> 1, 1); - RADEONCopyData(pScrn, buf + s3offset, dst_start + d3line + (left >> 1), - srcPitch2, dstPitch >> 1, (nlines + 1) >> 1, npixels >> 1, 1); - } - else { - s2offset = srcPitch * height; - srcPitch2 = RADEON_ALIGN(width >> 1, 4); - s3offset = (srcPitch2 * (height >> 1)) + s2offset; - top &= ~1; - dst_start += left << 1; - tmp = ((top >> 1) * srcPitch2) + (left >> 1); - s2offset += tmp; - s3offset += tmp; - if(id == FOURCC_I420) { - tmp = s2offset; - s2offset = s3offset; - s3offset = tmp; - } - nlines = ((yb + 0xffff) >> 16) - top; - RADEONCopyMungedData(pScrn, buf + (top * srcPitch) + left, - buf + s2offset, buf + s3offset, dst_start, - srcPitch, srcPitch2, dstPitch, nlines, npixels); + while( i-- ) { + dst[0] = cpu_to_le32(s1[0] | (s1[1] << 16) | (s3[0] << 8) | (s2[0] << 24)); + dst++; s2++; s3++; + s1 += 2; } - break; - case FOURCC_RGBT16: - case FOURCC_RGB16: - case FOURCC_UYVY: - case FOURCC_YUY2: - default: - left <<= 1; - buf += (top * srcPitch) + left; - nlines = ((yb + 0xffff) >> 16) - top; - dst_start += left; - RADEONCopyData(pScrn, buf, dst_start, srcPitch, dstPitch, nlines, npixels, 2); - break; - case FOURCC_RGBA32: - buf += (top * srcPitch) + left*4; - nlines = ((yb + 0xffff) >> 16) - top; - dst_start += left*4; - RADEONCopyData(pScrn, buf, dst_start, srcPitch, dstPitch, nlines, npixels, 4); - break; - case FOURCC_RGB24: - buf += (top * srcPitch) + left*3; - nlines = ((yb + 0xffff) >> 16) - top; - dst_start += left*4; - RADEONCopyRGB24Data(pScrn, buf, dst_start, srcPitch, dstPitch, nlines, npixels); - break; - } - - /* update cliplist */ - if(!REGION_EQUAL(pScrn->pScreen, &pPriv->clip, clipBoxes)) - { - REGION_COPY(pScrn->pScreen, &pPriv->clip, clipBoxes); - /* draw these */ - if(pPriv->autopaint_colorkey) - RADEONFillKeyHelper(pDraw, pPriv->colorKey, clipBoxes); + + dst1 += dstPitch; + src1 += srcPitch; + if( j & 1 ) { + src2 += srcPitch2; + src3 += srcPitch2; + } } - - /* FIXME: someone should look at these offsets, I don't think it makes sense how - they are handled throughout the source. */ - RADEONDisplayVideo(pScrn, crtc, pPriv, idconv, pPriv->video_offset, offset, - offset + d2line, offset + d3line, offset, offset + d2line, - offset + d3line, width, height, dstPitch, xa, xb, ya, - &dstBox, src_w, src_h, drw_w, drw_h, METHOD_BOB); - - pPriv->videoStatus = CLIENT_VIDEO_ON; - - info->VideoTimerCallback = RADEONVideoTimerCallback; - - return Success; } - int RADEONQueryImageAttributes( ScrnInfoPtr pScrn, @@ -3198,798 +535,3 @@ RADEONQueryImageAttributes( return size; } -static void -RADEONVideoTimerCallback(ScrnInfoPtr pScrn, Time now) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONPortPrivPtr pPriv = info->adaptor->pPortPrivates[0].ptr; - - if(pPriv->videoStatus & TIMER_MASK) { - if(pPriv->videoStatus & OFF_TIMER) { - if(pPriv->offTime < now) { - unsigned char *RADEONMMIO = info->MMIO; - OUTREG(RADEON_OV0_SCALE_CNTL, 0); - pPriv->videoStatus = FREE_TIMER; - pPriv->freeTime = now + FREE_DELAY; - } - } else { /* FREE_TIMER */ - if(pPriv->freeTime < now) { - RADEONFreeVideoMemory(pScrn, pPriv); - pPriv->videoStatus = 0; - info->VideoTimerCallback = NULL; - } - } - } else /* shouldn't get here */ - info->VideoTimerCallback = NULL; -} - -/****************** Offscreen stuff ***************/ -typedef struct { - void *surface_memory; - Bool isOn; -} OffscreenPrivRec, * OffscreenPrivPtr; - -static int -RADEONAllocateSurface( - ScrnInfoPtr pScrn, - int id, - unsigned short w, - unsigned short h, - XF86SurfacePtr surface -){ - int offset, pitch, size; - OffscreenPrivPtr pPriv; - void *surface_memory = NULL; - if((w > 1024) || (h > 1024)) - return BadAlloc; - - w = RADEON_ALIGN(w, 2); - pitch = RADEON_ALIGN(w << 1, 16); - size = pitch * h; - - offset = radeon_legacy_allocate_memory(pScrn, &surface_memory, size, 64, - RADEON_GEM_DOMAIN_VRAM); - if (offset == 0) - return BadAlloc; - - surface->width = w; - surface->height = h; - - if(!(surface->pitches = malloc(sizeof(int)))) { - radeon_legacy_free_memory(pScrn, surface_memory); - return BadAlloc; - } - if(!(surface->offsets = malloc(sizeof(int)))) { - free(surface->pitches); - radeon_legacy_free_memory(pScrn, surface_memory); - return BadAlloc; - } - if(!(pPriv = malloc(sizeof(OffscreenPrivRec)))) { - free(surface->pitches); - free(surface->offsets); - radeon_legacy_free_memory(pScrn, surface_memory); - return BadAlloc; - } - - pPriv->surface_memory = surface_memory; - pPriv->isOn = FALSE; - - surface->pScrn = pScrn; - surface->id = id; - surface->pitches[0] = pitch; - surface->offsets[0] = offset; - surface->devPrivate.ptr = (pointer)pPriv; - - return Success; -} - -static int -RADEONStopSurface( - XF86SurfacePtr surface -){ - OffscreenPrivPtr pPriv = (OffscreenPrivPtr)surface->devPrivate.ptr; - RADEONInfoPtr info = RADEONPTR(surface->pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - if(pPriv->isOn) { - OUTREG(RADEON_OV0_SCALE_CNTL, 0); - pPriv->isOn = FALSE; - } - return Success; -} - - -static int -RADEONFreeSurface( - XF86SurfacePtr surface -){ - ScrnInfoPtr pScrn = surface->pScrn; - OffscreenPrivPtr pPriv = (OffscreenPrivPtr)surface->devPrivate.ptr; - - if(pPriv->isOn) - RADEONStopSurface(surface); - radeon_legacy_free_memory(pScrn, pPriv->surface_memory); - pPriv->surface_memory = NULL; - free(surface->pitches); - free(surface->offsets); - free(surface->devPrivate.ptr); - - return Success; -} - -static int -RADEONGetSurfaceAttribute( - ScrnInfoPtr pScrn, - Atom attribute, - INT32 *value -){ - return RADEONGetPortAttribute(pScrn, attribute, value, - (pointer)(GET_PORT_PRIVATE(pScrn))); -} - -static int -RADEONSetSurfaceAttribute( - ScrnInfoPtr pScrn, - Atom attribute, - INT32 value -){ - return RADEONSetPortAttribute(pScrn, attribute, value, - (pointer)(GET_PORT_PRIVATE(pScrn))); -} - - -static int -RADEONDisplaySurface( - XF86SurfacePtr surface, - short src_x, short src_y, - short drw_x, short drw_y, - short src_w, short src_h, - short drw_w, short drw_h, - RegionPtr clipBoxes -){ - OffscreenPrivPtr pPriv = (OffscreenPrivPtr)surface->devPrivate.ptr; - ScrnInfoPtr pScrn = surface->pScrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONPortPrivPtr portPriv = info->adaptor->pPortPrivates[0].ptr; - - INT32 xa, ya, xb, yb; - BoxRec dstBox; - xf86CrtcPtr crtc; - - if (src_w > (drw_w << 4)) - drw_w = src_w >> 4; - if (src_h > (drw_h << 4)) - drw_h = src_h >> 4; - - xa = src_x; - xb = src_x + src_w; - ya = src_y; - yb = src_y + src_h; - - dstBox.x1 = drw_x; - dstBox.x2 = drw_x + drw_w; - dstBox.y1 = drw_y; - dstBox.y2 = drw_y + drw_h; - - if (!radeon_crtc_clip_video(pScrn, &crtc, portPriv->desired_crtc, - &dstBox, &xa, &xb, &ya, &yb, clipBoxes, - surface->width, surface->height)) - return Success; - - if (!crtc) { - if (pPriv->isOn) { - unsigned char *RADEONMMIO = info->MMIO; - OUTREG(RADEON_OV0_SCALE_CNTL, 0); - pPriv->isOn = FALSE; - } - return Success; - } - - dstBox.x1 -= crtc->x; - dstBox.x2 -= crtc->x; - dstBox.y1 -= crtc->y; - dstBox.y2 -= crtc->y; - -#if 0 - /* this isn't needed */ - RADEONResetVideo(pScrn); -#endif - RADEONDisplayVideo(pScrn, crtc, portPriv, surface->id, - surface->offsets[0], surface->offsets[0], - surface->offsets[0], surface->offsets[0], - surface->offsets[0], surface->offsets[0], - surface->offsets[0], surface->width, surface->height, - surface->pitches[0], xa, xb, ya, &dstBox, src_w, src_h, - drw_w, drw_h, METHOD_BOB); - - if (portPriv->autopaint_colorkey) - xf86XVFillKeyHelper(pScrn->pScreen, portPriv->colorKey, clipBoxes); - - pPriv->isOn = TRUE; - /* we've prempted the XvImage stream so set its free timer */ - if (portPriv->videoStatus & CLIENT_VIDEO_ON) { - REGION_EMPTY(pScrn->pScreen, &portPriv->clip); - UpdateCurrentTime(); - portPriv->videoStatus = FREE_TIMER; - portPriv->freeTime = currentTime.milliseconds + FREE_DELAY; - info->VideoTimerCallback = RADEONVideoTimerCallback; - } - - return Success; -} - - -static void -RADEONInitOffscreenImages(ScreenPtr pScreen) -{ -/* ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); - RADEONInfoPtr info = RADEONPTR(pScrn); */ - XF86OffscreenImagePtr offscreenImages; - /* need to free this someplace */ - - if (!(offscreenImages = malloc(sizeof(XF86OffscreenImageRec)))) - return; - - offscreenImages[0].image = &Images[0]; - offscreenImages[0].flags = VIDEO_OVERLAID_IMAGES /*| - VIDEO_CLIP_TO_VIEWPORT*/; - offscreenImages[0].alloc_surface = RADEONAllocateSurface; - offscreenImages[0].free_surface = RADEONFreeSurface; - offscreenImages[0].display = RADEONDisplaySurface; - offscreenImages[0].stop = RADEONStopSurface; - offscreenImages[0].setAttribute = RADEONSetSurfaceAttribute; - offscreenImages[0].getAttribute = RADEONGetSurfaceAttribute; - offscreenImages[0].max_width = 2047; - offscreenImages[0].max_height = 2047; - offscreenImages[0].num_attributes = NUM_ATTRIBUTES; - offscreenImages[0].attributes = Attributes; - - xf86XVRegisterOffscreenImages(pScreen, offscreenImages, 1); -} - - /* TV-in functions */ - -static int -RADEONPutVideo( - ScrnInfoPtr pScrn, - short src_x, short src_y, - short drw_x, short drw_y, - short src_w, short src_h, - short drw_w, short drw_h, - RegionPtr clipBoxes, pointer data, - DrawablePtr pDraw -){ - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)data; - unsigned char *RADEONMMIO = info->MMIO; - INT32 xa, xb, ya, yb, top; - unsigned int pitch, new_size, alloc_size; - unsigned int offset1, offset2, offset3, offset4, s2offset, s3offset; - unsigned int vbi_offset0, vbi_offset1; - int srcPitch, srcPitch2, dstPitch; - int bpp; - BoxRec dstBox; - uint32_t id, display_base; - int width, height; - int mult; - int vbi_line_width, vbi_start, vbi_end; - xf86CrtcPtr crtc; - - RADEON_SYNC(info, pScrn); - /* - * s2offset, s3offset - byte offsets into U and V plane of the - * source where copying starts. Y plane is - * done by editing "buf". - * - * offset - byte offset to the first line of the destination. - * - * dst_start - byte address to the first displayed pel. - * - */ - - /* make the compiler happy */ - s2offset = s3offset = srcPitch2 = 0; - - if(src_w > (drw_w << 4)) - drw_w = src_w >> 4; - if(src_h > (drw_h << 4)) - drw_h = src_h >> 4; - - /* Clip */ - xa = src_x; - xb = src_x + src_w; - ya = src_y; - yb = src_y + src_h; - - dstBox.x1 = drw_x; - dstBox.x2 = drw_x + drw_w; - dstBox.y1 = drw_y; - dstBox.y2 = drw_y + drw_h; - - width = InputVideoEncodings[pPriv->encoding].width; - height = InputVideoEncodings[pPriv->encoding].height; - - vbi_line_width = 798*2; - if(width<=640) - vbi_line_width = 0x640; /* 1600 actually */ - else - vbi_line_width = 2000; /* might need adjustment */ - - if (!radeon_crtc_clip_video(pScrn, &crtc, pPriv->desired_crtc, - &dstBox, &xa, &xb, &ya, &yb, - clipBoxes, width, height)) - return Success; - - if (!crtc) { - if (pPriv->videoStatus & CLIENT_VIDEO_ON) { - unsigned char *RADEONMMIO = info->MMIO; - OUTREG(RADEON_OV0_SCALE_CNTL, 0); - pPriv->videoStatus &= ~CLIENT_VIDEO_ON; - } - return Success; - } - - dstBox.x1 -= crtc->x; - dstBox.x2 -= crtc->x; - dstBox.y1 -= crtc->y; - dstBox.y2 -= crtc->y; - - bpp = pScrn->bitsPerPixel >> 3; - pitch = bpp * pScrn->displayWidth; - - switch(pPriv->overlay_deinterlacing_method){ - case METHOD_BOB: - case METHOD_SINGLE: - mult=2; - break; - case METHOD_WEAVE: - case METHOD_ADAPTIVE: - mult=4; - break; - default: - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Internal error: PutVideo\n"); - mult=4; - } - - id = FOURCC_YUY2; - - top = ya>>16; -#if 0 - /* setting the ID above makes this useful - needs revisiting */ - switch(id) { - case FOURCC_YV12: - case FOURCC_I420: - top &= ~1; - dstPitch = RADEON_ALIGN(width << 1, 16); - srcPitch = RADEON_ALIGN(width, 4); - s2offset = srcPitch * height; - srcPitch2 = RADEON_ALIGN(width >> 1, 4); - s3offset = (srcPitch2 * (height >> 1)) + s2offset; - break; - case FOURCC_UYVY: - case FOURCC_YUY2: - default: - dstPitch = RADEON_ALIGN(width<<1, 16); - srcPitch = (width<<1); - break; - } -#else - dstPitch = RADEON_ALIGN(width << 1, 16); - srcPitch = (width<<1); -#endif - - new_size = dstPitch * height; - new_size = new_size + 0x1f; /* for aligning */ - alloc_size = new_size * mult; - if (pPriv->capture_vbi_data) - alloc_size += 2 * 2 * vbi_line_width * 21; - - pPriv->video_offset = radeon_legacy_allocate_memory(pScrn, &pPriv->video_memory, - (pPriv->doubleBuffer ? - (new_size * 2) : new_size), 64, - RADEON_GEM_DOMAIN_GTT); - if (pPriv->video_offset == 0) - return BadAlloc; - -/* I have suspicion that capture engine must be active _before_ Rage Theatre - is being manipulated with.. */ - - RADEONWaitForIdleMMIO(pScrn); - display_base=INREG(RADEON_DISPLAY_BASE_ADDR); - -/* RADEONWaitForFifo(pScrn, 15); */ - - switch(pPriv->overlay_deinterlacing_method){ - case METHOD_BOB: - case METHOD_SINGLE: - offset1 = RADEON_ALIGN(pPriv->video_offset, 0x10); - offset2 = RADEON_ALIGN(pPriv->video_offset + new_size, 0x10); - offset3 = offset1; - offset4 = offset2; - break; - case METHOD_WEAVE: - offset1 = RADEON_ALIGN(pPriv->video_offset, 0x10); - offset2 = offset1+dstPitch; - offset3 = RADEON_ALIGN(pPriv->video_offset + 2 * new_size, 0x10); - offset4 = offset3+dstPitch; - break; - default: - offset1 = RADEON_ALIGN(pPriv->video_offset, 0x10); - offset2 = RADEON_ALIGN(pPriv->video_offset + new_size, 0x10); - offset3 = offset1; - offset4 = offset2; - } - - OUTREG(RADEON_CAP0_BUF0_OFFSET, offset1+display_base); - OUTREG(RADEON_CAP0_BUF0_EVEN_OFFSET, offset2+display_base); - OUTREG(RADEON_CAP0_BUF1_OFFSET, offset3+display_base); - OUTREG(RADEON_CAP0_BUF1_EVEN_OFFSET, offset4+display_base); - - OUTREG(RADEON_CAP0_ONESHOT_BUF_OFFSET, offset1+display_base); - - if(pPriv->capture_vbi_data){ - if ((pPriv->encoding==2)||(pPriv->encoding==8)) { - /* PAL, SECAM */ - vbi_start = 5; - vbi_end = 21; - } else { - /* NTSC */ - vbi_start = 8; - vbi_end = 20; - } - - vbi_offset0 = RADEON_ALIGN(pPriv->video_offset + mult * new_size * bpp, 0x10); - vbi_offset1 = vbi_offset0 + dstPitch*20; - OUTREG(RADEON_CAP0_VBI0_OFFSET, vbi_offset0+display_base); - OUTREG(RADEON_CAP0_VBI1_OFFSET, vbi_offset1+display_base); - OUTREG(RADEON_CAP0_VBI2_OFFSET, 0); - OUTREG(RADEON_CAP0_VBI3_OFFSET, 0); - OUTREG(RADEON_CAP0_VBI_V_WINDOW, vbi_start | (vbi_end<<16)); - OUTREG(RADEON_CAP0_VBI_H_WINDOW, 0 | (vbi_line_width)<<16); - } - - OUTREG(RADEON_CAP0_BUF_PITCH, dstPitch*mult/2); - OUTREG(RADEON_CAP0_H_WINDOW, (2*width)<<16); - OUTREG(RADEON_CAP0_V_WINDOW, (((height)+pPriv->v-1)<<16)|(pPriv->v-1)); - if(mult==2){ - OUTREG(RADEON_CAP0_CONFIG, ENABLE_RADEON_CAPTURE_BOB); - } else { - OUTREG(RADEON_CAP0_CONFIG, ENABLE_RADEON_CAPTURE_WEAVE); - } - OUTREG(RADEON_CAP0_DEBUG, 0); - - OUTREG(RADEON_VID_BUFFER_CONTROL, (1<<16) | 0x01); - OUTREG(RADEON_TEST_DEBUG_CNTL, 0); - - if(! pPriv->video_stream_active) - { - - RADEONWaitForIdleMMIO(pScrn); - OUTREG(RADEON_VIDEOMUX_CNTL, INREG(RADEON_VIDEOMUX_CNTL)|1 ); - OUTREG(RADEON_CAP0_PORT_MODE_CNTL, (pPriv->theatre!=NULL)? 1: 0); - OUTREG(RADEON_FCP_CNTL, RADEON_FCP0_SRC_PCLK); - OUTREG(RADEON_CAP0_TRIG_CNTL, 0x11); - if(pPriv->theatre != NULL) - { - RADEON_RT_SetEncoding(pScrn, pPriv); - } - if(pPriv->msp3430 != NULL) RADEON_MSP_SetEncoding(pPriv); - if(pPriv->tda9885 != NULL) RADEON_TDA9885_SetEncoding(pPriv); - if(pPriv->fi1236 != NULL) RADEON_FI1236_SetEncoding(pPriv); - if(pPriv->i2c != NULL)RADEON_board_setmisc(pPriv); - } - - - /* update cliplist */ - if(!REGION_EQUAL(pScrn->pScreen, &pPriv->clip, clipBoxes)) { - REGION_COPY(pScreen, &pPriv->clip, clipBoxes); - /* draw these */ - if(pPriv->autopaint_colorkey) - RADEONFillKeyHelper(pDraw, pPriv->colorKey, clipBoxes); - } - - RADEONDisplayVideo(pScrn, crtc, pPriv, id, pPriv->video_offset, - offset1+top*srcPitch, offset2+top*srcPitch, - offset3+top*srcPitch, offset4+top*srcPitch, - offset1+top*srcPitch, offset2+top*srcPitch, width, height, - dstPitch*mult/2, xa, xb, ya, &dstBox, src_w, src_h*mult/2, - drw_w, drw_h, pPriv->overlay_deinterlacing_method); - - RADEONWaitForFifo(pScrn, 1); - OUTREG(RADEON_OV0_REG_LOAD_CNTL, RADEON_REG_LD_CTL_LOCK); - RADEONWaitForIdleMMIO(pScrn); - while(!(INREG(RADEON_OV0_REG_LOAD_CNTL) & RADEON_REG_LD_CTL_LOCK_READBACK)); - - - switch(pPriv->overlay_deinterlacing_method){ - case METHOD_BOB: - OUTREG(RADEON_OV0_DEINTERLACE_PATTERN, 0xAAAAA); - OUTREG(RADEON_OV0_AUTO_FLIP_CNTL,0 /*| RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD*/ - |RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN); - break; - case METHOD_SINGLE: - OUTREG(RADEON_OV0_DEINTERLACE_PATTERN, 0xEEEEE | (9<<28)); - OUTREG(RADEON_OV0_AUTO_FLIP_CNTL, RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD - |RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN); - break; - case METHOD_WEAVE: - OUTREG(RADEON_OV0_DEINTERLACE_PATTERN, 0x11111 | (9<<28)); - OUTREG(RADEON_OV0_AUTO_FLIP_CNTL, 0 |RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD - | RADEON_OV0_AUTO_FLIP_CNTL_P1_FIRST_LINE_EVEN - /* |RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN */ - /*|RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_EVEN_DOWN */ - |RADEON_OV0_AUTO_FLIP_CNTL_FIELD_POL_SOURCE); - break; - default: - OUTREG(RADEON_OV0_DEINTERLACE_PATTERN, 0xAAAAA); - OUTREG(RADEON_OV0_AUTO_FLIP_CNTL, RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD - |RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN); - } - - - RADEONWaitForIdleMMIO(pScrn); - OUTREG (RADEON_OV0_AUTO_FLIP_CNTL, (INREG (RADEON_OV0_AUTO_FLIP_CNTL) ^ RADEON_OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE )); - OUTREG (RADEON_OV0_AUTO_FLIP_CNTL, (INREG (RADEON_OV0_AUTO_FLIP_CNTL) ^ RADEON_OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE )); - - OUTREG(RADEON_OV0_REG_LOAD_CNTL, 0); - -#if 0 - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "OV0_FLAG_CNTL=0x%08x\n", INREG(RADEON_OV0_FLAG_CNTL)); -/* OUTREG(RADEON_OV0_FLAG_CNTL, 8); */ - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "OV0_VID_BUFFER_CNTL=0x%08x\n", INREG(RADEON_VID_BUFFER_CONTROL)); - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "CAP0_BUF_STATUS=0x%08x\n", INREG(RADEON_CAP0_BUF_STATUS)); - -/* OUTREG(RADEON_OV0_SCALE_CNTL, 0x417f1B00); */ -#endif - - pPriv->videoStatus = CLIENT_VIDEO_ON; - pPriv->video_stream_active = TRUE; - - info->VideoTimerCallback = RADEONVideoTimerCallback; - - return Success; -} - /* miscellaneous TV-in helper functions */ - -static void RADEON_board_setmisc(RADEONPortPrivPtr pPriv) -{ - /* Adjust PAL/SECAM constants for FI1216MF tuner */ - if((((pPriv->tuner_type & 0xf)==5) || - ((pPriv->tuner_type & 0xf)==11)|| - ((pPriv->tuner_type & 0xf)==14)) - && (pPriv->fi1236!=NULL)) - { - if((pPriv->encoding>=1)&&(pPriv->encoding<=3)) /*PAL*/ - { - pPriv->fi1236->parm.band_low = 0xA1; - pPriv->fi1236->parm.band_mid = 0x91; - pPriv->fi1236->parm.band_high = 0x31; - } - if((pPriv->encoding>=7)&&(pPriv->encoding<=9)) /*SECAM*/ - { - pPriv->fi1236->parm.band_low = 0xA3; - pPriv->fi1236->parm.band_mid = 0x93; - pPriv->fi1236->parm.band_high = 0x33; - } - } - -} - -static void RADEON_RT_SetEncoding(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) -{ -int width, height; -RADEONWaitForIdleMMIO(pScrn); - -/* Disable VBI capture for anything but TV tuner */ -switch(pPriv->encoding){ - case 2: - case 5: - case 8: - pPriv->capture_vbi_data=1; - break; - default: - pPriv->capture_vbi_data=0; - } - -switch(pPriv->encoding){ - case 1: - xf86_RT_SetConnector(pPriv->theatre,DEC_COMPOSITE, 0); - xf86_RT_SetStandard(pPriv->theatre,DEC_PAL | extPAL); - pPriv->v=25; - break; - case 2: - xf86_RT_SetConnector(pPriv->theatre,DEC_TUNER,0); - xf86_RT_SetStandard(pPriv->theatre,DEC_PAL | extPAL); - pPriv->v=25; - break; - case 3: - xf86_RT_SetConnector(pPriv->theatre,DEC_SVIDEO,0); - xf86_RT_SetStandard(pPriv->theatre,DEC_PAL | extPAL); - pPriv->v=25; - break; - case 4: - xf86_RT_SetConnector(pPriv->theatre, DEC_COMPOSITE,0); - xf86_RT_SetStandard(pPriv->theatre,DEC_NTSC | extNONE); - pPriv->v=23; - break; - case 5: - xf86_RT_SetConnector(pPriv->theatre, DEC_TUNER, 0); - xf86_RT_SetStandard(pPriv->theatre,DEC_NTSC | extNONE); - pPriv->v=23; - break; - case 6: - xf86_RT_SetConnector(pPriv->theatre, DEC_SVIDEO, 0); - xf86_RT_SetStandard(pPriv->theatre,DEC_NTSC | extNONE); - pPriv->v=23; - break; - case 7: - xf86_RT_SetConnector(pPriv->theatre, DEC_COMPOSITE, 0); - xf86_RT_SetStandard(pPriv->theatre,DEC_SECAM | extNONE); - pPriv->v=25; - break; - case 8: - xf86_RT_SetConnector(pPriv->theatre, DEC_TUNER, 0); - xf86_RT_SetStandard(pPriv->theatre,DEC_SECAM | extNONE); - pPriv->v=25; - break; - case 9: - xf86_RT_SetConnector(pPriv->theatre, DEC_SVIDEO, 0); - xf86_RT_SetStandard(pPriv->theatre,DEC_SECAM | extNONE); - pPriv->v=25; - break; - case 10: - xf86_RT_SetConnector(pPriv->theatre,DEC_COMPOSITE, 0); - xf86_RT_SetStandard(pPriv->theatre,DEC_PAL | extPAL_60); - pPriv->v=25; - break; - case 11: - xf86_RT_SetConnector(pPriv->theatre,DEC_TUNER,0); - xf86_RT_SetStandard(pPriv->theatre,DEC_PAL | extPAL_60); - pPriv->v=25; - break; - case 12: - xf86_RT_SetConnector(pPriv->theatre,DEC_SVIDEO,0); - xf86_RT_SetStandard(pPriv->theatre,DEC_PAL | extPAL_60); - pPriv->v=25; - break; - default: - pPriv->v=0; - return; - } -xf86_RT_SetInterlace(pPriv->theatre, 1); -width = InputVideoEncodings[pPriv->encoding].width; -height = InputVideoEncodings[pPriv->encoding].height; -xf86_RT_SetOutputVideoSize(pPriv->theatre, width, height*2, 0, pPriv->capture_vbi_data); -} - -static void RADEON_MSP_SetEncoding(RADEONPortPrivPtr pPriv) -{ -xf86_MSP3430SetVolume(pPriv->msp3430, MSP3430_FAST_MUTE); -switch(pPriv->encoding){ - case 1: - pPriv->msp3430->standard = MSP3430_PAL; - pPriv->msp3430->connector = MSP3430_CONNECTOR_3; - break; - case 2: - pPriv->msp3430->standard = MSP3430_PAL; - pPriv->msp3430->connector = MSP3430_CONNECTOR_1; - break; - case 3: - pPriv->msp3430->standard = MSP3430_PAL; - pPriv->msp3430->connector = MSP3430_CONNECTOR_2; - break; - case 4: - pPriv->msp3430->standard = MSP3430_NTSC; - pPriv->msp3430->connector = MSP3430_CONNECTOR_3; - break; - case 5: - pPriv->msp3430->standard = MSP3430_NTSC; - pPriv->msp3430->connector = MSP3430_CONNECTOR_1; - break; - case 6: - pPriv->msp3430->standard = MSP3430_NTSC; - pPriv->msp3430->connector = MSP3430_CONNECTOR_2; - break; - case 7: - pPriv->msp3430->standard = MSP3430_SECAM; - pPriv->msp3430->connector = MSP3430_CONNECTOR_3; - break; - case 8: - pPriv->msp3430->standard = MSP3430_SECAM; - pPriv->msp3430->connector = MSP3430_CONNECTOR_1; - break; - case 9: - pPriv->msp3430->standard = MSP3430_SECAM; - pPriv->msp3430->connector = MSP3430_CONNECTOR_2; - break; - case 10: - pPriv->msp3430->standard = MSP3430_SECAM; - pPriv->msp3430->connector = MSP3430_CONNECTOR_3; - break; - case 11: - pPriv->msp3430->standard = MSP3430_SECAM; - pPriv->msp3430->connector = MSP3430_CONNECTOR_1; - break; - case 12: - pPriv->msp3430->standard = MSP3430_SECAM; - pPriv->msp3430->connector = MSP3430_CONNECTOR_2; - break; - default: - return; - } -xf86_InitMSP3430(pPriv->msp3430); -xf86_MSP3430SetVolume(pPriv->msp3430, pPriv->mute ? MSP3430_FAST_MUTE : MSP3430_VOLUME(pPriv->volume)); -} - -static void RADEON_TDA9885_SetEncoding(RADEONPortPrivPtr pPriv) -{ -TDA9885Ptr t=pPriv->tda9885; - -switch(pPriv->encoding){ - /* PAL */ - case 1: - case 2: - case 3: - t->standard_video_if=2; - t->standard_sound_carrier=1; - t->modulation=2; /* negative FM */ - break; - /* NTSC */ - case 4: - case 5: - case 6: - t->standard_video_if=1; - t->standard_sound_carrier=0; - t->modulation=2; /* negative FM */ - break; - /* SECAM */ - case 7: - case 8: - case 9: - case 10: - case 11: - case 12: - t->standard_video_if=0; - t->standard_sound_carrier=3; - t->modulation=0; /* positive AM */ - break; - default: - return; - } -xf86_tda9885_setparameters(pPriv->tda9885); -xf86_tda9885_getstatus(pPriv->tda9885); -xf86_tda9885_dumpstatus(pPriv->tda9885); -} - -static void RADEON_FI1236_SetEncoding(RADEONPortPrivPtr pPriv) -{ -/* at the moment this only affect MT2032 */ -switch(pPriv->encoding){ - /* PAL */ - case 1: - case 2: - case 3: - pPriv->fi1236->video_if=38.900; - break; - /* NTSC */ - case 4: - case 5: - case 6: - pPriv->fi1236->video_if=45.7812; - pPriv->fi1236->video_if=45.750; - pPriv->fi1236->video_if=45.125; - break; - /* SECAM */ - case 7: - case 8: - case 9: - case 10: - case 11: - case 12: - pPriv->fi1236->video_if=58.7812; - break; - default: - return; - } -} - diff --git a/src/radeon_video.h b/src/radeon_video.h index 684cb9e7..e2bfd6f7 100644 --- a/src/radeon_video.h +++ b/src/radeon_video.h @@ -2,15 +2,8 @@ #define __RADEON_VIDEO_H__ #include "xf86i2c.h" -#include "fi1236.h" -#include "msp3430.h" -#include "tda9885.h" -#include "uda1380.h" #include "i2c_def.h" -#include "generic_bus.h" -#include "theatre.h" - #include "xf86Crtc.h" #include "bicubic_table.h" @@ -27,64 +20,12 @@ typedef struct { int saturation; int hue; int contrast; - int red_intensity; - int green_intensity; - int blue_intensity; - - /* overlay composition mode */ - int alpha_mode; /* 0 = key mode, 1 = global mode */ - int ov_alpha; - int gr_alpha; - - /* i2c bus and devices */ - I2CBusPtr i2c; - uint32_t radeon_i2c_timing; - uint32_t radeon_M; - uint32_t radeon_N; - uint32_t i2c_status; - uint32_t i2c_cntl; - - FI1236Ptr fi1236; - uint8_t tuner_type; - MSP3430Ptr msp3430; - TDA9885Ptr tda9885; - UDA1380Ptr uda1380; - - /* VIP bus and devices */ - GENERIC_BUS_Ptr VIP; - TheatrePtr theatre; - - Bool video_stream_active; - int encoding; - uint32_t frequency; - int volume; - Bool mute; - int sap_channel; - int v; - uint32_t adjustment; /* general purpose variable */ - -#define METHOD_BOB 0 -#define METHOD_SINGLE 1 -#define METHOD_WEAVE 2 -#define METHOD_ADAPTIVE 3 - - int overlay_deinterlacing_method; - - int capture_vbi_data; - - int dec_brightness; - int dec_saturation; - int dec_hue; - int dec_contrast; - - Bool doubleBuffer; + unsigned char currentBuffer; RegionRec clip; - uint32_t colorKey; - uint32_t videoStatus; + Time offTime; Time freeTime; - Bool autopaint_colorkey; xf86CrtcPtr desired_crtc; int size; @@ -103,8 +44,6 @@ typedef struct { #define BICUBIC_ON 1 #define BICUBIC_AUTO 2 - Atom device_id, location_id, instance_id; - /* textured video */ Bool textured; DrawablePtr pDraw; @@ -145,14 +84,6 @@ typedef struct tagREF_TRANSFORM #define RTFContrast(a) (1.0 + ((a)*1.0)/1000.0) #define RTFHue(a) (((a)*3.1416)/1000.0) -void RADEONInitI2C(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv); -void RADEONResetI2C(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv); - -void RADEONVIP_init(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv); -void RADEONVIP_reset(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv); - -int RADEONSetPortAttribute(ScrnInfoPtr, Atom, INT32, pointer); -int RADEONGetPortAttribute(ScrnInfoPtr, Atom ,INT32 *, pointer); void RADEONFreeVideoMemory(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv); void RADEONStopVideo(ScrnInfoPtr, pointer, Bool); void RADEONQueryBestSize(ScrnInfoPtr, Bool, short, short, short, short, diff --git a/src/radeon_vip.c b/src/radeon_vip.c deleted file mode 100644 index eacfc803..00000000 --- a/src/radeon_vip.c +++ /dev/null @@ -1,362 +0,0 @@ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include <string.h> - -#include "radeon.h" -#include "radeon_reg.h" -#include "radeon_macros.h" -#include "radeon_probe.h" -#include <X11/extensions/Xv.h> -#include "radeon_video.h" - -#include "xf86.h" -#include "atipciids.h" - -#include "generic_bus.h" -#include "theatre_reg.h" - -#define VIP_NAME "RADEON VIP BUS" -#define VIP_TYPE "ATI VIP BUS" - -/* Status defines */ -#define VIP_BUSY 0 -#define VIP_IDLE 1 -#define VIP_RESET 2 - -static Bool RADEONVIP_ioctl(GENERIC_BUS_Ptr b, long ioctl, long arg1, char *arg2) -{ - long count; - switch(ioctl){ - case GB_IOCTL_GET_NAME: - count=strlen(VIP_NAME)+1; - if(count>arg1)return FALSE; - memcpy(arg2,VIP_NAME,count); - return TRUE; - - case GB_IOCTL_GET_TYPE: - count=strlen(VIP_TYPE)+1; - if(count>arg1)return FALSE; - memcpy(arg2,VIP_TYPE,count); - return TRUE; - - default: - return FALSE; - } -} - -static uint32_t RADEONVIP_idle(GENERIC_BUS_Ptr b) -{ - ScrnInfoPtr pScrn = b->pScrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - uint32_t timeout; - - RADEONWaitForIdleMMIO(pScrn); - timeout = INREG(RADEON_VIPH_TIMEOUT_STAT); - if(timeout & RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_STAT) /* lockup ?? */ - { - RADEONWaitForFifo(pScrn, 2); - OUTREG(RADEON_VIPH_TIMEOUT_STAT, (timeout & 0xffffff00) | RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_AK); - RADEONWaitForIdleMMIO(pScrn); - return (INREG(RADEON_VIPH_CONTROL) & 0x2000) ? VIP_BUSY : VIP_RESET; - } - RADEONWaitForIdleMMIO(pScrn); - return (INREG(RADEON_VIPH_CONTROL) & 0x2000) ? VIP_BUSY : VIP_IDLE ; -} - -static uint32_t RADEONVIP_fifo_idle(GENERIC_BUS_Ptr b, uint8_t channel) -{ - ScrnInfoPtr pScrn = b->pScrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - uint32_t timeout; - - RADEONWaitForIdleMMIO(pScrn); - timeout = INREG(VIPH_TIMEOUT_STAT); - if((timeout & 0x0000000f) & channel) /* lockup ?? */ - { - xf86DrvMsg(b->pScrn->scrnIndex, X_INFO, "RADEON_fifo_idle\n"); - RADEONWaitForFifo(pScrn, 2); - OUTREG(VIPH_TIMEOUT_STAT, (timeout & 0xfffffff0) | channel); - RADEONWaitForIdleMMIO(pScrn); - return (INREG(VIPH_CONTROL) & 0x2000) ? VIP_BUSY : VIP_RESET; - } - RADEONWaitForIdleMMIO(pScrn); - return (INREG(VIPH_CONTROL) & 0x2000) ? VIP_BUSY : VIP_IDLE ; -} - -/* address format: - ((device & 0x3)<<14) | (fifo << 12) | (addr) -*/ - -#define VIP_WAIT_FOR_IDLE() { \ - int i2ctries = 0; \ - while (i2ctries < 10) { \ - status = RADEONVIP_idle(b); \ - if (status==VIP_BUSY) \ - { \ - usleep(1000); \ - i2ctries++; \ - } else break; \ - } \ - } - -static Bool RADEONVIP_read(GENERIC_BUS_Ptr b, uint32_t address, uint32_t count, uint8_t *buffer) -{ - ScrnInfoPtr pScrn = b->pScrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - uint32_t status,tmp; - - if((count!=1) && (count!=2) && (count!=4)) - { - xf86DrvMsg(pScrn->scrnIndex,X_ERROR,"Attempt to access VIP bus with non-stadard transaction length\n"); - return FALSE; - } - - RADEONWaitForFifo(pScrn, 2); - OUTREG(RADEON_VIPH_REG_ADDR, address | 0x2000); - write_mem_barrier(); - VIP_WAIT_FOR_IDLE(); - if(VIP_IDLE != status) return FALSE; - -/* - disable RADEON_VIPH_REGR_DIS to enable VIP cycle. - The LSB of RADEON_VIPH_TIMEOUT_STAT are set to 0 - because 1 would have acknowledged various VIP - interrupts unexpectedly -*/ - RADEONWaitForIdleMMIO(pScrn); - OUTREG(RADEON_VIPH_TIMEOUT_STAT, INREG(RADEON_VIPH_TIMEOUT_STAT) & (0xffffff00 & ~RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS) ); - write_mem_barrier(); -/* - the value returned here is garbage. The read merely initiates - a register cycle -*/ - RADEONWaitForIdleMMIO(pScrn); - INREG(RADEON_VIPH_REG_DATA); - - VIP_WAIT_FOR_IDLE(); - if(VIP_IDLE != status) return FALSE; -/* - set RADEON_VIPH_REGR_DIS so that the read won't take too long. -*/ - RADEONWaitForIdleMMIO(pScrn); - tmp=INREG(RADEON_VIPH_TIMEOUT_STAT); - OUTREG(RADEON_VIPH_TIMEOUT_STAT, (tmp & 0xffffff00) | RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS); - write_mem_barrier(); - RADEONWaitForIdleMMIO(pScrn); - switch(count){ - case 1: - *buffer=(uint8_t)(INREG(RADEON_VIPH_REG_DATA) & 0xff); - break; - case 2: - *(uint16_t *)buffer=(uint16_t) (INREG(RADEON_VIPH_REG_DATA) & 0xffff); - break; - case 4: - *(uint32_t *)buffer=(uint32_t) ( INREG(RADEON_VIPH_REG_DATA) & 0xffffffff); - break; - } - VIP_WAIT_FOR_IDLE(); - if(VIP_IDLE != status) return FALSE; - /* - so that reading RADEON_VIPH_REG_DATA would not trigger unnecessary vip cycles. -*/ - OUTREG(RADEON_VIPH_TIMEOUT_STAT, (INREG(RADEON_VIPH_TIMEOUT_STAT) & 0xffffff00) | RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS); - write_mem_barrier(); - return TRUE; -} - -static Bool RADEONVIP_fifo_read(GENERIC_BUS_Ptr b, uint32_t address, uint32_t count, uint8_t *buffer) -{ - ScrnInfoPtr pScrn = b->pScrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - uint32_t status,tmp; - - if(count!=1) - { - xf86DrvMsg(pScrn->scrnIndex,X_ERROR,"Attempt to access VIP bus with non-stadard transaction length\n"); - return FALSE; - } - - RADEONWaitForFifo(pScrn, 2); - OUTREG(VIPH_REG_ADDR, address | 0x3000); - write_mem_barrier(); - while(VIP_BUSY == (status = RADEONVIP_fifo_idle(b, 0xff))); - if(VIP_IDLE != status) return FALSE; - -/* - disable VIPH_REGR_DIS to enable VIP cycle. - The LSB of VIPH_TIMEOUT_STAT are set to 0 - because 1 would have acknowledged various VIP - interrupts unexpectedly -*/ - - RADEONWaitForIdleMMIO(pScrn); - OUTREG(VIPH_TIMEOUT_STAT, INREG(VIPH_TIMEOUT_STAT) & (0xffffff00 & ~VIPH_TIMEOUT_STAT__VIPH_REGR_DIS) ); - write_mem_barrier(); - -/* - the value returned here is garbage. The read merely initiates - a register cycle -*/ - RADEONWaitForIdleMMIO(pScrn); - INREG(VIPH_REG_DATA); - - while(VIP_BUSY == (status = RADEONVIP_fifo_idle(b, 0xff))); - if(VIP_IDLE != status) return FALSE; - -/* - set VIPH_REGR_DIS so that the read won't take too long. -*/ - RADEONWaitForIdleMMIO(pScrn); - tmp=INREG(VIPH_TIMEOUT_STAT); - OUTREG(VIPH_TIMEOUT_STAT, (tmp & 0xffffff00) | VIPH_TIMEOUT_STAT__VIPH_REGR_DIS); - write_mem_barrier(); - - RADEONWaitForIdleMMIO(pScrn); - switch(count){ - case 1: - *buffer=(uint8_t)(INREG(VIPH_REG_DATA) & 0xff); - break; - case 2: - *(uint16_t *)buffer=(uint16_t) (INREG(VIPH_REG_DATA) & 0xffff); - break; - case 4: - *(uint32_t *)buffer=(uint32_t) ( INREG(VIPH_REG_DATA) & 0xffffffff); - break; - } - while(VIP_BUSY == (status = RADEONVIP_fifo_idle(b, 0xff))); - if(VIP_IDLE != status) return FALSE; - - /* - so that reading VIPH_REG_DATA would not trigger unnecessary vip cycles. -*/ - OUTREG(VIPH_TIMEOUT_STAT, (INREG(VIPH_TIMEOUT_STAT) & 0xffffff00) | VIPH_TIMEOUT_STAT__VIPH_REGR_DIS); - write_mem_barrier(); - return TRUE; - - -} - - -static Bool RADEONVIP_write(GENERIC_BUS_Ptr b, uint32_t address, uint32_t count, uint8_t *buffer) -{ - ScrnInfoPtr pScrn = b->pScrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - uint32_t status; - - - if((count!=4)) - { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Attempt to access VIP bus with non-stadard transaction length\n"); - return FALSE; - } - - RADEONWaitForFifo(pScrn, 2); - OUTREG(RADEON_VIPH_REG_ADDR, address & (~0x2000)); - while(VIP_BUSY == (status = RADEONVIP_idle(b))); - - if(VIP_IDLE != status) return FALSE; - - RADEONWaitForFifo(pScrn, 2); - switch(count){ - case 4: - OUTREG(RADEON_VIPH_REG_DATA, *(uint32_t *)buffer); - break; - } - write_mem_barrier(); - while(VIP_BUSY == (status = RADEONVIP_idle(b))); - if(VIP_IDLE != status) return FALSE; - return TRUE; -} - -static Bool RADEONVIP_fifo_write(GENERIC_BUS_Ptr b, uint32_t address, uint32_t count, uint8_t *buffer) -{ - ScrnInfoPtr pScrn = b->pScrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - uint32_t status; - uint32_t i; - - RADEONWaitForFifo(pScrn, 2); - OUTREG(VIPH_REG_ADDR, (address & (~0x2000)) | 0x1000); - while(VIP_BUSY == (status = RADEONVIP_fifo_idle(b, 0x0f))); - - - if(VIP_IDLE != status){ - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "cannot write %x to VIPH_REG_ADDR\n", (unsigned int)address); - return FALSE; - } - - RADEONWaitForFifo(pScrn, 2); - for (i = 0; i < count; i+=4) - { - OUTREG(VIPH_REG_DATA, *(uint32_t*)(buffer + i)); - write_mem_barrier(); - while(VIP_BUSY == (status = RADEONVIP_fifo_idle(b, 0x0f))); - if(VIP_IDLE != status) - { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "cannot write to VIPH_REG_DATA\n"); - return FALSE; - } - } - - return TRUE; -} - -void RADEONVIP_reset(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) -{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - - - RADEONWaitForIdleMMIO(pScrn); - switch(info->ChipFamily){ - case CHIP_FAMILY_RV250: - case CHIP_FAMILY_RV350: - case CHIP_FAMILY_R350: - case CHIP_FAMILY_R300: - OUTREG(RADEON_VIPH_CONTROL, 0x003F0009); /* slowest, timeout in 16 phases */ - OUTREG(RADEON_VIPH_TIMEOUT_STAT, (INREG(RADEON_VIPH_TIMEOUT_STAT) & 0xFFFFFF00) | RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS); - OUTREG(RADEON_VIPH_DV_LAT, 0x444400FF); /* set timeslice */ - OUTREG(RADEON_VIPH_BM_CHUNK, 0x0); - OUTREG(RADEON_TEST_DEBUG_CNTL, INREG(RADEON_TEST_DEBUG_CNTL) & (~RADEON_TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN)); - break; - case CHIP_FAMILY_RV380: - OUTREG(RADEON_VIPH_CONTROL, 0x003F000D); /* slowest, timeout in 16 phases */ - OUTREG(RADEON_VIPH_TIMEOUT_STAT, (INREG(RADEON_VIPH_TIMEOUT_STAT) & 0xFFFFFF00) | RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS); - OUTREG(RADEON_VIPH_DV_LAT, 0x444400FF); /* set timeslice */ - OUTREG(RADEON_VIPH_BM_CHUNK, 0x0); - OUTREG(RADEON_TEST_DEBUG_CNTL, INREG(RADEON_TEST_DEBUG_CNTL) & (~RADEON_TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN)); - break; - default: - OUTREG(RADEON_VIPH_CONTROL, 0x003F0004); /* slowest, timeout in 16 phases */ - OUTREG(RADEON_VIPH_TIMEOUT_STAT, (INREG(RADEON_VIPH_TIMEOUT_STAT) & 0xFFFFFF00) | RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS); - OUTREG(RADEON_VIPH_DV_LAT, 0x444400FF); /* set timeslice */ - OUTREG(RADEON_VIPH_BM_CHUNK, 0x151); - OUTREG(RADEON_TEST_DEBUG_CNTL, INREG(RADEON_TEST_DEBUG_CNTL) & (~RADEON_TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN)); - } -} - -void RADEONVIP_init(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) -{ - pPriv->VIP=calloc(1,sizeof(GENERIC_BUS_Rec)); - pPriv->VIP->pScrn=pScrn; - pPriv->VIP->DriverPrivate.ptr=pPriv; - pPriv->VIP->ioctl=RADEONVIP_ioctl; - pPriv->VIP->read=RADEONVIP_read; - pPriv->VIP->write=RADEONVIP_write; - pPriv->VIP->fifo_read=RADEONVIP_fifo_read; - pPriv->VIP->fifo_write=RADEONVIP_fifo_write; - - RADEONVIP_reset(pScrn, pPriv); -} diff --git a/src/theatre.c b/src/theatre.c deleted file mode 100644 index 09640faf..00000000 --- a/src/theatre.c +++ /dev/null @@ -1,2211 +0,0 @@ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include <unistd.h> -#include "xf86.h" -#include "generic_bus.h" -#include "theatre.h" -#include "theatre_reg.h" - -#undef read -#undef write -#undef ioctl - -static Bool theatre_read(TheatrePtr t,uint32_t reg, uint32_t *data) -{ - if(t->theatre_num<0)return FALSE; - return t->VIP->read(t->VIP, ((t->theatre_num & 0x3)<<14) | reg,4, (uint8_t *) data); -} - -static Bool theatre_write(TheatrePtr t,uint32_t reg, uint32_t data) -{ - if(t->theatre_num<0)return FALSE; - return t->VIP->write(t->VIP,((t->theatre_num & 0x03)<<14) | reg,4, (uint8_t *) &data); -} - -#define RT_regr(reg,data) theatre_read(t,(reg),(data)) -#define RT_regw(reg,data) theatre_write(t,(reg),(data)) -#define VIP_TYPE "ATI VIP BUS" - -static void CalculateCrCbGain (TheatrePtr t, double *CrGain, double *CbGain, uint16_t wStandard); -static void RT_SetCombFilter (TheatrePtr t, uint16_t wStandard, uint16_t wConnector); - -#if 0 -TheatrePtr DetectTheatre(GENERIC_BUS_Ptr b) -{ - TheatrePtr t; - uint32_t i; - uint32_t val; - char s[20]; - - b->ioctl(b,GB_IOCTL_GET_TYPE,20,s); - if(strcmp(VIP_TYPE, s)){ - xf86DrvMsg(b->scrnIndex, X_ERROR, "DetectTheatre must be called with bus of type \"%s\", not \"%s\"\n", - VIP_TYPE, s); - return NULL; - } - - t = calloc(1,sizeof(TheatreRec)); - t->VIP = b; - t->theatre_num = -1; - t->mode=MODE_UNINITIALIZED; - - b->read(b, VIP_VIP_VENDOR_DEVICE_ID, 4, (uint8_t *)&val); - for(i=0;i<4;i++) - { - if(b->read(b, ((i & 0x03)<<14) | VIP_VIP_VENDOR_DEVICE_ID, 4, (uint8_t *)&val)) - { - if(val)xf86DrvMsg(b->scrnIndex, X_INFO, "Device %d on VIP bus ids as 0x%08x\n",i,val); - if(t->theatre_num>=0)continue; /* already found one instance */ - switch(val){ - case RT100_ATI_ID: - t->theatre_num=i; - t->theatre_id=RT100_ATI_ID; - break; - case RT200_ATI_ID: - t->theatre_num=i; - t->theatre_id=RT200_ATI_ID; - break; - } - } else { - xf86DrvMsg(b->scrnIndex, X_INFO, "No response from device %d on VIP bus\n",i); - } - } - if(t->theatre_num>=0)xf86DrvMsg(b->scrnIndex, X_INFO, "Detected Rage Theatre as device %d on VIP bus with id 0x%08x\n",t->theatre_num,t->theatre_id); - - if(t->theatre_id==RT200_ATI_ID){ - xf86DrvMsg(b->scrnIndex, X_INFO, "Rage Theatre 200 is not supported yet\n"); - t->theatre_num=-1; - } - - if(t->theatre_num < 0) - { - free(t); - return NULL; - } - - RT_regr(VIP_VIP_REVISION_ID, &val); - xf86DrvMsg(b->scrnIndex, X_INFO, "Detected Rage Theatre revision %8.8X\n", val); - -#if 0 -DumpRageTheatreRegsByName(t); -#endif - return t; -} -#endif - -enum -{ -fld_tmpReg1=0, -fld_tmpReg2, -fld_tmpReg3, -fld_LP_CONTRAST, -fld_LP_BRIGHTNESS, -fld_CP_HUE_CNTL, -fld_LUMA_FILTER, -fld_H_SCALE_RATIO, -fld_H_SHARPNESS, -fld_V_SCALE_RATIO, -fld_V_DEINTERLACE_ON, -fld_V_BYPSS, -fld_V_DITHER_ON, -fld_EVENF_OFFSET, -fld_ODDF_OFFSET, -fld_INTERLACE_DETECTED, -fld_VS_LINE_COUNT, -fld_VS_DETECTED_LINES, -fld_VS_ITU656_VB, -fld_VBI_CC_DATA, -fld_VBI_CC_WT, -fld_VBI_CC_WT_ACK, -fld_VBI_CC_HOLD, -fld_VBI_DECODE_EN, -fld_VBI_CC_DTO_P, -fld_VBI_20BIT_DTO_P, -fld_VBI_CC_LEVEL, -fld_VBI_20BIT_LEVEL, -fld_VBI_CLK_RUNIN_GAIN, -fld_H_VBI_WIND_START, -fld_H_VBI_WIND_END, -fld_V_VBI_WIND_START, -fld_V_VBI_WIND_END, -fld_VBI_20BIT_DATA0, -fld_VBI_20BIT_DATA1, -fld_VBI_20BIT_WT, -fld_VBI_20BIT_WT_ACK, -fld_VBI_20BIT_HOLD, -fld_VBI_CAPTURE_ENABLE, -fld_VBI_EDS_DATA, -fld_VBI_EDS_WT, -fld_VBI_EDS_WT_ACK, -fld_VBI_EDS_HOLD, -fld_VBI_SCALING_RATIO, -fld_VBI_ALIGNER_ENABLE, -fld_H_ACTIVE_START, -fld_H_ACTIVE_END, -fld_V_ACTIVE_START, -fld_V_ACTIVE_END, -fld_CH_HEIGHT, -fld_CH_KILL_LEVEL, -fld_CH_AGC_ERROR_LIM, -fld_CH_AGC_FILTER_EN, -fld_CH_AGC_LOOP_SPEED, -fld_HUE_ADJ, -fld_STANDARD_SEL, -fld_STANDARD_YC, -fld_ADC_PDWN, -fld_INPUT_SELECT, -fld_ADC_PREFLO, -fld_H_SYNC_PULSE_WIDTH, -fld_HS_GENLOCKED, -fld_HS_SYNC_IN_WIN, -fld_VIN_ASYNC_RST, -fld_DVS_ASYNC_RST, -fld_VIP_VENDOR_ID, -fld_VIP_DEVICE_ID, -fld_VIP_REVISION_ID, -fld_BLACK_INT_START, -fld_BLACK_INT_LENGTH, -fld_UV_INT_START, -fld_U_INT_LENGTH, -fld_V_INT_LENGTH, -fld_CRDR_ACTIVE_GAIN, -fld_CBDB_ACTIVE_GAIN, -fld_DVS_DIRECTION, -fld_DVS_VBI_UINT8_SWAP, -fld_DVS_CLK_SELECT, -fld_CONTINUOUS_STREAM, -fld_DVSOUT_CLK_DRV, -fld_DVSOUT_DATA_DRV, -fld_COMB_CNTL0, -fld_COMB_CNTL1, -fld_COMB_CNTL2, -fld_COMB_LENGTH, -fld_SYNCTIP_REF0, -fld_SYNCTIP_REF1, -fld_CLAMP_REF, -fld_AGC_PEAKWHITE, -fld_VBI_PEAKWHITE, -fld_WPA_THRESHOLD, -fld_WPA_TRIGGER_LO, -fld_WPA_TRIGGER_HIGH, -fld_LOCKOUT_START, -fld_LOCKOUT_END, -fld_CH_DTO_INC, -fld_PLL_SGAIN, -fld_PLL_FGAIN, -fld_CR_BURST_GAIN, -fld_CB_BURST_GAIN, -fld_VERT_LOCKOUT_START, -fld_VERT_LOCKOUT_END, -fld_H_IN_WIND_START, -fld_V_IN_WIND_START, -fld_H_OUT_WIND_WIDTH, -fld_V_OUT_WIND_WIDTH, -fld_HS_LINE_TOTAL, -fld_MIN_PULSE_WIDTH, -fld_MAX_PULSE_WIDTH, -fld_WIN_CLOSE_LIMIT, -fld_WIN_OPEN_LIMIT, -fld_VSYNC_INT_TRIGGER, -fld_VSYNC_INT_HOLD, -fld_VIN_M0, -fld_VIN_N0, -fld_MNFLIP_EN, -fld_VIN_P, -fld_REG_CLK_SEL, -fld_VIN_M1, -fld_VIN_N1, -fld_VIN_DRIVER_SEL, -fld_VIN_MNFLIP_REQ, -fld_VIN_MNFLIP_DONE, -fld_TV_LOCK_TO_VIN, -fld_TV_P_FOR_WINCLK, -fld_VINRST, -fld_VIN_CLK_SEL, -fld_VS_FIELD_BLANK_START, -fld_VS_FIELD_BLANK_END, -fld_VS_FIELD_IDLOCATION, -fld_VS_FRAME_TOTAL, -fld_SYNC_TIP_START, -fld_SYNC_TIP_LENGTH, -fld_GAIN_FORCE_DATA, -fld_GAIN_FORCE_EN, -fld_I_CLAMP_SEL, -fld_I_AGC_SEL, -fld_EXT_CLAMP_CAP, -fld_EXT_AGC_CAP, -fld_DECI_DITHER_EN, -fld_ADC_PREFHI, -fld_ADC_CH_GAIN_SEL, -fld_HS_PLL_SGAIN, -fld_NREn, -fld_NRGainCntl, -fld_NRBWTresh, -fld_NRGCTresh, -fld_NRCoefDespeclMode, -fld_GPIO_5_OE, -fld_GPIO_6_OE, -fld_GPIO_5_OUT, -fld_GPIO_6_OUT, - -regRT_MAX_REGS -} a; - - -typedef struct { - uint8_t size; - uint32_t fld_id; - uint32_t dwRegAddrLSBs; - uint32_t dwFldOffsetLSBs; - uint32_t dwMaskLSBs; - uint32_t addr2; - uint32_t offs2; - uint32_t mask2; - uint32_t dwCurrValue; - uint32_t rw; -} RTREGMAP; - -#define READONLY 1 -#define WRITEONLY 2 -#define READWRITE 3 - -/* Rage Theatre's Register Mappings, including the default values: */ -RTREGMAP RT_RegMap[regRT_MAX_REGS]={ -/* -{size, fidname, AddrOfst, Ofst, Mask, Addr, Ofst, Mask, Cur, R/W -*/ -{32 , fld_tmpReg1 ,0x151 , 0, 0x0, 0, 0,0, 0,READWRITE }, -{1 , fld_tmpReg2 ,VIP_VIP_SUB_VENDOR_DEVICE_ID , 3, 0xFFFFFFFF, 0, 0,0, 0,READWRITE }, -{1 , fld_tmpReg3 ,VIP_VIP_COMMAND_STATUS , 3, 0xFFFFFFFF, 0, 0,0, 0,READWRITE }, -{8 , fld_LP_CONTRAST ,VIP_LP_CONTRAST , 0, 0xFFFFFF00, 0, 0,0, fld_LP_CONTRAST_def ,READWRITE }, -{14 , fld_LP_BRIGHTNESS ,VIP_LP_BRIGHTNESS , 0, 0xFFFFC000, 0, 0,0, fld_LP_BRIGHTNESS_def ,READWRITE }, -{8 , fld_CP_HUE_CNTL ,VIP_CP_HUE_CNTL , 0, 0xFFFFFF00, 0, 0,0, fld_CP_HUE_CNTL_def ,READWRITE }, -{1 , fld_LUMA_FILTER ,VIP_LP_BRIGHTNESS , 15, 0xFFFF7FFF, 0, 0,0, fld_LUMA_FILTER_def ,READWRITE }, -{21 , fld_H_SCALE_RATIO ,VIP_H_SCALER_CONTROL , 0, 0xFFE00000, 0, 0,0, fld_H_SCALE_RATIO_def ,READWRITE }, -{4 , fld_H_SHARPNESS ,VIP_H_SCALER_CONTROL , 25, 0xE1FFFFFF, 0, 0,0, fld_H_SHARPNESS_def ,READWRITE }, -{12 , fld_V_SCALE_RATIO ,VIP_V_SCALER_CONTROL , 0, 0xFFFFF000, 0, 0,0, fld_V_SCALE_RATIO_def ,READWRITE }, -{1 , fld_V_DEINTERLACE_ON,VIP_V_SCALER_CONTROL , 12, 0xFFFFEFFF, 0, 0,0, fld_V_DEINTERLACE_ON_def ,READWRITE }, -{1 , fld_V_BYPSS ,VIP_V_SCALER_CONTROL , 14, 0xFFFFBFFF, 0, 0,0, fld_V_BYPSS_def ,READWRITE }, -{1 , fld_V_DITHER_ON ,VIP_V_SCALER_CONTROL , 15, 0xFFFF7FFF, 0, 0,0, fld_V_DITHER_ON_def ,READWRITE }, -{11 , fld_EVENF_OFFSET ,VIP_V_DEINTERLACE_CONTROL , 0, 0xFFFFF800, 0, 0,0, fld_EVENF_OFFSET_def ,READWRITE }, -{11 , fld_ODDF_OFFSET ,VIP_V_DEINTERLACE_CONTROL , 11, 0xFFC007FF, 0, 0,0, fld_ODDF_OFFSET_def ,READWRITE }, -{1 , fld_INTERLACE_DETECTED ,VIP_VS_LINE_COUNT , 15, 0xFFFF7FFF, 0, 0,0, fld_INTERLACE_DETECTED_def,READONLY }, -{10 , fld_VS_LINE_COUNT ,VIP_VS_LINE_COUNT , 0, 0xFFFFFC00, 0, 0,0, fld_VS_LINE_COUNT_def ,READONLY }, -{10 , fld_VS_DETECTED_LINES ,VIP_VS_LINE_COUNT , 16, 0xFC00FFFF, 0, 0,0, fld_VS_DETECTED_LINES_def ,READONLY }, -{1 , fld_VS_ITU656_VB ,VIP_VS_LINE_COUNT , 13, 0xFFFFDFFF, 0, 0,0, fld_VS_ITU656_VB_def ,READONLY }, -{16 , fld_VBI_CC_DATA ,VIP_VBI_CC_CNTL , 0, 0xFFFF0000, 0, 0,0, fld_VBI_CC_DATA_def ,READWRITE }, -{1 , fld_VBI_CC_WT ,VIP_VBI_CC_CNTL , 24, 0xFEFFFFFF, 0, 0,0, fld_VBI_CC_WT_def ,READWRITE }, -{1 , fld_VBI_CC_WT_ACK ,VIP_VBI_CC_CNTL , 25, 0xFDFFFFFF, 0, 0,0, fld_VBI_CC_WT_ACK_def ,READONLY }, -{1 , fld_VBI_CC_HOLD ,VIP_VBI_CC_CNTL , 26, 0xFBFFFFFF, 0, 0,0, fld_VBI_CC_HOLD_def ,READWRITE }, -{1 , fld_VBI_DECODE_EN ,VIP_VBI_CC_CNTL , 31, 0x7FFFFFFF, 0, 0,0, fld_VBI_DECODE_EN_def ,READWRITE }, -{16 , fld_VBI_CC_DTO_P ,VIP_VBI_DTO_CNTL , 0, 0xFFFF0000, 0, 0,0, fld_VBI_CC_DTO_P_def ,READWRITE }, -{16 ,fld_VBI_20BIT_DTO_P,VIP_VBI_DTO_CNTL , 16, 0x0000FFFF, 0, 0,0, fld_VBI_20BIT_DTO_P_def ,READWRITE }, -{7 ,fld_VBI_CC_LEVEL ,VIP_VBI_LEVEL_CNTL , 0, 0xFFFFFF80, 0, 0,0, fld_VBI_CC_LEVEL_def ,READWRITE }, -{7 ,fld_VBI_20BIT_LEVEL,VIP_VBI_LEVEL_CNTL , 8, 0xFFFF80FF, 0, 0,0, fld_VBI_20BIT_LEVEL_def ,READWRITE }, -{9 ,fld_VBI_CLK_RUNIN_GAIN,VIP_VBI_LEVEL_CNTL , 16, 0xFE00FFFF, 0, 0,0, fld_VBI_CLK_RUNIN_GAIN_def,READWRITE }, -{11 ,fld_H_VBI_WIND_START,VIP_H_VBI_WINDOW , 0, 0xFFFFF800, 0, 0,0, fld_H_VBI_WIND_START_def ,READWRITE }, -{11 ,fld_H_VBI_WIND_END,VIP_H_VBI_WINDOW , 16, 0xF800FFFF, 0, 0,0, fld_H_VBI_WIND_END_def ,READWRITE }, -{10 ,fld_V_VBI_WIND_START,VIP_V_VBI_WINDOW , 0, 0xFFFFFC00, 0, 0,0, fld_V_VBI_WIND_START_def ,READWRITE }, -{10 ,fld_V_VBI_WIND_END,VIP_V_VBI_WINDOW , 16, 0xFC00FFFF, 0, 0,0, fld_V_VBI_WIND_END_def ,READWRITE }, /* CHK */ -{16 ,fld_VBI_20BIT_DATA0,VIP_VBI_20BIT_CNTL , 0, 0xFFFF0000, 0, 0,0, fld_VBI_20BIT_DATA0_def ,READWRITE }, -{4 ,fld_VBI_20BIT_DATA1,VIP_VBI_20BIT_CNTL , 16, 0xFFF0FFFF, 0, 0,0, fld_VBI_20BIT_DATA1_def ,READWRITE }, -{1 ,fld_VBI_20BIT_WT ,VIP_VBI_20BIT_CNTL , 24, 0xFEFFFFFF, 0, 0,0, fld_VBI_20BIT_WT_def ,READWRITE }, -{1 ,fld_VBI_20BIT_WT_ACK ,VIP_VBI_20BIT_CNTL , 25, 0xFDFFFFFF, 0, 0,0, fld_VBI_20BIT_WT_ACK_def ,READONLY }, -{1 ,fld_VBI_20BIT_HOLD ,VIP_VBI_20BIT_CNTL , 26, 0xFBFFFFFF, 0, 0,0, fld_VBI_20BIT_HOLD_def ,READWRITE }, -{2 ,fld_VBI_CAPTURE_ENABLE ,VIP_VBI_CONTROL , 0, 0xFFFFFFFC, 0, 0,0, fld_VBI_CAPTURE_ENABLE_def,READWRITE }, -{16 ,fld_VBI_EDS_DATA ,VIP_VBI_EDS_CNTL , 0, 0xFFFF0000, 0, 0,0, fld_VBI_EDS_DATA_def ,READWRITE }, -{1 ,fld_VBI_EDS_WT ,VIP_VBI_EDS_CNTL , 24, 0xFEFFFFFF, 0, 0,0, fld_VBI_EDS_WT_def ,READWRITE }, -{1 ,fld_VBI_EDS_WT_ACK ,VIP_VBI_EDS_CNTL , 25, 0xFDFFFFFF, 0, 0,0, fld_VBI_EDS_WT_ACK_def ,READONLY }, -{1 ,fld_VBI_EDS_HOLD ,VIP_VBI_EDS_CNTL , 26, 0xFBFFFFFF, 0, 0,0, fld_VBI_EDS_HOLD_def ,READWRITE }, -{17 ,fld_VBI_SCALING_RATIO ,VIP_VBI_SCALER_CONTROL , 0, 0xFFFE0000, 0, 0,0, fld_VBI_SCALING_RATIO_def ,READWRITE }, -{1 ,fld_VBI_ALIGNER_ENABLE ,VIP_VBI_SCALER_CONTROL , 17, 0xFFFDFFFF, 0, 0,0, fld_VBI_ALIGNER_ENABLE_def,READWRITE }, -{11 ,fld_H_ACTIVE_START ,VIP_H_ACTIVE_WINDOW , 0, 0xFFFFF800, 0, 0,0, fld_H_ACTIVE_START_def ,READWRITE }, -{11 ,fld_H_ACTIVE_END ,VIP_H_ACTIVE_WINDOW , 16, 0xF800FFFF, 0, 0,0, fld_H_ACTIVE_END_def ,READWRITE }, -{10 ,fld_V_ACTIVE_START ,VIP_V_ACTIVE_WINDOW , 0, 0xFFFFFC00, 0, 0,0, fld_V_ACTIVE_START_def ,READWRITE }, -{10 ,fld_V_ACTIVE_END ,VIP_V_ACTIVE_WINDOW , 16, 0xFC00FFFF, 0, 0,0, fld_V_ACTIVE_END_def ,READWRITE }, -{8 ,fld_CH_HEIGHT ,VIP_CP_AGC_CNTL , 0, 0xFFFFFF00, 0, 0,0, fld_CH_HEIGHT_def ,READWRITE }, -{8 ,fld_CH_KILL_LEVEL ,VIP_CP_AGC_CNTL , 8, 0xFFFF00FF, 0, 0,0, fld_CH_KILL_LEVEL_def ,READWRITE }, -{2 ,fld_CH_AGC_ERROR_LIM ,VIP_CP_AGC_CNTL , 16, 0xFFFCFFFF, 0, 0,0, fld_CH_AGC_ERROR_LIM_def ,READWRITE }, -{1 ,fld_CH_AGC_FILTER_EN ,VIP_CP_AGC_CNTL , 18, 0xFFFBFFFF, 0, 0,0, fld_CH_AGC_FILTER_EN_def ,READWRITE }, -{1 ,fld_CH_AGC_LOOP_SPEED ,VIP_CP_AGC_CNTL , 19, 0xFFF7FFFF, 0, 0,0, fld_CH_AGC_LOOP_SPEED_def ,READWRITE }, -{8 ,fld_HUE_ADJ ,VIP_CP_HUE_CNTL , 0, 0xFFFFFF00, 0, 0,0, fld_HUE_ADJ_def ,READWRITE }, -{2 ,fld_STANDARD_SEL ,VIP_STANDARD_SELECT , 0, 0xFFFFFFFC, 0, 0,0, fld_STANDARD_SEL_def ,READWRITE }, -{1 ,fld_STANDARD_YC ,VIP_STANDARD_SELECT , 2, 0xFFFFFFFB, 0, 0,0, fld_STANDARD_YC_def ,READWRITE }, -{1 ,fld_ADC_PDWN ,VIP_ADC_CNTL , 7, 0xFFFFFF7F, 0, 0,0, fld_ADC_PDWN_def ,READWRITE }, -{3 ,fld_INPUT_SELECT ,VIP_ADC_CNTL , 0, 0xFFFFFFF8, 0, 0,0, fld_INPUT_SELECT_def ,READWRITE }, -{2 ,fld_ADC_PREFLO ,VIP_ADC_CNTL , 24, 0xFCFFFFFF, 0, 0,0, fld_ADC_PREFLO_def ,READWRITE }, -{8 ,fld_H_SYNC_PULSE_WIDTH ,VIP_HS_PULSE_WIDTH , 0, 0xFFFFFF00, 0, 0,0, fld_H_SYNC_PULSE_WIDTH_def,READONLY }, -{1 ,fld_HS_GENLOCKED ,VIP_HS_PULSE_WIDTH , 8, 0xFFFFFEFF, 0, 0,0, fld_HS_GENLOCKED_def ,READONLY }, -{1 ,fld_HS_SYNC_IN_WIN ,VIP_HS_PULSE_WIDTH , 9, 0xFFFFFDFF, 0, 0,0, fld_HS_SYNC_IN_WIN_def ,READONLY }, -{1 ,fld_VIN_ASYNC_RST ,VIP_MASTER_CNTL , 5, 0xFFFFFFDF, 0, 0,0, fld_VIN_ASYNC_RST_def ,READWRITE }, -{1 ,fld_DVS_ASYNC_RST ,VIP_MASTER_CNTL , 7, 0xFFFFFF7F, 0, 0,0, fld_DVS_ASYNC_RST_def ,READWRITE }, -{16 ,fld_VIP_VENDOR_ID ,VIP_VIP_VENDOR_DEVICE_ID, 0, 0xFFFF0000, 0, 0,0, fld_VIP_VENDOR_ID_def ,READONLY }, -{16 ,fld_VIP_DEVICE_ID ,VIP_VIP_VENDOR_DEVICE_ID,16, 0x0000FFFF, 0, 0,0, fld_VIP_DEVICE_ID_def ,READONLY }, -{16 ,fld_VIP_REVISION_ID ,VIP_VIP_REVISION_ID , 0, 0xFFFF0000, 0, 0,0, fld_VIP_REVISION_ID_def ,READONLY }, -{8 ,fld_BLACK_INT_START ,VIP_SG_BLACK_GATE , 0, 0xFFFFFF00, 0, 0,0, fld_BLACK_INT_START_def ,READWRITE }, -{4 ,fld_BLACK_INT_LENGTH ,VIP_SG_BLACK_GATE , 8, 0xFFFFF0FF, 0, 0,0, fld_BLACK_INT_LENGTH_def ,READWRITE }, -{8 ,fld_UV_INT_START ,VIP_SG_UVGATE_GATE , 0, 0xFFFFFF00, 0, 0,0, fld_UV_INT_START_def ,READWRITE }, -{4 ,fld_U_INT_LENGTH ,VIP_SG_UVGATE_GATE , 8, 0xFFFFF0FF, 0, 0,0, fld_U_INT_LENGTH_def ,READWRITE }, -{4 ,fld_V_INT_LENGTH ,VIP_SG_UVGATE_GATE , 12, 0xFFFF0FFF, 0, 0,0, fld_V_INT_LENGTH_def ,READWRITE }, -{10 ,fld_CRDR_ACTIVE_GAIN ,VIP_CP_ACTIVE_GAIN , 0, 0xFFFFFC00, 0, 0,0, fld_CRDR_ACTIVE_GAIN_def ,READWRITE }, -{10 ,fld_CBDB_ACTIVE_GAIN ,VIP_CP_ACTIVE_GAIN , 16, 0xFC00FFFF, 0, 0,0, fld_CBDB_ACTIVE_GAIN_def ,READWRITE }, -{1 ,fld_DVS_DIRECTION ,VIP_DVS_PORT_CTRL , 0, 0xFFFFFFFE, 0, 0,0, fld_DVS_DIRECTION_def ,READWRITE }, -{1 ,fld_DVS_VBI_UINT8_SWAP ,VIP_DVS_PORT_CTRL , 1, 0xFFFFFFFD, 0, 0,0, fld_DVS_VBI_UINT8_SWAP_def ,READWRITE }, -{1 ,fld_DVS_CLK_SELECT ,VIP_DVS_PORT_CTRL , 2, 0xFFFFFFFB, 0, 0,0, fld_DVS_CLK_SELECT_def ,READWRITE }, -{1 ,fld_CONTINUOUS_STREAM ,VIP_DVS_PORT_CTRL , 3, 0xFFFFFFF7, 0, 0,0, fld_CONTINUOUS_STREAM_def ,READWRITE }, -{1 ,fld_DVSOUT_CLK_DRV ,VIP_DVS_PORT_CTRL , 4, 0xFFFFFFEF, 0, 0,0, fld_DVSOUT_CLK_DRV_def ,READWRITE }, -{1 ,fld_DVSOUT_DATA_DRV ,VIP_DVS_PORT_CTRL , 5, 0xFFFFFFDF, 0, 0,0, fld_DVSOUT_DATA_DRV_def ,READWRITE }, -{32 ,fld_COMB_CNTL0 ,VIP_COMB_CNTL0 , 0, 0x00000000, 0, 0,0, fld_COMB_CNTL0_def ,READWRITE }, -{32 ,fld_COMB_CNTL1 ,VIP_COMB_CNTL1 , 0, 0x00000000, 0, 0,0, fld_COMB_CNTL1_def ,READWRITE }, -{32 ,fld_COMB_CNTL2 ,VIP_COMB_CNTL2 , 0, 0x00000000, 0, 0,0, fld_COMB_CNTL2_def ,READWRITE }, -{32 ,fld_COMB_LENGTH ,VIP_COMB_LINE_LENGTH , 0, 0x00000000, 0, 0,0, fld_COMB_LENGTH_def ,READWRITE }, -{8 ,fld_SYNCTIP_REF0 ,VIP_LP_AGC_CLAMP_CNTL0 , 0, 0xFFFFFF00, 0, 0,0, fld_SYNCTIP_REF0_def ,READWRITE }, -{8 ,fld_SYNCTIP_REF1 ,VIP_LP_AGC_CLAMP_CNTL0 , 8, 0xFFFF00FF, 0, 0,0, fld_SYNCTIP_REF1_def ,READWRITE }, -{8 ,fld_CLAMP_REF ,VIP_LP_AGC_CLAMP_CNTL0 , 16, 0xFF00FFFF, 0, 0,0, fld_CLAMP_REF_def ,READWRITE }, -{8 ,fld_AGC_PEAKWHITE ,VIP_LP_AGC_CLAMP_CNTL0 , 24, 0x00FFFFFF, 0, 0,0, fld_AGC_PEAKWHITE_def ,READWRITE }, -{8 ,fld_VBI_PEAKWHITE ,VIP_LP_AGC_CLAMP_CNTL1 , 0, 0xFFFFFF00, 0, 0,0, fld_VBI_PEAKWHITE_def ,READWRITE }, -{11 ,fld_WPA_THRESHOLD ,VIP_LP_WPA_CNTL0 , 0, 0xFFFFF800, 0, 0,0, fld_WPA_THRESHOLD_def ,READWRITE }, -{10 ,fld_WPA_TRIGGER_LO ,VIP_LP_WPA_CNTL1 , 0, 0xFFFFFC00, 0, 0,0, fld_WPA_TRIGGER_LO_def ,READWRITE }, -{10 ,fld_WPA_TRIGGER_HIGH ,VIP_LP_WPA_CNTL1 , 16, 0xFC00FFFF, 0, 0,0, fld_WPA_TRIGGER_HIGH_def ,READWRITE }, -{10 ,fld_LOCKOUT_START ,VIP_LP_VERT_LOCKOUT , 0, 0xFFFFFC00, 0, 0,0, fld_LOCKOUT_START_def ,READWRITE }, -{10 ,fld_LOCKOUT_END ,VIP_LP_VERT_LOCKOUT , 16, 0xFC00FFFF, 0, 0,0, fld_LOCKOUT_END_def ,READWRITE }, -{24 ,fld_CH_DTO_INC ,VIP_CP_PLL_CNTL0 , 0, 0xFF000000, 0, 0,0, fld_CH_DTO_INC_def ,READWRITE }, -{4 ,fld_PLL_SGAIN ,VIP_CP_PLL_CNTL0 , 24, 0xF0FFFFFF, 0, 0,0, fld_PLL_SGAIN_def ,READWRITE }, -{4 ,fld_PLL_FGAIN ,VIP_CP_PLL_CNTL0 , 28, 0x0FFFFFFF, 0, 0,0, fld_PLL_FGAIN_def ,READWRITE }, -{9 ,fld_CR_BURST_GAIN ,VIP_CP_BURST_GAIN , 0, 0xFFFFFE00, 0, 0,0, fld_CR_BURST_GAIN_def ,READWRITE }, -{9 ,fld_CB_BURST_GAIN ,VIP_CP_BURST_GAIN , 16, 0xFE00FFFF, 0, 0,0, fld_CB_BURST_GAIN_def ,READWRITE }, -{10 ,fld_VERT_LOCKOUT_START ,VIP_CP_VERT_LOCKOUT , 0, 0xFFFFFC00, 0, 0,0, fld_VERT_LOCKOUT_START_def,READWRITE }, -{10 ,fld_VERT_LOCKOUT_END ,VIP_CP_VERT_LOCKOUT , 16, 0xFC00FFFF, 0, 0,0, fld_VERT_LOCKOUT_END_def ,READWRITE }, -{11 ,fld_H_IN_WIND_START ,VIP_SCALER_IN_WINDOW , 0, 0xFFFFF800, 0, 0,0, fld_H_IN_WIND_START_def ,READWRITE }, -{10 ,fld_V_IN_WIND_START ,VIP_SCALER_IN_WINDOW , 16, 0xFC00FFFF, 0, 0,0, fld_V_IN_WIND_START_def ,READWRITE }, -{10 ,fld_H_OUT_WIND_WIDTH ,VIP_SCALER_OUT_WINDOW , 0, 0xFFFFFC00, 0, 0,0, fld_H_OUT_WIND_WIDTH_def ,READWRITE }, -{9 ,fld_V_OUT_WIND_WIDTH ,VIP_SCALER_OUT_WINDOW , 16, 0xFE00FFFF, 0, 0,0, fld_V_OUT_WIND_WIDTH_def ,READWRITE }, -{11 ,fld_HS_LINE_TOTAL ,VIP_HS_PLINE , 0, 0xFFFFF800, 0, 0,0, fld_HS_LINE_TOTAL_def ,READWRITE }, -{8 ,fld_MIN_PULSE_WIDTH ,VIP_HS_MINMAXWIDTH , 0, 0xFFFFFF00, 0, 0,0, fld_MIN_PULSE_WIDTH_def ,READWRITE }, -{8 ,fld_MAX_PULSE_WIDTH ,VIP_HS_MINMAXWIDTH , 8, 0xFFFF00FF, 0, 0,0, fld_MAX_PULSE_WIDTH_def ,READWRITE }, -{11 ,fld_WIN_CLOSE_LIMIT ,VIP_HS_WINDOW_LIMIT , 0, 0xFFFFF800, 0, 0,0, fld_WIN_CLOSE_LIMIT_def ,READWRITE }, -{11 ,fld_WIN_OPEN_LIMIT ,VIP_HS_WINDOW_LIMIT , 16, 0xF800FFFF, 0, 0,0, fld_WIN_OPEN_LIMIT_def ,READWRITE }, -{11 ,fld_VSYNC_INT_TRIGGER ,VIP_VS_DETECTOR_CNTL , 0, 0xFFFFF800, 0, 0,0, fld_VSYNC_INT_TRIGGER_def ,READWRITE }, -{11 ,fld_VSYNC_INT_HOLD ,VIP_VS_DETECTOR_CNTL , 16, 0xF800FFFF, 0, 0,0, fld_VSYNC_INT_HOLD_def ,READWRITE }, -{11 ,fld_VIN_M0 ,VIP_VIN_PLL_CNTL , 0, 0xFFFFF800, 0, 0,0, fld_VIN_M0_def ,READWRITE }, -{11 ,fld_VIN_N0 ,VIP_VIN_PLL_CNTL , 11, 0xFFC007FF, 0, 0,0, fld_VIN_N0_def ,READWRITE }, -{1 ,fld_MNFLIP_EN ,VIP_VIN_PLL_CNTL , 22, 0xFFBFFFFF, 0, 0,0, fld_MNFLIP_EN_def ,READWRITE }, -{4 ,fld_VIN_P ,VIP_VIN_PLL_CNTL , 24, 0xF0FFFFFF, 0, 0,0, fld_VIN_P_def ,READWRITE }, -{2 ,fld_REG_CLK_SEL ,VIP_VIN_PLL_CNTL , 30, 0x3FFFFFFF, 0, 0,0, fld_REG_CLK_SEL_def ,READWRITE }, -{11 ,fld_VIN_M1 ,VIP_VIN_PLL_FINE_CNTL , 0, 0xFFFFF800, 0, 0,0, fld_VIN_M1_def ,READWRITE }, -{11 ,fld_VIN_N1 ,VIP_VIN_PLL_FINE_CNTL , 11, 0xFFC007FF, 0, 0,0, fld_VIN_N1_def ,READWRITE }, -{1 ,fld_VIN_DRIVER_SEL ,VIP_VIN_PLL_FINE_CNTL , 22, 0xFFBFFFFF, 0, 0,0, fld_VIN_DRIVER_SEL_def ,READWRITE }, -{1 ,fld_VIN_MNFLIP_REQ ,VIP_VIN_PLL_FINE_CNTL , 23, 0xFF7FFFFF, 0, 0,0, fld_VIN_MNFLIP_REQ_def ,READWRITE }, -{1 ,fld_VIN_MNFLIP_DONE ,VIP_VIN_PLL_FINE_CNTL , 24, 0xFEFFFFFF, 0, 0,0, fld_VIN_MNFLIP_DONE_def ,READONLY }, -{1 ,fld_TV_LOCK_TO_VIN ,VIP_VIN_PLL_FINE_CNTL , 27, 0xF7FFFFFF, 0, 0,0, fld_TV_LOCK_TO_VIN_def ,READWRITE }, -{4 ,fld_TV_P_FOR_WINCLK ,VIP_VIN_PLL_FINE_CNTL , 28, 0x0FFFFFFF, 0, 0,0, fld_TV_P_FOR_WINCLK_def ,READWRITE }, -{1 ,fld_VINRST ,VIP_PLL_CNTL1 , 1, 0xFFFFFFFD, 0, 0,0, fld_VINRST_def ,READWRITE }, -{1 ,fld_VIN_CLK_SEL ,VIP_CLOCK_SEL_CNTL , 7, 0xFFFFFF7F, 0, 0,0, fld_VIN_CLK_SEL_def ,READWRITE }, -{10 ,fld_VS_FIELD_BLANK_START,VIP_VS_BLANKING_CNTL , 0, 0xFFFFFC00, 0, 0,0, fld_VS_FIELD_BLANK_START_def ,READWRITE }, -{10 ,fld_VS_FIELD_BLANK_END,VIP_VS_BLANKING_CNTL , 16, 0xFC00FFFF, 0, 0,0, fld_VS_FIELD_BLANK_END_def ,READWRITE }, -{9 ,fld_VS_FIELD_IDLOCATION,VIP_VS_FIELD_ID_CNTL , 0, 0xFFFFFE00, 0, 0,0, fld_VS_FIELD_IDLOCATION_def ,READWRITE }, -{10 ,fld_VS_FRAME_TOTAL ,VIP_VS_FRAME_TOTAL , 0, 0xFFFFFC00, 0, 0,0, fld_VS_FRAME_TOTAL_def ,READWRITE }, -{11 ,fld_SYNC_TIP_START ,VIP_SG_SYNCTIP_GATE , 0, 0xFFFFF800, 0, 0,0, fld_SYNC_TIP_START_def ,READWRITE }, -{4 ,fld_SYNC_TIP_LENGTH ,VIP_SG_SYNCTIP_GATE , 12, 0xFFFF0FFF, 0, 0,0, fld_SYNC_TIP_LENGTH_def ,READWRITE }, -{12 ,fld_GAIN_FORCE_DATA ,VIP_CP_DEBUG_FORCE , 0, 0xFFFFF000, 0, 0,0, fld_GAIN_FORCE_DATA_def ,READWRITE }, -{1 ,fld_GAIN_FORCE_EN ,VIP_CP_DEBUG_FORCE , 12, 0xFFFFEFFF, 0, 0,0, fld_GAIN_FORCE_EN_def ,READWRITE }, -{2 ,fld_I_CLAMP_SEL ,VIP_ADC_CNTL , 3, 0xFFFFFFE7, 0, 0,0, fld_I_CLAMP_SEL_def ,READWRITE }, -{2 ,fld_I_AGC_SEL ,VIP_ADC_CNTL , 5, 0xFFFFFF9F, 0, 0,0, fld_I_AGC_SEL_def ,READWRITE }, -{1 ,fld_EXT_CLAMP_CAP ,VIP_ADC_CNTL , 8, 0xFFFFFEFF, 0, 0,0, fld_EXT_CLAMP_CAP_def ,READWRITE }, -{1 ,fld_EXT_AGC_CAP ,VIP_ADC_CNTL , 9, 0xFFFFFDFF, 0, 0,0, fld_EXT_AGC_CAP_def ,READWRITE }, -{1 ,fld_DECI_DITHER_EN ,VIP_ADC_CNTL , 12, 0xFFFFEFFF, 0, 0,0, fld_DECI_DITHER_EN_def ,READWRITE }, -{2 ,fld_ADC_PREFHI ,VIP_ADC_CNTL , 22, 0xFF3FFFFF, 0, 0,0, fld_ADC_PREFHI_def ,READWRITE }, -{2 ,fld_ADC_CH_GAIN_SEL ,VIP_ADC_CNTL , 16, 0xFFFCFFFF, 0, 0,0, fld_ADC_CH_GAIN_SEL_def ,READWRITE }, -{4 ,fld_HS_PLL_SGAIN ,VIP_HS_PLLGAIN , 0, 0xFFFFFFF0, 0, 0,0, fld_HS_PLL_SGAIN_def ,READWRITE }, -{1 ,fld_NREn ,VIP_NOISE_CNTL0 , 0, 0xFFFFFFFE, 0, 0,0, fld_NREn_def ,READWRITE }, -{3 ,fld_NRGainCntl ,VIP_NOISE_CNTL0 , 1, 0xFFFFFFF1, 0, 0,0, fld_NRGainCntl_def ,READWRITE }, -{6 ,fld_NRBWTresh ,VIP_NOISE_CNTL0 , 4, 0xFFFFFC0F, 0, 0,0, fld_NRBWTresh_def ,READWRITE }, -{5 ,fld_NRGCTresh ,VIP_NOISE_CNTL0 , 10, 0xFFFF83FF, 0, 0,0, fld_NRGCTresh_def ,READWRITE }, -{1 ,fld_NRCoefDespeclMode ,VIP_NOISE_CNTL0 , 15, 0xFFFF7FFF, 0, 0,0, fld_NRCoefDespeclMode_def ,READWRITE }, -{1 ,fld_GPIO_5_OE ,VIP_GPIO_CNTL , 5, 0xFFFFFFDF, 0, 0,0, fld_GPIO_5_OE_def ,READWRITE }, -{1 ,fld_GPIO_6_OE ,VIP_GPIO_CNTL , 6, 0xFFFFFFBF, 0, 0,0, fld_GPIO_6_OE_def ,READWRITE }, -{1 ,fld_GPIO_5_OUT ,VIP_GPIO_INOUT , 5, 0xFFFFFFDF, 0, 0,0, fld_GPIO_5_OUT_def ,READWRITE }, -{1 ,fld_GPIO_6_OUT ,VIP_GPIO_INOUT , 6, 0xFFFFFFBF, 0, 0,0, fld_GPIO_6_OUT_def ,READWRITE }, -}; - -/* Rage Theatre's register fields default values: */ -uint32_t RT_RegDef[regRT_MAX_REGS]= -{ -fld_tmpReg1_def, -fld_tmpReg2_def, -fld_tmpReg3_def, -fld_LP_CONTRAST_def, -fld_LP_BRIGHTNESS_def, -fld_CP_HUE_CNTL_def, -fld_LUMA_FILTER_def, -fld_H_SCALE_RATIO_def, -fld_H_SHARPNESS_def, -fld_V_SCALE_RATIO_def, -fld_V_DEINTERLACE_ON_def, -fld_V_BYPSS_def, -fld_V_DITHER_ON_def, -fld_EVENF_OFFSET_def, -fld_ODDF_OFFSET_def, -fld_INTERLACE_DETECTED_def, -fld_VS_LINE_COUNT_def, -fld_VS_DETECTED_LINES_def, -fld_VS_ITU656_VB_def, -fld_VBI_CC_DATA_def, -fld_VBI_CC_WT_def, -fld_VBI_CC_WT_ACK_def, -fld_VBI_CC_HOLD_def, -fld_VBI_DECODE_EN_def, -fld_VBI_CC_DTO_P_def, -fld_VBI_20BIT_DTO_P_def, -fld_VBI_CC_LEVEL_def, -fld_VBI_20BIT_LEVEL_def, -fld_VBI_CLK_RUNIN_GAIN_def, -fld_H_VBI_WIND_START_def, -fld_H_VBI_WIND_END_def, -fld_V_VBI_WIND_START_def, -fld_V_VBI_WIND_END_def, -fld_VBI_20BIT_DATA0_def, -fld_VBI_20BIT_DATA1_def, -fld_VBI_20BIT_WT_def, -fld_VBI_20BIT_WT_ACK_def, -fld_VBI_20BIT_HOLD_def, -fld_VBI_CAPTURE_ENABLE_def, -fld_VBI_EDS_DATA_def, -fld_VBI_EDS_WT_def, -fld_VBI_EDS_WT_ACK_def, -fld_VBI_EDS_HOLD_def, -fld_VBI_SCALING_RATIO_def, -fld_VBI_ALIGNER_ENABLE_def, -fld_H_ACTIVE_START_def, -fld_H_ACTIVE_END_def, -fld_V_ACTIVE_START_def, -fld_V_ACTIVE_END_def, -fld_CH_HEIGHT_def, -fld_CH_KILL_LEVEL_def, -fld_CH_AGC_ERROR_LIM_def, -fld_CH_AGC_FILTER_EN_def, -fld_CH_AGC_LOOP_SPEED_def, -fld_HUE_ADJ_def, -fld_STANDARD_SEL_def, -fld_STANDARD_YC_def, -fld_ADC_PDWN_def, -fld_INPUT_SELECT_def, -fld_ADC_PREFLO_def, -fld_H_SYNC_PULSE_WIDTH_def, -fld_HS_GENLOCKED_def, -fld_HS_SYNC_IN_WIN_def, -fld_VIN_ASYNC_RST_def, -fld_DVS_ASYNC_RST_def, -fld_VIP_VENDOR_ID_def, -fld_VIP_DEVICE_ID_def, -fld_VIP_REVISION_ID_def, -fld_BLACK_INT_START_def, -fld_BLACK_INT_LENGTH_def, -fld_UV_INT_START_def, -fld_U_INT_LENGTH_def, -fld_V_INT_LENGTH_def, -fld_CRDR_ACTIVE_GAIN_def, -fld_CBDB_ACTIVE_GAIN_def, -fld_DVS_DIRECTION_def, -fld_DVS_VBI_UINT8_SWAP_def, -fld_DVS_CLK_SELECT_def, -fld_CONTINUOUS_STREAM_def, -fld_DVSOUT_CLK_DRV_def, -fld_DVSOUT_DATA_DRV_def, -fld_COMB_CNTL0_def, -fld_COMB_CNTL1_def, -fld_COMB_CNTL2_def, -fld_COMB_LENGTH_def, -fld_SYNCTIP_REF0_def, -fld_SYNCTIP_REF1_def, -fld_CLAMP_REF_def, -fld_AGC_PEAKWHITE_def, -fld_VBI_PEAKWHITE_def, -fld_WPA_THRESHOLD_def, -fld_WPA_TRIGGER_LO_def, -fld_WPA_TRIGGER_HIGH_def, -fld_LOCKOUT_START_def, -fld_LOCKOUT_END_def, -fld_CH_DTO_INC_def, -fld_PLL_SGAIN_def, -fld_PLL_FGAIN_def, -fld_CR_BURST_GAIN_def, -fld_CB_BURST_GAIN_def, -fld_VERT_LOCKOUT_START_def, -fld_VERT_LOCKOUT_END_def, -fld_H_IN_WIND_START_def, -fld_V_IN_WIND_START_def, -fld_H_OUT_WIND_WIDTH_def, -fld_V_OUT_WIND_WIDTH_def, -fld_HS_LINE_TOTAL_def, -fld_MIN_PULSE_WIDTH_def, -fld_MAX_PULSE_WIDTH_def, -fld_WIN_CLOSE_LIMIT_def, -fld_WIN_OPEN_LIMIT_def, -fld_VSYNC_INT_TRIGGER_def, -fld_VSYNC_INT_HOLD_def, -fld_VIN_M0_def, -fld_VIN_N0_def, -fld_MNFLIP_EN_def, -fld_VIN_P_def, -fld_REG_CLK_SEL_def, -fld_VIN_M1_def, -fld_VIN_N1_def, -fld_VIN_DRIVER_SEL_def, -fld_VIN_MNFLIP_REQ_def, -fld_VIN_MNFLIP_DONE_def, -fld_TV_LOCK_TO_VIN_def, -fld_TV_P_FOR_WINCLK_def, -fld_VINRST_def, -fld_VIN_CLK_SEL_def, -fld_VS_FIELD_BLANK_START_def, -fld_VS_FIELD_BLANK_END_def, -fld_VS_FIELD_IDLOCATION_def, -fld_VS_FRAME_TOTAL_def, -fld_SYNC_TIP_START_def, -fld_SYNC_TIP_LENGTH_def, -fld_GAIN_FORCE_DATA_def, -fld_GAIN_FORCE_EN_def, -fld_I_CLAMP_SEL_def, -fld_I_AGC_SEL_def, -fld_EXT_CLAMP_CAP_def, -fld_EXT_AGC_CAP_def, -fld_DECI_DITHER_EN_def, -fld_ADC_PREFHI_def, -fld_ADC_CH_GAIN_SEL_def, -fld_HS_PLL_SGAIN_def, -fld_NREn_def, -fld_NRGainCntl_def, -fld_NRBWTresh_def, -fld_NRGCTresh_def, -fld_NRCoefDespeclMode_def, -fld_GPIO_5_OE_def, -fld_GPIO_6_OE_def, -fld_GPIO_5_OUT_def, -fld_GPIO_6_OUT_def, -}; - -/**************************************************************************** - * WriteRT_fld (uint32_t dwReg, uint32_t dwData) * - * Function: Writes a register field within Rage Theatre * - * Inputs: uint32_t dwReg = register field to be written * - * uint32_t dwData = data that will be written to the reg field * - * Outputs: NONE * - ****************************************************************************/ -static void WriteRT_fld1 (TheatrePtr t, uint32_t dwReg, uint32_t dwData) -{ - uint32_t dwResult=0; - uint32_t dwValue=0; - - if (RT_regr (RT_RegMap[dwReg].dwRegAddrLSBs, &dwResult) == TRUE) - { - dwValue = (dwResult & RT_RegMap[dwReg].dwMaskLSBs) | - (dwData << RT_RegMap[dwReg].dwFldOffsetLSBs); - - if (RT_regw (RT_RegMap[dwReg].dwRegAddrLSBs, dwValue) == TRUE) - { - /* update the memory mapped registers */ - RT_RegMap[dwReg].dwCurrValue = dwData; - } - - } - - return; - -} /* WriteRT_fld ()... */ - -/**************************************************************************** - * ReadRT_fld (uint32_t dwReg) * - * Function: Reads a register field within Rage Theatre * - * Inputs: uint32_t dwReg = register field to be read * - * Outputs: uint32_t - value read from register field * - ****************************************************************************/ -static uint32_t ReadRT_fld1 (TheatrePtr t,uint32_t dwReg) -{ - uint32_t dwResult=0; - - if (RT_regr (RT_RegMap[dwReg].dwRegAddrLSBs, &dwResult) == TRUE) - { - RT_RegMap[dwReg].dwCurrValue = ((dwResult & ~RT_RegMap[dwReg].dwMaskLSBs) >> - RT_RegMap[dwReg].dwFldOffsetLSBs); - return (RT_RegMap[dwReg].dwCurrValue); - } - else - { - return (0xFFFFFFFF); - } - -} /* ReadRT_fld ()... */ - -#define WriteRT_fld(a,b) WriteRT_fld1(t, (a), (b)) -#define ReadRT_fld(a) ReadRT_fld1(t,(a)) - -/**************************************************************************** - * RT_SetVINClock (uint16_t wStandard) * - * Function: to set the VIN clock for the selected standard * - * Inputs: uint16_t wStandard - input standard (NTSC, PAL, SECAM) * - * Outputs: NONE * - ****************************************************************************/ -static void RT_SetVINClock(TheatrePtr t, uint16_t wStandard) -{ - uint32_t dwM0=0, dwN0=0, dwP=0; - uint8_t ref_freq; - - /* Determine the reference frequency first. This can be obtained - from the MMTABLE.video_decoder_type field (bits 4:7) - The Rage Theatre currently only supports reference frequencies of - 27 or 29.49 MHz. */ - /* - R128ReadBIOS(0x48, - (uint8_t *)&bios_header, sizeof(bios_header)); - R128ReadBIOS(bios_header + 0x30, - (uint8_t *)&pll_info_block, sizeof(pll_info_block)); - - R128ReadBIOS(pll_info_block+0x07, &video_decoder_type, sizeof(video_decoder_type)); - */ - ref_freq = (t->video_decoder_type & 0xF0) >> 4; - - - switch (wStandard & 0x00FF) - { - case (DEC_NTSC): /* NTSC GROUP - 480 lines */ - switch (wStandard & 0xFF00) - { - case (extNONE): - case (extNTSC): - case (extNTSC_J): - if (ref_freq == RT_FREF_2950) - { - dwM0 = 0x39; - dwN0 = 0x14C; - dwP = 0x6; - } - else - { - dwM0 = 0x0B; - dwN0 = 0x46; - dwP = 0x6; - } - break; - - case (extNTSC_443): - if (ref_freq == RT_FREF_2950) - { - dwM0 = 0x23; - dwN0 = 0x88; - dwP = 0x7; - } - else - { - dwM0 = 0x2C; - dwN0 = 0x121; - dwP = 0x5; - } - break; - - case (extPAL_M): - if (ref_freq == RT_FREF_2950) - { - dwM0 = 0x2C; - dwN0 = 0x12B; - dwP = 0x7; - } - else - { - dwM0 = 0x0B; - dwN0 = 0x46; - dwP = 0x6; - } - break; - - default: - return; - } - break; - case (DEC_PAL): - switch (wStandard & 0xFF00) - { - case (extPAL): - case (extPAL_N): - case (extPAL_BGHI): - case (extPAL_60): - if (ref_freq == RT_FREF_2950) - { - dwM0 = 0x0E; - dwN0 = 0x65; - dwP = 0x6; - } - else - { - dwM0 = 0x2C; - dwN0 = 0x0121; - dwP = 0x5; - } - break; - - case (extPAL_NCOMB): - if (ref_freq == RT_FREF_2950) - { - dwM0 = 0x23; - dwN0 = 0x88; - dwP = 0x7; - } - else - { - dwM0 = 0x37; - dwN0 = 0x1D3; - dwP = 0x8; - } - break; - - default: - return; - } - break; - - case (DEC_SECAM): - if (ref_freq == RT_FREF_2950) - { - dwM0 = 0xE; - dwN0 = 0x65; - dwP = 0x6; - } - else - { - dwM0 = 0x2C; - dwN0 = 0x121; - dwP = 0x5; - } - break; - } - - /* VIN_PLL_CNTL */ - WriteRT_fld (fld_VIN_M0, dwM0); - WriteRT_fld (fld_VIN_N0, dwN0); - WriteRT_fld (fld_VIN_P, dwP); - - return; -} /* RT_SetVINClock ()... */ - -/**************************************************************************** - * RT_SetTint (int hue) * - * Function: sets the tint (hue) for the Rage Theatre video in * - * Inputs: int hue - the hue value to be set. * - * Outputs: NONE * - ****************************************************************************/ -_X_EXPORT void RT_SetTint (TheatrePtr t, int hue) -{ - uint32_t nhue = 0; - - t->iHue=hue; - /* Scale hue value from -1000<->1000 to -180<->180 */ - hue = (double)(hue+1000) * 0.18 - 180; - - /* Validate Hue level */ - if (hue < -180) - { - hue = -180; - } - else if (hue > 180) - { - hue = 180; - } - - /* save the "validated" hue, but scale it back up to -1000<->1000 */ - t->iHue = (double)hue/0.18; - - switch (t->wStandard & 0x00FF) - { - case (DEC_NTSC): /* original ATI code had _empty_ section for PAL/SECAM... which did not work, - obviously */ - case (DEC_PAL): - case (DEC_SECAM): - if (hue >= 0) - { - nhue = (uint32_t) (256 * hue)/360; - } - else - { - nhue = (uint32_t) (256 * (hue + 360))/360; - } - break; - - default: break; - } - - WriteRT_fld(fld_CP_HUE_CNTL, nhue); - - return; - -} /* RT_SetTint ()... */ - - -/**************************************************************************** - * RT_SetSaturation (int Saturation) * - * Function: sets the saturation level for the Rage Theatre video in * - * Inputs: int Saturation - the saturation value to be set. * - * Outputs: NONE * - ****************************************************************************/ -_X_EXPORT void RT_SetSaturation (TheatrePtr t, int Saturation) -{ - uint16_t wSaturation_V, wSaturation_U; - double dbSaturation = 0, dbCrGain = 0, dbCbGain = 0; - - /* VALIDATE SATURATION LEVEL */ - if (Saturation < -1000L) - { - Saturation = -1000; - } - else if (Saturation > 1000L) - { - Saturation = 1000; - } - - t->iSaturation = Saturation; - - if (Saturation > 0) - { - /* Scale saturation up, to use full allowable register width */ - Saturation = (double)(Saturation) * 4.9; - } - - dbSaturation = (double) (Saturation+1000.0) / 1000.0; - - CalculateCrCbGain (t, &dbCrGain, &dbCbGain, t->wStandard); - - wSaturation_U = (uint16_t) ((dbCrGain * dbSaturation * 128.0) + 0.5); - wSaturation_V = (uint16_t) ((dbCbGain * dbSaturation * 128.0) + 0.5); - - /* SET SATURATION LEVEL */ - WriteRT_fld (fld_CRDR_ACTIVE_GAIN, wSaturation_U); - WriteRT_fld (fld_CBDB_ACTIVE_GAIN, wSaturation_V); - - t->wSaturation_U = wSaturation_U; - t->wSaturation_V = wSaturation_V; - - return; - -} /* RT_SetSaturation ()...*/ - -/**************************************************************************** - * RT_SetBrightness (int Brightness) * - * Function: sets the brightness level for the Rage Theatre video in * - * Inputs: int Brightness - the brightness value to be set. * - * Outputs: NONE * - ****************************************************************************/ -_X_EXPORT void RT_SetBrightness (TheatrePtr t, int Brightness) -{ - double dbSynctipRef0=0, dbContrast=1; - - double dbYgain=0; - double dbBrightness=0; - double dbSetup=0; - uint16_t wBrightness=0; - - /* VALIDATE BRIGHTNESS LEVEL */ - if (Brightness < -1000) - { - Brightness = -1000; - } - else if (Brightness > 1000) - { - Brightness = 1000; - } - - /* Save value */ - t->iBrightness = Brightness; - - t->dbBrightnessRatio = (double) (Brightness+1000.0) / 10.0; - - dbBrightness = (double) (Brightness)/10.0; - - dbSynctipRef0 = ReadRT_fld (fld_SYNCTIP_REF0); - - if(t->dbContrast == 0) - { - t->dbContrast = 1.0; /*NTSC default; */ - } - - dbContrast = (double) t->dbContrast; - - /* Use the following formula to determine the brightness level */ - switch (t->wStandard & 0x00FF) - { - case (DEC_NTSC): - if ((t->wStandard & 0xFF00) == extNTSC_J) - { - dbYgain = 219.0 / ( 100.0 * (double)(dbSynctipRef0) /40.0); - } - else - { - dbSetup = 7.5 * (double)(dbSynctipRef0) / 40.0; - dbYgain = 219.0 / (92.5 * (double)(dbSynctipRef0) / 40.0); - } - break; - case (DEC_PAL): - case (DEC_SECAM): - dbYgain = 219.0 / ( 100.0 * (double)(dbSynctipRef0) /43.0); - break; - default: - break; - } - - wBrightness = (uint16_t) (16.0 * ((dbBrightness-dbSetup) + (16.0 / (dbContrast * dbYgain)))); - - WriteRT_fld (fld_LP_BRIGHTNESS, wBrightness); - - /*RT_SetSaturation (t->iSaturation); */ - - return; - -} /* RT_SetBrightness ()... */ - - -/**************************************************************************** - * RT_SetSharpness (uint16_t wSharpness) * - * Function: sets the sharpness level for the Rage Theatre video in * - * Inputs: uint16_t wSharpness - the sharpness value to be set. * - * Outputs: NONE * - ****************************************************************************/ -_X_EXPORT void RT_SetSharpness (TheatrePtr t, uint16_t wSharpness) -{ - switch (wSharpness) - { - case DEC_SMOOTH : - WriteRT_fld (fld_H_SHARPNESS, RT_NORM_SHARPNESS); - t->wSharpness = RT_NORM_SHARPNESS; - break; - case DEC_SHARP : - WriteRT_fld (fld_H_SHARPNESS, RT_HIGH_SHARPNESS); - t->wSharpness = RT_HIGH_SHARPNESS; - break; - default: - break; - } - return; - -} /* RT_SetSharpness ()... */ - - -/**************************************************************************** - * RT_SetContrast (int Contrast) * - * Function: sets the contrast level for the Rage Theatre video in * - * Inputs: int Contrast - the contrast value to be set. * - * Outputs: NONE * - ****************************************************************************/ -_X_EXPORT void RT_SetContrast (TheatrePtr t, int Contrast) -{ - double dbSynctipRef0=0, dbContrast=0; - double dbYgain=0; - uint8_t bTempContrast=0; - - /* VALIDATE CONTRAST LEVEL */ - if (Contrast < -1000) - { - Contrast = -1000; - } - else if (Contrast > 1000) - { - Contrast = 1000; - } - - /* Save contrast value */ - t->iContrast = Contrast; - - dbSynctipRef0 = ReadRT_fld (fld_SYNCTIP_REF0); - dbContrast = (double) (Contrast+1000.0) / 1000.0; - - switch (t->wStandard & 0x00FF) - { - case (DEC_NTSC): - if ((t->wStandard & 0xFF00) == (extNTSC_J)) - { - dbYgain = 219.0 / ( 100.0 * (double)(dbSynctipRef0) /40.0); - } - else - { - dbYgain = 219.0 / ( 92.5 * (double)(dbSynctipRef0) /40.0); - } - break; - case (DEC_PAL): - case (DEC_SECAM): - dbYgain = 219.0 / ( 100.0 * (double)(dbSynctipRef0) /43.0); - break; - default: - break; - } - - bTempContrast = (uint8_t) ((dbContrast * dbYgain * 64) + 0.5); - - WriteRT_fld (fld_LP_CONTRAST, (uint32_t)bTempContrast); - - /* Save value for future modification */ - t->dbContrast = dbContrast; - - return; - -} /* RT_SetContrast ()... */ - -/**************************************************************************** - * RT_SetInterlace (uint8_t bInterlace) * - * Function: to set the interlacing pattern for the Rage Theatre video in * - * Inputs: uint8_t bInterlace * - * Outputs: NONE * - ****************************************************************************/ -_X_EXPORT void RT_SetInterlace (TheatrePtr t, uint8_t bInterlace) -{ - - switch(bInterlace) - { - case (TRUE): /*DEC_INTERLACE */ - WriteRT_fld (fld_V_DEINTERLACE_ON, 0x1); - t->wInterlaced = (uint16_t) RT_DECINTERLACED; - break; - case (FALSE): /*DEC_NONINTERLACE */ - WriteRT_fld (fld_V_DEINTERLACE_ON, RT_DECNONINTERLACED); - t->wInterlaced = (uint16_t) RT_DECNONINTERLACED; - break; - default: - break; - } - - return; - -} /* RT_SetInterlace ()... */ - -/**************************************************************************** - * GetStandardConstants (double *LPeriod, double *FPeriod, * - * double *Fsamp, uint16_t wStandard) * - * Function: return timing values for a given standard * - * Inputs: double *LPeriod - - * double *FPeriod - - * double *Fsamp - sampling frequency used for a given standard * - * uint16_t wStandard - input standard (NTSC, PAL, SECAM) * - * Outputs: NONE * - ****************************************************************************/ -static void GetStandardConstants (double *LPeriod, double *FPeriod, - double *Fsamp, uint16_t wStandard) -{ - *LPeriod = 0.0; - *FPeriod = 0.0; - *Fsamp = 0.0; - - switch (wStandard & 0x00FF) - { - case (DEC_NTSC): /*NTSC GROUP - 480 lines*/ - switch (wStandard & 0xFF00) - { - case (extNONE): - case (extNTSC): - case (extNTSC_J): - *LPeriod = (double) 63.5555; - *FPeriod = (double) 16.6833; - *Fsamp = (double) 28.63636; - break; - case (extPAL_M): - *LPeriod = (double) 63.492; - *FPeriod = (double) 16.667; - *Fsamp = (double) 28.63689192; - break; - default: - return; - } - break; - case (DEC_PAL): - if( (wStandard & 0xFF00) == extPAL_N ) - { - *LPeriod = (double) 64.0; - *FPeriod = (double) 20.0; - *Fsamp = (double) 28.65645; - } - else - { - *LPeriod = (double) 64.0; - *FPeriod = (double) 20.0; - *Fsamp = (double) 35.46895; - } - break; - case (DEC_SECAM): - *LPeriod = (double) 64.0; - *FPeriod = (double) 20.0; - *Fsamp = (double) 35.46895; - break; - } - return; - -} /* GetStandardConstants ()...*/ - - -/**************************************************************************** - * RT_SetStandard (uint16_t wStandard) * - * Function: to set the input standard for the Rage Theatre video in * - * Inputs: uint16_t wStandard - input standard (NTSC, PAL, SECAM) * - * Outputs: NONE * - ****************************************************************************/ -_X_EXPORT void RT_SetStandard (TheatrePtr t, uint16_t wStandard) -{ - double dbFsamp=0, dbLPeriod=0, dbFPeriod=0; - uint16_t wFrameTotal = 0; - double dbSPPeriod = 4.70; - - xf86DrvMsg(t->VIP->pScrn->scrnIndex,X_INFO,"Rage Theatre setting standard 0x%04x\n", - wStandard); - t->wStandard = wStandard; - - /* Get the constants for the given standard. */ - GetStandardConstants (&dbLPeriod, &dbFPeriod, &dbFsamp, wStandard); - - wFrameTotal = (uint16_t) (((2.0 * dbFPeriod) * 1000 / dbLPeriod) + 0.5); - - /* Procedures before setting the standards: */ - WriteRT_fld (fld_VIN_CLK_SEL, RT_REF_CLK); - WriteRT_fld (fld_VINRST, RT_VINRST_RESET); - - RT_SetVINClock (t, wStandard); - - WriteRT_fld (fld_VINRST, RT_VINRST_ACTIVE); - WriteRT_fld (fld_VIN_CLK_SEL, RT_PLL_VIN_CLK); - - /* Program the new standards: */ - switch (wStandard & 0x00FF) - { - case (DEC_NTSC): /*NTSC GROUP - 480 lines */ - WriteRT_fld (fld_STANDARD_SEL, RT_NTSC); - WriteRT_fld (fld_SYNCTIP_REF0, RT_NTSCM_SYNCTIP_REF0); - WriteRT_fld (fld_SYNCTIP_REF1, RT_NTSCM_SYNCTIP_REF1); - WriteRT_fld (fld_CLAMP_REF, RT_NTSCM_CLAMP_REF); - WriteRT_fld (fld_AGC_PEAKWHITE, RT_NTSCM_PEAKWHITE); - WriteRT_fld (fld_VBI_PEAKWHITE, RT_NTSCM_VBI_PEAKWHITE); - WriteRT_fld (fld_WPA_THRESHOLD, RT_NTSCM_WPA_THRESHOLD); - WriteRT_fld (fld_WPA_TRIGGER_LO, RT_NTSCM_WPA_TRIGGER_LO); - WriteRT_fld (fld_WPA_TRIGGER_HIGH, RT_NTSCM_WPA_TRIGGER_HIGH); - WriteRT_fld (fld_LOCKOUT_START, RT_NTSCM_LP_LOCKOUT_START); - WriteRT_fld (fld_LOCKOUT_END, RT_NTSCM_LP_LOCKOUT_END); - WriteRT_fld (fld_CH_DTO_INC, RT_NTSCM_CH_DTO_INC); - WriteRT_fld (fld_PLL_SGAIN, RT_NTSCM_CH_PLL_SGAIN); - WriteRT_fld (fld_PLL_FGAIN, RT_NTSCM_CH_PLL_FGAIN); - - WriteRT_fld (fld_CH_HEIGHT, RT_NTSCM_CH_HEIGHT); - WriteRT_fld (fld_CH_KILL_LEVEL, RT_NTSCM_CH_KILL_LEVEL); - - WriteRT_fld (fld_CH_AGC_ERROR_LIM, RT_NTSCM_CH_AGC_ERROR_LIM); - WriteRT_fld (fld_CH_AGC_FILTER_EN, RT_NTSCM_CH_AGC_FILTER_EN); - WriteRT_fld (fld_CH_AGC_LOOP_SPEED,RT_NTSCM_CH_AGC_LOOP_SPEED); - - WriteRT_fld (fld_VS_FIELD_BLANK_START, RT_NTSCM_VS_FIELD_BLANK_START); - WriteRT_fld (fld_VS_FIELD_BLANK_END, RT_NTSCM_VS_FIELD_BLANK_END); - - WriteRT_fld (fld_H_ACTIVE_START, RT_NTSCM_H_ACTIVE_START); - WriteRT_fld (fld_H_ACTIVE_END, RT_NTSCM_H_ACTIVE_END); - - WriteRT_fld (fld_V_ACTIVE_START, RT_NTSCM_V_ACTIVE_START); - WriteRT_fld (fld_V_ACTIVE_END, RT_NTSCM_V_ACTIVE_END); - - WriteRT_fld (fld_H_VBI_WIND_START, RT_NTSCM_H_VBI_WIND_START); - WriteRT_fld (fld_H_VBI_WIND_END, RT_NTSCM_H_VBI_WIND_END); - - WriteRT_fld (fld_V_VBI_WIND_START, RT_NTSCM_V_VBI_WIND_START); - WriteRT_fld (fld_V_VBI_WIND_END, RT_NTSCM_V_VBI_WIND_END); - - WriteRT_fld (fld_UV_INT_START, (uint8_t)((0.10 * dbLPeriod * dbFsamp / 2.0) + 0.5 - 32)); - - WriteRT_fld (fld_VSYNC_INT_TRIGGER , (uint16_t) RT_NTSCM_VSYNC_INT_TRIGGER); - WriteRT_fld (fld_VSYNC_INT_HOLD, (uint16_t) RT_NTSCM_VSYNC_INT_HOLD); - - switch (wStandard & 0xFF00) - { - case (extPAL_M): - case (extNONE): - case (extNTSC): - WriteRT_fld (fld_CR_BURST_GAIN, RT_NTSCM_CR_BURST_GAIN); - WriteRT_fld (fld_CB_BURST_GAIN, RT_NTSCM_CB_BURST_GAIN); - - WriteRT_fld (fld_CRDR_ACTIVE_GAIN, RT_NTSCM_CRDR_ACTIVE_GAIN); - WriteRT_fld (fld_CBDB_ACTIVE_GAIN, RT_NTSCM_CBDB_ACTIVE_GAIN); - - WriteRT_fld (fld_VERT_LOCKOUT_START, RT_NTSCM_VERT_LOCKOUT_START); - WriteRT_fld (fld_VERT_LOCKOUT_END, RT_NTSCM_VERT_LOCKOUT_END); - - break; - case (extNTSC_J): - WriteRT_fld (fld_CR_BURST_GAIN, RT_NTSCJ_CR_BURST_GAIN); - WriteRT_fld (fld_CB_BURST_GAIN, RT_NTSCJ_CB_BURST_GAIN); - - WriteRT_fld (fld_CRDR_ACTIVE_GAIN, RT_NTSCJ_CRDR_ACTIVE_GAIN); - WriteRT_fld (fld_CBDB_ACTIVE_GAIN, RT_NTSCJ_CBDB_ACTIVE_GAIN); - - WriteRT_fld (fld_CH_HEIGHT, RT_NTSCJ_CH_HEIGHT); - WriteRT_fld (fld_CH_KILL_LEVEL, RT_NTSCJ_CH_KILL_LEVEL); - - WriteRT_fld (fld_CH_AGC_ERROR_LIM, RT_NTSCJ_CH_AGC_ERROR_LIM); - WriteRT_fld (fld_CH_AGC_FILTER_EN, RT_NTSCJ_CH_AGC_FILTER_EN); - WriteRT_fld (fld_CH_AGC_LOOP_SPEED, RT_NTSCJ_CH_AGC_LOOP_SPEED); - - WriteRT_fld (fld_VERT_LOCKOUT_START, RT_NTSCJ_VERT_LOCKOUT_START); - WriteRT_fld (fld_VERT_LOCKOUT_END, RT_NTSCJ_VERT_LOCKOUT_END); - - break; - default: - break; - } - break; - case (DEC_PAL): /*PAL GROUP - 525 lines */ - WriteRT_fld (fld_STANDARD_SEL, RT_PAL); - WriteRT_fld (fld_SYNCTIP_REF0, RT_PAL_SYNCTIP_REF0); - WriteRT_fld (fld_SYNCTIP_REF1, RT_PAL_SYNCTIP_REF1); - - WriteRT_fld (fld_CLAMP_REF, RT_PAL_CLAMP_REF); - WriteRT_fld (fld_AGC_PEAKWHITE, RT_PAL_PEAKWHITE); - WriteRT_fld (fld_VBI_PEAKWHITE, RT_PAL_VBI_PEAKWHITE); - - WriteRT_fld (fld_WPA_THRESHOLD, RT_PAL_WPA_THRESHOLD); - WriteRT_fld (fld_WPA_TRIGGER_LO, RT_PAL_WPA_TRIGGER_LO); - WriteRT_fld (fld_WPA_TRIGGER_HIGH, RT_PAL_WPA_TRIGGER_HIGH); - - WriteRT_fld (fld_LOCKOUT_START,RT_PAL_LP_LOCKOUT_START); - WriteRT_fld (fld_LOCKOUT_END, RT_PAL_LP_LOCKOUT_END); - WriteRT_fld (fld_CH_DTO_INC, RT_PAL_CH_DTO_INC); - WriteRT_fld (fld_PLL_SGAIN, RT_PAL_CH_PLL_SGAIN); - WriteRT_fld (fld_PLL_FGAIN, RT_PAL_CH_PLL_FGAIN); - - WriteRT_fld (fld_CR_BURST_GAIN, RT_PAL_CR_BURST_GAIN); - WriteRT_fld (fld_CB_BURST_GAIN, RT_PAL_CB_BURST_GAIN); - - WriteRT_fld (fld_CRDR_ACTIVE_GAIN, RT_PAL_CRDR_ACTIVE_GAIN); - WriteRT_fld (fld_CBDB_ACTIVE_GAIN, RT_PAL_CBDB_ACTIVE_GAIN); - - WriteRT_fld (fld_CH_HEIGHT, RT_PAL_CH_HEIGHT); - WriteRT_fld (fld_CH_KILL_LEVEL, RT_PAL_CH_KILL_LEVEL); - - WriteRT_fld (fld_CH_AGC_ERROR_LIM, RT_PAL_CH_AGC_ERROR_LIM); - WriteRT_fld (fld_CH_AGC_FILTER_EN, RT_PAL_CH_AGC_FILTER_EN); - WriteRT_fld (fld_CH_AGC_LOOP_SPEED,RT_PAL_CH_AGC_LOOP_SPEED); - - WriteRT_fld (fld_VERT_LOCKOUT_START, RT_PAL_VERT_LOCKOUT_START); - WriteRT_fld (fld_VERT_LOCKOUT_END, RT_PAL_VERT_LOCKOUT_END); - WriteRT_fld (fld_VS_FIELD_BLANK_START, (uint16_t)RT_PALSEM_VS_FIELD_BLANK_START); - - WriteRT_fld (fld_VS_FIELD_BLANK_END, RT_PAL_VS_FIELD_BLANK_END); - - WriteRT_fld (fld_H_ACTIVE_START, RT_PAL_H_ACTIVE_START); - WriteRT_fld (fld_H_ACTIVE_END, RT_PAL_H_ACTIVE_END); - - WriteRT_fld (fld_V_ACTIVE_START, RT_PAL_V_ACTIVE_START); - WriteRT_fld (fld_V_ACTIVE_END, RT_PAL_V_ACTIVE_END); - - WriteRT_fld (fld_H_VBI_WIND_START, RT_PAL_H_VBI_WIND_START); - WriteRT_fld (fld_H_VBI_WIND_END, RT_PAL_H_VBI_WIND_END); - - WriteRT_fld (fld_V_VBI_WIND_START, RT_PAL_V_VBI_WIND_START); - WriteRT_fld (fld_V_VBI_WIND_END, RT_PAL_V_VBI_WIND_END); - - /* Magic 0.10 is correct - according to Ivo. Also see SECAM code below */ -/* WriteRT_fld (fld_UV_INT_START, (uint8_t)( (0.12 * dbLPeriod * dbFsamp / 2.0) + 0.5 - 32 )); */ - WriteRT_fld (fld_UV_INT_START, (uint8_t)( (0.10 * dbLPeriod * dbFsamp / 2.0) + 0.5 - 32 )); - - WriteRT_fld (fld_VSYNC_INT_TRIGGER , (uint16_t) RT_PALSEM_VSYNC_INT_TRIGGER); - WriteRT_fld (fld_VSYNC_INT_HOLD, (uint16_t) RT_PALSEM_VSYNC_INT_HOLD); - - break; - case (DEC_SECAM): /*PAL GROUP*/ - WriteRT_fld (fld_STANDARD_SEL, RT_SECAM); - WriteRT_fld (fld_SYNCTIP_REF0, RT_SECAM_SYNCTIP_REF0); - WriteRT_fld (fld_SYNCTIP_REF1, RT_SECAM_SYNCTIP_REF1); - WriteRT_fld (fld_CLAMP_REF, RT_SECAM_CLAMP_REF); - WriteRT_fld (fld_AGC_PEAKWHITE, RT_SECAM_PEAKWHITE); - WriteRT_fld (fld_VBI_PEAKWHITE, RT_SECAM_VBI_PEAKWHITE); - - WriteRT_fld (fld_WPA_THRESHOLD, RT_SECAM_WPA_THRESHOLD); - - WriteRT_fld (fld_WPA_TRIGGER_LO, RT_SECAM_WPA_TRIGGER_LO); - WriteRT_fld (fld_WPA_TRIGGER_HIGH, RT_SECAM_WPA_TRIGGER_HIGH); - - WriteRT_fld (fld_LOCKOUT_START,RT_SECAM_LP_LOCKOUT_START); - WriteRT_fld (fld_LOCKOUT_END, RT_SECAM_LP_LOCKOUT_END); - - WriteRT_fld (fld_CH_DTO_INC, RT_SECAM_CH_DTO_INC); - WriteRT_fld (fld_PLL_SGAIN, RT_SECAM_CH_PLL_SGAIN); - WriteRT_fld (fld_PLL_FGAIN, RT_SECAM_CH_PLL_FGAIN); - - WriteRT_fld (fld_CR_BURST_GAIN, RT_SECAM_CR_BURST_GAIN); - WriteRT_fld (fld_CB_BURST_GAIN, RT_SECAM_CB_BURST_GAIN); - - WriteRT_fld (fld_CRDR_ACTIVE_GAIN, RT_SECAM_CRDR_ACTIVE_GAIN); - WriteRT_fld (fld_CBDB_ACTIVE_GAIN, RT_SECAM_CBDB_ACTIVE_GAIN); - - WriteRT_fld (fld_CH_HEIGHT, RT_SECAM_CH_HEIGHT); - WriteRT_fld (fld_CH_KILL_LEVEL, RT_SECAM_CH_KILL_LEVEL); - - WriteRT_fld (fld_CH_AGC_ERROR_LIM, RT_SECAM_CH_AGC_ERROR_LIM); - WriteRT_fld (fld_CH_AGC_FILTER_EN, RT_SECAM_CH_AGC_FILTER_EN); - WriteRT_fld (fld_CH_AGC_LOOP_SPEED,RT_SECAM_CH_AGC_LOOP_SPEED); - - WriteRT_fld (fld_VERT_LOCKOUT_START, RT_SECAM_VERT_LOCKOUT_START); /*Might not need */ - WriteRT_fld (fld_VERT_LOCKOUT_END, RT_SECAM_VERT_LOCKOUT_END); /* Might not need */ - - WriteRT_fld (fld_VS_FIELD_BLANK_START, (uint16_t)RT_PALSEM_VS_FIELD_BLANK_START); - WriteRT_fld (fld_VS_FIELD_BLANK_END, RT_PAL_VS_FIELD_BLANK_END); - - WriteRT_fld (fld_H_ACTIVE_START, RT_PAL_H_ACTIVE_START); - WriteRT_fld (fld_H_ACTIVE_END, RT_PAL_H_ACTIVE_END); - - WriteRT_fld (fld_V_ACTIVE_START, RT_PAL_V_ACTIVE_START); - WriteRT_fld (fld_V_ACTIVE_END, RT_PAL_V_ACTIVE_END); - - WriteRT_fld (fld_H_VBI_WIND_START, RT_PAL_H_VBI_WIND_START); - WriteRT_fld (fld_H_VBI_WIND_END, RT_PAL_H_VBI_WIND_END); - - WriteRT_fld (fld_V_VBI_WIND_START, RT_PAL_V_VBI_WIND_START); - WriteRT_fld (fld_V_VBI_WIND_END, RT_PAL_V_VBI_WIND_END); - - WriteRT_fld (fld_VSYNC_INT_TRIGGER , (uint16_t) RT_PALSEM_VSYNC_INT_TRIGGER); - WriteRT_fld (fld_VSYNC_INT_HOLD, (uint16_t) RT_PALSEM_VSYNC_INT_HOLD); - -/* WriteRT_fld (fld_UV_INT_START, (uint8_t)( (0.12 * dbLPeriod * dbFsamp / 2.0) + 0.5 - 32 )); */ - WriteRT_fld (fld_UV_INT_START, (uint8_t)( (0.10 * dbLPeriod * dbFsamp / 2.0) + 0.5 - 32 )); - - break; - default: - break; - } - - if (t->wConnector == DEC_SVIDEO) - { - - RT_SetCombFilter (t, wStandard, RT_SVIDEO); - } - else - { - /* Set up extra (connector and std) registers. */ - RT_SetCombFilter (t, wStandard, RT_COMPOSITE); - } - - /* Set the following values according to the formulas */ - WriteRT_fld (fld_HS_LINE_TOTAL, (uint16_t)((dbLPeriod * dbFsamp / 2.0) +0.5)); - /* According to Ivo PAL/SECAM needs different treatment */ - switch(wStandard & 0x00FF) - { - case DEC_PAL: - case DEC_SECAM: - WriteRT_fld (fld_MIN_PULSE_WIDTH, (uint8_t)(0.5 * dbSPPeriod * dbFsamp/2.0)); - WriteRT_fld (fld_MAX_PULSE_WIDTH, (uint8_t)(1.5 * dbSPPeriod * dbFsamp/2.0)); - WriteRT_fld (fld_WIN_OPEN_LIMIT, (uint16_t)(((dbLPeriod * dbFsamp / 4.0) + 0.5) - 16)); - WriteRT_fld (fld_WIN_CLOSE_LIMIT, (uint16_t)(2.39 * dbSPPeriod * dbFsamp / 2.0)); - /* WriteRT_fld (fld_VS_FIELD_IDLOCATION, (uint16_t)RT_PAL_FIELD_IDLOCATION); */ - /* According to docs the following value will work right, though the resulting stream deviates - slightly from CCIR..., in particular the value that was before will do nuts to VCRs in - pause/rewind state. */ - WriteRT_fld (fld_VS_FIELD_IDLOCATION, (uint16_t)0x01); - WriteRT_fld (fld_HS_PLL_SGAIN, 2); - break; - case DEC_NTSC: - WriteRT_fld (fld_MIN_PULSE_WIDTH, (uint8_t)(0.75 * dbSPPeriod * dbFsamp/2.0)); - WriteRT_fld (fld_MAX_PULSE_WIDTH, (uint8_t)(1.25 * dbSPPeriod * dbFsamp/2.0)); - WriteRT_fld (fld_WIN_OPEN_LIMIT, (uint16_t)(((dbLPeriod * dbFsamp / 4.0) + 0.5) - 16)); - WriteRT_fld (fld_WIN_CLOSE_LIMIT, (uint16_t)(1.15 * dbSPPeriod * dbFsamp / 2.0)); - /* WriteRT_fld (fld_VS_FIELD_IDLOCATION, (uint16_t)fld_VS_FIELD_IDLOCATION_def);*/ - /* I think the default value was the same as the one here.. does not hurt to hardcode it */ - WriteRT_fld (fld_VS_FIELD_IDLOCATION, (uint16_t)0x01); - - } - - WriteRT_fld (fld_VS_FRAME_TOTAL, (uint16_t)(wFrameTotal) + 10); - WriteRT_fld (fld_BLACK_INT_START, (uint8_t)((0.09 * dbLPeriod * dbFsamp / 2.0) - 32 )); - WriteRT_fld (fld_SYNC_TIP_START, (uint16_t)((dbLPeriod * dbFsamp / 2.0 + 0.5) - 28 )); - - return; - -} /* RT_SetStandard ()... */ - - - -/**************************************************************************** - * RT_SetCombFilter (uint16_t wStandard, uint16_t wConnector) * - * Function: sets the input comb filter based on the standard and * - * connector being used (composite vs. svideo) * - * Inputs: uint16_t wStandard - input standard (NTSC, PAL, SECAM) * - * uint16_t wConnector - COMPOSITE, SVIDEO * - * Outputs: NONE * - ****************************************************************************/ -static void RT_SetCombFilter (TheatrePtr t, uint16_t wStandard, uint16_t wConnector) -{ - uint32_t dwComb_Cntl0=0; - uint32_t dwComb_Cntl1=0; - uint32_t dwComb_Cntl2=0; - uint32_t dwComb_Line_Length=0; - - switch (wConnector) - { - case RT_COMPOSITE: - switch (wStandard & 0x00FF) - { - case (DEC_NTSC): - switch (wStandard & 0xFF00) - { - case (extNONE): - case (extNTSC): - case (extNTSC_J): - dwComb_Cntl0= RT_NTSCM_COMB_CNTL0_COMPOSITE; - dwComb_Cntl1= RT_NTSCM_COMB_CNTL1_COMPOSITE; - dwComb_Cntl2= RT_NTSCM_COMB_CNTL2_COMPOSITE; - dwComb_Line_Length= RT_NTSCM_COMB_LENGTH_COMPOSITE; - break; - case (extPAL_M): - dwComb_Cntl0= RT_PALM_COMB_CNTL0_COMPOSITE; - dwComb_Cntl1= RT_PALM_COMB_CNTL1_COMPOSITE; - dwComb_Cntl2= RT_PALM_COMB_CNTL2_COMPOSITE; - dwComb_Line_Length= RT_PALM_COMB_LENGTH_COMPOSITE; - break; - default: - return; - } - break; - case (DEC_PAL): - switch (wStandard & 0xFF00) - { - case (extNONE): - case (extPAL): - dwComb_Cntl0= RT_PAL_COMB_CNTL0_COMPOSITE; - dwComb_Cntl1= RT_PAL_COMB_CNTL1_COMPOSITE; - dwComb_Cntl2= RT_PAL_COMB_CNTL2_COMPOSITE; - dwComb_Line_Length= RT_PAL_COMB_LENGTH_COMPOSITE; - break; - case (extPAL_N): - dwComb_Cntl0= RT_PALN_COMB_CNTL0_COMPOSITE; - dwComb_Cntl1= RT_PALN_COMB_CNTL1_COMPOSITE; - dwComb_Cntl2= RT_PALN_COMB_CNTL2_COMPOSITE; - dwComb_Line_Length= RT_PALN_COMB_LENGTH_COMPOSITE; - break; - default: - return; - } - break; - case (DEC_SECAM): - dwComb_Cntl0= RT_SECAM_COMB_CNTL0_COMPOSITE; - dwComb_Cntl1= RT_SECAM_COMB_CNTL1_COMPOSITE; - dwComb_Cntl2= RT_SECAM_COMB_CNTL2_COMPOSITE; - dwComb_Line_Length= RT_SECAM_COMB_LENGTH_COMPOSITE; - break; - default: - return; - } - break; - case RT_SVIDEO: - switch (wStandard & 0x00FF) - { - case (DEC_NTSC): - switch (wStandard & 0xFF00) - { - case (extNONE): - case (extNTSC): - dwComb_Cntl0= RT_NTSCM_COMB_CNTL0_SVIDEO; - dwComb_Cntl1= RT_NTSCM_COMB_CNTL1_SVIDEO; - dwComb_Cntl2= RT_NTSCM_COMB_CNTL2_SVIDEO; - dwComb_Line_Length= RT_NTSCM_COMB_LENGTH_SVIDEO; - break; - case (extPAL_M): - dwComb_Cntl0= RT_PALM_COMB_CNTL0_SVIDEO; - dwComb_Cntl1= RT_PALM_COMB_CNTL1_SVIDEO; - dwComb_Cntl2= RT_PALM_COMB_CNTL2_SVIDEO; - dwComb_Line_Length= RT_PALM_COMB_LENGTH_SVIDEO; - break; - default: - return; - } - break; - case (DEC_PAL): - switch (wStandard & 0xFF00) - { - case (extNONE): - case (extPAL): - dwComb_Cntl0= RT_PAL_COMB_CNTL0_SVIDEO; - dwComb_Cntl1= RT_PAL_COMB_CNTL1_SVIDEO; - dwComb_Cntl2= RT_PAL_COMB_CNTL2_SVIDEO; - dwComb_Line_Length= RT_PAL_COMB_LENGTH_SVIDEO; - break; - case (extPAL_N): - dwComb_Cntl0= RT_PALN_COMB_CNTL0_SVIDEO; - dwComb_Cntl1= RT_PALN_COMB_CNTL1_SVIDEO; - dwComb_Cntl2= RT_PALN_COMB_CNTL2_SVIDEO; - dwComb_Line_Length= RT_PALN_COMB_LENGTH_SVIDEO; - break; - default: - return; - } - break; - case (DEC_SECAM): - dwComb_Cntl0= RT_SECAM_COMB_CNTL0_SVIDEO; - dwComb_Cntl1= RT_SECAM_COMB_CNTL1_SVIDEO; - dwComb_Cntl2= RT_SECAM_COMB_CNTL2_SVIDEO; - dwComb_Line_Length= RT_SECAM_COMB_LENGTH_SVIDEO; - break; - default: - return; - } - break; - default: - return; - } - - WriteRT_fld (fld_COMB_CNTL0, dwComb_Cntl0); - WriteRT_fld (fld_COMB_CNTL1, dwComb_Cntl1); - WriteRT_fld (fld_COMB_CNTL2, dwComb_Cntl2); - WriteRT_fld (fld_COMB_LENGTH, dwComb_Line_Length); - - return; - -} /* RT_SetCombFilter ()... */ - - -/**************************************************************************** - * RT_SetOutputVideoSize (uint16_t wHorzSize, uint16_t wVertSize, * - * uint8_t fCC_On, uint8_t fVBICap_On) * - * Function: sets the output video size for the Rage Theatre video in * - * Inputs: uint16_t wHorzSize - width of output in pixels * - * uint16_t wVertSize - height of output in pixels (lines) * - * uint8_t fCC_On - enable CC output * - * uint8_t fVBI_Cap_On - enable VBI capture * - * Outputs: NONE * - ****************************************************************************/ -_X_EXPORT void RT_SetOutputVideoSize (TheatrePtr t, uint16_t wHorzSize, uint16_t wVertSize, uint8_t fCC_On, uint8_t fVBICap_On) -{ - uint32_t dwHwinStart=0; - uint32_t dwHScaleRatio=0; - uint32_t dwHActiveLength=0; - uint32_t dwVwinStart=0; - uint32_t dwVScaleRatio=0; - uint32_t dwVActiveLength=0; - uint32_t dwTempRatio=0; - uint32_t dwEvenFieldOffset=0; - uint32_t dwOddFieldOffset=0; - uint32_t dwXin=0; - uint32_t dwYin=0; - - if (fVBICap_On) - { - WriteRT_fld (fld_VBI_CAPTURE_ENABLE, 1); - WriteRT_fld (fld_VBI_SCALING_RATIO, fld_VBI_SCALING_RATIO_def); - switch (t->wStandard & 0x00FF) - { - case (DEC_NTSC): - WriteRT_fld (fld_H_VBI_WIND_START, RT_NTSCM_H_VBI_WIND_START); - WriteRT_fld (fld_H_VBI_WIND_END, RT_NTSCM_H_VBI_WIND_END); - WriteRT_fld (fld_V_VBI_WIND_START, RT_NTSCM_V_VBI_WIND_START); - WriteRT_fld (fld_V_VBI_WIND_END, RT_NTSCM_V_VBI_WIND_END); - break; - case (DEC_PAL): - WriteRT_fld (fld_H_VBI_WIND_START, RT_PAL_H_VBI_WIND_START); - WriteRT_fld (fld_H_VBI_WIND_END, RT_PAL_H_VBI_WIND_END); - WriteRT_fld (fld_V_VBI_WIND_START, RT_PAL_V_VBI_WIND_START); - WriteRT_fld (fld_V_VBI_WIND_END, RT_PAL_V_VBI_WIND_END); - break; - case (DEC_SECAM): - WriteRT_fld (fld_H_VBI_WIND_START, RT_PAL_H_VBI_WIND_START); - WriteRT_fld (fld_H_VBI_WIND_END, RT_PAL_H_VBI_WIND_END); - WriteRT_fld (fld_V_VBI_WIND_START, RT_PAL_V_VBI_WIND_START); - WriteRT_fld (fld_V_VBI_WIND_END, RT_PAL_V_VBI_WIND_END); - break; - default: - break; - } - } - else - { - WriteRT_fld (fld_VBI_CAPTURE_ENABLE, 0); - } - - if (t->wInterlaced != RT_DECINTERLACED) - { - wVertSize *= 2; - } - - /*1. Calculate Horizontal Scaling ratio:*/ - switch (t->wStandard & 0x00FF) - { - case (DEC_NTSC): - dwHwinStart = RT_NTSCM_H_IN_START; - dwXin = (ReadRT_fld (fld_H_ACTIVE_END) - ReadRT_fld (fld_H_ACTIVE_START)); /*tempscaler*/ - dwXin = RT_NTSC_H_ACTIVE_SIZE; - dwHScaleRatio = (uint32_t) ((long) dwXin * 65536L / wHorzSize); - dwHScaleRatio = dwHScaleRatio & 0x001FFFFF; /*21 bit number;*/ - dwHActiveLength = wHorzSize; - break; - case (DEC_PAL): - dwHwinStart = RT_PAL_H_IN_START; - dwXin = RT_PAL_H_ACTIVE_SIZE; - dwHScaleRatio = (uint32_t) ((long) dwXin * 65536L / wHorzSize); - dwHScaleRatio = dwHScaleRatio & 0x001FFFFF; /*21 bit number;*/ - dwHActiveLength = wHorzSize; - break; - case (DEC_SECAM): - dwHwinStart = RT_SECAM_H_IN_START; - dwXin = RT_SECAM_H_ACTIVE_SIZE; - dwHScaleRatio = (uint32_t) ((long) dwXin * 65536L / wHorzSize); - dwHScaleRatio = dwHScaleRatio & 0x001FFFFF; /*21 bit number;*/ - dwHActiveLength = wHorzSize; - break; - default: - break; - } - - /*2. Calculate Vertical Scaling ratio:*/ - switch (t->wStandard & 0x00FF) - { - case (DEC_NTSC): - dwVwinStart = RT_NTSCM_V_IN_START; - /* dwYin = (ReadRT_fld (fld_V_ACTIVE_END) - ReadRT_fld (fld_V_ACTIVE_START)); */ /*tempscaler*/ - dwYin = RT_NTSCM_V_ACTIVE_SIZE; - dwTempRatio = (uint32_t)((long) wVertSize / dwYin); - dwVScaleRatio = (uint32_t)((long)wVertSize * 2048L / dwYin); - dwVScaleRatio = dwVScaleRatio & 0x00000FFF; - dwVActiveLength = wVertSize/2; - break; - case (DEC_PAL): - dwVwinStart = RT_PAL_V_IN_START; - dwYin = RT_PAL_V_ACTIVE_SIZE; - dwTempRatio = (uint32_t)(wVertSize/dwYin); - dwVScaleRatio = (uint32_t)((long)wVertSize * 2048L / dwYin); - dwVScaleRatio = dwVScaleRatio & 0x00000FFF; - dwVActiveLength = wVertSize/2; - break; - case (DEC_SECAM): - dwVwinStart = RT_SECAM_V_IN_START; - dwYin = RT_SECAM_V_ACTIVE_SIZE; - dwTempRatio = (uint32_t) (wVertSize / dwYin); - dwVScaleRatio = (uint32_t) ((long) wVertSize * 2048L / dwYin); - dwVScaleRatio = dwVScaleRatio & 0x00000FFF; - dwVActiveLength = wVertSize/2; - break; - default: - break; - } - - /*4. Set up offset based on if interlaced or not:*/ - if (t->wInterlaced == RT_DECINTERLACED) - { - dwEvenFieldOffset = (uint32_t) ((1.0 - ((double) wVertSize / (double) dwYin)) * 512.0); - dwOddFieldOffset = dwEvenFieldOffset; - WriteRT_fld (fld_V_DEINTERLACE_ON, 0x1); - } - else - { - dwEvenFieldOffset = (uint32_t)(dwTempRatio * 512.0); - dwOddFieldOffset = (uint32_t)(2048 - dwEvenFieldOffset); - WriteRT_fld (fld_V_DEINTERLACE_ON, 0x0); - } - - /* Set the registers:*/ - WriteRT_fld (fld_H_IN_WIND_START, dwHwinStart); - WriteRT_fld (fld_H_SCALE_RATIO, dwHScaleRatio); - WriteRT_fld (fld_H_OUT_WIND_WIDTH, dwHActiveLength); - - WriteRT_fld (fld_V_IN_WIND_START, dwVwinStart); - WriteRT_fld (fld_V_SCALE_RATIO, dwVScaleRatio); - WriteRT_fld (fld_V_OUT_WIND_WIDTH, dwVActiveLength); - - WriteRT_fld (fld_EVENF_OFFSET, dwEvenFieldOffset); - WriteRT_fld (fld_ODDF_OFFSET, dwOddFieldOffset); - - t->dwHorzScalingRatio = dwHScaleRatio; - t->dwVertScalingRatio = dwVScaleRatio; - - return; - -} /* RT_SetOutputVideoSize ()...*/ - - - -/**************************************************************************** - * CalculateCrCbGain (double *CrGain, double *CbGain, uint16_t wStandard) * - * Function: * - * Inputs: double *CrGain - - * double *CbGain - - * uint16_t wStandard - input standard (NTSC, PAL, SECAM) * - * Outputs: NONE * - ****************************************************************************/ -static void CalculateCrCbGain (TheatrePtr t, double *CrGain, double *CbGain, uint16_t wStandard) -{ - #define UVFLTGAIN 1.5 - #define FRMAX 280000.0 - #define FBMAX 230000.0 - - double dbSynctipRef0=0, dbFsamp=0, dbLPeriod=0, dbFPeriod=0; - - dbSynctipRef0 = ReadRT_fld (fld_SYNCTIP_REF0); - - GetStandardConstants (&dbLPeriod, &dbFPeriod, &dbFsamp, wStandard); - - *CrGain=0.0; - *CbGain=0.0; - - switch (wStandard & 0x00FF) - { - case (DEC_NTSC): /*NTSC GROUP - 480 lines*/ - switch (wStandard & 0xFF00) - { - case (extNONE): - case (extNTSC): - case (extPAL_M): - *CrGain = (double)(40.0 / (dbSynctipRef0)) * (100.0/92.5) * (1.0/0.877) * ((112.0/70.1)/UVFLTGAIN); - *CbGain = (double)(40.0 / (dbSynctipRef0)) * (100.0/92.5) * (1.0/0.492) * ((112.0/88.6)/UVFLTGAIN); - break; - case (extNTSC_J): - *CrGain = (double)(40.0 / (dbSynctipRef0)) * (100.0/100.0) * (1.0/0.877) * ((112.0/70.1)/UVFLTGAIN); - *CbGain = (double)(40.0 / (dbSynctipRef0)) * (100.0/100.0) * (1.0/0.492) * ((112.0/88.6)/UVFLTGAIN); - break; - default: - return; - } - break; - case (DEC_PAL): - *CrGain = (double)(43.0 / (dbSynctipRef0)) * (100.0/92.5) * (1.0/0.877) * ((112.0/70.1)/UVFLTGAIN); - *CbGain = (double)(43.0 / (dbSynctipRef0)) * (100.0/92.5) * (1.0/0.492) * ((112.0/88.6)/UVFLTGAIN); - break; - case (DEC_SECAM): - *CrGain = (double) 32.0 * 32768.0 / FRMAX / (33554432.0 / dbFsamp) * (1.597 / 1.902) / UVFLTGAIN; - *CbGain = (double) 32.0 * 32768.0 / FBMAX / (33554432.0 / dbFsamp) * (1.267 / 1.505) / UVFLTGAIN; - break; - } - - return; - -} /* CalculateCrCbGain ()...*/ - - -/**************************************************************************** - * RT_SetConnector (uint16_t wStandard, int tunerFlag) * - * Function: - * Inputs: uint16_t wStandard - input standard (NTSC, PAL, SECAM) * - * int tunerFlag - * Outputs: NONE * - ****************************************************************************/ -void RT_SetConnector (TheatrePtr t, uint16_t wConnector, int tunerFlag) -{ - uint32_t dwTempContrast=0; - int i; - long counter; - - t->wConnector = wConnector; - - /* Get the contrast value - make sure we are viewing a visible line*/ - counter=0; - #if 0 - while (!((ReadRT_fld (fld_VS_LINE_COUNT)> 1) && (ReadRT_fld (fld_VS_LINE_COUNT)<20)) && (counter < 100000)){ - #endif - while ((ReadRT_fld (fld_VS_LINE_COUNT)<20) && (counter < 10000)){ - counter++; - } - dwTempContrast = ReadRT_fld (fld_LP_CONTRAST); - if(counter>=10000)xf86DrvMsg(t->VIP->pScrn->scrnIndex, X_INFO, - "Rage Theatre: timeout waiting for line count (%u)\n", - (unsigned)ReadRT_fld (fld_VS_LINE_COUNT)); - - - WriteRT_fld (fld_LP_CONTRAST, 0x0); - - switch (wConnector) - { - case (DEC_TUNER): /* Tuner*/ - WriteRT_fld (fld_INPUT_SELECT, t->wTunerConnector ); - WriteRT_fld (fld_STANDARD_YC, RT_COMPOSITE); - RT_SetCombFilter (t, t->wStandard, RT_COMPOSITE); - break; - case (DEC_COMPOSITE): /* Comp*/ - WriteRT_fld (fld_INPUT_SELECT, t->wComp0Connector); - WriteRT_fld (fld_STANDARD_YC, RT_COMPOSITE); - RT_SetCombFilter (t, t->wStandard, RT_COMPOSITE); - break; - case (DEC_SVIDEO): /* Svideo*/ - WriteRT_fld (fld_INPUT_SELECT, t->wSVideo0Connector); - WriteRT_fld (fld_STANDARD_YC, RT_SVIDEO); - RT_SetCombFilter (t, t->wStandard, RT_SVIDEO); - break; - default: - WriteRT_fld (fld_INPUT_SELECT, t->wComp0Connector); - WriteRT_fld (fld_STANDARD_YC, RT_COMPOSITE); - RT_SetCombFilter (t, t->wStandard, RT_COMPOSITE); - break; - } - - t->wConnector = wConnector; - - WriteRT_fld (fld_COMB_CNTL1, ReadRT_fld (fld_COMB_CNTL1) ^ 0x100); - WriteRT_fld (fld_COMB_CNTL1, ReadRT_fld (fld_COMB_CNTL1) ^ 0x100); - - /* wait at most 1 sec here - VIP bus has a bandwidth of 27MB and it is 8bit. - A single Rage Theatre read should take at least 6 bytes (2 for address one way and 4 for data the other way) - However there are also latencies associated with such reads, plus latencies for PCI accesses. - - I guess we should not be doing more than 100000 per second.. At some point - I should really write a program to time this. - */ - i = 100000; - - while ((i>=0) && (! ReadRT_fld (fld_HS_GENLOCKED))) - { - i--; - } - if(i<0) xf86DrvMsg(t->VIP->pScrn->scrnIndex, X_INFO, "Rage Theatre: waiting for fld_HS_GENLOCKED failed\n"); - /* now we are waiting for a non-visible line.. and there is absolutely no point to wait too long */ - counter = 0; - while (!((ReadRT_fld (fld_VS_LINE_COUNT)> 1) && (ReadRT_fld (fld_VS_LINE_COUNT)<20)) && (counter < 10000)){ - counter++; - } - WriteRT_fld (fld_LP_CONTRAST, dwTempContrast); - if(counter>=10000)xf86DrvMsg(t->VIP->pScrn->scrnIndex, X_INFO, - "Rage Theatre: timeout waiting for line count (%u)\n", - (unsigned)ReadRT_fld (fld_VS_LINE_COUNT)); - - - - return; - -} /* RT_SetConnector ()...*/ - - -_X_EXPORT void InitTheatre(TheatrePtr t) -{ - uint32_t data; - - - /* 0 reset Rage Theatre */ - ShutdownTheatre(t); - usleep(100000); - - t->mode=MODE_INITIALIZATION_IN_PROGRESS; - /* 1. - Set the VIN_PLL to NTSC value */ - RT_SetVINClock(t, RT_NTSC); - - /* Take VINRST and L54RST out of reset */ - RT_regr (VIP_PLL_CNTL1, &data); - RT_regw (VIP_PLL_CNTL1, data & ~((RT_VINRST_RESET << 1) | (RT_L54RST_RESET << 3))); - RT_regr (VIP_PLL_CNTL1, &data); - - /* Set VIN_CLK_SEL to PLL_VIN_CLK */ - RT_regr (VIP_CLOCK_SEL_CNTL, &data); - RT_regw (VIP_CLOCK_SEL_CNTL, data | (RT_PLL_VIN_CLK << 7)); - RT_regr (VIP_CLOCK_SEL_CNTL, &data); - - /* 2. - Set HW_DEBUG to 0xF000 before setting the standards registers */ - RT_regw (VIP_HW_DEBUG, 0x0000F000); - - /* wait for things to settle */ - usleep(100000); - - RT_SetStandard(t, t->wStandard); - - /* 3. - Set DVS port to OUTPUT */ - RT_regr (VIP_DVS_PORT_CTRL, &data); - RT_regw (VIP_DVS_PORT_CTRL, data | RT_DVSDIR_OUT); - RT_regr (VIP_DVS_PORT_CTRL, &data); - - /* 4. - Set default values for ADC_CNTL */ - RT_regw (VIP_ADC_CNTL, RT_ADC_CNTL_DEFAULT); - - /* 5. - Clear the VIN_ASYNC_RST bit */ - RT_regr (VIP_MASTER_CNTL, &data); - RT_regw (VIP_MASTER_CNTL, data & ~0x20); - RT_regr (VIP_MASTER_CNTL, &data); - - /* Clear the DVS_ASYNC_RST bit */ - RT_regr (VIP_MASTER_CNTL, &data); - RT_regw (VIP_MASTER_CNTL, data & ~(RT_DVS_ASYNC_RST)); - RT_regr (VIP_MASTER_CNTL, &data); - - /* Set the GENLOCK delay */ - RT_regw (VIP_HS_GENLOCKDELAY, 0x10); - - RT_regr (fld_DVS_DIRECTION, &data); - RT_regw (fld_DVS_DIRECTION, data & RT_DVSDIR_OUT); -/* WriteRT_fld (fld_DVS_DIRECTION, RT_DVSDIR_IN); */ - - t->mode=MODE_INITIALIZED_FOR_TV_IN; -} - - -_X_EXPORT void ShutdownTheatre(TheatrePtr t) -{ - WriteRT_fld (fld_VIN_ASYNC_RST, RT_ASYNC_DISABLE); - WriteRT_fld (fld_VINRST , RT_VINRST_RESET); - WriteRT_fld (fld_ADC_PDWN , RT_ADC_DISABLE); - WriteRT_fld (fld_DVS_DIRECTION, RT_DVSDIR_IN); - t->mode=MODE_UNINITIALIZED; -} - -_X_EXPORT void DumpRageTheatreRegs(TheatrePtr t) -{ - int i; - uint32_t data; - - for(i=0;i<0x900;i+=4) - { - RT_regr(i, &data); - xf86DrvMsg(t->VIP->pScrn->scrnIndex, X_INFO, - "register 0x%04x is equal to 0x%08x\n", i, (unsigned)data); - } - -} - -void DumpRageTheatreRegsByName(TheatrePtr t) -{ - int i; - uint32_t data; - struct { char *name; long addr; } rt_reg_list[]={ - { "ADC_CNTL ", 0x0400 }, - { "ADC_DEBUG ", 0x0404 }, - { "AUD_CLK_DIVIDERS ", 0x00e8 }, - { "AUD_DTO_INCREMENTS ", 0x00ec }, - { "AUD_PLL_CNTL ", 0x00e0 }, - { "AUD_PLL_FINE_CNTL ", 0x00e4 }, - { "CLKOUT_CNTL ", 0x004c }, - { "CLKOUT_GPIO_CNTL ", 0x0038 }, - { "CLOCK_SEL_CNTL ", 0x00d0 }, - { "COMB_CNTL0 ", 0x0440 }, - { "COMB_CNTL1 ", 0x0444 }, - { "COMB_CNTL2 ", 0x0448 }, - { "COMB_LINE_LENGTH ", 0x044c }, - { "CP_ACTIVE_GAIN ", 0x0594 }, - { "CP_AGC_CNTL ", 0x0590 }, - { "CP_BURST_GAIN ", 0x058c }, - { "CP_DEBUG_FORCE ", 0x05b8 }, - { "CP_HUE_CNTL ", 0x0588 }, - { "CP_PLL_CNTL0 ", 0x0580 }, - { "CP_PLL_CNTL1 ", 0x0584 }, - { "CP_PLL_STATUS0 ", 0x0598 }, - { "CP_PLL_STATUS1 ", 0x059c }, - { "CP_PLL_STATUS2 ", 0x05a0 }, - { "CP_PLL_STATUS3 ", 0x05a4 }, - { "CP_PLL_STATUS4 ", 0x05a8 }, - { "CP_PLL_STATUS5 ", 0x05ac }, - { "CP_PLL_STATUS6 ", 0x05b0 }, - { "CP_PLL_STATUS7 ", 0x05b4 }, - { "CP_VERT_LOCKOUT ", 0x05bc }, - { "CRC_CNTL ", 0x02c0 }, - { "CRT_DTO_INCREMENTS ", 0x0394 }, - { "CRT_PLL_CNTL ", 0x00c4 }, - { "CRT_PLL_FINE_CNTL ", 0x00bc }, - { "DECODER_DEBUG_CNTL ", 0x05d4 }, - { "DELAY_ONE_MAP_A ", 0x0114 }, - { "DELAY_ONE_MAP_B ", 0x0118 }, - { "DELAY_ZERO_MAP_A ", 0x011c }, - { "DELAY_ZERO_MAP_B ", 0x0120 }, - { "DFCOUNT ", 0x00a4 }, - { "DFRESTART ", 0x00a8 }, - { "DHRESTART ", 0x00ac }, - { "DVRESTART ", 0x00b0 }, - { "DVS_PORT_CTRL ", 0x0610 }, - { "DVS_PORT_READBACK ", 0x0614 }, - { "FIFOA_CONFIG ", 0x0800 }, - { "FIFOB_CONFIG ", 0x0804 }, - { "FIFOC_CONFIG ", 0x0808 }, - { "FRAME_LOCK_CNTL ", 0x0100 }, - { "GAIN_LIMIT_SETTINGS ", 0x01e4 }, - { "GPIO_CNTL ", 0x0034 }, - { "GPIO_INOUT ", 0x0030 }, - { "HCOUNT ", 0x0090 }, - { "HDISP ", 0x0084 }, - { "HOST_RD_WT_CNTL ", 0x0188 }, - { "HOST_READ_DATA ", 0x0180 }, - { "HOST_WRITE_DATA ", 0x0184 }, - { "HSIZE ", 0x0088 }, - { "HSTART ", 0x008c }, - { "HS_DTOINC ", 0x0484 }, - { "HS_GENLOCKDELAY ", 0x0490 }, - { "HS_MINMAXWIDTH ", 0x048c }, - { "HS_PLINE ", 0x0480 }, - { "HS_PLLGAIN ", 0x0488 }, - { "HS_PLL_ERROR ", 0x04a0 }, - { "HS_PLL_FS_PATH ", 0x04a4 }, - { "HS_PULSE_WIDTH ", 0x049c }, - { "HS_WINDOW_LIMIT ", 0x0494 }, - { "HS_WINDOW_OC_SPEED ", 0x0498 }, - { "HTOTAL ", 0x0080 }, - { "HW_DEBUG ", 0x0010 }, - { "H_ACTIVE_WINDOW ", 0x05c0 }, - { "H_SCALER_CONTROL ", 0x0600 }, - { "H_VBI_WINDOW ", 0x05c8 }, - { "I2C_CNTL ", 0x0054 }, - { "I2C_CNTL_0 ", 0x0020 }, - { "I2C_CNTL_1 ", 0x0024 }, - { "I2C_DATA ", 0x0028 }, - { "I2S_RECEIVE_CNTL ", 0x081c }, - { "I2S_TRANSMIT_CNTL ", 0x0818 }, - { "IIS_TX_CNT_REG ", 0x0824 }, - { "INT_CNTL ", 0x002c }, - { "L54_DTO_INCREMENTS ", 0x00f8 }, - { "L54_PLL_CNTL ", 0x00f0 }, - { "L54_PLL_FINE_CNTL ", 0x00f4 }, - { "LINEAR_GAIN_SETTINGS ", 0x01e8 }, - { "LP_AGC_CLAMP_CNTL0 ", 0x0500 }, - { "LP_AGC_CLAMP_CNTL1 ", 0x0504 }, - { "LP_BLACK_LEVEL ", 0x051c }, - { "LP_BRIGHTNESS ", 0x0508 }, - { "LP_CONTRAST ", 0x050c }, - { "LP_SLICE_LEVEL ", 0x0520 }, - { "LP_SLICE_LIMIT ", 0x0510 }, - { "LP_SYNCTIP_LEVEL ", 0x0524 }, - { "LP_VERT_LOCKOUT ", 0x0528 }, - { "LP_WPA_CNTL0 ", 0x0514 }, - { "LP_WPA_CNTL1 ", 0x0518 }, - { "MASTER_CNTL ", 0x0040 }, - { "MODULATOR_CNTL1 ", 0x0200 }, - { "MODULATOR_CNTL2 ", 0x0204 }, - { "MV_LEVEL_CNTL1 ", 0x0210 }, - { "MV_LEVEL_CNTL2 ", 0x0214 }, - { "MV_MODE_CNTL ", 0x0208 }, - { "MV_STATUS ", 0x0330 }, - { "MV_STRIPE_CNTL ", 0x020c }, - { "NOISE_CNTL0 ", 0x0450 }, - { "PLL_CNTL0 ", 0x00c8 }, - { "PLL_CNTL1 ", 0x00fc }, - { "PLL_TEST_CNTL ", 0x00cc }, - { "PRE_DAC_MUX_CNTL ", 0x0240 }, - { "RGB_CNTL ", 0x0048 }, - { "RIPINTF_PORT_CNTL ", 0x003c }, - { "SCALER_IN_WINDOW ", 0x0618 }, - { "SCALER_OUT_WINDOW ", 0x061c }, - { "SG_BLACK_GATE ", 0x04c0 }, - { "SG_SYNCTIP_GATE ", 0x04c4 }, - { "SG_UVGATE_GATE ", 0x04c8 }, - { "SINGLE_STEP_DATA ", 0x05d8 }, - { "SPDIF_AC3_PREAMBLE ", 0x0814 }, - { "SPDIF_CHANNEL_STAT ", 0x0810 }, - { "SPDIF_PORT_CNTL ", 0x080c }, - { "SPDIF_TX_CNT_REG ", 0x0820 }, - { "STANDARD_SELECT ", 0x0408 }, - { "SW_SCRATCH ", 0x0014 }, - { "SYNC_CNTL ", 0x0050 }, - { "SYNC_LOCK_CNTL ", 0x0104 }, - { "SYNC_SIZE ", 0x00b4 }, - { "THERMO2BIN_STATUS ", 0x040c }, - { "TIMING_CNTL ", 0x01c4 }, - { "TVO_DATA_DELAY_A ", 0x0140 }, - { "TVO_DATA_DELAY_B ", 0x0144 }, - { "TVO_SYNC_PAT_ACCUM ", 0x0108 }, - { "TVO_SYNC_PAT_EXPECT ", 0x0110 }, - { "TVO_SYNC_THRESHOLD ", 0x010c }, - { "TV_DAC_CNTL ", 0x0280 }, - { "TV_DTO_INCREMENTS ", 0x0390 }, - { "TV_PLL_CNTL ", 0x00c0 }, - { "TV_PLL_FINE_CNTL ", 0x00b8 }, - { "UPSAMP_AND_GAIN_CNTL ", 0x01e0 }, - { "UPSAMP_COEFF0_0 ", 0x0340 }, - { "UPSAMP_COEFF0_1 ", 0x0344 }, - { "UPSAMP_COEFF0_2 ", 0x0348 }, - { "UPSAMP_COEFF1_0 ", 0x034c }, - { "UPSAMP_COEFF1_1 ", 0x0350 }, - { "UPSAMP_COEFF1_2 ", 0x0354 }, - { "UPSAMP_COEFF2_0 ", 0x0358 }, - { "UPSAMP_COEFF2_1 ", 0x035c }, - { "UPSAMP_COEFF2_2 ", 0x0360 }, - { "UPSAMP_COEFF3_0 ", 0x0364 }, - { "UPSAMP_COEFF3_1 ", 0x0368 }, - { "UPSAMP_COEFF3_2 ", 0x036c }, - { "UPSAMP_COEFF4_0 ", 0x0370 }, - { "UPSAMP_COEFF4_1 ", 0x0374 }, - { "UPSAMP_COEFF4_2 ", 0x0378 }, - { "UV_ADR ", 0x0300 }, - { "VBI_20BIT_CNTL ", 0x02d0 }, - { "VBI_CC_CNTL ", 0x02c8 }, - { "VBI_CONTROL ", 0x05d0 }, - { "VBI_DTO_CNTL ", 0x02d4 }, - { "VBI_EDS_CNTL ", 0x02cc }, - { "VBI_LEVEL_CNTL ", 0x02d8 }, - { "VBI_SCALER_CONTROL ", 0x060c }, - { "VCOUNT ", 0x009c }, - { "VDISP ", 0x0098 }, - { "VFTOTAL ", 0x00a0 }, - { "VIDEO_PORT_SIG ", 0x02c4 }, - { "VIN_PLL_CNTL ", 0x00d4 }, - { "VIN_PLL_FINE_CNTL ", 0x00d8 }, - { "VIP_COMMAND_STATUS ", 0x0008 }, - { "VIP_REVISION_ID ", 0x000c }, - { "VIP_SUB_VENDOR_DEVICE_ID", 0x0004 }, - { "VIP_VENDOR_DEVICE_ID ", 0x0000 }, - { "VSCALER_CNTL1 ", 0x01c0 }, - { "VSCALER_CNTL2 ", 0x01c8 }, - { "VSYNC_DIFF_CNTL ", 0x03a0 }, - { "VSYNC_DIFF_LIMITS ", 0x03a4 }, - { "VSYNC_DIFF_RD_DATA ", 0x03a8 }, - { "VS_BLANKING_CNTL ", 0x0544 }, - { "VS_COUNTER_CNTL ", 0x054c }, - { "VS_DETECTOR_CNTL ", 0x0540 }, - { "VS_FIELD_ID_CNTL ", 0x0548 }, - { "VS_FRAME_TOTAL ", 0x0550 }, - { "VS_LINE_COUNT ", 0x0554 }, - { "VTOTAL ", 0x0094 }, - { "V_ACTIVE_WINDOW ", 0x05c4 }, - { "V_DEINTERLACE_CONTROL ", 0x0608 }, - { "V_SCALER_CONTROL ", 0x0604 }, - { "V_VBI_WINDOW ", 0x05cc }, - { "Y_FALL_CNTL ", 0x01cc }, - { "Y_RISE_CNTL ", 0x01d0 }, - { "Y_SAW_TOOTH_CNTL ", 0x01d4 }, - {NULL, 0} - }; - - for(i=0; rt_reg_list[i].name!=NULL;i++){ - RT_regr(rt_reg_list[i].addr, &data); - xf86DrvMsg(t->VIP->pScrn->scrnIndex, X_INFO, - "register (0x%04lx) %s is equal to 0x%08x\n", - rt_reg_list[i].addr, rt_reg_list[i].name, (unsigned)data); - } - -} - -_X_EXPORT void ResetTheatreRegsForNoTVout(TheatrePtr t) -{ - RT_regw(VIP_CLKOUT_CNTL, 0x0); - RT_regw(VIP_HCOUNT, 0x0); - RT_regw(VIP_VCOUNT, 0x0); - RT_regw(VIP_DFCOUNT, 0x0); - #if 0 - RT_regw(VIP_CLOCK_SEL_CNTL, 0x2b7); /* versus 0x237 <-> 0x2b7 */ - RT_regw(VIP_VIN_PLL_CNTL, 0x60a6039); - #endif - RT_regw(VIP_FRAME_LOCK_CNTL, 0x0); -} - - -_X_EXPORT void ResetTheatreRegsForTVout(TheatrePtr t) -{ -/* RT_regw(VIP_HW_DEBUG, 0x200); */ -/* RT_regw(VIP_INT_CNTL, 0x0); - RT_regw(VIP_GPIO_INOUT, 0x10090000); - RT_regw(VIP_GPIO_INOUT, 0x340b0000); */ -/* RT_regw(VIP_MASTER_CNTL, 0x6e8); */ - RT_regw(VIP_CLKOUT_CNTL, 0x29); -#if 1 - RT_regw(VIP_HCOUNT, 0x1d1); - RT_regw(VIP_VCOUNT, 0x1e3); -#else - RT_regw(VIP_HCOUNT, 0x322); - RT_regw(VIP_VCOUNT, 0x151); -#endif - RT_regw(VIP_DFCOUNT, 0x01); -/* RT_regw(VIP_CLOCK_SEL_CNTL, 0xb7); versus 0x237 <-> 0x2b7 */ - RT_regw(VIP_CLOCK_SEL_CNTL, 0x2b7); /* versus 0x237 <-> 0x2b7 */ - RT_regw(VIP_VIN_PLL_CNTL, 0x60a6039); -/* RT_regw(VIP_PLL_CNTL1, 0xacacac74); */ - RT_regw(VIP_FRAME_LOCK_CNTL, 0x0f); -/* RT_regw(VIP_ADC_CNTL, 0x02a420a8); - RT_regw(VIP_COMB_CNTL_0, 0x0d438083); - RT_regw(VIP_COMB_CNTL_2, 0x06080102); - RT_regw(VIP_HS_MINMAXWIDTH, 0x462f); - ... - */ -/* - RT_regw(VIP_HS_PULSE_WIDTH, 0x359); - RT_regw(VIP_HS_PLL_ERROR, 0xab6); - RT_regw(VIP_HS_PLL_FS_PATH, 0x7fff08f8); - RT_regw(VIP_VS_LINE_COUNT, 0x49b5e005); - */ -} diff --git a/src/theatre.h b/src/theatre.h deleted file mode 100644 index c70a0e02..00000000 --- a/src/theatre.h +++ /dev/null @@ -1,71 +0,0 @@ -#ifndef __THEATRE_H__ -#define __THEATRE_H__ - -#define MODE_UNINITIALIZED 1 -#define MODE_INITIALIZATION_IN_PROGRESS 2 -#define MODE_INITIALIZED_FOR_TV_IN 3 - -typedef struct { - GENERIC_BUS_Ptr VIP; - - int theatre_num; - uint32_t theatre_id; - int mode; - char* microc_path; - char* microc_type; - - uint16_t video_decoder_type; - uint32_t wStandard; - uint32_t wConnector; - int iHue; - int iSaturation; - uint32_t wSaturation_U; - uint32_t wSaturation_V; - int iBrightness; - int dbBrightnessRatio; - uint32_t wSharpness; - int iContrast; - int dbContrast; - uint32_t wInterlaced; - uint32_t wTunerConnector; - uint32_t wComp0Connector; - uint32_t wSVideo0Connector; - uint32_t dwHorzScalingRatio; - uint32_t dwVertScalingRatio; - - } TheatreRec, * TheatrePtr; - - -/* DO NOT FORGET to setup constants before calling InitTheatre */ -#define xf86_InitTheatre InitTheatre -_X_EXPORT void InitTheatre(TheatrePtr t); -#define xf86_RT_SetTint RT_SetTint -_X_EXPORT void RT_SetTint (TheatrePtr t, int hue); -#define xf86_RT_SetSaturation RT_SetSaturation -_X_EXPORT void RT_SetSaturation (TheatrePtr t, int Saturation); -#define xf86_RT_SetBrightness RT_SetBrightness -_X_EXPORT void RT_SetBrightness (TheatrePtr t, int Brightness); -#define xf86_RT_SetSharpness RT_SetSharpness -_X_EXPORT void RT_SetSharpness (TheatrePtr t, uint16_t wSharpness); -#define xf86_RT_SetContrast RT_SetContrast -_X_EXPORT void RT_SetContrast (TheatrePtr t, int Contrast); -#define xf86_RT_SetInterlace RT_SetInterlace -_X_EXPORT void RT_SetInterlace (TheatrePtr t, uint8_t bInterlace); -#define xf86_RT_SetStandard RT_SetStandard -_X_EXPORT void RT_SetStandard (TheatrePtr t, uint16_t wStandard); -#define xf86_RT_SetOutputVideoSize RT_SetOutputVideoSize -_X_EXPORT void RT_SetOutputVideoSize (TheatrePtr t, uint16_t wHorzSize, uint16_t wVertSize, uint8_t fCC_On, uint8_t fVBICap_On); -#define xf86_RT_SetConnector RT_SetConnector -_X_EXPORT void RT_SetConnector (TheatrePtr t, uint16_t wConnector, int tunerFlag); -#define xf86_ResetTheatreRegsForNoTVout ResetTheatreRegsForNoTVout -_X_EXPORT void ResetTheatreRegsForNoTVout(TheatrePtr t); -#define xf86_ResetTheatreRegsForTVout ResetTheatreRegsForTVout -_X_EXPORT void ResetTheatreRegsForTVout(TheatrePtr t); -#define xf86_DumpRageTheatreRegs DumpRageTheatreRegs -_X_EXPORT void DumpRageTheatreRegs(TheatrePtr t); -#define xf86_DumpRageTheatreRegsByName DumpRageTheatreRegsByName -_X_EXPORT void DumpRageTheatreRegsByName(TheatrePtr t); -#define xf86_ShutdownTheatre ShutdownTheatre -_X_EXPORT void ShutdownTheatre(TheatrePtr t); - -#endif diff --git a/src/theatre200.c b/src/theatre200.c deleted file mode 100644 index 9de9299c..00000000 --- a/src/theatre200.c +++ /dev/null @@ -1,2275 +0,0 @@ -/************************************************************************************* - * - * Copyright (C) 2005 Bogdan D. bogdand@users.sourceforge.net - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this - * software and associated documentation files (the "Software"), to deal in the Software - * without restriction, including without limitation the rights to use, copy, modify, - * merge, publish, distribute, sublicense, and/or sell copies of the Software, - * and to permit persons to whom the Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, - * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE - * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of the author shall not be used in advertising or - * otherwise to promote the sale, use or other dealings in this Software without prior written - * authorization from the author. - * - * $Log$ - * Revision 1.6 2006/03/22 22:30:14 krh - * 2006-03-22 Kristian Høgsberg <krh@redhat.com> - * - * * src/theatre200.c: Convert use of xf86fopen() and other xf86 - * wrapped libc symbols to use libc symbols directly. The xf86* - * versions aren't supposed to be used directly. - * - * * src/ *.c: Drop libc wrapper; don't include xf86_ansic.h and add - * includes now missing. - * - * Revision 1.4 2005/08/28 18:00:23 bogdand - * Modified the licens type from GPL to a X/MIT one - * - * Revision 1.3 2005/07/11 02:29:45 ajax - * Prep for modular builds by adding guarded #include "config.h" everywhere. - * - * Revision 1.2 2005/07/01 22:43:11 daniels - * Change all misc.h and os.h references to <X11/foo.h>. - * - * - ************************************************************************************/ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include <stdio.h> -#include <string.h> - -#include "xf86.h" -#include "generic_bus.h" -#include "radeon_reg.h" -#include "radeon.h" -#include "theatre_reg.h" -#include "theatre200.h" -#include "radeon_macros.h" - -#undef read -#undef write -#undef ioctl - -void DumpRageTheatreRegsByName(TheatrePtr t); - -static int DownloadMicrocode(TheatrePtr t); -static int microc_load (char* micro_path, char* micro_type, struct rt200_microc_data* microc_datap, int screen); -static void microc_clean(struct rt200_microc_data* microc_datap, int screen); -static int dsp_init(TheatrePtr t, struct rt200_microc_data* microc_datap); -static int dsp_load(TheatrePtr t, struct rt200_microc_data* microc_datap); - -static uint32_t dsp_send_command(TheatrePtr t, uint32_t fb_scratch1, uint32_t fb_scratch0); -static uint32_t dsp_set_video_input_connector(TheatrePtr t, uint32_t connector); -//static uint32_t dsp_reset(TheatrePtr t); -static uint32_t dsp_set_lowpowerstate(TheatrePtr t, uint32_t pstate); -static uint32_t dsp_set_video_standard(TheatrePtr t, uint32_t standard); -static uint32_t dsp_set_videostreamformat(TheatrePtr t, uint32_t format); -static uint32_t dsp_video_standard_detection(TheatrePtr t); -//static uint32_t dsp_get_signallockstatus(TheatrePtr t); -//static uint32_t dsp_get_signallinenumber(TheatrePtr t); - -static uint32_t dsp_set_brightness(TheatrePtr t, uint8_t brightness); -static uint32_t dsp_set_contrast(TheatrePtr t, uint8_t contrast); -//static uint32_t dsp_set_sharpness(TheatrePtr t, int sharpness); -static uint32_t dsp_set_tint(TheatrePtr t, uint8_t tint); -static uint32_t dsp_set_saturation(TheatrePtr t, uint8_t saturation); -static uint32_t dsp_set_video_scaler_horizontal(TheatrePtr t, uint16_t output_width, uint16_t horz_start, uint16_t horz_end); -static uint32_t dsp_set_video_scaler_vertical(TheatrePtr t, uint16_t output_height, uint16_t vert_start, uint16_t vert_end); -static uint32_t dsp_audio_mute(TheatrePtr t, uint8_t left, uint8_t right); -static uint32_t dsp_set_audio_volume(TheatrePtr t, uint8_t left, uint8_t right, uint8_t auto_mute); -//static uint32_t dsp_audio_detection(TheatrePtr t, uint8_t option); -static uint32_t dsp_configure_i2s_port(TheatrePtr t, uint8_t tx_mode, uint8_t rx_mode, uint8_t clk_mode); -static uint32_t dsp_configure_spdif_port(TheatrePtr t, uint8_t state); - -static Bool theatre_read(TheatrePtr t,uint32_t reg, uint32_t *data) -{ - if(t->theatre_num<0)return FALSE; - return t->VIP->read(t->VIP, ((t->theatre_num & 0x3)<<14) | reg,4, (uint8_t *) data); -} - -static Bool theatre_write(TheatrePtr t,uint32_t reg, uint32_t data) -{ - if(t->theatre_num<0)return FALSE; - return t->VIP->write(t->VIP,((t->theatre_num & 0x03)<<14) | reg,4, (uint8_t *) &data); -} - -static Bool theatre_fifo_read(TheatrePtr t,uint32_t fifo, uint8_t *data) -{ - if(t->theatre_num<0)return FALSE; - return t->VIP->fifo_read(t->VIP, ((t->theatre_num & 0x3)<<14) | fifo,1, (uint8_t *) data); -} - -static Bool theatre_fifo_write(TheatrePtr t,uint32_t fifo, uint32_t count, uint8_t* buffer) -{ - if(t->theatre_num<0)return FALSE; - return t->VIP->fifo_write(t->VIP,((t->theatre_num & 0x03)<<14) | fifo,count, (uint8_t *)buffer); -} - -#define RT_regr(reg,data) theatre_read(t,(reg),(data)) -#define RT_regw(reg,data) theatre_write(t,(reg),(data)) -#define RT_fifor(fifo,data) theatre_fifo_read(t,(fifo),(data)) -#define RT_fifow(fifo,count,data) theatre_fifo_write(t,(fifo),(count),(data)) -#define VIP_TYPE "ATI VIP BUS" - -static int microc_load (char* micro_path, char* micro_type, struct rt200_microc_data* microc_datap, int screen) -{ - FILE* file; - struct rt200_microc_head* microc_headp = µc_datap->microc_head; - struct rt200_microc_seg* seg_list = NULL; - struct rt200_microc_seg* curr_seg = NULL; - struct rt200_microc_seg* prev_seg = NULL; - int i; - - if (micro_path == NULL) - return -1; - - if (micro_type == NULL) - return -1; - - file = fopen(micro_path, "r"); - if (file == NULL) { - ERROR_0("Cannot open microcode file\n"); - return -1; - } - - if (!strcmp(micro_type, "BINARY")) - { - if (fread(microc_headp, sizeof(struct rt200_microc_head), 1, file) != 1) - { - ERROR("Cannot read header from file: %s\n", micro_path); - goto fail_exit; - } - - DEBUG("Microcode: num_seg: %x\n", microc_headp->num_seg); - - if (microc_headp->num_seg == 0) - goto fail_exit; - - for (i = 0; i < microc_headp->num_seg; i++) - { - int ret; - - curr_seg = (struct rt200_microc_seg*)malloc(sizeof(struct rt200_microc_seg)); - if (curr_seg == NULL) - { - ERROR_0("Cannot allocate memory\n"); - goto fail_exit; - } - - ret = fread(&curr_seg->num_bytes, 4, 1, file); - ret += fread(&curr_seg->download_dst, 4, 1, file); - ret += fread(&curr_seg->crc_val, 4, 1, file); - if (ret != 3) - { - ERROR("Cannot read segment from microcode file: %s\n", micro_path); - goto fail_exit; - } - - curr_seg->data = (unsigned char*)malloc(curr_seg->num_bytes); - if (curr_seg->data == NULL) - { - ERROR_0("cannot allocate memory\n"); - goto fail_exit; - } - - DEBUG("Microcode: segment number: %x\n", i); - DEBUG("Microcode: curr_seg->num_bytes: %x\n", curr_seg->num_bytes); - DEBUG("Microcode: curr_seg->download_dst: %x\n", curr_seg->download_dst); - DEBUG("Microcode: curr_seg->crc_val: %x\n", curr_seg->crc_val); - - if (seg_list) - { - prev_seg->next = curr_seg; - curr_seg->next = NULL; - prev_seg = curr_seg; - } - else - seg_list = prev_seg = curr_seg; - - } - - curr_seg = seg_list; - while (curr_seg) - { - if (fread(curr_seg->data, curr_seg->num_bytes, 1, file) != 1) - { - ERROR_0("Cannot read segment data\n"); - goto fail_exit; - } - - curr_seg = curr_seg->next; - } - } - else if (!strcmp(micro_type, "ASCII")) - { - char tmp1[12], tmp2[12], tmp3[12], tmp4[12]; - unsigned int ltmp; - - if ((fgets(tmp1, 12, file) != NULL) && - (fgets(tmp2, 12, file) != NULL) && - (fgets(tmp3, 12, file) != NULL) && - fgets(tmp4, 12, file) != NULL) - { - microc_headp->device_id = strtoul(tmp1, NULL, 16); - microc_headp->vendor_id = strtoul(tmp2, NULL, 16); - microc_headp->revision_id = strtoul(tmp3, NULL, 16); - microc_headp->num_seg = strtoul(tmp4, NULL, 16); - } - else - { - ERROR("Cannot read header from file: %s\n", micro_path); - goto fail_exit; - } - - DEBUG("Microcode: num_seg: %x\n", microc_headp->num_seg); - - if (microc_headp->num_seg == 0) - goto fail_exit; - - for (i = 0; i < microc_headp->num_seg; i++) - { - curr_seg = (struct rt200_microc_seg*)malloc(sizeof(struct rt200_microc_seg)); - if (curr_seg == NULL) - { - ERROR_0("Cannot allocate memory\n"); - goto fail_exit; - } - - if (fgets(tmp1, 12, file) != NULL && - fgets(tmp2, 12, file) != NULL && - fgets(tmp3, 12, file) != NULL) - { - curr_seg->num_bytes = strtoul(tmp1, NULL, 16); - curr_seg->download_dst = strtoul(tmp2, NULL, 16); - curr_seg->crc_val = strtoul(tmp3, NULL, 16); - } - else - { - ERROR("Cannot read segment from microcode file: %s\n", micro_path); - goto fail_exit; - } - - curr_seg->data = (unsigned char*)malloc(curr_seg->num_bytes); - if (curr_seg->data == NULL) - { - ERROR_0("cannot allocate memory\n"); - goto fail_exit; - } - - DEBUG("Microcode: segment number: %x\n", i); - DEBUG("Microcode: curr_seg->num_bytes: %x\n", curr_seg->num_bytes); - DEBUG("Microcode: curr_seg->download_dst: %x\n", curr_seg->download_dst); - DEBUG("Microcode: curr_seg->crc_val: %x\n", curr_seg->crc_val); - - if (seg_list) - { - curr_seg->next = NULL; - prev_seg->next = curr_seg; - prev_seg = curr_seg; - } - else - seg_list = prev_seg = curr_seg; - } - - curr_seg = seg_list; - while (curr_seg) - { - for ( i = 0; i < curr_seg->num_bytes; i+=4) - { - - if (fgets(tmp1, 12, file) == NULL) - { - ERROR_0("Cannot read from file\n"); - goto fail_exit; - } - ltmp = strtoul(tmp1, NULL, 16); - - *(unsigned int*)(curr_seg->data + i) = ltmp; - } - - curr_seg = curr_seg->next; - } - - } - else - { - ERROR("File type %s unknown\n", micro_type); - } - - microc_datap->microc_seg_list = seg_list; - - fclose(file); - return 0; - -fail_exit: - curr_seg = seg_list; - while(curr_seg) - { - free(curr_seg->data); - prev_seg = curr_seg; - curr_seg = curr_seg->next; - free(prev_seg); - } - fclose(file); - - return -1; -} - -static void microc_clean(struct rt200_microc_data* microc_datap, int screen) -{ - struct rt200_microc_seg* seg_list = microc_datap->microc_seg_list; - struct rt200_microc_seg* prev_seg; - - while(seg_list) - { - free(seg_list->data); - prev_seg = seg_list; - seg_list = seg_list->next; - free(prev_seg); - } -} - -static int dsp_init(TheatrePtr t, struct rt200_microc_data* microc_datap) -{ - uint32_t data; - int i = 0; - int screen = t->VIP->pScrn->scrnIndex; - - /* Map FIFOD to DSP Port I/O port */ - RT_regr(VIP_HOSTINTF_PORT_CNTL, &data); - RT_regw(VIP_HOSTINTF_PORT_CNTL, data & (~VIP_HOSTINTF_PORT_CNTL__FIFO_RW_MODE)); - - /* The default endianess is LE. It matches the ost one for x86 */ - RT_regr(VIP_HOSTINTF_PORT_CNTL, &data); - RT_regw(VIP_HOSTINTF_PORT_CNTL, data & (~VIP_HOSTINTF_PORT_CNTL__FIFOD_ENDIAN_SWAP)); - - /* Wait until Shuttle bus channel 14 is available */ - RT_regr(VIP_TC_STATUS, &data); - while(((data & VIP_TC_STATUS__TC_CHAN_BUSY) & 0x00004000) && (i++ < 10000)) - RT_regr(VIP_TC_STATUS, &data); - - DEBUG_0("Microcode: dsp_init: channel 14 available\n"); - - return 0; -} - -static int dsp_load(TheatrePtr t, struct rt200_microc_data* microc_datap) -{ - struct rt200_microc_seg* seg_list = microc_datap->microc_seg_list; - uint8_t data8; - uint32_t data, fb_scratch0, fb_scratch1; - uint32_t i; - uint32_t tries = 0; - uint32_t result = 0; - uint32_t seg_id = 0; - int screen = t->VIP->pScrn->scrnIndex; - - DEBUG("Microcode: before everything: %x\n", data8); - - if (RT_fifor(0x000, &data8)) - DEBUG("Microcode: FIFO status0: %x\n", data8); - else - { - ERROR_0("Microcode: error reading FIFO status0\n"); - return -1; - } - - - if (RT_fifor(0x100, &data8)) - DEBUG("Microcode: FIFO status1: %x\n", data8); - else - { - ERROR_0("Microcode: error reading FIFO status1\n"); - return -1; - } - - /* - * Download the Boot Code and CRC Checking Code (first segment) - */ - seg_id = 1; - while(result != DSP_OK && tries < 10) - { - /* Put DSP in reset before download (0x02) */ - RT_regr(VIP_TC_DOWNLOAD, &data); - RT_regw(VIP_TC_DOWNLOAD, (data & ~VIP_TC_DOWNLOAD__TC_RESET_MODE) | (0x02 << 17)); - - /* - * Configure shuttle bus for tranfer between DSP I/O "Program Interface" - * and Program Memory at address 0 - */ - - RT_regw(VIP_TC_SOURCE, 0x90000000); - RT_regw(VIP_TC_DESTINATION, 0x00000000); - RT_regw(VIP_TC_COMMAND, 0xe0000044 | ((seg_list->num_bytes - 1) << 7)); - - /* Load first segment */ - DEBUG_0("Microcode: Loading first segment\n"); - - if (!RT_fifow(0x700, seg_list->num_bytes, seg_list->data)) - { - ERROR_0("Microcode: write to FIFOD failed\n"); - return -1; - } - - /* Wait until Shuttle bus channel 14 is available */ - i = data = 0; - RT_regr(VIP_TC_STATUS, &data); - while(((data & VIP_TC_STATUS__TC_CHAN_BUSY) & 0x00004000) && (i++ < 10000)) - RT_regr(VIP_TC_STATUS, &data); - - if (i >= 10000) - { - ERROR_0("Microcode: channel 14 timeout\n"); - return -1; - } - - DEBUG_0("Microcode: dsp_load: checkpoint 1\n"); - DEBUG("Microcode: TC_STATUS: %x\n", data); - - /* transfer the code from program memory to data memory */ - RT_regw(VIP_TC_SOURCE, 0x00000000); - RT_regw(VIP_TC_DESTINATION, 0x10000000); - RT_regw(VIP_TC_COMMAND, 0xe0000006 | ((seg_list->num_bytes - 1) << 7)); - - /* Wait until Shuttle bus channel 14 is available */ - i = data = 0; - RT_regr(VIP_TC_STATUS, &data); - while(((data & VIP_TC_STATUS__TC_CHAN_BUSY) & 0x00004000) && (i++ < 10000)) - RT_regr(VIP_TC_STATUS, &data); - - if (i >= 10000) - { - ERROR_0("Microcode: channel 14 timeout\n"); - return -1; - } - DEBUG_0("Microcode: dsp_load: checkpoint 2\n"); - DEBUG("Microcode: TC_STATUS: %x\n", data); - - /* Take DSP out from reset (0x0) */ - data = 0; - RT_regr(VIP_TC_DOWNLOAD, &data); - RT_regw(VIP_TC_DOWNLOAD, data & ~VIP_TC_DOWNLOAD__TC_RESET_MODE); - - RT_regr(VIP_TC_STATUS, &data); - DEBUG_0("Microcode: dsp_load: checkpoint 3\n"); - DEBUG("Microcode: TC_STATUS: %x\n", data); - - /* send dsp_download_check_CRC */ - fb_scratch0 = ((seg_list->num_bytes << 16) & 0xffff0000) | ((seg_id << 8) & 0xff00) | (0xff & 193); - fb_scratch1 = (unsigned int)seg_list->crc_val; - - result = dsp_send_command(t, fb_scratch1, fb_scratch0); - - DEBUG_0("Microcode: dsp_load: checkpoint 4\n"); - } - - if (tries >= 10) - { - ERROR_0("Microcode: Download of boot degment failed\n"); - return -1; - } - - DEBUG_0("Microcode: Download of boot code succeeded\n"); - - while((seg_list = seg_list->next) != NULL) - { - seg_id++; - result = tries = 0; - while(result != DSP_OK && tries < 10) - { - /* - * Configure shuttle bus for tranfer between DSP I/O "Program Interface" - * and Data Memory at address 0 - */ - - RT_regw(VIP_TC_SOURCE, 0x90000000); - RT_regw(VIP_TC_DESTINATION, 0x10000000); - RT_regw(VIP_TC_COMMAND, 0xe0000044 | ((seg_list->num_bytes - 1) << 7)); - - if (!RT_fifow(0x700, seg_list->num_bytes, seg_list->data)) - { - ERROR_0("Microcode: write to FIFOD failed\n"); - return -1; - } - - i = data = 0; - RT_regr(VIP_TC_STATUS, &data); - while(((data & VIP_TC_STATUS__TC_CHAN_BUSY) & 0x00004000) && (i++ < 10000)) - RT_regr(VIP_TC_STATUS, &data); - - /* send dsp_download_check_CRC */ - fb_scratch0 = ((seg_list->num_bytes << 16) & 0xffff0000) | ((seg_id << 8) & 0xff00) | (0xff & 193); - fb_scratch1 = (unsigned int)seg_list->crc_val; - - result = dsp_send_command(t, fb_scratch1, fb_scratch0); - } - - if (i >=10) - { - ERROR("Microcode: DSP failed to move seg: %x from data to code memory\n", seg_id); - return -1; - } - - DEBUG("Microcode: segment: %x loaded\n", seg_id); - - /* - * The segment is downloaded correctly to data memory. Now move it to code memory - * by using dsp_download_code_transfer command. - */ - - fb_scratch0 = ((seg_list->num_bytes << 16) & 0xffff0000) | ((seg_id << 8) & 0xff00) | (0xff & 194); - fb_scratch1 = (unsigned int)seg_list->download_dst; - - result = dsp_send_command(t, fb_scratch1, fb_scratch0); - - if (result != DSP_OK) - { - ERROR("Microcode: DSP failed to move seg: %x from data to code memory\n", seg_id); - return -1; - } - } - - DEBUG_0("Microcode: download complete\n"); - - /* - * The last step is sending dsp_download_check_CRC with "download complete" - */ - - fb_scratch0 = ((165 << 8) & 0xff00) | (0xff & 193); - fb_scratch1 = (unsigned int)0x11111; - - result = dsp_send_command(t, fb_scratch1, fb_scratch0); - - if (result == DSP_OK) - DEBUG_0("Microcode: DSP microcode successfully loaded\n"); - else - { - ERROR_0("Microcode: DSP microcode UNsuccessfully loaded\n"); - return -1; - } - - return 0; -} - -static uint32_t dsp_send_command(TheatrePtr t, uint32_t fb_scratch1, uint32_t fb_scratch0) -{ - uint32_t data; - int i; - - /* - * Clear the FB_INT0 bit in INT_CNTL - */ - RT_regr(VIP_INT_CNTL, &data); - RT_regw(VIP_INT_CNTL, data | VIP_INT_CNTL__FB_INT0_CLR); - - /* - * Write FB_SCRATCHx registers. If FB_SCRATCH1==0 then we have a DWORD command. - */ - RT_regw(VIP_FB_SCRATCH0, fb_scratch0); - if (fb_scratch1 != 0) - RT_regw(VIP_FB_SCRATCH1, fb_scratch1); - - /* - * Attention DSP. We are talking to you. - */ - RT_regr(VIP_FB_INT, &data); - RT_regw(VIP_FB_INT, data | VIP_FB_INT__INT_7); - - /* - * Wait (by polling) for the DSP to process the command. - */ - i = 0; - RT_regr(VIP_INT_CNTL, &data); - while((!(data & VIP_INT_CNTL__FB_INT0)) /*&& (i++ < 10000)*/) - RT_regr(VIP_INT_CNTL, &data); - - /* - * The return code is in FB_SCRATCH0 - */ - RT_regr(VIP_FB_SCRATCH0, &fb_scratch0); - - /* - * If we are here it means we got an answer. Clear the FB_INT0 bit. - */ - RT_regr(VIP_INT_CNTL, &data); - RT_regw(VIP_INT_CNTL, data | VIP_INT_CNTL__FB_INT0_CLR); - - - return fb_scratch0; -} - -static uint32_t dsp_set_video_input_connector(TheatrePtr t, uint32_t connector) -{ - uint32_t fb_scratch0 = 0; - uint32_t result; - int screen = t->VIP->pScrn->scrnIndex; - - fb_scratch0 = ((connector << 8) & 0xff00) | (55 & 0xff); - - result = dsp_send_command(t, 0, fb_scratch0); - - DEBUG_2("dsp_set_video_input_connector: %x, result: %x\n", connector, result); - - return result; -} - -#if 0 -static uint32_t dsp_reset(TheatrePtr t) -{ - uint32_t fb_scratch0 = 0; - uint32_t result; - int screen = t->VIP->pScrn->scrnIndex; - - fb_scratch0 = ((2 << 8) & 0xff00) | (8 & 0xff); - - result = dsp_send_command(t, 0, fb_scratch0); - - DEBUG("dsp_reset: %x\n", result); - - return result; -} -#endif - -static uint32_t dsp_set_lowpowerstate(TheatrePtr t, uint32_t pstate) -{ - uint32_t fb_scratch0 = 0; - uint32_t result; - int screen = t->VIP->pScrn->scrnIndex; - - fb_scratch0 = ((pstate << 8) & 0xff00) | (82 & 0xff); - - result = dsp_send_command(t, 0, fb_scratch0); - - DEBUG("dsp_set_lowpowerstate: %x\n", result); - - return result; -} -static uint32_t dsp_set_video_standard(TheatrePtr t, uint32_t standard) -{ - uint32_t fb_scratch0 = 0; - uint32_t result; - int screen = t->VIP->pScrn->scrnIndex; - - fb_scratch0 = ((standard << 8) & 0xff00) | (52 & 0xff); - - result = dsp_send_command(t, 0, fb_scratch0); - - DEBUG("dsp_set_video_standard: %x\n", result); - - return result; -} - -static uint32_t dsp_set_videostreamformat(TheatrePtr t, uint32_t format) -{ - uint32_t fb_scratch0 = 0; - uint32_t result; - int screen = t->VIP->pScrn->scrnIndex; - - fb_scratch0 = ((format << 8) & 0xff00) | (65 & 0xff); - - result = dsp_send_command(t, 0, fb_scratch0); - - DEBUG("dsp_set_videostreamformat: %x\n", result); - - return result; -} - -static uint32_t dsp_video_standard_detection(TheatrePtr t) -{ - uint32_t fb_scratch0 = 0; - uint32_t result; - int screen = t->VIP->pScrn->scrnIndex; - - fb_scratch0 = 0 | (54 & 0xff); - - result = dsp_send_command(t, 0, fb_scratch0); - - DEBUG("dsp_video_standard_detection: %x\n", result); - - return result; -} - -#if 0 -static uint32_t dsp_get_signallockstatus(TheatrePtr t) -{ - uint32_t fb_scratch1 = 0; - uint32_t fb_scratch0 = 0; - uint32_t result; - int screen = t->VIP->pScrn->scrnIndex; - - fb_scratch0 = 0 | (77 & 0xff); - - result = dsp_send_command(t, fb_scratch1, fb_scratch0); - - DEBUG_3("dsp_get_signallockstatus: %x, h_pll: %x, v_pll: %x\n", \ - result, (result >> 8) & 0xff, (result >> 16) & 0xff); - - return result; -} - -static uint32_t dsp_get_signallinenumber(TheatrePtr t) -{ - uint32_t fb_scratch1 = 0; - uint32_t fb_scratch0 = 0; - uint32_t result; - int screen = t->VIP->pScrn->scrnIndex; - - fb_scratch0 = 0 | (78 & 0xff); - - result = dsp_send_command(t, fb_scratch1, fb_scratch0); - - DEBUG_2("dsp_get_signallinenumber: %x, linenum: %x\n", \ - result, (result >> 8) & 0xffff); - - return result; -} -#endif - -static uint32_t dsp_set_brightness(TheatrePtr t, uint8_t brightness) -{ - uint32_t fb_scratch1 = 0; - uint32_t fb_scratch0 = 0; - uint32_t result; - int screen = t->VIP->pScrn->scrnIndex; - - fb_scratch0 = ((brightness << 8) & 0xff00) | (67 & 0xff); - - result = dsp_send_command(t, fb_scratch1, fb_scratch0); - - DEBUG("dsp_set_brightness: %x\n", result); - - return result; -} - -static uint32_t dsp_set_contrast(TheatrePtr t, uint8_t contrast) -{ - uint32_t fb_scratch1 = 0; - uint32_t fb_scratch0 = 0; - uint32_t result; - int screen = t->VIP->pScrn->scrnIndex; - - fb_scratch0 = ((contrast << 8) & 0xff00) | (71 & 0xff); - - result = dsp_send_command(t, fb_scratch1, fb_scratch0); - - DEBUG("dsp_set_contrast: %x\n", result); - - return result; -} - -#if 0 -static uint32_t dsp_set_sharpness(TheatrePtr t, int sharpness) -{ - uint32_t fb_scratch1 = 0; - uint32_t fb_scratch0 = 0; - uint32_t result; - int screen = t->VIP->pScrn->scrnIndex; - - fb_scratch0 = 0 | (73 & 0xff); - - result = dsp_send_command(t, fb_scratch1, fb_scratch0); - - DEBUG("dsp_set_sharpness: %x\n", result); - - return result; -} -#endif - -static uint32_t dsp_set_tint(TheatrePtr t, uint8_t tint) -{ - uint32_t fb_scratch1 = 0; - uint32_t fb_scratch0 = 0; - uint32_t result; - int screen = t->VIP->pScrn->scrnIndex; - - fb_scratch0 = ((tint << 8) & 0xff00) | (75 & 0xff); - - result = dsp_send_command(t, fb_scratch1, fb_scratch0); - - DEBUG("dsp_set_tint: %x\n", result); - - return result; -} - -static uint32_t dsp_set_saturation(TheatrePtr t, uint8_t saturation) -{ - uint32_t fb_scratch1 = 0; - uint32_t fb_scratch0 = 0; - uint32_t result; - int screen = t->VIP->pScrn->scrnIndex; - - fb_scratch0 = ((saturation << 8) & 0xff00) | (69 & 0xff); - - result = dsp_send_command(t, fb_scratch1, fb_scratch0); - - DEBUG("dsp_set_saturation: %x\n", result); - - return result; -} - -static uint32_t dsp_set_video_scaler_horizontal(TheatrePtr t, uint16_t output_width, uint16_t horz_start, uint16_t horz_end) -{ - uint32_t fb_scratch1 = 0; - uint32_t fb_scratch0 = 0; - uint32_t result; - int screen = t->VIP->pScrn->scrnIndex; - - fb_scratch0 = ((output_width << 8) & 0x00ffff00) | (195 & 0xff); - fb_scratch1 = ((horz_end << 16) & 0xffff0000) | (horz_start & 0xffff); - - result = dsp_send_command(t, fb_scratch1, fb_scratch0); - - DEBUG("dsp_set_video_scaler_horizontal: %x\n", result); - - return result; -} - -static uint32_t dsp_set_video_scaler_vertical(TheatrePtr t, uint16_t output_height, uint16_t vert_start, uint16_t vert_end) -{ - uint32_t fb_scratch1 = 0; - uint32_t fb_scratch0 = 0; - uint32_t result; - int screen = t->VIP->pScrn->scrnIndex; - - fb_scratch0 = ((output_height << 8) & 0x00ffff00) | (196 & 0xff); - fb_scratch1 = ((vert_end << 16) & 0xffff0000) | (vert_start & 0xffff); - - result = dsp_send_command(t, fb_scratch1, fb_scratch0); - - DEBUG("dsp_set_video_scaler_vertical: %x\n", result); - - return result; -} - -static uint32_t dsp_audio_mute(TheatrePtr t, uint8_t left, uint8_t right) -{ - uint32_t fb_scratch1 = 0; - uint32_t fb_scratch0 = 0; - uint32_t result; - int screen = t->VIP->pScrn->scrnIndex; - - fb_scratch0 = ((right << 16) & 0xff0000) | ((left << 8) & 0xff00) | (21 & 0xff); - - result = dsp_send_command(t, fb_scratch1, fb_scratch0); - - DEBUG("dsp_audio_mute: %x\n", result); - - return result; -} - -static uint32_t dsp_set_audio_volume(TheatrePtr t, uint8_t left, uint8_t right, uint8_t auto_mute) -{ - uint32_t fb_scratch1 = 0; - uint32_t fb_scratch0 = 0; - uint32_t result; - int screen = t->VIP->pScrn->scrnIndex; - - fb_scratch0 = ((auto_mute << 24) & 0xff000000) | ((right << 16) & 0xff0000) | ((left << 8) & 0xff00) | (22 & 0xff); - - result = dsp_send_command(t, fb_scratch1, fb_scratch0); - - DEBUG("dsp_set_audio_volume: %x\n", result); - - return result; -} - -#if 0 -static uint32_t dsp_audio_detection(TheatrePtr t, uint8_t option) -{ - uint32_t fb_scratch1 = 0; - uint32_t fb_scratch0 = 0; - uint32_t result; - int screen = t->VIP->pScrn->scrnIndex; - - fb_scratch0 = ((option << 8) & 0xff00) | (16 & 0xff); - - result = dsp_send_command(t, fb_scratch1, fb_scratch0); - - DEBUG("dsp_audio_detection: %x\n", result); - - return result; -} -#endif - -static uint32_t dsp_configure_i2s_port(TheatrePtr t, uint8_t tx_mode, uint8_t rx_mode, uint8_t clk_mode) -{ - uint32_t fb_scratch1 = 0; - uint32_t fb_scratch0 = 0; - uint32_t result; - int screen = t->VIP->pScrn->scrnIndex; - - fb_scratch0 = ((clk_mode << 24) & 0xff000000) | ((rx_mode << 16) & 0xff0000) | ((tx_mode << 8) & 0xff00) | (40 & 0xff); - - result = dsp_send_command(t, fb_scratch1, fb_scratch0); - - DEBUG("dsp_configure_i2s_port: %x\n", result); - - return result; -} - -static uint32_t dsp_configure_spdif_port(TheatrePtr t, uint8_t state) -{ - uint32_t fb_scratch1 = 0; - uint32_t fb_scratch0 = 0; - uint32_t result; - int screen = t->VIP->pScrn->scrnIndex; - - fb_scratch0 = ((state << 8) & 0xff00) | (41 & 0xff); - - result = dsp_send_command(t, fb_scratch1, fb_scratch0); - - DEBUG("dsp_configure_spdif_port: %x\n", result); - - return result; -} - -enum -{ -fld_tmpReg1=0, -fld_tmpReg2, -fld_tmpReg3, -fld_LP_CONTRAST, -fld_LP_BRIGHTNESS, -fld_CP_HUE_CNTL, -fld_LUMA_FILTER, -fld_H_SCALE_RATIO, -fld_H_SHARPNESS, -fld_V_SCALE_RATIO, -fld_V_DEINTERLACE_ON, -fld_V_BYPSS, -fld_V_DITHER_ON, -fld_EVENF_OFFSET, -fld_ODDF_OFFSET, -fld_INTERLACE_DETECTED, -fld_VS_LINE_COUNT, -fld_VS_DETECTED_LINES, -fld_VS_ITU656_VB, -fld_VBI_CC_DATA, -fld_VBI_CC_WT, -fld_VBI_CC_WT_ACK, -fld_VBI_CC_HOLD, -fld_VBI_DECODE_EN, -fld_VBI_CC_DTO_P, -fld_VBI_20BIT_DTO_P, -fld_VBI_CC_LEVEL, -fld_VBI_20BIT_LEVEL, -fld_VBI_CLK_RUNIN_GAIN, -fld_H_VBI_WIND_START, -fld_H_VBI_WIND_END, -fld_V_VBI_WIND_START, -fld_V_VBI_WIND_END, -fld_VBI_20BIT_DATA0, -fld_VBI_20BIT_DATA1, -fld_VBI_20BIT_WT, -fld_VBI_20BIT_WT_ACK, -fld_VBI_20BIT_HOLD, -fld_VBI_CAPTURE_ENABLE, -fld_VBI_EDS_DATA, -fld_VBI_EDS_WT, -fld_VBI_EDS_WT_ACK, -fld_VBI_EDS_HOLD, -fld_VBI_SCALING_RATIO, -fld_VBI_ALIGNER_ENABLE, -fld_H_ACTIVE_START, -fld_H_ACTIVE_END, -fld_V_ACTIVE_START, -fld_V_ACTIVE_END, -fld_CH_HEIGHT, -fld_CH_KILL_LEVEL, -fld_CH_AGC_ERROR_LIM, -fld_CH_AGC_FILTER_EN, -fld_CH_AGC_LOOP_SPEED, -fld_HUE_ADJ, -fld_STANDARD_SEL, -fld_STANDARD_YC, -fld_ADC_PDWN, -fld_INPUT_SELECT, -fld_ADC_PREFLO, -fld_H_SYNC_PULSE_WIDTH, -fld_HS_GENLOCKED, -fld_HS_SYNC_IN_WIN, -fld_VIN_ASYNC_RST, -fld_DVS_ASYNC_RST, -fld_VIP_VENDOR_ID, -fld_VIP_DEVICE_ID, -fld_VIP_REVISION_ID, -fld_BLACK_INT_START, -fld_BLACK_INT_LENGTH, -fld_UV_INT_START, -fld_U_INT_LENGTH, -fld_V_INT_LENGTH, -fld_CRDR_ACTIVE_GAIN, -fld_CBDB_ACTIVE_GAIN, -fld_DVS_DIRECTION, -fld_DVS_VBI_UINT8_SWAP, -fld_DVS_CLK_SELECT, -fld_CONTINUOUS_STREAM, -fld_DVSOUT_CLK_DRV, -fld_DVSOUT_DATA_DRV, -fld_COMB_CNTL0, -fld_COMB_CNTL1, -fld_COMB_CNTL2, -fld_COMB_LENGTH, -fld_SYNCTIP_REF0, -fld_SYNCTIP_REF1, -fld_CLAMP_REF, -fld_AGC_PEAKWHITE, -fld_VBI_PEAKWHITE, -fld_WPA_THRESHOLD, -fld_WPA_TRIGGER_LO, -fld_WPA_TRIGGER_HIGH, -fld_LOCKOUT_START, -fld_LOCKOUT_END, -fld_CH_DTO_INC, -fld_PLL_SGAIN, -fld_PLL_FGAIN, -fld_CR_BURST_GAIN, -fld_CB_BURST_GAIN, -fld_VERT_LOCKOUT_START, -fld_VERT_LOCKOUT_END, -fld_H_IN_WIND_START, -fld_V_IN_WIND_START, -fld_H_OUT_WIND_WIDTH, -fld_V_OUT_WIND_WIDTH, -fld_HS_LINE_TOTAL, -fld_MIN_PULSE_WIDTH, -fld_MAX_PULSE_WIDTH, -fld_WIN_CLOSE_LIMIT, -fld_WIN_OPEN_LIMIT, -fld_VSYNC_INT_TRIGGER, -fld_VSYNC_INT_HOLD, -fld_VIN_M0, -fld_VIN_N0, -fld_MNFLIP_EN, -fld_VIN_P, -fld_REG_CLK_SEL, -fld_VIN_M1, -fld_VIN_N1, -fld_VIN_DRIVER_SEL, -fld_VIN_MNFLIP_REQ, -fld_VIN_MNFLIP_DONE, -fld_TV_LOCK_TO_VIN, -fld_TV_P_FOR_WINCLK, -fld_VINRST, -fld_VIN_CLK_SEL, -fld_VS_FIELD_BLANK_START, -fld_VS_FIELD_BLANK_END, -fld_VS_FIELD_IDLOCATION, -fld_VS_FRAME_TOTAL, -fld_SYNC_TIP_START, -fld_SYNC_TIP_LENGTH, -fld_GAIN_FORCE_DATA, -fld_GAIN_FORCE_EN, -fld_I_CLAMP_SEL, -fld_I_AGC_SEL, -fld_EXT_CLAMP_CAP, -fld_EXT_AGC_CAP, -fld_DECI_DITHER_EN, -fld_ADC_PREFHI, -fld_ADC_CH_GAIN_SEL, -fld_HS_PLL_SGAIN, -fld_NREn, -fld_NRGainCntl, -fld_NRBWTresh, -fld_NRGCTresh, -fld_NRCoefDespeclMode, -fld_GPIO_5_OE, -fld_GPIO_6_OE, -fld_GPIO_5_OUT, -fld_GPIO_6_OUT, - -regRT_MAX_REGS -} a; - - -typedef struct { - uint8_t size; - uint32_t fld_id; - uint32_t dwRegAddrLSBs; - uint32_t dwFldOffsetLSBs; - uint32_t dwMaskLSBs; - uint32_t addr2; - uint32_t offs2; - uint32_t mask2; - uint32_t dwCurrValue; - uint32_t rw; - } RTREGMAP; - -#define READONLY 1 -#define WRITEONLY 2 -#define READWRITE 3 - -/* Rage Theatre's Register Mappings, including the default values: */ -RTREGMAP RT_RegMap[regRT_MAX_REGS]={ -/* -{size, fidname, AddrOfst, Ofst, Mask, Addr, Ofst, Mask, Cur, R/W -*/ -{32 , fld_tmpReg1 ,0x151 , 0, 0x0, 0, 0,0, 0,READWRITE }, -{1 , fld_tmpReg2 ,VIP_VIP_SUB_VENDOR_DEVICE_ID , 3, 0xFFFFFFFF, 0, 0,0, 0,READWRITE }, -{1 , fld_tmpReg3 ,VIP_VIP_COMMAND_STATUS , 3, 0xFFFFFFFF, 0, 0,0, 0,READWRITE }, -{8 , fld_LP_CONTRAST ,VIP_LP_CONTRAST , 0, 0xFFFFFF00, 0, 0,0, fld_LP_CONTRAST_def ,READWRITE }, -{14 , fld_LP_BRIGHTNESS ,VIP_LP_BRIGHTNESS , 0, 0xFFFFC000, 0, 0,0, fld_LP_BRIGHTNESS_def ,READWRITE }, -{8 , fld_CP_HUE_CNTL ,VIP_CP_HUE_CNTL , 0, 0xFFFFFF00, 0, 0,0, fld_CP_HUE_CNTL_def ,READWRITE }, -{1 , fld_LUMA_FILTER ,VIP_LP_BRIGHTNESS , 15, 0xFFFF7FFF, 0, 0,0, fld_LUMA_FILTER_def ,READWRITE }, -{21 , fld_H_SCALE_RATIO ,VIP_H_SCALER_CONTROL , 0, 0xFFE00000, 0, 0,0, fld_H_SCALE_RATIO_def ,READWRITE }, -{4 , fld_H_SHARPNESS ,VIP_H_SCALER_CONTROL , 25, 0xE1FFFFFF, 0, 0,0, fld_H_SHARPNESS_def ,READWRITE }, -{12 , fld_V_SCALE_RATIO ,VIP_V_SCALER_CONTROL , 0, 0xFFFFF000, 0, 0,0, fld_V_SCALE_RATIO_def ,READWRITE }, -{1 , fld_V_DEINTERLACE_ON,VIP_V_SCALER_CONTROL , 12, 0xFFFFEFFF, 0, 0,0, fld_V_DEINTERLACE_ON_def ,READWRITE }, -{1 , fld_V_BYPSS ,VIP_V_SCALER_CONTROL , 14, 0xFFFFBFFF, 0, 0,0, fld_V_BYPSS_def ,READWRITE }, -{1 , fld_V_DITHER_ON ,VIP_V_SCALER_CONTROL , 15, 0xFFFF7FFF, 0, 0,0, fld_V_DITHER_ON_def ,READWRITE }, -{11 , fld_EVENF_OFFSET ,VIP_V_DEINTERLACE_CONTROL , 0, 0xFFFFF800, 0, 0,0, fld_EVENF_OFFSET_def ,READWRITE }, -{11 , fld_ODDF_OFFSET ,VIP_V_DEINTERLACE_CONTROL , 11, 0xFFC007FF, 0, 0,0, fld_ODDF_OFFSET_def ,READWRITE }, -{1 , fld_INTERLACE_DETECTED ,VIP_VS_LINE_COUNT , 15, 0xFFFF7FFF, 0, 0,0, fld_INTERLACE_DETECTED_def,READONLY }, -{10 , fld_VS_LINE_COUNT ,VIP_VS_LINE_COUNT , 0, 0xFFFFFC00, 0, 0,0, fld_VS_LINE_COUNT_def ,READONLY }, -{10 , fld_VS_DETECTED_LINES ,VIP_VS_LINE_COUNT , 16, 0xFC00FFFF, 0, 0,0, fld_VS_DETECTED_LINES_def ,READONLY }, -{1 , fld_VS_ITU656_VB ,VIP_VS_LINE_COUNT , 13, 0xFFFFDFFF, 0, 0,0, fld_VS_ITU656_VB_def ,READONLY }, -{16 , fld_VBI_CC_DATA ,VIP_VBI_CC_CNTL , 0, 0xFFFF0000, 0, 0,0, fld_VBI_CC_DATA_def ,READWRITE }, -{1 , fld_VBI_CC_WT ,VIP_VBI_CC_CNTL , 24, 0xFEFFFFFF, 0, 0,0, fld_VBI_CC_WT_def ,READWRITE }, -{1 , fld_VBI_CC_WT_ACK ,VIP_VBI_CC_CNTL , 25, 0xFDFFFFFF, 0, 0,0, fld_VBI_CC_WT_ACK_def ,READONLY }, -{1 , fld_VBI_CC_HOLD ,VIP_VBI_CC_CNTL , 26, 0xFBFFFFFF, 0, 0,0, fld_VBI_CC_HOLD_def ,READWRITE }, -{1 , fld_VBI_DECODE_EN ,VIP_VBI_CC_CNTL , 31, 0x7FFFFFFF, 0, 0,0, fld_VBI_DECODE_EN_def ,READWRITE }, -{16 , fld_VBI_CC_DTO_P ,VIP_VBI_DTO_CNTL , 0, 0xFFFF0000, 0, 0,0, fld_VBI_CC_DTO_P_def ,READWRITE }, -{16 ,fld_VBI_20BIT_DTO_P,VIP_VBI_DTO_CNTL , 16, 0x0000FFFF, 0, 0,0, fld_VBI_20BIT_DTO_P_def ,READWRITE }, -{7 ,fld_VBI_CC_LEVEL ,VIP_VBI_LEVEL_CNTL , 0, 0xFFFFFF80, 0, 0,0, fld_VBI_CC_LEVEL_def ,READWRITE }, -{7 ,fld_VBI_20BIT_LEVEL,VIP_VBI_LEVEL_CNTL , 8, 0xFFFF80FF, 0, 0,0, fld_VBI_20BIT_LEVEL_def ,READWRITE }, -{9 ,fld_VBI_CLK_RUNIN_GAIN,VIP_VBI_LEVEL_CNTL , 16, 0xFE00FFFF, 0, 0,0, fld_VBI_CLK_RUNIN_GAIN_def,READWRITE }, -{11 ,fld_H_VBI_WIND_START,VIP_H_VBI_WINDOW , 0, 0xFFFFF800, 0, 0,0, fld_H_VBI_WIND_START_def ,READWRITE }, -{11 ,fld_H_VBI_WIND_END,VIP_H_VBI_WINDOW , 16, 0xF800FFFF, 0, 0,0, fld_H_VBI_WIND_END_def ,READWRITE }, -{10 ,fld_V_VBI_WIND_START,VIP_V_VBI_WINDOW , 0, 0xFFFFFC00, 0, 0,0, fld_V_VBI_WIND_START_def ,READWRITE }, -{10 ,fld_V_VBI_WIND_END,VIP_V_VBI_WINDOW , 16, 0xFC00FFFF, 0, 0,0, fld_V_VBI_WIND_END_def ,READWRITE }, /* CHK */ -{16 ,fld_VBI_20BIT_DATA0,VIP_VBI_20BIT_CNTL , 0, 0xFFFF0000, 0, 0,0, fld_VBI_20BIT_DATA0_def ,READWRITE }, -{4 ,fld_VBI_20BIT_DATA1,VIP_VBI_20BIT_CNTL , 16, 0xFFF0FFFF, 0, 0,0, fld_VBI_20BIT_DATA1_def ,READWRITE }, -{1 ,fld_VBI_20BIT_WT ,VIP_VBI_20BIT_CNTL , 24, 0xFEFFFFFF, 0, 0,0, fld_VBI_20BIT_WT_def ,READWRITE }, -{1 ,fld_VBI_20BIT_WT_ACK ,VIP_VBI_20BIT_CNTL , 25, 0xFDFFFFFF, 0, 0,0, fld_VBI_20BIT_WT_ACK_def ,READONLY }, -{1 ,fld_VBI_20BIT_HOLD ,VIP_VBI_20BIT_CNTL , 26, 0xFBFFFFFF, 0, 0,0, fld_VBI_20BIT_HOLD_def ,READWRITE }, -{2 ,fld_VBI_CAPTURE_ENABLE ,VIP_VBI_CONTROL , 0, 0xFFFFFFFC, 0, 0,0, fld_VBI_CAPTURE_ENABLE_def,READWRITE }, -{16 ,fld_VBI_EDS_DATA ,VIP_VBI_EDS_CNTL , 0, 0xFFFF0000, 0, 0,0, fld_VBI_EDS_DATA_def ,READWRITE }, -{1 ,fld_VBI_EDS_WT ,VIP_VBI_EDS_CNTL , 24, 0xFEFFFFFF, 0, 0,0, fld_VBI_EDS_WT_def ,READWRITE }, -{1 ,fld_VBI_EDS_WT_ACK ,VIP_VBI_EDS_CNTL , 25, 0xFDFFFFFF, 0, 0,0, fld_VBI_EDS_WT_ACK_def ,READONLY }, -{1 ,fld_VBI_EDS_HOLD ,VIP_VBI_EDS_CNTL , 26, 0xFBFFFFFF, 0, 0,0, fld_VBI_EDS_HOLD_def ,READWRITE }, -{17 ,fld_VBI_SCALING_RATIO ,VIP_VBI_SCALER_CONTROL , 0, 0xFFFE0000, 0, 0,0, fld_VBI_SCALING_RATIO_def ,READWRITE }, -{1 ,fld_VBI_ALIGNER_ENABLE ,VIP_VBI_SCALER_CONTROL , 17, 0xFFFDFFFF, 0, 0,0, fld_VBI_ALIGNER_ENABLE_def,READWRITE }, -{11 ,fld_H_ACTIVE_START ,VIP_H_ACTIVE_WINDOW , 0, 0xFFFFF800, 0, 0,0, fld_H_ACTIVE_START_def ,READWRITE }, -{11 ,fld_H_ACTIVE_END ,VIP_H_ACTIVE_WINDOW , 16, 0xF800FFFF, 0, 0,0, fld_H_ACTIVE_END_def ,READWRITE }, -{10 ,fld_V_ACTIVE_START ,VIP_V_ACTIVE_WINDOW , 0, 0xFFFFFC00, 0, 0,0, fld_V_ACTIVE_START_def ,READWRITE }, -{10 ,fld_V_ACTIVE_END ,VIP_V_ACTIVE_WINDOW , 16, 0xFC00FFFF, 0, 0,0, fld_V_ACTIVE_END_def ,READWRITE }, -{8 ,fld_CH_HEIGHT ,VIP_CP_AGC_CNTL , 0, 0xFFFFFF00, 0, 0,0, fld_CH_HEIGHT_def ,READWRITE }, -{8 ,fld_CH_KILL_LEVEL ,VIP_CP_AGC_CNTL , 8, 0xFFFF00FF, 0, 0,0, fld_CH_KILL_LEVEL_def ,READWRITE }, -{2 ,fld_CH_AGC_ERROR_LIM ,VIP_CP_AGC_CNTL , 16, 0xFFFCFFFF, 0, 0,0, fld_CH_AGC_ERROR_LIM_def ,READWRITE }, -{1 ,fld_CH_AGC_FILTER_EN ,VIP_CP_AGC_CNTL , 18, 0xFFFBFFFF, 0, 0,0, fld_CH_AGC_FILTER_EN_def ,READWRITE }, -{1 ,fld_CH_AGC_LOOP_SPEED ,VIP_CP_AGC_CNTL , 19, 0xFFF7FFFF, 0, 0,0, fld_CH_AGC_LOOP_SPEED_def ,READWRITE }, -{8 ,fld_HUE_ADJ ,VIP_CP_HUE_CNTL , 0, 0xFFFFFF00, 0, 0,0, fld_HUE_ADJ_def ,READWRITE }, -{2 ,fld_STANDARD_SEL ,VIP_STANDARD_SELECT , 0, 0xFFFFFFFC, 0, 0,0, fld_STANDARD_SEL_def ,READWRITE }, -{1 ,fld_STANDARD_YC ,VIP_STANDARD_SELECT , 2, 0xFFFFFFFB, 0, 0,0, fld_STANDARD_YC_def ,READWRITE }, -{1 ,fld_ADC_PDWN ,VIP_ADC_CNTL , 7, 0xFFFFFF7F, 0, 0,0, fld_ADC_PDWN_def ,READWRITE }, -{3 ,fld_INPUT_SELECT ,VIP_ADC_CNTL , 0, 0xFFFFFFF8, 0, 0,0, fld_INPUT_SELECT_def ,READWRITE }, -{2 ,fld_ADC_PREFLO ,VIP_ADC_CNTL , 24, 0xFCFFFFFF, 0, 0,0, fld_ADC_PREFLO_def ,READWRITE }, -{8 ,fld_H_SYNC_PULSE_WIDTH ,VIP_HS_PULSE_WIDTH , 0, 0xFFFFFF00, 0, 0,0, fld_H_SYNC_PULSE_WIDTH_def,READONLY }, -{1 ,fld_HS_GENLOCKED ,VIP_HS_PULSE_WIDTH , 8, 0xFFFFFEFF, 0, 0,0, fld_HS_GENLOCKED_def ,READONLY }, -{1 ,fld_HS_SYNC_IN_WIN ,VIP_HS_PULSE_WIDTH , 9, 0xFFFFFDFF, 0, 0,0, fld_HS_SYNC_IN_WIN_def ,READONLY }, -{1 ,fld_VIN_ASYNC_RST ,VIP_MASTER_CNTL , 5, 0xFFFFFFDF, 0, 0,0, fld_VIN_ASYNC_RST_def ,READWRITE }, -{1 ,fld_DVS_ASYNC_RST ,VIP_MASTER_CNTL , 7, 0xFFFFFF7F, 0, 0,0, fld_DVS_ASYNC_RST_def ,READWRITE }, -{16 ,fld_VIP_VENDOR_ID ,VIP_VIP_VENDOR_DEVICE_ID, 0, 0xFFFF0000, 0, 0,0, fld_VIP_VENDOR_ID_def ,READONLY }, -{16 ,fld_VIP_DEVICE_ID ,VIP_VIP_VENDOR_DEVICE_ID,16, 0x0000FFFF, 0, 0,0, fld_VIP_DEVICE_ID_def ,READONLY }, -{16 ,fld_VIP_REVISION_ID ,VIP_VIP_REVISION_ID , 0, 0xFFFF0000, 0, 0,0, fld_VIP_REVISION_ID_def ,READONLY }, -{8 ,fld_BLACK_INT_START ,VIP_SG_BLACK_GATE , 0, 0xFFFFFF00, 0, 0,0, fld_BLACK_INT_START_def ,READWRITE }, -{4 ,fld_BLACK_INT_LENGTH ,VIP_SG_BLACK_GATE , 8, 0xFFFFF0FF, 0, 0,0, fld_BLACK_INT_LENGTH_def ,READWRITE }, -{8 ,fld_UV_INT_START ,VIP_SG_UVGATE_GATE , 0, 0xFFFFFF00, 0, 0,0, fld_UV_INT_START_def ,READWRITE }, -{4 ,fld_U_INT_LENGTH ,VIP_SG_UVGATE_GATE , 8, 0xFFFFF0FF, 0, 0,0, fld_U_INT_LENGTH_def ,READWRITE }, -{4 ,fld_V_INT_LENGTH ,VIP_SG_UVGATE_GATE , 12, 0xFFFF0FFF, 0, 0,0, fld_V_INT_LENGTH_def ,READWRITE }, -{10 ,fld_CRDR_ACTIVE_GAIN ,VIP_CP_ACTIVE_GAIN , 0, 0xFFFFFC00, 0, 0,0, fld_CRDR_ACTIVE_GAIN_def ,READWRITE }, -{10 ,fld_CBDB_ACTIVE_GAIN ,VIP_CP_ACTIVE_GAIN , 16, 0xFC00FFFF, 0, 0,0, fld_CBDB_ACTIVE_GAIN_def ,READWRITE }, -{1 ,fld_DVS_DIRECTION ,VIP_DVS_PORT_CTRL , 0, 0xFFFFFFFE, 0, 0,0, fld_DVS_DIRECTION_def ,READWRITE }, -{1 ,fld_DVS_VBI_UINT8_SWAP ,VIP_DVS_PORT_CTRL , 1, 0xFFFFFFFD, 0, 0,0, fld_DVS_VBI_UINT8_SWAP_def ,READWRITE }, -{1 ,fld_DVS_CLK_SELECT ,VIP_DVS_PORT_CTRL , 2, 0xFFFFFFFB, 0, 0,0, fld_DVS_CLK_SELECT_def ,READWRITE }, -{1 ,fld_CONTINUOUS_STREAM ,VIP_DVS_PORT_CTRL , 3, 0xFFFFFFF7, 0, 0,0, fld_CONTINUOUS_STREAM_def ,READWRITE }, -{1 ,fld_DVSOUT_CLK_DRV ,VIP_DVS_PORT_CTRL , 4, 0xFFFFFFEF, 0, 0,0, fld_DVSOUT_CLK_DRV_def ,READWRITE }, -{1 ,fld_DVSOUT_DATA_DRV ,VIP_DVS_PORT_CTRL , 5, 0xFFFFFFDF, 0, 0,0, fld_DVSOUT_DATA_DRV_def ,READWRITE }, -{32 ,fld_COMB_CNTL0 ,VIP_COMB_CNTL0 , 0, 0x00000000, 0, 0,0, fld_COMB_CNTL0_def ,READWRITE }, -{32 ,fld_COMB_CNTL1 ,VIP_COMB_CNTL1 , 0, 0x00000000, 0, 0,0, fld_COMB_CNTL1_def ,READWRITE }, -{32 ,fld_COMB_CNTL2 ,VIP_COMB_CNTL2 , 0, 0x00000000, 0, 0,0, fld_COMB_CNTL2_def ,READWRITE }, -{32 ,fld_COMB_LENGTH ,VIP_COMB_LINE_LENGTH , 0, 0x00000000, 0, 0,0, fld_COMB_LENGTH_def ,READWRITE }, -{8 ,fld_SYNCTIP_REF0 ,VIP_LP_AGC_CLAMP_CNTL0 , 0, 0xFFFFFF00, 0, 0,0, fld_SYNCTIP_REF0_def ,READWRITE }, -{8 ,fld_SYNCTIP_REF1 ,VIP_LP_AGC_CLAMP_CNTL0 , 8, 0xFFFF00FF, 0, 0,0, fld_SYNCTIP_REF1_def ,READWRITE }, -{8 ,fld_CLAMP_REF ,VIP_LP_AGC_CLAMP_CNTL0 , 16, 0xFF00FFFF, 0, 0,0, fld_CLAMP_REF_def ,READWRITE }, -{8 ,fld_AGC_PEAKWHITE ,VIP_LP_AGC_CLAMP_CNTL0 , 24, 0x00FFFFFF, 0, 0,0, fld_AGC_PEAKWHITE_def ,READWRITE }, -{8 ,fld_VBI_PEAKWHITE ,VIP_LP_AGC_CLAMP_CNTL1 , 0, 0xFFFFFF00, 0, 0,0, fld_VBI_PEAKWHITE_def ,READWRITE }, -{11 ,fld_WPA_THRESHOLD ,VIP_LP_WPA_CNTL0 , 0, 0xFFFFF800, 0, 0,0, fld_WPA_THRESHOLD_def ,READWRITE }, -{10 ,fld_WPA_TRIGGER_LO ,VIP_LP_WPA_CNTL1 , 0, 0xFFFFFC00, 0, 0,0, fld_WPA_TRIGGER_LO_def ,READWRITE }, -{10 ,fld_WPA_TRIGGER_HIGH ,VIP_LP_WPA_CNTL1 , 16, 0xFC00FFFF, 0, 0,0, fld_WPA_TRIGGER_HIGH_def ,READWRITE }, -{10 ,fld_LOCKOUT_START ,VIP_LP_VERT_LOCKOUT , 0, 0xFFFFFC00, 0, 0,0, fld_LOCKOUT_START_def ,READWRITE }, -{10 ,fld_LOCKOUT_END ,VIP_LP_VERT_LOCKOUT , 16, 0xFC00FFFF, 0, 0,0, fld_LOCKOUT_END_def ,READWRITE }, -{24 ,fld_CH_DTO_INC ,VIP_CP_PLL_CNTL0 , 0, 0xFF000000, 0, 0,0, fld_CH_DTO_INC_def ,READWRITE }, -{4 ,fld_PLL_SGAIN ,VIP_CP_PLL_CNTL0 , 24, 0xF0FFFFFF, 0, 0,0, fld_PLL_SGAIN_def ,READWRITE }, -{4 ,fld_PLL_FGAIN ,VIP_CP_PLL_CNTL0 , 28, 0x0FFFFFFF, 0, 0,0, fld_PLL_FGAIN_def ,READWRITE }, -{9 ,fld_CR_BURST_GAIN ,VIP_CP_BURST_GAIN , 0, 0xFFFFFE00, 0, 0,0, fld_CR_BURST_GAIN_def ,READWRITE }, -{9 ,fld_CB_BURST_GAIN ,VIP_CP_BURST_GAIN , 16, 0xFE00FFFF, 0, 0,0, fld_CB_BURST_GAIN_def ,READWRITE }, -{10 ,fld_VERT_LOCKOUT_START ,VIP_CP_VERT_LOCKOUT , 0, 0xFFFFFC00, 0, 0,0, fld_VERT_LOCKOUT_START_def,READWRITE }, -{10 ,fld_VERT_LOCKOUT_END ,VIP_CP_VERT_LOCKOUT , 16, 0xFC00FFFF, 0, 0,0, fld_VERT_LOCKOUT_END_def ,READWRITE }, -{11 ,fld_H_IN_WIND_START ,VIP_SCALER_IN_WINDOW , 0, 0xFFFFF800, 0, 0,0, fld_H_IN_WIND_START_def ,READWRITE }, -{10 ,fld_V_IN_WIND_START ,VIP_SCALER_IN_WINDOW , 16, 0xFC00FFFF, 0, 0,0, fld_V_IN_WIND_START_def ,READWRITE }, -{10 ,fld_H_OUT_WIND_WIDTH ,VIP_SCALER_OUT_WINDOW , 0, 0xFFFFFC00, 0, 0,0, fld_H_OUT_WIND_WIDTH_def ,READWRITE }, -{9 ,fld_V_OUT_WIND_WIDTH ,VIP_SCALER_OUT_WINDOW , 16, 0xFE00FFFF, 0, 0,0, fld_V_OUT_WIND_WIDTH_def ,READWRITE }, -{11 ,fld_HS_LINE_TOTAL ,VIP_HS_PLINE , 0, 0xFFFFF800, 0, 0,0, fld_HS_LINE_TOTAL_def ,READWRITE }, -{8 ,fld_MIN_PULSE_WIDTH ,VIP_HS_MINMAXWIDTH , 0, 0xFFFFFF00, 0, 0,0, fld_MIN_PULSE_WIDTH_def ,READWRITE }, -{8 ,fld_MAX_PULSE_WIDTH ,VIP_HS_MINMAXWIDTH , 8, 0xFFFF00FF, 0, 0,0, fld_MAX_PULSE_WIDTH_def ,READWRITE }, -{11 ,fld_WIN_CLOSE_LIMIT ,VIP_HS_WINDOW_LIMIT , 0, 0xFFFFF800, 0, 0,0, fld_WIN_CLOSE_LIMIT_def ,READWRITE }, -{11 ,fld_WIN_OPEN_LIMIT ,VIP_HS_WINDOW_LIMIT , 16, 0xF800FFFF, 0, 0,0, fld_WIN_OPEN_LIMIT_def ,READWRITE }, -{11 ,fld_VSYNC_INT_TRIGGER ,VIP_VS_DETECTOR_CNTL , 0, 0xFFFFF800, 0, 0,0, fld_VSYNC_INT_TRIGGER_def ,READWRITE }, -{11 ,fld_VSYNC_INT_HOLD ,VIP_VS_DETECTOR_CNTL , 16, 0xF800FFFF, 0, 0,0, fld_VSYNC_INT_HOLD_def ,READWRITE }, -{11 ,fld_VIN_M0 ,VIP_VIN_PLL_CNTL , 0, 0xFFFFF800, 0, 0,0, fld_VIN_M0_def ,READWRITE }, -{11 ,fld_VIN_N0 ,VIP_VIN_PLL_CNTL , 11, 0xFFC007FF, 0, 0,0, fld_VIN_N0_def ,READWRITE }, -{1 ,fld_MNFLIP_EN ,VIP_VIN_PLL_CNTL , 22, 0xFFBFFFFF, 0, 0,0, fld_MNFLIP_EN_def ,READWRITE }, -{4 ,fld_VIN_P ,VIP_VIN_PLL_CNTL , 24, 0xF0FFFFFF, 0, 0,0, fld_VIN_P_def ,READWRITE }, -{2 ,fld_REG_CLK_SEL ,VIP_VIN_PLL_CNTL , 30, 0x3FFFFFFF, 0, 0,0, fld_REG_CLK_SEL_def ,READWRITE }, -{11 ,fld_VIN_M1 ,VIP_VIN_PLL_FINE_CNTL , 0, 0xFFFFF800, 0, 0,0, fld_VIN_M1_def ,READWRITE }, -{11 ,fld_VIN_N1 ,VIP_VIN_PLL_FINE_CNTL , 11, 0xFFC007FF, 0, 0,0, fld_VIN_N1_def ,READWRITE }, -{1 ,fld_VIN_DRIVER_SEL ,VIP_VIN_PLL_FINE_CNTL , 22, 0xFFBFFFFF, 0, 0,0, fld_VIN_DRIVER_SEL_def ,READWRITE }, -{1 ,fld_VIN_MNFLIP_REQ ,VIP_VIN_PLL_FINE_CNTL , 23, 0xFF7FFFFF, 0, 0,0, fld_VIN_MNFLIP_REQ_def ,READWRITE }, -{1 ,fld_VIN_MNFLIP_DONE ,VIP_VIN_PLL_FINE_CNTL , 24, 0xFEFFFFFF, 0, 0,0, fld_VIN_MNFLIP_DONE_def ,READONLY }, -{1 ,fld_TV_LOCK_TO_VIN ,VIP_VIN_PLL_FINE_CNTL , 27, 0xF7FFFFFF, 0, 0,0, fld_TV_LOCK_TO_VIN_def ,READWRITE }, -{4 ,fld_TV_P_FOR_WINCLK ,VIP_VIN_PLL_FINE_CNTL , 28, 0x0FFFFFFF, 0, 0,0, fld_TV_P_FOR_WINCLK_def ,READWRITE }, -{1 ,fld_VINRST ,VIP_PLL_CNTL1 , 1, 0xFFFFFFFD, 0, 0,0, fld_VINRST_def ,READWRITE }, -{1 ,fld_VIN_CLK_SEL ,VIP_CLOCK_SEL_CNTL , 7, 0xFFFFFF7F, 0, 0,0, fld_VIN_CLK_SEL_def ,READWRITE }, -{10 ,fld_VS_FIELD_BLANK_START,VIP_VS_BLANKING_CNTL , 0, 0xFFFFFC00, 0, 0,0, fld_VS_FIELD_BLANK_START_def ,READWRITE }, -{10 ,fld_VS_FIELD_BLANK_END,VIP_VS_BLANKING_CNTL , 16, 0xFC00FFFF, 0, 0,0, fld_VS_FIELD_BLANK_END_def ,READWRITE }, -{9 ,fld_VS_FIELD_IDLOCATION,VIP_VS_FIELD_ID_CNTL , 0, 0xFFFFFE00, 0, 0,0, fld_VS_FIELD_IDLOCATION_def ,READWRITE }, -{10 ,fld_VS_FRAME_TOTAL ,VIP_VS_FRAME_TOTAL , 0, 0xFFFFFC00, 0, 0,0, fld_VS_FRAME_TOTAL_def ,READWRITE }, -{11 ,fld_SYNC_TIP_START ,VIP_SG_SYNCTIP_GATE , 0, 0xFFFFF800, 0, 0,0, fld_SYNC_TIP_START_def ,READWRITE }, -{4 ,fld_SYNC_TIP_LENGTH ,VIP_SG_SYNCTIP_GATE , 12, 0xFFFF0FFF, 0, 0,0, fld_SYNC_TIP_LENGTH_def ,READWRITE }, -{12 ,fld_GAIN_FORCE_DATA ,VIP_CP_DEBUG_FORCE , 0, 0xFFFFF000, 0, 0,0, fld_GAIN_FORCE_DATA_def ,READWRITE }, -{1 ,fld_GAIN_FORCE_EN ,VIP_CP_DEBUG_FORCE , 12, 0xFFFFEFFF, 0, 0,0, fld_GAIN_FORCE_EN_def ,READWRITE }, -{2 ,fld_I_CLAMP_SEL ,VIP_ADC_CNTL , 3, 0xFFFFFFE7, 0, 0,0, fld_I_CLAMP_SEL_def ,READWRITE }, -{2 ,fld_I_AGC_SEL ,VIP_ADC_CNTL , 5, 0xFFFFFF9F, 0, 0,0, fld_I_AGC_SEL_def ,READWRITE }, -{1 ,fld_EXT_CLAMP_CAP ,VIP_ADC_CNTL , 8, 0xFFFFFEFF, 0, 0,0, fld_EXT_CLAMP_CAP_def ,READWRITE }, -{1 ,fld_EXT_AGC_CAP ,VIP_ADC_CNTL , 9, 0xFFFFFDFF, 0, 0,0, fld_EXT_AGC_CAP_def ,READWRITE }, -{1 ,fld_DECI_DITHER_EN ,VIP_ADC_CNTL , 12, 0xFFFFEFFF, 0, 0,0, fld_DECI_DITHER_EN_def ,READWRITE }, -{2 ,fld_ADC_PREFHI ,VIP_ADC_CNTL , 22, 0xFF3FFFFF, 0, 0,0, fld_ADC_PREFHI_def ,READWRITE }, -{2 ,fld_ADC_CH_GAIN_SEL ,VIP_ADC_CNTL , 16, 0xFFFCFFFF, 0, 0,0, fld_ADC_CH_GAIN_SEL_def ,READWRITE }, -{4 ,fld_HS_PLL_SGAIN ,VIP_HS_PLLGAIN , 0, 0xFFFFFFF0, 0, 0,0, fld_HS_PLL_SGAIN_def ,READWRITE }, -{1 ,fld_NREn ,VIP_NOISE_CNTL0 , 0, 0xFFFFFFFE, 0, 0,0, fld_NREn_def ,READWRITE }, -{3 ,fld_NRGainCntl ,VIP_NOISE_CNTL0 , 1, 0xFFFFFFF1, 0, 0,0, fld_NRGainCntl_def ,READWRITE }, -{6 ,fld_NRBWTresh ,VIP_NOISE_CNTL0 , 4, 0xFFFFFC0F, 0, 0,0, fld_NRBWTresh_def ,READWRITE }, -{5 ,fld_NRGCTresh ,VIP_NOISE_CNTL0 , 10, 0xFFFF83FF, 0, 0,0, fld_NRGCTresh_def ,READWRITE }, -{1 ,fld_NRCoefDespeclMode ,VIP_NOISE_CNTL0 , 15, 0xFFFF7FFF, 0, 0,0, fld_NRCoefDespeclMode_def ,READWRITE }, -{1 ,fld_GPIO_5_OE ,VIP_GPIO_CNTL , 5, 0xFFFFFFDF, 0, 0,0, fld_GPIO_5_OE_def ,READWRITE }, -{1 ,fld_GPIO_6_OE ,VIP_GPIO_CNTL , 6, 0xFFFFFFBF, 0, 0,0, fld_GPIO_6_OE_def ,READWRITE }, -{1 ,fld_GPIO_5_OUT ,VIP_GPIO_INOUT , 5, 0xFFFFFFDF, 0, 0,0, fld_GPIO_5_OUT_def ,READWRITE }, -{1 ,fld_GPIO_6_OUT ,VIP_GPIO_INOUT , 6, 0xFFFFFFBF, 0, 0,0, fld_GPIO_6_OUT_def ,READWRITE }, -}; - -/* Rage Theatre's register fields default values: */ -uint32_t RT_RegDef[regRT_MAX_REGS]= -{ -fld_tmpReg1_def, -fld_tmpReg2_def, -fld_tmpReg3_def, -fld_LP_CONTRAST_def, -fld_LP_BRIGHTNESS_def, -fld_CP_HUE_CNTL_def, -fld_LUMA_FILTER_def, -fld_H_SCALE_RATIO_def, -fld_H_SHARPNESS_def, -fld_V_SCALE_RATIO_def, -fld_V_DEINTERLACE_ON_def, -fld_V_BYPSS_def, -fld_V_DITHER_ON_def, -fld_EVENF_OFFSET_def, -fld_ODDF_OFFSET_def, -fld_INTERLACE_DETECTED_def, -fld_VS_LINE_COUNT_def, -fld_VS_DETECTED_LINES_def, -fld_VS_ITU656_VB_def, -fld_VBI_CC_DATA_def, -fld_VBI_CC_WT_def, -fld_VBI_CC_WT_ACK_def, -fld_VBI_CC_HOLD_def, -fld_VBI_DECODE_EN_def, -fld_VBI_CC_DTO_P_def, -fld_VBI_20BIT_DTO_P_def, -fld_VBI_CC_LEVEL_def, -fld_VBI_20BIT_LEVEL_def, -fld_VBI_CLK_RUNIN_GAIN_def, -fld_H_VBI_WIND_START_def, -fld_H_VBI_WIND_END_def, -fld_V_VBI_WIND_START_def, -fld_V_VBI_WIND_END_def, -fld_VBI_20BIT_DATA0_def, -fld_VBI_20BIT_DATA1_def, -fld_VBI_20BIT_WT_def, -fld_VBI_20BIT_WT_ACK_def, -fld_VBI_20BIT_HOLD_def, -fld_VBI_CAPTURE_ENABLE_def, -fld_VBI_EDS_DATA_def, -fld_VBI_EDS_WT_def, -fld_VBI_EDS_WT_ACK_def, -fld_VBI_EDS_HOLD_def, -fld_VBI_SCALING_RATIO_def, -fld_VBI_ALIGNER_ENABLE_def, -fld_H_ACTIVE_START_def, -fld_H_ACTIVE_END_def, -fld_V_ACTIVE_START_def, -fld_V_ACTIVE_END_def, -fld_CH_HEIGHT_def, -fld_CH_KILL_LEVEL_def, -fld_CH_AGC_ERROR_LIM_def, -fld_CH_AGC_FILTER_EN_def, -fld_CH_AGC_LOOP_SPEED_def, -fld_HUE_ADJ_def, -fld_STANDARD_SEL_def, -fld_STANDARD_YC_def, -fld_ADC_PDWN_def, -fld_INPUT_SELECT_def, -fld_ADC_PREFLO_def, -fld_H_SYNC_PULSE_WIDTH_def, -fld_HS_GENLOCKED_def, -fld_HS_SYNC_IN_WIN_def, -fld_VIN_ASYNC_RST_def, -fld_DVS_ASYNC_RST_def, -fld_VIP_VENDOR_ID_def, -fld_VIP_DEVICE_ID_def, -fld_VIP_REVISION_ID_def, -fld_BLACK_INT_START_def, -fld_BLACK_INT_LENGTH_def, -fld_UV_INT_START_def, -fld_U_INT_LENGTH_def, -fld_V_INT_LENGTH_def, -fld_CRDR_ACTIVE_GAIN_def, -fld_CBDB_ACTIVE_GAIN_def, -fld_DVS_DIRECTION_def, -fld_DVS_VBI_UINT8_SWAP_def, -fld_DVS_CLK_SELECT_def, -fld_CONTINUOUS_STREAM_def, -fld_DVSOUT_CLK_DRV_def, -fld_DVSOUT_DATA_DRV_def, -fld_COMB_CNTL0_def, -fld_COMB_CNTL1_def, -fld_COMB_CNTL2_def, -fld_COMB_LENGTH_def, -fld_SYNCTIP_REF0_def, -fld_SYNCTIP_REF1_def, -fld_CLAMP_REF_def, -fld_AGC_PEAKWHITE_def, -fld_VBI_PEAKWHITE_def, -fld_WPA_THRESHOLD_def, -fld_WPA_TRIGGER_LO_def, -fld_WPA_TRIGGER_HIGH_def, -fld_LOCKOUT_START_def, -fld_LOCKOUT_END_def, -fld_CH_DTO_INC_def, -fld_PLL_SGAIN_def, -fld_PLL_FGAIN_def, -fld_CR_BURST_GAIN_def, -fld_CB_BURST_GAIN_def, -fld_VERT_LOCKOUT_START_def, -fld_VERT_LOCKOUT_END_def, -fld_H_IN_WIND_START_def, -fld_V_IN_WIND_START_def, -fld_H_OUT_WIND_WIDTH_def, -fld_V_OUT_WIND_WIDTH_def, -fld_HS_LINE_TOTAL_def, -fld_MIN_PULSE_WIDTH_def, -fld_MAX_PULSE_WIDTH_def, -fld_WIN_CLOSE_LIMIT_def, -fld_WIN_OPEN_LIMIT_def, -fld_VSYNC_INT_TRIGGER_def, -fld_VSYNC_INT_HOLD_def, -fld_VIN_M0_def, -fld_VIN_N0_def, -fld_MNFLIP_EN_def, -fld_VIN_P_def, -fld_REG_CLK_SEL_def, -fld_VIN_M1_def, -fld_VIN_N1_def, -fld_VIN_DRIVER_SEL_def, -fld_VIN_MNFLIP_REQ_def, -fld_VIN_MNFLIP_DONE_def, -fld_TV_LOCK_TO_VIN_def, -fld_TV_P_FOR_WINCLK_def, -fld_VINRST_def, -fld_VIN_CLK_SEL_def, -fld_VS_FIELD_BLANK_START_def, -fld_VS_FIELD_BLANK_END_def, -fld_VS_FIELD_IDLOCATION_def, -fld_VS_FRAME_TOTAL_def, -fld_SYNC_TIP_START_def, -fld_SYNC_TIP_LENGTH_def, -fld_GAIN_FORCE_DATA_def, -fld_GAIN_FORCE_EN_def, -fld_I_CLAMP_SEL_def, -fld_I_AGC_SEL_def, -fld_EXT_CLAMP_CAP_def, -fld_EXT_AGC_CAP_def, -fld_DECI_DITHER_EN_def, -fld_ADC_PREFHI_def, -fld_ADC_CH_GAIN_SEL_def, -fld_HS_PLL_SGAIN_def, -fld_NREn_def, -fld_NRGainCntl_def, -fld_NRBWTresh_def, -fld_NRGCTresh_def, -fld_NRCoefDespeclMode_def, -fld_GPIO_5_OE_def, -fld_GPIO_6_OE_def, -fld_GPIO_5_OUT_def, -fld_GPIO_6_OUT_def, -}; - -/**************************************************************************** - * WriteRT_fld (uint32_t dwReg, uint32_t dwData) * - * Function: Writes a register field within Rage Theatre * - * Inputs: uint32_t dwReg = register field to be written * - * uint32_t dwData = data that will be written to the reg field * - * Outputs: NONE * - ****************************************************************************/ -static void WriteRT_fld1 (TheatrePtr t, uint32_t dwReg, uint32_t dwData) -{ - uint32_t dwResult=0; - uint32_t dwValue=0; - - if (RT_regr (RT_RegMap[dwReg].dwRegAddrLSBs, &dwResult) == TRUE) - { - dwValue = (dwResult & RT_RegMap[dwReg].dwMaskLSBs) | - (dwData << RT_RegMap[dwReg].dwFldOffsetLSBs); - - if (RT_regw (RT_RegMap[dwReg].dwRegAddrLSBs, dwValue) == TRUE) - { - /* update the memory mapped registers */ - RT_RegMap[dwReg].dwCurrValue = dwData; - } - } - - return; - -} /* WriteRT_fld ()... */ - -#if 0 -/**************************************************************************** - * ReadRT_fld (uint32_t dwReg) * - * Function: Reads a register field within Rage Theatre * - * Inputs: uint32_t dwReg = register field to be read * - * Outputs: uint32_t - value read from register field * - ****************************************************************************/ -static uint32_t ReadRT_fld1 (TheatrePtr t,uint32_t dwReg) -{ - uint32_t dwResult=0; - - if (RT_regr (RT_RegMap[dwReg].dwRegAddrLSBs, &dwResult) == TRUE) - { - RT_RegMap[dwReg].dwCurrValue = ((dwResult & ~RT_RegMap[dwReg].dwMaskLSBs) >> - RT_RegMap[dwReg].dwFldOffsetLSBs); - return (RT_RegMap[dwReg].dwCurrValue); - } - else - { - return (0xFFFFFFFF); - } - -} /* ReadRT_fld ()... */ - -#define ReadRT_fld(a) ReadRT_fld1(t,(a)) -#endif - -#define WriteRT_fld(a,b) WriteRT_fld1(t, (a), (b)) - - -/**************************************************************************** - * RT_SetTint (int hue) * - * Function: sets the tint (hue) for the Rage Theatre video in * - * Inputs: int hue - the hue value to be set. * - * Outputs: NONE * - ****************************************************************************/ -_X_EXPORT void RT_SetTint (TheatrePtr t, int hue) -{ - /* Validate Hue level */ - if (hue < -1000) - { - hue = -1000; - } - else if (hue > 1000) - { - hue = 1000; - } - - t->iHue=hue; - - dsp_set_tint(t, (uint8_t)((hue*255)/2000 + 128)); - -} /* RT_SetTint ()... */ - - -/**************************************************************************** - * RT_SetSaturation (int Saturation) * - * Function: sets the saturation level for the Rage Theatre video in * - * Inputs: int Saturation - the saturation value to be set. * - * Outputs: NONE * - ****************************************************************************/ -_X_EXPORT void RT_SetSaturation (TheatrePtr t, int Saturation) -{ - /* VALIDATE SATURATION LEVEL */ - if (Saturation < -1000L) - { - Saturation = -1000; - } - else if (Saturation > 1000L) - { - Saturation = 1000; - } - - t->iSaturation = Saturation; - - /* RT200 has saturation in range 0 to 255 with nominal value 128 */ - dsp_set_saturation(t, (uint8_t)((Saturation*255)/2000 + 128)); - - return; -} /* RT_SetSaturation ()...*/ - -/**************************************************************************** - * RT_SetBrightness (int Brightness) * - * Function: sets the brightness level for the Rage Theatre video in * - * Inputs: int Brightness - the brightness value to be set. * - * Outputs: NONE * - ****************************************************************************/ -_X_EXPORT void RT_SetBrightness (TheatrePtr t, int Brightness) -{ - /* VALIDATE BRIGHTNESS LEVEL */ - if (Brightness < -1000) - { - Brightness = -1000; - } - else if (Brightness > 1000) - { - Brightness = 1000; - } - - /* Save value */ - t->iBrightness = Brightness; - t->dbBrightnessRatio = (double) (Brightness+1000.0) / 10.0; - - /* RT200 is having brightness level from 0 to 255 with 128 nominal value */ - dsp_set_brightness(t, (uint8_t)((Brightness*255)/2000 + 128)); - - return; -} /* RT_SetBrightness ()... */ - - -/**************************************************************************** - * RT_SetSharpness (uint16_t wSharpness) * - * Function: sets the sharpness level for the Rage Theatre video in * - * Inputs: uint16_t wSharpness - the sharpness value to be set. * - * Outputs: NONE * - ****************************************************************************/ -_X_EXPORT void RT_SetSharpness (TheatrePtr t, uint16_t wSharpness) -{ - switch (wSharpness) - { - case DEC_SMOOTH : - WriteRT_fld (fld_H_SHARPNESS, RT_NORM_SHARPNESS); - t->wSharpness = RT_NORM_SHARPNESS; - break; - case DEC_SHARP : - WriteRT_fld (fld_H_SHARPNESS, RT_HIGH_SHARPNESS); - t->wSharpness = RT_HIGH_SHARPNESS; - break; - default: - break; - } - return; - -} /* RT_SetSharpness ()... */ - - -/**************************************************************************** - * RT_SetContrast (int Contrast) * - * Function: sets the contrast level for the Rage Theatre video in * - * Inputs: int Contrast - the contrast value to be set. * - * Outputs: NONE * - ****************************************************************************/ -_X_EXPORT void RT_SetContrast (TheatrePtr t, int Contrast) -{ - /* VALIDATE CONTRAST LEVEL */ - if (Contrast < -1000) - { - Contrast = -1000; - } - else if (Contrast > 1000) - { - Contrast = 1000; - } - - /* Save contrast value */ - t->iContrast = Contrast; - t->dbContrast = (double) (Contrast+1000.0) / 1000.0; - - /* RT200 has contrast values between 0 to 255 with nominal value at 128 */ - dsp_set_contrast(t, (uint8_t)((Contrast*255)/2000 + 128)); - return; - -} /* RT_SetContrast ()... */ - -/**************************************************************************** - * RT_SetInterlace (uint8_t bInterlace) * - * Function: to set the interlacing pattern for the Rage Theatre video in * - * Inputs: uint8_t bInterlace * - * Outputs: NONE * - ****************************************************************************/ -_X_EXPORT void RT_SetInterlace (TheatrePtr t, uint8_t bInterlace) -{ - switch(bInterlace) - { - case (TRUE): /*DEC_INTERLACE */ - WriteRT_fld (fld_V_DEINTERLACE_ON, 0x1); - t->wInterlaced = (uint16_t) RT_DECINTERLACED; - break; - case (FALSE): /*DEC_NONINTERLACE */ - WriteRT_fld (fld_V_DEINTERLACE_ON, RT_DECNONINTERLACED); - t->wInterlaced = (uint16_t) RT_DECNONINTERLACED; - break; - default: - break; - } - - return; - -} /* RT_SetInterlace ()... */ - - -/**************************************************************************** - * RT_SetStandard (uint16_t wStandard) * - * Function: to set the input standard for the Rage Theatre video in * - * Inputs: uint16_t wStandard - input standard (NTSC, PAL, SECAM) * - * Outputs: NONE * - ****************************************************************************/ -_X_EXPORT void RT_SetStandard (TheatrePtr t, uint16_t wStandard) -{ - xf86DrvMsg(t->VIP->pScrn->scrnIndex,X_INFO,"Rage Theatre setting standard 0x%04x\n", - wStandard); - - t->wStandard = wStandard; - - /* Program the new standards: */ - switch (wStandard & 0x00FF) - { - case (DEC_NTSC): /*NTSC GROUP - 480 lines */ - switch (wStandard & 0xFF00) - { - case (extNONE): - case (extNTSC): - dsp_set_video_standard(t, 2); - break; - case (extNTSC_J): - dsp_set_video_standard(t, RT200_NTSC_J); - break; - case (extNTSC_443): - dsp_set_video_standard(t, RT200_NTSC_433); - break; - default: - dsp_video_standard_detection(t); - break; - } - break; - case (DEC_PAL): /*PAL GROUP - 625 lines */ - switch (wStandard & 0xFF00) - { - case (extNONE): - case (extPAL): - case (extPAL_B): - case (extPAL_BGHI): - dsp_set_video_standard(t, RT200_PAL_B); - break; - case (extPAL_D): - dsp_set_video_standard(t, RT200_PAL_D); - break; - case (extPAL_G): - dsp_set_video_standard(t, RT200_PAL_G); - break; - case (extPAL_H): - dsp_set_video_standard(t, RT200_PAL_H); - break; - case (extPAL_I): - dsp_set_video_standard(t, RT200_PAL_D); - break; - case (extPAL_N): - dsp_set_video_standard(t, RT200_PAL_N); - break; - case (extPAL_NCOMB): - dsp_set_video_standard(t, RT200_PAL_Ncomb); - break; - case (extPAL_M): - dsp_set_video_standard(t, RT200_PAL_M); - break; - case (extPAL_60): - dsp_set_video_standard(t, RT200_PAL_60); - break; - default: - dsp_video_standard_detection(t); - break; - } - break; - case (DEC_SECAM): /*SECAM GROUP*/ - switch (wStandard & 0xFF00) - { - case (extNONE): - case (extSECAM): - dsp_set_video_standard(t, RT200_SECAM); - break; - case (extSECAM_B): - dsp_set_video_standard(t, RT200_SECAM_B); - break; - case (extSECAM_D): - dsp_set_video_standard(t, RT200_SECAM_D); - break; - case (extSECAM_G): - dsp_set_video_standard(t, RT200_SECAM_G); - break; - case (extSECAM_H): - dsp_set_video_standard(t, RT200_SECAM_H); - break; - case (extSECAM_K): - dsp_set_video_standard(t, RT200_SECAM_K); - break; - case (extSECAM_K1): - dsp_set_video_standard(t, RT200_SECAM_K1); - break; - case (extSECAM_L): - dsp_set_video_standard(t, RT200_SECAM_L); - break; - case (extSECAM_L1): - dsp_set_video_standard(t, RT200_SECAM_L1); - break; - default: - dsp_video_standard_detection(t); - break; - } - break; - default: - dsp_video_standard_detection(t); - } - -} /* RT_SetStandard ()... */ - - -/**************************************************************************** - * RT_SetOutputVideoSize (uint16_t wHorzSize, uint16_t wVertSize, * - * uint8_t fCC_On, uint8_t fVBICap_On) * - * Function: sets the output video size for the Rage Theatre video in * - * Inputs: uint16_t wHorzSize - width of output in pixels * - * uint16_t wVertSize - height of output in pixels (lines) * - * uint8_t fCC_On - enable CC output * - * uint8_t fVBI_Cap_On - enable VBI capture * - * Outputs: NONE * - ****************************************************************************/ -_X_EXPORT void RT_SetOutputVideoSize (TheatrePtr t, uint16_t wHorzSize, uint16_t wVertSize, uint8_t fCC_On, uint8_t fVBICap_On) -{ - /* VBI is ignored now */ - - /* - * If I pass the (wHorzSize, 0, 0) (wVertSize, 0, 0) the image does not synchronize - */ - dsp_set_video_scaler_horizontal(t, 0, 0, 0); - dsp_set_video_scaler_vertical(t, 0, 0, 0); - -} /* RT_SetOutputVideoSize ()...*/ - - -/**************************************************************************** - * RT_SetConnector (uint16_t wStandard, int tunerFlag) * - * Function: - * Inputs: uint16_t wStandard - input standard (NTSC, PAL, SECAM) * - * int tunerFlag - * Outputs: NONE * - ****************************************************************************/ -_X_EXPORT void RT_SetConnector (TheatrePtr t, uint16_t wConnector, int tunerFlag) -{ - uint32_t data; - - t->wConnector = wConnector; - - theatre_read(t, VIP_GPIO_CNTL, &data); - xf86DrvMsg(t->VIP->pScrn->scrnIndex,X_INFO,"VIP_GPIO_CNTL: %x\n", - (unsigned)data); - - theatre_read(t, VIP_GPIO_INOUT, &data); - xf86DrvMsg(t->VIP->pScrn->scrnIndex,X_INFO,"VIP_GPIO_INOUT: %x\n", - (unsigned)data); - - switch (wConnector) - { - case (DEC_TUNER): /* Tuner*/ - /* RT200 does not have any input connector 0 */ - dsp_set_video_input_connector(t, t->wTunerConnector + 1); - - /* this is to set the analog mux used for sond */ - theatre_read(t, VIP_GPIO_CNTL, &data); - data &= ~0x10; - theatre_write(t, VIP_GPIO_CNTL, data); - - theatre_read(t, VIP_GPIO_INOUT, &data); - data &= ~0x10; - theatre_write(t, VIP_GPIO_INOUT, data); - - break; - case (DEC_COMPOSITE): /* Comp*/ - dsp_set_video_input_connector(t, t->wComp0Connector); - - /* this is to set the analog mux used for sond */ - theatre_read(t, VIP_GPIO_CNTL, &data); - data |= 0x10; - theatre_write(t, VIP_GPIO_CNTL, data); - - theatre_read(t, VIP_GPIO_INOUT, &data); - data |= 0x10; - theatre_write(t, VIP_GPIO_INOUT, data); - - break; - case (DEC_SVIDEO): /* Svideo*/ - dsp_set_video_input_connector(t, t->wSVideo0Connector); - - /* this is to set the analog mux used for sond */ - theatre_read(t, VIP_GPIO_CNTL, &data); - data |= 0x10; - theatre_write(t, VIP_GPIO_CNTL, data); - - theatre_read(t, VIP_GPIO_INOUT, &data); - data |= 0x10; - theatre_write(t, VIP_GPIO_INOUT, data); - - break; - default: - dsp_set_video_input_connector(t, t->wComp0Connector); - } - - theatre_read(t, VIP_GPIO_CNTL, &data); - xf86DrvMsg(t->VIP->pScrn->scrnIndex,X_INFO,"VIP_GPIO_CNTL: %x\n", - (unsigned)data); - - theatre_read(t, VIP_GPIO_INOUT, &data); - xf86DrvMsg(t->VIP->pScrn->scrnIndex,X_INFO,"VIP_GPIO_INOUT: %x\n", - (unsigned)data); - - - dsp_configure_i2s_port(t, 0, 0, 0); - dsp_configure_spdif_port(t, 0); - - /*dsp_audio_detection(t, 0);*/ - dsp_audio_mute(t, 1, 1); - dsp_set_audio_volume(t, 128, 128, 0); - -} /* RT_SetConnector ()...*/ - - -_X_EXPORT void InitTheatre(TheatrePtr t) -{ - uint32_t data; - uint32_t M, N, P; - - /* this will give 108Mhz at 27Mhz reference */ - M = 28; - N = 224; - P = 1; - - ShutdownTheatre(t); - usleep(100000); - t->mode=MODE_INITIALIZATION_IN_PROGRESS; - - - data = M | (N << 11) | (P <<24); - RT_regw(VIP_DSP_PLL_CNTL, data); - - RT_regr(VIP_PLL_CNTL0, &data); - data |= 0x2000; - RT_regw(VIP_PLL_CNTL0, data); - - /* RT_regw(VIP_I2C_SLVCNTL, 0x249); */ - RT_regr(VIP_PLL_CNTL1, &data); - data |= 0x00030003; - RT_regw(VIP_PLL_CNTL1, data); - - RT_regr(VIP_PLL_CNTL0, &data); - data &= 0xfffffffc; - RT_regw(VIP_PLL_CNTL0, data); - usleep(15000); - - RT_regr(VIP_CLOCK_SEL_CNTL, &data); - data |= 0x1b; - RT_regw(VIP_CLOCK_SEL_CNTL, data); - - RT_regr(VIP_MASTER_CNTL, &data); - data &= 0xffffff07; - RT_regw(VIP_MASTER_CNTL, data); - data &= 0xffffff03; - RT_regw(VIP_MASTER_CNTL, data); - usleep(1000); - - if (t->microc_path == NULL) - { - t->microc_path = DEFAULT_MICROC_PATH; - xf86DrvMsg(t->VIP->pScrn->scrnIndex, X_INFO, "Microcode: Use default microcode path: %s\n", DEFAULT_MICROC_PATH); - } - else - xf86DrvMsg(t->VIP->pScrn->scrnIndex, X_INFO, "Microcode: Use microcode path: %s\n", t->microc_path); - - - if (t->microc_type == NULL) - { - t->microc_type = DEFAULT_MICROC_TYPE; - xf86DrvMsg(t->VIP->pScrn->scrnIndex, X_INFO, "Microcode: Use default microcode type: %s\n", DEFAULT_MICROC_TYPE); - } - else - xf86DrvMsg(t->VIP->pScrn->scrnIndex, X_INFO, "Microcode: Use microcode type: %s\n", t->microc_type); - - if (DownloadMicrocode(t) < 0) - { - ShutdownTheatre(t); - return; - } - - dsp_set_lowpowerstate(t, 1); - dsp_set_videostreamformat(t, 1); - - t->mode=MODE_INITIALIZED_FOR_TV_IN; -} - -static int DownloadMicrocode(TheatrePtr t) -{ - struct rt200_microc_data microc_data; - microc_data.microc_seg_list = NULL; - - if (microc_load(t->microc_path, t->microc_type, µc_data, t->VIP->pScrn->scrnIndex) < 0) - { - xf86DrvMsg(t->VIP->pScrn->scrnIndex, X_ERROR, "Microcode: cannot load microcode\n"); - goto err_exit; - } - else - { - xf86DrvMsg(t->VIP->pScrn->scrnIndex, X_INFO, "Microcode: device_id: %x\n", microc_data.microc_head.device_id); - xf86DrvMsg(t->VIP->pScrn->scrnIndex, X_INFO, "Microcode: vendor_id: %x\n", microc_data.microc_head.vendor_id); - xf86DrvMsg(t->VIP->pScrn->scrnIndex, X_INFO, "Microcode: rev_id: %x\n", microc_data.microc_head.revision_id); - xf86DrvMsg(t->VIP->pScrn->scrnIndex, X_INFO, "Microcode: num_seg: %x\n", microc_data.microc_head.num_seg); - } - - if (dsp_init(t, µc_data) < 0) - { - xf86DrvMsg(t->VIP->pScrn->scrnIndex, X_ERROR, "Microcode: dsp_init failed\n"); - goto err_exit; - } - else - { - xf86DrvMsg(t->VIP->pScrn->scrnIndex, X_INFO, "Microcode: dsp_init OK\n"); - } - - if (dsp_load(t, µc_data) < 0) - { - xf86DrvMsg(t->VIP->pScrn->scrnIndex, X_ERROR, "Microcode: dsp_download failed\n"); - goto err_exit; - } - else - { - xf86DrvMsg(t->VIP->pScrn->scrnIndex, X_INFO, "Microcode: dsp_download OK\n"); - } - - microc_clean(µc_data, t->VIP->pScrn->scrnIndex); - return 0; - -err_exit: - - microc_clean(µc_data, t->VIP->pScrn->scrnIndex); - return -1; - -} - - -_X_EXPORT void ShutdownTheatre(TheatrePtr t) -{ -#if 0 - WriteRT_fld (fld_VIN_ASYNC_RST, RT_ASYNC_DISABLE); - WriteRT_fld (fld_VINRST , RT_VINRST_RESET); - WriteRT_fld (fld_ADC_PDWN , RT_ADC_DISABLE); - WriteRT_fld (fld_DVS_DIRECTION, RT_DVSDIR_IN); -#endif - t->mode=MODE_UNINITIALIZED; -} - -_X_EXPORT void DumpRageTheatreRegs(TheatrePtr t) -{ - int i; - uint32_t data; - - for(i=0;i<0x900;i+=4) - { - RT_regr(i, &data); - xf86DrvMsg(t->VIP->pScrn->scrnIndex, X_INFO, - "register 0x%04x is equal to 0x%08x\n", i, (unsigned)data); - } - -} - -void DumpRageTheatreRegsByName(TheatrePtr t) -{ - int i; - uint32_t data; - struct { char *name; long addr; } rt_reg_list[]={ - { "ADC_CNTL ", 0x0400 }, - { "ADC_DEBUG ", 0x0404 }, - { "AUD_CLK_DIVIDERS ", 0x00e8 }, - { "AUD_DTO_INCREMENTS ", 0x00ec }, - { "AUD_PLL_CNTL ", 0x00e0 }, - { "AUD_PLL_FINE_CNTL ", 0x00e4 }, - { "CLKOUT_CNTL ", 0x004c }, - { "CLKOUT_GPIO_CNTL ", 0x0038 }, - { "CLOCK_SEL_CNTL ", 0x00d0 }, - { "COMB_CNTL0 ", 0x0440 }, - { "COMB_CNTL1 ", 0x0444 }, - { "COMB_CNTL2 ", 0x0448 }, - { "COMB_LINE_LENGTH ", 0x044c }, - { "CP_ACTIVE_GAIN ", 0x0594 }, - { "CP_AGC_CNTL ", 0x0590 }, - { "CP_BURST_GAIN ", 0x058c }, - { "CP_DEBUG_FORCE ", 0x05b8 }, - { "CP_HUE_CNTL ", 0x0588 }, - { "CP_PLL_CNTL0 ", 0x0580 }, - { "CP_PLL_CNTL1 ", 0x0584 }, - { "CP_PLL_STATUS0 ", 0x0598 }, - { "CP_PLL_STATUS1 ", 0x059c }, - { "CP_PLL_STATUS2 ", 0x05a0 }, - { "CP_PLL_STATUS3 ", 0x05a4 }, - { "CP_PLL_STATUS4 ", 0x05a8 }, - { "CP_PLL_STATUS5 ", 0x05ac }, - { "CP_PLL_STATUS6 ", 0x05b0 }, - { "CP_PLL_STATUS7 ", 0x05b4 }, - { "CP_VERT_LOCKOUT ", 0x05bc }, - { "CRC_CNTL ", 0x02c0 }, - { "CRT_DTO_INCREMENTS ", 0x0394 }, - { "CRT_PLL_CNTL ", 0x00c4 }, - { "CRT_PLL_FINE_CNTL ", 0x00bc }, - { "DECODER_DEBUG_CNTL ", 0x05d4 }, - { "DELAY_ONE_MAP_A ", 0x0114 }, - { "DELAY_ONE_MAP_B ", 0x0118 }, - { "DELAY_ZERO_MAP_A ", 0x011c }, - { "DELAY_ZERO_MAP_B ", 0x0120 }, - { "DFCOUNT ", 0x00a4 }, - { "DFRESTART ", 0x00a8 }, - { "DHRESTART ", 0x00ac }, - { "DVRESTART ", 0x00b0 }, - { "DVS_PORT_CTRL ", 0x0610 }, - { "DVS_PORT_READBACK ", 0x0614 }, - { "FIFOA_CONFIG ", 0x0800 }, - { "FIFOB_CONFIG ", 0x0804 }, - { "FIFOC_CONFIG ", 0x0808 }, - { "FRAME_LOCK_CNTL ", 0x0100 }, - { "GAIN_LIMIT_SETTINGS ", 0x01e4 }, - { "GPIO_CNTL ", 0x0034 }, - { "GPIO_INOUT ", 0x0030 }, - { "HCOUNT ", 0x0090 }, - { "HDISP ", 0x0084 }, - { "HOST_RD_WT_CNTL ", 0x0188 }, - { "HOST_READ_DATA ", 0x0180 }, - { "HOST_WRITE_DATA ", 0x0184 }, - { "HSIZE ", 0x0088 }, - { "HSTART ", 0x008c }, - { "HS_DTOINC ", 0x0484 }, - { "HS_GENLOCKDELAY ", 0x0490 }, - { "HS_MINMAXWIDTH ", 0x048c }, - { "HS_PLINE ", 0x0480 }, - { "HS_PLLGAIN ", 0x0488 }, - { "HS_PLL_ERROR ", 0x04a0 }, - { "HS_PLL_FS_PATH ", 0x04a4 }, - { "HS_PULSE_WIDTH ", 0x049c }, - { "HS_WINDOW_LIMIT ", 0x0494 }, - { "HS_WINDOW_OC_SPEED ", 0x0498 }, - { "HTOTAL ", 0x0080 }, - { "HW_DEBUG ", 0x0010 }, - { "H_ACTIVE_WINDOW ", 0x05c0 }, - { "H_SCALER_CONTROL ", 0x0600 }, - { "H_VBI_WINDOW ", 0x05c8 }, - { "I2C_CNTL ", 0x0054 }, - { "I2C_CNTL_0 ", 0x0020 }, - { "I2C_CNTL_1 ", 0x0024 }, - { "I2C_DATA ", 0x0028 }, - { "I2S_RECEIVE_CNTL ", 0x081c }, - { "I2S_TRANSMIT_CNTL ", 0x0818 }, - { "IIS_TX_CNT_REG ", 0x0824 }, - { "INT_CNTL ", 0x002c }, - { "L54_DTO_INCREMENTS ", 0x00f8 }, - { "L54_PLL_CNTL ", 0x00f0 }, - { "L54_PLL_FINE_CNTL ", 0x00f4 }, - { "LINEAR_GAIN_SETTINGS ", 0x01e8 }, - { "LP_AGC_CLAMP_CNTL0 ", 0x0500 }, - { "LP_AGC_CLAMP_CNTL1 ", 0x0504 }, - { "LP_BLACK_LEVEL ", 0x051c }, - { "LP_BRIGHTNESS ", 0x0508 }, - { "LP_CONTRAST ", 0x050c }, - { "LP_SLICE_LEVEL ", 0x0520 }, - { "LP_SLICE_LIMIT ", 0x0510 }, - { "LP_SYNCTIP_LEVEL ", 0x0524 }, - { "LP_VERT_LOCKOUT ", 0x0528 }, - { "LP_WPA_CNTL0 ", 0x0514 }, - { "LP_WPA_CNTL1 ", 0x0518 }, - { "MASTER_CNTL ", 0x0040 }, - { "MODULATOR_CNTL1 ", 0x0200 }, - { "MODULATOR_CNTL2 ", 0x0204 }, - { "MV_LEVEL_CNTL1 ", 0x0210 }, - { "MV_LEVEL_CNTL2 ", 0x0214 }, - { "MV_MODE_CNTL ", 0x0208 }, - { "MV_STATUS ", 0x0330 }, - { "MV_STRIPE_CNTL ", 0x020c }, - { "NOISE_CNTL0 ", 0x0450 }, - { "PLL_CNTL0 ", 0x00c8 }, - { "PLL_CNTL1 ", 0x00fc }, - { "PLL_TEST_CNTL ", 0x00cc }, - { "PRE_DAC_MUX_CNTL ", 0x0240 }, - { "RGB_CNTL ", 0x0048 }, - { "RIPINTF_PORT_CNTL ", 0x003c }, - { "SCALER_IN_WINDOW ", 0x0618 }, - { "SCALER_OUT_WINDOW ", 0x061c }, - { "SG_BLACK_GATE ", 0x04c0 }, - { "SG_SYNCTIP_GATE ", 0x04c4 }, - { "SG_UVGATE_GATE ", 0x04c8 }, - { "SINGLE_STEP_DATA ", 0x05d8 }, - { "SPDIF_AC3_PREAMBLE ", 0x0814 }, - { "SPDIF_CHANNEL_STAT ", 0x0810 }, - { "SPDIF_PORT_CNTL ", 0x080c }, - { "SPDIF_TX_CNT_REG ", 0x0820 }, - { "STANDARD_SELECT ", 0x0408 }, - { "SW_SCRATCH ", 0x0014 }, - { "SYNC_CNTL ", 0x0050 }, - { "SYNC_LOCK_CNTL ", 0x0104 }, - { "SYNC_SIZE ", 0x00b4 }, - { "THERMO2BIN_STATUS ", 0x040c }, - { "TIMING_CNTL ", 0x01c4 }, - { "TVO_DATA_DELAY_A ", 0x0140 }, - { "TVO_DATA_DELAY_B ", 0x0144 }, - { "TVO_SYNC_PAT_ACCUM ", 0x0108 }, - { "TVO_SYNC_PAT_EXPECT ", 0x0110 }, - { "TVO_SYNC_THRESHOLD ", 0x010c }, - { "TV_DAC_CNTL ", 0x0280 }, - { "TV_DTO_INCREMENTS ", 0x0390 }, - { "TV_PLL_CNTL ", 0x00c0 }, - { "TV_PLL_FINE_CNTL ", 0x00b8 }, - { "UPSAMP_AND_GAIN_CNTL ", 0x01e0 }, - { "UPSAMP_COEFF0_0 ", 0x0340 }, - { "UPSAMP_COEFF0_1 ", 0x0344 }, - { "UPSAMP_COEFF0_2 ", 0x0348 }, - { "UPSAMP_COEFF1_0 ", 0x034c }, - { "UPSAMP_COEFF1_1 ", 0x0350 }, - { "UPSAMP_COEFF1_2 ", 0x0354 }, - { "UPSAMP_COEFF2_0 ", 0x0358 }, - { "UPSAMP_COEFF2_1 ", 0x035c }, - { "UPSAMP_COEFF2_2 ", 0x0360 }, - { "UPSAMP_COEFF3_0 ", 0x0364 }, - { "UPSAMP_COEFF3_1 ", 0x0368 }, - { "UPSAMP_COEFF3_2 ", 0x036c }, - { "UPSAMP_COEFF4_0 ", 0x0370 }, - { "UPSAMP_COEFF4_1 ", 0x0374 }, - { "UPSAMP_COEFF4_2 ", 0x0378 }, - { "UV_ADR ", 0x0300 }, - { "VBI_20BIT_CNTL ", 0x02d0 }, - { "VBI_CC_CNTL ", 0x02c8 }, - { "VBI_CONTROL ", 0x05d0 }, - { "VBI_DTO_CNTL ", 0x02d4 }, - { "VBI_EDS_CNTL ", 0x02cc }, - { "VBI_LEVEL_CNTL ", 0x02d8 }, - { "VBI_SCALER_CONTROL ", 0x060c }, - { "VCOUNT ", 0x009c }, - { "VDISP ", 0x0098 }, - { "VFTOTAL ", 0x00a0 }, - { "VIDEO_PORT_SIG ", 0x02c4 }, - { "VIN_PLL_CNTL ", 0x00d4 }, - { "VIN_PLL_FINE_CNTL ", 0x00d8 }, - { "VIP_COMMAND_STATUS ", 0x0008 }, - { "VIP_REVISION_ID ", 0x000c }, - { "VIP_SUB_VENDOR_DEVICE_ID", 0x0004 }, - { "VIP_VENDOR_DEVICE_ID ", 0x0000 }, - { "VSCALER_CNTL1 ", 0x01c0 }, - { "VSCALER_CNTL2 ", 0x01c8 }, - { "VSYNC_DIFF_CNTL ", 0x03a0 }, - { "VSYNC_DIFF_LIMITS ", 0x03a4 }, - { "VSYNC_DIFF_RD_DATA ", 0x03a8 }, - { "VS_BLANKING_CNTL ", 0x0544 }, - { "VS_COUNTER_CNTL ", 0x054c }, - { "VS_DETECTOR_CNTL ", 0x0540 }, - { "VS_FIELD_ID_CNTL ", 0x0548 }, - { "VS_FRAME_TOTAL ", 0x0550 }, - { "VS_LINE_COUNT ", 0x0554 }, - { "VTOTAL ", 0x0094 }, - { "V_ACTIVE_WINDOW ", 0x05c4 }, - { "V_DEINTERLACE_CONTROL ", 0x0608 }, - { "V_SCALER_CONTROL ", 0x0604 }, - { "V_VBI_WINDOW ", 0x05cc }, - { "Y_FALL_CNTL ", 0x01cc }, - { "Y_RISE_CNTL ", 0x01d0 }, - { "Y_SAW_TOOTH_CNTL ", 0x01d4 }, - {NULL, 0} - }; - - for(i=0; rt_reg_list[i].name!=NULL;i++){ - RT_regr(rt_reg_list[i].addr, &data); - xf86DrvMsg(t->VIP->pScrn->scrnIndex, X_INFO, - "register (0x%04lx) %s is equal to 0x%08x\n", - rt_reg_list[i].addr, rt_reg_list[i].name, (unsigned)data); - } - -} - -_X_EXPORT void ResetTheatreRegsForNoTVout(TheatrePtr t) -{ - RT_regw(VIP_CLKOUT_CNTL, 0x0); - RT_regw(VIP_HCOUNT, 0x0); - RT_regw(VIP_VCOUNT, 0x0); - RT_regw(VIP_DFCOUNT, 0x0); - #if 0 - RT_regw(VIP_CLOCK_SEL_CNTL, 0x2b7); /* versus 0x237 <-> 0x2b7 */ - RT_regw(VIP_VIN_PLL_CNTL, 0x60a6039); - #endif - RT_regw(VIP_FRAME_LOCK_CNTL, 0x0); -} - - -_X_EXPORT void ResetTheatreRegsForTVout(TheatrePtr t) -{ -/* RT_regw(VIP_HW_DEBUG, 0x200); */ -/* RT_regw(VIP_INT_CNTL, 0x0); - RT_regw(VIP_GPIO_INOUT, 0x10090000); - RT_regw(VIP_GPIO_INOUT, 0x340b0000); */ -/* RT_regw(VIP_MASTER_CNTL, 0x6e8); */ - RT_regw(VIP_CLKOUT_CNTL, 0x29); -#if 1 - RT_regw(VIP_HCOUNT, 0x1d1); - RT_regw(VIP_VCOUNT, 0x1e3); -#else - RT_regw(VIP_HCOUNT, 0x322); - RT_regw(VIP_VCOUNT, 0x151); -#endif - RT_regw(VIP_DFCOUNT, 0x01); -/* RT_regw(VIP_CLOCK_SEL_CNTL, 0xb7); versus 0x237 <-> 0x2b7 */ - RT_regw(VIP_CLOCK_SEL_CNTL, 0x2b7); /* versus 0x237 <-> 0x2b7 */ - RT_regw(VIP_VIN_PLL_CNTL, 0x60a6039); -/* RT_regw(VIP_PLL_CNTL1, 0xacacac74); */ - RT_regw(VIP_FRAME_LOCK_CNTL, 0x0f); -/* RT_regw(VIP_ADC_CNTL, 0x02a420a8); - RT_regw(VIP_COMB_CNTL_0, 0x0d438083); - RT_regw(VIP_COMB_CNTL_2, 0x06080102); - RT_regw(VIP_HS_MINMAXWIDTH, 0x462f); - ... - */ -/* - RT_regw(VIP_HS_PULSE_WIDTH, 0x359); - RT_regw(VIP_HS_PLL_ERROR, 0xab6); - RT_regw(VIP_HS_PLL_FS_PATH, 0x7fff08f8); - RT_regw(VIP_VS_LINE_COUNT, 0x49b5e005); - */ -} - diff --git a/src/theatre200.h b/src/theatre200.h deleted file mode 100644 index 815bd916..00000000 --- a/src/theatre200.h +++ /dev/null @@ -1,140 +0,0 @@ -/************************************************************************************* - * Copyright (C) 2005 Bogdan D. bogdand@users.sourceforge.net - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this - * software and associated documentation files (the "Software"), to deal in the Software - * without restriction, including without limitation the rights to use, copy, modify, - * merge, publish, distribute, sublicense, and/or sell copies of the Software, - * and to permit persons to whom the Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, - * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE - * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of the author shall not be used in advertising or - * otherwise to promote the sale, use or other dealings in this Software without prior written - * authorization from the author. - * - * $Log$ - * Revision 1.5 2005/12/08 17:54:40 kem - * Allow hard-coded paths to be configurable. - * - * Revision 1.4 2005/11/07 19:28:40 bogdand - * Replaced the variadic macros(gcc) by macros according to C99 standard - * - * Revision 1.3 2005/08/28 18:00:23 bogdand - * Modified the licens type from GPL to a X/MIT one - * - * Revision 1.2 2005/07/01 22:43:11 daniels - * Change all misc.h and os.h references to <X11/foo.h>. - * - * - ************************************************************************************/ - -#ifndef __THEATRE200_H__ -#define __THEATRE200_H__ - -#include "theatre.h" - -#ifdef MICROC_DIR -#define DEFAULT_MICROC_PATH MICROC_DIR"/rt2_pmem.bin" -#else -#define DEFAULT_MICROC_PATH "/usr/X11R6/lib/modules/multimedia/rt2_pmem.bin" -#endif -#define DEFAULT_MICROC_TYPE "BINARY" - -/* #define ENABLE_DEBUG 1 */ - -#ifdef ENABLE_DEBUG -#define ERROR_0(str) xf86DrvMsg(screen, X_ERROR, str) -#define DEBUG_0(str) xf86DrvMsg(screen, X_INFO, str) -#define ERROR(str,param1) xf86DrvMsg(screen, X_ERROR, str, param1) -#define DEBUG(str,param1) xf86DrvMsg(screen, X_INFO, str, param1) -#define ERROR_2(str,param1,param2) xf86DrvMsg(screen, X_ERROR, str, param1, param2) -#define DEBUG_2(str,param1,param2) xf86DrvMsg(screen, X_INFO, str, param1, param2) -#define ERROR_3(str,param1,param2,param3) xf86DrvMsg(screen, X_ERROR, str, param1, param2, param3) -#define DEBUG_3(str,param1,param2,param3) xf86DrvMsg(screen, X_INFO, str, param1, param2, param3) -#else -#define ERROR_0(str) (void)screen -#define DEBUG_0(str) (void)screen -#define ERROR(str,param1) (void)screen -#define DEBUG(str,param1) (void)screen -#define ERROR_2(str,param1,param2) (void)screen -#define DEBUG_2(str,param1,param2) (void)screen -#define ERROR_3(str,param1,param2,param3) (void)screen -#define DEBUG_3(str,param1,param2,param3) (void)screen -#endif - - -#define DSP_OK 0x21 -#define DSP_INVALID_PARAMETER 0x22 -#define DSP_MISSING_PARAMETER 0x23 -#define DSP_UNKNOWN_COMMAND 0x24 -#define DSP_UNSUCCESS 0x25 -#define DSP_BUSY 0x26 -#define DSP_RESET_REQUIRED 0x27 -#define DSP_UNKNOWN_RESULT 0x28 -#define DSP_CRC_ERROR 0x29 -#define DSP_AUDIO_GAIN_ADJ_FAIL 0x2a -#define DSP_AUDIO_GAIN_CHK_ERROR 0x2b -#define DSP_WARNING 0x2c -#define DSP_POWERDOWN_MODE 0x2d - -#define RT200_NTSC_M 0x01 -#define RT200_NTSC_433 0x03 -#define RT200_NTSC_J 0x04 -#define RT200_PAL_B 0x05 -#define RT200_PAL_D 0x06 -#define RT200_PAL_G 0x07 -#define RT200_PAL_H 0x08 -#define RT200_PAL_I 0x09 -#define RT200_PAL_N 0x0a -#define RT200_PAL_Ncomb 0x0b -#define RT200_PAL_M 0x0c -#define RT200_PAL_60 0x0d -#define RT200_SECAM 0x0e -#define RT200_SECAM_B 0x0f -#define RT200_SECAM_D 0x10 -#define RT200_SECAM_G 0x11 -#define RT200_SECAM_H 0x12 -#define RT200_SECAM_K 0x13 -#define RT200_SECAM_K1 0x14 -#define RT200_SECAM_L 0x15 -#define RT200_SECAM_L1 0x16 -#define RT200_480i 0x17 -#define RT200_480p 0x18 -#define RT200_576i 0x19 -#define RT200_720p 0x1a -#define RT200_1080i 0x1b - -struct rt200_microc_head -{ - unsigned int device_id; - unsigned int vendor_id; - unsigned int revision_id; - unsigned int num_seg; -}; - -struct rt200_microc_seg -{ - unsigned int num_bytes; - unsigned int download_dst; - unsigned int crc_val; - - unsigned char* data; - struct rt200_microc_seg* next; -}; - - -struct rt200_microc_data -{ - struct rt200_microc_head microc_head; - struct rt200_microc_seg* microc_seg_list; -}; - -#endif diff --git a/src/theatre200_module.c b/src/theatre200_module.c deleted file mode 100644 index 7e7d3571..00000000 --- a/src/theatre200_module.c +++ /dev/null @@ -1,33 +0,0 @@ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include "xf86Module.h" - -static MODULESETUPPROTO(theatre200Setup); - - -static XF86ModuleVersionInfo theatre200VersRec = -{ - "theatre200", - MODULEVENDORSTRING, - MODINFOSTRING1, - MODINFOSTRING2, - XORG_VERSION_CURRENT, - 1, 0, 0, - ABI_CLASS_VIDEODRV, /* This needs the video driver ABI */ - ABI_VIDEODRV_VERSION, - MOD_CLASS_NONE, - {0,0,0,0} -}; - -_X_EXPORT XF86ModuleData theatre200ModuleData = { - &theatre200VersRec, - theatre200Setup, - NULL -}; - -static pointer -theatre200Setup(pointer module, pointer opts, int *errmaj, int *errmin) { - return (pointer)1; -} diff --git a/src/theatre_detect.c b/src/theatre_detect.c deleted file mode 100644 index 0d97cc8a..00000000 --- a/src/theatre_detect.c +++ /dev/null @@ -1,130 +0,0 @@ -/************************************************************************************* - * - * Copyright (C) 2005 Bogdan D. bogdand@users.sourceforge.net - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this - * software and associated documentation files (the "Software"), to deal in the Software - * without restriction, including without limitation the rights to use, copy, modify, - * merge, publish, distribute, sublicense, and/or sell copies of the Software, - * and to permit persons to whom the Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, - * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE - * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of the author shall not be used in advertising or - * otherwise to promote the sale, use or other dealings in this Software without prior written - * authorization from the author. - * - * $Log$ - * Revision 1.4 2005/08/28 18:00:23 bogdand - * Modified the licens type from GPL to a X/MIT one - * - * Revision 1.3 2005/07/11 02:29:45 ajax - * Prep for modular builds by adding guarded #include "config.h" everywhere. - * - * Revision 1.2 2005/07/01 22:43:11 daniels - * Change all misc.h and os.h references to <X11/foo.h>. - * - * - ************************************************************************************/ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include <string.h> -#include "xf86.h" -#include "generic_bus.h" -#include "theatre.h" -#include "theatre_reg.h" -#include "theatre_detect.h" - -static Bool theatre_read(TheatrePtr t,uint32_t reg, uint32_t *data) -{ - if(t->theatre_num<0)return FALSE; - return t->VIP->read(t->VIP, ((t->theatre_num & 0x3)<<14) | reg,4, (uint8_t *) data); -} - -/* Unused code - reference */ -#if 0 -static Bool theatre_write(TheatrePtr t,uint32_t reg, uint32_t data) -{ - if(t->theatre_num<0)return FALSE; - return t->VIP->write(t->VIP,((t->theatre_num & 0x03)<<14) | reg,4, (uint8_t *) &data); -} -#define RT_regw(reg,data) theatre_write(t,(reg),(data)) -#endif - -#define RT_regr(reg,data) theatre_read(t,(reg),(data)) -#define VIP_TYPE "ATI VIP BUS" - - -_X_EXPORT TheatrePtr DetectTheatre(GENERIC_BUS_Ptr b) -{ - TheatrePtr t; - int i; - uint32_t val; - char s[20]; - - b->ioctl(b,GB_IOCTL_GET_TYPE,20,s); - if(strcmp(VIP_TYPE, s)){ - xf86DrvMsg(b->pScrn->scrnIndex, X_ERROR, "DetectTheatre must be called with bus of type \"%s\", not \"%s\"\n", - VIP_TYPE, s); - return NULL; - } - - t = calloc(1,sizeof(TheatreRec)); - t->VIP = b; - t->theatre_num = -1; - t->mode=MODE_UNINITIALIZED; - - b->read(b, VIP_VIP_VENDOR_DEVICE_ID, 4, (uint8_t *)&val); - for(i=0;i<4;i++) - { - if(b->read(b, ((i & 0x03)<<14) | VIP_VIP_VENDOR_DEVICE_ID, 4, (uint8_t *)&val)) - { - if(val)xf86DrvMsg(b->pScrn->scrnIndex, X_INFO, - "Device %d on VIP bus ids as 0x%08x\n", i, - (unsigned)val); - if(t->theatre_num>=0)continue; /* already found one instance */ - switch(val){ - case RT100_ATI_ID: - t->theatre_num=i; - t->theatre_id=RT100_ATI_ID; - break; - case RT200_ATI_ID: - t->theatre_num=i; - t->theatre_id=RT200_ATI_ID; - break; - } - } else { - xf86DrvMsg(b->pScrn->scrnIndex, X_INFO, "No response from device %d on VIP bus\n",i); - } - } - if(t->theatre_num>=0)xf86DrvMsg(b->pScrn->scrnIndex, X_INFO, - "Detected Rage Theatre as device %d on VIP bus with id 0x%08x\n", - t->theatre_num, (unsigned)t->theatre_id); - - if(t->theatre_num < 0) - { - free(t); - return NULL; - } - - RT_regr(VIP_VIP_REVISION_ID, &val); - xf86DrvMsg(b->pScrn->scrnIndex, X_INFO, "Detected Rage Theatre revision %8.8X\n", - (unsigned)val); - -#if 0 -DumpRageTheatreRegsByName(t); -#endif - - return t; -} - diff --git a/src/theatre_detect.h b/src/theatre_detect.h deleted file mode 100644 index 53d8d119..00000000 --- a/src/theatre_detect.h +++ /dev/null @@ -1,46 +0,0 @@ -/************************************************************************************* - * Copyright (C) 2005 Bogdan D. bogdand@users.sourceforge.net - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of this - * software and associated documentation files (the "Software"), to deal in the Software - * without restriction, including without limitation the rights to use, copy, modify, - * merge, publish, distribute, sublicense, and/or sell copies of the Software, - * and to permit persons to whom the Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, - * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE - * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of the author shall not be used in advertising or - * otherwise to promote the sale, use or other dealings in this Software without prior written - * authorization from the author. - * - * $Log$ - * Revision 1.3 2005/08/28 18:00:23 bogdand - * Modified the licens type from GPL to a X/MIT one - * - * Revision 1.2 2005/07/01 22:43:11 daniels - * Change all misc.h and os.h references to <X11/foo.h>. - * - * - ************************************************************************************/ - -#ifndef __THEATRE_DETECT_H__ -#define __THEATRE_DETECT_H__ - -/* - * Created by Bogdan D. bogdand@users.sourceforge.net - */ - - -#define xf86_DetectTheatre DetectTheatre -_X_EXPORT TheatrePtr DetectTheatre(GENERIC_BUS_Ptr b); - - - -#endif diff --git a/src/theatre_detect_module.c b/src/theatre_detect_module.c deleted file mode 100644 index 1546ce21..00000000 --- a/src/theatre_detect_module.c +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Created by Bogdan D. bogdand@users.sourceforge.net - */ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include "xf86Module.h" - -static MODULESETUPPROTO(theatre_detectSetup); - - -static XF86ModuleVersionInfo theatre_detectVersRec = -{ - "theatre_detect", - MODULEVENDORSTRING, - MODINFOSTRING1, - MODINFOSTRING2, - XORG_VERSION_CURRENT, - 1, 0, 0, - ABI_CLASS_VIDEODRV, /* This needs the video driver ABI */ - ABI_VIDEODRV_VERSION, - MOD_CLASS_NONE, - {0,0,0,0} -}; - -_X_EXPORT XF86ModuleData theatre_detectModuleData = { - &theatre_detectVersRec, - theatre_detectSetup, - NULL -}; - -static pointer -theatre_detectSetup(pointer module, pointer opts, int *errmaj, int *errmin) { - return (pointer)1; -} diff --git a/src/theatre_module.c b/src/theatre_module.c deleted file mode 100644 index 608b3560..00000000 --- a/src/theatre_module.c +++ /dev/null @@ -1,33 +0,0 @@ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include "xf86Module.h" - -static MODULESETUPPROTO(theatreSetup); - - -static XF86ModuleVersionInfo theatreVersRec = -{ - "theatre", - MODULEVENDORSTRING, - MODINFOSTRING1, - MODINFOSTRING2, - XORG_VERSION_CURRENT, - 1, 0, 0, - ABI_CLASS_VIDEODRV, /* This needs the video driver ABI */ - ABI_VIDEODRV_VERSION, - MOD_CLASS_NONE, - {0,0,0,0} -}; - -_X_EXPORT XF86ModuleData theatreModuleData = { - &theatreVersRec, - theatreSetup, - NULL -}; - -static pointer -theatreSetup(pointer module, pointer opts, int *errmaj, int *errmin) { - return (pointer)1; -} diff --git a/src/theatre_reg.h b/src/theatre_reg.h deleted file mode 100644 index 30fafe77..00000000 --- a/src/theatre_reg.h +++ /dev/null @@ -1,876 +0,0 @@ -#ifndef __THEATRE_REGS_H__ -#define __THEATRE_REGS_H__ - - -#define VIPH_CH0_DATA 0x0c00 -#define VIPH_CH1_DATA 0x0c04 -#define VIPH_CH2_DATA 0x0c08 -#define VIPH_CH3_DATA 0x0c0c -#define VIPH_CH0_ADDR 0x0c10 -#define VIPH_CH1_ADDR 0x0c14 -#define VIPH_CH2_ADDR 0x0c18 -#define VIPH_CH3_ADDR 0x0c1c -#define VIPH_CH0_SBCNT 0x0c20 -#define VIPH_CH1_SBCNT 0x0c24 -#define VIPH_CH2_SBCNT 0x0c28 -#define VIPH_CH3_SBCNT 0x0c2c -#define VIPH_CH0_ABCNT 0x0c30 -#define VIPH_CH1_ABCNT 0x0c34 -#define VIPH_CH2_ABCNT 0x0c38 -#define VIPH_CH3_ABCNT 0x0c3c -#define VIPH_CONTROL 0x0c40 -#define VIPH_DV_LAT 0x0c44 -#define VIPH_BM_CHUNK 0x0c48 -#define VIPH_DV_INT 0x0c4c -#define VIPH_TIMEOUT_STAT 0x0c50 - -#define VIPH_REG_DATA 0x0084 -#define VIPH_REG_ADDR 0x0080 - -/* Address Space Rage Theatre Registers (VIP Access) */ -#define VIP_VIP_VENDOR_DEVICE_ID 0x0000 -#define VIP_VIP_SUB_VENDOR_DEVICE_ID 0x0004 -#define VIP_VIP_COMMAND_STATUS 0x0008 -#define VIP_VIP_REVISION_ID 0x000c -#define VIP_HW_DEBUG 0x0010 -#define VIP_SW_SCRATCH 0x0014 -#define VIP_I2C_CNTL_0 0x0020 -#define VIP_I2C_CNTL_1 0x0024 -#define VIP_I2C_DATA 0x0028 -#define VIP_INT_CNTL 0x002c -/* RT200 */ -#define VIP_INT_CNTL__FB_INT0 0x02000000 -#define VIP_INT_CNTL__FB_INT0_CLR 0x02000000 -#define VIP_GPIO_INOUT 0x0030 -#define VIP_GPIO_CNTL 0x0034 -#define VIP_CLKOUT_GPIO_CNTL 0x0038 -#define VIP_RIPINTF_PORT_CNTL 0x003c - -/* RT200 */ -#define VIP_GPIO_INOUT 0x0030 -#define VIP_GPIO_CNTL 0x0034 -#define VIP_HOSTINTF_PORT_CNTL 0x003c -#define VIP_HOSTINTF_PORT_CNTL__HAD_HCTL_SDA_SN 0x00000008 -#define VIP_HOSTINTF_PORT_CNTL__HAD_HCTL_SDA_SP 0x00000080 -#define VIP_HOSTINTF_PORT_CNTL__HAD_HCTL_SDA_SR 0x00000100 -#define VIP_HOSTINTF_PORT_CNTL__SUB_SYS_ID_EN 0x00010000 -#define VIP_HOSTINTF_PORT_CNTL__FIFO_RW_MODE 0x00300000 -#define VIP_HOSTINTF_PORT_CNTL__FIFOA_ENDIAN_SWAP 0x00c00000 -#define VIP_HOSTINTF_PORT_CNTL__FIFOB_ENDIAN_SWAP 0x03000000 -#define VIP_HOSTINTF_PORT_CNTL__FIFOC_ENDIAN_SWAP 0x0c000000 -#define VIP_HOSTINTF_PORT_CNTL__FIFOD_ENDIAN_SWAP 0x30000000 -#define VIP_HOSTINTF_PORT_CNTL__FIFOE_ENDIAN_SWAP 0xc0000000 - -/* RT200 */ -#define VIP_DSP_PLL_CNTL 0x0bc - -/* RT200 */ -#define VIP_TC_SOURCE 0x300 -#define VIP_TC_DESTINATION 0x304 -#define VIP_TC_COMMAND 0x308 - -/* RT200 */ -#define VIP_TC_STATUS 0x030c -#define VIP_TC_STATUS__TC_CHAN_BUSY 0x00007fff -#define VIP_TC_STATUS__TC_WRITE_PENDING 0x00008000 -#define VIP_TC_STATUS__TC_FIFO_4_EMPTY 0x00040000 -#define VIP_TC_STATUS__TC_FIFO_6_EMPTY 0x00080000 -#define VIP_TC_STATUS__TC_FIFO_8_EMPTY 0x00100000 -#define VIP_TC_STATUS__TC_FIFO_10_EMPTY 0x00200000 -#define VIP_TC_STATUS__TC_FIFO_4_FULL 0x04000000 -#define VIP_TC_STATUS__TC_FIFO_6_FULL 0x08080000 -#define VIP_TC_STATUS__TC_FIFO_8_FULL 0x10080000 -#define VIP_TC_STATUS__TC_FIFO_10_FULL 0x20080000 -#define VIP_TC_STATUS__DSP_ILLEGAL_OP 0x80080000 - -/* RT200 */ -#define VIP_TC_DOWNLOAD 0x0310 -#define VIP_TC_DOWNLOAD__TC_DONE_MASK 0x00003fff -#define VIP_TC_DOWNLOAD__TC_RESET_MODE 0x00060000 - -/* RT200 */ -#define VIP_FB_INT 0x0314 -#define VIP_FB_INT__INT_7 0x00000080 -#define VIP_FB_SCRATCH0 0x0318 -#define VIP_FB_SCRATCH1 0x031c - -#define VIP_ADC_CNTL 0x0400 -#define VIP_ADC_DEBUG 0x0404 -#define VIP_STANDARD_SELECT 0x0408 -#define VIP_THERMO2BIN_STATUS 0x040c -#define VIP_COMB_CNTL0 0x0440 -#define VIP_COMB_CNTL1 0x0444 -#define VIP_COMB_CNTL2 0x0448 -#define VIP_COMB_LINE_LENGTH 0x044c -#define VIP_NOISE_CNTL0 0x0450 -#define VIP_HS_PLINE 0x0480 -#define VIP_HS_DTOINC 0x0484 -#define VIP_HS_PLLGAIN 0x0488 -#define VIP_HS_MINMAXWIDTH 0x048c -#define VIP_HS_GENLOCKDELAY 0x0490 -#define VIP_HS_WINDOW_LIMIT 0x0494 -#define VIP_HS_WINDOW_OC_SPEED 0x0498 -#define VIP_HS_PULSE_WIDTH 0x049c -#define VIP_HS_PLL_ERROR 0x04a0 -#define VIP_HS_PLL_FS_PATH 0x04a4 -#define VIP_SG_BLACK_GATE 0x04c0 -#define VIP_SG_SYNCTIP_GATE 0x04c4 -#define VIP_SG_UVGATE_GATE 0x04c8 -#define VIP_LP_AGC_CLAMP_CNTL0 0x0500 -#define VIP_LP_AGC_CLAMP_CNTL1 0x0504 -#define VIP_LP_BRIGHTNESS 0x0508 -#define VIP_LP_CONTRAST 0x050c -#define VIP_LP_SLICE_LIMIT 0x0510 -#define VIP_LP_WPA_CNTL0 0x0514 -#define VIP_LP_WPA_CNTL1 0x0518 -#define VIP_LP_BLACK_LEVEL 0x051c -#define VIP_LP_SLICE_LEVEL 0x0520 -#define VIP_LP_SYNCTIP_LEVEL 0x0524 -#define VIP_LP_VERT_LOCKOUT 0x0528 -#define VIP_VS_DETECTOR_CNTL 0x0540 -#define VIP_VS_BLANKING_CNTL 0x0544 -#define VIP_VS_FIELD_ID_CNTL 0x0548 -#define VIP_VS_COUNTER_CNTL 0x054c -#define VIP_VS_FRAME_TOTAL 0x0550 -#define VIP_VS_LINE_COUNT 0x0554 -#define VIP_CP_PLL_CNTL0 0x0580 -#define VIP_CP_PLL_CNTL1 0x0584 -#define VIP_CP_HUE_CNTL 0x0588 -#define VIP_CP_BURST_GAIN 0x058c -#define VIP_CP_AGC_CNTL 0x0590 -#define VIP_CP_ACTIVE_GAIN 0x0594 -#define VIP_CP_PLL_STATUS0 0x0598 -#define VIP_CP_PLL_STATUS1 0x059c -#define VIP_CP_PLL_STATUS2 0x05a0 -#define VIP_CP_PLL_STATUS3 0x05a4 -#define VIP_CP_PLL_STATUS4 0x05a8 -#define VIP_CP_PLL_STATUS5 0x05ac -#define VIP_CP_PLL_STATUS6 0x05b0 -#define VIP_CP_PLL_STATUS7 0x05b4 -#define VIP_CP_DEBUG_FORCE 0x05b8 -#define VIP_CP_VERT_LOCKOUT 0x05bc -#define VIP_H_ACTIVE_WINDOW 0x05c0 -#define VIP_V_ACTIVE_WINDOW 0x05c4 -#define VIP_H_VBI_WINDOW 0x05c8 -#define VIP_V_VBI_WINDOW 0x05cc -#define VIP_VBI_CONTROL 0x05d0 -#define VIP_DECODER_DEBUG_CNTL 0x05d4 -#define VIP_SINGLE_STEP_DATA 0x05d8 -#define VIP_MASTER_CNTL 0x0040 -#define VIP_RGB_CNTL 0x0048 -#define VIP_CLKOUT_CNTL 0x004c -#define VIP_SYNC_CNTL 0x0050 -#define VIP_I2C_CNTL 0x0054 -#define VIP_HTOTAL 0x0080 -#define VIP_HDISP 0x0084 -#define VIP_HSIZE 0x0088 -#define VIP_HSTART 0x008c -#define VIP_HCOUNT 0x0090 -#define VIP_VTOTAL 0x0094 -#define VIP_VDISP 0x0098 -#define VIP_VCOUNT 0x009c -#define VIP_VFTOTAL 0x00a0 -#define VIP_DFCOUNT 0x00a4 -#define VIP_DFRESTART 0x00a8 -#define VIP_DHRESTART 0x00ac -#define VIP_DVRESTART 0x00b0 -#define VIP_SYNC_SIZE 0x00b4 -#define VIP_TV_PLL_FINE_CNTL 0x00b8 -#define VIP_CRT_PLL_FINE_CNTL 0x00bc -#define VIP_TV_PLL_CNTL 0x00c0 -#define VIP_CRT_PLL_CNTL 0x00c4 -#define VIP_PLL_CNTL0 0x00c8 -#define VIP_PLL_TEST_CNTL 0x00cc -#define VIP_CLOCK_SEL_CNTL 0x00d0 -#define VIP_VIN_PLL_CNTL 0x00d4 -#define VIP_VIN_PLL_FINE_CNTL 0x00d8 -#define VIP_AUD_PLL_CNTL 0x00e0 -#define VIP_AUD_PLL_FINE_CNTL 0x00e4 -#define VIP_AUD_CLK_DIVIDERS 0x00e8 -#define VIP_AUD_DTO_INCREMENTS 0x00ec -#define VIP_L54_PLL_CNTL 0x00f0 -#define VIP_L54_PLL_FINE_CNTL 0x00f4 -#define VIP_L54_DTO_INCREMENTS 0x00f8 -#define VIP_PLL_CNTL1 0x00fc -#define VIP_FRAME_LOCK_CNTL 0x0100 -#define VIP_SYNC_LOCK_CNTL 0x0104 -#define VIP_TVO_SYNC_PAT_ACCUM 0x0108 -#define VIP_TVO_SYNC_THRESHOLD 0x010c -#define VIP_TVO_SYNC_PAT_EXPECT 0x0110 -#define VIP_DELAY_ONE_MAP_A 0x0114 -#define VIP_DELAY_ONE_MAP_B 0x0118 -#define VIP_DELAY_ZERO_MAP_A 0x011c -#define VIP_DELAY_ZERO_MAP_B 0x0120 -#define VIP_TVO_DATA_DELAY_A 0x0140 -#define VIP_TVO_DATA_DELAY_B 0x0144 -#define VIP_HOST_READ_DATA 0x0180 -#define VIP_HOST_WRITE_DATA 0x0184 -#define VIP_HOST_RD_WT_CNTL 0x0188 -#define VIP_VSCALER_CNTL1 0x01c0 -#define VIP_TIMING_CNTL 0x01c4 -#define VIP_VSCALER_CNTL2 0x01c8 -#define VIP_Y_FALL_CNTL 0x01cc -#define VIP_Y_RISE_CNTL 0x01d0 -#define VIP_Y_SAW_TOOTH_CNTL 0x01d4 -#define VIP_UPSAMP_AND_GAIN_CNTL 0x01e0 -#define VIP_GAIN_LIMIT_SETTINGS 0x01e4 -#define VIP_LINEAR_GAIN_SETTINGS 0x01e8 -#define VIP_MODULATOR_CNTL1 0x0200 -#define VIP_MODULATOR_CNTL2 0x0204 -#define VIP_MV_MODE_CNTL 0x0208 -#define VIP_MV_STRIPE_CNTL 0x020c -#define VIP_MV_LEVEL_CNTL1 0x0210 -#define VIP_MV_LEVEL_CNTL2 0x0214 -#define VIP_PRE_DAC_MUX_CNTL 0x0240 -#define VIP_TV_DAC_CNTL 0x0280 -#define VIP_CRC_CNTL 0x02c0 -#define VIP_VIDEO_PORT_SIG 0x02c4 -#define VIP_VBI_CC_CNTL 0x02c8 -#define VIP_VBI_EDS_CNTL 0x02cc -#define VIP_VBI_20BIT_CNTL 0x02d0 -#define VIP_VBI_DTO_CNTL 0x02d4 -#define VIP_VBI_LEVEL_CNTL 0x02d8 -#define VIP_UV_ADR 0x0300 -#define VIP_MV_STATUS 0x0330 -#define VIP_UPSAMP_COEFF0_0 0x0340 -#define VIP_UPSAMP_COEFF0_1 0x0344 -#define VIP_UPSAMP_COEFF0_2 0x0348 -#define VIP_UPSAMP_COEFF1_0 0x034c -#define VIP_UPSAMP_COEFF1_1 0x0350 -#define VIP_UPSAMP_COEFF1_2 0x0354 -#define VIP_UPSAMP_COEFF2_0 0x0358 -#define VIP_UPSAMP_COEFF2_1 0x035c -#define VIP_UPSAMP_COEFF2_2 0x0360 -#define VIP_UPSAMP_COEFF3_0 0x0364 -#define VIP_UPSAMP_COEFF3_1 0x0368 -#define VIP_UPSAMP_COEFF3_2 0x036c -#define VIP_UPSAMP_COEFF4_0 0x0370 -#define VIP_UPSAMP_COEFF4_1 0x0374 -#define VIP_UPSAMP_COEFF4_2 0x0378 -#define VIP_TV_DTO_INCREMENTS 0x0390 -#define VIP_CRT_DTO_INCREMENTS 0x0394 -#define VIP_VSYNC_DIFF_CNTL 0x03a0 -#define VIP_VSYNC_DIFF_LIMITS 0x03a4 -#define VIP_VSYNC_DIFF_RD_DATA 0x03a8 -#define VIP_SCALER_IN_WINDOW 0x0618 -#define VIP_SCALER_OUT_WINDOW 0x061c -#define VIP_H_SCALER_CONTROL 0x0600 -#define VIP_V_SCALER_CONTROL 0x0604 -#define VIP_V_DEINTERLACE_CONTROL 0x0608 -#define VIP_VBI_SCALER_CONTROL 0x060c -#define VIP_DVS_PORT_CTRL 0x0610 -#define VIP_DVS_PORT_READBACK 0x0614 -#define VIP_FIFOA_CONFIG 0x0800 -#define VIP_FIFOB_CONFIG 0x0804 -#define VIP_FIFOC_CONFIG 0x0808 -#define VIP_SPDIF_PORT_CNTL 0x080c -#define VIP_SPDIF_CHANNEL_STAT 0x0810 -#define VIP_SPDIF_AC3_PREAMBLE 0x0814 -#define VIP_I2S_TRANSMIT_CNTL 0x0818 -#define VIP_I2S_RECEIVE_CNTL 0x081c -#define VIP_SPDIF_TX_CNT_REG 0x0820 -#define VIP_IIS_TX_CNT_REG 0x0824 - -/* Status defines */ -#define VIP_BUSY 0 -#define VIP_IDLE 1 -#define VIP_RESET 2 - -#define VIPH_TIMEOUT_STAT__VIPH_FIFO0_STAT 0x00000001 -#define VIPH_TIMEOUT_STAT__VIPH_FIFO0_AK 0x00000001 -#define VIPH_TIMEOUT_STAT__VIPH_FIFO1_STAT 0x00000002 -#define VIPH_TIMEOUT_STAT__VIPH_FIFO1_AK 0x00000002 -#define VIPH_TIMEOUT_STAT__VIPH_FIFO2_STAT 0x00000004 -#define VIPH_TIMEOUT_STAT__VIPH_FIFO2_AK 0x00000004 -#define VIPH_TIMEOUT_STAT__VIPH_FIFO3_STAT 0x00000008 -#define VIPH_TIMEOUT_STAT__VIPH_FIFO3_AK 0x00000008 - -#define VIPH_TIMEOUT_STAT__VIPH_REG_STAT 0x00000010 -#define VIPH_TIMEOUT_STAT__VIPH_REG_AK 0x00000010 -#define VIPH_TIMEOUT_STAT__VIPH_REGR_DIS 0x01000000 -#define TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN 0x00000001 - -#define RT100_ATI_ID 0x4D541002 -#define RT200_ATI_ID 0x4d4a1002 - -/* Register/Field values: */ -#define RT_COMP0 0x0 -#define RT_COMP1 0x1 -#define RT_COMP2 0x2 -#define RT_YF_COMP3 0x3 -#define RT_YR_COMP3 0x4 -#define RT_YCF_COMP4 0x5 -#define RT_YCR_COMP4 0x6 - -/* Video standard defines */ -#define RT_NTSC 0x0 -#define RT_PAL 0x1 -#define RT_SECAM 0x2 -#define extNONE 0x0000 -#define extNTSC 0x0100 -#define extRsvd 0x0200 -#define extPAL 0x0300 -#define extPAL_M 0x0400 -#define extPAL_N 0x0500 -#define extSECAM 0x0600 -#define extPAL_NCOMB 0x0700 -#define extNTSC_J 0x0800 -#define extNTSC_443 0x0900 -#define extPAL_BGHI 0x0A00 -#define extPAL_60 0x0B00 - /* these are used in MSP3430 */ -#define extPAL_DK1 0x0C00 -#define extPAL_AUTO 0x0D00 - /* these are used in RT200. Some are defined above */ -#define extPAL_B 0x0E00 -#define extPAL_D 0x0F00 -#define extPAL_G 0x1000 -#define extPAL_H 0x1100 -#define extPAL_I 0x1200 -#define extSECAM_B 0x1300 -#define extSECAM_D 0x1400 -#define extSECAM_G 0x1500 -#define extSECAM_H 0x1600 -#define extSECAM_K 0x1700 -#define extSECAM_K1 0x1800 -#define extSECAM_L 0x1900 -#define extSECAM_L1 0x1A00 - -#define RT_FREF_2700 6 -#define RT_FREF_2950 5 - -#define RT_COMPOSITE 0x0 -#define RT_SVIDEO 0x1 - -#define RT_NORM_SHARPNESS 0x03 -#define RT_HIGH_SHARPNESS 0x0F - -#define RT_HUE_PAL_DEF 0x00 - -#define RT_DECINTERLACED 0x1 -#define RT_DECNONINTERLACED 0x0 - -#define NTSC_LINES 525 -#define PAL_SECAM_LINES 625 - -#define RT_ASYNC_ENABLE 0x0 -#define RT_ASYNC_DISABLE 0x1 -#define RT_ASYNC_RESET 0x1 - -#define RT_VINRST_ACTIVE 0x0 -#define RT_VINRST_RESET 0x1 -#define RT_L54RST_RESET 0x1 - -#define RT_REF_CLK 0x0 -#define RT_PLL_VIN_CLK 0x1 - -#define RT_VIN_ASYNC_RST 0x20 -#define RT_DVS_ASYNC_RST 0x80 - -#define RT_ADC_ENABLE 0x0 -#define RT_ADC_DISABLE 0x1 - -#define RT_DVSDIR_IN 0x0 -#define RT_DVSDIR_OUT 0x1 - -#define RT_DVSCLK_HIGH 0x0 -#define RT_DVSCLK_LOW 0x1 - -#define RT_DVSCLK_SEL_8FS 0x0 -#define RT_DVSCLK_SEL_27MHZ 0x1 - -#define RT_DVS_CONTSTREAM 0x1 -#define RT_DVS_NONCONTSTREAM 0x0 - -#define RT_DVSDAT_HIGH 0x0 -#define RT_DVSDAT_LOW 0x1 - -#define RT_ADC_CNTL_DEFAULT 0x03252338 - -/* COMB_CNTL0 FILTER SETTINGS FOR DIFFERENT STANDARDS: */ -#define RT_NTSCM_COMB_CNTL0_COMPOSITE 0x09438090 /* was 0x09438090 */ -#define RT_NTSCM_COMB_CNTL0_SVIDEO 0x48540000 - -#define RT_PAL_COMB_CNTL0_COMPOSITE 0x09438090 -#define RT_PAL_COMB_CNTL0_SVIDEO 0x40348090 - -#define RT_SECAM_COMB_CNTL0_COMPOSITE 0xD0108090 /* instead of orig 0xD0088090 - eric*/ -#define RT_SECAM_COMB_CNTL0_SVIDEO 0x50148090 - -#define RT_PALN_COMB_CNTL0_COMPOSITE 0x09438090 -#define RT_PALN_COMB_CNTL0_SVIDEO 0x40348090 - -#define RT_PALM_COMB_CNTL0_COMPOSITE 0x09438090 -#define RT_PALM_COMB_CNTL0_SVIDEO 0x40348090 -/* End of filter settings. */ - -/* COMB_CNTL1 FILTER SETTINGS FOR DIFFERENT STANDARDS: */ -#define RT_NTSCM_COMB_CNTL1_COMPOSITE 0x00000010 -#define RT_NTSCM_COMB_CNTL1_SVIDEO 0x00000081 - -#define RT_PAL_COMB_CNTL1_COMPOSITE 0x00000010 -#define RT_PAL_COMB_CNTL1_SVIDEO 0x000000A1 - -#define RT_SECAM_COMB_CNTL1_COMPOSITE 0x00000091 -#define RT_SECAM_COMB_CNTL1_SVIDEO 0x00000081 - -#define RT_PALN_COMB_CNTL1_COMPOSITE 0x00000010 -#define RT_PALN_COMB_CNTL1_SVIDEO 0x000000A1 - -#define RT_PALM_COMB_CNTL1_COMPOSITE 0x00000010 -#define RT_PALM_COMB_CNTL1_SVIDEO 0x000000A1 -/* End of filter settings. */ - -/* COMB_CNTL2 FILTER SETTINGS FOR DIFFERENT STANDARDS: */ -#define RT_NTSCM_COMB_CNTL2_COMPOSITE 0x16161010 -#define RT_NTSCM_COMB_CNTL2_SVIDEO 0xFFFFFFFF - -#define RT_PAL_COMB_CNTL2_COMPOSITE 0x06080102 /* instead of 0x16161010 - Ivo */ -#define RT_PAL_COMB_CNTL2_SVIDEO 0x06080102 - -#define RT_SECAM_COMB_CNTL2_COMPOSITE 0xffffffff /* instead of 0x06080102 - eric */ -#define RT_SECAM_COMB_CNTL2_SVIDEO 0x06080102 - -#define RT_PALN_COMB_CNTL2_COMPOSITE 0x06080102 -#define RT_PALN_COMB_CNTL2_SVIDEO 0x06080102 - -#define RT_PALM_COMB_CNTL2_COMPOSITE 0x06080102 -#define RT_PALM_COMB_CNTL2_SVIDEO 0x06080102 -/* End of filter settings. */ - -/* COMB_LINE_LENGTH FILTER SETTINGS FOR DIFFERENT STANDARDS: */ -#define RT_NTSCM_COMB_LENGTH_COMPOSITE 0x0718038A -#define RT_NTSCM_COMB_LENGTH_SVIDEO 0x0718038A - -#define RT_PAL_COMB_LENGTH_COMPOSITE 0x08DA046B -#define RT_PAL_COMB_LENGTH_SVIDEO 0x08DA046B - -#define RT_SECAM_COMB_LENGTH_COMPOSITE 0x08DA046A -#define RT_SECAM_COMB_LENGTH_SVIDEO 0x08DA046A - -#define RT_PALN_COMB_LENGTH_COMPOSITE 0x07260391 -#define RT_PALN_COMB_LENGTH_SVIDEO 0x07260391 - -#define RT_PALM_COMB_LENGTH_COMPOSITE 0x07160389 -#define RT_PALM_COMB_LENGTH_SVIDEO 0x07160389 -/* End of filter settings. */ - -/* LP_AGC_CLAMP_CNTL0 */ -#define RT_NTSCM_SYNCTIP_REF0 0x00000037 -#define RT_NTSCM_SYNCTIP_REF1 0x00000029 -#define RT_NTSCM_CLAMP_REF 0x0000003B -#define RT_NTSCM_PEAKWHITE 0x000000FF -#define RT_NTSCM_VBI_PEAKWHITE 0x000000D2 /* was 0xc2 - docs say d2 */ - -#define RT_NTSCM_WPA_THRESHOLD 0x00000406 -#define RT_NTSCM_WPA_TRIGGER_LO 0x000000B3 - -#define RT_NTSCM_WPA_TRIGGER_HIGH 0x0000021B - -#define RT_NTSCM_LP_LOCKOUT_START 0x00000206 -#define RT_NTSCM_LP_LOCKOUT_END 0x00000021 -#define RT_NTSCM_CH_DTO_INC 0x00400000 -#define RT_NTSCM_CH_PLL_SGAIN 0x00000001 -#define RT_NTSCM_CH_PLL_FGAIN 0x00000002 - -#define RT_NTSCM_CR_BURST_GAIN 0x0000007A -#define RT_NTSCM_CB_BURST_GAIN 0x000000AC - -#define RT_NTSCM_CH_HEIGHT 0x000000CD -#define RT_NTSCM_CH_KILL_LEVEL 0x000000C0 -#define RT_NTSCM_CH_AGC_ERROR_LIM 0x00000002 -#define RT_NTSCM_CH_AGC_FILTER_EN 0x00000000 -#define RT_NTSCM_CH_AGC_LOOP_SPEED 0x00000000 - -#define RT_NTSCM_CRDR_ACTIVE_GAIN 0x0000007A -#define RT_NTSCM_CBDB_ACTIVE_GAIN 0x000000AC - -#define RT_NTSCM_VERT_LOCKOUT_START 0x00000207 -#define RT_NTSCM_VERT_LOCKOUT_END 0x0000000E - -#define RT_NTSCJ_SYNCTIP_REF0 0x00000004 -#define RT_NTSCJ_SYNCTIP_REF1 0x00000012 -#define RT_NTSCJ_CLAMP_REF 0x0000003B -#define RT_NTSCJ_PEAKWHITE 0x000000CB -#define RT_NTSCJ_VBI_PEAKWHITE 0x000000C2 -#define RT_NTSCJ_WPA_THRESHOLD 0x000004B0 -#define RT_NTSCJ_WPA_TRIGGER_LO 0x000000B4 -#define RT_NTSCJ_WPA_TRIGGER_HIGH 0x0000021C -#define RT_NTSCJ_LP_LOCKOUT_START 0x00000206 -#define RT_NTSCJ_LP_LOCKOUT_END 0x00000021 - -#define RT_NTSCJ_CR_BURST_GAIN 0x00000071 -#define RT_NTSCJ_CB_BURST_GAIN 0x0000009F -#define RT_NTSCJ_CH_HEIGHT 0x000000CD -#define RT_NTSCJ_CH_KILL_LEVEL 0x000000C0 -#define RT_NTSCJ_CH_AGC_ERROR_LIM 0x00000002 -#define RT_NTSCJ_CH_AGC_FILTER_EN 0x00000000 -#define RT_NTSCJ_CH_AGC_LOOP_SPEED 0x00000000 - -#define RT_NTSCJ_CRDR_ACTIVE_GAIN 0x00000071 -#define RT_NTSCJ_CBDB_ACTIVE_GAIN 0x0000009F -#define RT_NTSCJ_VERT_LOCKOUT_START 0x00000207 -#define RT_NTSCJ_VERT_LOCKOUT_END 0x0000000E - -#define RT_PAL_SYNCTIP_REF0 0x37 /* instead of 0x00000004 - Ivo */ -#define RT_PAL_SYNCTIP_REF1 0x26 /* instead of 0x0000000F - Ivo */ -#define RT_PAL_CLAMP_REF 0x0000003B -#define RT_PAL_PEAKWHITE 0xFF /* instead of 0x000000C1 - Ivo */ -#define RT_PAL_VBI_PEAKWHITE 0xC6 /* instead of 0x000000C7 - Ivo */ -#define RT_PAL_WPA_THRESHOLD 0x59C /* instead of 0x000006A4 - Ivo */ - -#define RT_PAL_WPA_TRIGGER_LO 0x00000096 -#define RT_PAL_WPA_TRIGGER_HIGH 0x000001C2 -#define RT_PAL_LP_LOCKOUT_START 0x00000263 -#define RT_PAL_LP_LOCKOUT_END 0x0000002C - -#define RT_PAL_CH_DTO_INC 0x00400000 -#define RT_PAL_CH_PLL_SGAIN 1 /* instead of 0x00000002 - Ivo */ -#define RT_PAL_CH_PLL_FGAIN 2 /* instead of 0x00000001 - Ivo */ -#define RT_PAL_CR_BURST_GAIN 0x0000007A -#define RT_PAL_CB_BURST_GAIN 0x000000AB -#define RT_PAL_CH_HEIGHT 0x0000009C -#define RT_PAL_CH_KILL_LEVEL 4 /* instead of 0x00000090 - Ivo */ -#define RT_PAL_CH_AGC_ERROR_LIM 1 /* instead of 0x00000002 - Ivo */ -#define RT_PAL_CH_AGC_FILTER_EN 1 /* instead of 0x00000000 - Ivo */ -#define RT_PAL_CH_AGC_LOOP_SPEED 0x00000000 - -#define RT_PAL_CRDR_ACTIVE_GAIN 0x9E /* instead of 0x0000007A - Ivo */ -#define RT_PAL_CBDB_ACTIVE_GAIN 0xDF /* instead of 0x000000AB - Ivo */ -#define RT_PAL_VERT_LOCKOUT_START 0x00000269 -#define RT_PAL_VERT_LOCKOUT_END 0x00000012 - -#define RT_SECAM_SYNCTIP_REF0 0x37 /* instead of 0x00000004 - Ivo */ -#define RT_SECAM_SYNCTIP_REF1 0x26 /* instead of 0x0000000F - Ivo */ -#define RT_SECAM_CLAMP_REF 0x0000003B -#define RT_SECAM_PEAKWHITE 0xFF /* instead of 0x000000C1 - Ivo */ -#define RT_SECAM_VBI_PEAKWHITE 0xC6 /* instead of 0x000000C7 - Ivo */ -#define RT_SECAM_WPA_THRESHOLD 0x57A /* instead of 0x6A4, instead of 0x0000059C is Ivo's value , -eric*/ - -#define RT_SECAM_WPA_TRIGGER_LO 0x96 /* instead of 0x0000026B - eric */ -#define RT_SECAM_WPA_TRIGGER_HIGH 0x000001C2 -#define RT_SECAM_LP_LOCKOUT_START 0x263 /* instead of 0x0000026B - eric */ -#define RT_SECAM_LP_LOCKOUT_END 0x2b /* instead of 0x0000002C -eric */ - -#define RT_SECAM_CH_DTO_INC 0x003E7A28 -#define RT_SECAM_CH_PLL_SGAIN 0x4 /* instead of 0x00000006 - Volodya */ -#define RT_SECAM_CH_PLL_FGAIN 0x7 /* instead of 0x00000006 -Volodya */ - -#define RT_SECAM_CR_BURST_GAIN 0x1FF /* instead of 0x00000200 -Volodya */ -#define RT_SECAM_CB_BURST_GAIN 0x1FF /* instead of 0x00000200 -Volodya */ -#define RT_SECAM_CH_HEIGHT 0x00000066 -#define RT_SECAM_CH_KILL_LEVEL 0x00000060 -#define RT_SECAM_CH_AGC_ERROR_LIM 0x00000003 -#define RT_SECAM_CH_AGC_FILTER_EN 0x00000000 -#define RT_SECAM_CH_AGC_LOOP_SPEED 0x00000000 - -#define RT_SECAM_CRDR_ACTIVE_GAIN 0x11B /* instead of 0x00000200 - eric */ -#define RT_SECAM_CBDB_ACTIVE_GAIN 0x15A /* instead of 0x00000200 - eric */ -#define RT_SECAM_VERT_LOCKOUT_START 0x00000269 -#define RT_SECAM_VERT_LOCKOUT_END 0x00000012 - -#define RT_PAL_VS_FIELD_BLANK_END 0x2A /* instead of 0x0000002C - Ivo*/ -#define RT_NTSCM_VS_FIELD_BLANK_END 0x0000000a - -#define RT_NTSCM_FIELD_IDLOCATION 0x00000105 -#define RT_PAL_FIELD_IDLOCATION 0x00000137 - -#define RT_NTSCM_H_ACTIVE_START 0x00000070 -#define RT_NTSCM_H_ACTIVE_END 0x00000363 - -#define RT_PAL_H_ACTIVE_START 0x0000009A -#define RT_PAL_H_ACTIVE_END 0x00000439 - -#define RT_NTSCM_V_ACTIVE_START ((22-4)*2+1) -#define RT_NTSCM_V_ACTIVE_END ((22+240-4)*2+1) - -#define RT_PAL_V_ACTIVE_START 0x2E /* instead of 0x00000023 (Same as SECAM) - Ivo */ -#define RT_PAL_V_ACTIVE_END 0x269 /* instead of 0x00000262 - Ivo */ - -/* VBI */ -#define RT_NTSCM_H_VBI_WIND_START 0x32 /* instead of 0x00000049 - V.D. */ -#define RT_NTSCM_H_VBI_WIND_END 0x367 /* instead of 0x00000366 - V.D. */ - -#define RT_PAL_H_VBI_WIND_START 0x00000084 -#define RT_PAL_H_VBI_WIND_END 0x0000041F - -#define RT_NTSCM_V_VBI_WIND_START fld_V_VBI_WIND_START_def -#define RT_NTSCM_V_VBI_WIND_END fld_V_VBI_WIND_END_def - -#define RT_PAL_V_VBI_WIND_START 0x8 /* instead of 0x0000000B - Ivo */ -#define RT_PAL_V_VBI_WIND_END 0x2D /* instead of 0x00000022 - Ivo */ - -#define RT_VBI_CAPTURE_EN 0x00000001 /* Enable */ -#define RT_VBI_CAPTURE_DIS 0x00000000 /* Disable */ -#define RT_RAW_CAPTURE 0x00000002 /* Use raw Video Capture. */ - -#define RT_NTSCM_VSYNC_INT_TRIGGER 0x2AA -#define RT_PALSEM_VSYNC_INT_TRIGGER 0x353 - -#define RT_NTSCM_VSYNC_INT_HOLD 0x17 -#define RT_PALSEM_VSYNC_INT_HOLD 0x1C - -#define RT_NTSCM_VS_FIELD_BLANK_START 0x206 -#define RT_PALSEM_VS_FIELD_BLANK_START 0x26D /* instead of 0x26C - Ivo */ - -#define RT_FIELD_FLIP_EN 0x4 -#define RT_V_FIELD_FLIP_INVERTED 0x2000 - -#define RT_NTSCM_H_IN_START 0x70 -#define RT_PAL_H_IN_START 154 /* instead of 144 - Ivo */ -#define RT_SECAM_H_IN_START 0x91 /* instead of 0x9A, Ivo value is 154, instead of 144 - Volodya, - eric */ -#define RT_NTSC_H_ACTIVE_SIZE 744 -#define RT_PAL_H_ACTIVE_SIZE 928 /* instead of 927 - Ivo */ -#define RT_SECAM_H_ACTIVE_SIZE 932 /* instead of 928, instead of 927 - Ivo, - eric */ -#define RT_NTSCM_V_IN_START (0x23) -#define RT_PAL_V_IN_START 44 /* instead of (45-6) - Ivo */ -#define RT_SECAM_V_IN_START 0x2C /* instead of (45-6) - Volodya */ -#define RT_NTSCM_V_ACTIVE_SIZE 480 -#define RT_PAL_V_ACTIVE_SIZE 572 /* instead of 575 - Ivo */ -#define RT_SECAM_V_ACTIVE_SIZE 570 /* instead of 572, instead of 575 - Ivo, - eric */ - -#define RT_NTSCM_WIN_CLOSE_LIMIT 0x4D -#define RT_NTSCJ_WIN_CLOSE_LIMIT 0x4D -#define RT_NTSC443_WIN_CLOSE_LIMIT 0x5F -#define RT_PALM_WIN_CLOSE_LIMIT 0x4D -#define RT_PALN_WIN_CLOSE_LIMIT 0x5F -#define RT_SECAM_WIN_CLOSE_LIMIT 0xC7 /* instead of 0x5F - eric */ - -#define RT_NTSCM_VS_FIELD_BLANK_START 0x206 - -#define RT_NTSCM_HS_PLL_SGAIN 0x5 -#define RT_NTSCM_HS_PLL_FGAIN 0x7 - -#define RT_NTSCM_H_OUT_WIND_WIDTH 0x2F4 -#define RT_NTSCM_V_OUT_WIND_HEIGHT 0xF0 - -#define TV 0x1 -#define LINEIN 0x2 -#define MUTE 0x3 - -#define DEC_COMPOSITE 0 -#define DEC_SVIDEO 1 -#define DEC_TUNER 2 - -#define DEC_NTSC 0 -#define DEC_PAL 1 -#define DEC_SECAM 2 -#define DEC_NTSC_J 8 - -#define DEC_SMOOTH 0 -#define DEC_SHARP 1 - -/* RT Register Field Defaults: */ -#define fld_tmpReg1_def (uint32_t) 0x00000000 -#define fld_tmpReg2_def (uint32_t) 0x00000001 -#define fld_tmpReg3_def (uint32_t) 0x00000002 - -#define fld_LP_CONTRAST_def (uint32_t) 0x0000006e -#define fld_LP_BRIGHTNESS_def (uint32_t) 0x00003ff0 -#define fld_CP_HUE_CNTL_def (uint32_t) 0x00000000 -#define fld_LUMA_FILTER_def (uint32_t) 0x00000001 -#define fld_H_SCALE_RATIO_def (uint32_t) 0x00010000 -#define fld_H_SHARPNESS_def (uint32_t) 0x00000000 - -#define fld_V_SCALE_RATIO_def (uint32_t) 0x00000800 -#define fld_V_DEINTERLACE_ON_def (uint32_t) 0x00000001 -#define fld_V_BYPSS_def (uint32_t) 0x00000000 -#define fld_V_DITHER_ON_def (uint32_t) 0x00000001 -#define fld_EVENF_OFFSET_def (uint32_t) 0x00000000 -#define fld_ODDF_OFFSET_def (uint32_t) 0x00000000 - -#define fld_INTERLACE_DETECTED_def (uint32_t) 0x00000000 - -#define fld_VS_LINE_COUNT_def (uint32_t) 0x00000000 -#define fld_VS_DETECTED_LINES_def (uint32_t) 0x00000000 -#define fld_VS_ITU656_VB_def (uint32_t) 0x00000000 - -#define fld_VBI_CC_DATA_def (uint32_t) 0x00000000 -#define fld_VBI_CC_WT_def (uint32_t) 0x00000000 -#define fld_VBI_CC_WT_ACK_def (uint32_t) 0x00000000 -#define fld_VBI_CC_HOLD_def (uint32_t) 0x00000000 -#define fld_VBI_DECODE_EN_def (uint32_t) 0x00000000 - -#define fld_VBI_CC_DTO_P_def (uint32_t) 0x00001802 -#define fld_VBI_20BIT_DTO_P_def (uint32_t) 0x0000155c - -#define fld_VBI_CC_LEVEL_def (uint32_t) 0x0000003f -#define fld_VBI_20BIT_LEVEL_def (uint32_t) 0x00000059 -#define fld_VBI_CLK_RUNIN_GAIN_def (uint32_t) 0x0000010f - -#define fld_H_VBI_WIND_START_def (uint32_t) 0x00000041 -#define fld_H_VBI_WIND_END_def (uint32_t) 0x00000366 - -#define fld_V_VBI_WIND_START_def (uint32_t) 0x0B /* instead of 0x0D - V.D. */ -#define fld_V_VBI_WIND_END_def (uint32_t) 0x24 - -#define fld_VBI_20BIT_DATA0_def (uint32_t) 0x00000000 -#define fld_VBI_20BIT_DATA1_def (uint32_t) 0x00000000 -#define fld_VBI_20BIT_WT_def (uint32_t) 0x00000000 -#define fld_VBI_20BIT_WT_ACK_def (uint32_t) 0x00000000 -#define fld_VBI_20BIT_HOLD_def (uint32_t) 0x00000000 - -#define fld_VBI_CAPTURE_ENABLE_def (uint32_t) 0x00000000 - -#define fld_VBI_EDS_DATA_def (uint32_t) 0x00000000 -#define fld_VBI_EDS_WT_def (uint32_t) 0x00000000 -#define fld_VBI_EDS_WT_ACK_def (uint32_t) 0x00000000 -#define fld_VBI_EDS_HOLD_def (uint32_t) 0x00000000 - -#define fld_VBI_SCALING_RATIO_def (uint32_t) 0x00010000 -#define fld_VBI_ALIGNER_ENABLE_def (uint32_t) 0x00000000 - -#define fld_H_ACTIVE_START_def (uint32_t) 0x00000070 -#define fld_H_ACTIVE_END_def (uint32_t) 0x000002f0 - -#define fld_V_ACTIVE_START_def (uint32_t) ((22-4)*2+1) -#define fld_V_ACTIVE_END_def (uint32_t) ((22+240-4)*2+2) - -#define fld_CH_HEIGHT_def (uint32_t) 0x000000CD -#define fld_CH_KILL_LEVEL_def (uint32_t) 0x000000C0 -#define fld_CH_AGC_ERROR_LIM_def (uint32_t) 0x00000002 -#define fld_CH_AGC_FILTER_EN_def (uint32_t) 0x00000000 -#define fld_CH_AGC_LOOP_SPEED_def (uint32_t) 0x00000000 - -#define fld_HUE_ADJ_def (uint32_t) 0x00000000 - -#define fld_STANDARD_SEL_def (uint32_t) 0x00000000 -#define fld_STANDARD_YC_def (uint32_t) 0x00000000 - -#define fld_ADC_PDWN_def (uint32_t) 0x00000001 -#define fld_INPUT_SELECT_def (uint32_t) 0x00000000 - -#define fld_ADC_PREFLO_def (uint32_t) 0x00000003 -#define fld_H_SYNC_PULSE_WIDTH_def (uint32_t) 0x00000000 -#define fld_HS_GENLOCKED_def (uint32_t) 0x00000000 -#define fld_HS_SYNC_IN_WIN_def (uint32_t) 0x00000000 - -#define fld_VIN_ASYNC_RST_def (uint32_t) 0x00000001 -#define fld_DVS_ASYNC_RST_def (uint32_t) 0x00000001 - -/* Vendor IDs: */ -#define fld_VIP_VENDOR_ID_def (uint32_t) 0x00001002 -#define fld_VIP_DEVICE_ID_def (uint32_t) 0x00004d54 -#define fld_VIP_REVISION_ID_def (uint32_t) 0x00000001 - -/* AGC Delay Register */ -#define fld_BLACK_INT_START_def (uint32_t) 0x00000031 -#define fld_BLACK_INT_LENGTH_def (uint32_t) 0x0000000f - -#define fld_UV_INT_START_def (uint32_t) 0x0000003b -#define fld_U_INT_LENGTH_def (uint32_t) 0x0000000f -#define fld_V_INT_LENGTH_def (uint32_t) 0x0000000f -#define fld_CRDR_ACTIVE_GAIN_def (uint32_t) 0x0000007a -#define fld_CBDB_ACTIVE_GAIN_def (uint32_t) 0x000000ac - -#define fld_DVS_DIRECTION_def (uint32_t) 0x00000000 -#define fld_DVS_VBI_UINT8_SWAP_def (uint32_t) 0x00000000 -#define fld_DVS_CLK_SELECT_def (uint32_t) 0x00000000 -#define fld_CONTINUOUS_STREAM_def (uint32_t) 0x00000000 -#define fld_DVSOUT_CLK_DRV_def (uint32_t) 0x00000001 -#define fld_DVSOUT_DATA_DRV_def (uint32_t) 0x00000001 - -#define fld_COMB_CNTL0_def (uint32_t) 0x09438090 -#define fld_COMB_CNTL1_def (uint32_t) 0x00000010 - -#define fld_COMB_CNTL2_def (uint32_t) 0x16161010 -#define fld_COMB_LENGTH_def (uint32_t) 0x0718038A - -#define fld_SYNCTIP_REF0_def (uint32_t) 0x00000037 -#define fld_SYNCTIP_REF1_def (uint32_t) 0x00000029 -#define fld_CLAMP_REF_def (uint32_t) 0x0000003B -#define fld_AGC_PEAKWHITE_def (uint32_t) 0x000000FF -#define fld_VBI_PEAKWHITE_def (uint32_t) 0x000000D2 - -#define fld_WPA_THRESHOLD_def (uint32_t) 0x000003B0 - -#define fld_WPA_TRIGGER_LO_def (uint32_t) 0x000000B4 -#define fld_WPA_TRIGGER_HIGH_def (uint32_t) 0x0000021C - -#define fld_LOCKOUT_START_def (uint32_t) 0x00000206 -#define fld_LOCKOUT_END_def (uint32_t) 0x00000021 - -#define fld_CH_DTO_INC_def (uint32_t) 0x00400000 -#define fld_PLL_SGAIN_def (uint32_t) 0x00000001 -#define fld_PLL_FGAIN_def (uint32_t) 0x00000002 - -#define fld_CR_BURST_GAIN_def (uint32_t) 0x0000007a -#define fld_CB_BURST_GAIN_def (uint32_t) 0x000000ac - -#define fld_VERT_LOCKOUT_START_def (uint32_t) 0x00000207 -#define fld_VERT_LOCKOUT_END_def (uint32_t) 0x0000000E - -#define fld_H_IN_WIND_START_def (uint32_t) 0x00000070 -#define fld_V_IN_WIND_START_def (uint32_t) 0x00000027 - -#define fld_H_OUT_WIND_WIDTH_def (uint32_t) 0x000002f4 - -#define fld_V_OUT_WIND_WIDTH_def (uint32_t) 0x000000f0 - -#define fld_HS_LINE_TOTAL_def (uint32_t) 0x0000038E - -#define fld_MIN_PULSE_WIDTH_def (uint32_t) 0x0000002F -#define fld_MAX_PULSE_WIDTH_def (uint32_t) 0x00000046 - -#define fld_WIN_CLOSE_LIMIT_def (uint32_t) 0x0000004D -#define fld_WIN_OPEN_LIMIT_def (uint32_t) 0x000001B7 - -#define fld_VSYNC_INT_TRIGGER_def (uint32_t) 0x000002AA - -#define fld_VSYNC_INT_HOLD_def (uint32_t) 0x0000001D - -#define fld_VIN_M0_def (uint32_t) 0x00000039 -#define fld_VIN_N0_def (uint32_t) 0x0000014c -#define fld_MNFLIP_EN_def (uint32_t) 0x00000000 -#define fld_VIN_P_def (uint32_t) 0x00000006 -#define fld_REG_CLK_SEL_def (uint32_t) 0x00000000 - -#define fld_VIN_M1_def (uint32_t) 0x00000000 -#define fld_VIN_N1_def (uint32_t) 0x00000000 -#define fld_VIN_DRIVER_SEL_def (uint32_t) 0x00000000 -#define fld_VIN_MNFLIP_REQ_def (uint32_t) 0x00000000 -#define fld_VIN_MNFLIP_DONE_def (uint32_t) 0x00000000 -#define fld_TV_LOCK_TO_VIN_def (uint32_t) 0x00000000 -#define fld_TV_P_FOR_WINCLK_def (uint32_t) 0x00000004 - -#define fld_VINRST_def (uint32_t) 0x00000001 -#define fld_VIN_CLK_SEL_def (uint32_t) 0x00000000 - -#define fld_VS_FIELD_BLANK_START_def (uint32_t) 0x00000206 - -#define fld_VS_FIELD_BLANK_END_def (uint32_t) 0x0000000A - -/*#define fld_VS_FIELD_IDLOCATION_def (uint32_t) 0x00000105 */ -#define fld_VS_FIELD_IDLOCATION_def (uint32_t) 0x00000001 -#define fld_VS_FRAME_TOTAL_def (uint32_t) 0x00000217 - -#define fld_SYNC_TIP_START_def (uint32_t) 0x00000372 -#define fld_SYNC_TIP_LENGTH_def (uint32_t) 0x0000000F - -#define fld_GAIN_FORCE_DATA_def (uint32_t) 0x00000000 -#define fld_GAIN_FORCE_EN_def (uint32_t) 0x00000000 -#define fld_I_CLAMP_SEL_def (uint32_t) 0x00000003 -#define fld_I_AGC_SEL_def (uint32_t) 0x00000001 -#define fld_EXT_CLAMP_CAP_def (uint32_t) 0x00000001 -#define fld_EXT_AGC_CAP_def (uint32_t) 0x00000001 -#define fld_DECI_DITHER_EN_def (uint32_t) 0x00000001 -#define fld_ADC_PREFHI_def (uint32_t) 0x00000000 -#define fld_ADC_CH_GAIN_SEL_def (uint32_t) 0x00000001 - -#define fld_HS_PLL_SGAIN_def (uint32_t) 0x00000003 - -#define fld_NREn_def (uint32_t) 0x00000000 -#define fld_NRGainCntl_def (uint32_t) 0x00000000 -#define fld_NRBWTresh_def (uint32_t) 0x00000000 -#define fld_NRGCTresh_def (uint32_t) 0x00000000 -#define fld_NRCoefDespeclMode_def (uint32_t) 0x00000000 - -#define fld_GPIO_5_OE_def (uint32_t) 0x00000000 -#define fld_GPIO_6_OE_def (uint32_t) 0x00000000 - -#define fld_GPIO_5_OUT_def (uint32_t) 0x00000000 -#define fld_GPIO_6_OUT_def (uint32_t) 0x00000000 - -/* End of field default values. */ - -#endif |