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2015-06-29Fix inconsistent default eg_tile_split in evergreen_accel.cMario Kleiner
eg_tile_split() maps the default: switch-case to tile split flag 6, like for a tile split size of 4096 Bytes. All other instances of tile split mappings or reverse mappings in both the ddx and in Mesa's radeon gallium drivers assign the default: case to tile split flag 4, consistent with a default of 1024 Bytes. Make this one outlier consistent with other instances of mappings in the code to avoid surprises. Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
2014-08-12radeon: drop redundant radeon_drm.h includesAndreas Boll
Already included via radeon.h. Signed-off-by: Andreas Boll <andreas.boll.dev@gmail.com>
2014-02-24evergreen: fix shader constant upload on ppcJérôme Glisse
The number of dword we have to swap is (16*4) ie 16 vectors of 4 floats each not 16 floats. Never hit this issue before because we never had more than 4 constant vector. Signed-off-by: Jérôme Glisse <jglisse@redhat.com>
2013-07-22EXA/evergreen/ni: accelerate PictOpOver with component alphaGrigori Goronzy
Subpixel text rendering is typically done with a solid src and a pixmap mask. Traditionally, this cannot be accelerated in a single pass and requires two passes [1]. However, we can cheat a little with a constant blend color. We can use: const.A = src.A / src.A const.R = src.R / src.A const.G = src.G / src.A const.B = src.B / src.A dst.A = const.A * (src.A * mask.A) + (1 - (src.A * mask.A)) * dst.A dst.R = const.R * (src.A * mask.R) + (1 - (src.A * mask.R)) * dst.R dst.G = const.G * (src.A * mask.G) + (1 - (src.A * mask.G)) * dst.G dst.B = const.B * (src.A * mask.B) + (1 - (src.A * mask.B)) * dst.B This only needs a single source value. src.A is cancelled down in the right places. [1] http://anholt.livejournal.com/32058.html
2012-06-15radeon: drop vb_mc_addr, not needed anymoreDave Airlie
This field is totally unused now, so drop it. Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-06-15radeon: drop offset member of r600 accel objectDave Airlie
This is always 0 now. Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-06-15radeon: drop all UMS/DRI1/XAA/overlay support.Dave Airlie
This overhauls the radeon driver and removes all the old UMS-only code, it drops all the UMS, DRI1, XAA, overlay Xv, video capture, tv tuners There are probably a lot more cleanups that will fall out of this afterwards. So far this is compile/build tested. Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-03-20radeon/kms: add support for TN (trinity) APUsAlex Deucher
- KMS only - Includes full EXA/Xv support Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2012-02-06r600-evergreen: use common surface allocator for tiling v11Jerome Glisse
Use libdrm common surface code so mesa,ddx have same idea about tiling surface and what their pitch should be and the alignment constraint. v2 fix remaining issue add new option to conditionaly enable v3 fix fbcon copy and r600 exa copy path v4 fix non tiled path 2D tiling on GPU >= R600, set it to false as default v5 adapt to pixel/element size split of libdrm/radeon v6 update to properly handle falling back to 1d tiled v6 final fix to tile split value on evergreen and newer v7 fix default array mode on r6xx, fix height alignment issue on evergreen v8 fix tile split value v9 add stencil tile split support, simplify dri2 for stencil with evergreen v10 Try to fix xv path regarding tiling. Adapt to libdrm API change. Try to fix case where there is no surface which means non tiled bo. v11 check for proper libdrm Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-02-01Fix vline range calculations.Michel Dänzer
The range passed in is in pixmap coordinates, so the CRTC offset needs to be added to the clamping limits and subtracted from the clamped range for pre-AVIVO display engines. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-02-01Check for empty vline ranges after clamping.Michel Dänzer
The clamping could turn a previously non-empty range into an empty one. Also, start == stop means the range is empty. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2011-11-21ddx/evergreen: Fix endian of ALU constantsBenjamin Herrenschmidt
The constants are written directly into a buffer object shared with the card and we "forget" to swap them. This patch fixes it by doing the swap in evergreen_set_alu_consts() in-place (ie, it modifies the buffer), which should be fine with the way we use it in the ddx. This makes everything work fine on my caicos card on a G5 including some quik tests with Xv, gnome3 shell, etc... Thanks a lot to Jerome Glisse for holding my hand through debugging that (and finding the actual bug). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-08-03r5xx+: Fix vline setup with crtc offsetsAlex Deucher
On r5xx+, vline is relative to to the viewport, not the scanlines. Based on initial patch and investigation from Herbert Pötzl (Bertl) on IRC. Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-07-12evergreen: Emit SQ_LDS_RESOURCE_MGMTDave Airlie
Avoids rendering problems when compute changes this reg. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=39119 Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-05-31radeon: add support for llano APUsAlex Deucher
- KMS only - Includes full EXA/Xv support Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-05-25EXA: make evergreen_fix_scissor_coordinates staticAlex Deucher
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-05-24EXA/Xv: add workarounds for eg/cayman scissors bugsAlex Deucher
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-05-24cayman: add a default state functionAlex Deucher
The rest of the state functions can be shared with evergreen. I've noted where there are differences. Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-02-16kms: EXA/Xv tiling fixesAlex Deucher
- properly set tiling flags for temp surfaces - fix CB non_disp_tiling bits on evergreen Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-02-11kms: evergreen/ni big endian accel supportAlex Deucher
Based on 6xx/7xx patches from Cédric Cano. Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-02-10evergreen/NI: consolidate spi setupAlex Deucher
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-02-10evergreen/ni: consolidate CB state handlingAlex Deucher
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-01-21vbo: remove useless radeon_vb_discard()Alex Deucher
We already reset vb_start_op to -1 in the UMS/KMS ib discard functions.
2011-01-06Add EXA/Xv acceleration support for NI chipsAlex Deucher
2010-11-22Add EXA/Xv acceleration support for Ontario Fusion APUsAlex Deucher
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2010-10-07fix the non-kms buildAlex Deucher
Should fix: https://bugs.freedesktop.org/show_bug.cgi?id=30685
2010-09-09Fix NULL possible deref in evergreen_cp_wait_vline_syncMathieu Bérard
2010-09-02evergreen: add additional default stateAlex Deucher
Note, you also need a drm patch to fix the GPU hangs: drm/radeon/kms/evergreen: fix gpu hangs in userspace accel code Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2010-08-23evergreen: use vbo pool for constant buffersAlex Deucher
2010-08-23radeon: move vbo data to a separate structAlex Deucher
this way we can share the vbo code with const buffers
2010-08-23evergreen: fix dword counts in default stateAlex Deucher
2010-08-20Add initial EXA and Xv support for evergreenAlex Deucher
Based on the r6xx/r7xx code updated for evergreen. Still causes GPU hangs in some cases. We haven't tracked down why yet. Might be related to constant buffer persistence. Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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