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Inspired by amdgpu, preparation for the following change. For now, this
is mostly a wrapper around struct radeon_bo, no functional change
intended.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
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This patch adds an option called consider_disabled to
radeon_pick_best_crtc function. If this option is set
and searching for best-fit CRTC yields nothing, the search
will be widened to include CRTCs in DPMS "off" state.
The new option is not used yet; it will be in the patches
to follow.
v2: Do not look at the CRTC mode, we only care about its box.
Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
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Reviewed-by: Alex Deucher <aleander.deucher@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
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This is always 0 now.
Signed-off-by: Dave Airlie <airlied@redhat.com>
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This overhauls the radeon driver and removes all the old UMS-only code,
it drops all the UMS, DRI1, XAA, overlay Xv, video capture, tv tuners
There are probably a lot more cleanups that will fall out of this afterwards.
So far this is compile/build tested.
Signed-off-by: Dave Airlie <airlied@redhat.com>
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Those formats were invented for exactly that purpose so use them.
This saves some code and also some hw resources (only need one
sampler instead of two for packed yuv).
Only tested on EG.
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make sure the division is done with floats, otherwise the coordinate
can be wrong up to 1 texel.
Particularly visible with clipping and small source scaled up (since one
texel can be a shift of several pixels) but could be seen even unscaled.
Should provide more accurate coords without clipping too depending on the
scale factor probably.
Changed for r100-r600, though only tested on r300.
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And some UMS specific warnings.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
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Should also fix xv for some case.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Use libdrm common surface code so mesa,ddx have same idea
about tiling surface and what their pitch should be and
the alignment constraint.
v2 fix remaining issue add new option to conditionaly enable
v3 fix fbcon copy and r600 exa copy path
v4 fix non tiled path 2D tiling on GPU >= R600, set it to false
as default
v5 adapt to pixel/element size split of libdrm/radeon
v6 update to properly handle falling back to 1d tiled
v6 final fix to tile split value on evergreen and newer
v7 fix default array mode on r6xx, fix height alignment issue
on evergreen
v8 fix tile split value
v9 add stencil tile split support, simplify dri2 for stencil
with evergreen
v10 Try to fix xv path regarding tiling. Adapt to libdrm API
change. Try to fix case where there is no surface which
means non tiled bo.
v11 check for proper libdrm
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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This avoids calling into the kernel for each bo in the accel
code. This is a follow on to:
cc7d1fa39da40a532fcdbe6c7924ca47a879e66a
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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agd5f: minor cleanups
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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linear aligned is supposedly more performant, but more
importantly, linear general only works on the CB without
slices. The texture blocks technically don't support
linear general although, I think linear general gets
upgraded to linear aligned in the hw which is why it
currently works.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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bad textures size for cache flushes.
Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=22007
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this way we can share the vbo code with const buffers
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Based on the r6xx/r7xx code updated for evergreen.
Still causes GPU hangs in some cases. We haven't
tracked down why yet. Might be related to constant
buffer persistence.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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reduces code duplication.
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This is a precursor for r300/500 vbo support.
Signed-off-by: Dave Airlie <airlied@redhat.com>
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Group the op variable state into one emit block, re-order
to reduce dwords emitted.
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This cleans up the accel state objects as well.
Signed-off-by: Dave Airlie <airlied@redhat.com>
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Create a small accel object that can be used to reduce the amount
of parameters passed to SetAccelState. This can be cleaned up a lot more.
Signed-off-by: Dave Airlie <airlied@redhat.com>
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This moves CS bo checking and alignment checks into
a central location. It also cleans up the code.
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Much of the code is shared, so track the src/dst
domains so we make sure the uses consistent domains
for each bo.
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Noticed by Pauli and Michel on IRC.
Improves GetImage performace by a factor of ~10.
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Also fix some RADEON_ALIGN(x, 63), which would return incorrect results
for odd x. Though this shouldn't happen, it's still not right. You
wouldn't ever write (x + 62) & ~62 which is clearly wrong (and what it
expands to).
CC: Jerome Glisse <jglisse@redhat.com>
CC: Alex Deucher <alexdeucher@gmail.com>
CC: Dave Airlie <airlied@redhat.com>
Signed-off-by: Matt Turner <mattst88@gmail.com>
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Use the Xv version as it takes into account the area
covered by the op rather than just picking the largest
crtc area.
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This ports the mesa DMA buffer handling with the 3 lists,
Signed-off-by: Dave Airlie <airlied@redhat.com>
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All of the drawing ops were the exact same modulo the vtx size,
this along with the vertex buffer wrapping code could all be consolidated
into a smaller set of functions.
This also adds 2 VBO which we switch between, and merges a #define to
enable the multiple operations in one CS under KMS mode.
Multi-operation still isn't working though.
Signed-off-by: Dave Airlie <airlied@redhat.com>
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To put multiple ops into one CS, you can't just discard the whole
IB. This add supports for reset the CS cdw to the correct place
after an op discards.
Still doesn't enable the final accel bits.
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This changes the vertex buffer index to be an offset, and
records the start of the vb for each operation and uses
that to set the operations up.
This still flushes after each operation to make sure we have
no regressions in non-kms/kms cases.
Signed-off-by: Dave Airlie <airlied@redhat.com>
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This attribute allows the user to override which
crtc is synced with when XV_VSYNC is enabled. This
is useful for clone modes where the user can might want
to override the default.
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In order to avoid stalling on previous frame.
OTOH without KMS we can't do this but have to wait for the previous frame to
finish rendering.
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drm crtc ids do not correspond to actual hw crtcs,
as such the vline stuff was never enabled for Xv.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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fixes Xv after changes in:
8f80e37eed3ec028718b4e71bbb9b598847fd94e
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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Adapted from various patches from Dave and Jerome.
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Abstract vertex buffer, preliminary work before others change
to bring cs support along IB support.
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