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Ported from the equivalent fix in Mesa.
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Based on the r6xx/r7xx code updated for evergreen.
Still causes GPU hangs in some cases. We haven't
tracked down why yet. Might be related to constant
buffer persistence.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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The *_HIGH regs are reversed. The secondary ones are in the
primary block and vice versa.
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so remove them from radeon use.
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Also, r6xx/r7xx don't have indirect MC space, so
don't try to access it.
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As recommended by the register reference when using the WAIT_CRTC_VLINE bit in
the WAIT_UNTIL register, as we are.
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Also remove SetMemoryClk() for pre-atom cards for now
as it requires quite a bit more asic specific work.
To set the mclk we'll need to use the mem reset/dll tables
in the bios.
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This helps with flickering and blanking when
there is contention for MC bandwidth.
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- hw i2c engine has pin selection on r2xx/r2xx/r3xx chips
- also switch hw i2c pin sel for external tmds
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Patch from Eduard Fuchs with some cleanup from me.
Tested at 32 bpp on MPC8641HPCN board (PowerPC) with
HD2400 PCIe card
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should fix bug 13872
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uses 3 textures for planar yuv and does yuv->rgb conversion in the shader.
Similar to r300 code, but might have precision issues - hardware alu should
have enough precision but hardware consts are only 8bit and we'd want
at least 11.
This also enables textured video on rv250 (and also supports packed yuv
on that chip by using basically the same shader with packed data).
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uses 3 textures for planar yuv and does yuv->rgb conversion in the shader.
small performance advantage, but manual texture cache setting is necessary
otherwise it may be measurably slower (but probably not relevant) in some
cases.
Unlike some other drivers, using MADs instead of DP3s, since this requires
less instructions due to no MOVs are required, the end result is the same
though the constants need to be different.
Use of this is user settable for now (XV_HWPLANAR attrib).
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git+ssh://agd5f@git.freedesktop.org/git/xorg/driver/xf86-video-ati
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Noticed by osiris on IRC
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Please test if you have an RS600
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should fix bug 19984
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This fixes some VT switch issues on some chips
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Call EnableYUV to set the transform and enable/disable it.
should also fix green tint with tv connected at boot issues.
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- Fix up VLINE handling to trigger whenever scanout is outside the
visible area.
- Render the video as a scissored triangle as R300+ cannot render a
quad in a single pass.
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if the dest pixmap is the front buffer, stall the pipe
until the vline is outside the active area.
For EXA, pick crtc based on the larger mode area;
ideally we'd have one pixmap per crtc.
For Xv, use dst window area to determine crtc.
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work yet...
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- r1xx - switch from tri fan to rect list
- r2xx/r3xx/r4xx/r5xx - switch from tri fan to quad list
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- support for LB allocation
- MC priority bumps for display1/2 on RV515 variants and RS690
If you are having display underflow problems (flickering on sides of
screen in high res modes, etc.) on RV515 or RS690 boards, try setting:
Option "DisplayPriority" "HIGH" in your config.
- still no support for full display watermark programming yet
Something similar might be useful in rhd as well.
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- makes crtc1 and crtc2 watermark setup independant.
- fixes the case where only crtc2 is active
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This patch fixes the console switch for me on R5xx.
There are two aspects to it:
- Fix the ordering of avivo_restore() to better match what's
happening in the driver & ATOM, properly locking/unlocking and
only enabling the CRTCs after everything has been properly
programmed.
- Don't ASIC_INIT if the card has any CRTC enabled. This is the
best I came up with for avoiding spurrious ASIC_INIT on cards that
-are- POSTed but don't have the BIOS coming from c0000 on x86. The
problem with spurrious ASIC_INIT is that we do it before we do
RADEONSave(), so that screws up the console switch.
Note that I think we also should save/restore the palette, I don't think
we do. right now, it's a minor issue for me because I fixed offb to be
able to set it on AVIVO's but it might still have to be done in the long
run.
Tested with a VGA analog setup on DACA and a DVI setup on TMDS 0. I
haven't tested any other combo but that should get us going.
Cheers,
Ben.
Signed-off-by: Dave Airlie <airlied@redhat.com>
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adds pci ids and one register from AMD code
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This should help to avoid 2d & 3d engine to step on each
other dma transaction.
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According to the hw guys, you should use DSTCACHE_CTLSTAT to
flush the 2D dst cache rather than RB2D_DSTCACHE_CTLSTAT.
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Is there any reason to still do this in the ddx?
Maybe real old drms?
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