diff options
| -rw-r--r-- | src/cim/cim_df.c | 8 | ||||
| -rw-r--r-- | src/cim/cim_vg.c | 3 |
2 files changed, 7 insertions, 4 deletions
diff --git a/src/cim/cim_df.c b/src/cim/cim_df.c index 676ef3c..f81b740 100644 --- a/src/cim/cim_df.c +++ b/src/cim/cim_df.c @@ -983,11 +983,15 @@ df_set_video_palette_entry(unsigned long index, unsigned long palette) /* Ensure that the Graphic data passes through the Gamma * Correction RAM + * + * XXX is this a bug? perhaps it should be setting the bit so that video + * data is routed, according to the description above. + * it also mismatches df_set_video_palette(). */ dcfg &= ~DF_DCFG_GV_PAL_BYP; - /* The graphics and video data are passed through gamma - * correction RAM + /* Unset the "bypass both" bit to make sure the above selection (gfx/video + * data through gamma correction RAM) takes effect. */ misc &= ~DF_GAMMA_BYPASS_BOTH; diff --git a/src/cim/cim_vg.c b/src/cim/cim_vg.c index 6a8ea49..ff24221 100644 --- a/src/cim/cim_vg.c +++ b/src/cim/cim_vg.c @@ -1002,8 +1002,7 @@ vg_set_custom_mode(VG_DISPLAY_MODE * mode_params, int bpp) temp &= ~(DF_DCFG_CRT_SYNC_SKW_MASK | DF_DCFG_PWR_SEQ_DLY_MASK | DF_DCFG_CRT_HSYNC_POL | DF_DCFG_CRT_VSYNC_POL); - temp |= (DF_DCFG_CRT_SYNC_SKW_INIT | - DF_DCFG_PWR_SEQ_DLY_INIT | DF_DCFG_GV_PAL_BYP); + temp |= DF_DCFG_CRT_SYNC_SKW_INIT | DF_DCFG_PWR_SEQ_DLY_INIT; if (mode_params->flags & VG_MODEFLAG_NEG_HSYNC) temp |= DF_DCFG_CRT_HSYNC_POL; |