Add support for Ivybridge chipset.

This gets display and 2D blit acceleration up and running.  No Render
acceleration is provided yet.
(cherry picked from commit 79e59fb2a047b1e733a7b0dee608db3311391725)

Conflicts:

	src/intel_module.c

4 files changed, 68 insertions, 49 deletions

diff --git a/src/i965_render.c b/src/i965_render.c
index 363cf50e..4d4e4eef 100644
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@ -181,6 +181,10 @@ i965_check_composite(int op,
 		     int width, int height)
 {
 	ScrnInfoPtr scrn = xf86Screens[dest_picture->pDrawable->pScreen->myNum];
+	intel_screen_private *intel = intel_get_screen_private(scrn);
+
+	if (IS_GEN7(intel))
+		return FALSE;
 
 	/* Check for unsupported compositing operations. */
 	if (op >= sizeof(i965_blend_op) / sizeof(i965_blend_op[0])) {
diff --git a/src/intel_batchbuffer.c b/src/intel_batchbuffer.c
index fcdd1084..53d3dccc 100644
--- a/src/intel_batchbuffer.c
+++ b/src/intel_batchbuffer.c
@@ -211,7 +211,9 @@ void intel_batch_submit(ScrnInfoPtr scrn)
 		ret = drm_intel_bo_mrb_exec(intel->batch_bo,
 				intel->batch_used*4,
 				NULL, 0, 0xffffffff,
-				IS_GEN6(intel) ? intel->current_batch: I915_EXEC_DEFAULT);
+				(HAS_BLT(intel) ?
+				 intel->current_batch:
+				 I915_EXEC_DEFAULT));
 	}
 
 	if (ret != 0) {
diff --git a/src/intel_driver.h b/src/intel_driver.h
index 6aa39546..c1fb92b9 100644
--- a/src/intel_driver.h
+++ b/src/intel_driver.h
@@ -216,6 +216,7 @@
 #define IS_GEN4(intel) IS_GENx(intel, 4)
 #define IS_GEN5(intel) IS_GENx(intel, 5)
 #define IS_GEN6(intel) IS_GENx(intel, 6)
+#define IS_GEN7(intel) IS_GENx(intel, 7)
 
 /* Some chips have specific errata (or limits) that we need to workaround. */
 #define IS_I830(intel) (DEVICE_ID((intel)->PciInfo) == PCI_CHIP_I830_M)
@@ -279,6 +280,7 @@
 #define DSPARB_HWCONTROL(pI810) (IS_G4X(pI810) || IS_IGDNG(pI810))
 /* supports Y tiled surfaces (pre-965 Mesa isn't ready yet) */
 #define SUPPORTS_YTILING(pI810) (INTEL_INFO(intel)->gen >= 40)
+#define HAS_BLT(pI810) (INTEL_INFO(intel)->gen >= 60)
 
 extern SymTabRec *intel_chipsets;
 
diff --git a/src/intel_module.c b/src/intel_module.c
index df8ae146..875ba443 100644
--- a/src/intel_module.c
+++ b/src/intel_module.c
@@ -72,55 +72,59 @@ static const struct intel_device_info intel_sandybridge_info = {
 	.gen = 60,
 };
 
+static const struct intel_device_info intel_ivybridge_info = {
+	.gen = 70,
+};
+
 static const SymTabRec _intel_chipsets[] = {
-	{PCI_CHIP_I810,				"i810"},
-	{PCI_CHIP_I810_DC100,			"i810-dc100"},
-	{PCI_CHIP_I810_E,			"i810e"},
-	{PCI_CHIP_I815,				"i815"},
-	{PCI_CHIP_I830_M,			"i830M"},
-	{PCI_CHIP_845_G,			"845G"},
-	{PCI_CHIP_I854,				"854"},
-	{PCI_CHIP_I855_GM,			"852GM/855GM"},
-	{PCI_CHIP_I865_G,			"865G"},
-	{PCI_CHIP_I915_G,			"915G"},
-	{PCI_CHIP_E7221_G,			"E7221 (i915)"},
-	{PCI_CHIP_I915_GM,			"915GM"},
-	{PCI_CHIP_I945_G,			"945G"},
-	{PCI_CHIP_I945_GM,			"945GM"},
-	{PCI_CHIP_I945_GME,			"945GME"},
-	{PCI_CHIP_PINEVIEW_M,			"Pineview GM"},
-	{PCI_CHIP_PINEVIEW_G,			"Pineview G"},
-	{PCI_CHIP_I965_G,			"965G"},
-	{PCI_CHIP_G35_G,			"G35"},
-	{PCI_CHIP_I965_Q,			"965Q"},
-	{PCI_CHIP_I946_GZ,			"946GZ"},
-	{PCI_CHIP_I965_GM,			"965GM"},
-	{PCI_CHIP_I965_GME,			"965GME/GLE"},
-	{PCI_CHIP_G33_G,			"G33"},
-	{PCI_CHIP_Q35_G,			"Q35"},
-	{PCI_CHIP_Q33_G,			"Q33"},
-	{PCI_CHIP_GM45_GM,			"GM45"},
-	{PCI_CHIP_G45_E_G,			"4 Series"},
-	{PCI_CHIP_G45_G,			"G45/G43"},
-	{PCI_CHIP_Q45_G,			"Q45/Q43"},
-	{PCI_CHIP_G41_G,			"G41"},
-	{PCI_CHIP_B43_G,			"B43"},
-	{PCI_CHIP_B43_G1,			"B43"},
-	{PCI_CHIP_IRONLAKE_D_G,			"Clarkdale"},
-	{PCI_CHIP_IRONLAKE_M_G,			"Arrandale"},
-	{PCI_CHIP_SANDYBRIDGE_GT1,		"Sandybridge Desktop (GT1)" },
-	{PCI_CHIP_SANDYBRIDGE_GT2,		"Sandybridge Desktop (GT2)" },
-	{PCI_CHIP_SANDYBRIDGE_GT2_PLUS,		"Sandybridge Desktop (GT2+)" },
-	{PCI_CHIP_SANDYBRIDGE_M_GT1,		"Sandybridge Mobile (GT1)" },
-	{PCI_CHIP_SANDYBRIDGE_M_GT2,		"Sandybridge Mobile (GT2)" },
-	{PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS,	"Sandybridge Mobile (GT2+)" },
-	{PCI_CHIP_SANDYBRIDGE_S_GT,		"Sandybridge Server" },
-	{PCI_CHIP_IVYBRIDGE_M_GT1,		"Ivybridge Mobile (GT1)" },
-	{PCI_CHIP_IVYBRIDGE_M_GT2,		"Ivybridge Mobile (GT2)" },
-	{PCI_CHIP_IVYBRIDGE_D_GT1,		"Ivybridge Desktop (GT1)" },
-	{PCI_CHIP_IVYBRIDGE_D_GT2,		"Ivybridge Desktop (GT2)" },
-	{PCI_CHIP_IVYBRIDGE_S_GT1,		"Ivybridge Server" },
-	{-1,					NULL}
+    {PCI_CHIP_I810,		"i810"},
+    {PCI_CHIP_I810_DC100,	"i810-dc100"},
+    {PCI_CHIP_I810_E,		"i810e"},
+    {PCI_CHIP_I815,		"i815"},
+    {PCI_CHIP_I830_M,		"i830M"},
+    {PCI_CHIP_845_G,		"845G"},
+    {PCI_CHIP_I854,		"854"},
+    {PCI_CHIP_I855_GM,		"852GM/855GM"},
+    {PCI_CHIP_I865_G,		"865G"},
+    {PCI_CHIP_I915_G,		"915G"},
+    {PCI_CHIP_E7221_G,		"E7221 (i915)"},
+    {PCI_CHIP_I915_GM,		"915GM"},
+    {PCI_CHIP_I945_G,		"945G"},
+    {PCI_CHIP_I945_GM,		"945GM"},
+    {PCI_CHIP_I945_GME,		"945GME"},
+    {PCI_CHIP_PINEVIEW_M,	"Pineview GM"},
+    {PCI_CHIP_PINEVIEW_G,	"Pineview G"},
+    {PCI_CHIP_I965_G,		"965G"},
+    {PCI_CHIP_G35_G,		"G35"},
+    {PCI_CHIP_I965_Q,		"965Q"},
+    {PCI_CHIP_I946_GZ,		"946GZ"},
+    {PCI_CHIP_I965_GM,		"965GM"},
+    {PCI_CHIP_I965_GME,		"965GME/GLE"},
+    {PCI_CHIP_G33_G,		"G33"},
+    {PCI_CHIP_Q35_G,		"Q35"},
+    {PCI_CHIP_Q33_G,		"Q33"},
+    {PCI_CHIP_GM45_GM,		"GM45"},
+    {PCI_CHIP_G45_E_G,		"4 Series"},
+    {PCI_CHIP_G45_G,		"G45/G43"},
+    {PCI_CHIP_Q45_G,		"Q45/Q43"},
+    {PCI_CHIP_G41_G,		"G41"},
+    {PCI_CHIP_B43_G,		"B43"},
+    {PCI_CHIP_B43_G1,		"B43"},
+    {PCI_CHIP_IRONLAKE_D_G,		"Clarkdale"},
+    {PCI_CHIP_IRONLAKE_M_G,		"Arrandale"},
+    {PCI_CHIP_SANDYBRIDGE_GT1,	"Sandybridge" },
+    {PCI_CHIP_SANDYBRIDGE_GT2,	"Sandybridge" },
+    {PCI_CHIP_SANDYBRIDGE_GT2_PLUS,	"Sandybridge" },
+    {PCI_CHIP_SANDYBRIDGE_M_GT1,	"Sandybridge" },
+    {PCI_CHIP_SANDYBRIDGE_M_GT2,	"Sandybridge" },
+    {PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS,	"Sandybridge" },
+    {PCI_CHIP_SANDYBRIDGE_S_GT,	"Sandybridge" },
+    {PCI_CHIP_IVYBRIDGE_M_GT1,	"Ivybridge Mobile GT1" },
+    {PCI_CHIP_IVYBRIDGE_M_GT2,	"Ivybridge Mobile GT2" },
+    {PCI_CHIP_IVYBRIDGE_D_GT1,	"Ivybridge Desktop GT1" },
+    {PCI_CHIP_IVYBRIDGE_D_GT2,	"Ivybridge Desktop GT2" },
+    {PCI_CHIP_IVYBRIDGE_S_GT1,	"Ivybridge Server GT1" },
+    {-1,				NULL}
 };
 SymTabRec *intel_chipsets = (SymTabRec *) _intel_chipsets;
 
@@ -177,6 +181,13 @@ static const struct pci_id_match intel_device_match[] = {
     INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS, &intel_sandybridge_info ),
     INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_S_GT, &intel_sandybridge_info ),
 
+
+    INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_M_GT1, &intel_ivybridge_info ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_M_GT2, &intel_ivybridge_info ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_D_GT1, &intel_ivybridge_info ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_D_GT2, &intel_ivybridge_info ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_S_GT1, &intel_ivybridge_info ),
+
     { 0, 0, 0 },
 };