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authorOwain G. Ainsworth <oga@openbsd.org>2011-03-16 22:35:09 +0000
committerOwain G. Ainsworth <oga@openbsd.org>2011-03-16 22:35:09 +0000
commitd71c28ef56abec2b3866b89401008934415b8381 (patch)
tree4485ceaeb7541873e64ffd2c3af29e5ca391732a
parent8e72acd1e018d9f10da6756199563a117f5cc35f (diff)
Fallback to shadow for Sandybridge if we don't have access to the BLT
If we attempt to emit BLT batches without kernel support, we just end up with EINVAL and no rendering. Prevent this, and avoid uncached rendering, by restoring the shadow fallback paths if there is no BLT support. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> (cherry picked from commit 18839aaec505f8bbdb0690fe694162bf09a87d5c) Conflicts: src/intel_driver.c
-rw-r--r--src/intel_driver.c20
1 files changed, 20 insertions, 0 deletions
diff --git a/src/intel_driver.c b/src/intel_driver.c
index 5a019333..eec1ae0d 100644
--- a/src/intel_driver.c
+++ b/src/intel_driver.c
@@ -1293,6 +1293,24 @@ static void I830XvInit(ScrnInfoPtr scrn)
intel->colorKey);
}
+static Bool can_accelerate_2d(struct intel_screen_private *intel)
+{
+ if (INTEL_INFO(intel)->gen >= 60) {
+ drm_i915_getparam_t gp;
+ int value;
+
+ /* On Sandybridge we need the BLT in order to do anything since
+ * it so frequently used in the acceleration code paths.
+ */
+ gp.value = &value;
+ gp.param = I915_PARAM_HAS_BLT;
+ if (drmIoctl(intel->drmSubFD, DRM_IOCTL_I915_GETPARAM, &gp))
+ return FALSE;
+ }
+
+ return TRUE;
+}
+
/**
* This is called before ScreenInit to do any require probing of screen
* configuration.
@@ -2205,6 +2223,8 @@ I830ScreenInit(int scrnIndex, ScreenPtr screen, int argc, char **argv)
intel->force_fallback = FALSE;
intel->use_shadow = FALSE;
+ if (!can_accelerate_2d(intel))
+ intel->use_shadow = TRUE;
/* Enable tiling by default */
intel->tiling = TRUE;