diff options
| author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2011-03-29 18:02:24 +0200 |
|---|---|---|
| committer | Owain G. Ainsworth <oga@openbsd.org> | 2011-05-29 23:31:41 +0100 |
| commit | e8739a9cc5be501d75f5218ade44793e2f71f314 (patch) | |
| tree | 1f20c2715bbffb3ef877624647b90d17724f7a92 | |
| parent | 21add004fb775bfb962fef9f9e97cb307bd2bdaf (diff) | |
Cleanup gen2 tiling confusion
A tile on gen2 has a size of 2kb, stride of 128 bytes and 16 rows.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
(cherry picked from commit f660df2cb44b310740ed850037ff37891b671f28)
Signed-off-by: Owain G. Ainsworth <oga@openbsd.org>
| -rw-r--r-- | src/intel_uxa.c | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/src/intel_uxa.c b/src/intel_uxa.c index d485e34b..7a287aa8 100644 --- a/src/intel_uxa.c +++ b/src/intel_uxa.c @@ -198,13 +198,12 @@ intel_uxa_pixmap_compute_size(PixmapPtr pixmap, if (*tiling != I915_TILING_NONE) { int aligned_h, tile_height; - if (*tiling == I915_TILING_X) + if (IS_GEN2(intel)) + tile_height = 16; + else if (*tiling == I915_TILING_X) tile_height = 8; else tile_height = 32; - /* i8xx has a 2-row interleaved tile layout */ - if (IS_GEN2(intel)) - tile_height *= 2; aligned_h = ALIGN(h, tile_height); *stride = intel_get_fence_pitch(intel, |