Store the chipset info struct in the PCI match struct, instead of a switch().

Acked-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit adf7bbd3a8758de6cdecbace42e399dd27188497)

Conflicts:

	src/intel_module.c
(merges in an earlier s/igd/pineview s/igdng/ironlake commit)

3 files changed, 152 insertions, 144 deletions

diff --git a/src/intel_batchbuffer.h b/src/intel_batchbuffer.h
index 6d119b2e..3022f254 100644
--- a/src/intel_batchbuffer.h
+++ b/src/intel_batchbuffer.h
@@ -137,8 +137,6 @@ intel_batch_mark_pixmap_domains(intel_screen_private *intel,
 
 	priv->batch_write |= write_domain != 0;
 	priv->busy = 1;
-
-	intel->needs_flush |= write_domain != 0;
 }
 
 static inline void
diff --git a/src/intel_driver.h b/src/intel_driver.h
index 3bbc0214..6aa39546 100644
--- a/src/intel_driver.h
+++ b/src/intel_driver.h
@@ -76,11 +76,11 @@
 #define PCI_CHIP_I945_GME_BRIDGE 0x27AC
 #endif
 
-#ifndef PCI_CHIP_IGD_GM
-#define PCI_CHIP_IGD_GM		0xA011
-#define PCI_CHIP_IGD_GM_BRIDGE	0xA010
-#define PCI_CHIP_IGD_G		0xA001
-#define PCI_CHIP_IGD_G_BRIDGE	0xA000
+#ifndef PCI_CHIP_PINEVIEW_M
+#define PCI_CHIP_PINEVIEW_M		0xA011
+#define PCI_CHIP_PINEVIEW_M_BRIDGE	0xA010
+#define PCI_CHIP_PINEVIEW_G		0xA001
+#define PCI_CHIP_PINEVIEW_G_BRIDGE	0xA000
 #endif
 
 #ifndef PCI_CHIP_G35_G
@@ -133,9 +133,9 @@
 #define PCI_CHIP_GM45_BRIDGE    0x2A40
 #endif
 
-#ifndef PCI_CHIP_IGD_E_G
-#define PCI_CHIP_IGD_E_G	0x2E02
-#define PCI_CHIP_IGD_E_G_BRIDGE 0x2E00
+#ifndef PCI_CHIP_G45_E_G
+#define PCI_CHIP_G45_E_G	0x2E02
+#define PCI_CHIP_G45_E_G_BRIDGE 0x2E00
 #endif
 
 #ifndef PCI_CHIP_G45_G
@@ -163,21 +163,34 @@
 #define PCI_CHIP_B43_G1_BRIDGE	0x2E90
 #endif
 
-#ifndef PCI_CHIP_IGDNG_D_G
-#define PCI_CHIP_IGDNG_D_G		0x0042
-#define PCI_CHIP_IGDNG_D_G_BRIDGE	0x0040
+#ifndef PCI_CHIP_IRONLAKE_D_G
+#define PCI_CHIP_IRONLAKE_D_G		0x0042
+#define PCI_CHIP_IRONLAKE_D_G_BRIDGE	0x0040
 #endif
 
-#ifndef PCI_CHIP_IGDNG_M_G
-#define PCI_CHIP_IGDNG_M_G		0x0046
-#define PCI_CHIP_IGDNG_M_G_BRIDGE	0x0044
+#ifndef PCI_CHIP_IRONLAKE_M_G
+#define PCI_CHIP_IRONLAKE_M_G		0x0046
+#define PCI_CHIP_IRONLAKE_M_G_BRIDGE	0x0044
 #endif
 
-#ifndef PCI_CHIP_SANDYBRIDGE
-#define PCI_CHIP_SANDYBRIDGE		0x0102
-#define PCI_CHIP_SANDYBRIDGE_BRIDGE	0x0100
-#define PCI_CHIP_SANDYBRIDGE_M		0x0106
-#define PCI_CHIP_SANDYBRIDGE_BRIDGE_M	0x0104
+#ifndef PCI_CHIP_SANDYBRIDGE_BRIDGE
+#define PCI_CHIP_SANDYBRIDGE_BRIDGE	0x0100	/* Desktop */
+#define PCI_CHIP_SANDYBRIDGE_GT1	0x0102
+#define PCI_CHIP_SANDYBRIDGE_GT2	0x0112
+#define PCI_CHIP_SANDYBRIDGE_GT2_PLUS	0x0122
+#define PCI_CHIP_SANDYBRIDGE_BRIDGE_M	0x0104	/* Mobile */
+#define PCI_CHIP_SANDYBRIDGE_M_GT1	0x0106
+#define PCI_CHIP_SANDYBRIDGE_M_GT2	0x0116
+#define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS	0x0126
+#define PCI_CHIP_SANDYBRIDGE_BRIDGE_S	0x0108	/* Server */
+#define PCI_CHIP_SANDYBRIDGE_S_GT	0x010A
+
+#define PCI_CHIP_IVYBRIDGE_M_GT1	0x0156
+#define PCI_CHIP_IVYBRIDGE_M_GT2	0x0166
+#define PCI_CHIP_IVYBRIDGE_D_GT1	0x0152
+#define PCI_CHIP_IVYBRIDGE_D_GT2	0x0162
+#define PCI_CHIP_IVYBRIDGE_S_GT1	0x015a
+
 #endif
 
 #define I85X_CAPID			0x44
@@ -216,16 +229,16 @@
 #define IS_I915GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I915_GM)
  #define IS_I945G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_G)
  #define IS_I945GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GME)
- #define IS_IGDGM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_GM)
- #define IS_IGDG(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_G)
+ #define IS_IGDGM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_PINEVIEW_M)
+ #define IS_IGDG(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_PINEVIEW_G)
  #define IS_IGD(pI810) (IS_IGDG(pI810) || IS_IGDGM(pI810))
  #define IS_GM45(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_GM45_GM)
- #define IS_G4X(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_E_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G45_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q45_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G41_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_B43_G || IS_GM45(pI810))
+ #define IS_G4X(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G45_E_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G45_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q45_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G41_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_B43_G || IS_GM45(pI810))
  #define IS_I965GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME)
 
 #define IS_965_Q(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q)
-#define IS_IGDNG_D(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGDNG_D_G)
-#define IS_IGDNG_M(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGDNG_M_G)
+#define IS_IGDNG_D(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IRONLAKE_D_G)
+#define IS_IGDNG_M(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IRONLAKE_M_G)
 #define IS_IGDNG(pI810) (IS_IGDNG_D(pI810) || IS_IGDNG_M(pI810))
 #define IS_I965G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_G || \
 			 DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G35_G || \
diff --git a/src/intel_module.c b/src/intel_module.c
index 1ae9f3c0..86cf921a 100644
--- a/src/intel_module.c
+++ b/src/intel_module.c
@@ -37,6 +37,9 @@
 #include "intel_driver.h"
 #include "legacy/legacy.h"
 
+
+static struct intel_device_info *chipset_info;
+
 static const struct intel_device_info intel_i81x_info = {
 	.gen = 10,
 };
@@ -70,85 +73,110 @@ static const struct intel_device_info intel_sandybridge_info = {
 };
 
 static const SymTabRec _intel_chipsets[] = {
-    {PCI_CHIP_I810,		"i810"},
-    {PCI_CHIP_I810_DC100,	"i810-dc100"},
-    {PCI_CHIP_I810_E,		"i810e"},
-    {PCI_CHIP_I815,		"i815"},
-    {PCI_CHIP_I830_M,		"i830M"},
-    {PCI_CHIP_845_G,		"845G"},
-    {PCI_CHIP_I854,		"854"},
-    {PCI_CHIP_I855_GM,		"852GM/855GM"},
-    {PCI_CHIP_I865_G,		"865G"},
-    {PCI_CHIP_I915_G,		"915G"},
-    {PCI_CHIP_E7221_G,		"E7221 (i915)"},
-    {PCI_CHIP_I915_GM,		"915GM"},
-    {PCI_CHIP_I945_G,		"945G"},
-    {PCI_CHIP_I945_GM,		"945GM"},
-    {PCI_CHIP_I945_GME,		"945GME"},
-    {PCI_CHIP_IGD_GM,		"Pineview GM"},
-    {PCI_CHIP_IGD_G,		"Pineview G"},
-    {PCI_CHIP_I965_G,		"965G"},
-    {PCI_CHIP_G35_G,		"G35"},
-    {PCI_CHIP_I965_Q,		"965Q"},
-    {PCI_CHIP_I946_GZ,		"946GZ"},
-    {PCI_CHIP_I965_GM,		"965GM"},
-    {PCI_CHIP_I965_GME,		"965GME/GLE"},
-    {PCI_CHIP_G33_G,		"G33"},
-    {PCI_CHIP_Q35_G,		"Q35"},
-    {PCI_CHIP_Q33_G,		"Q33"},
-    {PCI_CHIP_GM45_GM,		"GM45"},
-    {PCI_CHIP_IGD_E_G,		"4 Series"},
-    {PCI_CHIP_G45_G,		"G45/G43"},
-    {PCI_CHIP_Q45_G,		"Q45/Q43"},
-    {PCI_CHIP_G41_G,		"G41"},
-    {PCI_CHIP_B43_G,		"B43"},
-    {PCI_CHIP_B43_G1,		"B43"},
-    {PCI_CHIP_IGDNG_D_G,		"Clarkdale"},
-    {PCI_CHIP_IGDNG_M_G,		"Arrandale"},
-    {-1,				NULL}
+	{PCI_CHIP_I810,				"i810"},
+	{PCI_CHIP_I810_DC100,			"i810-dc100"},
+	{PCI_CHIP_I810_E,			"i810e"},
+	{PCI_CHIP_I815,				"i815"},
+	{PCI_CHIP_I830_M,			"i830M"},
+	{PCI_CHIP_845_G,			"845G"},
+	{PCI_CHIP_I854,				"854"},
+	{PCI_CHIP_I855_GM,			"852GM/855GM"},
+	{PCI_CHIP_I865_G,			"865G"},
+	{PCI_CHIP_I915_G,			"915G"},
+	{PCI_CHIP_E7221_G,			"E7221 (i915)"},
+	{PCI_CHIP_I915_GM,			"915GM"},
+	{PCI_CHIP_I945_G,			"945G"},
+	{PCI_CHIP_I945_GM,			"945GM"},
+	{PCI_CHIP_I945_GME,			"945GME"},
+	{PCI_CHIP_PINEVIEW_M,			"Pineview GM"},
+	{PCI_CHIP_PINEVIEW_G,			"Pineview G"},
+	{PCI_CHIP_I965_G,			"965G"},
+	{PCI_CHIP_G35_G,			"G35"},
+	{PCI_CHIP_I965_Q,			"965Q"},
+	{PCI_CHIP_I946_GZ,			"946GZ"},
+	{PCI_CHIP_I965_GM,			"965GM"},
+	{PCI_CHIP_I965_GME,			"965GME/GLE"},
+	{PCI_CHIP_G33_G,			"G33"},
+	{PCI_CHIP_Q35_G,			"Q35"},
+	{PCI_CHIP_Q33_G,			"Q33"},
+	{PCI_CHIP_GM45_GM,			"GM45"},
+	{PCI_CHIP_G45_E_G,			"4 Series"},
+	{PCI_CHIP_G45_G,			"G45/G43"},
+	{PCI_CHIP_Q45_G,			"Q45/Q43"},
+	{PCI_CHIP_G41_G,			"G41"},
+	{PCI_CHIP_B43_G,			"B43"},
+	{PCI_CHIP_B43_G1,			"B43"},
+	{PCI_CHIP_IRONLAKE_D_G,			"Clarkdale"},
+	{PCI_CHIP_IRONLAKE_M_G,			"Arrandale"},
+	{PCI_CHIP_SANDYBRIDGE_GT1,		"Sandybridge Desktop (GT1)" },
+	{PCI_CHIP_SANDYBRIDGE_GT2,		"Sandybridge Desktop (GT2)" },
+	{PCI_CHIP_SANDYBRIDGE_GT2_PLUS,		"Sandybridge Desktop (GT2+)" },
+	{PCI_CHIP_SANDYBRIDGE_M_GT1,		"Sandybridge Mobile (GT1)" },
+	{PCI_CHIP_SANDYBRIDGE_M_GT2,		"Sandybridge Mobile (GT2)" },
+	{PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS,	"Sandybridge Mobile (GT2+)" },
+	{PCI_CHIP_SANDYBRIDGE_S_GT,		"Sandybridge Server" },
+	{PCI_CHIP_IVYBRIDGE_M_GT1,		"Ivybridge Mobile (GT1)" },
+	{PCI_CHIP_IVYBRIDGE_M_GT2,		"Ivybridge Mobile (GT2)" },
+	{PCI_CHIP_IVYBRIDGE_D_GT1,		"Ivybridge Desktop (GT1)" },
+	{PCI_CHIP_IVYBRIDGE_D_GT2,		"Ivybridge Desktop (GT2)" },
+	{PCI_CHIP_IVYBRIDGE_S_GT1,		"Ivybridge Server" },
+	{-1,					NULL}
 };
 SymTabRec *intel_chipsets = (SymTabRec *) _intel_chipsets;
 
 #define INTEL_DEVICE_MATCH(d,i) \
-{ 0x8086, (d), PCI_MATCH_ANY, PCI_MATCH_ANY, 0, 0, (i) }
+    { 0x8086, (d), PCI_MATCH_ANY, PCI_MATCH_ANY, 0, 0, (intptr_t)(i) }
 
 static const struct pci_id_match intel_device_match[] = {
-    INTEL_DEVICE_MATCH (PCI_CHIP_I810, 0 ),
-    INTEL_DEVICE_MATCH (PCI_CHIP_I810_DC100, 0 ),
-    INTEL_DEVICE_MATCH (PCI_CHIP_I810_E, 0 ),
-    INTEL_DEVICE_MATCH (PCI_CHIP_I815, 0 ),
-    INTEL_DEVICE_MATCH (PCI_CHIP_I830_M, 0 ),
-    INTEL_DEVICE_MATCH (PCI_CHIP_845_G, 0 ),
-    INTEL_DEVICE_MATCH (PCI_CHIP_I854, 0 ),
-    INTEL_DEVICE_MATCH (PCI_CHIP_I855_GM, 0 ),
-    INTEL_DEVICE_MATCH (PCI_CHIP_I865_G, 0 ),
-    INTEL_DEVICE_MATCH (PCI_CHIP_I915_G, 0 ),
-    INTEL_DEVICE_MATCH (PCI_CHIP_E7221_G, 0 ),
-    INTEL_DEVICE_MATCH (PCI_CHIP_I915_GM, 0 ),
-    INTEL_DEVICE_MATCH (PCI_CHIP_I945_G, 0 ),
-    INTEL_DEVICE_MATCH (PCI_CHIP_I945_GM, 0 ),
-    INTEL_DEVICE_MATCH (PCI_CHIP_I945_GME, 0 ),
-    INTEL_DEVICE_MATCH (PCI_CHIP_IGD_GM, 0 ),
-    INTEL_DEVICE_MATCH (PCI_CHIP_IGD_G, 0 ),
-    INTEL_DEVICE_MATCH (PCI_CHIP_I965_G, 0 ),
-    INTEL_DEVICE_MATCH (PCI_CHIP_G35_G, 0 ),
-    INTEL_DEVICE_MATCH (PCI_CHIP_I965_Q, 0 ),
-    INTEL_DEVICE_MATCH (PCI_CHIP_I946_GZ, 0 ),
-    INTEL_DEVICE_MATCH (PCI_CHIP_I965_GM, 0 ),
-    INTEL_DEVICE_MATCH (PCI_CHIP_I965_GME, 0 ),
-    INTEL_DEVICE_MATCH (PCI_CHIP_G33_G, 0 ),
-    INTEL_DEVICE_MATCH (PCI_CHIP_Q35_G, 0 ),
-    INTEL_DEVICE_MATCH (PCI_CHIP_Q33_G, 0 ),
-    INTEL_DEVICE_MATCH (PCI_CHIP_GM45_GM, 0 ),
-    INTEL_DEVICE_MATCH (PCI_CHIP_IGD_E_G, 0 ),
-    INTEL_DEVICE_MATCH (PCI_CHIP_G45_G, 0 ),
-    INTEL_DEVICE_MATCH (PCI_CHIP_Q45_G, 0 ),
-    INTEL_DEVICE_MATCH (PCI_CHIP_G41_G, 0 ),
-    INTEL_DEVICE_MATCH (PCI_CHIP_B43_G, 0 ),
-    INTEL_DEVICE_MATCH (PCI_CHIP_IGDNG_D_G, 0 ),
-    INTEL_DEVICE_MATCH (PCI_CHIP_IGDNG_M_G, 0 ),
-    INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE, 0 ),
-    INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M, 0 ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_I810, &intel_i81x_info ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_I810_DC100, &intel_i81x_info ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_I810_E, &intel_i81x_info ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_I815, &intel_i81x_info ),
+
+    INTEL_DEVICE_MATCH (PCI_CHIP_I830_M, &intel_i8xx_info ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_845_G, &intel_i8xx_info ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_I854, &intel_i8xx_info ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_I855_GM, &intel_i8xx_info ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_I865_G, &intel_i8xx_info ),
+
+    INTEL_DEVICE_MATCH (PCI_CHIP_I915_G, &intel_i915_info ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_E7221_G, &intel_i915_info ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_I915_GM, &intel_i915_info ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_I945_G, &intel_i915_info ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_I945_GM, &intel_i915_info ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_I945_GME, &intel_i915_info ),
+
+    INTEL_DEVICE_MATCH (PCI_CHIP_G33_G, &intel_g33_info ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_PINEVIEW_M, &intel_g33_info ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_PINEVIEW_G, &intel_g33_info ),
+
+    INTEL_DEVICE_MATCH (PCI_CHIP_I965_G, &intel_i965_info ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_G35_G, &intel_i965_info ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_I965_Q, &intel_i965_info ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_I946_GZ, &intel_i965_info ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_I965_GM, &intel_i965_info ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_I965_GME, &intel_i965_info ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_Q35_G, &intel_i965_info ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_Q33_G, &intel_i965_info ),
+
+    INTEL_DEVICE_MATCH (PCI_CHIP_GM45_GM, &intel_g4x_info ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_G45_E_G, &intel_g4x_info ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_G45_G, &intel_g4x_info ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_Q45_G, &intel_g4x_info ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_G41_G, &intel_g4x_info ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_B43_G, &intel_g4x_info ),
+
+    INTEL_DEVICE_MATCH (PCI_CHIP_IRONLAKE_D_G, &intel_ironlake_info ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_IRONLAKE_M_G, &intel_ironlake_info ),
+
+    INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT1, &intel_sandybridge_info ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT2, &intel_sandybridge_info ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT2_PLUS, &intel_sandybridge_info ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT1, &intel_sandybridge_info ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT2, &intel_sandybridge_info ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS, &intel_sandybridge_info ),
+    INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_S_GT, &intel_sandybridge_info ),
+
     { 0, 0, 0 },
 };
 
@@ -168,8 +196,8 @@ static PciChipsets intel_pci_chipsets[] = {
     {PCI_CHIP_I945_G,		PCI_CHIP_I945_G,	NULL},
     {PCI_CHIP_I945_GM,		PCI_CHIP_I945_GM,	NULL},
     {PCI_CHIP_I945_GME,		PCI_CHIP_I945_GME,	NULL},
-    {PCI_CHIP_IGD_GM,		PCI_CHIP_IGD_GM,	NULL},
-    {PCI_CHIP_IGD_G,		PCI_CHIP_IGD_G,		NULL},
+    {PCI_CHIP_PINEVIEW_M,	PCI_CHIP_PINEVIEW_M,	NULL},
+    {PCI_CHIP_PINEVIEW_G,	PCI_CHIP_PINEVIEW_G,	NULL},
     {PCI_CHIP_I965_G,		PCI_CHIP_I965_G,	NULL},
     {PCI_CHIP_G35_G,		PCI_CHIP_G35_G,		NULL},
     {PCI_CHIP_I965_Q,		PCI_CHIP_I965_Q,	NULL},
@@ -180,13 +208,13 @@ static PciChipsets intel_pci_chipsets[] = {
     {PCI_CHIP_Q35_G,		PCI_CHIP_Q35_G,		NULL},
     {PCI_CHIP_Q33_G,		PCI_CHIP_Q33_G,		NULL},
     {PCI_CHIP_GM45_GM,		PCI_CHIP_GM45_GM,	NULL},
-    {PCI_CHIP_IGD_E_G,		PCI_CHIP_IGD_E_G,	NULL},
+    {PCI_CHIP_G45_E_G,		PCI_CHIP_G45_E_G,	NULL},
     {PCI_CHIP_G45_G,		PCI_CHIP_G45_G,		NULL},
     {PCI_CHIP_Q45_G,		PCI_CHIP_Q45_G,		NULL},
     {PCI_CHIP_G41_G,		PCI_CHIP_G41_G,		NULL},
     {PCI_CHIP_B43_G,		PCI_CHIP_B43_G,		NULL},
-    {PCI_CHIP_IGDNG_D_G,		PCI_CHIP_IGDNG_D_G,	NULL},
-    {PCI_CHIP_IGDNG_M_G,		PCI_CHIP_IGDNG_M_G,	NULL},
+    {PCI_CHIP_IRONLAKE_D_G,		PCI_CHIP_IRONLAKE_D_G,	NULL},
+    {PCI_CHIP_IRONLAKE_M_G,		PCI_CHIP_IRONLAKE_M_G,	NULL},
     {-1,				-1, NULL }
 };
 
@@ -196,34 +224,29 @@ void intel_detect_chipset(ScrnInfoPtr scrn,
 {
     uint32_t capid;
 
+    chipset->info = chipset_info;
+
     switch (DEVICE_ID(pci)) {
     case PCI_CHIP_I810:
 	chipset->name = "i810";
-	chipset->info = &intel_i81x_info;
 	break;
     case PCI_CHIP_I810_DC100:
 	chipset->name = "i810-dc100";
-	chipset->info = &intel_i81x_info;
 	break;
     case PCI_CHIP_I810_E:
 	chipset->name = "i810e";
-	chipset->info = &intel_i81x_info;
 	break;
     case PCI_CHIP_I815:
 	chipset->name = "i815";
-	chipset->info = &intel_i81x_info;
 	break;
     case PCI_CHIP_I830_M:
 	chipset->name = "830M";
-	chipset->info = &intel_i8xx_info;
 	break;
     case PCI_CHIP_845_G:
 	chipset->name = "845G";
-	chipset->info = &intel_i8xx_info;
 	break;
     case PCI_CHIP_I854:
 	chipset->name = "854";
-	chipset->info = &intel_i8xx_info;
 	break;
     case PCI_CHIP_I855_GM:
 	/* Check capid register to find the chipset variant */
@@ -250,111 +273,84 @@ void intel_detect_chipset(ScrnInfoPtr scrn,
 	    chipset->name = "852GM/855GM (unknown variant)";
 	    break;
 	}
-	chipset->info = &intel_i8xx_info;
 	break;
     case PCI_CHIP_I865_G:
 	chipset->name = "865G";
-	chipset->info = &intel_i8xx_info;
 	break;
     case PCI_CHIP_I915_G:
 	chipset->name = "915G";
-	chipset->info = &intel_i915_info;
 	break;
     case PCI_CHIP_E7221_G:
 	chipset->name = "E7221 (i915)";
-	chipset->info = &intel_i915_info;
 	break;
     case PCI_CHIP_I915_GM:
 	chipset->name = "915GM";
-	chipset->info = &intel_i915_info;
 	break;
     case PCI_CHIP_I945_G:
 	chipset->name = "945G";
-	chipset->info = &intel_i915_info;
 	break;
     case PCI_CHIP_I945_GM:
 	chipset->name = "945GM";
-	chipset->info = &intel_i915_info;
 	break;
     case PCI_CHIP_I945_GME:
 	chipset->name = "945GME";
-	chipset->info = &intel_i915_info;
 	break;
-    case PCI_CHIP_IGD_GM:
+    case PCI_CHIP_PINEVIEW_M:
 	chipset->name = "Pineview GM";
-	chipset->info = &intel_g33_info;
 	break;
-    case PCI_CHIP_IGD_G:
+    case PCI_CHIP_PINEVIEW_G:
 	chipset->name = "Pineview G";
-	chipset->info = &intel_g33_info;
 	break;
     case PCI_CHIP_I965_G:
 	chipset->name = "965G";
-	chipset->info = &intel_i965_info;
 	break;
     case PCI_CHIP_G35_G:
 	chipset->name = "G35";
-	chipset->info = &intel_i965_info;
 	break;
     case PCI_CHIP_I965_Q:
 	chipset->name = "965Q";
-	chipset->info = &intel_i965_info;
 	break;
     case PCI_CHIP_I946_GZ:
 	chipset->name = "946GZ";
-	chipset->info = &intel_i965_info;
 	break;
     case PCI_CHIP_I965_GM:
 	chipset->name = "965GM";
-	chipset->info = &intel_i965_info;
 	break;
     case PCI_CHIP_I965_GME:
 	chipset->name = "965GME/GLE";
-	chipset->info = &intel_i965_info;
 	break;
     case PCI_CHIP_G33_G:
 	chipset->name = "G33";
-	chipset->info = &intel_g33_info;
 	break;
     case PCI_CHIP_Q35_G:
 	chipset->name = "Q35";
-	chipset->info = &intel_g33_info;
 	break;
     case PCI_CHIP_Q33_G:
 	chipset->name = "Q33";
-	chipset->info = &intel_g33_info;
 	break;
     case PCI_CHIP_GM45_GM:
 	chipset->name = "GM45";
-	chipset->info = &intel_g4x_info;
 	break;
-    case PCI_CHIP_IGD_E_G:
+    case PCI_CHIP_G45_E_G:
 	chipset->name = "4 Series";
-	chipset->info = &intel_g4x_info;
 	break;
     case PCI_CHIP_G45_G:
 	chipset->name = "G45/G43";
-	chipset->info = &intel_g4x_info;
 	break;
     case PCI_CHIP_Q45_G:
 	chipset->name = "Q45/Q43";
-	chipset->info = &intel_g4x_info;
 	break;
     case PCI_CHIP_G41_G:
 	chipset->name = "G41";
-	chipset->info = &intel_g4x_info;
 	break;
     case PCI_CHIP_B43_G:
 	chipset->name = "B43";
-	chipset->info = &intel_g4x_info;
 	break;
-    case PCI_CHIP_IGDNG_D_G:
+    case PCI_CHIP_IRONLAKE_D_G:
 	chipset->name = "Clarkdale";
-	chipset->info = &intel_ironlake_info;
 	break;
-    case PCI_CHIP_IGDNG_M_G:
+    case PCI_CHIP_IRONLAKE_M_G:
 	chipset->name = "Arrandale";
-	chipset->info = &intel_ironlake_info;
 	break;
 #if 0
     case PCI_CHIP_SANDYBRIDGE_GT1:
@@ -365,7 +361,6 @@ void intel_detect_chipset(ScrnInfoPtr scrn,
     case PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS:
     case PCI_CHIP_SANDYBRIDGE_S_GT:
 	chipset->name = "Sandybridge";
-	chipset->info = &intel_sandybridge_info;
 	break;
 #endif
     default:
@@ -425,6 +420,8 @@ static Bool intel_pci_probe (DriverPtr		driver,
 {
     ScrnInfoPtr scrn = NULL;
 
+    chipset_info = (void *)match_data;
+
     scrn = xf86ConfigPciEntity(scrn, 0, entity_num, intel_pci_chipsets,
 			       NULL,
 			       NULL, NULL, NULL, NULL);