diff options
| author | Kenneth Graunke <kenneth@whitecape.org> | 2011-07-14 00:30:09 -0700 |
|---|---|---|
| committer | Kenneth Graunke <kenneth@whitecape.org> | 2011-07-28 15:01:07 -0700 |
| commit | 0d92612b2a2782f80196a08eb9a17af906169f18 (patch) | |
| tree | c2cde728c379790c066c77e95ade146f0bc1dc18 | |
| parent | 7460ee73d1fd22e6b02ce125f11ac38efff743ce (diff) | |
render: Update pixel shader state for Ivybridge.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Eric Anholt <eric@anholt.net>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
| -rw-r--r-- | src/i965_render.c | 38 |
1 files changed, 35 insertions, 3 deletions
diff --git a/src/i965_render.c b/src/i965_render.c index 5222d1c5..596d0707 100644 --- a/src/i965_render.c +++ b/src/i965_render.c @@ -2657,6 +2657,37 @@ gen6_composite_wm_state(intel_screen_private *intel, } static void +gen7_composite_wm_state(intel_screen_private *intel, + Bool has_mask, + drm_intel_bo *bo) +{ + int num_surfaces = has_mask ? 3 : 2; + + if (intel->gen6_render_state.kernel == bo) + return; + + intel->gen6_render_state.kernel = bo; + + OUT_BATCH(GEN6_3DSTATE_WM | (3 - 2)); + OUT_BATCH(GEN7_WM_DISPATCH_ENABLE | + GEN7_WM_PERSPECTIVE_PIXEL_BARYCENTRIC); + OUT_BATCH(0); + + OUT_BATCH(GEN7_3DSTATE_PS | (8 - 2)); + OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); + OUT_BATCH((1 << GEN7_PS_SAMPLER_COUNT_SHIFT) | + (num_surfaces << GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT)); + OUT_BATCH(0); /* scratch space base offset */ + OUT_BATCH(((86 - 1) << GEN7_PS_MAX_THREADS_SHIFT) | + GEN7_PS_ATTRIBUTE_ENABLE | + GEN7_PS_16_DISPATCH_ENABLE); + OUT_BATCH((6 << GEN7_PS_DISPATCH_START_GRF_SHIFT_0)); + OUT_BATCH(0); /* kernel 1 pointer */ + OUT_BATCH(0); /* kernel 2 pointer */ +} + + +static void gen6_composite_drawing_rectangle(intel_screen_private *intel, PixmapPtr dest) { @@ -2809,12 +2840,13 @@ gen6_emit_composite_state(struct intel_screen_private *intel) (src * BRW_BLENDFACTOR_COUNT + dst) * GEN6_BLEND_STATE_PADDED_SIZE); gen6_composite_sampler_state_pointers(intel, ps_sampler_state_bo); gen6_composite_sf_state(intel, has_mask); - gen6_composite_wm_state(intel, - has_mask, - render->wm_kernel_bo[composite_op->wm_kernel]); if (ivb) { + gen7_composite_wm_state(intel, has_mask, + render->wm_kernel_bo[composite_op->wm_kernel]); gen7_upload_binding_table(intel, intel->surface_table); } else { + gen6_composite_wm_state(intel, has_mask, + render->wm_kernel_bo[composite_op->wm_kernel]); gen6_upload_binding_table(intel, intel->surface_table); } gen6_composite_drawing_rectangle(intel, intel->render_dest); |