diff options
author | Keith Packard <keithp@keithp.com> | 2008-04-08 16:08:20 -0500 |
---|---|---|
committer | Keith Packard <keithp@keithp.com> | 2008-04-10 16:58:11 -0500 |
commit | 781be9d47289713b0a8fcd95c769a9c6241d62e9 (patch) | |
tree | 55e6b22121acfec9e62919c25f950b2fa0d98099 | |
parent | 2871ac8eefd0192080bb0569140c3f5d0e1d9b44 (diff) |
Rename src/mask/data registers to indicate channel
-rw-r--r-- | src/exa_wm.g4i | 50 | ||||
-rw-r--r-- | src/exa_wm_ca.g4a | 8 | ||||
-rw-r--r-- | src/exa_wm_ca_srcalpha.g4a | 8 | ||||
-rw-r--r-- | src/exa_wm_mask_sample_a.g4a | 2 | ||||
-rw-r--r-- | src/exa_wm_mask_sample_argb.g4a | 2 | ||||
-rw-r--r-- | src/exa_wm_noca.g4a | 8 | ||||
-rw-r--r-- | src/exa_wm_src_sample_a.g4a | 2 | ||||
-rw-r--r-- | src/exa_wm_src_sample_argb.g4a | 2 | ||||
-rw-r--r-- | src/exa_wm_write.g4a | 54 |
9 files changed, 76 insertions, 60 deletions
diff --git a/src/exa_wm.g4i b/src/exa_wm.g4i index 10e630e1..ee8e3ad0 100644 --- a/src/exa_wm.g4i +++ b/src/exa_wm.g4i @@ -102,21 +102,39 @@ define(`mask_w_0', `src_w_0') define(`mask_w_1', `src_w_1') /* sample src to these registers */ -define(`src_sample0', `g14') -define(`src_sample1', `g15') -define(`src_sample2', `g16') -define(`src_sample3', `g17') -define(`src_sample4', `g18') -define(`src_sample5', `g19') -define(`src_sample6', `g20') -define(`src_sample7', `g21') +define(`src_sample_base', `g14') +define(`src_sample_r_01', `g14') +define(`src_sample_r_23', `g15') +define(`src_sample_g_01', `g16') +define(`src_sample_g_23', `g17') +define(`src_sample_b_01', `g18') +define(`src_sample_b_23', `g19') +define(`src_sample_a_01', `g20') +define(`src_sample_a_23', `g21') /* sample mask to these registers */ -define(`mask_sample0', `g22') -define(`mask_sample1', `g23') -define(`mask_sample2', `g24') -define(`mask_sample3', `g25') -define(`mask_sample4', `g26') -define(`mask_sample5', `g27') -define(`mask_sample6', `g28') -define(`mask_sample7', `g29') +define(`mask_sample_base', `g22') +define(`mask_sample_r_01', `g22') +define(`mask_sample_r_23', `g23') +define(`mask_sample_g_01', `g24') +define(`mask_sample_g_23', `g25') +define(`mask_sample_b_01', `g26') +define(`mask_sample_b_23', `g27') +define(`mask_sample_a_01', `g28') +define(`mask_sample_a_23', `g29') + +/* data port SIMD16 send registers */ + +define(`data_port_msg_0', `m0') +define(`data_port_msg_0_ind', `0') +define(`data_port_msg_1', `m1') +define(`data_port_r_01', `m2') +define(`data_port_g_01', `m3') +define(`data_port_b_01', `m4') +define(`data_port_a_01', `m5') + +define(`data_port_r_23', `m6') +define(`data_port_g_23', `m7') +define(`data_port_b_23', `m8') +define(`data_port_a_23', `m9') + diff --git a/src/exa_wm_ca.g4a b/src/exa_wm_ca.g4a index 955c68c2..5d982b38 100644 --- a/src/exa_wm_ca.g4a +++ b/src/exa_wm_ca.g4a @@ -32,7 +32,7 @@ include(`exa_wm.g4i') /* mul mask rgba channels to src */ -mul (16) src_sample0<1>F src_sample0<8,8,1>F mask_sample0<8,8,1>F { compr align1 }; -mul (16) src_sample2<1>F src_sample2<8,8,1>F mask_sample2<8,8,1>F { compr align1 }; -mul (16) src_sample4<1>F src_sample4<8,8,1>F mask_sample4<8,8,1>F { compr align1 }; -mul (16) src_sample6<1>F src_sample6<8,8,1>F mask_sample6<8,8,1>F { compr align1 }; +mul (16) src_sample_r_01<1>F src_sample_r_01<8,8,1>F mask_sample_r_01<8,8,1>F { compr align1 }; +mul (16) src_sample_g_01<1>F src_sample_g_01<8,8,1>F mask_sample_g_01<8,8,1>F { compr align1 }; +mul (16) src_sample_b_01<1>F src_sample_b_01<8,8,1>F mask_sample_b_01<8,8,1>F { compr align1 }; +mul (16) src_sample_a_01<1>F src_sample_a_01<8,8,1>F mask_sample_a_01<8,8,1>F { compr align1 }; diff --git a/src/exa_wm_ca_srcalpha.g4a b/src/exa_wm_ca_srcalpha.g4a index e252e19b..d1f847fd 100644 --- a/src/exa_wm_ca_srcalpha.g4a +++ b/src/exa_wm_ca_srcalpha.g4a @@ -31,7 +31,7 @@ include(`exa_wm.g4i') -mul (16) src_sample0<1>F mask_sample0<8,8,1>F src_sample6<8,8,1>F { compr align1 }; -mul (16) src_sample2<1>F mask_sample2<8,8,1>F src_sample6<8,8,1>F { compr align1 }; -mul (16) src_sample4<1>F mask_sample4<8,8,1>F src_sample6<8,8,1>F { compr align1 }; -mul (16) src_sample6<1>F mask_sample6<8,8,1>F src_sample6<8,8,1>F { compr align1 }; +mul (16) src_sample_r_01<1>F mask_sample_r_01<8,8,1>F src_sample_a_01<8,8,1>F { compr align1 }; +mul (16) src_sample_g_01<1>F mask_sample_g_01<8,8,1>F src_sample_a_01<8,8,1>F { compr align1 }; +mul (16) src_sample_b_01<1>F mask_sample_b_01<8,8,1>F src_sample_a_01<8,8,1>F { compr align1 }; +mul (16) src_sample_a_01<1>F mask_sample_a_01<8,8,1>F src_sample_a_01<8,8,1>F { compr align1 }; diff --git a/src/exa_wm_mask_sample_a.g4a b/src/exa_wm_mask_sample_a.g4a index c06611d5..bbb19d7a 100644 --- a/src/exa_wm_mask_sample_a.g4a +++ b/src/exa_wm_mask_sample_a.g4a @@ -40,7 +40,7 @@ mov (1) g0.8<1>UD 0x00007000UD { align1 mask_disable }; /* mask_msg will be copied with g0, as it contains send desc */ /* emit sampler 'send' cmd */ send (16) mask_msg_ind /* msg reg index */ - mask_sample6<1>UW /* readback */ + mask_sample_a_01<1>UW /* readback */ g0<8,8,1>UW /* copy to msg start reg*/ sampler (2,1,F) /* sampler message description, (binding_table,sampler_index,datatype) /* here(src->dst) we should use src_sampler and src_surface */ diff --git a/src/exa_wm_mask_sample_argb.g4a b/src/exa_wm_mask_sample_argb.g4a index 7f0815f2..def4cfe4 100644 --- a/src/exa_wm_mask_sample_argb.g4a +++ b/src/exa_wm_mask_sample_argb.g4a @@ -40,7 +40,7 @@ mov (1) g0.8<1>UD 0x00000000UD { align1 mask_disable }; /* mask_msg will be copied with g0, as it contains send desc */ /* emit sampler 'send' cmd */ send (16) mask_msg_ind /* msg reg index */ - mask_sample0<1>UW /* readback */ + mask_sample_base<1>UW /* readback */ g0<8,8,1>UW /* copy to msg start reg*/ sampler (2,1,F) /* sampler message description, (binding_table,sampler_index,datatype) /* here(src->dst) we should use src_sampler and src_surface */ diff --git a/src/exa_wm_noca.g4a b/src/exa_wm_noca.g4a index 7dd12247..d0d60faa 100644 --- a/src/exa_wm_noca.g4a +++ b/src/exa_wm_noca.g4a @@ -32,7 +32,7 @@ include(`exa_wm.g4i') /* mul mask's alpha channel to src */ -mul (16) src_sample0<1>F src_sample0<8,8,1>F mask_sample6<8,8,1>F { compr align1 }; -mul (16) src_sample2<1>F src_sample2<8,8,1>F mask_sample6<8,8,1>F { compr align1 }; -mul (16) src_sample4<1>F src_sample4<8,8,1>F mask_sample6<8,8,1>F { compr align1 }; -mul (16) src_sample6<1>F src_sample6<8,8,1>F mask_sample6<8,8,1>F { compr align1 }; +mul (16) src_sample_r_01<1>F src_sample_r_01<8,8,1>F mask_sample_a_01<8,8,1>F { compr align1 }; +mul (16) src_sample_g_01<1>F src_sample_g_01<8,8,1>F mask_sample_a_01<8,8,1>F { compr align1 }; +mul (16) src_sample_b_01<1>F src_sample_b_01<8,8,1>F mask_sample_a_01<8,8,1>F { compr align1 }; +mul (16) src_sample_a_01<1>F src_sample_a_01<8,8,1>F mask_sample_a_01<8,8,1>F { compr align1 }; diff --git a/src/exa_wm_src_sample_a.g4a b/src/exa_wm_src_sample_a.g4a index 803c358a..552aaeeb 100644 --- a/src/exa_wm_src_sample_a.g4a +++ b/src/exa_wm_src_sample_a.g4a @@ -40,7 +40,7 @@ mov (1) g0.8<1>UD 0x00007000UD { align1 mask_disable }; /* src_msg will be copied with g0, as it contains send desc */ /* emit sampler 'send' cmd */ send (16) src_msg_ind /* msg reg index */ - src_sample6<1>UW /* readback */ + src_sample_a_01<1>UW /* readback */ g0<8,8,1>UW /* copy to msg start reg*/ sampler (1,0,F) /* sampler message description, (binding_table,sampler_index,datatype) /* here(src->dst) we should use src_sampler and src_surface */ diff --git a/src/exa_wm_src_sample_argb.g4a b/src/exa_wm_src_sample_argb.g4a index 4fcf276c..c20f53f2 100644 --- a/src/exa_wm_src_sample_argb.g4a +++ b/src/exa_wm_src_sample_argb.g4a @@ -40,7 +40,7 @@ mov (1) g0.8<1>UD 0x00000000UD { align1 mask_disable }; /* src_msg will be copied with g0, as it contains send desc */ /* emit sampler 'send' cmd */ send (16) src_msg_ind /* msg reg index */ - src_sample0<1>UW /* readback */ + src_sample_base<1>UW /* readback */ g0<8,8,1>UW /* copy to msg start reg*/ sampler (1,0,F) /* sampler message description, (binding_table,sampler_index,datatype) /* here(src->dst) we should use src_sampler and src_surface */ diff --git a/src/exa_wm_write.g4a b/src/exa_wm_write.g4a index 5d3e6b1e..b16e6497 100644 --- a/src/exa_wm_write.g4a +++ b/src/exa_wm_write.g4a @@ -25,41 +25,39 @@ * Keith Packard <keithp@keithp.com> */ -/* - * Once the data are ready, write them to the destination - */ - include(`exa_wm.g4i') -/* prepare data in m2-m5 for subspan(1,0), m6-m9 for subspan(3,2), then it's ready to write */ -/* src_sample0 -> m2 - src_sample1 -> m6 - src_sample2 -> m3 - src_sample3 -> m7 - src_sample4 -> m4 - src_sample5 -> m8 - src_sample6 -> m5 - src_sample7 -> m9 -*/ +/* + * Prepare data in m2-m5 for subspan(1,0), m6-m9 for subspan(3,2), + * + * Note that the SIMD16 write message takes data for the first + * two sub-spans followed by the data for the second two sub-spans + * instead of having the two sub-spans interleaved by channel. Weird. + */ + +mov (8) data_port_r_01<1>F src_sample_r_01<8,8,1>F { align1 }; +mov (8) data_port_g_01<1>F src_sample_g_01<8,8,1>F { align1 }; +mov (8) data_port_b_01<1>F src_sample_b_01<8,8,1>F { align1 }; +mov (8) data_port_a_01<1>F src_sample_a_01<8,8,1>F { align1 }; -mov (8) m2<1>F src_sample0<8,8,1>F { align1 }; -mov (8) m3<1>F src_sample2<8,8,1>F { align1 }; -mov (8) m4<1>F src_sample4<8,8,1>F { align1 }; -mov (8) m5<1>F src_sample6<8,8,1>F { align1 }; -mov (8) m6<1>F src_sample1<8,8,1>F { align1 }; -mov (8) m7<1>F src_sample3<8,8,1>F { align1 }; -mov (8) m8<1>F src_sample5<8,8,1>F { align1 }; -mov (8) m9<1>F src_sample7<8,8,1>F { align1 }; +mov (8) data_port_r_23<1>F src_sample_r_23<8,8,1>F { align1 }; +mov (8) data_port_g_23<1>F src_sample_g_23<8,8,1>F { align1 }; +mov (8) data_port_b_23<1>F src_sample_b_23<8,8,1>F { align1 }; +mov (8) data_port_a_23<1>F src_sample_a_23<8,8,1>F { align1 }; /* m0, m1 are all direct passed by PS thread payload */ -mov (8) m1<1>UD g1<8,8,1>UD { align1 }; +mov (8) data_port_msg_1<1>UD g1<8,8,1>UD { align1 }; /* write */ -send (16) 0 acc0<1>UW g0<8,8,1>UW write ( - 0, /* binding_table */ - 8, /* pixel scordboard clear, msg type simd16 single source */ - 4, /* render target write */ - 0 /* no write commit message */ +send (16) + data_port_msg_0_ind + acc0<1>UW + g0<8,8,1>UW + write ( + 0, /* binding_table */ + 8, /* pixel scordboard clear, msg type simd16 single source */ + 4, /* render target write */ + 0 /* no write commit message */ ) mlen 10 rlen 0 |