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authorZhenyu Wang <zhenyu.z.wang@intel.com>2008-09-18 10:42:33 +0800
committerZhenyu Wang <zhenyu.z.wang@intel.com>2008-09-18 10:42:33 +0800
commitbc36608e321e01a2be792688b4b734bb7c0667f7 (patch)
tree8443619ea185e8fb15e1e302593b78f54ae7b6bc
parent62b75df84c893bf28e20014cf88ce45064611dc9 (diff)
Check display stride limit when allocate front buffer
-rw-r--r--src/i830_memory.c29
1 files changed, 29 insertions, 0 deletions
diff --git a/src/i830_memory.c b/src/i830_memory.c
index 2cbdd17a..ecfdf2a2 100644
--- a/src/i830_memory.c
+++ b/src/i830_memory.c
@@ -158,6 +158,29 @@ i830_get_fence_size(ScrnInfoPtr pScrn, unsigned long size)
}
static Bool
+i830_check_display_stride(ScrnInfoPtr pScrn, int stride, Bool tiling)
+{
+ I830Ptr pI830 = I830PTR(pScrn);
+ int limit = KB(32);
+
+ /* 8xx spec has always 8K limit, but tests show larger limit in
+ non-tiling mode, which makes large monitor work. */
+ if ((IS_845G(pI830) || IS_I85X(pI830)) && tiling)
+ limit = KB(8);
+
+ if (IS_I915(pI830) && tiling)
+ limit = KB(8);
+
+ if (IS_I965G(pI830) && tiling)
+ limit = KB(16);
+
+ if (stride <= limit)
+ return TRUE;
+ else
+ return FALSE;
+}
+
+static Bool
i830_bind_memory(ScrnInfoPtr pScrn, i830_memory *mem)
{
I830Ptr pI830 = I830PTR(pScrn);
@@ -1200,6 +1223,12 @@ i830_allocate_framebuffer(ScrnInfoPtr pScrn, I830Ptr pI830, BoxPtr FbMemBox,
else
tiling = pI830->tiling;
+ if (!i830_check_display_stride(pScrn, pitch, tiling)) {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Front buffer stride %d kB "
+ "exceed display limit\n", pitch/1024);
+ return NULL;
+ }
+
/* Attempt to allocate it tiled first if we have page flipping on. */
if (tiling && IsTileable(pScrn, pitch)) {
/* XXX: probably not the case on 965 */