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authorEric Anholt <eric@anholt.net>2006-11-10 14:40:40 -0800
committerEric Anholt <eric@anholt.net>2006-11-10 14:40:44 -0800
commitd51555fba4e57c059fd184c1e54822d7e5b62a2f (patch)
tree4bd100ec097549a5d0de15133f36c8e8a9026634
parentdd1dcfab0ab0f2d0c25077fa663209e2762f26e8 (diff)
Fix clock range for single-channel LVDS.
-rw-r--r--src/i830_display.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/i830_display.c b/src/i830_display.c
index 36036603..f661c4ed 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -189,7 +189,10 @@ i830FindBestPLL(ScrnInfoPtr pScrn, int pipe, int target, int refclk,
min_p1 = 1;
max_p1 = 8;
if (i830PipeHasType (pScrn, pipe, I830_OUTPUT_LVDS)) {
- if (target < 200000) /* XXX: Is this the right cutoff? */
+ /* The single-channel range is 25-112Mhz, and dual-channel
+ * is 80-224Mhz. Prefer single channel as much as possible.
+ */
+ if (target < 112000)
p2 = 14;
else
p2 = 7;