diff options
| author | Chris Wilson <chris@chris-wilson.co.uk> | 2013-07-26 10:07:23 +0100 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2013-07-28 14:49:07 +0100 |
| commit | e94f66c951ae9e0d4304cf8005537a147bda5d79 (patch) | |
| tree | 182721d9d3eed7f31a9840e04ba6d2f273e71be8 | |
| parent | 04d5c33b9677fc920ad58522f93d832a42de4744 (diff) | |
intel: Move some backend specific macros out of the common header
All the IS_GEN/IS_DEVICE are only used by the UXA backend, so move them
to its headers.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| -rw-r--r-- | src/intel_driver.h | 25 | ||||
| -rw-r--r-- | src/sna/sna_video_hwmc.c | 2 | ||||
| -rw-r--r-- | src/uxa/intel.h | 25 |
3 files changed, 26 insertions, 26 deletions
diff --git a/src/intel_driver.h b/src/intel_driver.h index 22b623ff..7660f006 100644 --- a/src/intel_driver.h +++ b/src/intel_driver.h @@ -278,31 +278,6 @@ #define SUBSYS_ID(p) (p)->subdevice_id #define CHIP_REVISION(p) (p)->revision -#define INTEL_INFO(intel) ((intel)->info) -#define IS_GENx(intel, X) (INTEL_INFO(intel)->gen >= 8*(X) && INTEL_INFO(intel)->gen < 8*((X)+1)) -#define IS_GEN1(intel) IS_GENx(intel, 1) -#define IS_GEN2(intel) IS_GENx(intel, 2) -#define IS_GEN3(intel) IS_GENx(intel, 3) -#define IS_GEN4(intel) IS_GENx(intel, 4) -#define IS_GEN5(intel) IS_GENx(intel, 5) -#define IS_GEN6(intel) IS_GENx(intel, 6) -#define IS_GEN7(intel) IS_GENx(intel, 7) -#define IS_HSW(intel) (INTEL_INFO(intel)->gen == 075) - -/* Some chips have specific errata (or limits) that we need to workaround. */ -#define IS_I830(intel) (DEVICE_ID((intel)->PciInfo) == PCI_CHIP_I830_M) -#define IS_845G(intel) (DEVICE_ID((intel)->PciInfo) == PCI_CHIP_845_G) -#define IS_I865G(intel) (DEVICE_ID((intel)->PciInfo) == PCI_CHIP_I865_G) - -#define IS_I915G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I915_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_E7221_G) -#define IS_I915GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I915_GM) - -#define IS_965_Q(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q) - -/* supports Y tiled surfaces (pre-965 Mesa isn't ready yet) */ -#define SUPPORTS_YTILING(pI810) (INTEL_INFO(intel)->gen >= 040) -#define HAS_BLT(pI810) (INTEL_INFO(intel)->gen >= 060) - struct intel_device_info { int gen; }; diff --git a/src/sna/sna_video_hwmc.c b/src/sna/sna_video_hwmc.c index 15a7844a..52f1560b 100644 --- a/src/sna/sna_video_hwmc.c +++ b/src/sna/sna_video_hwmc.c @@ -86,7 +86,7 @@ static int create_context(XvPortPtr port, XvMCContextPtr ctx, else priv->type = XVMC_I965_MPEG2_MC; priv->i965.is_g4x = sna->kgem.gen == 045; - priv->i965.is_965_q = IS_965_Q(sna); + priv->i965.is_965_q = DEVICE_ID(sna->PciInfo) == PCI_CHIP_I965_Q; priv->i965.is_igdng = sna->kgem.gen == 050; } else priv->type = XVMC_I915_MPEG2_MC; diff --git a/src/uxa/intel.h b/src/uxa/intel.h index d4c9aff2..2b1ff5e2 100644 --- a/src/uxa/intel.h +++ b/src/uxa/intel.h @@ -352,6 +352,31 @@ typedef struct intel_screen_private { Bool has_prime_vmap_flush; } intel_screen_private; +#define INTEL_INFO(intel) ((intel)->info) +#define IS_GENx(intel, X) (INTEL_INFO(intel)->gen >= 8*(X) && INTEL_INFO(intel)->gen < 8*((X)+1)) +#define IS_GEN1(intel) IS_GENx(intel, 1) +#define IS_GEN2(intel) IS_GENx(intel, 2) +#define IS_GEN3(intel) IS_GENx(intel, 3) +#define IS_GEN4(intel) IS_GENx(intel, 4) +#define IS_GEN5(intel) IS_GENx(intel, 5) +#define IS_GEN6(intel) IS_GENx(intel, 6) +#define IS_GEN7(intel) IS_GENx(intel, 7) +#define IS_HSW(intel) (INTEL_INFO(intel)->gen == 075) + +/* Some chips have specific errata (or limits) that we need to workaround. */ +#define IS_I830(intel) (DEVICE_ID((intel)->PciInfo) == PCI_CHIP_I830_M) +#define IS_845G(intel) (DEVICE_ID((intel)->PciInfo) == PCI_CHIP_845_G) +#define IS_I865G(intel) (DEVICE_ID((intel)->PciInfo) == PCI_CHIP_I865_G) + +#define IS_I915G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I915_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_E7221_G) +#define IS_I915GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I915_GM) + +#define IS_965_Q(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q) + +/* supports Y tiled surfaces (pre-965 Mesa isn't ready yet) */ +#define SUPPORTS_YTILING(pI810) (INTEL_INFO(intel)->gen >= 040) +#define HAS_BLT(pI810) (INTEL_INFO(intel)->gen >= 060) + #ifndef I915_PARAM_HAS_PRIME_VMAP_FLUSH #define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 #endif |