i810: Move into a legacy directory.

The driver is still built but is no longer under active development so
move it and supporting files to a new directory.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
(cherry picked from commit 797d173a9af12055ba2609293182b616dd673ef4)

    Conflicts:

    	configure.ac
    	src/Makefile.am
    	src/common.h
    	src/i830.h
    	src/i830_accel.c
    	src/i830_batchbuffer.c
    	src/i830_driver.c
    	src/legacy/i810/i810_driver.c

OGA: had to make abunch of changes due to ums still existing, but this
was more sensible that having to modify every single cherry-picked patch
from now on.

1 files changed, 0 insertions, 241 deletions

diff --git a/src/common.h b/src/common.h
index bc08f1c9..05de264b 100644
--- a/src/common.h
+++ b/src/common.h
@@ -122,38 +122,16 @@ static inline void memcpy_volatile(volatile void *dst, const void *src,
 
 #define OUTREG8(addr, val) do {						\
    *(volatile uint8_t *)(RecPtr->MMIOBase  + (addr)) = (val);		\
-   if (I810_DEBUG&DEBUG_VERBOSE_OUTREG) {				\
-      ErrorF("OUTREG8(0x%lx, 0x%lx) in %s\n", (unsigned long)(addr),	\
-		(unsigned long)(val), FUNCTION_NAME);			\
-   }									\
 } while (0)
 
 #define OUTREG16(addr, val) do {					\
    *(volatile uint16_t *)(RecPtr->MMIOBase + (addr)) = (val);		\
-   if (I810_DEBUG&DEBUG_VERBOSE_OUTREG) {				\
-      ErrorF("OUTREG16(0x%lx, 0x%lx) in %s\n", (unsigned long)(addr),	\
-		(unsigned long)(val), FUNCTION_NAME);			\
-   }									\
 } while (0)
 
 #define OUTREG(addr, val) do {						\
    *(volatile uint32_t *)(RecPtr->MMIOBase + (addr)) = (val);		\
-   if (I810_DEBUG&DEBUG_VERBOSE_OUTREG) {				\
-      ErrorF("OUTREG(0x%lx, 0x%lx) in %s\n", (unsigned long)(addr),	\
-		(unsigned long)(val), FUNCTION_NAME);			\
-   }									\
 } while (0)
 
-/* To remove all debugging, make sure I810_DEBUG is defined as a
- * preprocessor symbol, and equal to zero.
- */
-#if 1
-#define I810_DEBUG 0
-#endif
-#ifndef I810_DEBUG
-#warning "Debugging enabled - expect reduced performance"
-extern int I810_DEBUG;
-#endif
 
 #define DEBUG_VERBOSE_ACCEL  0x1
 #define DEBUG_VERBOSE_SYNC   0x2
@@ -171,225 +149,6 @@ extern int I810_DEBUG;
  */
 #define I810_REG_SIZE 0x80000
 
-#ifndef PCI_CHIP_I810
-#define PCI_CHIP_I810              0x7121
-#define PCI_CHIP_I810_DC100        0x7123
-#define PCI_CHIP_I810_E            0x7125
-#define PCI_CHIP_I815              0x1132
-#define PCI_CHIP_I810_BRIDGE       0x7120
-#define PCI_CHIP_I810_DC100_BRIDGE 0x7122
-#define PCI_CHIP_I810_E_BRIDGE     0x7124
-#define PCI_CHIP_I815_BRIDGE       0x1130
-#endif
-
-#ifndef PCI_CHIP_I830_M
-#define PCI_CHIP_I830_M            0x3577
-#define PCI_CHIP_I830_M_BRIDGE     0x3575
-#endif
-
-#ifndef PCI_CHIP_845_G
-#define PCI_CHIP_845_G		   0x2562
-#define PCI_CHIP_845_G_BRIDGE	   0x2560
-#endif
-
-#ifndef PCI_CHIP_I854
-#define PCI_CHIP_I854		   0x358E
-#define PCI_CHIP_I854_BRIDGE	   0x358C
-#endif
-
-#ifndef PCI_CHIP_I855_GM
-#define PCI_CHIP_I855_GM	   0x3582
-#define PCI_CHIP_I855_GM_BRIDGE	   0x3580
-#endif
-
-#ifndef PCI_CHIP_I865_G
-#define PCI_CHIP_I865_G		   0x2572
-#define PCI_CHIP_I865_G_BRIDGE	   0x2570
-#endif
-
-#ifndef PCI_CHIP_I915_G
-#define PCI_CHIP_I915_G		   0x2582
-#define PCI_CHIP_I915_G_BRIDGE	   0x2580
-#endif
-
-#ifndef PCI_CHIP_I915_GM
-#define PCI_CHIP_I915_GM	   0x2592
-#define PCI_CHIP_I915_GM_BRIDGE	   0x2590
-#endif
-
-#ifndef PCI_CHIP_E7221_G
-#define PCI_CHIP_E7221_G	   0x258A
-/* Same as I915_G_BRIDGE */
-#define PCI_CHIP_E7221_G_BRIDGE	   0x2580
-#endif
-
-#ifndef PCI_CHIP_I945_G
-#define PCI_CHIP_I945_G        0x2772
-#define PCI_CHIP_I945_G_BRIDGE 0x2770
-#endif
-
-#ifndef PCI_CHIP_I945_GM
-#define PCI_CHIP_I945_GM        0x27A2
-#define PCI_CHIP_I945_GM_BRIDGE 0x27A0
-#endif
-
-#ifndef PCI_CHIP_I945_GME
-#define PCI_CHIP_I945_GME	 0x27AE
-#define PCI_CHIP_I945_GME_BRIDGE 0x27AC
-#endif
-
-#ifndef PCI_CHIP_IGD_GM
-#define PCI_CHIP_IGD_GM		0xA011
-#define PCI_CHIP_IGD_GM_BRIDGE	0xA010
-#define PCI_CHIP_IGD_G		0xA001
-#define PCI_CHIP_IGD_G_BRIDGE	0xA000
-#endif
-
-#ifndef PCI_CHIP_G35_G
-#define PCI_CHIP_G35_G		0x2982
-#define PCI_CHIP_G35_G_BRIDGE 	0x2980
-#endif
-
-#ifndef PCI_CHIP_I965_Q
-#define PCI_CHIP_I965_Q		0x2992
-#define PCI_CHIP_I965_Q_BRIDGE 	0x2990
-#endif
-
-#ifndef PCI_CHIP_I965_G
-#define PCI_CHIP_I965_G		0x29A2
-#define PCI_CHIP_I965_G_BRIDGE 	0x29A0
-#endif
-
-#ifndef PCI_CHIP_I946_GZ
-#define PCI_CHIP_I946_GZ		0x2972
-#define PCI_CHIP_I946_GZ_BRIDGE 	0x2970
-#endif
-
-#ifndef PCI_CHIP_I965_GM
-#define PCI_CHIP_I965_GM        0x2A02
-#define PCI_CHIP_I965_GM_BRIDGE 0x2A00
-#endif
-
-#ifndef PCI_CHIP_I965_GME
-#define PCI_CHIP_I965_GME       0x2A12
-#define PCI_CHIP_I965_GME_BRIDGE 0x2A10
-#endif
-
-#ifndef PCI_CHIP_G33_G
-#define PCI_CHIP_G33_G		0x29C2
-#define PCI_CHIP_G33_G_BRIDGE 	0x29C0
-#endif
-
-#ifndef PCI_CHIP_Q35_G
-#define PCI_CHIP_Q35_G		0x29B2
-#define PCI_CHIP_Q35_G_BRIDGE 	0x29B0
-#endif
-
-#ifndef PCI_CHIP_Q33_G
-#define PCI_CHIP_Q33_G		0x29D2
-#define PCI_CHIP_Q33_G_BRIDGE 	0x29D0
-#endif
-
-#ifndef PCI_CHIP_GM45_GM
-#define PCI_CHIP_GM45_GM	0x2A42
-#define PCI_CHIP_GM45_BRIDGE    0x2A40
-#endif
-
-#ifndef PCI_CHIP_IGD_E_G
-#define PCI_CHIP_IGD_E_G	0x2E02
-#define PCI_CHIP_IGD_E_G_BRIDGE 0x2E00
-#endif
-
-#ifndef PCI_CHIP_G45_G
-#define PCI_CHIP_G45_G		0x2E22
-#define PCI_CHIP_G45_G_BRIDGE	0x2E20
-#endif
-
-#ifndef PCI_CHIP_Q45_G
-#define PCI_CHIP_Q45_G		0x2E12
-#define PCI_CHIP_Q45_G_BRIDGE	0x2E10
-#endif
-
-#ifndef PCI_CHIP_G41_G
-#define PCI_CHIP_G41_G		0x2E32
-#define PCI_CHIP_G41_G_BRIDGE	0x2E30
-#endif
-
-#ifndef PCI_CHIP_B43_G
-#define PCI_CHIP_B43_G		0x2E42
-#define PCI_CHIP_B43_G_BRIDGE	0x2E40
-#endif
-
-#ifndef PCI_CHIP_IGDNG_D_G
-#define PCI_CHIP_IGDNG_D_G		0x0042
-#define PCI_CHIP_IGDNG_D_G_BRIDGE	0x0040
-#endif
-
-#ifndef PCI_CHIP_IGDNG_M_G
-#define PCI_CHIP_IGDNG_M_G		0x0046
-#define PCI_CHIP_IGDNG_M_G_BRIDGE	0x0044
-#endif
-
-#define I810_MEMBASE(p,n) (p)->regions[(n)].base_addr
-#define VENDOR_ID(p)      (p)->vendor_id
-#define DEVICE_ID(p)      (p)->device_id
-#define SUBVENDOR_ID(p)	  (p)->subvendor_id
-#define SUBSYS_ID(p)      (p)->subdevice_id
-#define CHIP_REVISION(p)  (p)->revision
-
-#define IS_I810(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I810 ||	\
-			DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I810_DC100 || \
-			DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I810_E)
-#define IS_I815(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I815)
-#define IS_I830(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I830_M)
-#define IS_845G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_845_G)
-#define IS_I85X(pI810)  (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I855_GM || \
-			 DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I854)
-#define IS_I852(pI810)  (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I855_GM && (pI810->variant == I852_GM || pI810->variant == I852_GME))
-#define IS_I854(pI810)  (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I854)
-#define IS_I855(pI810)  (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I855_GM && (pI810->variant == I855_GM || pI810->variant == I855_GME))
-#define IS_I865G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I865_G)
-#define IS_I8XX(pI810)	(IS_I830(pI810) || IS_845G(pI810) || IS_I85X(pI810) || IS_I865G(pI810))
-
-#define IS_I915G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I915_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_E7221_G)
-#define IS_I915GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I915_GM)
-#define IS_I945G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_G)
-#define IS_I945GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GME)
-#define IS_IGDGM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_GM)
-#define IS_IGDG(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_G)
-#define IS_IGD(pI810) (IS_IGDG(pI810) || IS_IGDGM(pI810))
-#define IS_GM45(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_GM45_GM)
-#define IS_G4X(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_E_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G45_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q45_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G41_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_B43_G || IS_GM45(pI810))
-#define IS_I965GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME)
-#define IS_965_Q(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q)
-#define IS_IGDNG_D(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGDNG_D_G)
-#define IS_IGDNG_M(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGDNG_M_G)
-#define IS_IGDNG(pI810) (IS_IGDNG_D(pI810) || IS_IGDNG_M(pI810))
-#define IS_I965G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G35_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I946_GZ || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME || IS_G4X(pI810) || IS_IGDNG(pI810))
-#define IS_G33CLASS(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G33_G ||\
- 			    DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q35_G ||\
-			    DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q33_G || \
-			    IS_IGD(pI810))
-#define IS_I9XX(pI810) (IS_I915G(pI810) || IS_I915GM(pI810) || IS_I945G(pI810) || IS_I945GM(pI810) || IS_I965G(pI810) || IS_G33CLASS(pI810))
-#define IS_I915(pI810) (IS_I915G(pI810) || IS_I915GM(pI810) || IS_I945G(pI810) || IS_I945GM(pI810) || IS_G33CLASS(pI810))
-
-#define IS_MOBILE(pI810) (IS_I830(pI810) || IS_I85X(pI810) || IS_I915GM(pI810) || IS_I945GM(pI810) || IS_I965GM(pI810) || IS_GM45(pI810) || IS_IGD(pI810) || IS_IGDNG_M(pI810))
-/* mark chipsets for using gfx VM offset for overlay */
-#define OVERLAY_NOPHYSICAL(pI810) (IS_G33CLASS(pI810) || IS_I965G(pI810))
-/* mark chipsets without overlay hw */
-#define OVERLAY_NOEXIST(pI810) (IS_G4X(pI810) || IS_IGDNG(pI810))
-/* chipsets require graphics mem for hardware status page */
-#define HWS_NEED_GFX(pI810) (!pI810->use_drm_mode && \
-			     (IS_G33CLASS(pI810) ||\
-			      IS_G4X(pI810) || IS_IGDNG(pI810)))
-/* chipsets require status page in non stolen memory */
-#define HWS_NEED_NONSTOLEN(pI810) (IS_G4X(pI810) || IS_IGDNG(pI810))
-#define SUPPORTS_INTEGRATED_HDMI(pI810) (IS_G4X(pI810) || IS_IGDNG(pI810))
-/* dsparb controlled by hw only */
-#define DSPARB_HWCONTROL(pI810) (IS_G4X(pI810) || IS_IGDNG(pI810))
-/* supports Y tiled surfaces (pre-965 Mesa isn't ready yet) */
-#define SUPPORTS_YTILING(pI810) (IS_I965G(intel))
-
 #define GTT_PAGE_SIZE			KB(4)
 #define ROUND_TO(x, y)			(((x) + (y) - 1) / (y) * (y))
 #define ROUND_DOWN_TO(x, y)		((x) / (y) * (y))