diff options
| author | Shaohua Li <shaohua.li@intel.com> | 2009-02-23 15:19:23 +0800 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2009-02-26 14:47:04 -0800 |
| commit | f53bdad1412f841075232455837578f00709c6ef (patch) | |
| tree | f76737dc8668778b537a04c72f513ee451dc6015 /src/common.h | |
| parent | 22dc9a5580d77cc4707bfb8e19474e611a06ae9a (diff) | |
Intel video driver patch
This is the intel video driver patch for a new chip, which is G33-like
and has some clocking setting related register changes. This patch adds
the pci id and DPLx/FPx register changes.
The gtt tool should just work to me, as the chip hasn't any changes
against G33 on this side.
Signed-off-by: Shaohua Li <shaohua.li@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'src/common.h')
| -rw-r--r-- | src/common.h | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/src/common.h b/src/common.h index be222df5..8b32a66e 100644 --- a/src/common.h +++ b/src/common.h @@ -241,6 +241,13 @@ extern int I810_DEBUG; #define PCI_CHIP_I945_GME_BRIDGE 0x27AC #endif +#ifndef PCI_CHIP_IGD_GM +#define PCI_CHIP_IGD_GM 0xA011 +#define PCI_CHIP_IGD_GM_BRIDGE 0xA010 +#define PCI_CHIP_IGD_G 0xA001 +#define PCI_CHIP_IGD_G_BRIDGE 0xA000 +#endif + #ifndef PCI_CHIP_G35_G #define PCI_CHIP_G35_G 0x2982 #define PCI_CHIP_G35_G_BRIDGE 0x2980 @@ -342,6 +349,9 @@ extern int I810_DEBUG; #define IS_I915GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I915_GM) #define IS_I945G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_G) #define IS_I945GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GME) +#define IS_IGDGM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_GM) +#define IS_IGDG(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_G) +#define IS_IGD(pI810) (IS_IGDG(pI810) || IS_IGDGM(pI810)) #define IS_GM45(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_GM45_GM) #define IS_G4X(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_E_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G45_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q45_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G41_G || IS_GM45(pI810)) #define IS_I965GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME) @@ -349,11 +359,12 @@ extern int I810_DEBUG; #define IS_I965G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G35_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I946_GZ || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME || IS_G4X(pI810)) #define IS_G33CLASS(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G33_G ||\ DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q35_G ||\ - DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q33_G) + DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q33_G || \ + IS_IGD(pI810)) #define IS_I9XX(pI810) (IS_I915G(pI810) || IS_I915GM(pI810) || IS_I945G(pI810) || IS_I945GM(pI810) || IS_I965G(pI810) || IS_G33CLASS(pI810)) #define IS_I915(pI810) (IS_I915G(pI810) || IS_I915GM(pI810) || IS_I945G(pI810) || IS_I945GM(pI810) || IS_G33CLASS(pI810)) -#define IS_MOBILE(pI810) (IS_I830(pI810) || IS_I85X(pI810) || IS_I915GM(pI810) || IS_I945GM(pI810) || IS_I965GM(pI810) || IS_GM45(pI810)) +#define IS_MOBILE(pI810) (IS_I830(pI810) || IS_I85X(pI810) || IS_I915GM(pI810) || IS_I945GM(pI810) || IS_I965GM(pI810) || IS_GM45(pI810) || IS_IGD(pI810)) /* mark chipsets for using gfx VM offset for overlay */ #define OVERLAY_NOPHYSICAL(pI810) (IS_G33CLASS(pI810) || IS_I965G(pI810)) /* mark chipsets without overlay hw */ |