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authorZhenyu Wang <zhenyu.z.wang@intel.com>2008-06-17 12:39:28 -0700
committerEric Anholt <eric@anholt.net>2008-06-17 12:39:28 -0700
commit1cfe769c74d1a3a392bf1aaaf5c2dcc8273daf66 (patch)
tree5feb1735ce740b8d8160a509f60fb455e1625de4 /src/i810_driver.c
parent289790c0467d27e96b537598a6589fc6a36da8b8 (diff)
Add support for Intel 4 series chipsets.
Diffstat (limited to 'src/i810_driver.c')
-rw-r--r--src/i810_driver.c12
1 files changed, 12 insertions, 0 deletions
diff --git a/src/i810_driver.c b/src/i810_driver.c
index 4b716608..de4f3cb5 100644
--- a/src/i810_driver.c
+++ b/src/i810_driver.c
@@ -153,6 +153,9 @@ static const struct pci_id_match intel_device_match[] = {
INTEL_DEVICE_MATCH (PCI_CHIP_Q35_G, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_Q33_G, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_IGD_GM, 0 ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_IGD_E_G, 0 ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_G45_G, 0 ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_Q45_G, 0 ),
{ 0, 0, 0 },
};
@@ -206,6 +209,9 @@ static SymTabRec I810Chipsets[] = {
{PCI_CHIP_Q35_G, "Q35"},
{PCI_CHIP_Q33_G, "Q33"},
{PCI_CHIP_IGD_GM, "Intel Integrated Graphics Device"},
+ {PCI_CHIP_IGD_E_G, "Intel Integrated Graphics Device"},
+ {PCI_CHIP_G45_G, "G45/G43"},
+ {PCI_CHIP_Q45_G, "Q45/Q43"},
{-1, NULL}
};
@@ -236,6 +242,9 @@ static PciChipsets I810PciChipsets[] = {
{PCI_CHIP_Q35_G, PCI_CHIP_Q35_G, RES_SHARED_VGA},
{PCI_CHIP_Q33_G, PCI_CHIP_Q33_G, RES_SHARED_VGA},
{PCI_CHIP_IGD_GM, PCI_CHIP_IGD_GM, RES_SHARED_VGA},
+ {PCI_CHIP_IGD_E_G, PCI_CHIP_IGD_E_G, RES_SHARED_VGA},
+ {PCI_CHIP_G45_G, PCI_CHIP_G45_G, RES_SHARED_VGA},
+ {PCI_CHIP_Q45_G, PCI_CHIP_Q45_G, RES_SHARED_VGA},
{-1, -1, RES_UNDEFINED }
};
@@ -800,6 +809,9 @@ I810Probe(DriverPtr drv, int flags)
case PCI_CHIP_Q35_G:
case PCI_CHIP_Q33_G:
case PCI_CHIP_IGD_GM:
+ case PCI_CHIP_IGD_E_G:
+ case PCI_CHIP_G45_G:
+ case PCI_CHIP_Q45_G:
xf86SetEntitySharable(usedChips[i]);
/* Allocate an entity private if necessary */