diff options
| author | Wang Zhenyu <zhenyu.z.wang@intel.com> | 2007-06-05 11:07:41 -0700 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2007-06-05 11:34:22 -0700 |
| commit | f4c05973d391bdb0a9b0eadb155548310baa98fd (patch) | |
| tree | 0e1f21768e1dfffdb0f06349780870c8df8ab563 /src/i810_driver.c | |
| parent | 36fcaeb2ef94db5399071540bba106dec3db81d5 (diff) | |
Add support for the G33, Q33, and Q35 chipsets.
These chipsets require that the hardware status page be referenced by an offset
in the GTT rather than a physical memory address, so the X Server allocates it
rather than the DRM.
Diffstat (limited to 'src/i810_driver.c')
| -rw-r--r-- | src/i810_driver.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/i810_driver.c b/src/i810_driver.c index 5b04a476..972b6d50 100644 --- a/src/i810_driver.c +++ b/src/i810_driver.c @@ -147,6 +147,9 @@ static SymTabRec I810Chipsets[] = { {PCI_CHIP_I946_GZ, "946GZ"}, {PCI_CHIP_I965_GM, "965GM"}, {PCI_CHIP_I965_GME, "965GME/GLE"}, + {PCI_CHIP_G33_G, "G33"}, + {PCI_CHIP_Q35_G, "Q35"}, + {PCI_CHIP_Q33_G, "Q33"}, {-1, NULL} }; @@ -173,6 +176,9 @@ static PciChipsets I810PciChipsets[] = { {PCI_CHIP_I946_GZ, PCI_CHIP_I946_GZ, RES_SHARED_VGA}, {PCI_CHIP_I965_GM, PCI_CHIP_I965_GM, RES_SHARED_VGA}, {PCI_CHIP_I965_GME, PCI_CHIP_I965_GME, RES_SHARED_VGA}, + {PCI_CHIP_G33_G, PCI_CHIP_G33_G, RES_SHARED_VGA}, + {PCI_CHIP_Q35_G, PCI_CHIP_Q35_G, RES_SHARED_VGA}, + {PCI_CHIP_Q33_G, PCI_CHIP_Q33_G, RES_SHARED_VGA}, {-1, -1, RES_UNDEFINED } }; @@ -620,6 +626,9 @@ I810Probe(DriverPtr drv, int flags) case PCI_CHIP_I946_GZ: case PCI_CHIP_I965_GM: case PCI_CHIP_I965_GME: + case PCI_CHIP_G33_G: + case PCI_CHIP_Q35_G: + case PCI_CHIP_Q33_G: xf86SetEntitySharable(usedChips[i]); /* Allocate an entity private if necessary */ |