diff options
| author | Kristian Høgsberg <krh@redhat.com> | 2009-02-02 11:51:47 -0500 |
|---|---|---|
| committer | Kristian Høgsberg <krh@redhat.com> | 2009-02-02 11:51:50 -0500 |
| commit | 2013799b20599a58de48cb21a5a389e898a58af1 (patch) | |
| tree | 0ddde73476d9228191785db8471e5a6967b18bb6 /src/i830_dri.c | |
| parent | 127330bfd53ac7571bdd12a551142528b972893f (diff) | |
Un-revert the I915_SETPARAM_NUM_USED_FENCES commit reverted by accident.
Oops, my bad. Reverted 8d4bc36fae50b09a73ba2cfab920adb32141a358
since my kernel doesn't yet have the new param, committed
the revert by accident.
Diffstat (limited to 'src/i830_dri.c')
| -rw-r--r-- | src/i830_dri.c | 13 |
1 files changed, 4 insertions, 9 deletions
diff --git a/src/i830_dri.c b/src/i830_dri.c index ec83abdb..f03be43c 100644 --- a/src/i830_dri.c +++ b/src/i830_dri.c @@ -1570,7 +1570,7 @@ I830DRI2CreateBuffers(DrawablePtr pDraw, unsigned int *attachments, int count) pDraw->depth, 0); switch (attachments[i]) { case DRI2BufferDepth: - if (IS_I965G(pI830)) + if (SUPPORTS_YTILING(pI830)) tiling = I915_TILING_Y; else tiling = I915_TILING_X; @@ -1583,19 +1583,14 @@ I830DRI2CreateBuffers(DrawablePtr pDraw, unsigned int *attachments, int count) break; } - /* Disable tiling on 915-class 3D for now. Because the 2D blitter - * requires fence regs to operate, and they're not being managed - * by the kernel yet, we don't want to expose tiled buffers to the - * 3D client as it'll just render incorrectly if it pays attention - * to our tiling bits at all. - */ - if (!IS_I965G(pI830)) + if (!pI830->tiling || + (!IS_I965G(pI830) && !pI830->kernel_exec_fencing)) tiling = I915_TILING_NONE; if (tiling != I915_TILING_NONE) { bo = i830_get_pixmap_bo(pPixmap); drm_intel_bo_set_tiling(bo, &tiling, - pDraw->width * pDraw->bitsPerPixel / 8); + intel_get_pixmap_pitch(pPixmap)); } } |